Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.85 99.02 92.26 96.79 94.08 98.62 99.77 97.45


Total test records in report: 727
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T551 /workspace/coverage/default/41.edn_stress_all.3902552852 Oct 11 12:52:37 PM PDT 23 Oct 11 12:52:39 PM PDT 23 68750241 ps
T552 /workspace/coverage/default/35.edn_stress_all_with_rand_reset.1921862698 Oct 11 12:52:48 PM PDT 23 Oct 11 12:59:39 PM PDT 23 18595923389 ps
T553 /workspace/coverage/default/42.edn_disable_auto_req_mode.1165380963 Oct 11 12:52:40 PM PDT 23 Oct 11 12:52:41 PM PDT 23 62813376 ps
T554 /workspace/coverage/default/13.edn_disable.2636424786 Oct 11 12:52:05 PM PDT 23 Oct 11 12:52:06 PM PDT 23 24159587 ps
T181 /workspace/coverage/default/33.edn_err.594606011 Oct 11 12:52:24 PM PDT 23 Oct 11 12:52:26 PM PDT 23 31090166 ps
T555 /workspace/coverage/default/20.edn_smoke.761994191 Oct 11 12:52:48 PM PDT 23 Oct 11 12:52:50 PM PDT 23 15252077 ps
T280 /workspace/coverage/default/22.edn_genbits.781637120 Oct 11 12:52:52 PM PDT 23 Oct 11 12:52:53 PM PDT 23 53429978 ps
T129 /workspace/coverage/default/12.edn_disable.1782259542 Oct 11 12:53:06 PM PDT 23 Oct 11 12:53:07 PM PDT 23 21137734 ps
T556 /workspace/coverage/default/48.edn_disable_auto_req_mode.929588307 Oct 11 12:52:34 PM PDT 23 Oct 11 12:52:35 PM PDT 23 35986295 ps
T297 /workspace/coverage/default/9.edn_regwen.1080659308 Oct 11 12:52:06 PM PDT 23 Oct 11 12:52:08 PM PDT 23 53168634 ps
T557 /workspace/coverage/default/46.edn_smoke.3103553041 Oct 11 12:53:00 PM PDT 23 Oct 11 12:53:02 PM PDT 23 38065681 ps
T558 /workspace/coverage/default/35.edn_intr.1584594772 Oct 11 12:53:22 PM PDT 23 Oct 11 12:53:23 PM PDT 23 24088804 ps
T559 /workspace/coverage/default/6.edn_alert.772686976 Oct 11 12:52:51 PM PDT 23 Oct 11 12:52:52 PM PDT 23 22012365 ps
T560 /workspace/coverage/default/20.edn_stress_all.1322289155 Oct 11 12:51:48 PM PDT 23 Oct 11 12:51:52 PM PDT 23 152402130 ps
T561 /workspace/coverage/default/13.edn_stress_all.1674393723 Oct 11 12:52:00 PM PDT 23 Oct 11 12:52:01 PM PDT 23 40396536 ps
T562 /workspace/coverage/default/25.edn_stress_all_with_rand_reset.2973382677 Oct 11 12:53:11 PM PDT 23 Oct 11 01:10:11 PM PDT 23 236908616047 ps
T302 /workspace/coverage/default/13.edn_alert.1522175600 Oct 11 12:51:53 PM PDT 23 Oct 11 12:51:54 PM PDT 23 55306976 ps
T563 /workspace/coverage/default/38.edn_stress_all.3638375210 Oct 11 12:52:47 PM PDT 23 Oct 11 12:52:51 PM PDT 23 155454958 ps
T301 /workspace/coverage/default/8.edn_alert.3144974691 Oct 11 12:51:28 PM PDT 23 Oct 11 12:51:29 PM PDT 23 18320353 ps
T564 /workspace/coverage/default/44.edn_intr.1852443936 Oct 11 12:53:07 PM PDT 23 Oct 11 12:53:09 PM PDT 23 24340243 ps
T281 /workspace/coverage/default/39.edn_genbits.1016615450 Oct 11 12:52:49 PM PDT 23 Oct 11 12:52:51 PM PDT 23 81181829 ps
T565 /workspace/coverage/default/14.edn_stress_all.1915930411 Oct 11 12:52:23 PM PDT 23 Oct 11 12:52:26 PM PDT 23 1214492427 ps
T566 /workspace/coverage/default/49.edn_err.676739317 Oct 11 12:53:06 PM PDT 23 Oct 11 12:53:07 PM PDT 23 19599242 ps
T567 /workspace/coverage/default/56.edn_err.4177826477 Oct 11 12:53:10 PM PDT 23 Oct 11 12:53:11 PM PDT 23 25172177 ps
T568 /workspace/coverage/default/33.edn_alert_test.3041417222 Oct 11 12:52:16 PM PDT 23 Oct 11 12:52:18 PM PDT 23 196249508 ps
T286 /workspace/coverage/default/48.edn_genbits.2692315975 Oct 11 12:53:01 PM PDT 23 Oct 11 12:53:03 PM PDT 23 48646157 ps
T307 /workspace/coverage/default/48.edn_alert.2300111133 Oct 11 12:52:49 PM PDT 23 Oct 11 12:52:50 PM PDT 23 27438604 ps
T569 /workspace/coverage/default/19.edn_smoke.581381805 Oct 11 12:52:46 PM PDT 23 Oct 11 12:52:48 PM PDT 23 16407098 ps
T570 /workspace/coverage/default/22.edn_stress_all.1312791523 Oct 11 12:52:47 PM PDT 23 Oct 11 12:52:51 PM PDT 23 651104907 ps
T571 /workspace/coverage/default/26.edn_err.3013439076 Oct 11 12:52:33 PM PDT 23 Oct 11 12:52:35 PM PDT 23 18526545 ps
T572 /workspace/coverage/default/26.edn_alert_test.3541094310 Oct 11 12:52:20 PM PDT 23 Oct 11 12:52:22 PM PDT 23 25117816 ps
T573 /workspace/coverage/default/12.edn_stress_all.506337300 Oct 11 12:52:46 PM PDT 23 Oct 11 12:52:48 PM PDT 23 30296491 ps
T574 /workspace/coverage/default/16.edn_alert_test.3712742351 Oct 11 12:51:36 PM PDT 23 Oct 11 12:51:38 PM PDT 23 95004942 ps
T166 /workspace/coverage/default/44.edn_err.1871242635 Oct 11 12:53:08 PM PDT 23 Oct 11 12:53:09 PM PDT 23 25408313 ps
T575 /workspace/coverage/default/23.edn_stress_all_with_rand_reset.1130185711 Oct 11 12:52:45 PM PDT 23 Oct 11 01:11:57 PM PDT 23 174174862125 ps
T576 /workspace/coverage/default/36.edn_alert_test.354972915 Oct 11 12:52:44 PM PDT 23 Oct 11 12:52:46 PM PDT 23 14192718 ps
T577 /workspace/coverage/default/13.edn_alert_test.1831379291 Oct 11 12:52:27 PM PDT 23 Oct 11 12:52:28 PM PDT 23 56278361 ps
T578 /workspace/coverage/default/11.edn_stress_all.3515330832 Oct 11 12:53:01 PM PDT 23 Oct 11 12:53:04 PM PDT 23 82694675 ps
T579 /workspace/coverage/default/37.edn_err.180295535 Oct 11 12:52:37 PM PDT 23 Oct 11 12:52:39 PM PDT 23 18581117 ps
T196 /workspace/coverage/default/91.edn_err.3437877937 Oct 11 12:54:53 PM PDT 23 Oct 11 12:54:54 PM PDT 23 40901016 ps
T580 /workspace/coverage/default/48.edn_smoke.3316609290 Oct 11 12:53:30 PM PDT 23 Oct 11 12:53:31 PM PDT 23 15575236 ps
T169 /workspace/coverage/default/58.edn_err.2090449449 Oct 11 12:53:24 PM PDT 23 Oct 11 12:53:25 PM PDT 23 32002372 ps
T581 /workspace/coverage/default/20.edn_alert_test.3191622791 Oct 11 12:51:42 PM PDT 23 Oct 11 12:51:44 PM PDT 23 13190198 ps
T582 /workspace/coverage/default/34.edn_stress_all_with_rand_reset.559041713 Oct 11 12:52:48 PM PDT 23 Oct 11 01:13:09 PM PDT 23 49323517667 ps
T583 /workspace/coverage/default/30.edn_disable.3250992544 Oct 11 12:52:56 PM PDT 23 Oct 11 12:52:58 PM PDT 23 12969663 ps
T172 /workspace/coverage/default/87.edn_err.4241937366 Oct 11 12:53:19 PM PDT 23 Oct 11 12:53:21 PM PDT 23 55964297 ps
T584 /workspace/coverage/default/19.edn_disable.2447392874 Oct 11 12:51:52 PM PDT 23 Oct 11 12:51:53 PM PDT 23 20161860 ps
T248 /workspace/coverage/default/17.edn_disable_auto_req_mode.1515251158 Oct 11 12:52:33 PM PDT 23 Oct 11 12:52:35 PM PDT 23 98946626 ps
T585 /workspace/coverage/default/48.edn_intr.1290869452 Oct 11 12:52:57 PM PDT 23 Oct 11 12:53:04 PM PDT 23 31708889 ps
T586 /workspace/coverage/default/34.edn_alert_test.4269099177 Oct 11 12:52:36 PM PDT 23 Oct 11 12:52:37 PM PDT 23 44560883 ps
T587 /workspace/coverage/default/6.edn_regwen.4112564692 Oct 11 12:53:12 PM PDT 23 Oct 11 12:53:15 PM PDT 23 15267888 ps
T588 /workspace/coverage/default/48.edn_stress_all.3446823662 Oct 11 12:52:56 PM PDT 23 Oct 11 12:52:59 PM PDT 23 231956961 ps
T589 /workspace/coverage/default/13.edn_smoke.1064094943 Oct 11 12:51:42 PM PDT 23 Oct 11 12:51:44 PM PDT 23 60007315 ps
T590 /workspace/coverage/default/0.edn_smoke.2134652336 Oct 11 12:51:02 PM PDT 23 Oct 11 12:51:04 PM PDT 23 27009360 ps
T591 /workspace/coverage/default/44.edn_genbits.3716833537 Oct 11 12:52:50 PM PDT 23 Oct 11 12:52:52 PM PDT 23 107998001 ps
T592 /workspace/coverage/default/26.edn_alert.3856299654 Oct 11 12:53:04 PM PDT 23 Oct 11 12:53:05 PM PDT 23 36680417 ps
T593 /workspace/coverage/default/27.edn_genbits.2250569677 Oct 11 12:52:40 PM PDT 23 Oct 11 12:52:41 PM PDT 23 165136184 ps
T594 /workspace/coverage/default/30.edn_disable_auto_req_mode.2282973259 Oct 11 12:52:45 PM PDT 23 Oct 11 12:52:47 PM PDT 23 89680368 ps
T595 /workspace/coverage/default/39.edn_smoke.4060992720 Oct 11 12:54:02 PM PDT 23 Oct 11 12:54:03 PM PDT 23 33777817 ps
T596 /workspace/coverage/default/2.edn_alert.1727288056 Oct 11 12:52:32 PM PDT 23 Oct 11 12:52:34 PM PDT 23 81093978 ps
T597 /workspace/coverage/default/34.edn_intr.4203140638 Oct 11 12:52:16 PM PDT 23 Oct 11 12:52:17 PM PDT 23 23754045 ps
T284 /workspace/coverage/default/49.edn_genbits.2230979483 Oct 11 12:52:27 PM PDT 23 Oct 11 12:52:29 PM PDT 23 17336168 ps
T173 /workspace/coverage/default/72.edn_err.3125678837 Oct 11 12:53:30 PM PDT 23 Oct 11 12:53:32 PM PDT 23 33184925 ps
T184 /workspace/coverage/default/84.edn_err.840057632 Oct 11 12:52:49 PM PDT 23 Oct 11 12:52:51 PM PDT 23 68485066 ps
T598 /workspace/coverage/default/36.edn_smoke.1623215100 Oct 11 12:54:00 PM PDT 23 Oct 11 12:54:01 PM PDT 23 20408908 ps
T599 /workspace/coverage/default/16.edn_stress_all.2905183615 Oct 11 12:51:42 PM PDT 23 Oct 11 12:51:45 PM PDT 23 51684556 ps
T197 /workspace/coverage/default/43.edn_disable.3255275352 Oct 11 12:52:58 PM PDT 23 Oct 11 12:52:59 PM PDT 23 11113362 ps
T600 /workspace/coverage/default/42.edn_alert.134688948 Oct 11 12:52:42 PM PDT 23 Oct 11 12:52:43 PM PDT 23 26345591 ps
T601 /workspace/coverage/default/1.edn_regwen.1110593671 Oct 11 12:52:05 PM PDT 23 Oct 11 12:52:06 PM PDT 23 52828853 ps
T291 /workspace/coverage/default/9.edn_alert.3695002192 Oct 11 12:52:07 PM PDT 23 Oct 11 12:52:08 PM PDT 23 30442096 ps
T602 /workspace/coverage/default/12.edn_disable_auto_req_mode.1465202976 Oct 11 12:52:58 PM PDT 23 Oct 11 12:52:59 PM PDT 23 44433252 ps
T603 /workspace/coverage/default/49.edn_alert_test.2630452134 Oct 11 12:53:00 PM PDT 23 Oct 11 12:53:02 PM PDT 23 36497660 ps
T604 /workspace/coverage/default/34.edn_err.3275590712 Oct 11 12:52:52 PM PDT 23 Oct 11 12:52:53 PM PDT 23 62876011 ps
T605 /workspace/coverage/default/27.edn_alert.3932255545 Oct 11 12:52:32 PM PDT 23 Oct 11 12:52:34 PM PDT 23 21574278 ps
T135 /workspace/coverage/default/1.edn_disable.896826111 Oct 11 12:51:43 PM PDT 23 Oct 11 12:51:44 PM PDT 23 17842022 ps
T606 /workspace/coverage/default/70.edn_err.1337819280 Oct 11 12:53:51 PM PDT 23 Oct 11 12:53:52 PM PDT 23 23096032 ps
T607 /workspace/coverage/default/27.edn_disable.2998732426 Oct 11 12:52:54 PM PDT 23 Oct 11 12:52:56 PM PDT 23 22823791 ps
T608 /workspace/coverage/default/37.edn_stress_all.483736325 Oct 11 12:53:00 PM PDT 23 Oct 11 12:53:03 PM PDT 23 52233119 ps
T609 /workspace/coverage/default/30.edn_intr.555441183 Oct 11 12:52:38 PM PDT 23 Oct 11 12:52:40 PM PDT 23 22022517 ps
T610 /workspace/coverage/default/35.edn_stress_all.1648428386 Oct 11 12:52:47 PM PDT 23 Oct 11 12:52:49 PM PDT 23 44434873 ps
T193 /workspace/coverage/default/89.edn_err.2171548490 Oct 11 12:53:00 PM PDT 23 Oct 11 12:53:03 PM PDT 23 29571565 ps
T611 /workspace/coverage/default/11.edn_intr.1904194821 Oct 11 12:52:28 PM PDT 23 Oct 11 12:52:40 PM PDT 23 20364231 ps
T269 /workspace/coverage/default/29.edn_stress_all_with_rand_reset.3266222161 Oct 11 12:52:53 PM PDT 23 Oct 11 01:23:49 PM PDT 23 85297106698 ps
T612 /workspace/coverage/default/20.edn_alert.1275239202 Oct 11 12:51:50 PM PDT 23 Oct 11 12:51:52 PM PDT 23 53488034 ps
T613 /workspace/coverage/default/23.edn_err.2921695726 Oct 11 12:53:05 PM PDT 23 Oct 11 12:53:06 PM PDT 23 18698139 ps
T137 /workspace/coverage/default/29.edn_disable.2766179386 Oct 11 12:52:59 PM PDT 23 Oct 11 12:53:00 PM PDT 23 12931558 ps
T264 /workspace/coverage/default/42.edn_stress_all.456099085 Oct 11 12:53:08 PM PDT 23 Oct 11 12:53:10 PM PDT 23 120957092 ps
T614 /workspace/coverage/default/15.edn_alert.2340237584 Oct 11 12:52:46 PM PDT 23 Oct 11 12:52:48 PM PDT 23 30647368 ps
T615 /workspace/coverage/default/46.edn_intr.3114912421 Oct 11 12:53:12 PM PDT 23 Oct 11 12:53:15 PM PDT 23 28460235 ps
T270 /workspace/coverage/default/28.edn_genbits.4087684776 Oct 11 12:52:28 PM PDT 23 Oct 11 12:52:29 PM PDT 23 22557523 ps
T190 /workspace/coverage/default/3.edn_disable.3031138347 Oct 11 12:51:09 PM PDT 23 Oct 11 12:51:10 PM PDT 23 38406174 ps
T182 /workspace/coverage/default/60.edn_err.717913642 Oct 11 12:53:16 PM PDT 23 Oct 11 12:53:18 PM PDT 23 19463943 ps
T616 /workspace/coverage/default/8.edn_err.3675659766 Oct 11 12:51:29 PM PDT 23 Oct 11 12:51:30 PM PDT 23 23868599 ps
T617 /workspace/coverage/default/41.edn_disable.472362093 Oct 11 12:52:28 PM PDT 23 Oct 11 12:52:30 PM PDT 23 13906232 ps
T618 /workspace/coverage/default/22.edn_intr.1193612816 Oct 11 12:52:30 PM PDT 23 Oct 11 12:52:31 PM PDT 23 130344988 ps
T619 /workspace/coverage/default/26.edn_genbits.3389509506 Oct 11 12:53:03 PM PDT 23 Oct 11 12:53:04 PM PDT 23 36996224 ps
T620 /workspace/coverage/default/23.edn_alert.164870585 Oct 11 12:53:07 PM PDT 23 Oct 11 12:53:09 PM PDT 23 94988593 ps
T621 /workspace/coverage/default/28.edn_stress_all.3087362173 Oct 11 12:52:52 PM PDT 23 Oct 11 12:52:54 PM PDT 23 145322749 ps
T622 /workspace/coverage/default/1.edn_smoke.3644868145 Oct 11 12:51:29 PM PDT 23 Oct 11 12:51:30 PM PDT 23 15852061 ps
T623 /workspace/coverage/default/13.edn_stress_all_with_rand_reset.476684036 Oct 11 12:52:25 PM PDT 23 Oct 11 01:09:25 PM PDT 23 440408130449 ps
T624 /workspace/coverage/default/18.edn_stress_all_with_rand_reset.3625235613 Oct 11 12:51:26 PM PDT 23 Oct 11 12:54:14 PM PDT 23 30298740829 ps
T298 /workspace/coverage/default/12.edn_alert.434877134 Oct 11 12:52:46 PM PDT 23 Oct 11 12:52:47 PM PDT 23 175788687 ps
T625 /workspace/coverage/default/24.edn_alert.1120163128 Oct 11 12:52:53 PM PDT 23 Oct 11 12:52:55 PM PDT 23 20497857 ps
T626 /workspace/coverage/default/43.edn_alert_test.2641196371 Oct 11 12:52:44 PM PDT 23 Oct 11 12:52:45 PM PDT 23 48913092 ps
T627 /workspace/coverage/default/33.edn_disable_auto_req_mode.1275553761 Oct 11 12:52:46 PM PDT 23 Oct 11 12:52:53 PM PDT 23 63836053 ps
T628 /workspace/coverage/default/24.edn_stress_all_with_rand_reset.2179155551 Oct 11 12:53:05 PM PDT 23 Oct 11 01:15:25 PM PDT 23 106066911850 ps
T240 /workspace/coverage/default/31.edn_disable.2498325578 Oct 11 12:52:12 PM PDT 23 Oct 11 12:52:13 PM PDT 23 17978662 ps
T629 /workspace/coverage/default/13.edn_disable_auto_req_mode.4038717610 Oct 11 12:52:08 PM PDT 23 Oct 11 12:52:09 PM PDT 23 27946751 ps
T130 /workspace/coverage/default/18.edn_disable.2397851745 Oct 11 12:52:30 PM PDT 23 Oct 11 12:52:31 PM PDT 23 30326517 ps
T630 /workspace/coverage/default/32.edn_err.2108473099 Oct 11 12:53:41 PM PDT 23 Oct 11 12:53:43 PM PDT 23 31849252 ps
T631 /workspace/coverage/default/8.edn_intr.3244368016 Oct 11 12:52:21 PM PDT 23 Oct 11 12:52:22 PM PDT 23 35535035 ps
T632 /workspace/coverage/default/36.edn_alert.1734086578 Oct 11 12:52:58 PM PDT 23 Oct 11 12:52:59 PM PDT 23 34114566 ps
T633 /workspace/coverage/default/43.edn_intr.4068447410 Oct 11 12:52:49 PM PDT 23 Oct 11 12:52:51 PM PDT 23 20834835 ps
T634 /workspace/coverage/default/47.edn_smoke.3600260250 Oct 11 12:52:59 PM PDT 23 Oct 11 12:53:00 PM PDT 23 12166165 ps
T635 /workspace/coverage/default/44.edn_disable_auto_req_mode.2362425920 Oct 11 12:52:47 PM PDT 23 Oct 11 12:52:49 PM PDT 23 303424462 ps
T252 /workspace/coverage/default/9.edn_disable_auto_req_mode.3299570864 Oct 11 12:52:14 PM PDT 23 Oct 11 12:52:16 PM PDT 23 17449160 ps
T287 /workspace/coverage/default/23.edn_genbits.3541856146 Oct 11 12:52:58 PM PDT 23 Oct 11 12:53:00 PM PDT 23 35538237 ps
T636 /workspace/coverage/default/73.edn_err.3120528976 Oct 11 12:54:13 PM PDT 23 Oct 11 12:54:15 PM PDT 23 57897871 ps
T637 /workspace/coverage/default/40.edn_alert.356137178 Oct 11 12:52:15 PM PDT 23 Oct 11 12:52:16 PM PDT 23 17954923 ps
T638 /workspace/coverage/default/45.edn_err.1402385954 Oct 11 12:52:57 PM PDT 23 Oct 11 12:52:58 PM PDT 23 45843323 ps
T639 /workspace/coverage/default/14.edn_alert_test.231561409 Oct 11 12:52:25 PM PDT 23 Oct 11 12:52:26 PM PDT 23 16807729 ps
T640 /workspace/coverage/default/2.edn_stress_all_with_rand_reset.2678157214 Oct 11 12:51:19 PM PDT 23 Oct 11 01:00:47 PM PDT 23 254321893289 ps
T641 /workspace/coverage/default/5.edn_stress_all_with_rand_reset.2820199362 Oct 11 12:52:45 PM PDT 23 Oct 11 01:27:11 PM PDT 23 1366179923698 ps
T642 /workspace/coverage/default/74.edn_err.1592446551 Oct 11 12:53:38 PM PDT 23 Oct 11 12:53:39 PM PDT 23 22925439 ps
T643 /workspace/coverage/default/7.edn_alert.3092440195 Oct 11 12:51:15 PM PDT 23 Oct 11 12:51:17 PM PDT 23 32107340 ps
T644 /workspace/coverage/default/47.edn_alert.2894230029 Oct 11 12:52:47 PM PDT 23 Oct 11 12:52:48 PM PDT 23 57152573 ps
T645 /workspace/coverage/default/43.edn_smoke.3966227502 Oct 11 12:52:48 PM PDT 23 Oct 11 12:52:49 PM PDT 23 24750162 ps
T646 /workspace/coverage/default/37.edn_smoke.1322092411 Oct 11 12:53:10 PM PDT 23 Oct 11 12:53:11 PM PDT 23 44024025 ps
T647 /workspace/coverage/default/21.edn_alert.2440729008 Oct 11 12:52:29 PM PDT 23 Oct 11 12:52:30 PM PDT 23 19292864 ps
T294 /workspace/coverage/default/1.edn_alert.2399921845 Oct 11 12:52:14 PM PDT 23 Oct 11 12:52:16 PM PDT 23 37047323 ps
T648 /workspace/coverage/default/3.edn_stress_all_with_rand_reset.2063055817 Oct 11 12:52:18 PM PDT 23 Oct 11 12:58:52 PM PDT 23 17512011833 ps
T649 /workspace/coverage/default/45.edn_genbits.3785780137 Oct 11 12:52:55 PM PDT 23 Oct 11 12:52:56 PM PDT 23 16141850 ps
T288 /workspace/coverage/default/8.edn_genbits.1963108412 Oct 11 12:51:39 PM PDT 23 Oct 11 12:51:40 PM PDT 23 67527269 ps
T650 /workspace/coverage/default/14.edn_intr.3109468829 Oct 11 12:52:46 PM PDT 23 Oct 11 12:52:48 PM PDT 23 27101800 ps
T651 /workspace/coverage/default/5.edn_stress_all.2059865336 Oct 11 12:52:27 PM PDT 23 Oct 11 12:52:29 PM PDT 23 173646185 ps
T652 /workspace/coverage/default/40.edn_disable_auto_req_mode.411809977 Oct 11 12:52:32 PM PDT 23 Oct 11 12:52:34 PM PDT 23 18357693 ps
T653 /workspace/coverage/default/29.edn_err.2624943982 Oct 11 12:53:06 PM PDT 23 Oct 11 12:53:08 PM PDT 23 71999255 ps
T120 /workspace/coverage/default/41.edn_intr.444673704 Oct 11 12:53:21 PM PDT 23 Oct 11 12:53:22 PM PDT 23 33457354 ps
T654 /workspace/coverage/default/36.edn_stress_all.1886436689 Oct 11 12:52:56 PM PDT 23 Oct 11 12:53:00 PM PDT 23 188040964 ps
T655 /workspace/coverage/default/86.edn_err.3214379625 Oct 11 12:53:19 PM PDT 23 Oct 11 12:53:20 PM PDT 23 21713890 ps
T132 /workspace/coverage/default/24.edn_disable.2049068204 Oct 11 12:52:56 PM PDT 23 Oct 11 12:52:57 PM PDT 23 80487226 ps
T656 /workspace/coverage/default/27.edn_stress_all_with_rand_reset.1440522302 Oct 11 12:52:40 PM PDT 23 Oct 11 01:27:07 PM PDT 23 190948906128 ps
T657 /workspace/coverage/default/19.edn_stress_all.3818455251 Oct 11 12:52:11 PM PDT 23 Oct 11 12:52:20 PM PDT 23 350441356 ps
T658 /workspace/coverage/default/25.edn_disable.3364032703 Oct 11 12:52:28 PM PDT 23 Oct 11 12:52:29 PM PDT 23 40041548 ps
T659 /workspace/coverage/default/30.edn_genbits.2291844759 Oct 11 12:52:55 PM PDT 23 Oct 11 12:52:57 PM PDT 23 35886198 ps
T660 /workspace/coverage/default/50.edn_err.3912548331 Oct 11 12:53:55 PM PDT 23 Oct 11 12:53:56 PM PDT 23 25435545 ps
T661 /workspace/coverage/default/54.edn_err.49133723 Oct 11 12:53:40 PM PDT 23 Oct 11 12:53:41 PM PDT 23 21958744 ps
T662 /workspace/coverage/default/45.edn_disable.3495992888 Oct 11 12:52:52 PM PDT 23 Oct 11 12:52:54 PM PDT 23 28043538 ps
T187 /workspace/coverage/default/82.edn_err.2237578530 Oct 11 12:53:03 PM PDT 23 Oct 11 12:53:04 PM PDT 23 75556619 ps
T127 /workspace/coverage/default/47.edn_disable.697286666 Oct 11 12:52:47 PM PDT 23 Oct 11 12:52:48 PM PDT 23 12935019 ps
T663 /workspace/coverage/default/29.edn_alert_test.3617042520 Oct 11 12:53:19 PM PDT 23 Oct 11 12:53:20 PM PDT 23 49486133 ps
T664 /workspace/coverage/default/2.edn_disable.719279674 Oct 11 12:52:41 PM PDT 23 Oct 11 12:52:42 PM PDT 23 19169957 ps
T665 /workspace/coverage/default/17.edn_intr.3294566780 Oct 11 12:51:57 PM PDT 23 Oct 11 12:51:58 PM PDT 23 20279873 ps
T666 /workspace/coverage/default/28.edn_stress_all_with_rand_reset.509221427 Oct 11 12:52:50 PM PDT 23 Oct 11 01:03:51 PM PDT 23 31314784699 ps
T667 /workspace/coverage/default/36.edn_intr.4206171708 Oct 11 12:53:10 PM PDT 23 Oct 11 12:53:12 PM PDT 23 18606571 ps
T668 /workspace/coverage/default/1.edn_intr.3837053073 Oct 11 12:52:06 PM PDT 23 Oct 11 12:52:07 PM PDT 23 34075158 ps
T188 /workspace/coverage/default/1.edn_err.1950770775 Oct 11 12:51:35 PM PDT 23 Oct 11 12:51:36 PM PDT 23 26169690 ps
T669 /workspace/coverage/default/9.edn_err.3022793539 Oct 11 12:52:15 PM PDT 23 Oct 11 12:52:17 PM PDT 23 19154413 ps
T670 /workspace/coverage/default/8.edn_disable.4140674836 Oct 11 12:52:06 PM PDT 23 Oct 11 12:52:07 PM PDT 23 11076975 ps
T671 /workspace/coverage/default/33.edn_stress_all.110814258 Oct 11 12:52:41 PM PDT 23 Oct 11 12:52:43 PM PDT 23 55738001 ps
T672 /workspace/coverage/default/6.edn_intr.53678564 Oct 11 12:53:06 PM PDT 23 Oct 11 12:53:07 PM PDT 23 24906303 ps
T673 /workspace/coverage/default/28.edn_alert_test.1153991500 Oct 11 12:52:58 PM PDT 23 Oct 11 12:52:59 PM PDT 23 19082127 ps
T674 /workspace/coverage/default/40.edn_err.904713799 Oct 11 12:53:10 PM PDT 23 Oct 11 12:53:12 PM PDT 23 32620132 ps
T675 /workspace/coverage/default/39.edn_alert.1464724824 Oct 11 12:52:38 PM PDT 23 Oct 11 12:52:40 PM PDT 23 20501938 ps
T676 /workspace/coverage/default/9.edn_stress_all_with_rand_reset.487040205 Oct 11 12:52:14 PM PDT 23 Oct 11 01:21:42 PM PDT 23 149157325381 ps
T677 /workspace/coverage/default/14.edn_disable.3373928422 Oct 11 12:52:30 PM PDT 23 Oct 11 12:52:31 PM PDT 23 12677491 ps
T189 /workspace/coverage/default/2.edn_err.3383327337 Oct 11 12:53:01 PM PDT 23 Oct 11 12:53:02 PM PDT 23 20374223 ps
T254 /workspace/coverage/default/36.edn_err.3374138133 Oct 11 12:52:52 PM PDT 23 Oct 11 12:52:53 PM PDT 23 24125228 ps
T250 /workspace/coverage/default/93.edn_err.2617461531 Oct 11 12:53:09 PM PDT 23 Oct 11 12:53:11 PM PDT 23 24521200 ps
T678 /workspace/coverage/default/28.edn_smoke.2887787533 Oct 11 12:52:28 PM PDT 23 Oct 11 12:52:30 PM PDT 23 14594009 ps
T679 /workspace/coverage/default/29.edn_intr.2330298187 Oct 11 12:52:31 PM PDT 23 Oct 11 12:52:33 PM PDT 23 103700179 ps
T680 /workspace/coverage/default/8.edn_smoke.439225561 Oct 11 12:51:32 PM PDT 23 Oct 11 12:51:33 PM PDT 23 49094624 ps
T681 /workspace/coverage/default/3.edn_intr.2119438692 Oct 11 12:51:28 PM PDT 23 Oct 11 12:51:29 PM PDT 23 23891365 ps
T682 /workspace/coverage/default/33.edn_smoke.763578934 Oct 11 12:52:38 PM PDT 23 Oct 11 12:52:40 PM PDT 23 12977966 ps
T200 /workspace/coverage/default/88.edn_err.937236809 Oct 11 12:53:01 PM PDT 23 Oct 11 12:53:02 PM PDT 23 29911852 ps
T683 /workspace/coverage/default/38.edn_intr.3709991364 Oct 11 12:52:59 PM PDT 23 Oct 11 12:53:00 PM PDT 23 23228595 ps
T684 /workspace/coverage/default/0.edn_intr.2883730490 Oct 11 12:51:36 PM PDT 23 Oct 11 12:51:39 PM PDT 23 24021517 ps
T685 /workspace/coverage/default/12.edn_alert_test.2157712220 Oct 11 12:52:15 PM PDT 23 Oct 11 12:52:16 PM PDT 23 33067245 ps
T686 /workspace/coverage/default/39.edn_stress_all.66512823 Oct 11 12:52:43 PM PDT 23 Oct 11 12:52:46 PM PDT 23 472832709 ps
T687 /workspace/coverage/default/1.edn_stress_all_with_rand_reset.291037089 Oct 11 12:52:21 PM PDT 23 Oct 11 01:08:30 PM PDT 23 113977677231 ps
T688 /workspace/coverage/default/15.edn_stress_all.2723880533 Oct 11 12:52:41 PM PDT 23 Oct 11 12:52:43 PM PDT 23 47107239 ps
T689 /workspace/coverage/default/14.edn_alert.2901466293 Oct 11 12:52:33 PM PDT 23 Oct 11 12:52:35 PM PDT 23 17007912 ps
T690 /workspace/coverage/default/44.edn_alert_test.3550470346 Oct 11 12:53:17 PM PDT 23 Oct 11 12:53:18 PM PDT 23 32300209 ps
T691 /workspace/coverage/default/9.edn_genbits.1116428902 Oct 11 12:52:21 PM PDT 23 Oct 11 12:52:25 PM PDT 23 64312725 ps
T261 /workspace/coverage/default/71.edn_err.3585964370 Oct 11 12:53:44 PM PDT 23 Oct 11 12:53:45 PM PDT 23 94412446 ps
T692 /workspace/coverage/default/32.edn_intr.3643229658 Oct 11 12:52:46 PM PDT 23 Oct 11 12:52:47 PM PDT 23 30696987 ps
T693 /workspace/coverage/default/39.edn_err.3429799769 Oct 11 12:52:37 PM PDT 23 Oct 11 12:52:38 PM PDT 23 22492740 ps
T694 /workspace/coverage/default/25.edn_alert_test.1542687950 Oct 11 12:52:33 PM PDT 23 Oct 11 12:52:34 PM PDT 23 20293346 ps
T695 /workspace/coverage/default/25.edn_intr.2943549281 Oct 11 12:52:40 PM PDT 23 Oct 11 12:52:42 PM PDT 23 18772616 ps
T696 /workspace/coverage/default/31.edn_intr.2779917336 Oct 11 12:52:38 PM PDT 23 Oct 11 12:52:39 PM PDT 23 30980257 ps
T697 /workspace/coverage/default/61.edn_err.127326253 Oct 11 12:53:54 PM PDT 23 Oct 11 12:53:55 PM PDT 23 24919191 ps
T698 /workspace/coverage/default/0.edn_alert_test.2141099770 Oct 11 12:52:34 PM PDT 23 Oct 11 12:52:35 PM PDT 23 33712750 ps
T54 /workspace/coverage/default/4.edn_sec_cm.2336409314 Oct 11 12:52:35 PM PDT 23 Oct 11 12:52:41 PM PDT 23 644461303 ps
T699 /workspace/coverage/default/17.edn_err.4088095349 Oct 11 12:52:09 PM PDT 23 Oct 11 12:52:11 PM PDT 23 30932870 ps
T700 /workspace/coverage/default/33.edn_genbits.14615450 Oct 11 12:52:26 PM PDT 23 Oct 11 12:52:28 PM PDT 23 26475148 ps
T701 /workspace/coverage/default/7.edn_stress_all_with_rand_reset.2514980215 Oct 11 12:51:51 PM PDT 23 Oct 11 01:17:38 PM PDT 23 66671264500 ps
T702 /workspace/coverage/default/28.edn_disable_auto_req_mode.267249953 Oct 11 12:53:03 PM PDT 23 Oct 11 12:53:04 PM PDT 23 37032560 ps
T703 /workspace/coverage/default/24.edn_intr.1978826470 Oct 11 12:52:45 PM PDT 23 Oct 11 12:52:47 PM PDT 23 44825471 ps
T704 /workspace/coverage/default/27.edn_alert_test.1403868678 Oct 11 12:52:31 PM PDT 23 Oct 11 12:52:33 PM PDT 23 21402375 ps
T705 /workspace/coverage/default/30.edn_alert_test.1100763508 Oct 11 12:52:38 PM PDT 23 Oct 11 12:52:40 PM PDT 23 26101613 ps
T706 /workspace/coverage/default/30.edn_alert.906952425 Oct 11 12:52:56 PM PDT 23 Oct 11 12:52:58 PM PDT 23 17751973 ps
T55 /workspace/coverage/default/3.edn_sec_cm.1373789290 Oct 11 12:51:28 PM PDT 23 Oct 11 12:51:32 PM PDT 23 319422984 ps
T707 /workspace/coverage/default/6.edn_stress_all.2575771696 Oct 11 12:52:46 PM PDT 23 Oct 11 12:52:48 PM PDT 23 64533474 ps
T249 /workspace/coverage/default/7.edn_disable.4171185824 Oct 11 12:51:26 PM PDT 23 Oct 11 12:51:27 PM PDT 23 42535827 ps
T708 /workspace/coverage/default/4.edn_intr.1482911609 Oct 11 12:51:40 PM PDT 23 Oct 11 12:51:42 PM PDT 23 26231569 ps
T709 /workspace/coverage/default/22.edn_alert_test.2469525602 Oct 11 12:52:41 PM PDT 23 Oct 11 12:52:42 PM PDT 23 46974310 ps
T710 /workspace/coverage/default/27.edn_intr.2534634127 Oct 11 12:52:19 PM PDT 23 Oct 11 12:52:20 PM PDT 23 18574676 ps
T711 /workspace/coverage/default/9.edn_disable.4146060757 Oct 11 12:53:01 PM PDT 23 Oct 11 12:53:02 PM PDT 23 22247922 ps
T712 /workspace/coverage/default/24.edn_smoke.4191422356 Oct 11 12:52:51 PM PDT 23 Oct 11 12:52:53 PM PDT 23 20094441 ps
T713 /workspace/coverage/default/4.edn_stress_all_with_rand_reset.1984961334 Oct 11 12:51:47 PM PDT 23 Oct 11 01:01:35 PM PDT 23 27832455596 ps
T306 /workspace/coverage/default/7.edn_regwen.3156396645 Oct 11 12:51:15 PM PDT 23 Oct 11 12:51:16 PM PDT 23 26485896 ps
T714 /workspace/coverage/default/26.edn_disable_auto_req_mode.2079065780 Oct 11 12:52:09 PM PDT 23 Oct 11 12:52:10 PM PDT 23 49683055 ps
T715 /workspace/coverage/default/30.edn_stress_all_with_rand_reset.3295361067 Oct 11 12:52:59 PM PDT 23 Oct 11 01:32:37 PM PDT 23 394891836201 ps
T716 /workspace/coverage/default/23.edn_disable.163448735 Oct 11 12:53:00 PM PDT 23 Oct 11 12:53:02 PM PDT 23 64680347 ps
T717 /workspace/coverage/default/29.edn_smoke.1593359379 Oct 11 12:52:54 PM PDT 23 Oct 11 12:52:56 PM PDT 23 33406902 ps
T718 /workspace/coverage/default/43.edn_alert.3861571777 Oct 11 12:52:27 PM PDT 23 Oct 11 12:52:28 PM PDT 23 18839386 ps
T719 /workspace/coverage/default/14.edn_genbits.1406592145 Oct 11 12:52:44 PM PDT 23 Oct 11 12:52:46 PM PDT 23 54293309 ps
T238 /workspace/coverage/default/43.edn_err.3859810669 Oct 11 12:53:05 PM PDT 23 Oct 11 12:53:06 PM PDT 23 29312768 ps
T295 /workspace/coverage/default/5.edn_alert.1249960744 Oct 11 12:52:20 PM PDT 23 Oct 11 12:52:22 PM PDT 23 64609033 ps
T720 /workspace/coverage/default/7.edn_stress_all.150276285 Oct 11 12:51:31 PM PDT 23 Oct 11 12:51:34 PM PDT 23 112705428 ps
T721 /workspace/coverage/default/11.edn_alert_test.2490023152 Oct 11 12:53:07 PM PDT 23 Oct 11 12:53:08 PM PDT 23 18285612 ps
T722 /workspace/coverage/default/2.edn_stress_all.3516268818 Oct 11 12:52:39 PM PDT 23 Oct 11 12:52:42 PM PDT 23 534238973 ps
T723 /workspace/coverage/default/32.edn_alert.1920233885 Oct 11 12:52:49 PM PDT 23 Oct 11 12:52:50 PM PDT 23 27161539 ps
T724 /workspace/coverage/default/11.edn_alert.4282233504 Oct 11 12:53:04 PM PDT 23 Oct 11 12:53:05 PM PDT 23 63406446 ps
T725 /workspace/coverage/default/41.edn_genbits.1717084108 Oct 11 12:52:42 PM PDT 23 Oct 11 12:52:44 PM PDT 23 19026451 ps
T726 /workspace/coverage/default/8.edn_stress_all.4237993128 Oct 11 12:51:12 PM PDT 23 Oct 11 12:51:15 PM PDT 23 194764923 ps
T727 /workspace/coverage/default/13.edn_intr.658816213 Oct 11 12:51:35 PM PDT 23 Oct 11 12:51:36 PM PDT 23 23945911 ps

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.4054631229
Short name T17
Test name
Test status
Simulation time 129842590511 ps
CPU time 1494.24 seconds
Started Oct 11 12:52:48 PM PDT 23
Finished Oct 11 01:17:43 PM PDT 23
Peak memory 218452 kb
Host smart-7b0a7607-e92f-436b-9cdb-e8aa10904657
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054631229 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.4054631229
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.2680750690
Short name T6
Test name
Test status
Simulation time 89544743 ps
CPU time 1.03 seconds
Started Oct 11 12:53:02 PM PDT 23
Finished Oct 11 12:53:04 PM PDT 23
Peak memory 214676 kb
Host smart-394a4c38-8ab5-470f-b85e-34eaa40d1cf9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680750690 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.2680750690
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_genbits.2058711693
Short name T30
Test name
Test status
Simulation time 72692709 ps
CPU time 1.05 seconds
Started Oct 11 12:52:51 PM PDT 23
Finished Oct 11 12:52:52 PM PDT 23
Peak memory 205208 kb
Host smart-049c3200-9296-4e39-86b5-3afecf4feab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058711693 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.2058711693
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.206026256
Short name T74
Test name
Test status
Simulation time 55698577 ps
CPU time 0.8 seconds
Started Oct 11 12:53:35 PM PDT 23
Finished Oct 11 12:53:36 PM PDT 23
Peak memory 215608 kb
Host smart-6444e47e-d71a-4668-aca1-9ed71f225c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206026256 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.206026256
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/1.edn_sec_cm.3630308597
Short name T22
Test name
Test status
Simulation time 416313999 ps
CPU time 5.91 seconds
Started Oct 11 12:52:14 PM PDT 23
Finished Oct 11 12:52:21 PM PDT 23
Peak memory 232100 kb
Host smart-7f187f6f-7a8f-4ddb-a78b-0f6a74db0cb9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630308597 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.3630308597
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/38.edn_disable.2217177168
Short name T35
Test name
Test status
Simulation time 37031632 ps
CPU time 0.84 seconds
Started Oct 11 12:53:02 PM PDT 23
Finished Oct 11 12:53:04 PM PDT 23
Peak memory 214384 kb
Host smart-e9dd0176-0637-4ab1-aaa8-c949ef080d0b
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217177168 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.2217177168
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/45.edn_alert.1560716350
Short name T13
Test name
Test status
Simulation time 189491838 ps
CPU time 0.87 seconds
Started Oct 11 12:52:56 PM PDT 23
Finished Oct 11 12:52:57 PM PDT 23
Peak memory 206232 kb
Host smart-4f95260b-f094-4b7d-a447-46e9779c34e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560716350 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.1560716350
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/2.edn_regwen.2674352209
Short name T19
Test name
Test status
Simulation time 36585136 ps
CPU time 0.83 seconds
Started Oct 11 12:52:46 PM PDT 23
Finished Oct 11 12:52:48 PM PDT 23
Peak memory 205024 kb
Host smart-d19674a2-376f-4679-9161-cb97ce9225d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674352209 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.2674352209
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/92.edn_err.4173740917
Short name T4
Test name
Test status
Simulation time 23677494 ps
CPU time 1.18 seconds
Started Oct 11 12:53:23 PM PDT 23
Finished Oct 11 12:53:25 PM PDT 23
Peak memory 220248 kb
Host smart-4e1d0207-f8e6-4799-8ac7-f007b48df7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173740917 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.4173740917
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.3137325451
Short name T80
Test name
Test status
Simulation time 22725421 ps
CPU time 1.04 seconds
Started Oct 11 12:52:51 PM PDT 23
Finished Oct 11 12:52:52 PM PDT 23
Peak memory 214644 kb
Host smart-05d8ee37-7672-485e-9d74-c021472b359e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137325451 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.3137325451
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2911866802
Short name T142
Test name
Test status
Simulation time 26009183 ps
CPU time 1.16 seconds
Started Oct 11 12:52:27 PM PDT 23
Finished Oct 11 12:52:28 PM PDT 23
Peak memory 205872 kb
Host smart-500e7f36-dc44-4db8-8d15-419761eca6d8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911866802 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.2911866802
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/default/35.edn_genbits.4064526647
Short name T9
Test name
Test status
Simulation time 20116996 ps
CPU time 1.12 seconds
Started Oct 11 12:53:27 PM PDT 23
Finished Oct 11 12:53:29 PM PDT 23
Peak memory 214436 kb
Host smart-0fd86cc9-110b-4fda-953e-0b45173e16d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064526647 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.4064526647
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_disable.3859179273
Short name T204
Test name
Test status
Simulation time 19748604 ps
CPU time 0.86 seconds
Started Oct 11 12:53:34 PM PDT 23
Finished Oct 11 12:53:35 PM PDT 23
Peak memory 214628 kb
Host smart-e51eb1ed-6961-46ce-81a2-1144f5ac22c4
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859179273 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.3859179273
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.983704418
Short name T150
Test name
Test status
Simulation time 90395926 ps
CPU time 2.37 seconds
Started Oct 11 12:52:57 PM PDT 23
Finished Oct 11 12:53:00 PM PDT 23
Peak memory 205796 kb
Host smart-6f50f6f8-a289-4716-a212-f4880e7acea3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983704418 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.983704418
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/17.edn_disable.1130062029
Short name T138
Test name
Test status
Simulation time 11737890 ps
CPU time 0.83 seconds
Started Oct 11 12:52:34 PM PDT 23
Finished Oct 11 12:52:35 PM PDT 23
Peak memory 214488 kb
Host smart-b040b07d-c1e5-47d1-9c3d-cf48953d2804
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130062029 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.1130062029
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable.3373928422
Short name T677
Test name
Test status
Simulation time 12677491 ps
CPU time 0.85 seconds
Started Oct 11 12:52:30 PM PDT 23
Finished Oct 11 12:52:31 PM PDT 23
Peak memory 214580 kb
Host smart-d2613911-af16-486c-961c-a2301264a476
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373928422 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.3373928422
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable.2498325578
Short name T240
Test name
Test status
Simulation time 17978662 ps
CPU time 0.82 seconds
Started Oct 11 12:52:12 PM PDT 23
Finished Oct 11 12:52:13 PM PDT 23
Peak memory 214348 kb
Host smart-5ddac882-8a61-486f-b56c-9e4a779a068d
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498325578 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.2498325578
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable.4171185824
Short name T249
Test name
Test status
Simulation time 42535827 ps
CPU time 0.88 seconds
Started Oct 11 12:51:26 PM PDT 23
Finished Oct 11 12:51:27 PM PDT 23
Peak memory 214424 kb
Host smart-0c8461f5-612a-4597-8a9a-0f9778f241a0
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171185824 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.4171185824
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.2893960049
Short name T82
Test name
Test status
Simulation time 26885990 ps
CPU time 0.88 seconds
Started Oct 11 12:52:53 PM PDT 23
Finished Oct 11 12:52:54 PM PDT 23
Peak memory 214676 kb
Host smart-e9138553-6f8d-48a1-a846-23bd74fec5ac
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893960049 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.2893960049
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_intr.3329405119
Short name T1
Test name
Test status
Simulation time 59561543 ps
CPU time 0.78 seconds
Started Oct 11 12:53:02 PM PDT 23
Finished Oct 11 12:53:03 PM PDT 23
Peak memory 214640 kb
Host smart-0e871277-ed64-4b14-94d1-a64b1e2b16c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329405119 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.3329405119
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.969815979
Short name T179
Test name
Test status
Simulation time 19299285 ps
CPU time 0.95 seconds
Started Oct 11 12:52:56 PM PDT 23
Finished Oct 11 12:52:58 PM PDT 23
Peak memory 214616 kb
Host smart-92ba606d-c110-4681-b147-2706dda7047b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969815979 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_di
sable_auto_req_mode.969815979
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.3667683907
Short name T44
Test name
Test status
Simulation time 32383253 ps
CPU time 1.28 seconds
Started Oct 11 12:52:30 PM PDT 23
Finished Oct 11 12:52:31 PM PDT 23
Peak memory 227660 kb
Host smart-f643de26-cc60-4c52-a330-3165daa07204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667683907 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.3667683907
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/36.edn_disable.4205083741
Short name T25
Test name
Test status
Simulation time 11305110 ps
CPU time 0.84 seconds
Started Oct 11 12:52:43 PM PDT 23
Finished Oct 11 12:52:45 PM PDT 23
Peak memory 214400 kb
Host smart-55070b56-f251-41a6-8a2b-08176dc0e205
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205083741 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.4205083741
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/0.edn_regwen.2124892118
Short name T290
Test name
Test status
Simulation time 181761722 ps
CPU time 0.84 seconds
Started Oct 11 12:51:30 PM PDT 23
Finished Oct 11 12:51:32 PM PDT 23
Peak memory 204632 kb
Host smart-6d5572b8-db15-4815-96f3-0d8cdb7dcbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124892118 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.2124892118
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_regwen.1725778769
Short name T293
Test name
Test status
Simulation time 31690112 ps
CPU time 0.83 seconds
Started Oct 11 12:51:34 PM PDT 23
Finished Oct 11 12:51:35 PM PDT 23
Peak memory 204992 kb
Host smart-ab6b76b6-0276-4336-bafc-bcf2d330f0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725778769 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.1725778769
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_disable.896826111
Short name T135
Test name
Test status
Simulation time 17842022 ps
CPU time 0.81 seconds
Started Oct 11 12:51:43 PM PDT 23
Finished Oct 11 12:51:44 PM PDT 23
Peak memory 214428 kb
Host smart-75ced0f7-5906-4ec5-974f-52038d7421dc
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896826111 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.896826111
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable.2766179386
Short name T137
Test name
Test status
Simulation time 12931558 ps
CPU time 0.9 seconds
Started Oct 11 12:52:59 PM PDT 23
Finished Oct 11 12:53:00 PM PDT 23
Peak memory 214672 kb
Host smart-27085b49-6698-4851-8597-3f67e53b2be4
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766179386 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.2766179386
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/16.edn_intr.2673648178
Short name T116
Test name
Test status
Simulation time 21323791 ps
CPU time 1.03 seconds
Started Oct 11 12:51:25 PM PDT 23
Finished Oct 11 12:51:26 PM PDT 23
Peak memory 225612 kb
Host smart-a1a1ca19-54a2-4da1-b20b-c282079f648b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673648178 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.2673648178
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.702707392
Short name T520
Test name
Test status
Simulation time 32087027 ps
CPU time 0.94 seconds
Started Oct 11 12:52:37 PM PDT 23
Finished Oct 11 12:52:43 PM PDT 23
Peak memory 214604 kb
Host smart-c2c7bde6-ebe7-4094-9a72-6c8c1f33f29f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702707392 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_di
sable_auto_req_mode.702707392
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.2185654212
Short name T161
Test name
Test status
Simulation time 76000350 ps
CPU time 1 seconds
Started Oct 11 12:52:52 PM PDT 23
Finished Oct 11 12:52:53 PM PDT 23
Peak memory 214676 kb
Host smart-5826acdf-43ac-4b00-ab0e-892ef9ab164a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185654212 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.2185654212
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_disable.719279674
Short name T664
Test name
Test status
Simulation time 19169957 ps
CPU time 0.83 seconds
Started Oct 11 12:52:41 PM PDT 23
Finished Oct 11 12:52:42 PM PDT 23
Peak memory 214356 kb
Host smart-3ffe98ed-512c-4e89-abf5-b251dfe80dfb
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719279674 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.719279674
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/12.edn_alert.434877134
Short name T298
Test name
Test status
Simulation time 175788687 ps
CPU time 1 seconds
Started Oct 11 12:52:46 PM PDT 23
Finished Oct 11 12:52:47 PM PDT 23
Peak memory 206156 kb
Host smart-02464d7a-7baa-49db-b593-537a90ca06ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434877134 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.434877134
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert.1522175600
Short name T302
Test name
Test status
Simulation time 55306976 ps
CPU time 0.87 seconds
Started Oct 11 12:51:53 PM PDT 23
Finished Oct 11 12:51:54 PM PDT 23
Peak memory 205268 kb
Host smart-be3d598e-fcaf-4cc4-ad7f-0d5a524f75be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522175600 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.1522175600
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert.485725508
Short name T305
Test name
Test status
Simulation time 20493648 ps
CPU time 0.96 seconds
Started Oct 11 12:53:07 PM PDT 23
Finished Oct 11 12:53:08 PM PDT 23
Peak memory 205244 kb
Host smart-b4214cc1-148f-44af-8531-6f8094d85c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485725508 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.485725508
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/11.edn_genbits.2205565473
Short name T285
Test name
Test status
Simulation time 20025682 ps
CPU time 0.95 seconds
Started Oct 11 12:52:26 PM PDT 23
Finished Oct 11 12:52:27 PM PDT 23
Peak memory 205176 kb
Host smart-4cd5074e-1a76-46c3-a890-c7199a5fd4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205565473 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.2205565473
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.1598187738
Short name T267
Test name
Test status
Simulation time 234402231354 ps
CPU time 1475.49 seconds
Started Oct 11 12:52:52 PM PDT 23
Finished Oct 11 01:17:28 PM PDT 23
Peak memory 220452 kb
Host smart-06686502-5f69-4c9a-a7b8-115165579417
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598187738 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.1598187738
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert_test.837590985
Short name T18
Test name
Test status
Simulation time 76071881 ps
CPU time 0.78 seconds
Started Oct 11 12:52:16 PM PDT 23
Finished Oct 11 12:52:17 PM PDT 23
Peak memory 204468 kb
Host smart-b1cf11e4-1610-4c49-a028-1ae7a0b45e20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837590985 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.837590985
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_genbits.781637120
Short name T280
Test name
Test status
Simulation time 53429978 ps
CPU time 1.18 seconds
Started Oct 11 12:52:52 PM PDT 23
Finished Oct 11 12:52:53 PM PDT 23
Peak memory 214420 kb
Host smart-546b3910-c131-4078-8968-7e6c0c134890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781637120 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.781637120
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_genbits.1963108412
Short name T288
Test name
Test status
Simulation time 67527269 ps
CPU time 1.23 seconds
Started Oct 11 12:51:39 PM PDT 23
Finished Oct 11 12:51:40 PM PDT 23
Peak memory 214332 kb
Host smart-da015c39-1ed8-479d-af7a-d64f44159329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963108412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.1963108412
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_stress_all.4168262412
Short name T266
Test name
Test status
Simulation time 140288042 ps
CPU time 2.99 seconds
Started Oct 11 12:52:22 PM PDT 23
Finished Oct 11 12:52:26 PM PDT 23
Peak memory 206160 kb
Host smart-66b3ea42-0340-436a-8f79-7ddf3951e2c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168262412 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.4168262412
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.3909596553
Short name T263
Test name
Test status
Simulation time 44751803210 ps
CPU time 1020.91 seconds
Started Oct 11 12:52:35 PM PDT 23
Finished Oct 11 01:09:36 PM PDT 23
Peak memory 216008 kb
Host smart-be54417c-61e2-46d4-bf0b-5e5ab9cd990e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909596553 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.3909596553
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.3266222161
Short name T269
Test name
Test status
Simulation time 85297106698 ps
CPU time 1855.81 seconds
Started Oct 11 12:52:53 PM PDT 23
Finished Oct 11 01:23:49 PM PDT 23
Peak memory 220068 kb
Host smart-ad076f31-32bd-41aa-a117-59283c500032
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266222161 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.3266222161
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1337595767
Short name T274
Test name
Test status
Simulation time 307300283 ps
CPU time 2.17 seconds
Started Oct 11 12:52:23 PM PDT 23
Finished Oct 11 12:52:26 PM PDT 23
Peak memory 205872 kb
Host smart-70c3b80b-0e24-427a-81ff-c138b3b830a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337595767 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1337595767
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/default/10.edn_genbits.4047719505
Short name T64
Test name
Test status
Simulation time 21568674 ps
CPU time 0.86 seconds
Started Oct 11 12:52:17 PM PDT 23
Finished Oct 11 12:52:18 PM PDT 23
Peak memory 204732 kb
Host smart-c34f1b24-557d-4676-a9a9-bb1960865ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047719505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.4047719505
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_genbits.3366306033
Short name T94
Test name
Test status
Simulation time 55804577 ps
CPU time 1.08 seconds
Started Oct 11 12:52:31 PM PDT 23
Finished Oct 11 12:52:33 PM PDT 23
Peak memory 205612 kb
Host smart-73f0d1be-8002-4d24-9da5-fb2657f6c1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366306033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.3366306033
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_genbits.2381661265
Short name T283
Test name
Test status
Simulation time 17959602 ps
CPU time 0.97 seconds
Started Oct 11 12:51:41 PM PDT 23
Finished Oct 11 12:51:44 PM PDT 23
Peak memory 205560 kb
Host smart-9cf67b8a-cc26-4b08-83c3-fdef32473ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381661265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.2381661265
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.164870585
Short name T620
Test name
Test status
Simulation time 94988593 ps
CPU time 1.05 seconds
Started Oct 11 12:53:07 PM PDT 23
Finished Oct 11 12:53:09 PM PDT 23
Peak memory 206268 kb
Host smart-8b108b74-5a80-4324-8e52-8cf957ea0b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164870585 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.164870585
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/3.edn_genbits.3465380701
Short name T262
Test name
Test status
Simulation time 42437886 ps
CPU time 1.04 seconds
Started Oct 11 12:51:23 PM PDT 23
Finished Oct 11 12:51:25 PM PDT 23
Peak memory 214336 kb
Host smart-6117fefd-9204-4137-8813-de22c631a209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465380701 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.3465380701
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_genbits.1793307995
Short name T279
Test name
Test status
Simulation time 99991545 ps
CPU time 0.9 seconds
Started Oct 11 12:52:57 PM PDT 23
Finished Oct 11 12:52:58 PM PDT 23
Peak memory 205008 kb
Host smart-7196b725-1700-4f53-9b66-60681c54e25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793307995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.1793307995
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.3585964370
Short name T261
Test name
Test status
Simulation time 94412446 ps
CPU time 1.13 seconds
Started Oct 11 12:53:44 PM PDT 23
Finished Oct 11 12:53:45 PM PDT 23
Peak memory 214624 kb
Host smart-f73d827f-5aef-41e6-93df-2002ddf7085e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585964370 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.3585964370
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.1656809252
Short name T233
Test name
Test status
Simulation time 67113940 ps
CPU time 0.82 seconds
Started Oct 11 12:52:42 PM PDT 23
Finished Oct 11 12:52:43 PM PDT 23
Peak memory 205788 kb
Host smart-510514c5-6feb-4c32-818f-bffac451d0a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656809252 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.1656809252
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/default/5.edn_intr.2247439312
Short name T115
Test name
Test status
Simulation time 31269430 ps
CPU time 0.84 seconds
Started Oct 11 12:52:43 PM PDT 23
Finished Oct 11 12:52:44 PM PDT 23
Peak memory 214632 kb
Host smart-52741e8e-735d-4dce-b1a9-a97cf20e0bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247439312 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.2247439312
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/13.edn_intr.658816213
Short name T727
Test name
Test status
Simulation time 23945911 ps
CPU time 0.92 seconds
Started Oct 11 12:51:35 PM PDT 23
Finished Oct 11 12:51:36 PM PDT 23
Peak memory 214792 kb
Host smart-15e20148-1a6d-4fa3-be49-52fe73493c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658816213 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.658816213
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/12.edn_disable.1782259542
Short name T129
Test name
Test status
Simulation time 21137734 ps
CPU time 0.81 seconds
Started Oct 11 12:53:06 PM PDT 23
Finished Oct 11 12:53:07 PM PDT 23
Peak memory 214416 kb
Host smart-4a28840b-ae0d-4ec2-beed-b68f3af870e7
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782259542 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.1782259542
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable.4019178012
Short name T125
Test name
Test status
Simulation time 31453278 ps
CPU time 0.77 seconds
Started Oct 11 12:52:22 PM PDT 23
Finished Oct 11 12:52:23 PM PDT 23
Peak memory 214436 kb
Host smart-269437da-8e3b-44ab-b8a3-d77c4fc48572
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019178012 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.4019178012
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable.2049068204
Short name T132
Test name
Test status
Simulation time 80487226 ps
CPU time 0.81 seconds
Started Oct 11 12:52:56 PM PDT 23
Finished Oct 11 12:52:57 PM PDT 23
Peak memory 214432 kb
Host smart-fce42e12-2100-43ba-9e56-8d5097cb9a43
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049068204 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.2049068204
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/1.edn_genbits.3621487543
Short name T510
Test name
Test status
Simulation time 55291076 ps
CPU time 1.12 seconds
Started Oct 11 12:52:34 PM PDT 23
Finished Oct 11 12:52:35 PM PDT 23
Peak memory 205308 kb
Host smart-5dd2fddf-5ed9-40cb-a19b-689663002802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621487543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.3621487543
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3576189996
Short name T357
Test name
Test status
Simulation time 235589766 ps
CPU time 5 seconds
Started Oct 11 12:52:34 PM PDT 23
Finished Oct 11 12:52:44 PM PDT 23
Peak memory 205764 kb
Host smart-2dc8b57e-af09-4348-8306-973b2665f4c0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576189996 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.3576189996
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.662013291
Short name T232
Test name
Test status
Simulation time 65014625 ps
CPU time 0.85 seconds
Started Oct 11 12:51:42 PM PDT 23
Finished Oct 11 12:51:44 PM PDT 23
Peak memory 205776 kb
Host smart-b44982ef-1788-4fa8-b174-1588351ffe62
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662013291 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.662013291
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1206537800
Short name T389
Test name
Test status
Simulation time 20454202 ps
CPU time 1.07 seconds
Started Oct 11 12:52:50 PM PDT 23
Finished Oct 11 12:52:51 PM PDT 23
Peak memory 214052 kb
Host smart-90be037d-1278-44bb-8147-8a89d59244fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206537800 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.1206537800
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.1716056113
Short name T378
Test name
Test status
Simulation time 19528499 ps
CPU time 0.78 seconds
Started Oct 11 12:52:21 PM PDT 23
Finished Oct 11 12:52:23 PM PDT 23
Peak memory 205608 kb
Host smart-7389a43d-9a1e-4e3f-825c-9562385065a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716056113 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1716056113
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1475674260
Short name T362
Test name
Test status
Simulation time 15801796 ps
CPU time 0.94 seconds
Started Oct 11 12:52:52 PM PDT 23
Finished Oct 11 12:52:54 PM PDT 23
Peak memory 205836 kb
Host smart-ea854435-919c-46ef-b15c-af5600be5174
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475674260 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.1475674260
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.513985579
Short name T345
Test name
Test status
Simulation time 82514602 ps
CPU time 2.86 seconds
Started Oct 11 12:52:37 PM PDT 23
Finished Oct 11 12:52:41 PM PDT 23
Peak memory 213888 kb
Host smart-e310cf3c-623b-47e3-885d-e164d78e3bd1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513985579 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.513985579
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1559608938
Short name T402
Test name
Test status
Simulation time 608500455 ps
CPU time 2.28 seconds
Started Oct 11 12:52:35 PM PDT 23
Finished Oct 11 12:52:38 PM PDT 23
Peak memory 205776 kb
Host smart-866a0e5b-cdeb-4e0c-a2ae-de9a03ec719f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559608938 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.1559608938
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2780786911
Short name T147
Test name
Test status
Simulation time 23467135 ps
CPU time 1.04 seconds
Started Oct 11 12:52:38 PM PDT 23
Finished Oct 11 12:52:39 PM PDT 23
Peak memory 205700 kb
Host smart-f1f06b9a-9c25-4534-bf14-0a758798e59f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780786911 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.2780786911
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2491284782
Short name T163
Test name
Test status
Simulation time 1841992647 ps
CPU time 3.7 seconds
Started Oct 11 12:52:42 PM PDT 23
Finished Oct 11 12:52:46 PM PDT 23
Peak memory 205716 kb
Host smart-222d98e5-0bbf-49d8-a50c-5f24b0391bef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491284782 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2491284782
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3120348998
Short name T226
Test name
Test status
Simulation time 74437508 ps
CPU time 0.81 seconds
Started Oct 11 12:53:07 PM PDT 23
Finished Oct 11 12:53:09 PM PDT 23
Peak memory 205536 kb
Host smart-e6bbb174-e967-48ef-803c-bbf87e19d1dd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120348998 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.3120348998
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2073776919
Short name T348
Test name
Test status
Simulation time 60036217 ps
CPU time 1.26 seconds
Started Oct 11 12:52:27 PM PDT 23
Finished Oct 11 12:52:29 PM PDT 23
Peak memory 214056 kb
Host smart-70a13bf8-80c8-46a9-8f7c-d27d02c4658a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073776919 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.2073776919
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.615329197
Short name T210
Test name
Test status
Simulation time 13761189 ps
CPU time 0.86 seconds
Started Oct 11 12:52:15 PM PDT 23
Finished Oct 11 12:52:16 PM PDT 23
Peak memory 205744 kb
Host smart-3cc2266f-aed0-4991-b9ae-b0b26b69b57f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615329197 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.615329197
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.2472890302
Short name T398
Test name
Test status
Simulation time 90261407 ps
CPU time 0.83 seconds
Started Oct 11 12:52:53 PM PDT 23
Finished Oct 11 12:52:55 PM PDT 23
Peak memory 205576 kb
Host smart-29bc5928-4fe0-499c-a82c-1bcfd1ba669b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472890302 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.2472890302
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.894626137
Short name T405
Test name
Test status
Simulation time 36525862 ps
CPU time 0.98 seconds
Started Oct 11 12:52:54 PM PDT 23
Finished Oct 11 12:52:56 PM PDT 23
Peak memory 205804 kb
Host smart-b167494d-d8ad-44b0-b77c-76865910a23b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894626137 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_out
standing.894626137
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.2219010770
Short name T361
Test name
Test status
Simulation time 237252305 ps
CPU time 3.33 seconds
Started Oct 11 12:52:58 PM PDT 23
Finished Oct 11 12:53:02 PM PDT 23
Peak memory 213884 kb
Host smart-453e1649-3cb8-4504-91ff-35165219d8a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219010770 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.2219010770
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2391377902
Short name T349
Test name
Test status
Simulation time 340942747 ps
CPU time 2.39 seconds
Started Oct 11 12:52:50 PM PDT 23
Finished Oct 11 12:52:53 PM PDT 23
Peak memory 205740 kb
Host smart-ac2d6f82-75b8-40e6-a9ca-c81b36edb586
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391377902 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.2391377902
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3675561224
Short name T145
Test name
Test status
Simulation time 23704982 ps
CPU time 1.15 seconds
Started Oct 11 12:52:37 PM PDT 23
Finished Oct 11 12:52:39 PM PDT 23
Peak memory 214052 kb
Host smart-9f6bcc30-98ea-4a9f-ba67-b3ff211dafa1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675561224 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.3675561224
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.413772144
Short name T213
Test name
Test status
Simulation time 97720123 ps
CPU time 0.82 seconds
Started Oct 11 12:53:00 PM PDT 23
Finished Oct 11 12:53:02 PM PDT 23
Peak memory 205604 kb
Host smart-9a710b10-173a-47d4-afca-a269c6ea4366
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413772144 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.413772144
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.1880710563
Short name T342
Test name
Test status
Simulation time 16749200 ps
CPU time 0.87 seconds
Started Oct 11 12:52:22 PM PDT 23
Finished Oct 11 12:52:23 PM PDT 23
Peak memory 205576 kb
Host smart-02dc7370-0881-4b12-b9cd-13d8069994b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880710563 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.1880710563
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2635926097
Short name T397
Test name
Test status
Simulation time 37422229 ps
CPU time 1.07 seconds
Started Oct 11 12:52:57 PM PDT 23
Finished Oct 11 12:52:59 PM PDT 23
Peak memory 205728 kb
Host smart-e241f603-56d7-45bd-af61-9dff9ec52c63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635926097 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.2635926097
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.3159359115
Short name T399
Test name
Test status
Simulation time 192596890 ps
CPU time 3.51 seconds
Started Oct 11 12:52:58 PM PDT 23
Finished Oct 11 12:53:02 PM PDT 23
Peak memory 214048 kb
Host smart-4524eefb-1e5a-49ae-9590-b846b5fd2300
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159359115 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.3159359115
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3848901445
Short name T394
Test name
Test status
Simulation time 201832987 ps
CPU time 1.44 seconds
Started Oct 11 12:52:43 PM PDT 23
Finished Oct 11 12:52:45 PM PDT 23
Peak memory 205804 kb
Host smart-be8b7276-b5ab-40a4-b27e-6a5513ff05a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848901445 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.3848901445
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.856726591
Short name T228
Test name
Test status
Simulation time 61979506 ps
CPU time 1.31 seconds
Started Oct 11 12:52:57 PM PDT 23
Finished Oct 11 12:52:59 PM PDT 23
Peak memory 214128 kb
Host smart-54e3d3de-8199-43fc-9338-e51135586d60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856726591 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.856726591
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.3101931454
Short name T375
Test name
Test status
Simulation time 36860897 ps
CPU time 0.83 seconds
Started Oct 11 12:52:44 PM PDT 23
Finished Oct 11 12:52:45 PM PDT 23
Peak memory 205740 kb
Host smart-e9cb15c6-5d4a-4f7f-bf4a-b71f1764da65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101931454 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.3101931454
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.301713057
Short name T396
Test name
Test status
Simulation time 16560260 ps
CPU time 0.91 seconds
Started Oct 11 12:52:20 PM PDT 23
Finished Oct 11 12:52:21 PM PDT 23
Peak memory 205608 kb
Host smart-56e8011d-2806-47c7-87bd-9c016007edec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301713057 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.301713057
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2929880164
Short name T431
Test name
Test status
Simulation time 14588643 ps
CPU time 0.91 seconds
Started Oct 11 12:52:41 PM PDT 23
Finished Oct 11 12:52:43 PM PDT 23
Peak memory 205780 kb
Host smart-a1b62717-c162-4aee-8d7f-a8c2e56fec35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929880164 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.2929880164
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.3151750998
Short name T429
Test name
Test status
Simulation time 426312281 ps
CPU time 3.81 seconds
Started Oct 11 12:52:35 PM PDT 23
Finished Oct 11 12:52:40 PM PDT 23
Peak memory 214168 kb
Host smart-dcf52d32-db9d-40af-8717-957063db39a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151750998 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.3151750998
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.104856288
Short name T380
Test name
Test status
Simulation time 36814668 ps
CPU time 0.99 seconds
Started Oct 11 12:52:04 PM PDT 23
Finished Oct 11 12:52:05 PM PDT 23
Peak memory 205880 kb
Host smart-a8af688f-25c2-40d3-b4ca-e182c6e06220
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104856288 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.104856288
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.4273222684
Short name T218
Test name
Test status
Simulation time 23379882 ps
CPU time 0.83 seconds
Started Oct 11 12:52:15 PM PDT 23
Finished Oct 11 12:52:16 PM PDT 23
Peak memory 205656 kb
Host smart-03ff8d5b-2bc0-47a4-b264-88027d057edb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273222684 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.4273222684
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.1066609428
Short name T355
Test name
Test status
Simulation time 73412880 ps
CPU time 0.85 seconds
Started Oct 11 12:52:19 PM PDT 23
Finished Oct 11 12:52:26 PM PDT 23
Peak memory 205688 kb
Host smart-184a148d-eb96-4d97-ae31-a13f69294e57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066609428 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.1066609428
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.635709258
Short name T359
Test name
Test status
Simulation time 17386737 ps
CPU time 1.09 seconds
Started Oct 11 12:51:24 PM PDT 23
Finished Oct 11 12:51:26 PM PDT 23
Peak memory 205660 kb
Host smart-848fce6f-2e27-4bb9-8f49-9c9d2d81f468
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635709258 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_ou
tstanding.635709258
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.305376282
Short name T354
Test name
Test status
Simulation time 244014055 ps
CPU time 2.59 seconds
Started Oct 11 12:53:01 PM PDT 23
Finished Oct 11 12:53:04 PM PDT 23
Peak memory 214028 kb
Host smart-8746ba03-64dd-40a2-83c9-e6bb85dcc8ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305376282 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.305376282
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1853692654
Short name T276
Test name
Test status
Simulation time 84030127 ps
CPU time 2.24 seconds
Started Oct 11 12:52:53 PM PDT 23
Finished Oct 11 12:52:56 PM PDT 23
Peak memory 205832 kb
Host smart-94d36180-54a0-4c19-a2c2-c2efcef03f77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853692654 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.1853692654
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.910822354
Short name T219
Test name
Test status
Simulation time 48889313 ps
CPU time 1.21 seconds
Started Oct 11 12:51:26 PM PDT 23
Finished Oct 11 12:51:28 PM PDT 23
Peak memory 214072 kb
Host smart-591c8ac4-fe39-4bd0-9e1b-ccb39091119a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910822354 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.910822354
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.507040901
Short name T369
Test name
Test status
Simulation time 61864883 ps
CPU time 0.84 seconds
Started Oct 11 12:51:30 PM PDT 23
Finished Oct 11 12:51:31 PM PDT 23
Peak memory 205692 kb
Host smart-ff05c2a9-511a-4e86-8b52-a79313366965
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507040901 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.507040901
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.247354668
Short name T352
Test name
Test status
Simulation time 65996812 ps
CPU time 0.73 seconds
Started Oct 11 12:52:09 PM PDT 23
Finished Oct 11 12:52:10 PM PDT 23
Peak memory 205440 kb
Host smart-de94935a-7aa6-4084-a4ff-927b4e3cd22f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247354668 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.247354668
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.280113388
Short name T384
Test name
Test status
Simulation time 53624483 ps
CPU time 1.45 seconds
Started Oct 11 12:52:44 PM PDT 23
Finished Oct 11 12:52:48 PM PDT 23
Peak memory 205840 kb
Host smart-0b257b34-3625-4016-b5ec-6564fb520a27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280113388 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_ou
tstanding.280113388
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.1604581062
Short name T376
Test name
Test status
Simulation time 77111745 ps
CPU time 2.49 seconds
Started Oct 11 12:51:43 PM PDT 23
Finished Oct 11 12:51:46 PM PDT 23
Peak memory 213996 kb
Host smart-ea9fc1c2-3960-4f4a-9bca-9635f442ce86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604581062 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.1604581062
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2489951059
Short name T423
Test name
Test status
Simulation time 174019857 ps
CPU time 1.5 seconds
Started Oct 11 12:52:13 PM PDT 23
Finished Oct 11 12:52:15 PM PDT 23
Peak memory 205772 kb
Host smart-c67fa241-4b1e-4d81-9fe7-36e8744020dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489951059 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.2489951059
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2091509152
Short name T216
Test name
Test status
Simulation time 90417226 ps
CPU time 1.06 seconds
Started Oct 11 12:51:39 PM PDT 23
Finished Oct 11 12:51:41 PM PDT 23
Peak memory 205712 kb
Host smart-83bab08e-af19-440d-acee-d4ffc91c2ebf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091509152 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2091509152
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.911101327
Short name T418
Test name
Test status
Simulation time 43061213 ps
CPU time 0.89 seconds
Started Oct 11 12:51:33 PM PDT 23
Finished Oct 11 12:51:34 PM PDT 23
Peak memory 205772 kb
Host smart-74cd32f1-ddbf-4e00-a537-f97b05f6eea7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911101327 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.911101327
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.72344960
Short name T435
Test name
Test status
Simulation time 14448635 ps
CPU time 0.83 seconds
Started Oct 11 12:51:40 PM PDT 23
Finished Oct 11 12:51:41 PM PDT 23
Peak memory 205676 kb
Host smart-94e4595c-8cd6-4e00-8895-fc094a58e980
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72344960 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.72344960
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.309197330
Short name T425
Test name
Test status
Simulation time 61090018 ps
CPU time 1.04 seconds
Started Oct 11 12:52:21 PM PDT 23
Finished Oct 11 12:52:23 PM PDT 23
Peak memory 205712 kb
Host smart-5be9f3e8-60ab-498f-aa24-d159eb09baea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309197330 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_ou
tstanding.309197330
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.3255350097
Short name T365
Test name
Test status
Simulation time 127960851 ps
CPU time 2.32 seconds
Started Oct 11 12:51:26 PM PDT 23
Finished Oct 11 12:51:29 PM PDT 23
Peak memory 213988 kb
Host smart-41f97889-fac6-4c5a-b926-6c3753c640b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255350097 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.3255350097
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3727247822
Short name T428
Test name
Test status
Simulation time 57681734 ps
CPU time 1.67 seconds
Started Oct 11 12:52:21 PM PDT 23
Finished Oct 11 12:52:24 PM PDT 23
Peak memory 205872 kb
Host smart-138a8088-d5e3-4098-9182-f2d68f477970
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727247822 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.3727247822
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.3397980826
Short name T404
Test name
Test status
Simulation time 111209917 ps
CPU time 1.15 seconds
Started Oct 11 12:53:06 PM PDT 23
Finished Oct 11 12:53:07 PM PDT 23
Peak memory 214040 kb
Host smart-3f3c0e1f-907a-49d8-b03b-410c0e13c895
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397980826 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.3397980826
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.993303632
Short name T236
Test name
Test status
Simulation time 34974801 ps
CPU time 0.77 seconds
Started Oct 11 12:52:57 PM PDT 23
Finished Oct 11 12:52:58 PM PDT 23
Peak memory 205644 kb
Host smart-9f538313-854f-475a-9854-d2217e6fb6ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993303632 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.993303632
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.3757628220
Short name T347
Test name
Test status
Simulation time 31121382 ps
CPU time 0.76 seconds
Started Oct 11 12:52:38 PM PDT 23
Finished Oct 11 12:52:45 PM PDT 23
Peak memory 205488 kb
Host smart-c21bdef6-7c79-49c3-a339-b42986ab16a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757628220 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3757628220
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3792138809
Short name T393
Test name
Test status
Simulation time 61474563 ps
CPU time 1.07 seconds
Started Oct 11 12:52:18 PM PDT 23
Finished Oct 11 12:52:20 PM PDT 23
Peak memory 205760 kb
Host smart-49cc5481-9cfb-49fc-a577-d1ae6b9ef8c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792138809 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.3792138809
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.2980348930
Short name T358
Test name
Test status
Simulation time 39117118 ps
CPU time 1.69 seconds
Started Oct 11 12:52:42 PM PDT 23
Finished Oct 11 12:52:44 PM PDT 23
Peak memory 214020 kb
Host smart-dd42d590-094f-45e5-a718-dd7ac22b384f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980348930 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.2980348930
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1438356419
Short name T158
Test name
Test status
Simulation time 83971964 ps
CPU time 1.48 seconds
Started Oct 11 12:52:16 PM PDT 23
Finished Oct 11 12:52:17 PM PDT 23
Peak memory 205720 kb
Host smart-ff72384c-58ec-4520-9c62-cb1c189ca0f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438356419 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.1438356419
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1452785695
Short name T234
Test name
Test status
Simulation time 24808810 ps
CPU time 1.52 seconds
Started Oct 11 12:52:57 PM PDT 23
Finished Oct 11 12:53:09 PM PDT 23
Peak memory 214040 kb
Host smart-c19ff875-4a04-46dc-a027-6a05d1065dca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452785695 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.1452785695
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.3888409182
Short name T377
Test name
Test status
Simulation time 47820972 ps
CPU time 0.87 seconds
Started Oct 11 12:52:43 PM PDT 23
Finished Oct 11 12:52:47 PM PDT 23
Peak memory 205788 kb
Host smart-d6328347-8c0f-434a-9834-e3d191077c58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888409182 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.3888409182
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.2376851777
Short name T351
Test name
Test status
Simulation time 27432986 ps
CPU time 0.82 seconds
Started Oct 11 12:52:27 PM PDT 23
Finished Oct 11 12:52:29 PM PDT 23
Peak memory 205664 kb
Host smart-9adff224-aeba-4f1f-ba3d-c6f8e63bc85b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376851777 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.2376851777
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1459115127
Short name T235
Test name
Test status
Simulation time 13828171 ps
CPU time 0.9 seconds
Started Oct 11 12:52:48 PM PDT 23
Finished Oct 11 12:52:50 PM PDT 23
Peak memory 205684 kb
Host smart-1b74d8c0-2ff9-44ad-8eee-a758c09d4ace
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459115127 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.1459115127
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.1379036089
Short name T390
Test name
Test status
Simulation time 22683779 ps
CPU time 1.6 seconds
Started Oct 11 12:52:56 PM PDT 23
Finished Oct 11 12:52:58 PM PDT 23
Peak memory 214272 kb
Host smart-ba340817-8b63-4367-8724-e0bf34cb7f6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379036089 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.1379036089
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.139988933
Short name T273
Test name
Test status
Simulation time 154888262 ps
CPU time 1.48 seconds
Started Oct 11 12:53:03 PM PDT 23
Finished Oct 11 12:53:05 PM PDT 23
Peak memory 205688 kb
Host smart-b2216045-9996-476d-9960-f80c6d54323a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139988933 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.139988933
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2450611367
Short name T440
Test name
Test status
Simulation time 15994571 ps
CPU time 1.15 seconds
Started Oct 11 12:53:10 PM PDT 23
Finished Oct 11 12:53:12 PM PDT 23
Peak memory 214060 kb
Host smart-63319496-4dcd-4127-bf67-cfdf9fec74ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450611367 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2450611367
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.3103533747
Short name T214
Test name
Test status
Simulation time 28608923 ps
CPU time 0.92 seconds
Started Oct 11 12:52:28 PM PDT 23
Finished Oct 11 12:52:30 PM PDT 23
Peak memory 205812 kb
Host smart-4b31a421-7a39-4c21-888f-4b737210fa8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103533747 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.3103533747
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.2858976702
Short name T419
Test name
Test status
Simulation time 49798365 ps
CPU time 0.8 seconds
Started Oct 11 12:52:44 PM PDT 23
Finished Oct 11 12:52:50 PM PDT 23
Peak memory 205616 kb
Host smart-506bcc9c-1419-47a0-960a-daa9d4a43196
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858976702 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.2858976702
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3613855297
Short name T436
Test name
Test status
Simulation time 43720387 ps
CPU time 1.13 seconds
Started Oct 11 12:53:19 PM PDT 23
Finished Oct 11 12:53:26 PM PDT 23
Peak memory 205992 kb
Host smart-8bdac72a-bf88-461f-a097-8e6efb058f04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613855297 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.3613855297
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.2532039245
Short name T438
Test name
Test status
Simulation time 111280185 ps
CPU time 2.13 seconds
Started Oct 11 12:53:07 PM PDT 23
Finished Oct 11 12:53:10 PM PDT 23
Peak memory 213932 kb
Host smart-e758e27d-a25e-4aae-b1d4-56a5e811ba34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532039245 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.2532039245
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2941083583
Short name T272
Test name
Test status
Simulation time 84313586 ps
CPU time 2.19 seconds
Started Oct 11 12:52:49 PM PDT 23
Finished Oct 11 12:52:54 PM PDT 23
Peak memory 205752 kb
Host smart-7834690a-d820-4a28-8cc7-b6ab00d0680c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941083583 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.2941083583
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3743112283
Short name T379
Test name
Test status
Simulation time 73240543 ps
CPU time 1.08 seconds
Started Oct 11 12:52:45 PM PDT 23
Finished Oct 11 12:52:47 PM PDT 23
Peak memory 214060 kb
Host smart-44e1c603-74b8-4f6e-89dd-2ac0a6e5b48f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743112283 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.3743112283
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.2448027888
Short name T215
Test name
Test status
Simulation time 34803876 ps
CPU time 0.8 seconds
Started Oct 11 12:52:23 PM PDT 23
Finished Oct 11 12:52:24 PM PDT 23
Peak memory 205576 kb
Host smart-34b7e72d-c52c-4c0f-b645-333ee261191a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448027888 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.2448027888
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.3344350374
Short name T208
Test name
Test status
Simulation time 11505533 ps
CPU time 0.84 seconds
Started Oct 11 12:53:10 PM PDT 23
Finished Oct 11 12:53:11 PM PDT 23
Peak memory 205640 kb
Host smart-29d80a31-e1b7-46b6-bc89-2b1f26d282aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344350374 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.3344350374
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1408590221
Short name T442
Test name
Test status
Simulation time 53909122 ps
CPU time 1.22 seconds
Started Oct 11 12:52:28 PM PDT 23
Finished Oct 11 12:52:29 PM PDT 23
Peak memory 205776 kb
Host smart-57290934-926b-4ab9-b2c7-9988d80613a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408590221 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.1408590221
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.973374560
Short name T392
Test name
Test status
Simulation time 227571611 ps
CPU time 2.69 seconds
Started Oct 11 12:52:25 PM PDT 23
Finished Oct 11 12:52:28 PM PDT 23
Peak memory 213992 kb
Host smart-25253927-c537-4433-aac6-32722ed270bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973374560 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.973374560
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1612080301
Short name T371
Test name
Test status
Simulation time 244772892 ps
CPU time 2.02 seconds
Started Oct 11 12:53:03 PM PDT 23
Finished Oct 11 12:53:06 PM PDT 23
Peak memory 205768 kb
Host smart-36845b1d-6c33-4030-be68-27998bc1d2b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612080301 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1612080301
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1544126340
Short name T401
Test name
Test status
Simulation time 26289117 ps
CPU time 1.17 seconds
Started Oct 11 12:51:28 PM PDT 23
Finished Oct 11 12:51:30 PM PDT 23
Peak memory 214228 kb
Host smart-238286e0-90e6-4fa5-a80f-c10b564d17c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544126340 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.1544126340
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.2410597597
Short name T363
Test name
Test status
Simulation time 40827728 ps
CPU time 0.84 seconds
Started Oct 11 12:52:10 PM PDT 23
Finished Oct 11 12:52:12 PM PDT 23
Peak memory 205800 kb
Host smart-6f3ee370-3523-4e03-ac6d-e0cabc7d9d8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410597597 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2410597597
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.2423703694
Short name T434
Test name
Test status
Simulation time 13027805 ps
CPU time 0.8 seconds
Started Oct 11 12:52:47 PM PDT 23
Finished Oct 11 12:52:53 PM PDT 23
Peak memory 205576 kb
Host smart-68355e56-2bee-4441-b2e3-685fa93a0af1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423703694 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2423703694
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1256432716
Short name T123
Test name
Test status
Simulation time 22182027 ps
CPU time 0.89 seconds
Started Oct 11 12:52:17 PM PDT 23
Finished Oct 11 12:52:18 PM PDT 23
Peak memory 205776 kb
Host smart-0ba0c17e-149b-4c31-86df-cb2f6b0b7be9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256432716 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.1256432716
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.4005587836
Short name T407
Test name
Test status
Simulation time 70294994 ps
CPU time 2.34 seconds
Started Oct 11 12:52:43 PM PDT 23
Finished Oct 11 12:52:46 PM PDT 23
Peak memory 214152 kb
Host smart-5c43b503-9bf9-411a-8803-8e26c225c8ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005587836 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.4005587836
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1904763920
Short name T151
Test name
Test status
Simulation time 114791502 ps
CPU time 1.52 seconds
Started Oct 11 12:52:50 PM PDT 23
Finished Oct 11 12:52:52 PM PDT 23
Peak memory 205736 kb
Host smart-c4e23077-9809-46b3-85e6-cd05c4fad95f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904763920 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1904763920
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.744721730
Short name T143
Test name
Test status
Simulation time 35963871 ps
CPU time 1.41 seconds
Started Oct 11 12:51:24 PM PDT 23
Finished Oct 11 12:51:26 PM PDT 23
Peak memory 205864 kb
Host smart-831b652a-f8a9-461b-abbd-ceb27ae71450
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744721730 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.744721730
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3376089941
Short name T211
Test name
Test status
Simulation time 219434204 ps
CPU time 3.28 seconds
Started Oct 11 12:51:18 PM PDT 23
Finished Oct 11 12:51:23 PM PDT 23
Peak memory 205828 kb
Host smart-d79183a7-c018-46be-a65d-3533facb68bc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376089941 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.3376089941
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2089185059
Short name T146
Test name
Test status
Simulation time 16464781 ps
CPU time 0.9 seconds
Started Oct 11 12:51:26 PM PDT 23
Finished Oct 11 12:51:27 PM PDT 23
Peak memory 205708 kb
Host smart-b3412573-d00a-4238-a9b9-55c026497fb2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089185059 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.2089185059
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2562781357
Short name T356
Test name
Test status
Simulation time 21187714 ps
CPU time 1.38 seconds
Started Oct 11 12:52:23 PM PDT 23
Finished Oct 11 12:52:25 PM PDT 23
Peak memory 213976 kb
Host smart-85f33da9-3790-4661-943b-f1ff1569243e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562781357 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.2562781357
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.569109004
Short name T411
Test name
Test status
Simulation time 12771284 ps
CPU time 0.91 seconds
Started Oct 11 12:51:35 PM PDT 23
Finished Oct 11 12:51:36 PM PDT 23
Peak memory 206028 kb
Host smart-61d37bef-b6fc-4416-9af0-ebf2e204cca0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569109004 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.569109004
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.616834498
Short name T391
Test name
Test status
Simulation time 23931981 ps
CPU time 0.8 seconds
Started Oct 11 12:52:56 PM PDT 23
Finished Oct 11 12:52:57 PM PDT 23
Peak memory 205656 kb
Host smart-6c142ebb-ddfe-45bd-b52d-9a30ad957f4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616834498 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.616834498
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1005868660
Short name T221
Test name
Test status
Simulation time 45796977 ps
CPU time 0.95 seconds
Started Oct 11 12:51:20 PM PDT 23
Finished Oct 11 12:51:21 PM PDT 23
Peak memory 205888 kb
Host smart-f4442ec9-a9b4-4d38-9fcb-1aef4ae09742
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005868660 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.1005868660
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.2729306270
Short name T439
Test name
Test status
Simulation time 654637040 ps
CPU time 1.8 seconds
Started Oct 11 12:52:35 PM PDT 23
Finished Oct 11 12:52:38 PM PDT 23
Peak memory 213892 kb
Host smart-ac220476-cad8-4839-a74d-152840126d0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729306270 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.2729306270
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3069538423
Short name T409
Test name
Test status
Simulation time 48806509 ps
CPU time 1.54 seconds
Started Oct 11 12:51:20 PM PDT 23
Finished Oct 11 12:51:22 PM PDT 23
Peak memory 205884 kb
Host smart-f8aab7dd-5052-426b-a640-93c4d12482f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069538423 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.3069538423
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.902564915
Short name T382
Test name
Test status
Simulation time 14008662 ps
CPU time 0.84 seconds
Started Oct 11 12:52:05 PM PDT 23
Finished Oct 11 12:52:07 PM PDT 23
Peak memory 205684 kb
Host smart-109b21f4-2856-4bc9-80f5-149508388520
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902564915 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.902564915
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.1604658686
Short name T364
Test name
Test status
Simulation time 23119109 ps
CPU time 0.81 seconds
Started Oct 11 12:51:47 PM PDT 23
Finished Oct 11 12:51:48 PM PDT 23
Peak memory 205640 kb
Host smart-97343e5d-1eb6-415e-a91f-df55c5820f44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604658686 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.1604658686
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.1380715434
Short name T447
Test name
Test status
Simulation time 36565763 ps
CPU time 0.77 seconds
Started Oct 11 12:51:34 PM PDT 23
Finished Oct 11 12:51:36 PM PDT 23
Peak memory 205572 kb
Host smart-ae3c27e5-d742-44b9-aad6-7a3ac2f62604
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380715434 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.1380715434
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.4168413232
Short name T406
Test name
Test status
Simulation time 13738807 ps
CPU time 0.85 seconds
Started Oct 11 12:51:45 PM PDT 23
Finished Oct 11 12:51:47 PM PDT 23
Peak memory 205604 kb
Host smart-ecc4e1e7-0e38-46dc-ae5c-067639900697
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168413232 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.4168413232
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.2891273074
Short name T337
Test name
Test status
Simulation time 12806959 ps
CPU time 0.87 seconds
Started Oct 11 12:52:22 PM PDT 23
Finished Oct 11 12:52:24 PM PDT 23
Peak memory 205664 kb
Host smart-8b169ed9-9e1c-45b7-9524-2c2421ffe524
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891273074 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.2891273074
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.3065163107
Short name T414
Test name
Test status
Simulation time 13129067 ps
CPU time 0.79 seconds
Started Oct 11 12:51:42 PM PDT 23
Finished Oct 11 12:51:44 PM PDT 23
Peak memory 205600 kb
Host smart-f530b428-2da8-45af-be8f-209ec9589fdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065163107 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3065163107
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.801087217
Short name T400
Test name
Test status
Simulation time 19363348 ps
CPU time 0.78 seconds
Started Oct 11 12:52:42 PM PDT 23
Finished Oct 11 12:52:43 PM PDT 23
Peak memory 205616 kb
Host smart-800616b2-d6a9-49ec-8987-2c13928a471f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801087217 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.801087217
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.162373097
Short name T159
Test name
Test status
Simulation time 21019435 ps
CPU time 0.77 seconds
Started Oct 11 12:52:34 PM PDT 23
Finished Oct 11 12:52:35 PM PDT 23
Peak memory 205612 kb
Host smart-27ab33b5-3e6f-4bde-a4d0-1106edc61d98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162373097 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.162373097
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.2409634139
Short name T207
Test name
Test status
Simulation time 32411564 ps
CPU time 0.77 seconds
Started Oct 11 12:52:46 PM PDT 23
Finished Oct 11 12:52:47 PM PDT 23
Peak memory 205608 kb
Host smart-df2eb094-ea46-4e48-82c6-abc8b7e7aceb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409634139 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2409634139
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.412692892
Short name T360
Test name
Test status
Simulation time 14408240 ps
CPU time 0.87 seconds
Started Oct 11 12:52:19 PM PDT 23
Finished Oct 11 12:52:20 PM PDT 23
Peak memory 205656 kb
Host smart-95bfc3f3-fb08-4293-9c9e-42e9d89df806
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412692892 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.412692892
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.755792490
Short name T227
Test name
Test status
Simulation time 176112693 ps
CPU time 1.17 seconds
Started Oct 11 12:52:17 PM PDT 23
Finished Oct 11 12:52:19 PM PDT 23
Peak memory 205764 kb
Host smart-b863113c-fa80-4dfe-89fc-c51b443f1187
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755792490 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.755792490
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3869454703
Short name T422
Test name
Test status
Simulation time 997070324 ps
CPU time 6.29 seconds
Started Oct 11 12:52:26 PM PDT 23
Finished Oct 11 12:52:33 PM PDT 23
Peak memory 205780 kb
Host smart-534ef510-7c18-4d88-b6be-d4556b30430d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869454703 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.3869454703
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2313556601
Short name T415
Test name
Test status
Simulation time 18214584 ps
CPU time 0.84 seconds
Started Oct 11 12:51:21 PM PDT 23
Finished Oct 11 12:51:22 PM PDT 23
Peak memory 205684 kb
Host smart-2662f4d2-59c4-44cc-8fd0-df94ab783d63
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313556601 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2313556601
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.892693274
Short name T368
Test name
Test status
Simulation time 28185619 ps
CPU time 1.62 seconds
Started Oct 11 12:51:24 PM PDT 23
Finished Oct 11 12:51:26 PM PDT 23
Peak memory 214056 kb
Host smart-5cc01c63-c9e0-43de-9213-e53d414d2d96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892693274 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.892693274
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.3852417059
Short name T403
Test name
Test status
Simulation time 20361629 ps
CPU time 0.81 seconds
Started Oct 11 12:51:26 PM PDT 23
Finished Oct 11 12:51:27 PM PDT 23
Peak memory 205644 kb
Host smart-8e15f486-7649-4d49-8f8c-c1bb696b252f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852417059 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.3852417059
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.1791501445
Short name T387
Test name
Test status
Simulation time 24553816 ps
CPU time 0.75 seconds
Started Oct 11 12:52:15 PM PDT 23
Finished Oct 11 12:52:17 PM PDT 23
Peak memory 205596 kb
Host smart-423ee47c-9e32-4a21-975f-28faf9d6f990
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791501445 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.1791501445
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2670269728
Short name T426
Test name
Test status
Simulation time 219587323 ps
CPU time 1.08 seconds
Started Oct 11 12:52:28 PM PDT 23
Finished Oct 11 12:52:29 PM PDT 23
Peak memory 205784 kb
Host smart-0b67e9b7-3a4e-4aa1-bf99-ee4f56d728d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670269728 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.2670269728
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.1938329219
Short name T437
Test name
Test status
Simulation time 407080388 ps
CPU time 3.49 seconds
Started Oct 11 12:51:20 PM PDT 23
Finished Oct 11 12:51:24 PM PDT 23
Peak memory 214024 kb
Host smart-64c7e7b5-fd70-4717-93f4-3a8c241b8443
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938329219 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.1938329219
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.326022231
Short name T416
Test name
Test status
Simulation time 169601277 ps
CPU time 1.43 seconds
Started Oct 11 12:51:08 PM PDT 23
Finished Oct 11 12:51:10 PM PDT 23
Peak memory 205704 kb
Host smart-f557df65-833d-422e-87e7-e60b2ee56b76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326022231 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.326022231
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.511568005
Short name T338
Test name
Test status
Simulation time 36576401 ps
CPU time 0.79 seconds
Started Oct 11 12:52:39 PM PDT 23
Finished Oct 11 12:52:40 PM PDT 23
Peak memory 205608 kb
Host smart-2bba5bf8-2f13-48c1-9449-2d002a5299a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511568005 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.511568005
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.2175403485
Short name T421
Test name
Test status
Simulation time 37070978 ps
CPU time 0.75 seconds
Started Oct 11 12:52:47 PM PDT 23
Finished Oct 11 12:52:49 PM PDT 23
Peak memory 205668 kb
Host smart-7cb3f331-dea7-4933-a07e-faa0e3d145a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175403485 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.2175403485
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.2280404527
Short name T367
Test name
Test status
Simulation time 14090937 ps
CPU time 0.82 seconds
Started Oct 11 12:53:01 PM PDT 23
Finished Oct 11 12:53:02 PM PDT 23
Peak memory 205684 kb
Host smart-25c9c256-e300-482c-a025-58cc1cc8bb6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280404527 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2280404527
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.797134092
Short name T343
Test name
Test status
Simulation time 29685063 ps
CPU time 0.89 seconds
Started Oct 11 12:52:44 PM PDT 23
Finished Oct 11 12:52:46 PM PDT 23
Peak memory 205608 kb
Host smart-cd22c9fc-9ab6-4c84-8ebe-8488c0b20175
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797134092 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.797134092
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.424347080
Short name T340
Test name
Test status
Simulation time 15709260 ps
CPU time 0.86 seconds
Started Oct 11 12:52:45 PM PDT 23
Finished Oct 11 12:52:46 PM PDT 23
Peak memory 205620 kb
Host smart-744d1927-77f0-4297-a185-85b5884f570b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424347080 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.424347080
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.2069706068
Short name T430
Test name
Test status
Simulation time 71204648 ps
CPU time 0.76 seconds
Started Oct 11 12:53:20 PM PDT 23
Finished Oct 11 12:53:21 PM PDT 23
Peak memory 205544 kb
Host smart-f8390ee3-bc0c-4788-96dd-b7b1f79961d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069706068 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.2069706068
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.3421910482
Short name T366
Test name
Test status
Simulation time 12650675 ps
CPU time 0.88 seconds
Started Oct 11 12:52:44 PM PDT 23
Finished Oct 11 12:52:45 PM PDT 23
Peak memory 205568 kb
Host smart-24c2d32d-739b-49c9-9121-8d6951e89acf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421910482 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3421910482
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.1982614775
Short name T339
Test name
Test status
Simulation time 16435113 ps
CPU time 0.81 seconds
Started Oct 11 12:53:22 PM PDT 23
Finished Oct 11 12:53:35 PM PDT 23
Peak memory 205688 kb
Host smart-08653f72-2cd5-45ba-9184-24d9c026ef37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982614775 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.1982614775
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.36974350
Short name T441
Test name
Test status
Simulation time 17299757 ps
CPU time 0.87 seconds
Started Oct 11 12:52:28 PM PDT 23
Finished Oct 11 12:52:29 PM PDT 23
Peak memory 205676 kb
Host smart-04b8df3c-acbc-4cd6-a6e0-8541f0ef5ca6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36974350 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.36974350
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.137281895
Short name T372
Test name
Test status
Simulation time 51767156 ps
CPU time 0.84 seconds
Started Oct 11 12:52:18 PM PDT 23
Finished Oct 11 12:52:19 PM PDT 23
Peak memory 205536 kb
Host smart-1b677261-9fa1-4630-ade6-bcbbe0868659
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137281895 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.137281895
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.474090006
Short name T206
Test name
Test status
Simulation time 73486602 ps
CPU time 1.33 seconds
Started Oct 11 12:52:49 PM PDT 23
Finished Oct 11 12:52:51 PM PDT 23
Peak memory 205796 kb
Host smart-b1ecd41c-cafd-46ea-a6d8-27d9d1b67028
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474090006 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.474090006
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3604092093
Short name T223
Test name
Test status
Simulation time 512878141 ps
CPU time 6.31 seconds
Started Oct 11 12:52:44 PM PDT 23
Finished Oct 11 12:52:51 PM PDT 23
Peak memory 205720 kb
Host smart-9c266a22-43e0-4c68-86f2-73d01b22e0d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604092093 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.3604092093
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3902313247
Short name T224
Test name
Test status
Simulation time 25059324 ps
CPU time 0.83 seconds
Started Oct 11 12:52:20 PM PDT 23
Finished Oct 11 12:52:22 PM PDT 23
Peak memory 205692 kb
Host smart-da900feb-9867-4a9a-8b0b-6f69d6972cde
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902313247 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3902313247
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.879760110
Short name T350
Test name
Test status
Simulation time 19016571 ps
CPU time 1.34 seconds
Started Oct 11 12:52:07 PM PDT 23
Finished Oct 11 12:52:09 PM PDT 23
Peak memory 214172 kb
Host smart-896e0223-e8c4-492c-8886-57c40cf7e446
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879760110 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.879760110
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.1623597922
Short name T230
Test name
Test status
Simulation time 126019753 ps
CPU time 0.81 seconds
Started Oct 11 12:52:13 PM PDT 23
Finished Oct 11 12:52:14 PM PDT 23
Peak memory 205644 kb
Host smart-ffacbcb8-5042-42b5-a17d-ec323380e5ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623597922 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.1623597922
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.976763488
Short name T433
Test name
Test status
Simulation time 49686012 ps
CPU time 0.8 seconds
Started Oct 11 12:52:42 PM PDT 23
Finished Oct 11 12:52:43 PM PDT 23
Peak memory 205572 kb
Host smart-8068b74c-049e-4c70-95ac-ae248326f975
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976763488 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.976763488
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2771476462
Short name T229
Test name
Test status
Simulation time 37729331 ps
CPU time 0.99 seconds
Started Oct 11 12:53:00 PM PDT 23
Finished Oct 11 12:53:02 PM PDT 23
Peak memory 205800 kb
Host smart-873ebbb9-f201-46dd-8e47-4ee2e6e01033
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771476462 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.2771476462
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.2305851146
Short name T149
Test name
Test status
Simulation time 120500253 ps
CPU time 1.88 seconds
Started Oct 11 12:52:25 PM PDT 23
Finished Oct 11 12:52:28 PM PDT 23
Peak memory 213932 kb
Host smart-1e5ebad0-51fd-4c2c-a6c6-53fe1f85cced
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305851146 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.2305851146
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.138190433
Short name T124
Test name
Test status
Simulation time 124884448 ps
CPU time 2.76 seconds
Started Oct 11 12:52:06 PM PDT 23
Finished Oct 11 12:52:09 PM PDT 23
Peak memory 205732 kb
Host smart-7ea625a0-d627-494c-92ee-c8599a923f31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138190433 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.138190433
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.1495899507
Short name T412
Test name
Test status
Simulation time 121689393 ps
CPU time 0.88 seconds
Started Oct 11 12:52:45 PM PDT 23
Finished Oct 11 12:52:47 PM PDT 23
Peak memory 205600 kb
Host smart-53505774-c4bd-4b84-895f-1078cd16ef8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495899507 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.1495899507
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.1077134937
Short name T336
Test name
Test status
Simulation time 30524454 ps
CPU time 0.76 seconds
Started Oct 11 12:53:03 PM PDT 23
Finished Oct 11 12:53:04 PM PDT 23
Peak memory 205440 kb
Host smart-ae973043-9818-413e-967e-bcb2717ef0ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077134937 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1077134937
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.301260366
Short name T386
Test name
Test status
Simulation time 13164306 ps
CPU time 0.82 seconds
Started Oct 11 12:53:15 PM PDT 23
Finished Oct 11 12:53:16 PM PDT 23
Peak memory 205636 kb
Host smart-12beb4f8-522a-4b6e-866c-18b8437b5654
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301260366 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.301260366
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.474937782
Short name T370
Test name
Test status
Simulation time 46474113 ps
CPU time 0.8 seconds
Started Oct 11 12:52:48 PM PDT 23
Finished Oct 11 12:52:49 PM PDT 23
Peak memory 205668 kb
Host smart-fae9eacd-d23f-4488-851b-eff1cba65044
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474937782 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.474937782
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.2974825644
Short name T417
Test name
Test status
Simulation time 24039990 ps
CPU time 0.81 seconds
Started Oct 11 12:52:32 PM PDT 23
Finished Oct 11 12:52:33 PM PDT 23
Peak memory 205696 kb
Host smart-67dd0be0-5d12-4686-b810-968f587f1f1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974825644 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.2974825644
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.3270559931
Short name T446
Test name
Test status
Simulation time 14380180 ps
CPU time 0.83 seconds
Started Oct 11 12:52:44 PM PDT 23
Finished Oct 11 12:52:46 PM PDT 23
Peak memory 205700 kb
Host smart-5d307c55-7a56-4554-9690-282f40cc33cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270559931 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.3270559931
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.3189339364
Short name T353
Test name
Test status
Simulation time 21653691 ps
CPU time 0.89 seconds
Started Oct 11 12:51:33 PM PDT 23
Finished Oct 11 12:51:34 PM PDT 23
Peak memory 205656 kb
Host smart-47747cde-2f29-4231-b78c-50b6e42c7ac0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189339364 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.3189339364
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.2918587413
Short name T374
Test name
Test status
Simulation time 42320922 ps
CPU time 0.74 seconds
Started Oct 11 12:52:46 PM PDT 23
Finished Oct 11 12:52:48 PM PDT 23
Peak memory 205512 kb
Host smart-697e251f-36c3-490e-a562-494ae1eacbbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918587413 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.2918587413
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.3005724621
Short name T432
Test name
Test status
Simulation time 148024750 ps
CPU time 0.82 seconds
Started Oct 11 12:51:25 PM PDT 23
Finished Oct 11 12:51:27 PM PDT 23
Peak memory 205620 kb
Host smart-7452683e-034c-46a7-8b92-81c57f39c0b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005724621 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.3005724621
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.1619012456
Short name T209
Test name
Test status
Simulation time 13824653 ps
CPU time 0.82 seconds
Started Oct 11 12:51:14 PM PDT 23
Finished Oct 11 12:51:15 PM PDT 23
Peak memory 205656 kb
Host smart-b075da0b-a590-4b0d-900a-708986b5932b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619012456 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.1619012456
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2503405406
Short name T144
Test name
Test status
Simulation time 63727980 ps
CPU time 1.25 seconds
Started Oct 11 12:51:27 PM PDT 23
Finished Oct 11 12:51:29 PM PDT 23
Peak memory 216192 kb
Host smart-d786fc4b-a161-420b-a543-3328833ace31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503405406 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.2503405406
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.355796886
Short name T443
Test name
Test status
Simulation time 82727287 ps
CPU time 0.8 seconds
Started Oct 11 12:51:21 PM PDT 23
Finished Oct 11 12:51:22 PM PDT 23
Peak memory 205616 kb
Host smart-0ed7a765-7643-4cd5-8305-ea66abca4da8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355796886 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.355796886
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.4107855514
Short name T408
Test name
Test status
Simulation time 38418263 ps
CPU time 0.77 seconds
Started Oct 11 12:51:09 PM PDT 23
Finished Oct 11 12:51:10 PM PDT 23
Peak memory 205532 kb
Host smart-3677f6f2-1244-4778-89e0-458db482bda7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107855514 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.4107855514
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1301573171
Short name T217
Test name
Test status
Simulation time 37172729 ps
CPU time 0.89 seconds
Started Oct 11 12:51:32 PM PDT 23
Finished Oct 11 12:51:34 PM PDT 23
Peak memory 205796 kb
Host smart-16c48b6a-e101-49ce-998d-1a37e10d83bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301573171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.1301573171
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.1154243589
Short name T344
Test name
Test status
Simulation time 75636816 ps
CPU time 2.3 seconds
Started Oct 11 12:52:47 PM PDT 23
Finished Oct 11 12:52:50 PM PDT 23
Peak memory 213896 kb
Host smart-451fc5a9-63bc-4d82-957b-cbc82ac147f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154243589 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.1154243589
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1321866935
Short name T271
Test name
Test status
Simulation time 298155688 ps
CPU time 2.02 seconds
Started Oct 11 12:51:31 PM PDT 23
Finished Oct 11 12:51:34 PM PDT 23
Peak memory 205716 kb
Host smart-94c2f0d3-9f4d-4f8c-ad0e-27d9fb66ff36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321866935 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.1321866935
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.350230449
Short name T395
Test name
Test status
Simulation time 23748621 ps
CPU time 1.09 seconds
Started Oct 11 12:52:22 PM PDT 23
Finished Oct 11 12:52:23 PM PDT 23
Peak memory 213988 kb
Host smart-345cd45a-4c1f-44d6-a26e-82c29bdbbbf0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350230449 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.350230449
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.3232487994
Short name T445
Test name
Test status
Simulation time 97891002 ps
CPU time 0.79 seconds
Started Oct 11 12:52:08 PM PDT 23
Finished Oct 11 12:52:10 PM PDT 23
Peak memory 205708 kb
Host smart-397ec0d5-4176-4ee6-9f5c-99f8ab7ba26a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232487994 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.3232487994
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.2048056509
Short name T385
Test name
Test status
Simulation time 12128852 ps
CPU time 0.81 seconds
Started Oct 11 12:51:43 PM PDT 23
Finished Oct 11 12:51:44 PM PDT 23
Peak memory 205692 kb
Host smart-7c4a8851-79a8-4d6c-b8dd-8f80b50d5cdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048056509 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.2048056509
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.304914185
Short name T231
Test name
Test status
Simulation time 56879574 ps
CPU time 1.23 seconds
Started Oct 11 12:51:22 PM PDT 23
Finished Oct 11 12:51:23 PM PDT 23
Peak memory 205784 kb
Host smart-15dbfb00-5f73-4172-8ddf-9b00749fd911
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304914185 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_out
standing.304914185
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.1903535076
Short name T381
Test name
Test status
Simulation time 489661515 ps
CPU time 3.93 seconds
Started Oct 11 12:51:42 PM PDT 23
Finished Oct 11 12:51:57 PM PDT 23
Peak memory 214048 kb
Host smart-d0d9bb3b-2fce-46a5-8d70-c2ca8d598d8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903535076 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.1903535076
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3375910327
Short name T275
Test name
Test status
Simulation time 595425030 ps
CPU time 1.88 seconds
Started Oct 11 12:52:13 PM PDT 23
Finished Oct 11 12:52:15 PM PDT 23
Peak memory 205788 kb
Host smart-d216e15d-caa3-4047-b1c8-518ddc9a3572
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375910327 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.3375910327
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1359449574
Short name T220
Test name
Test status
Simulation time 64288210 ps
CPU time 1 seconds
Started Oct 11 12:52:20 PM PDT 23
Finished Oct 11 12:52:21 PM PDT 23
Peak memory 213920 kb
Host smart-527e5306-b2e8-4c99-8aa8-ca7ccc0e6ea3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359449574 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.1359449574
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.1084201023
Short name T383
Test name
Test status
Simulation time 25782924 ps
CPU time 0.88 seconds
Started Oct 11 12:51:36 PM PDT 23
Finished Oct 11 12:51:38 PM PDT 23
Peak memory 205940 kb
Host smart-9e1c56ce-9da2-41b1-bb4b-573d92ab486f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084201023 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1084201023
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.2652988901
Short name T388
Test name
Test status
Simulation time 14290127 ps
CPU time 0.83 seconds
Started Oct 11 12:51:22 PM PDT 23
Finished Oct 11 12:51:23 PM PDT 23
Peak memory 205684 kb
Host smart-05f6338c-4ac3-4634-9d76-e17ea17a2bd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652988901 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.2652988901
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.992462346
Short name T152
Test name
Test status
Simulation time 45567388 ps
CPU time 1.1 seconds
Started Oct 11 12:52:12 PM PDT 23
Finished Oct 11 12:52:14 PM PDT 23
Peak memory 205852 kb
Host smart-6876be94-0a51-4545-b7b9-ba8d770e7a8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992462346 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_out
standing.992462346
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.967730946
Short name T444
Test name
Test status
Simulation time 104233591 ps
CPU time 1.44 seconds
Started Oct 11 12:51:38 PM PDT 23
Finished Oct 11 12:51:40 PM PDT 23
Peak memory 213932 kb
Host smart-6b9b9a1b-990d-4083-ac13-a74a64fe14cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967730946 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.967730946
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2341855779
Short name T420
Test name
Test status
Simulation time 87833046 ps
CPU time 2.18 seconds
Started Oct 11 12:51:31 PM PDT 23
Finished Oct 11 12:51:33 PM PDT 23
Peak memory 205768 kb
Host smart-f5af42e7-aeb9-4367-b9d1-cdc2eaa5599c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341855779 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.2341855779
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.814968425
Short name T427
Test name
Test status
Simulation time 47078727 ps
CPU time 1.24 seconds
Started Oct 11 12:52:15 PM PDT 23
Finished Oct 11 12:52:16 PM PDT 23
Peak memory 214060 kb
Host smart-8335e006-7c1f-4e50-bf4b-fe004c96cca0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814968425 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.814968425
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.1611108042
Short name T212
Test name
Test status
Simulation time 20397197 ps
CPU time 0.83 seconds
Started Oct 11 12:52:16 PM PDT 23
Finished Oct 11 12:52:18 PM PDT 23
Peak memory 205940 kb
Host smart-47cdabb6-0810-4994-b6cc-e1675aa027b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611108042 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.1611108042
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.73918852
Short name T410
Test name
Test status
Simulation time 80408393 ps
CPU time 0.73 seconds
Started Oct 11 12:52:19 PM PDT 23
Finished Oct 11 12:52:20 PM PDT 23
Peak memory 205584 kb
Host smart-04ae794d-99b8-40dc-8692-2a5a74d9bca8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73918852 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.73918852
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1011197598
Short name T373
Test name
Test status
Simulation time 83429645 ps
CPU time 1.01 seconds
Started Oct 11 12:52:02 PM PDT 23
Finished Oct 11 12:52:04 PM PDT 23
Peak memory 205772 kb
Host smart-5c2f2786-6524-4267-aee9-7b8eea6e1b7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011197598 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.1011197598
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.4132909417
Short name T341
Test name
Test status
Simulation time 92197945 ps
CPU time 1.71 seconds
Started Oct 11 12:52:24 PM PDT 23
Finished Oct 11 12:52:36 PM PDT 23
Peak memory 213968 kb
Host smart-f59f6f4f-4dde-4b85-9a77-4f73c5df8ad8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132909417 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.4132909417
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1106573138
Short name T346
Test name
Test status
Simulation time 89109785 ps
CPU time 2.32 seconds
Started Oct 11 12:52:28 PM PDT 23
Finished Oct 11 12:52:31 PM PDT 23
Peak memory 205788 kb
Host smart-623bba4e-18ea-46f9-9e44-24b53837836e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106573138 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.1106573138
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.279891679
Short name T413
Test name
Test status
Simulation time 22595069 ps
CPU time 1.17 seconds
Started Oct 11 12:52:37 PM PDT 23
Finished Oct 11 12:52:39 PM PDT 23
Peak memory 214112 kb
Host smart-8c6ac732-0b72-4bef-af29-d2cfb06402f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279891679 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.279891679
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.3519361942
Short name T225
Test name
Test status
Simulation time 14143629 ps
CPU time 0.83 seconds
Started Oct 11 12:52:50 PM PDT 23
Finished Oct 11 12:52:51 PM PDT 23
Peak memory 205692 kb
Host smart-3c6d85ca-8362-4e32-98bb-a0e57b020638
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519361942 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3519361942
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.348378143
Short name T424
Test name
Test status
Simulation time 44787749 ps
CPU time 0.77 seconds
Started Oct 11 12:52:25 PM PDT 23
Finished Oct 11 12:52:26 PM PDT 23
Peak memory 205584 kb
Host smart-2a88434e-fbb3-41ea-b860-8dc1c62bc7fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348378143 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.348378143
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.583987581
Short name T148
Test name
Test status
Simulation time 73128904 ps
CPU time 1 seconds
Started Oct 11 12:52:55 PM PDT 23
Finished Oct 11 12:52:56 PM PDT 23
Peak memory 205732 kb
Host smart-1af711b1-0844-4500-ac11-c294dd74faa7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583987581 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_out
standing.583987581
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.4007340306
Short name T222
Test name
Test status
Simulation time 42987777 ps
CPU time 2.67 seconds
Started Oct 11 12:53:11 PM PDT 23
Finished Oct 11 12:53:14 PM PDT 23
Peak memory 214016 kb
Host smart-6c56f0d1-3434-448c-848d-00f0d0aa2e60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007340306 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.4007340306
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/default/0.edn_alert.3740813862
Short name T303
Test name
Test status
Simulation time 19051402 ps
CPU time 0.96 seconds
Started Oct 11 12:51:22 PM PDT 23
Finished Oct 11 12:51:24 PM PDT 23
Peak memory 205148 kb
Host smart-24f3b43c-6f03-45d5-8a84-668130c86544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740813862 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.3740813862
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.2141099770
Short name T698
Test name
Test status
Simulation time 33712750 ps
CPU time 0.91 seconds
Started Oct 11 12:52:34 PM PDT 23
Finished Oct 11 12:52:35 PM PDT 23
Peak memory 205244 kb
Host smart-afaeb409-b604-498c-b635-4659d4d13fef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141099770 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2141099770
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.11391866
Short name T58
Test name
Test status
Simulation time 34754947 ps
CPU time 0.79 seconds
Started Oct 11 12:51:32 PM PDT 23
Finished Oct 11 12:51:33 PM PDT 23
Peak memory 214496 kb
Host smart-02ec29dd-fae4-4f04-8e8b-2e58680fdbf4
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11391866 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.11391866
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_err.3908579096
Short name T63
Test name
Test status
Simulation time 19302091 ps
CPU time 1.34 seconds
Started Oct 11 12:51:27 PM PDT 23
Finished Oct 11 12:51:28 PM PDT 23
Peak memory 215680 kb
Host smart-daa786f7-4bbd-4a24-838e-6f0553fa39ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908579096 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.3908579096
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.2741901757
Short name T95
Test name
Test status
Simulation time 110687908 ps
CPU time 1.14 seconds
Started Oct 11 12:52:24 PM PDT 23
Finished Oct 11 12:52:26 PM PDT 23
Peak memory 205184 kb
Host smart-86d10d21-9fd8-4d25-9866-90ba8639a0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741901757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2741901757
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.2883730490
Short name T684
Test name
Test status
Simulation time 24021517 ps
CPU time 0.87 seconds
Started Oct 11 12:51:36 PM PDT 23
Finished Oct 11 12:51:39 PM PDT 23
Peak memory 214788 kb
Host smart-9130ff4a-292f-4ee4-a7c9-2cd3a367a000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883730490 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.2883730490
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_sec_cm.1105722549
Short name T24
Test name
Test status
Simulation time 441133194 ps
CPU time 6.21 seconds
Started Oct 11 12:51:26 PM PDT 23
Finished Oct 11 12:51:33 PM PDT 23
Peak memory 235112 kb
Host smart-99e80d3f-b234-4dfa-87a2-cac52e0e5336
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105722549 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.1105722549
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.2134652336
Short name T590
Test name
Test status
Simulation time 27009360 ps
CPU time 0.84 seconds
Started Oct 11 12:51:02 PM PDT 23
Finished Oct 11 12:51:04 PM PDT 23
Peak memory 204700 kb
Host smart-18f5b7df-7c50-49b7-9d43-f5816ef855a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134652336 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.2134652336
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.3536025333
Short name T539
Test name
Test status
Simulation time 807604463 ps
CPU time 3.49 seconds
Started Oct 11 12:51:13 PM PDT 23
Finished Oct 11 12:51:17 PM PDT 23
Peak memory 205924 kb
Host smart-a9e821db-ce80-444d-bf33-a9c7a3a62b7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536025333 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.3536025333
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.4205868377
Short name T2
Test name
Test status
Simulation time 34946050923 ps
CPU time 574.1 seconds
Started Oct 11 12:51:36 PM PDT 23
Finished Oct 11 01:01:12 PM PDT 23
Peak memory 216156 kb
Host smart-eedc497c-fad8-4dee-b9e3-9b39fcbf68d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205868377 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.4205868377
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.2399921845
Short name T294
Test name
Test status
Simulation time 37047323 ps
CPU time 0.95 seconds
Started Oct 11 12:52:14 PM PDT 23
Finished Oct 11 12:52:16 PM PDT 23
Peak memory 206188 kb
Host smart-51c33ac5-fdab-48da-b3c3-5735aa92cf6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399921845 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.2399921845
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.369487279
Short name T178
Test name
Test status
Simulation time 37325941 ps
CPU time 0.91 seconds
Started Oct 11 12:52:19 PM PDT 23
Finished Oct 11 12:52:20 PM PDT 23
Peak memory 214604 kb
Host smart-a0c481da-219a-4c1b-a7b4-f3703d1f4603
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369487279 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_dis
able_auto_req_mode.369487279
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.1950770775
Short name T188
Test name
Test status
Simulation time 26169690 ps
CPU time 0.85 seconds
Started Oct 11 12:51:35 PM PDT 23
Finished Oct 11 12:51:36 PM PDT 23
Peak memory 215704 kb
Host smart-ca510a7a-d810-48db-a279-07e1d36a946a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950770775 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.1950770775
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_intr.3837053073
Short name T668
Test name
Test status
Simulation time 34075158 ps
CPU time 0.85 seconds
Started Oct 11 12:52:06 PM PDT 23
Finished Oct 11 12:52:07 PM PDT 23
Peak memory 214392 kb
Host smart-2499a3e3-70aa-43a3-93c3-2cc5c896be17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837053073 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.3837053073
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.1110593671
Short name T601
Test name
Test status
Simulation time 52828853 ps
CPU time 0.9 seconds
Started Oct 11 12:52:05 PM PDT 23
Finished Oct 11 12:52:06 PM PDT 23
Peak memory 204744 kb
Host smart-ffbf5495-a709-47fa-9f9a-0a91729b14d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110593671 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.1110593671
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_smoke.3644868145
Short name T622
Test name
Test status
Simulation time 15852061 ps
CPU time 0.9 seconds
Started Oct 11 12:51:29 PM PDT 23
Finished Oct 11 12:51:30 PM PDT 23
Peak memory 204936 kb
Host smart-33129645-eea5-48c9-ad14-8da49fb6c9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644868145 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.3644868145
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.291037089
Short name T687
Test name
Test status
Simulation time 113977677231 ps
CPU time 968.2 seconds
Started Oct 11 12:52:21 PM PDT 23
Finished Oct 11 01:08:30 PM PDT 23
Peak memory 215916 kb
Host smart-bac767f1-7a24-4169-a096-d680a9955301
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291037089 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.291037089
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.3462689841
Short name T506
Test name
Test status
Simulation time 66546159 ps
CPU time 0.94 seconds
Started Oct 11 12:52:43 PM PDT 23
Finished Oct 11 12:52:44 PM PDT 23
Peak memory 206076 kb
Host smart-181f3d20-8f06-430f-a8da-f2ad05fa7c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462689841 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.3462689841
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.3252858692
Short name T487
Test name
Test status
Simulation time 70970835 ps
CPU time 0.9 seconds
Started Oct 11 12:53:03 PM PDT 23
Finished Oct 11 12:53:04 PM PDT 23
Peak memory 204556 kb
Host smart-c3b58eec-ed8d-436a-9f0b-d8e6d37d4889
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252858692 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.3252858692
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.1295814092
Short name T203
Test name
Test status
Simulation time 13677139 ps
CPU time 0.84 seconds
Started Oct 11 12:52:40 PM PDT 23
Finished Oct 11 12:52:41 PM PDT 23
Peak memory 214396 kb
Host smart-df4ae473-fe54-4ec6-a44f-ae839bd9d567
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295814092 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.1295814092
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_err.2499086771
Short name T242
Test name
Test status
Simulation time 18559193 ps
CPU time 0.98 seconds
Started Oct 11 12:53:07 PM PDT 23
Finished Oct 11 12:53:09 PM PDT 23
Peak memory 214460 kb
Host smart-912fe8a0-350c-4f10-a7d0-91edcc6c71d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499086771 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.2499086771
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_intr.3468292639
Short name T118
Test name
Test status
Simulation time 93018281 ps
CPU time 0.75 seconds
Started Oct 11 12:52:44 PM PDT 23
Finished Oct 11 12:52:45 PM PDT 23
Peak memory 214676 kb
Host smart-052c27f2-cfef-46b0-9a54-304758c9b47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468292639 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.3468292639
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.3952799966
Short name T526
Test name
Test status
Simulation time 76476541 ps
CPU time 0.84 seconds
Started Oct 11 12:52:33 PM PDT 23
Finished Oct 11 12:52:34 PM PDT 23
Peak memory 204684 kb
Host smart-0d9fc5e8-5e9c-4fe9-a7fc-a477c6ad79b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952799966 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.3952799966
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.1830318471
Short name T518
Test name
Test status
Simulation time 40845817 ps
CPU time 1.29 seconds
Started Oct 11 12:52:15 PM PDT 23
Finished Oct 11 12:52:16 PM PDT 23
Peak memory 205244 kb
Host smart-03a4b54f-a497-4e0f-8031-ce81b765ac29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830318471 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.1830318471
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.749650120
Short name T542
Test name
Test status
Simulation time 383835527708 ps
CPU time 2319.37 seconds
Started Oct 11 12:52:35 PM PDT 23
Finished Oct 11 01:31:15 PM PDT 23
Peak memory 222676 kb
Host smart-8a374790-9e0c-48cd-bbbc-769989927e1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749650120 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.749650120
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.edn_alert.4282233504
Short name T724
Test name
Test status
Simulation time 63406446 ps
CPU time 0.91 seconds
Started Oct 11 12:53:04 PM PDT 23
Finished Oct 11 12:53:05 PM PDT 23
Peak memory 205024 kb
Host smart-457c48e9-b8d2-403c-b06c-404add55143b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282233504 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.4282233504
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.2490023152
Short name T721
Test name
Test status
Simulation time 18285612 ps
CPU time 0.93 seconds
Started Oct 11 12:53:07 PM PDT 23
Finished Oct 11 12:53:08 PM PDT 23
Peak memory 204796 kb
Host smart-75be83bd-7b3a-4e0c-b329-f402539d6808
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490023152 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.2490023152
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.1450523293
Short name T134
Test name
Test status
Simulation time 47817515 ps
CPU time 0.83 seconds
Started Oct 11 12:52:40 PM PDT 23
Finished Oct 11 12:52:46 PM PDT 23
Peak memory 214488 kb
Host smart-b71ba090-4f84-4421-b8b3-b8ca4cad9af0
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450523293 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.1450523293
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_err.2310929209
Short name T508
Test name
Test status
Simulation time 55028223 ps
CPU time 0.97 seconds
Started Oct 11 12:52:56 PM PDT 23
Finished Oct 11 12:52:58 PM PDT 23
Peak memory 214324 kb
Host smart-4678a0a6-6916-4496-b535-2b662aef088f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310929209 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.2310929209
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_intr.1904194821
Short name T611
Test name
Test status
Simulation time 20364231 ps
CPU time 1.03 seconds
Started Oct 11 12:52:28 PM PDT 23
Finished Oct 11 12:52:40 PM PDT 23
Peak memory 214736 kb
Host smart-8af6e4b8-169c-48b0-b0d7-a0719fda8b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904194821 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.1904194821
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.976468401
Short name T61
Test name
Test status
Simulation time 47230692 ps
CPU time 0.88 seconds
Started Oct 11 12:52:55 PM PDT 23
Finished Oct 11 12:52:56 PM PDT 23
Peak memory 204876 kb
Host smart-001a87a1-3c32-42ae-9fc6-8319effa0d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976468401 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.976468401
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.3515330832
Short name T578
Test name
Test status
Simulation time 82694675 ps
CPU time 2.03 seconds
Started Oct 11 12:53:01 PM PDT 23
Finished Oct 11 12:53:04 PM PDT 23
Peak memory 205380 kb
Host smart-78232efc-3dbe-4eaa-9359-ce4134ddc446
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515330832 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.3515330832
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.3022805462
Short name T473
Test name
Test status
Simulation time 327179028696 ps
CPU time 1726.84 seconds
Started Oct 11 12:52:52 PM PDT 23
Finished Oct 11 01:21:39 PM PDT 23
Peak memory 218948 kb
Host smart-d336cd8b-e262-498a-97ed-b809d9f83fc2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022805462 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.3022805462
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.edn_alert_test.2157712220
Short name T685
Test name
Test status
Simulation time 33067245 ps
CPU time 0.84 seconds
Started Oct 11 12:52:15 PM PDT 23
Finished Oct 11 12:52:16 PM PDT 23
Peak memory 204560 kb
Host smart-23f11fad-de6d-421b-a179-117d60928df1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157712220 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2157712220
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.1465202976
Short name T602
Test name
Test status
Simulation time 44433252 ps
CPU time 0.95 seconds
Started Oct 11 12:52:58 PM PDT 23
Finished Oct 11 12:52:59 PM PDT 23
Peak memory 214544 kb
Host smart-0c5ce659-b2a8-4a7a-84f4-2a08ce61acac
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465202976 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.1465202976
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.2395215078
Short name T329
Test name
Test status
Simulation time 27386395 ps
CPU time 0.88 seconds
Started Oct 11 12:53:10 PM PDT 23
Finished Oct 11 12:53:12 PM PDT 23
Peak memory 221564 kb
Host smart-88c4df45-bc71-4605-8ca8-7a5e3b42bbeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395215078 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.2395215078
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.1041846694
Short name T474
Test name
Test status
Simulation time 26327176 ps
CPU time 0.91 seconds
Started Oct 11 12:52:45 PM PDT 23
Finished Oct 11 12:52:46 PM PDT 23
Peak memory 204912 kb
Host smart-4b408622-7c57-42f2-aef8-4a5576d15481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041846694 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.1041846694
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.1595454969
Short name T62
Test name
Test status
Simulation time 19122749 ps
CPU time 1 seconds
Started Oct 11 12:52:21 PM PDT 23
Finished Oct 11 12:52:23 PM PDT 23
Peak memory 214596 kb
Host smart-9c9f1f8b-91ce-4eac-8c7a-02fb9f6a80f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595454969 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.1595454969
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.60249857
Short name T308
Test name
Test status
Simulation time 12189814 ps
CPU time 0.83 seconds
Started Oct 11 12:53:03 PM PDT 23
Finished Oct 11 12:53:04 PM PDT 23
Peak memory 204868 kb
Host smart-88ddfa56-a39c-4129-9912-c0db1456048b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60249857 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.60249857
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.506337300
Short name T573
Test name
Test status
Simulation time 30296491 ps
CPU time 1.12 seconds
Started Oct 11 12:52:46 PM PDT 23
Finished Oct 11 12:52:48 PM PDT 23
Peak memory 205060 kb
Host smart-e815b769-9577-4a3c-becf-05257a297ee6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506337300 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.506337300
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.3221501797
Short name T464
Test name
Test status
Simulation time 18039447121 ps
CPU time 378.74 seconds
Started Oct 11 12:52:25 PM PDT 23
Finished Oct 11 12:58:44 PM PDT 23
Peak memory 216116 kb
Host smart-cccda3f2-9e90-4644-b1d3-e534ddb97c1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221501797 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.3221501797
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.edn_alert_test.1831379291
Short name T577
Test name
Test status
Simulation time 56278361 ps
CPU time 0.87 seconds
Started Oct 11 12:52:27 PM PDT 23
Finished Oct 11 12:52:28 PM PDT 23
Peak memory 204684 kb
Host smart-de3329dc-9f31-4384-90f6-d88a732db812
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831379291 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.1831379291
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.2636424786
Short name T554
Test name
Test status
Simulation time 24159587 ps
CPU time 0.82 seconds
Started Oct 11 12:52:05 PM PDT 23
Finished Oct 11 12:52:06 PM PDT 23
Peak memory 214496 kb
Host smart-8b8dd044-284d-4d0a-a482-11592a9660eb
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636424786 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.2636424786
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.4038717610
Short name T629
Test name
Test status
Simulation time 27946751 ps
CPU time 1.09 seconds
Started Oct 11 12:52:08 PM PDT 23
Finished Oct 11 12:52:09 PM PDT 23
Peak memory 214676 kb
Host smart-460b05d6-de5b-4f32-87c6-950a79053385
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038717610 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.4038717610
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.3982797370
Short name T241
Test name
Test status
Simulation time 25531432 ps
CPU time 1.05 seconds
Started Oct 11 12:52:15 PM PDT 23
Finished Oct 11 12:52:27 PM PDT 23
Peak memory 214596 kb
Host smart-fc5eee49-b004-4871-a6b2-52f99333dd88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982797370 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.3982797370
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.2651292464
Short name T7
Test name
Test status
Simulation time 23955919 ps
CPU time 1.23 seconds
Started Oct 11 12:51:35 PM PDT 23
Finished Oct 11 12:51:37 PM PDT 23
Peak memory 214416 kb
Host smart-13e6c1c9-1c8c-457e-af03-3d58fb1f8d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651292464 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.2651292464
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_smoke.1064094943
Short name T589
Test name
Test status
Simulation time 60007315 ps
CPU time 0.82 seconds
Started Oct 11 12:51:42 PM PDT 23
Finished Oct 11 12:51:44 PM PDT 23
Peak memory 204688 kb
Host smart-cd8fda16-0687-45bd-91f1-6e11a916ae03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064094943 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.1064094943
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.1674393723
Short name T561
Test name
Test status
Simulation time 40396536 ps
CPU time 1.34 seconds
Started Oct 11 12:52:00 PM PDT 23
Finished Oct 11 12:52:01 PM PDT 23
Peak memory 205104 kb
Host smart-accc0cb2-b18e-4be0-9087-fb43be8dc83e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674393723 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.1674393723
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.476684036
Short name T623
Test name
Test status
Simulation time 440408130449 ps
CPU time 1019.3 seconds
Started Oct 11 12:52:25 PM PDT 23
Finished Oct 11 01:09:25 PM PDT 23
Peak memory 217488 kb
Host smart-f63108b5-b196-4a59-8877-7f169deb4741
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476684036 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.476684036
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.edn_alert.2901466293
Short name T689
Test name
Test status
Simulation time 17007912 ps
CPU time 0.92 seconds
Started Oct 11 12:52:33 PM PDT 23
Finished Oct 11 12:52:35 PM PDT 23
Peak memory 206168 kb
Host smart-7c1e2d8f-9f7a-4ea8-b598-e8f167ebb88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901466293 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.2901466293
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.231561409
Short name T639
Test name
Test status
Simulation time 16807729 ps
CPU time 0.79 seconds
Started Oct 11 12:52:25 PM PDT 23
Finished Oct 11 12:52:26 PM PDT 23
Peak memory 204284 kb
Host smart-544e1c5f-f4d7-410c-95bd-deda681e6d36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231561409 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.231561409
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.1953186547
Short name T524
Test name
Test status
Simulation time 94904367 ps
CPU time 0.97 seconds
Started Oct 11 12:53:06 PM PDT 23
Finished Oct 11 12:53:07 PM PDT 23
Peak memory 214716 kb
Host smart-daa8588f-4155-4ea7-9375-6f840c39e7fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953186547 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.1953186547
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.1806511415
Short name T453
Test name
Test status
Simulation time 42712006 ps
CPU time 1.05 seconds
Started Oct 11 12:52:31 PM PDT 23
Finished Oct 11 12:52:32 PM PDT 23
Peak memory 214664 kb
Host smart-e1cd4f30-a908-4ff8-860b-c8aa6d1a55e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806511415 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.1806511415
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.1406592145
Short name T719
Test name
Test status
Simulation time 54293309 ps
CPU time 1.22 seconds
Started Oct 11 12:52:44 PM PDT 23
Finished Oct 11 12:52:46 PM PDT 23
Peak memory 205236 kb
Host smart-d5130c5f-47fb-4367-bd0b-c259042958ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406592145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.1406592145
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.3109468829
Short name T650
Test name
Test status
Simulation time 27101800 ps
CPU time 0.91 seconds
Started Oct 11 12:52:46 PM PDT 23
Finished Oct 11 12:52:48 PM PDT 23
Peak memory 214792 kb
Host smart-b651a11a-5eb8-4771-a01e-265d24c004d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109468829 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.3109468829
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.2773983583
Short name T104
Test name
Test status
Simulation time 19211845 ps
CPU time 0.85 seconds
Started Oct 11 12:52:47 PM PDT 23
Finished Oct 11 12:52:49 PM PDT 23
Peak memory 204820 kb
Host smart-198b784f-5431-4e23-b761-f2a1e2919906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773983583 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.2773983583
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.1915930411
Short name T565
Test name
Test status
Simulation time 1214492427 ps
CPU time 2.47 seconds
Started Oct 11 12:52:23 PM PDT 23
Finished Oct 11 12:52:26 PM PDT 23
Peak memory 206080 kb
Host smart-d9fdcb40-0802-4af1-8435-7c13ef6cb2bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915930411 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.1915930411
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.3299855495
Short name T516
Test name
Test status
Simulation time 455659264972 ps
CPU time 1839.78 seconds
Started Oct 11 12:53:45 PM PDT 23
Finished Oct 11 01:24:26 PM PDT 23
Peak memory 220316 kb
Host smart-3d59a063-d1c8-49a0-a33f-a8aef4210e28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299855495 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.3299855495
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.edn_alert.2340237584
Short name T614
Test name
Test status
Simulation time 30647368 ps
CPU time 0.91 seconds
Started Oct 11 12:52:46 PM PDT 23
Finished Oct 11 12:52:48 PM PDT 23
Peak memory 205284 kb
Host smart-31891cb6-647c-45d8-99b2-d44d480ffc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340237584 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.2340237584
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.2882543654
Short name T530
Test name
Test status
Simulation time 115392509 ps
CPU time 0.79 seconds
Started Oct 11 12:53:05 PM PDT 23
Finished Oct 11 12:53:06 PM PDT 23
Peak memory 204616 kb
Host smart-043ddb2f-bf0f-49ce-ba04-929e0e0c9f9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882543654 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.2882543654
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.3934851420
Short name T136
Test name
Test status
Simulation time 11717067 ps
CPU time 0.85 seconds
Started Oct 11 12:53:18 PM PDT 23
Finished Oct 11 12:53:19 PM PDT 23
Peak memory 214392 kb
Host smart-1e4a17e1-3adc-4eab-94ec-0c7ec2252c67
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934851420 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.3934851420
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.4086316296
Short name T76
Test name
Test status
Simulation time 37929411 ps
CPU time 0.96 seconds
Started Oct 11 12:53:08 PM PDT 23
Finished Oct 11 12:53:10 PM PDT 23
Peak memory 214676 kb
Host smart-18951353-cbce-494d-9639-5377397053b8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086316296 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.4086316296
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.2811118704
Short name T237
Test name
Test status
Simulation time 22367886 ps
CPU time 0.9 seconds
Started Oct 11 12:53:00 PM PDT 23
Finished Oct 11 12:53:02 PM PDT 23
Peak memory 214636 kb
Host smart-58d61808-b31a-414a-82dd-3eaaa25eda13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811118704 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.2811118704
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.3195877419
Short name T448
Test name
Test status
Simulation time 29964493 ps
CPU time 1.04 seconds
Started Oct 11 12:52:35 PM PDT 23
Finished Oct 11 12:52:37 PM PDT 23
Peak memory 214376 kb
Host smart-efff124e-08a0-484e-8837-e309e6028982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195877419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.3195877419
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.2262427379
Short name T332
Test name
Test status
Simulation time 20787469 ps
CPU time 1.12 seconds
Started Oct 11 12:52:29 PM PDT 23
Finished Oct 11 12:52:30 PM PDT 23
Peak memory 221468 kb
Host smart-b88c112d-e816-4572-a196-eb43e3f41965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262427379 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.2262427379
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.2334615878
Short name T470
Test name
Test status
Simulation time 17552139 ps
CPU time 0.92 seconds
Started Oct 11 12:53:02 PM PDT 23
Finished Oct 11 12:53:04 PM PDT 23
Peak memory 204880 kb
Host smart-65e3e667-26ed-4772-a8e0-bd4175ad71bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334615878 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2334615878
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.2723880533
Short name T688
Test name
Test status
Simulation time 47107239 ps
CPU time 1.4 seconds
Started Oct 11 12:52:41 PM PDT 23
Finished Oct 11 12:52:43 PM PDT 23
Peak memory 205224 kb
Host smart-9454935d-49a9-42d6-87d4-226de1d286f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723880533 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.2723880533
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.2318757731
Short name T543
Test name
Test status
Simulation time 29055817847 ps
CPU time 704.12 seconds
Started Oct 11 12:52:23 PM PDT 23
Finished Oct 11 01:04:08 PM PDT 23
Peak memory 215348 kb
Host smart-0ea77e1b-cedd-4105-b27d-933d118f48c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318757731 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.2318757731
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.edn_alert.2035959091
Short name T296
Test name
Test status
Simulation time 84168745 ps
CPU time 0.91 seconds
Started Oct 11 12:51:32 PM PDT 23
Finished Oct 11 12:51:33 PM PDT 23
Peak memory 206048 kb
Host smart-bd6fd0a1-e878-4bf4-b365-ddd4967f0c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035959091 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.2035959091
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.3712742351
Short name T574
Test name
Test status
Simulation time 95004942 ps
CPU time 0.82 seconds
Started Oct 11 12:51:36 PM PDT 23
Finished Oct 11 12:51:38 PM PDT 23
Peak memory 204684 kb
Host smart-3ebd44b1-63c7-446b-a2a5-18834fb644b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712742351 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.3712742351
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.527666230
Short name T109
Test name
Test status
Simulation time 32393780 ps
CPU time 0.8 seconds
Started Oct 11 12:52:05 PM PDT 23
Finished Oct 11 12:52:07 PM PDT 23
Peak memory 214436 kb
Host smart-80f8b67b-433b-427f-8fcb-12bab753f6b4
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527666230 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.527666230
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.1539994660
Short name T167
Test name
Test status
Simulation time 32946186 ps
CPU time 0.89 seconds
Started Oct 11 12:51:44 PM PDT 23
Finished Oct 11 12:51:45 PM PDT 23
Peak memory 214676 kb
Host smart-cc84d98e-4149-46f0-9949-8f20e2f2e740
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539994660 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.1539994660
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.355241989
Short name T110
Test name
Test status
Simulation time 45951940 ps
CPU time 0.83 seconds
Started Oct 11 12:51:41 PM PDT 23
Finished Oct 11 12:51:44 PM PDT 23
Peak memory 215520 kb
Host smart-f8b2cf81-5bb0-4a3b-8d47-60ba52674226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355241989 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.355241989
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.990543015
Short name T490
Test name
Test status
Simulation time 36544239 ps
CPU time 0.96 seconds
Started Oct 11 12:51:42 PM PDT 23
Finished Oct 11 12:51:44 PM PDT 23
Peak memory 214424 kb
Host smart-b9a74dd0-6be0-4ace-a7a8-fce191875e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990543015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.990543015
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_smoke.3058262830
Short name T546
Test name
Test status
Simulation time 26131460 ps
CPU time 0.89 seconds
Started Oct 11 12:51:41 PM PDT 23
Finished Oct 11 12:51:42 PM PDT 23
Peak memory 204764 kb
Host smart-219cadb5-6e80-411f-8e59-4ff1239df08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058262830 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.3058262830
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.2905183615
Short name T599
Test name
Test status
Simulation time 51684556 ps
CPU time 1.48 seconds
Started Oct 11 12:51:42 PM PDT 23
Finished Oct 11 12:51:45 PM PDT 23
Peak memory 205080 kb
Host smart-1683b781-fc6c-4584-81a5-efe757284683
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905183615 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2905183615
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_alert.1491848590
Short name T160
Test name
Test status
Simulation time 17751703 ps
CPU time 0.92 seconds
Started Oct 11 12:52:42 PM PDT 23
Finished Oct 11 12:52:44 PM PDT 23
Peak memory 205100 kb
Host smart-5eee331a-08c4-4b1d-99a6-be89ab1f8a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491848590 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.1491848590
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.3517863117
Short name T548
Test name
Test status
Simulation time 15469294 ps
CPU time 0.93 seconds
Started Oct 11 12:52:44 PM PDT 23
Finished Oct 11 12:52:45 PM PDT 23
Peak memory 205264 kb
Host smart-ed81a6c9-e4da-468a-98e2-1bfd4c7f330e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517863117 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3517863117
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.1515251158
Short name T248
Test name
Test status
Simulation time 98946626 ps
CPU time 1.08 seconds
Started Oct 11 12:52:33 PM PDT 23
Finished Oct 11 12:52:35 PM PDT 23
Peak memory 214680 kb
Host smart-8e18490d-4057-4343-ade5-2dadf06490f4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515251158 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.1515251158
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.4088095349
Short name T699
Test name
Test status
Simulation time 30932870 ps
CPU time 0.91 seconds
Started Oct 11 12:52:09 PM PDT 23
Finished Oct 11 12:52:11 PM PDT 23
Peak memory 214540 kb
Host smart-3da6558c-c3a7-49f1-b332-58169b1c6936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088095349 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.4088095349
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.2492209045
Short name T96
Test name
Test status
Simulation time 55952526 ps
CPU time 1.05 seconds
Started Oct 11 12:52:21 PM PDT 23
Finished Oct 11 12:52:23 PM PDT 23
Peak memory 205132 kb
Host smart-70fc6e7e-3c18-43fe-a55c-bacd6f61a65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492209045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.2492209045
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.3294566780
Short name T665
Test name
Test status
Simulation time 20279873 ps
CPU time 0.87 seconds
Started Oct 11 12:51:57 PM PDT 23
Finished Oct 11 12:51:58 PM PDT 23
Peak memory 214808 kb
Host smart-b122e5a2-cd12-4f15-9d76-626738b40e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294566780 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3294566780
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.3506158523
Short name T311
Test name
Test status
Simulation time 13098085 ps
CPU time 0.87 seconds
Started Oct 11 12:52:12 PM PDT 23
Finished Oct 11 12:52:13 PM PDT 23
Peak memory 204620 kb
Host smart-ed7f55b0-faa8-4e10-aa9f-ba8e76efa916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506158523 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.3506158523
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.3742281942
Short name T319
Test name
Test status
Simulation time 270538490 ps
CPU time 2.86 seconds
Started Oct 11 12:51:39 PM PDT 23
Finished Oct 11 12:51:42 PM PDT 23
Peak memory 205744 kb
Host smart-20e0c385-4751-475c-b02b-b63bfc3bec04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742281942 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.3742281942
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.708381967
Short name T484
Test name
Test status
Simulation time 298101741671 ps
CPU time 1634.41 seconds
Started Oct 11 12:52:35 PM PDT 23
Finished Oct 11 01:19:50 PM PDT 23
Peak memory 217520 kb
Host smart-ed05563c-d2d4-4121-a71d-b5e7366f5b63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708381967 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.708381967
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.edn_alert.2829210595
Short name T299
Test name
Test status
Simulation time 34765651 ps
CPU time 1.03 seconds
Started Oct 11 12:51:36 PM PDT 23
Finished Oct 11 12:51:39 PM PDT 23
Peak memory 206084 kb
Host smart-4cf7a1e4-5fe5-497f-ab0c-d80765de5cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829210595 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.2829210595
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.2215825760
Short name T476
Test name
Test status
Simulation time 25437650 ps
CPU time 0.83 seconds
Started Oct 11 12:52:25 PM PDT 23
Finished Oct 11 12:52:26 PM PDT 23
Peak memory 204604 kb
Host smart-59c06f50-63c1-45ec-bda5-111d56492613
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215825760 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2215825760
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.2397851745
Short name T130
Test name
Test status
Simulation time 30326517 ps
CPU time 0.81 seconds
Started Oct 11 12:52:30 PM PDT 23
Finished Oct 11 12:52:31 PM PDT 23
Peak memory 214460 kb
Host smart-71c1c21b-09f9-4e75-9f91-497f90b69bbd
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397851745 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2397851745
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.793293745
Short name T185
Test name
Test status
Simulation time 37547616 ps
CPU time 1.02 seconds
Started Oct 11 12:51:48 PM PDT 23
Finished Oct 11 12:51:49 PM PDT 23
Peak memory 214716 kb
Host smart-b5f7e88a-4a92-4f40-8dde-7a0b9b7841ea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793293745 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_di
sable_auto_req_mode.793293745
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.2712169532
Short name T199
Test name
Test status
Simulation time 19072470 ps
CPU time 1.05 seconds
Started Oct 11 12:51:36 PM PDT 23
Finished Oct 11 12:51:39 PM PDT 23
Peak memory 221524 kb
Host smart-b56b53e7-497c-4c9a-a14e-46fd715ca23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712169532 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.2712169532
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_intr.2135345943
Short name T514
Test name
Test status
Simulation time 24007212 ps
CPU time 0.9 seconds
Started Oct 11 12:52:20 PM PDT 23
Finished Oct 11 12:52:22 PM PDT 23
Peak memory 214540 kb
Host smart-86997c33-8a0a-4a20-8dee-6ae76a6f6194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135345943 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.2135345943
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.3333014126
Short name T65
Test name
Test status
Simulation time 12661310 ps
CPU time 0.86 seconds
Started Oct 11 12:52:29 PM PDT 23
Finished Oct 11 12:52:30 PM PDT 23
Peak memory 204988 kb
Host smart-5827b00c-4ccc-4004-877e-592c580be01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333014126 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.3333014126
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.3929512173
Short name T511
Test name
Test status
Simulation time 139224611 ps
CPU time 3.26 seconds
Started Oct 11 12:51:27 PM PDT 23
Finished Oct 11 12:51:31 PM PDT 23
Peak memory 206072 kb
Host smart-6e7d3fc5-6977-4e26-939c-590b0be9fa14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929512173 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.3929512173
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.3625235613
Short name T624
Test name
Test status
Simulation time 30298740829 ps
CPU time 167.18 seconds
Started Oct 11 12:51:26 PM PDT 23
Finished Oct 11 12:54:14 PM PDT 23
Peak memory 214540 kb
Host smart-bdb3372d-cc1e-4030-8b4d-5efbc6dd6dbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625235613 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.3625235613
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.edn_alert.2242010906
Short name T504
Test name
Test status
Simulation time 35872836 ps
CPU time 0.92 seconds
Started Oct 11 12:52:45 PM PDT 23
Finished Oct 11 12:52:47 PM PDT 23
Peak memory 206116 kb
Host smart-fcfacc8c-c9ca-462b-852b-2a10afd1296f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242010906 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.2242010906
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.2124027285
Short name T456
Test name
Test status
Simulation time 43427200 ps
CPU time 0.91 seconds
Started Oct 11 12:52:43 PM PDT 23
Finished Oct 11 12:52:44 PM PDT 23
Peak memory 204716 kb
Host smart-f87b5343-4096-4c91-93b7-a0221a838b1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124027285 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.2124027285
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.2447392874
Short name T584
Test name
Test status
Simulation time 20161860 ps
CPU time 0.82 seconds
Started Oct 11 12:51:52 PM PDT 23
Finished Oct 11 12:51:53 PM PDT 23
Peak memory 214424 kb
Host smart-bb53ecdf-ba54-4a19-826d-751a2023e3f9
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447392874 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.2447392874
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.1165035647
Short name T174
Test name
Test status
Simulation time 52863469 ps
CPU time 0.91 seconds
Started Oct 11 12:51:41 PM PDT 23
Finished Oct 11 12:51:42 PM PDT 23
Peak memory 214676 kb
Host smart-8c0c818c-6c0c-42b9-a565-9dfc671d4f77
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165035647 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.1165035647
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.3918473911
Short name T462
Test name
Test status
Simulation time 20311046 ps
CPU time 1.14 seconds
Started Oct 11 12:52:26 PM PDT 23
Finished Oct 11 12:52:28 PM PDT 23
Peak memory 221952 kb
Host smart-ad95edc1-5ce6-4bbe-a963-b76ccfe59c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918473911 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.3918473911
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_intr.329111064
Short name T458
Test name
Test status
Simulation time 29817071 ps
CPU time 0.99 seconds
Started Oct 11 12:52:27 PM PDT 23
Finished Oct 11 12:52:28 PM PDT 23
Peak memory 221804 kb
Host smart-b7c94997-e3b9-4bfe-a74b-7348505b73b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329111064 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.329111064
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.581381805
Short name T569
Test name
Test status
Simulation time 16407098 ps
CPU time 0.89 seconds
Started Oct 11 12:52:46 PM PDT 23
Finished Oct 11 12:52:48 PM PDT 23
Peak memory 204648 kb
Host smart-631b39a2-98a9-4ab4-8be0-82da2853ad14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581381805 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.581381805
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.3818455251
Short name T657
Test name
Test status
Simulation time 350441356 ps
CPU time 3.58 seconds
Started Oct 11 12:52:11 PM PDT 23
Finished Oct 11 12:52:20 PM PDT 23
Peak memory 205632 kb
Host smart-97afa4f0-aadc-4e9e-b892-7cfe6f88d230
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818455251 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.3818455251
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.1340180815
Short name T140
Test name
Test status
Simulation time 22176884112 ps
CPU time 290.93 seconds
Started Oct 11 12:52:34 PM PDT 23
Finished Oct 11 12:57:25 PM PDT 23
Peak memory 214696 kb
Host smart-8db6fc4f-046e-4614-971e-f7f189bf36ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340180815 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.1340180815
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.edn_alert.1727288056
Short name T596
Test name
Test status
Simulation time 81093978 ps
CPU time 0.86 seconds
Started Oct 11 12:52:32 PM PDT 23
Finished Oct 11 12:52:34 PM PDT 23
Peak memory 205224 kb
Host smart-740cf6af-28de-4501-8f88-989c1296836c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727288056 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.1727288056
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.3403286361
Short name T547
Test name
Test status
Simulation time 21265633 ps
CPU time 0.99 seconds
Started Oct 11 12:51:26 PM PDT 23
Finished Oct 11 12:51:27 PM PDT 23
Peak memory 204708 kb
Host smart-9c3d35c9-35f2-452c-b871-aa004f17752d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403286361 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.3403286361
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.210294529
Short name T177
Test name
Test status
Simulation time 240341373 ps
CPU time 1.09 seconds
Started Oct 11 12:51:31 PM PDT 23
Finished Oct 11 12:51:32 PM PDT 23
Peak memory 214660 kb
Host smart-80c08e4f-3aca-4e94-83f6-fece2d439128
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210294529 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_dis
able_auto_req_mode.210294529
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.3383327337
Short name T189
Test name
Test status
Simulation time 20374223 ps
CPU time 0.85 seconds
Started Oct 11 12:53:01 PM PDT 23
Finished Oct 11 12:53:02 PM PDT 23
Peak memory 215528 kb
Host smart-98deb38d-c19c-42f5-ad06-31a036c53367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383327337 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.3383327337
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_intr.1578648098
Short name T485
Test name
Test status
Simulation time 19536693 ps
CPU time 1.15 seconds
Started Oct 11 12:53:01 PM PDT 23
Finished Oct 11 12:53:03 PM PDT 23
Peak memory 221804 kb
Host smart-e093a6b0-378c-4918-ae0d-fbaa9d6b3180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578648098 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.1578648098
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_sec_cm.1965191834
Short name T23
Test name
Test status
Simulation time 248678456 ps
CPU time 4.07 seconds
Started Oct 11 12:51:30 PM PDT 23
Finished Oct 11 12:51:35 PM PDT 23
Peak memory 232228 kb
Host smart-2e201f7b-1224-4604-9bf6-06d7282b24bc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965191834 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.1965191834
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.1450755299
Short name T56
Test name
Test status
Simulation time 12455710 ps
CPU time 0.84 seconds
Started Oct 11 12:52:49 PM PDT 23
Finished Oct 11 12:52:50 PM PDT 23
Peak memory 204644 kb
Host smart-855a8ff2-71b3-4ff6-afbf-a24a5208440a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450755299 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.1450755299
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.3516268818
Short name T722
Test name
Test status
Simulation time 534238973 ps
CPU time 1.72 seconds
Started Oct 11 12:52:39 PM PDT 23
Finished Oct 11 12:52:42 PM PDT 23
Peak memory 205728 kb
Host smart-96c5f60e-1ba3-4f04-b438-2be2d70776cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516268818 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.3516268818
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.2678157214
Short name T640
Test name
Test status
Simulation time 254321893289 ps
CPU time 567.29 seconds
Started Oct 11 12:51:19 PM PDT 23
Finished Oct 11 01:00:47 PM PDT 23
Peak memory 214996 kb
Host smart-da5b98ca-ae20-496e-9d0b-2c842fc262ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678157214 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.2678157214
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.1275239202
Short name T612
Test name
Test status
Simulation time 53488034 ps
CPU time 0.92 seconds
Started Oct 11 12:51:50 PM PDT 23
Finished Oct 11 12:51:52 PM PDT 23
Peak memory 206128 kb
Host smart-9a42ffd7-c018-4e38-b1af-f7945bc7a274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275239202 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.1275239202
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.3191622791
Short name T581
Test name
Test status
Simulation time 13190198 ps
CPU time 0.84 seconds
Started Oct 11 12:51:42 PM PDT 23
Finished Oct 11 12:51:44 PM PDT 23
Peak memory 204568 kb
Host smart-70c9114f-0434-4ddd-a14c-f2ef477f53fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191622791 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.3191622791
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.1461530633
Short name T133
Test name
Test status
Simulation time 18355905 ps
CPU time 0.84 seconds
Started Oct 11 12:52:22 PM PDT 23
Finished Oct 11 12:52:23 PM PDT 23
Peak memory 214652 kb
Host smart-ab1be9cb-8638-4e85-b5e0-d50e88e7182b
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461530633 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.1461530633
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.61668664
Short name T26
Test name
Test status
Simulation time 22666463 ps
CPU time 0.94 seconds
Started Oct 11 12:52:34 PM PDT 23
Finished Oct 11 12:52:36 PM PDT 23
Peak memory 214676 kb
Host smart-0c7a17dc-0ec3-4fb8-8e6a-f76976125617
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61668664 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_dis
able_auto_req_mode.61668664
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.915747622
Short name T165
Test name
Test status
Simulation time 34818918 ps
CPU time 1.06 seconds
Started Oct 11 12:52:21 PM PDT 23
Finished Oct 11 12:52:23 PM PDT 23
Peak memory 214448 kb
Host smart-7ff6d3bb-2e82-4d8a-93c5-8c97c5b37761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915747622 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.915747622
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.122805354
Short name T278
Test name
Test status
Simulation time 35361285 ps
CPU time 0.94 seconds
Started Oct 11 12:51:42 PM PDT 23
Finished Oct 11 12:51:44 PM PDT 23
Peak memory 214348 kb
Host smart-d3def377-32be-4124-8721-7c9ac15492ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122805354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.122805354
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.1852218409
Short name T545
Test name
Test status
Simulation time 38011416 ps
CPU time 0.92 seconds
Started Oct 11 12:51:53 PM PDT 23
Finished Oct 11 12:51:55 PM PDT 23
Peak memory 221516 kb
Host smart-409bea23-a24a-42e8-9c24-4f62d5783745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852218409 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.1852218409
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.761994191
Short name T555
Test name
Test status
Simulation time 15252077 ps
CPU time 0.89 seconds
Started Oct 11 12:52:48 PM PDT 23
Finished Oct 11 12:52:50 PM PDT 23
Peak memory 204700 kb
Host smart-33214bfd-5948-44d7-a51a-dc3cfe160686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761994191 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.761994191
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.1322289155
Short name T560
Test name
Test status
Simulation time 152402130 ps
CPU time 3.46 seconds
Started Oct 11 12:51:48 PM PDT 23
Finished Oct 11 12:51:52 PM PDT 23
Peak memory 205960 kb
Host smart-40f38338-2667-47a0-b2e8-320c4375731d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322289155 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.1322289155
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.328764533
Short name T331
Test name
Test status
Simulation time 357383713866 ps
CPU time 1311.94 seconds
Started Oct 11 12:51:42 PM PDT 23
Finished Oct 11 01:13:35 PM PDT 23
Peak memory 216132 kb
Host smart-f6cd6c7c-d2c1-47f0-835b-a7f65c90d08f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328764533 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.328764533
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.edn_alert.2440729008
Short name T647
Test name
Test status
Simulation time 19292864 ps
CPU time 0.94 seconds
Started Oct 11 12:52:29 PM PDT 23
Finished Oct 11 12:52:30 PM PDT 23
Peak memory 205272 kb
Host smart-a19e7ca1-66fa-4dea-995f-5a9ababe1041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440729008 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.2440729008
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.851681182
Short name T90
Test name
Test status
Simulation time 43231457 ps
CPU time 0.74 seconds
Started Oct 11 12:52:21 PM PDT 23
Finished Oct 11 12:52:23 PM PDT 23
Peak memory 203164 kb
Host smart-f651aafb-2785-461b-9bd3-513a26acf872
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851681182 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.851681182
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.3718444847
Short name T478
Test name
Test status
Simulation time 38551391 ps
CPU time 0.97 seconds
Started Oct 11 12:52:54 PM PDT 23
Finished Oct 11 12:52:55 PM PDT 23
Peak memory 214708 kb
Host smart-20b946a5-a2f5-41ad-9721-b9734f26eb24
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718444847 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.3718444847
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.3248915853
Short name T247
Test name
Test status
Simulation time 66816419 ps
CPU time 1.01 seconds
Started Oct 11 12:52:25 PM PDT 23
Finished Oct 11 12:52:27 PM PDT 23
Peak memory 216984 kb
Host smart-6bbaca2c-af85-4a38-ab7f-497fc38fda70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248915853 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.3248915853
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.307705745
Short name T68
Test name
Test status
Simulation time 60175318 ps
CPU time 0.89 seconds
Started Oct 11 12:52:06 PM PDT 23
Finished Oct 11 12:52:07 PM PDT 23
Peak memory 205056 kb
Host smart-5cd2fb8f-85d3-4643-ae37-55c994718ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307705745 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.307705745
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.3126385600
Short name T114
Test name
Test status
Simulation time 21866725 ps
CPU time 0.9 seconds
Started Oct 11 12:52:46 PM PDT 23
Finished Oct 11 12:52:47 PM PDT 23
Peak memory 214812 kb
Host smart-d4b4e5d6-8ea1-4d39-bc2e-29c8f0f26398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126385600 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.3126385600
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.1258986886
Short name T513
Test name
Test status
Simulation time 23215663 ps
CPU time 0.84 seconds
Started Oct 11 12:52:16 PM PDT 23
Finished Oct 11 12:52:17 PM PDT 23
Peak memory 204712 kb
Host smart-d70b3e60-b060-4b0b-9757-8e6aa09e0cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258986886 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.1258986886
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.2205964806
Short name T489
Test name
Test status
Simulation time 125016707 ps
CPU time 3.01 seconds
Started Oct 11 12:53:23 PM PDT 23
Finished Oct 11 12:53:27 PM PDT 23
Peak memory 205696 kb
Host smart-a0875b34-acde-4ba9-adc2-7d154712dfa5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205964806 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.2205964806
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.2871236907
Short name T139
Test name
Test status
Simulation time 26581915919 ps
CPU time 529.48 seconds
Started Oct 11 12:52:29 PM PDT 23
Finished Oct 11 01:01:19 PM PDT 23
Peak memory 216080 kb
Host smart-a2923231-ef8b-4a66-9007-44320418439c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871236907 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.2871236907
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.edn_alert.263320020
Short name T300
Test name
Test status
Simulation time 66522472 ps
CPU time 0.9 seconds
Started Oct 11 12:52:39 PM PDT 23
Finished Oct 11 12:52:41 PM PDT 23
Peak memory 205004 kb
Host smart-6b869a1e-65b1-4c03-864e-d50888c4de45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263320020 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.263320020
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.2469525602
Short name T709
Test name
Test status
Simulation time 46974310 ps
CPU time 0.98 seconds
Started Oct 11 12:52:41 PM PDT 23
Finished Oct 11 12:52:42 PM PDT 23
Peak memory 204668 kb
Host smart-990b6d8b-de6d-4b90-a253-d1f143b36768
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469525602 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.2469525602
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.1675225385
Short name T106
Test name
Test status
Simulation time 30807120 ps
CPU time 0.78 seconds
Started Oct 11 12:52:42 PM PDT 23
Finished Oct 11 12:52:44 PM PDT 23
Peak memory 214456 kb
Host smart-bf23f023-f0c3-4043-a08a-af92076a0177
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675225385 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.1675225385
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.3574210039
Short name T99
Test name
Test status
Simulation time 21579676 ps
CPU time 0.99 seconds
Started Oct 11 12:52:27 PM PDT 23
Finished Oct 11 12:52:28 PM PDT 23
Peak memory 214724 kb
Host smart-0d1117c5-1089-4ed3-a472-6624de433f30
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574210039 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.3574210039
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.3784629126
Short name T318
Test name
Test status
Simulation time 105378602 ps
CPU time 1.11 seconds
Started Oct 11 12:52:59 PM PDT 23
Finished Oct 11 12:53:00 PM PDT 23
Peak memory 214652 kb
Host smart-d4a71c3a-e5db-494d-83aa-0ddc5b4e2b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784629126 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.3784629126
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_intr.1193612816
Short name T618
Test name
Test status
Simulation time 130344988 ps
CPU time 0.82 seconds
Started Oct 11 12:52:30 PM PDT 23
Finished Oct 11 12:52:31 PM PDT 23
Peak memory 214288 kb
Host smart-91d95232-9e39-41ce-9adf-cd5dbd04b975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193612816 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.1193612816
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.2388781366
Short name T335
Test name
Test status
Simulation time 36918231 ps
CPU time 0.86 seconds
Started Oct 11 12:52:47 PM PDT 23
Finished Oct 11 12:52:49 PM PDT 23
Peak memory 204804 kb
Host smart-b72e3680-43b5-4a25-9e02-99d7d3e46cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388781366 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.2388781366
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.1312791523
Short name T570
Test name
Test status
Simulation time 651104907 ps
CPU time 3.35 seconds
Started Oct 11 12:52:47 PM PDT 23
Finished Oct 11 12:52:51 PM PDT 23
Peak memory 205988 kb
Host smart-f8d8647e-0c18-469e-8e90-1b89876513b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312791523 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.1312791523
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.923913306
Short name T472
Test name
Test status
Simulation time 102373637009 ps
CPU time 1079.28 seconds
Started Oct 11 12:52:48 PM PDT 23
Finished Oct 11 01:10:49 PM PDT 23
Peak memory 215204 kb
Host smart-f274f058-4e26-4a1c-b36b-02844393b3f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923913306 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.923913306
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.edn_alert_test.745365850
Short name T495
Test name
Test status
Simulation time 22913702 ps
CPU time 0.81 seconds
Started Oct 11 12:52:54 PM PDT 23
Finished Oct 11 12:53:01 PM PDT 23
Peak memory 205068 kb
Host smart-0007c503-6976-4ff0-b269-23603c4b3d66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745365850 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.745365850
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.163448735
Short name T716
Test name
Test status
Simulation time 64680347 ps
CPU time 0.79 seconds
Started Oct 11 12:53:00 PM PDT 23
Finished Oct 11 12:53:02 PM PDT 23
Peak memory 214496 kb
Host smart-3cfaf39f-6857-4524-a090-2d911d845db1
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163448735 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.163448735
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_err.2921695726
Short name T613
Test name
Test status
Simulation time 18698139 ps
CPU time 1.31 seconds
Started Oct 11 12:53:05 PM PDT 23
Finished Oct 11 12:53:06 PM PDT 23
Peak memory 221564 kb
Host smart-329ba81c-5466-493f-8950-ed1a5975c3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921695726 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.2921695726
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.3541856146
Short name T287
Test name
Test status
Simulation time 35538237 ps
CPU time 0.99 seconds
Started Oct 11 12:52:58 PM PDT 23
Finished Oct 11 12:53:00 PM PDT 23
Peak memory 205124 kb
Host smart-f7615d8c-bcad-43b7-bb4f-07efe00c6674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541856146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.3541856146
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.2201336374
Short name T519
Test name
Test status
Simulation time 35490228 ps
CPU time 0.81 seconds
Started Oct 11 12:53:07 PM PDT 23
Finished Oct 11 12:53:08 PM PDT 23
Peak memory 214556 kb
Host smart-3218faf6-3e1c-4df1-bfe8-b99fa0f80eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201336374 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.2201336374
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.2982052704
Short name T69
Test name
Test status
Simulation time 22251828 ps
CPU time 0.82 seconds
Started Oct 11 12:52:53 PM PDT 23
Finished Oct 11 12:52:54 PM PDT 23
Peak memory 204804 kb
Host smart-670d7fb2-b1a8-452d-b9ef-231062341e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982052704 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.2982052704
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.2712359597
Short name T66
Test name
Test status
Simulation time 76050789 ps
CPU time 1.93 seconds
Started Oct 11 12:53:00 PM PDT 23
Finished Oct 11 12:53:03 PM PDT 23
Peak memory 206104 kb
Host smart-86436055-20ce-42d6-9706-df1ba1836c64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712359597 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.2712359597
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.1130185711
Short name T575
Test name
Test status
Simulation time 174174862125 ps
CPU time 1150.41 seconds
Started Oct 11 12:52:45 PM PDT 23
Finished Oct 11 01:11:57 PM PDT 23
Peak memory 216984 kb
Host smart-9ab44ca9-3e0c-4f62-b7ba-b94e424d316c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130185711 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.1130185711
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.edn_alert.1120163128
Short name T625
Test name
Test status
Simulation time 20497857 ps
CPU time 0.97 seconds
Started Oct 11 12:52:53 PM PDT 23
Finished Oct 11 12:52:55 PM PDT 23
Peak memory 205192 kb
Host smart-82b90ecf-ec21-42ee-9bd7-7979f8eb2d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120163128 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.1120163128
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.1367716091
Short name T544
Test name
Test status
Simulation time 16683789 ps
CPU time 0.9 seconds
Started Oct 11 12:54:12 PM PDT 23
Finished Oct 11 12:54:13 PM PDT 23
Peak memory 205252 kb
Host smart-f9d594a0-5e28-4bb4-aac6-aba2d05799d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367716091 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.1367716091
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_err.669974852
Short name T164
Test name
Test status
Simulation time 23294826 ps
CPU time 1.09 seconds
Started Oct 11 12:52:45 PM PDT 23
Finished Oct 11 12:52:46 PM PDT 23
Peak memory 214320 kb
Host smart-5ef21ccb-8fe3-49a8-b8ff-56e12afe36ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669974852 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.669974852
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.3276633925
Short name T36
Test name
Test status
Simulation time 41275083 ps
CPU time 0.97 seconds
Started Oct 11 12:52:54 PM PDT 23
Finished Oct 11 12:52:56 PM PDT 23
Peak memory 205524 kb
Host smart-b4728e96-2304-4293-b3fc-88986b9c839f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276633925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.3276633925
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.1978826470
Short name T703
Test name
Test status
Simulation time 44825471 ps
CPU time 0.79 seconds
Started Oct 11 12:52:45 PM PDT 23
Finished Oct 11 12:52:47 PM PDT 23
Peak memory 214344 kb
Host smart-ef183ef5-80d4-49af-94dd-5c9bc7a5efc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978826470 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.1978826470
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.4191422356
Short name T712
Test name
Test status
Simulation time 20094441 ps
CPU time 0.79 seconds
Started Oct 11 12:52:51 PM PDT 23
Finished Oct 11 12:52:53 PM PDT 23
Peak memory 204844 kb
Host smart-77434c33-c731-49d1-95a5-cab73eb94589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191422356 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.4191422356
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.4178228343
Short name T538
Test name
Test status
Simulation time 247561044 ps
CPU time 1.79 seconds
Started Oct 11 12:52:56 PM PDT 23
Finished Oct 11 12:52:58 PM PDT 23
Peak memory 205636 kb
Host smart-1f19a345-1430-4efb-9991-d3416af0d0fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178228343 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.4178228343
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.2179155551
Short name T628
Test name
Test status
Simulation time 106066911850 ps
CPU time 1338.79 seconds
Started Oct 11 12:53:05 PM PDT 23
Finished Oct 11 01:15:25 PM PDT 23
Peak memory 219684 kb
Host smart-27c3ea9a-2eb2-4f4a-aef4-e8fa6510c6f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179155551 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.2179155551
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.edn_alert.3942429950
Short name T509
Test name
Test status
Simulation time 31685499 ps
CPU time 0.93 seconds
Started Oct 11 12:53:33 PM PDT 23
Finished Oct 11 12:53:34 PM PDT 23
Peak memory 205056 kb
Host smart-13e21151-ca98-4ed3-ab2c-53f76358fcc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942429950 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.3942429950
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.1542687950
Short name T694
Test name
Test status
Simulation time 20293346 ps
CPU time 0.78 seconds
Started Oct 11 12:52:33 PM PDT 23
Finished Oct 11 12:52:34 PM PDT 23
Peak memory 204280 kb
Host smart-2d86a68f-9eba-41b5-b0f6-2c016b183d61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542687950 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.1542687950
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.3364032703
Short name T658
Test name
Test status
Simulation time 40041548 ps
CPU time 0.81 seconds
Started Oct 11 12:52:28 PM PDT 23
Finished Oct 11 12:52:29 PM PDT 23
Peak memory 214344 kb
Host smart-cff53934-6d98-49a4-8d8d-7fb5e3fe7bbb
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364032703 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.3364032703
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.1022549219
Short name T88
Test name
Test status
Simulation time 27669066 ps
CPU time 0.94 seconds
Started Oct 11 12:53:23 PM PDT 23
Finished Oct 11 12:53:25 PM PDT 23
Peak memory 214692 kb
Host smart-fc62f681-ceb4-4de4-b897-9cb37580fb42
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022549219 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.1022549219
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.2734987035
Short name T195
Test name
Test status
Simulation time 41637942 ps
CPU time 0.8 seconds
Started Oct 11 12:53:07 PM PDT 23
Finished Oct 11 12:53:09 PM PDT 23
Peak memory 215664 kb
Host smart-97e79895-581a-434c-a791-c2996dcf3fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734987035 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.2734987035
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.3226069372
Short name T455
Test name
Test status
Simulation time 178715860 ps
CPU time 0.84 seconds
Started Oct 11 12:52:55 PM PDT 23
Finished Oct 11 12:52:56 PM PDT 23
Peak memory 205044 kb
Host smart-5b234d2b-b2af-4012-aafa-dc6cf2e6b90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226069372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3226069372
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.2943549281
Short name T695
Test name
Test status
Simulation time 18772616 ps
CPU time 1.09 seconds
Started Oct 11 12:52:40 PM PDT 23
Finished Oct 11 12:52:42 PM PDT 23
Peak memory 221608 kb
Host smart-8645ec83-5671-42fb-bdb8-fb8a7bf32599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943549281 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.2943549281
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.118546589
Short name T533
Test name
Test status
Simulation time 42753491 ps
CPU time 0.81 seconds
Started Oct 11 12:53:09 PM PDT 23
Finished Oct 11 12:53:10 PM PDT 23
Peak memory 204880 kb
Host smart-d208d897-cedf-4fb6-a0cf-d8ca227faf39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118546589 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.118546589
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.1218146573
Short name T51
Test name
Test status
Simulation time 125933345 ps
CPU time 2.81 seconds
Started Oct 11 12:52:50 PM PDT 23
Finished Oct 11 12:52:53 PM PDT 23
Peak memory 205948 kb
Host smart-7ba409ad-3368-4d43-90b1-2e0698f01f78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218146573 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.1218146573
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.2973382677
Short name T562
Test name
Test status
Simulation time 236908616047 ps
CPU time 1019.17 seconds
Started Oct 11 12:53:11 PM PDT 23
Finished Oct 11 01:10:11 PM PDT 23
Peak memory 214852 kb
Host smart-511bf395-c6e2-43a5-bf5a-901651886b7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973382677 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.2973382677
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.edn_alert.3856299654
Short name T592
Test name
Test status
Simulation time 36680417 ps
CPU time 1 seconds
Started Oct 11 12:53:04 PM PDT 23
Finished Oct 11 12:53:05 PM PDT 23
Peak memory 206064 kb
Host smart-7efbe126-694d-4a83-b5d3-fd13ccd593e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856299654 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.3856299654
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.3541094310
Short name T572
Test name
Test status
Simulation time 25117816 ps
CPU time 1.06 seconds
Started Oct 11 12:52:20 PM PDT 23
Finished Oct 11 12:52:22 PM PDT 23
Peak memory 204656 kb
Host smart-3ddfeeaa-4d57-494a-b1d6-73a6345887c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541094310 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.3541094310
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.1190291042
Short name T122
Test name
Test status
Simulation time 15899416 ps
CPU time 0.77 seconds
Started Oct 11 12:52:48 PM PDT 23
Finished Oct 11 12:52:50 PM PDT 23
Peak memory 214532 kb
Host smart-0bbd06a3-0ef0-4a6c-b876-5e48d72b22f2
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190291042 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.1190291042
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.2079065780
Short name T714
Test name
Test status
Simulation time 49683055 ps
CPU time 0.98 seconds
Started Oct 11 12:52:09 PM PDT 23
Finished Oct 11 12:52:10 PM PDT 23
Peak memory 214596 kb
Host smart-fe3a1375-d4e1-4860-be3c-3f2465e9f14a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079065780 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.2079065780
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.3013439076
Short name T571
Test name
Test status
Simulation time 18526545 ps
CPU time 1.24 seconds
Started Oct 11 12:52:33 PM PDT 23
Finished Oct 11 12:52:35 PM PDT 23
Peak memory 215796 kb
Host smart-a039a6a9-75df-44d3-80fc-ab7ebc310496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013439076 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.3013439076
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.3389509506
Short name T619
Test name
Test status
Simulation time 36996224 ps
CPU time 0.89 seconds
Started Oct 11 12:53:03 PM PDT 23
Finished Oct 11 12:53:04 PM PDT 23
Peak memory 205400 kb
Host smart-fd7f3b41-866e-4b16-a6ea-c357609b597f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389509506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.3389509506
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.1624146753
Short name T333
Test name
Test status
Simulation time 75197997 ps
CPU time 0.81 seconds
Started Oct 11 12:52:15 PM PDT 23
Finished Oct 11 12:52:17 PM PDT 23
Peak memory 214348 kb
Host smart-e4ab9523-ba9a-4408-9db7-9720a5312fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624146753 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.1624146753
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.97651508
Short name T317
Test name
Test status
Simulation time 36789624 ps
CPU time 0.84 seconds
Started Oct 11 12:52:52 PM PDT 23
Finished Oct 11 12:52:53 PM PDT 23
Peak memory 204716 kb
Host smart-8b434fd8-dc94-4b5e-ad8f-11868723e0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97651508 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.97651508
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.3017668104
Short name T522
Test name
Test status
Simulation time 160002780 ps
CPU time 3.25 seconds
Started Oct 11 12:52:25 PM PDT 23
Finished Oct 11 12:52:39 PM PDT 23
Peak memory 206116 kb
Host smart-3f3e8494-89bd-41c4-98a9-ab7c65893edb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017668104 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3017668104
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.1663284208
Short name T92
Test name
Test status
Simulation time 58314057540 ps
CPU time 375.06 seconds
Started Oct 11 12:52:15 PM PDT 23
Finished Oct 11 12:58:30 PM PDT 23
Peak memory 214772 kb
Host smart-114cff3a-b504-4cea-9a72-f28b2e2e2184
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663284208 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.1663284208
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.edn_alert.3932255545
Short name T605
Test name
Test status
Simulation time 21574278 ps
CPU time 0.99 seconds
Started Oct 11 12:52:32 PM PDT 23
Finished Oct 11 12:52:34 PM PDT 23
Peak memory 205256 kb
Host smart-71a7de42-b133-43e4-b869-356f6e6a6c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932255545 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.3932255545
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.1403868678
Short name T704
Test name
Test status
Simulation time 21402375 ps
CPU time 0.82 seconds
Started Oct 11 12:52:31 PM PDT 23
Finished Oct 11 12:52:33 PM PDT 23
Peak memory 204092 kb
Host smart-434b5094-d53e-43db-8841-5b7352b35329
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403868678 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1403868678
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.2998732426
Short name T607
Test name
Test status
Simulation time 22823791 ps
CPU time 0.79 seconds
Started Oct 11 12:52:54 PM PDT 23
Finished Oct 11 12:52:56 PM PDT 23
Peak memory 214352 kb
Host smart-ab19a422-3978-4ff6-a2b0-f41f2499381a
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998732426 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.2998732426
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.1406261596
Short name T107
Test name
Test status
Simulation time 102035795 ps
CPU time 1 seconds
Started Oct 11 12:52:14 PM PDT 23
Finished Oct 11 12:52:21 PM PDT 23
Peak memory 214600 kb
Host smart-e0898b91-36f1-49e9-bb39-f37d192d5b34
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406261596 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.1406261596
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.2260056828
Short name T3
Test name
Test status
Simulation time 31806775 ps
CPU time 0.85 seconds
Started Oct 11 12:52:47 PM PDT 23
Finished Oct 11 12:52:49 PM PDT 23
Peak memory 214308 kb
Host smart-a505024d-866d-4eaf-a036-49fd50b89bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260056828 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.2260056828
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.2250569677
Short name T593
Test name
Test status
Simulation time 165136184 ps
CPU time 0.91 seconds
Started Oct 11 12:52:40 PM PDT 23
Finished Oct 11 12:52:41 PM PDT 23
Peak memory 205224 kb
Host smart-a3fdd22c-6f28-482c-8a9e-05d6dd2ebd3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250569677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.2250569677
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.2534634127
Short name T710
Test name
Test status
Simulation time 18574676 ps
CPU time 1.03 seconds
Started Oct 11 12:52:19 PM PDT 23
Finished Oct 11 12:52:20 PM PDT 23
Peak memory 214540 kb
Host smart-f89c50c1-e9c6-4987-abdb-c3212d8515cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534634127 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.2534634127
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.2782184269
Short name T477
Test name
Test status
Simulation time 14254272 ps
CPU time 0.85 seconds
Started Oct 11 12:52:21 PM PDT 23
Finished Oct 11 12:52:22 PM PDT 23
Peak memory 204636 kb
Host smart-e5683b52-7ff0-4bc3-a33e-fcbbf90ff378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782184269 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.2782184269
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.2882436901
Short name T493
Test name
Test status
Simulation time 98013894 ps
CPU time 2.43 seconds
Started Oct 11 12:52:25 PM PDT 23
Finished Oct 11 12:52:28 PM PDT 23
Peak memory 205676 kb
Host smart-eb975034-fee5-441d-980c-eac718c62143
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882436901 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.2882436901
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.1440522302
Short name T656
Test name
Test status
Simulation time 190948906128 ps
CPU time 2066.06 seconds
Started Oct 11 12:52:40 PM PDT 23
Finished Oct 11 01:27:07 PM PDT 23
Peak memory 220888 kb
Host smart-9b9cf971-4c20-4049-9943-c7467d5433a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440522302 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.1440522302
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.edn_alert.35096901
Short name T87
Test name
Test status
Simulation time 66786029 ps
CPU time 1 seconds
Started Oct 11 12:53:02 PM PDT 23
Finished Oct 11 12:53:04 PM PDT 23
Peak memory 205124 kb
Host smart-db37fb03-286e-4991-8856-2d8bdacd37d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35096901 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.35096901
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.1153991500
Short name T673
Test name
Test status
Simulation time 19082127 ps
CPU time 0.92 seconds
Started Oct 11 12:52:58 PM PDT 23
Finished Oct 11 12:52:59 PM PDT 23
Peak memory 204564 kb
Host smart-d28014ed-d748-458b-a6eb-6c820b0559c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153991500 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.1153991500
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.1260546390
Short name T43
Test name
Test status
Simulation time 39233833 ps
CPU time 0.83 seconds
Started Oct 11 12:52:43 PM PDT 23
Finished Oct 11 12:52:44 PM PDT 23
Peak memory 214484 kb
Host smart-1559eb58-55ca-43f7-917e-f714ab6c7a65
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260546390 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1260546390
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.267249953
Short name T702
Test name
Test status
Simulation time 37032560 ps
CPU time 0.89 seconds
Started Oct 11 12:53:03 PM PDT 23
Finished Oct 11 12:53:04 PM PDT 23
Peak memory 214684 kb
Host smart-46dab7d7-3e53-4a67-b023-66f0761b8bed
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267249953 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_di
sable_auto_req_mode.267249953
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.380775681
Short name T517
Test name
Test status
Simulation time 28945106 ps
CPU time 1 seconds
Started Oct 11 12:53:52 PM PDT 23
Finished Oct 11 12:53:53 PM PDT 23
Peak memory 221824 kb
Host smart-84ee3126-db91-466d-aaf6-c75bd8ae7194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380775681 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.380775681
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.4087684776
Short name T270
Test name
Test status
Simulation time 22557523 ps
CPU time 0.86 seconds
Started Oct 11 12:52:28 PM PDT 23
Finished Oct 11 12:52:29 PM PDT 23
Peak memory 204916 kb
Host smart-7d7b3c66-5491-4c7e-accf-0de689a9f2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087684776 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.4087684776
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.3824529722
Short name T501
Test name
Test status
Simulation time 28699281 ps
CPU time 0.8 seconds
Started Oct 11 12:52:34 PM PDT 23
Finished Oct 11 12:52:35 PM PDT 23
Peak memory 214664 kb
Host smart-c1e13df5-743f-4f62-8786-ee8d56f66378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824529722 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.3824529722
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.2887787533
Short name T678
Test name
Test status
Simulation time 14594009 ps
CPU time 0.87 seconds
Started Oct 11 12:52:28 PM PDT 23
Finished Oct 11 12:52:30 PM PDT 23
Peak memory 204712 kb
Host smart-0d9437b9-ef1a-4d18-873c-cae585ff1b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887787533 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.2887787533
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.3087362173
Short name T621
Test name
Test status
Simulation time 145322749 ps
CPU time 1.06 seconds
Started Oct 11 12:52:52 PM PDT 23
Finished Oct 11 12:52:54 PM PDT 23
Peak memory 205340 kb
Host smart-b8533c16-963f-4794-a7da-bd7ee54c0140
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087362173 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.3087362173
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.509221427
Short name T666
Test name
Test status
Simulation time 31314784699 ps
CPU time 660.53 seconds
Started Oct 11 12:52:50 PM PDT 23
Finished Oct 11 01:03:51 PM PDT 23
Peak memory 215560 kb
Host smart-46f79167-c1c7-4a08-8172-710a7f7ac7a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509221427 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.509221427
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.edn_alert_test.3617042520
Short name T663
Test name
Test status
Simulation time 49486133 ps
CPU time 0.82 seconds
Started Oct 11 12:53:19 PM PDT 23
Finished Oct 11 12:53:20 PM PDT 23
Peak memory 205204 kb
Host smart-467c6877-57f3-45cf-b34c-c6ccff7a50bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617042520 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.3617042520
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.3400613370
Short name T100
Test name
Test status
Simulation time 21720551 ps
CPU time 0.96 seconds
Started Oct 11 12:53:18 PM PDT 23
Finished Oct 11 12:53:19 PM PDT 23
Peak memory 214620 kb
Host smart-ac347089-8133-4d88-9e7a-9f9e9508f054
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400613370 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.3400613370
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.2624943982
Short name T653
Test name
Test status
Simulation time 71999255 ps
CPU time 1 seconds
Started Oct 11 12:53:06 PM PDT 23
Finished Oct 11 12:53:08 PM PDT 23
Peak memory 216828 kb
Host smart-0aad2b3d-0606-471f-bd2d-5f8dae191c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624943982 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.2624943982
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.1127372872
Short name T40
Test name
Test status
Simulation time 61241173 ps
CPU time 1.2 seconds
Started Oct 11 12:52:52 PM PDT 23
Finished Oct 11 12:52:54 PM PDT 23
Peak memory 205228 kb
Host smart-d61e3876-7046-442c-8971-471a8e306cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127372872 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.1127372872
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.2330298187
Short name T679
Test name
Test status
Simulation time 103700179 ps
CPU time 0.91 seconds
Started Oct 11 12:52:31 PM PDT 23
Finished Oct 11 12:52:33 PM PDT 23
Peak memory 224768 kb
Host smart-36cd3cfd-46f7-4eee-845e-ee525c5a96bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330298187 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.2330298187
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.1593359379
Short name T717
Test name
Test status
Simulation time 33406902 ps
CPU time 0.79 seconds
Started Oct 11 12:52:54 PM PDT 23
Finished Oct 11 12:52:56 PM PDT 23
Peak memory 204528 kb
Host smart-aeb5a521-0941-4aca-bbdb-d190c5dcbd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593359379 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.1593359379
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.3697882772
Short name T70
Test name
Test status
Simulation time 469488833 ps
CPU time 2.72 seconds
Started Oct 11 12:52:31 PM PDT 23
Finished Oct 11 12:52:35 PM PDT 23
Peak memory 206356 kb
Host smart-389469b6-cace-431e-b790-72c3223f9e3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697882772 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.3697882772
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_alert.4110654730
Short name T101
Test name
Test status
Simulation time 42921323 ps
CPU time 0.87 seconds
Started Oct 11 12:51:30 PM PDT 23
Finished Oct 11 12:51:32 PM PDT 23
Peak memory 205316 kb
Host smart-160c2c9e-8c36-49c4-83ca-feea27d3910c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110654730 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.4110654730
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.153075998
Short name T498
Test name
Test status
Simulation time 25043689 ps
CPU time 0.84 seconds
Started Oct 11 12:51:27 PM PDT 23
Finished Oct 11 12:51:28 PM PDT 23
Peak memory 204656 kb
Host smart-7afcac79-d194-4ea9-9d08-578b4ee47d5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153075998 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.153075998
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.3031138347
Short name T190
Test name
Test status
Simulation time 38406174 ps
CPU time 0.83 seconds
Started Oct 11 12:51:09 PM PDT 23
Finished Oct 11 12:51:10 PM PDT 23
Peak memory 214396 kb
Host smart-ca965e01-3c5d-4726-94e7-cfa6b15aa0d6
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031138347 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.3031138347
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.2213871713
Short name T10
Test name
Test status
Simulation time 28190215 ps
CPU time 0.97 seconds
Started Oct 11 12:51:30 PM PDT 23
Finished Oct 11 12:51:31 PM PDT 23
Peak memory 214552 kb
Host smart-9aa46438-dbd6-49c9-ba72-998143c9603f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213871713 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.2213871713
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.1472745643
Short name T198
Test name
Test status
Simulation time 31173191 ps
CPU time 0.78 seconds
Started Oct 11 12:52:27 PM PDT 23
Finished Oct 11 12:52:28 PM PDT 23
Peak memory 215308 kb
Host smart-53377e7e-689e-48e0-aced-33c28903d82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472745643 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.1472745643
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_intr.2119438692
Short name T681
Test name
Test status
Simulation time 23891365 ps
CPU time 1 seconds
Started Oct 11 12:51:28 PM PDT 23
Finished Oct 11 12:51:29 PM PDT 23
Peak memory 225480 kb
Host smart-49187bde-6e0d-4aef-912f-06a3062d4dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119438692 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.2119438692
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.4092805389
Short name T259
Test name
Test status
Simulation time 32993375 ps
CPU time 0.87 seconds
Started Oct 11 12:52:27 PM PDT 23
Finished Oct 11 12:52:28 PM PDT 23
Peak memory 204740 kb
Host smart-d4eed13d-ca01-45ea-a664-407d57e1f8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092805389 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.4092805389
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.1373789290
Short name T55
Test name
Test status
Simulation time 319422984 ps
CPU time 3.02 seconds
Started Oct 11 12:51:28 PM PDT 23
Finished Oct 11 12:51:32 PM PDT 23
Peak memory 233424 kb
Host smart-d5127ca0-a02e-41ce-9b73-4dd7d07ed28e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373789290 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.1373789290
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.2651915419
Short name T469
Test name
Test status
Simulation time 236377042 ps
CPU time 0.88 seconds
Started Oct 11 12:51:26 PM PDT 23
Finished Oct 11 12:51:28 PM PDT 23
Peak memory 204824 kb
Host smart-b561f193-0e75-41b8-8448-3e75a56b3e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651915419 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.2651915419
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.33258329
Short name T157
Test name
Test status
Simulation time 117715978 ps
CPU time 2.64 seconds
Started Oct 11 12:51:33 PM PDT 23
Finished Oct 11 12:51:36 PM PDT 23
Peak memory 205780 kb
Host smart-933dce24-1ac6-4f28-ad86-4fe6b5b113c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33258329 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.33258329
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.2063055817
Short name T648
Test name
Test status
Simulation time 17512011833 ps
CPU time 393.47 seconds
Started Oct 11 12:52:18 PM PDT 23
Finished Oct 11 12:58:52 PM PDT 23
Peak memory 214732 kb
Host smart-6ec3b16a-9aaf-41dc-9cd8-6afb42c24338
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063055817 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.2063055817
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.906952425
Short name T706
Test name
Test status
Simulation time 17751973 ps
CPU time 0.94 seconds
Started Oct 11 12:52:56 PM PDT 23
Finished Oct 11 12:52:58 PM PDT 23
Peak memory 205056 kb
Host smart-9a2da05b-d458-43d5-a0f6-7e7b2f53d936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906952425 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.906952425
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.1100763508
Short name T705
Test name
Test status
Simulation time 26101613 ps
CPU time 0.86 seconds
Started Oct 11 12:52:38 PM PDT 23
Finished Oct 11 12:52:40 PM PDT 23
Peak memory 205520 kb
Host smart-2c59790a-fc1d-4b16-b448-0657b400afa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100763508 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.1100763508
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.3250992544
Short name T583
Test name
Test status
Simulation time 12969663 ps
CPU time 0.87 seconds
Started Oct 11 12:52:56 PM PDT 23
Finished Oct 11 12:52:58 PM PDT 23
Peak memory 214536 kb
Host smart-8a2a0cc5-fe28-4111-b347-161cd7134277
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250992544 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.3250992544
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.2282973259
Short name T594
Test name
Test status
Simulation time 89680368 ps
CPU time 1 seconds
Started Oct 11 12:52:45 PM PDT 23
Finished Oct 11 12:52:47 PM PDT 23
Peak memory 214624 kb
Host smart-e5f2af57-ce43-4f8d-b653-8eac9d30850e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282973259 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.2282973259
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.1758072666
Short name T529
Test name
Test status
Simulation time 36804099 ps
CPU time 1.4 seconds
Started Oct 11 12:52:46 PM PDT 23
Finished Oct 11 12:52:48 PM PDT 23
Peak memory 227768 kb
Host smart-7baef2ed-83e0-44ad-a7ff-97f8553b9d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758072666 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.1758072666
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.2291844759
Short name T659
Test name
Test status
Simulation time 35886198 ps
CPU time 1.54 seconds
Started Oct 11 12:52:55 PM PDT 23
Finished Oct 11 12:52:57 PM PDT 23
Peak memory 214316 kb
Host smart-7a842351-8388-43a9-a0e2-23951f25f754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291844759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.2291844759
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.555441183
Short name T609
Test name
Test status
Simulation time 22022517 ps
CPU time 1 seconds
Started Oct 11 12:52:38 PM PDT 23
Finished Oct 11 12:52:40 PM PDT 23
Peak memory 214492 kb
Host smart-58dfa710-c6d9-4fba-8684-af2f1dee5a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555441183 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.555441183
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.262588469
Short name T324
Test name
Test status
Simulation time 23957013 ps
CPU time 0.83 seconds
Started Oct 11 12:52:33 PM PDT 23
Finished Oct 11 12:52:35 PM PDT 23
Peak memory 205120 kb
Host smart-ac54570e-646e-4adf-8c19-94c6b47e0c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262588469 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.262588469
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.1495267516
Short name T315
Test name
Test status
Simulation time 466944020 ps
CPU time 2.93 seconds
Started Oct 11 12:52:40 PM PDT 23
Finished Oct 11 12:52:44 PM PDT 23
Peak memory 205932 kb
Host smart-162d9e4c-cc2f-4f9c-8af0-79ee4e3197d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495267516 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.1495267516
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.3295361067
Short name T715
Test name
Test status
Simulation time 394891836201 ps
CPU time 2378.11 seconds
Started Oct 11 12:52:59 PM PDT 23
Finished Oct 11 01:32:37 PM PDT 23
Peak memory 225260 kb
Host smart-567435bd-bcb8-4745-aec9-208d55e4aedc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295361067 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.3295361067
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.3480053432
Short name T81
Test name
Test status
Simulation time 55749794 ps
CPU time 0.91 seconds
Started Oct 11 12:52:12 PM PDT 23
Finished Oct 11 12:52:14 PM PDT 23
Peak memory 206156 kb
Host smart-e82e6f5c-e342-444f-8262-c864dd674435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480053432 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.3480053432
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.452924825
Short name T162
Test name
Test status
Simulation time 38748163 ps
CPU time 0.87 seconds
Started Oct 11 12:52:11 PM PDT 23
Finished Oct 11 12:52:12 PM PDT 23
Peak memory 205192 kb
Host smart-b23cfda0-57b9-4363-a214-3022e362a443
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452924825 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.452924825
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.1953089604
Short name T334
Test name
Test status
Simulation time 72068444 ps
CPU time 0.93 seconds
Started Oct 11 12:52:35 PM PDT 23
Finished Oct 11 12:52:36 PM PDT 23
Peak memory 214584 kb
Host smart-d0efd5b4-49af-4db3-bfdf-103e1ce5b270
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953089604 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.1953089604
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.3454202872
Short name T325
Test name
Test status
Simulation time 22581645 ps
CPU time 0.95 seconds
Started Oct 11 12:52:32 PM PDT 23
Finished Oct 11 12:52:34 PM PDT 23
Peak memory 215580 kb
Host smart-ebd48f50-fef9-4bc9-bd39-df5623e42bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454202872 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.3454202872
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.4255818316
Short name T97
Test name
Test status
Simulation time 43421242 ps
CPU time 1.14 seconds
Started Oct 11 12:53:02 PM PDT 23
Finished Oct 11 12:53:04 PM PDT 23
Peak memory 205264 kb
Host smart-b27f0951-d247-4607-ae20-1eb530bfa6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255818316 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.4255818316
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.2779917336
Short name T696
Test name
Test status
Simulation time 30980257 ps
CPU time 0.81 seconds
Started Oct 11 12:52:38 PM PDT 23
Finished Oct 11 12:52:39 PM PDT 23
Peak memory 214548 kb
Host smart-276f2d33-4673-40fb-b32f-c9531a67df2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779917336 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.2779917336
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.2774826239
Short name T71
Test name
Test status
Simulation time 89621207 ps
CPU time 0.83 seconds
Started Oct 11 12:52:36 PM PDT 23
Finished Oct 11 12:52:38 PM PDT 23
Peak memory 204696 kb
Host smart-99358df9-0c5f-4294-9aa6-a2ecf5919861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774826239 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.2774826239
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.4031218506
Short name T67
Test name
Test status
Simulation time 21664247 ps
CPU time 1.02 seconds
Started Oct 11 12:52:59 PM PDT 23
Finished Oct 11 12:53:02 PM PDT 23
Peak memory 204944 kb
Host smart-eb047b20-777f-4501-8347-0ac377e5cf3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031218506 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.4031218506
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.51137038
Short name T85
Test name
Test status
Simulation time 106421158883 ps
CPU time 588.66 seconds
Started Oct 11 12:52:19 PM PDT 23
Finished Oct 11 01:02:08 PM PDT 23
Peak memory 214684 kb
Host smart-f1077ffe-9fd9-4d48-b200-1642ac6e4af4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51137038 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.51137038
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.1920233885
Short name T723
Test name
Test status
Simulation time 27161539 ps
CPU time 0.96 seconds
Started Oct 11 12:52:49 PM PDT 23
Finished Oct 11 12:52:50 PM PDT 23
Peak memory 206084 kb
Host smart-8147a115-e07e-46b0-9221-1b0e00bf085e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920233885 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.1920233885
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.1522881282
Short name T155
Test name
Test status
Simulation time 40692742 ps
CPU time 0.78 seconds
Started Oct 11 12:52:39 PM PDT 23
Finished Oct 11 12:52:40 PM PDT 23
Peak memory 204372 kb
Host smart-ef294302-2524-4519-a9fd-2ee310e1a949
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522881282 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.1522881282
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.249569736
Short name T93
Test name
Test status
Simulation time 35323095 ps
CPU time 0.77 seconds
Started Oct 11 12:52:12 PM PDT 23
Finished Oct 11 12:52:13 PM PDT 23
Peak memory 214636 kb
Host smart-8128c86d-f2c3-4640-b05d-21929271a776
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249569736 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.249569736
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.2099859670
Short name T27
Test name
Test status
Simulation time 43986415 ps
CPU time 0.94 seconds
Started Oct 11 12:52:41 PM PDT 23
Finished Oct 11 12:52:42 PM PDT 23
Peak memory 214604 kb
Host smart-289e195c-6e8f-4865-ad1d-6e1fdf230681
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099859670 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.2099859670
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.2108473099
Short name T630
Test name
Test status
Simulation time 31849252 ps
CPU time 1.01 seconds
Started Oct 11 12:53:41 PM PDT 23
Finished Oct 11 12:53:43 PM PDT 23
Peak memory 216024 kb
Host smart-0a6c12fa-6310-4cfc-8bba-0d7da3f0f9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108473099 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.2108473099
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.3032303151
Short name T41
Test name
Test status
Simulation time 42623577 ps
CPU time 1.37 seconds
Started Oct 11 12:52:41 PM PDT 23
Finished Oct 11 12:52:43 PM PDT 23
Peak memory 205588 kb
Host smart-c3f2fc7f-6189-466b-9ae9-ed79e505f66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032303151 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.3032303151
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.3643229658
Short name T692
Test name
Test status
Simulation time 30696987 ps
CPU time 0.8 seconds
Started Oct 11 12:52:46 PM PDT 23
Finished Oct 11 12:52:47 PM PDT 23
Peak memory 214484 kb
Host smart-855d4512-c9d6-4ee5-996d-9daa9d9147eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643229658 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.3643229658
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.4008496881
Short name T507
Test name
Test status
Simulation time 100562683 ps
CPU time 0.82 seconds
Started Oct 11 12:52:22 PM PDT 23
Finished Oct 11 12:52:25 PM PDT 23
Peak memory 204656 kb
Host smart-b5ca4467-393f-402a-a09e-0209003f0532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008496881 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.4008496881
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.62416873
Short name T52
Test name
Test status
Simulation time 120795711 ps
CPU time 2.85 seconds
Started Oct 11 12:52:46 PM PDT 23
Finished Oct 11 12:52:49 PM PDT 23
Peak memory 205372 kb
Host smart-c2711aea-653e-4192-9797-a4ccfd076f67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62416873 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.62416873
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_alert.3103099198
Short name T15
Test name
Test status
Simulation time 34254393 ps
CPU time 0.91 seconds
Started Oct 11 12:52:30 PM PDT 23
Finished Oct 11 12:52:31 PM PDT 23
Peak memory 205052 kb
Host smart-ef5a583b-dd7f-4e6e-aca7-5a8ee8d582fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103099198 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.3103099198
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.3041417222
Short name T568
Test name
Test status
Simulation time 196249508 ps
CPU time 0.82 seconds
Started Oct 11 12:52:16 PM PDT 23
Finished Oct 11 12:52:18 PM PDT 23
Peak memory 204660 kb
Host smart-ab8cc1d5-344a-49ba-beb1-7bc576624075
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041417222 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.3041417222
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.3726451074
Short name T79
Test name
Test status
Simulation time 10739469 ps
CPU time 0.84 seconds
Started Oct 11 12:52:48 PM PDT 23
Finished Oct 11 12:52:54 PM PDT 23
Peak memory 214392 kb
Host smart-46df5051-8bf1-4556-a285-714afd93df40
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726451074 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.3726451074
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.1275553761
Short name T627
Test name
Test status
Simulation time 63836053 ps
CPU time 0.94 seconds
Started Oct 11 12:52:46 PM PDT 23
Finished Oct 11 12:52:53 PM PDT 23
Peak memory 214724 kb
Host smart-f14f90b5-c3e5-456a-af3d-13377d6bd05a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275553761 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.1275553761
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.594606011
Short name T181
Test name
Test status
Simulation time 31090166 ps
CPU time 1.02 seconds
Started Oct 11 12:52:24 PM PDT 23
Finished Oct 11 12:52:26 PM PDT 23
Peak memory 214516 kb
Host smart-f8d9fa79-533f-4e36-aa5d-c836f31dc0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594606011 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.594606011
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.14615450
Short name T700
Test name
Test status
Simulation time 26475148 ps
CPU time 1.17 seconds
Started Oct 11 12:52:26 PM PDT 23
Finished Oct 11 12:52:28 PM PDT 23
Peak memory 214476 kb
Host smart-6c1dd504-ecc4-4311-974a-99f8312e9658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14615450 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.14615450
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.3779176612
Short name T117
Test name
Test status
Simulation time 18431640 ps
CPU time 0.97 seconds
Started Oct 11 12:52:26 PM PDT 23
Finished Oct 11 12:52:27 PM PDT 23
Peak memory 214900 kb
Host smart-ae46932f-b6ad-405f-a3bd-ae190e31c594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779176612 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.3779176612
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.763578934
Short name T682
Test name
Test status
Simulation time 12977966 ps
CPU time 0.87 seconds
Started Oct 11 12:52:38 PM PDT 23
Finished Oct 11 12:52:40 PM PDT 23
Peak memory 204872 kb
Host smart-0e6f2d7f-6b9b-43e3-b48b-0d8b0aa0c93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763578934 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.763578934
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.110814258
Short name T671
Test name
Test status
Simulation time 55738001 ps
CPU time 1.54 seconds
Started Oct 11 12:52:41 PM PDT 23
Finished Oct 11 12:52:43 PM PDT 23
Peak memory 205556 kb
Host smart-8c4af40a-b5cd-4db7-83b3-b3891a9c5b6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110814258 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.110814258
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.3551950024
Short name T532
Test name
Test status
Simulation time 247152966091 ps
CPU time 1400.49 seconds
Started Oct 11 12:52:54 PM PDT 23
Finished Oct 11 01:16:15 PM PDT 23
Peak memory 218040 kb
Host smart-f193d0a4-97fc-4f0b-8283-07dde50f83ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551950024 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.3551950024
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.1924671966
Short name T256
Test name
Test status
Simulation time 37494321 ps
CPU time 0.97 seconds
Started Oct 11 12:52:42 PM PDT 23
Finished Oct 11 12:52:43 PM PDT 23
Peak memory 205280 kb
Host smart-bb2cbc9c-5294-4bf9-9a33-eb183d9935ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924671966 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.1924671966
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.4269099177
Short name T586
Test name
Test status
Simulation time 44560883 ps
CPU time 0.87 seconds
Started Oct 11 12:52:36 PM PDT 23
Finished Oct 11 12:52:37 PM PDT 23
Peak memory 204600 kb
Host smart-3fb3d12b-b0ce-4e58-835b-cb7e185fe0a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269099177 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.4269099177
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.3106142967
Short name T457
Test name
Test status
Simulation time 22022485 ps
CPU time 0.84 seconds
Started Oct 11 12:52:59 PM PDT 23
Finished Oct 11 12:53:01 PM PDT 23
Peak memory 214384 kb
Host smart-e44be9a5-023a-4eb0-807c-fd336c1dae46
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106142967 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.3106142967
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.1397515772
Short name T251
Test name
Test status
Simulation time 30662556 ps
CPU time 0.97 seconds
Started Oct 11 12:52:49 PM PDT 23
Finished Oct 11 12:52:55 PM PDT 23
Peak memory 214604 kb
Host smart-154cdafa-9358-4d02-a246-b7612db073b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397515772 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.1397515772
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.3275590712
Short name T604
Test name
Test status
Simulation time 62876011 ps
CPU time 0.77 seconds
Started Oct 11 12:52:52 PM PDT 23
Finished Oct 11 12:52:53 PM PDT 23
Peak memory 215432 kb
Host smart-7a26c3e4-1da0-4597-b783-88c1b33930e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275590712 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.3275590712
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.3432128358
Short name T103
Test name
Test status
Simulation time 44444304 ps
CPU time 1.1 seconds
Started Oct 11 12:52:28 PM PDT 23
Finished Oct 11 12:52:29 PM PDT 23
Peak memory 214336 kb
Host smart-d93acab3-8451-436d-8f03-197529f33691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432128358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.3432128358
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.4203140638
Short name T597
Test name
Test status
Simulation time 23754045 ps
CPU time 1 seconds
Started Oct 11 12:52:16 PM PDT 23
Finished Oct 11 12:52:17 PM PDT 23
Peak memory 225680 kb
Host smart-b409c9a9-5377-4973-be21-e38c2624adcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203140638 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.4203140638
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.644770307
Short name T480
Test name
Test status
Simulation time 43662618 ps
CPU time 0.82 seconds
Started Oct 11 12:52:44 PM PDT 23
Finished Oct 11 12:52:45 PM PDT 23
Peak memory 204756 kb
Host smart-57eae1e8-d23e-40d1-9fc9-a577bf22f017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644770307 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.644770307
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.3301076548
Short name T21
Test name
Test status
Simulation time 2252449858 ps
CPU time 3.54 seconds
Started Oct 11 12:52:35 PM PDT 23
Finished Oct 11 12:52:39 PM PDT 23
Peak memory 206080 kb
Host smart-3c714ca2-09f4-4ca2-8495-ed7d8dc2bd21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301076548 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.3301076548
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.559041713
Short name T582
Test name
Test status
Simulation time 49323517667 ps
CPU time 1220.5 seconds
Started Oct 11 12:52:48 PM PDT 23
Finished Oct 11 01:13:09 PM PDT 23
Peak memory 216412 kb
Host smart-89a04fb1-833e-4044-af6f-19d9e8c68921
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559041713 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.559041713
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.3554393186
Short name T258
Test name
Test status
Simulation time 19433325 ps
CPU time 0.99 seconds
Started Oct 11 12:53:45 PM PDT 23
Finished Oct 11 12:53:47 PM PDT 23
Peak memory 205368 kb
Host smart-9ba69ec4-e178-47c8-9784-268108ae9b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554393186 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.3554393186
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.2296655249
Short name T323
Test name
Test status
Simulation time 24941596 ps
CPU time 0.84 seconds
Started Oct 11 12:53:59 PM PDT 23
Finished Oct 11 12:54:00 PM PDT 23
Peak memory 204580 kb
Host smart-fe19d899-4e87-43ad-b2fd-3f5a93f79b41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296655249 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.2296655249
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.3606804486
Short name T28
Test name
Test status
Simulation time 50345405 ps
CPU time 0.94 seconds
Started Oct 11 12:53:01 PM PDT 23
Finished Oct 11 12:53:02 PM PDT 23
Peak memory 214692 kb
Host smart-cbfa3c8c-a332-4d85-98e0-f20c9029a8a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606804486 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.3606804486
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.1582201895
Short name T201
Test name
Test status
Simulation time 19255542 ps
CPU time 1 seconds
Started Oct 11 12:52:52 PM PDT 23
Finished Oct 11 12:52:54 PM PDT 23
Peak memory 215664 kb
Host smart-037fedb3-f6c8-49ec-81f7-c36bbf52fd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582201895 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.1582201895
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_intr.1584594772
Short name T558
Test name
Test status
Simulation time 24088804 ps
CPU time 1.08 seconds
Started Oct 11 12:53:22 PM PDT 23
Finished Oct 11 12:53:23 PM PDT 23
Peak memory 214396 kb
Host smart-6e92035b-6f90-47c9-981a-d83c97d67c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584594772 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.1584594772
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.1712185852
Short name T321
Test name
Test status
Simulation time 12536164 ps
CPU time 0.84 seconds
Started Oct 11 12:52:26 PM PDT 23
Finished Oct 11 12:52:27 PM PDT 23
Peak memory 204880 kb
Host smart-5407ea96-3c17-463e-a09f-e076acb85ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712185852 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.1712185852
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.1648428386
Short name T610
Test name
Test status
Simulation time 44434873 ps
CPU time 0.95 seconds
Started Oct 11 12:52:47 PM PDT 23
Finished Oct 11 12:52:49 PM PDT 23
Peak memory 204252 kb
Host smart-2e7473b5-6c5e-482d-a54b-15db937a10d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648428386 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.1648428386
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.1921862698
Short name T552
Test name
Test status
Simulation time 18595923389 ps
CPU time 409.98 seconds
Started Oct 11 12:52:48 PM PDT 23
Finished Oct 11 12:59:39 PM PDT 23
Peak memory 215132 kb
Host smart-86ddfc43-4770-4ce5-a7aa-983cc86fda73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921862698 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.1921862698
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.1734086578
Short name T632
Test name
Test status
Simulation time 34114566 ps
CPU time 0.98 seconds
Started Oct 11 12:52:58 PM PDT 23
Finished Oct 11 12:52:59 PM PDT 23
Peak memory 206060 kb
Host smart-9c4cf0b5-352f-464a-94e8-4748b2dc1249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734086578 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.1734086578
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.354972915
Short name T576
Test name
Test status
Simulation time 14192718 ps
CPU time 0.84 seconds
Started Oct 11 12:52:44 PM PDT 23
Finished Oct 11 12:52:46 PM PDT 23
Peak memory 204616 kb
Host smart-91d0e5b5-f6b3-479a-9437-1cff3ce58baf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354972915 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.354972915
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.3943058375
Short name T34
Test name
Test status
Simulation time 84333878 ps
CPU time 0.93 seconds
Started Oct 11 12:52:48 PM PDT 23
Finished Oct 11 12:52:49 PM PDT 23
Peak memory 214640 kb
Host smart-7537ac92-979f-43ce-925d-1a1fe01ec71b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943058375 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.3943058375
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.3374138133
Short name T254
Test name
Test status
Simulation time 24125228 ps
CPU time 1.1 seconds
Started Oct 11 12:52:52 PM PDT 23
Finished Oct 11 12:52:53 PM PDT 23
Peak memory 214296 kb
Host smart-88087ace-87eb-4c5d-a32e-908b67b97f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374138133 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.3374138133
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.4277157503
Short name T535
Test name
Test status
Simulation time 28235111 ps
CPU time 0.91 seconds
Started Oct 11 12:52:47 PM PDT 23
Finished Oct 11 12:52:48 PM PDT 23
Peak memory 205088 kb
Host smart-822e2a3a-fc1a-4c53-962d-2df78e74761f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277157503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.4277157503
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.4206171708
Short name T667
Test name
Test status
Simulation time 18606571 ps
CPU time 1.11 seconds
Started Oct 11 12:53:10 PM PDT 23
Finished Oct 11 12:53:12 PM PDT 23
Peak memory 221816 kb
Host smart-10517569-efda-4118-914c-bacf0973279d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206171708 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.4206171708
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.1623215100
Short name T598
Test name
Test status
Simulation time 20408908 ps
CPU time 0.86 seconds
Started Oct 11 12:54:00 PM PDT 23
Finished Oct 11 12:54:01 PM PDT 23
Peak memory 204640 kb
Host smart-6f3d8045-d688-4ace-8a5d-1be0d023816c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623215100 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.1623215100
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.1886436689
Short name T654
Test name
Test status
Simulation time 188040964 ps
CPU time 3.03 seconds
Started Oct 11 12:52:56 PM PDT 23
Finished Oct 11 12:53:00 PM PDT 23
Peak memory 205896 kb
Host smart-ba27a3aa-b411-4922-bf89-756ef20bdf1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886436689 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.1886436689
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.3778788775
Short name T468
Test name
Test status
Simulation time 50328769665 ps
CPU time 1062.91 seconds
Started Oct 11 12:52:39 PM PDT 23
Finished Oct 11 01:10:23 PM PDT 23
Peak memory 214928 kb
Host smart-80a71874-1c34-45ba-a4ef-9041a296c09f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778788775 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.3778788775
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.1620306464
Short name T257
Test name
Test status
Simulation time 29780802 ps
CPU time 0.9 seconds
Started Oct 11 12:52:24 PM PDT 23
Finished Oct 11 12:52:25 PM PDT 23
Peak memory 205260 kb
Host smart-2c2dabd5-a217-4135-9967-db3b8f41346d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620306464 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.1620306464
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.3876823321
Short name T475
Test name
Test status
Simulation time 26320963 ps
CPU time 0.83 seconds
Started Oct 11 12:52:33 PM PDT 23
Finished Oct 11 12:52:40 PM PDT 23
Peak memory 204692 kb
Host smart-c57d9035-6e01-4804-b303-b566044b69b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876823321 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.3876823321
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.3087055760
Short name T89
Test name
Test status
Simulation time 29217463 ps
CPU time 0.83 seconds
Started Oct 11 12:52:49 PM PDT 23
Finished Oct 11 12:52:50 PM PDT 23
Peak memory 214516 kb
Host smart-b5d4bdce-dd09-41a1-a1dc-f61307810ca8
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087055760 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.3087055760
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_err.180295535
Short name T579
Test name
Test status
Simulation time 18581117 ps
CPU time 1.32 seconds
Started Oct 11 12:52:37 PM PDT 23
Finished Oct 11 12:52:39 PM PDT 23
Peak memory 222000 kb
Host smart-90f8afa1-1cd7-41f0-b9d5-1b48c58a1f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180295535 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.180295535
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.1941900213
Short name T268
Test name
Test status
Simulation time 66805358 ps
CPU time 1.26 seconds
Started Oct 11 12:52:50 PM PDT 23
Finished Oct 11 12:52:52 PM PDT 23
Peak memory 205532 kb
Host smart-d29acf6a-99d5-40f2-820b-285f60efefeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941900213 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1941900213
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.2298533506
Short name T496
Test name
Test status
Simulation time 19690763 ps
CPU time 1.12 seconds
Started Oct 11 12:52:54 PM PDT 23
Finished Oct 11 12:52:56 PM PDT 23
Peak memory 221700 kb
Host smart-1d3d7aaa-f02b-4a38-8e4a-3d1e7989cec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298533506 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2298533506
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.1322092411
Short name T646
Test name
Test status
Simulation time 44024025 ps
CPU time 0.79 seconds
Started Oct 11 12:53:10 PM PDT 23
Finished Oct 11 12:53:11 PM PDT 23
Peak memory 204664 kb
Host smart-6335477f-6a57-4c54-8bc2-111327bcacae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322092411 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.1322092411
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.483736325
Short name T608
Test name
Test status
Simulation time 52233119 ps
CPU time 1.65 seconds
Started Oct 11 12:53:00 PM PDT 23
Finished Oct 11 12:53:03 PM PDT 23
Peak memory 205676 kb
Host smart-72af376d-e5e0-4a58-b175-d206d85e6653
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483736325 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.483736325
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.117611514
Short name T483
Test name
Test status
Simulation time 89503191327 ps
CPU time 985.63 seconds
Started Oct 11 12:53:23 PM PDT 23
Finished Oct 11 01:09:50 PM PDT 23
Peak memory 216024 kb
Host smart-3a46fb9e-2c03-4245-9687-ed6345889acf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117611514 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.117611514
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.692815299
Short name T304
Test name
Test status
Simulation time 20547727 ps
CPU time 0.97 seconds
Started Oct 11 12:52:59 PM PDT 23
Finished Oct 11 12:53:10 PM PDT 23
Peak memory 205128 kb
Host smart-ae8081ec-8adb-4b7a-8f91-a5f9e6135dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692815299 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.692815299
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.2319981123
Short name T503
Test name
Test status
Simulation time 21999173 ps
CPU time 0.81 seconds
Started Oct 11 12:52:49 PM PDT 23
Finished Oct 11 12:52:50 PM PDT 23
Peak memory 204324 kb
Host smart-56443959-e5cd-432e-9896-87fa61acf46e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319981123 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.2319981123
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.3848465780
Short name T32
Test name
Test status
Simulation time 37182291 ps
CPU time 0.96 seconds
Started Oct 11 12:53:11 PM PDT 23
Finished Oct 11 12:53:12 PM PDT 23
Peak memory 214636 kb
Host smart-bf96d3f6-a27d-4253-8628-2b4f3b127eca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848465780 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.3848465780
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.951495839
Short name T192
Test name
Test status
Simulation time 110730672 ps
CPU time 0.83 seconds
Started Oct 11 12:52:41 PM PDT 23
Finished Oct 11 12:52:43 PM PDT 23
Peak memory 215520 kb
Host smart-673a9488-4ccd-4e9c-ada0-d68505d4bdc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951495839 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.951495839
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.2221822368
Short name T39
Test name
Test status
Simulation time 48211628 ps
CPU time 1.03 seconds
Started Oct 11 12:52:38 PM PDT 23
Finished Oct 11 12:52:40 PM PDT 23
Peak memory 205624 kb
Host smart-e83fee04-97db-42c6-a87e-307ccac51eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221822368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.2221822368
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.3709991364
Short name T683
Test name
Test status
Simulation time 23228595 ps
CPU time 0.92 seconds
Started Oct 11 12:52:59 PM PDT 23
Finished Oct 11 12:53:00 PM PDT 23
Peak memory 214712 kb
Host smart-60df5b83-2611-44d9-a4d4-dbd4381d3c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709991364 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.3709991364
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.1239367329
Short name T527
Test name
Test status
Simulation time 42958706 ps
CPU time 0.91 seconds
Started Oct 11 12:53:12 PM PDT 23
Finished Oct 11 12:53:13 PM PDT 23
Peak memory 205016 kb
Host smart-a51463b7-61a9-43ec-b153-e5964e27b561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239367329 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.1239367329
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.3638375210
Short name T563
Test name
Test status
Simulation time 155454958 ps
CPU time 3.16 seconds
Started Oct 11 12:52:47 PM PDT 23
Finished Oct 11 12:52:51 PM PDT 23
Peak memory 205992 kb
Host smart-af123e83-c86a-468e-9b55-cc2f9558280d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638375210 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.3638375210
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.2749648870
Short name T53
Test name
Test status
Simulation time 34162934185 ps
CPU time 732.17 seconds
Started Oct 11 12:53:51 PM PDT 23
Finished Oct 11 01:06:04 PM PDT 23
Peak memory 214596 kb
Host smart-2a753ecc-db79-400a-959e-1bd57e821272
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749648870 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.2749648870
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.1464724824
Short name T675
Test name
Test status
Simulation time 20501938 ps
CPU time 0.96 seconds
Started Oct 11 12:52:38 PM PDT 23
Finished Oct 11 12:52:40 PM PDT 23
Peak memory 206060 kb
Host smart-e9f2aa58-507c-4643-a8db-8e2e4c112c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464724824 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.1464724824
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.2386173983
Short name T83
Test name
Test status
Simulation time 225372997 ps
CPU time 1.03 seconds
Started Oct 11 12:52:49 PM PDT 23
Finished Oct 11 12:52:51 PM PDT 23
Peak memory 205484 kb
Host smart-2090032e-066b-41c3-a297-be473af229ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386173983 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.2386173983
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.1837869685
Short name T128
Test name
Test status
Simulation time 39883885 ps
CPU time 0.82 seconds
Started Oct 11 12:52:35 PM PDT 23
Finished Oct 11 12:52:37 PM PDT 23
Peak memory 214476 kb
Host smart-a93852cb-d986-4e13-aecd-9335639664c5
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837869685 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.1837869685
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.3939030357
Short name T75
Test name
Test status
Simulation time 20907448 ps
CPU time 0.9 seconds
Started Oct 11 12:52:56 PM PDT 23
Finished Oct 11 12:52:58 PM PDT 23
Peak memory 214676 kb
Host smart-96f6b195-bb2a-466a-9372-5f7d080aa037
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939030357 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.3939030357
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.3429799769
Short name T693
Test name
Test status
Simulation time 22492740 ps
CPU time 0.98 seconds
Started Oct 11 12:52:37 PM PDT 23
Finished Oct 11 12:52:38 PM PDT 23
Peak memory 222084 kb
Host smart-7e7f32de-e151-4aa5-bffb-dcb631517f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429799769 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.3429799769
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.1016615450
Short name T281
Test name
Test status
Simulation time 81181829 ps
CPU time 0.95 seconds
Started Oct 11 12:52:49 PM PDT 23
Finished Oct 11 12:52:51 PM PDT 23
Peak memory 205292 kb
Host smart-268874dd-8ba0-4659-b5a7-9cc0a3b5765f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016615450 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.1016615450
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.4066256215
Short name T112
Test name
Test status
Simulation time 17887503 ps
CPU time 1.08 seconds
Started Oct 11 12:52:49 PM PDT 23
Finished Oct 11 12:52:51 PM PDT 23
Peak memory 225520 kb
Host smart-3e49207b-742b-4733-abe1-f717711bd73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066256215 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.4066256215
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.4060992720
Short name T595
Test name
Test status
Simulation time 33777817 ps
CPU time 0.81 seconds
Started Oct 11 12:54:02 PM PDT 23
Finished Oct 11 12:54:03 PM PDT 23
Peak memory 204664 kb
Host smart-fd50a26a-c550-4533-9036-bf703ae594c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060992720 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.4060992720
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.66512823
Short name T686
Test name
Test status
Simulation time 472832709 ps
CPU time 2.52 seconds
Started Oct 11 12:52:43 PM PDT 23
Finished Oct 11 12:52:46 PM PDT 23
Peak memory 205820 kb
Host smart-7ec75b15-0651-414a-8235-111caf812157
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66512823 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.66512823
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_alert.4274772530
Short name T255
Test name
Test status
Simulation time 22147215 ps
CPU time 0.92 seconds
Started Oct 11 12:51:58 PM PDT 23
Finished Oct 11 12:52:00 PM PDT 23
Peak memory 206068 kb
Host smart-bbf1517e-962c-40cd-b7ce-3ba50402efa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274772530 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.4274772530
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.532342218
Short name T91
Test name
Test status
Simulation time 14787337 ps
CPU time 0.85 seconds
Started Oct 11 12:52:18 PM PDT 23
Finished Oct 11 12:52:20 PM PDT 23
Peak memory 205268 kb
Host smart-83ff1bc1-7d1f-40a9-9ec1-a075ee8e3bb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532342218 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.532342218
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.842290697
Short name T537
Test name
Test status
Simulation time 89091341 ps
CPU time 0.84 seconds
Started Oct 11 12:52:16 PM PDT 23
Finished Oct 11 12:52:17 PM PDT 23
Peak memory 214568 kb
Host smart-2a6d2c6b-a132-4166-9ac1-3dddc880bbf3
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842290697 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.842290697
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.2893465774
Short name T186
Test name
Test status
Simulation time 27848510 ps
CPU time 0.97 seconds
Started Oct 11 12:52:22 PM PDT 23
Finished Oct 11 12:52:23 PM PDT 23
Peak memory 214664 kb
Host smart-d4193833-5715-4f8e-a870-8710d4f7e542
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893465774 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.2893465774
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.1217943473
Short name T205
Test name
Test status
Simulation time 89915009 ps
CPU time 0.78 seconds
Started Oct 11 12:51:51 PM PDT 23
Finished Oct 11 12:51:52 PM PDT 23
Peak memory 214216 kb
Host smart-e1d216de-aa27-4509-b580-df7346af11ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217943473 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.1217943473
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.176882678
Short name T549
Test name
Test status
Simulation time 31477770 ps
CPU time 1.08 seconds
Started Oct 11 12:52:29 PM PDT 23
Finished Oct 11 12:52:31 PM PDT 23
Peak memory 205528 kb
Host smart-046f17e3-258a-4fd0-81d2-ec4ea1eaf347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176882678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.176882678
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.1482911609
Short name T708
Test name
Test status
Simulation time 26231569 ps
CPU time 0.9 seconds
Started Oct 11 12:51:40 PM PDT 23
Finished Oct 11 12:51:42 PM PDT 23
Peak memory 214624 kb
Host smart-7a36a625-29c5-4fd9-85dc-d47dbfaeca3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482911609 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.1482911609
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.1862197607
Short name T289
Test name
Test status
Simulation time 15624025 ps
CPU time 0.82 seconds
Started Oct 11 12:52:23 PM PDT 23
Finished Oct 11 12:52:24 PM PDT 23
Peak memory 204852 kb
Host smart-79931e82-814d-47e4-bb28-12b215417ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862197607 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.1862197607
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.2336409314
Short name T54
Test name
Test status
Simulation time 644461303 ps
CPU time 5.35 seconds
Started Oct 11 12:52:35 PM PDT 23
Finished Oct 11 12:52:41 PM PDT 23
Peak memory 235320 kb
Host smart-ccc6a033-b08c-431a-bb4e-afa55f1f195e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336409314 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.2336409314
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.3941034862
Short name T314
Test name
Test status
Simulation time 172821836 ps
CPU time 0.83 seconds
Started Oct 11 12:51:29 PM PDT 23
Finished Oct 11 12:51:30 PM PDT 23
Peak memory 204764 kb
Host smart-aeaafec5-cfd5-4c52-8b8e-7af6a3e60b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941034862 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3941034862
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.444754205
Short name T471
Test name
Test status
Simulation time 309162773 ps
CPU time 1.26 seconds
Started Oct 11 12:51:52 PM PDT 23
Finished Oct 11 12:51:53 PM PDT 23
Peak memory 205076 kb
Host smart-8a8c16d4-6e59-40b4-b166-330006b4c665
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444754205 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.444754205
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.1984961334
Short name T713
Test name
Test status
Simulation time 27832455596 ps
CPU time 587.29 seconds
Started Oct 11 12:51:47 PM PDT 23
Finished Oct 11 01:01:35 PM PDT 23
Peak memory 214584 kb
Host smart-3e59e281-344e-4785-942e-a7bb2153fc24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984961334 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.1984961334
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.356137178
Short name T637
Test name
Test status
Simulation time 17954923 ps
CPU time 0.96 seconds
Started Oct 11 12:52:15 PM PDT 23
Finished Oct 11 12:52:16 PM PDT 23
Peak memory 205024 kb
Host smart-818c89c0-3a09-4855-9da3-7d05b8725038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356137178 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.356137178
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.3341883884
Short name T482
Test name
Test status
Simulation time 19119617 ps
CPU time 0.94 seconds
Started Oct 11 12:52:25 PM PDT 23
Finished Oct 11 12:52:26 PM PDT 23
Peak memory 205568 kb
Host smart-dc0d5630-506b-46d8-bd02-a99ea0ad90be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341883884 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3341883884
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.1654292495
Short name T108
Test name
Test status
Simulation time 12211178 ps
CPU time 0.85 seconds
Started Oct 11 12:52:54 PM PDT 23
Finished Oct 11 12:52:55 PM PDT 23
Peak memory 214416 kb
Host smart-ad262edf-c78a-43bd-8bdc-72db523bc8af
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654292495 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.1654292495
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.411809977
Short name T652
Test name
Test status
Simulation time 18357693 ps
CPU time 0.98 seconds
Started Oct 11 12:52:32 PM PDT 23
Finished Oct 11 12:52:34 PM PDT 23
Peak memory 214648 kb
Host smart-a068196f-8231-4c62-8202-905558c64c9a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411809977 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_di
sable_auto_req_mode.411809977
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.904713799
Short name T674
Test name
Test status
Simulation time 32620132 ps
CPU time 0.82 seconds
Started Oct 11 12:53:10 PM PDT 23
Finished Oct 11 12:53:12 PM PDT 23
Peak memory 215548 kb
Host smart-9be5c1fb-27b4-4239-b905-695e7c92f56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904713799 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.904713799
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.2243857891
Short name T38
Test name
Test status
Simulation time 39777799 ps
CPU time 1.39 seconds
Started Oct 11 12:52:46 PM PDT 23
Finished Oct 11 12:52:48 PM PDT 23
Peak memory 214436 kb
Host smart-ac11e969-c86e-470d-96a7-fae3129457b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243857891 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.2243857891
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.1548720690
Short name T42
Test name
Test status
Simulation time 23391246 ps
CPU time 1.01 seconds
Started Oct 11 12:52:40 PM PDT 23
Finished Oct 11 12:52:42 PM PDT 23
Peak memory 225680 kb
Host smart-babdd1dc-43a0-4376-bdda-ee8bb6db5942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548720690 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.1548720690
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.2461029145
Short name T451
Test name
Test status
Simulation time 14239546 ps
CPU time 0.85 seconds
Started Oct 11 12:52:40 PM PDT 23
Finished Oct 11 12:52:41 PM PDT 23
Peak memory 204820 kb
Host smart-0e3455f3-65ca-4727-85fc-4c212e9efc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461029145 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.2461029145
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.1906863559
Short name T531
Test name
Test status
Simulation time 40476243 ps
CPU time 1.33 seconds
Started Oct 11 12:52:59 PM PDT 23
Finished Oct 11 12:53:01 PM PDT 23
Peak memory 205112 kb
Host smart-415c0386-f317-4607-a973-a1781466fb5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906863559 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.1906863559
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.1124408734
Short name T77
Test name
Test status
Simulation time 77300816244 ps
CPU time 978.7 seconds
Started Oct 11 12:53:02 PM PDT 23
Finished Oct 11 01:09:22 PM PDT 23
Peak memory 217240 kb
Host smart-baa0e034-5911-41c5-a8ab-2e65e48d5007
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124408734 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.1124408734
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.4116451598
Short name T14
Test name
Test status
Simulation time 292643018 ps
CPU time 0.97 seconds
Started Oct 11 12:52:19 PM PDT 23
Finished Oct 11 12:52:20 PM PDT 23
Peak memory 206268 kb
Host smart-7e96f428-38c7-4005-ad4f-77acccebf770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116451598 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.4116451598
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.1837399320
Short name T309
Test name
Test status
Simulation time 33230485 ps
CPU time 0.93 seconds
Started Oct 11 12:53:00 PM PDT 23
Finished Oct 11 12:53:02 PM PDT 23
Peak memory 204576 kb
Host smart-d01b7aea-afb3-4aa1-beab-35a4bb0cb13d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837399320 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.1837399320
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.472362093
Short name T617
Test name
Test status
Simulation time 13906232 ps
CPU time 0.87 seconds
Started Oct 11 12:52:28 PM PDT 23
Finished Oct 11 12:52:30 PM PDT 23
Peak memory 214556 kb
Host smart-9b2f3159-c559-454e-841b-44947f426cbe
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472362093 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.472362093
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_err.2244971669
Short name T180
Test name
Test status
Simulation time 159350118 ps
CPU time 1.04 seconds
Started Oct 11 12:52:51 PM PDT 23
Finished Oct 11 12:52:53 PM PDT 23
Peak memory 228868 kb
Host smart-1d8a71d7-952a-4322-8fd1-52451ab13981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244971669 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2244971669
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.1717084108
Short name T725
Test name
Test status
Simulation time 19026451 ps
CPU time 0.96 seconds
Started Oct 11 12:52:42 PM PDT 23
Finished Oct 11 12:52:44 PM PDT 23
Peak memory 205472 kb
Host smart-248f6c9e-2591-4d7f-864e-0f4cd34fa82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717084108 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.1717084108
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.444673704
Short name T120
Test name
Test status
Simulation time 33457354 ps
CPU time 0.86 seconds
Started Oct 11 12:53:21 PM PDT 23
Finished Oct 11 12:53:22 PM PDT 23
Peak memory 214628 kb
Host smart-ed8cdc90-2d0e-4d97-a0db-582ac47dbadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444673704 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.444673704
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.1022648144
Short name T154
Test name
Test status
Simulation time 45801995 ps
CPU time 0.86 seconds
Started Oct 11 12:52:27 PM PDT 23
Finished Oct 11 12:52:28 PM PDT 23
Peak memory 204672 kb
Host smart-678299b0-da81-4054-a69a-79318c0c1ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022648144 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.1022648144
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.3902552852
Short name T551
Test name
Test status
Simulation time 68750241 ps
CPU time 1.84 seconds
Started Oct 11 12:52:37 PM PDT 23
Finished Oct 11 12:52:39 PM PDT 23
Peak memory 205748 kb
Host smart-311bbfb1-b0d7-4b90-bfe6-11762e1609c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902552852 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.3902552852
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.3127310522
Short name T141
Test name
Test status
Simulation time 504522138587 ps
CPU time 1575.31 seconds
Started Oct 11 12:52:45 PM PDT 23
Finished Oct 11 01:19:01 PM PDT 23
Peak memory 218296 kb
Host smart-11748b56-ad9e-4635-80b4-4e1e54cf8fb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127310522 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.3127310522
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.134688948
Short name T600
Test name
Test status
Simulation time 26345591 ps
CPU time 0.9 seconds
Started Oct 11 12:52:42 PM PDT 23
Finished Oct 11 12:52:43 PM PDT 23
Peak memory 205156 kb
Host smart-f5abdcb5-cfc4-48f9-849c-0d2f793b2d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134688948 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.134688948
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.4260420389
Short name T313
Test name
Test status
Simulation time 49368949 ps
CPU time 0.91 seconds
Started Oct 11 12:52:58 PM PDT 23
Finished Oct 11 12:52:59 PM PDT 23
Peak memory 204612 kb
Host smart-5d0a3811-bccc-4cd5-956a-51951e422314
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260420389 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.4260420389
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.1165380963
Short name T553
Test name
Test status
Simulation time 62813376 ps
CPU time 0.93 seconds
Started Oct 11 12:52:40 PM PDT 23
Finished Oct 11 12:52:41 PM PDT 23
Peak memory 214724 kb
Host smart-330a2ba8-c21e-4a28-bf71-b5a39b6bd009
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165380963 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.1165380963
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.612743019
Short name T253
Test name
Test status
Simulation time 18740097 ps
CPU time 1.36 seconds
Started Oct 11 12:52:35 PM PDT 23
Finished Oct 11 12:52:37 PM PDT 23
Peak memory 222060 kb
Host smart-e8669c28-3eb6-4e11-842a-892f8e7ad073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612743019 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.612743019
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.1861477141
Short name T282
Test name
Test status
Simulation time 29419542 ps
CPU time 0.97 seconds
Started Oct 11 12:52:17 PM PDT 23
Finished Oct 11 12:52:18 PM PDT 23
Peak memory 205140 kb
Host smart-aefc6238-ed0a-4097-99f6-0dd17c54c3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861477141 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.1861477141
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.50336425
Short name T320
Test name
Test status
Simulation time 21336687 ps
CPU time 0.99 seconds
Started Oct 11 12:52:51 PM PDT 23
Finished Oct 11 12:52:53 PM PDT 23
Peak memory 214400 kb
Host smart-e5e8b597-589c-496b-a8d9-7924ccfc5e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50336425 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.50336425
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.3882445123
Short name T515
Test name
Test status
Simulation time 30072516 ps
CPU time 0.85 seconds
Started Oct 11 12:52:57 PM PDT 23
Finished Oct 11 12:52:58 PM PDT 23
Peak memory 204600 kb
Host smart-eb9440b3-92b4-4151-b8d2-c4cfafdff154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882445123 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.3882445123
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.456099085
Short name T264
Test name
Test status
Simulation time 120957092 ps
CPU time 1.74 seconds
Started Oct 11 12:53:08 PM PDT 23
Finished Oct 11 12:53:10 PM PDT 23
Peak memory 206052 kb
Host smart-69d38641-e8f0-4914-a489-b8dc3e824634
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456099085 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.456099085
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.4190828257
Short name T20
Test name
Test status
Simulation time 444657547540 ps
CPU time 2940.5 seconds
Started Oct 11 12:52:46 PM PDT 23
Finished Oct 11 01:41:47 PM PDT 23
Peak memory 227724 kb
Host smart-c749b8c5-c861-45d8-93e6-7b0adb963b87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190828257 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.4190828257
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.3861571777
Short name T718
Test name
Test status
Simulation time 18839386 ps
CPU time 0.93 seconds
Started Oct 11 12:52:27 PM PDT 23
Finished Oct 11 12:52:28 PM PDT 23
Peak memory 205124 kb
Host smart-11e532ad-fec1-4e8d-a2f9-b1a0a9cffe07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861571777 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.3861571777
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.2641196371
Short name T626
Test name
Test status
Simulation time 48913092 ps
CPU time 0.81 seconds
Started Oct 11 12:52:44 PM PDT 23
Finished Oct 11 12:52:45 PM PDT 23
Peak memory 204652 kb
Host smart-bbd5a397-2aa3-43fb-a5b4-0c33326c0d60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641196371 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.2641196371
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.3255275352
Short name T197
Test name
Test status
Simulation time 11113362 ps
CPU time 0.81 seconds
Started Oct 11 12:52:58 PM PDT 23
Finished Oct 11 12:52:59 PM PDT 23
Peak memory 214484 kb
Host smart-615ce47f-1fef-4114-8be6-3704af06b5fc
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255275352 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.3255275352
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.119006154
Short name T29
Test name
Test status
Simulation time 39400747 ps
CPU time 0.95 seconds
Started Oct 11 12:52:39 PM PDT 23
Finished Oct 11 12:52:40 PM PDT 23
Peak memory 214724 kb
Host smart-72e05135-71c3-44bd-a2f5-531a4a744d88
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119006154 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_di
sable_auto_req_mode.119006154
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.3859810669
Short name T238
Test name
Test status
Simulation time 29312768 ps
CPU time 1 seconds
Started Oct 11 12:53:05 PM PDT 23
Finished Oct 11 12:53:06 PM PDT 23
Peak memory 214556 kb
Host smart-c4c1caf6-1a34-4063-a4fe-57a06d5873c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859810669 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.3859810669
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.61197888
Short name T8
Test name
Test status
Simulation time 144637109 ps
CPU time 1.12 seconds
Started Oct 11 12:52:57 PM PDT 23
Finished Oct 11 12:52:59 PM PDT 23
Peak memory 214368 kb
Host smart-93730071-3dd2-4d36-a81d-4d03f4005efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61197888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.61197888
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.4068447410
Short name T633
Test name
Test status
Simulation time 20834835 ps
CPU time 1.02 seconds
Started Oct 11 12:52:49 PM PDT 23
Finished Oct 11 12:52:51 PM PDT 23
Peak memory 225700 kb
Host smart-3ea1dae1-3b5c-4d19-a781-048de2527ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068447410 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.4068447410
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.3966227502
Short name T645
Test name
Test status
Simulation time 24750162 ps
CPU time 0.82 seconds
Started Oct 11 12:52:48 PM PDT 23
Finished Oct 11 12:52:49 PM PDT 23
Peak memory 205076 kb
Host smart-78fd1bc9-6e64-4eee-891b-800df8db74f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966227502 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.3966227502
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.1337404438
Short name T265
Test name
Test status
Simulation time 30719612 ps
CPU time 0.99 seconds
Started Oct 11 12:53:07 PM PDT 23
Finished Oct 11 12:53:08 PM PDT 23
Peak memory 204776 kb
Host smart-4a5d6ebb-1b8f-4b80-ab18-590aa746841d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337404438 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1337404438
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.3372338312
Short name T534
Test name
Test status
Simulation time 50409278107 ps
CPU time 636.76 seconds
Started Oct 11 12:52:45 PM PDT 23
Finished Oct 11 01:03:22 PM PDT 23
Peak memory 214760 kb
Host smart-ba6ceae5-dd84-4bac-9b69-ed6011a4ddf4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372338312 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.3372338312
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.581906588
Short name T292
Test name
Test status
Simulation time 18399336 ps
CPU time 0.94 seconds
Started Oct 11 12:52:46 PM PDT 23
Finished Oct 11 12:52:47 PM PDT 23
Peak memory 205048 kb
Host smart-30b00b74-8667-441c-8f94-823ad67c62ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581906588 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.581906588
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.3550470346
Short name T690
Test name
Test status
Simulation time 32300209 ps
CPU time 0.8 seconds
Started Oct 11 12:53:17 PM PDT 23
Finished Oct 11 12:53:18 PM PDT 23
Peak memory 204004 kb
Host smart-877abbe3-adf4-415a-b806-2567efda6898
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550470346 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.3550470346
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.3094505182
Short name T121
Test name
Test status
Simulation time 34778992 ps
CPU time 0.78 seconds
Started Oct 11 12:52:31 PM PDT 23
Finished Oct 11 12:52:32 PM PDT 23
Peak memory 214460 kb
Host smart-1bafd873-2085-412b-bfbc-7bd2a500d2d9
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094505182 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.3094505182
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.2362425920
Short name T635
Test name
Test status
Simulation time 303424462 ps
CPU time 1.07 seconds
Started Oct 11 12:52:47 PM PDT 23
Finished Oct 11 12:52:49 PM PDT 23
Peak memory 214708 kb
Host smart-617cea81-1caf-4535-840b-02a6f4fa3cd5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362425920 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.2362425920
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.1871242635
Short name T166
Test name
Test status
Simulation time 25408313 ps
CPU time 1.13 seconds
Started Oct 11 12:53:08 PM PDT 23
Finished Oct 11 12:53:09 PM PDT 23
Peak memory 215592 kb
Host smart-511a1197-9b19-4f77-b421-e26a9122b776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871242635 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.1871242635
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.3716833537
Short name T591
Test name
Test status
Simulation time 107998001 ps
CPU time 1.54 seconds
Started Oct 11 12:52:50 PM PDT 23
Finished Oct 11 12:52:52 PM PDT 23
Peak memory 205544 kb
Host smart-cf9d6ad8-e304-4bdf-8901-acf9131105d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716833537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.3716833537
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.1852443936
Short name T564
Test name
Test status
Simulation time 24340243 ps
CPU time 0.91 seconds
Started Oct 11 12:53:07 PM PDT 23
Finished Oct 11 12:53:09 PM PDT 23
Peak memory 214612 kb
Host smart-b6e3b1e1-a8ab-4be8-9a78-e7ba4ff95bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852443936 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.1852443936
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.2782664950
Short name T528
Test name
Test status
Simulation time 42915740 ps
CPU time 0.82 seconds
Started Oct 11 12:52:55 PM PDT 23
Finished Oct 11 12:52:56 PM PDT 23
Peak memory 204848 kb
Host smart-0b58b5e9-089a-40f4-a7f0-0ab644b2bf81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782664950 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.2782664950
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.3127595452
Short name T153
Test name
Test status
Simulation time 404501571 ps
CPU time 4 seconds
Started Oct 11 12:52:27 PM PDT 23
Finished Oct 11 12:52:32 PM PDT 23
Peak memory 206140 kb
Host smart-af7345c9-8b5f-4029-b839-3f2ce87bb839
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127595452 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.3127595452
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_alert_test.1659526801
Short name T467
Test name
Test status
Simulation time 51093698 ps
CPU time 0.87 seconds
Started Oct 11 12:52:30 PM PDT 23
Finished Oct 11 12:52:31 PM PDT 23
Peak memory 205168 kb
Host smart-8d377511-08a9-43b1-a851-b04e9f019231
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659526801 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.1659526801
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.3495992888
Short name T662
Test name
Test status
Simulation time 28043538 ps
CPU time 0.78 seconds
Started Oct 11 12:52:52 PM PDT 23
Finished Oct 11 12:52:54 PM PDT 23
Peak memory 214520 kb
Host smart-4624443a-3aac-445f-be9c-cb77167cc34b
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495992888 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3495992888
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.926813781
Short name T31
Test name
Test status
Simulation time 43753960 ps
CPU time 0.94 seconds
Started Oct 11 12:53:03 PM PDT 23
Finished Oct 11 12:53:05 PM PDT 23
Peak memory 206392 kb
Host smart-72343ce4-2bc9-4da5-860f-d50670b9457c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926813781 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_di
sable_auto_req_mode.926813781
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.1402385954
Short name T638
Test name
Test status
Simulation time 45843323 ps
CPU time 1.11 seconds
Started Oct 11 12:52:57 PM PDT 23
Finished Oct 11 12:52:58 PM PDT 23
Peak memory 222068 kb
Host smart-45180fe7-479e-4ff2-9982-3d01a78208d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402385954 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.1402385954
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.3785780137
Short name T649
Test name
Test status
Simulation time 16141850 ps
CPU time 0.9 seconds
Started Oct 11 12:52:55 PM PDT 23
Finished Oct 11 12:52:56 PM PDT 23
Peak memory 205188 kb
Host smart-938a8178-80ec-471b-a6e5-dda7a7d159c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785780137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.3785780137
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_smoke.4038122313
Short name T521
Test name
Test status
Simulation time 14376977 ps
CPU time 0.91 seconds
Started Oct 11 12:53:21 PM PDT 23
Finished Oct 11 12:53:23 PM PDT 23
Peak memory 204880 kb
Host smart-d8da11c6-eb28-43dc-9dee-22812e425cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038122313 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.4038122313
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.3203993948
Short name T312
Test name
Test status
Simulation time 596519060 ps
CPU time 3.56 seconds
Started Oct 11 12:53:03 PM PDT 23
Finished Oct 11 12:53:07 PM PDT 23
Peak memory 206200 kb
Host smart-4af99477-2429-42b6-b3d3-d56e843fefae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203993948 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.3203993948
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.359661288
Short name T541
Test name
Test status
Simulation time 137857318621 ps
CPU time 745.48 seconds
Started Oct 11 12:52:57 PM PDT 23
Finished Oct 11 01:05:23 PM PDT 23
Peak memory 214620 kb
Host smart-d29bbae2-b83e-4998-ae8e-4768c427bae6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359661288 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.359661288
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.2492158478
Short name T57
Test name
Test status
Simulation time 23006660 ps
CPU time 0.93 seconds
Started Oct 11 12:52:48 PM PDT 23
Finished Oct 11 12:52:50 PM PDT 23
Peak memory 205252 kb
Host smart-96a05342-38ea-4b6c-a9d0-49e5f2e768ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492158478 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.2492158478
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.620697103
Short name T86
Test name
Test status
Simulation time 14193579 ps
CPU time 0.9 seconds
Started Oct 11 12:52:54 PM PDT 23
Finished Oct 11 12:52:56 PM PDT 23
Peak memory 204536 kb
Host smart-b4e3d23c-ec3e-433b-b4ef-7bab25c388c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620697103 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.620697103
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.3192566575
Short name T328
Test name
Test status
Simulation time 27801322 ps
CPU time 0.8 seconds
Started Oct 11 12:52:40 PM PDT 23
Finished Oct 11 12:52:42 PM PDT 23
Peak memory 214388 kb
Host smart-a9b8ab04-8faa-467b-a3d9-2c9364cd04fd
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192566575 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.3192566575
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.68003311
Short name T536
Test name
Test status
Simulation time 56977174 ps
CPU time 1.14 seconds
Started Oct 11 12:53:24 PM PDT 23
Finished Oct 11 12:53:25 PM PDT 23
Peak memory 214772 kb
Host smart-c037e587-95b2-4490-9921-46eff9be740c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68003311 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_dis
able_auto_req_mode.68003311
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.4173337805
Short name T191
Test name
Test status
Simulation time 28452203 ps
CPU time 1.24 seconds
Started Oct 11 12:53:01 PM PDT 23
Finished Oct 11 12:53:03 PM PDT 23
Peak memory 222156 kb
Host smart-2eca99f1-0727-4bc5-af96-d306d0e0646f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173337805 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.4173337805
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.1328652719
Short name T481
Test name
Test status
Simulation time 34975791 ps
CPU time 0.99 seconds
Started Oct 11 12:52:54 PM PDT 23
Finished Oct 11 12:52:55 PM PDT 23
Peak memory 205108 kb
Host smart-77d31243-c85e-4a74-9496-8b07f1cac82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328652719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1328652719
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.3114912421
Short name T615
Test name
Test status
Simulation time 28460235 ps
CPU time 0.88 seconds
Started Oct 11 12:53:12 PM PDT 23
Finished Oct 11 12:53:15 PM PDT 23
Peak memory 214576 kb
Host smart-b6bc578c-c375-484a-8b4a-68e59623e92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114912421 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.3114912421
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.3103553041
Short name T557
Test name
Test status
Simulation time 38065681 ps
CPU time 0.81 seconds
Started Oct 11 12:53:00 PM PDT 23
Finished Oct 11 12:53:02 PM PDT 23
Peak memory 204796 kb
Host smart-221abd6f-af29-4868-9f90-4650947696ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103553041 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.3103553041
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.2084320587
Short name T84
Test name
Test status
Simulation time 53345382 ps
CPU time 1.1 seconds
Started Oct 11 12:52:55 PM PDT 23
Finished Oct 11 12:52:56 PM PDT 23
Peak memory 205132 kb
Host smart-e42f9730-954f-44d9-aae4-725b75607fe7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084320587 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.2084320587
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.713843098
Short name T59
Test name
Test status
Simulation time 148896201764 ps
CPU time 966.55 seconds
Started Oct 11 12:52:57 PM PDT 23
Finished Oct 11 01:09:04 PM PDT 23
Peak memory 216400 kb
Host smart-563bc9e2-ab2c-478a-8bf7-812c04bc607b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713843098 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.713843098
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.2894230029
Short name T644
Test name
Test status
Simulation time 57152573 ps
CPU time 0.92 seconds
Started Oct 11 12:52:47 PM PDT 23
Finished Oct 11 12:52:48 PM PDT 23
Peak memory 205248 kb
Host smart-4625c31c-cb4a-48f8-8364-93c8cc5d511c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894230029 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2894230029
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.3679829156
Short name T512
Test name
Test status
Simulation time 38240231 ps
CPU time 0.89 seconds
Started Oct 11 12:52:56 PM PDT 23
Finished Oct 11 12:52:58 PM PDT 23
Peak memory 205284 kb
Host smart-1abfbc69-6b11-4807-8ee0-e0e33e08ebae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679829156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.3679829156
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.697286666
Short name T127
Test name
Test status
Simulation time 12935019 ps
CPU time 0.84 seconds
Started Oct 11 12:52:47 PM PDT 23
Finished Oct 11 12:52:48 PM PDT 23
Peak memory 214636 kb
Host smart-1864608a-d05f-48dc-9f08-a99c6954b1cb
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697286666 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.697286666
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.1122840754
Short name T239
Test name
Test status
Simulation time 101217947 ps
CPU time 1.09 seconds
Started Oct 11 12:52:56 PM PDT 23
Finished Oct 11 12:52:57 PM PDT 23
Peak memory 214636 kb
Host smart-502ffa06-94f3-4a62-aea5-576bc1f326bb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122840754 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.1122840754
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_intr.192065375
Short name T119
Test name
Test status
Simulation time 18480471 ps
CPU time 0.97 seconds
Started Oct 11 12:52:52 PM PDT 23
Finished Oct 11 12:52:54 PM PDT 23
Peak memory 214736 kb
Host smart-34450f4b-b792-42d2-ad3d-bccee904fd0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192065375 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.192065375
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.3600260250
Short name T634
Test name
Test status
Simulation time 12166165 ps
CPU time 0.81 seconds
Started Oct 11 12:52:59 PM PDT 23
Finished Oct 11 12:53:00 PM PDT 23
Peak memory 204632 kb
Host smart-a19db4dc-0a23-4d85-95db-a01cf3bb2df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600260250 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.3600260250
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.2659959976
Short name T156
Test name
Test status
Simulation time 258102693 ps
CPU time 2.8 seconds
Started Oct 11 12:52:53 PM PDT 23
Finished Oct 11 12:52:57 PM PDT 23
Peak memory 206008 kb
Host smart-90cbff96-4ec8-465a-9544-19392c8c0463
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659959976 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.2659959976
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.272444417
Short name T486
Test name
Test status
Simulation time 563216163046 ps
CPU time 2747.25 seconds
Started Oct 11 12:53:01 PM PDT 23
Finished Oct 11 01:38:49 PM PDT 23
Peak memory 227020 kb
Host smart-8373f0a1-e57b-422e-ad4a-b97193738fc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272444417 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.272444417
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.2300111133
Short name T307
Test name
Test status
Simulation time 27438604 ps
CPU time 0.98 seconds
Started Oct 11 12:52:49 PM PDT 23
Finished Oct 11 12:52:50 PM PDT 23
Peak memory 205176 kb
Host smart-622ab7ee-d262-4c5e-b1b7-50c3bb42963d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300111133 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.2300111133
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.1056194173
Short name T16
Test name
Test status
Simulation time 27878288 ps
CPU time 0.86 seconds
Started Oct 11 12:52:57 PM PDT 23
Finished Oct 11 12:52:59 PM PDT 23
Peak memory 205452 kb
Host smart-e4ea9153-8e5e-4403-a1b2-dce84402e983
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056194173 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.1056194173
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.1884869534
Short name T550
Test name
Test status
Simulation time 35801982 ps
CPU time 0.77 seconds
Started Oct 11 12:52:56 PM PDT 23
Finished Oct 11 12:52:58 PM PDT 23
Peak memory 214432 kb
Host smart-100e576f-8ed8-44de-b55a-fbf66fe24fcf
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884869534 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.1884869534
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.929588307
Short name T556
Test name
Test status
Simulation time 35986295 ps
CPU time 0.95 seconds
Started Oct 11 12:52:34 PM PDT 23
Finished Oct 11 12:52:35 PM PDT 23
Peak memory 214732 kb
Host smart-6d7cacb1-ed16-4b97-8d45-11b33308fcb0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929588307 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_di
sable_auto_req_mode.929588307
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.601682067
Short name T497
Test name
Test status
Simulation time 29829528 ps
CPU time 0.83 seconds
Started Oct 11 12:53:03 PM PDT 23
Finished Oct 11 12:53:04 PM PDT 23
Peak memory 215544 kb
Host smart-45b608f1-128b-40e3-bb3f-a385fef6d0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601682067 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.601682067
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.2692315975
Short name T286
Test name
Test status
Simulation time 48646157 ps
CPU time 0.96 seconds
Started Oct 11 12:53:01 PM PDT 23
Finished Oct 11 12:53:03 PM PDT 23
Peak memory 204980 kb
Host smart-65ec62ee-651c-4ec1-bd3c-5d5ece8c4056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692315975 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.2692315975
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.1290869452
Short name T585
Test name
Test status
Simulation time 31708889 ps
CPU time 0.97 seconds
Started Oct 11 12:52:57 PM PDT 23
Finished Oct 11 12:53:04 PM PDT 23
Peak memory 222104 kb
Host smart-4f9abbb5-41bd-4baf-9022-3593d4b07ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290869452 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.1290869452
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.3316609290
Short name T580
Test name
Test status
Simulation time 15575236 ps
CPU time 0.9 seconds
Started Oct 11 12:53:30 PM PDT 23
Finished Oct 11 12:53:31 PM PDT 23
Peak memory 204792 kb
Host smart-cd2233c2-bbbf-48a6-9187-0b287a1dcdd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316609290 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.3316609290
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.3446823662
Short name T588
Test name
Test status
Simulation time 231956961 ps
CPU time 1.55 seconds
Started Oct 11 12:52:56 PM PDT 23
Finished Oct 11 12:52:59 PM PDT 23
Peak memory 205328 kb
Host smart-b9acc159-3c17-434f-845e-981c64ebe283
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446823662 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.3446823662
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.197598702
Short name T465
Test name
Test status
Simulation time 206090215232 ps
CPU time 1692.68 seconds
Started Oct 11 12:52:58 PM PDT 23
Finished Oct 11 01:21:12 PM PDT 23
Peak memory 218944 kb
Host smart-a676a1d1-3fe5-41ac-bd95-b6d58336449e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197598702 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.197598702
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.18270895
Short name T102
Test name
Test status
Simulation time 54946223 ps
CPU time 0.92 seconds
Started Oct 11 12:54:24 PM PDT 23
Finished Oct 11 12:54:25 PM PDT 23
Peak memory 206120 kb
Host smart-9fd2ed51-9c09-4d03-8e40-899ac9e99b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18270895 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.18270895
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.2630452134
Short name T603
Test name
Test status
Simulation time 36497660 ps
CPU time 0.96 seconds
Started Oct 11 12:53:00 PM PDT 23
Finished Oct 11 12:53:02 PM PDT 23
Peak memory 204656 kb
Host smart-b9836836-08af-43f1-8fb7-3352c290aed7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630452134 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.2630452134
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.1748202250
Short name T126
Test name
Test status
Simulation time 20468578 ps
CPU time 0.82 seconds
Started Oct 11 12:53:00 PM PDT 23
Finished Oct 11 12:53:02 PM PDT 23
Peak memory 214376 kb
Host smart-ae2d9df2-b2af-4036-87c3-69a43a48d1bb
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748202250 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.1748202250
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.2217585826
Short name T105
Test name
Test status
Simulation time 25032182 ps
CPU time 0.96 seconds
Started Oct 11 12:52:54 PM PDT 23
Finished Oct 11 12:52:55 PM PDT 23
Peak memory 214740 kb
Host smart-e00adf92-9a11-42e7-bcab-449ae2df8d5b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217585826 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.2217585826
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.676739317
Short name T566
Test name
Test status
Simulation time 19599242 ps
CPU time 1.34 seconds
Started Oct 11 12:53:06 PM PDT 23
Finished Oct 11 12:53:07 PM PDT 23
Peak memory 215688 kb
Host smart-9bae36e4-efe1-4336-b7e2-71e58fcd4e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676739317 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.676739317
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.2230979483
Short name T284
Test name
Test status
Simulation time 17336168 ps
CPU time 0.92 seconds
Started Oct 11 12:52:27 PM PDT 23
Finished Oct 11 12:52:29 PM PDT 23
Peak memory 204880 kb
Host smart-65d93b1a-b2c9-4664-a2ba-de781d80e8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230979483 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.2230979483
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.1145910705
Short name T479
Test name
Test status
Simulation time 31678542 ps
CPU time 0.87 seconds
Started Oct 11 12:53:25 PM PDT 23
Finished Oct 11 12:53:28 PM PDT 23
Peak memory 214512 kb
Host smart-003e6aa5-11e4-4b2f-a8c4-fd27809caabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145910705 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.1145910705
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.3239788710
Short name T502
Test name
Test status
Simulation time 40572798 ps
CPU time 0.81 seconds
Started Oct 11 12:53:07 PM PDT 23
Finished Oct 11 12:53:09 PM PDT 23
Peak memory 204676 kb
Host smart-2fbc8ece-66d8-4736-be1e-542ec4696d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239788710 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.3239788710
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.3792112489
Short name T494
Test name
Test status
Simulation time 418488500 ps
CPU time 2.78 seconds
Started Oct 11 12:52:54 PM PDT 23
Finished Oct 11 12:52:57 PM PDT 23
Peak memory 206112 kb
Host smart-f3a90923-4371-49a5-be49-afc980e994e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792112489 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.3792112489
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.2286341483
Short name T525
Test name
Test status
Simulation time 104909875982 ps
CPU time 331.7 seconds
Started Oct 11 12:52:45 PM PDT 23
Finished Oct 11 12:58:17 PM PDT 23
Peak memory 222788 kb
Host smart-b431cef7-60d1-4e12-baad-62702d9e5364
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286341483 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.2286341483
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.1249960744
Short name T295
Test name
Test status
Simulation time 64609033 ps
CPU time 0.93 seconds
Started Oct 11 12:52:20 PM PDT 23
Finished Oct 11 12:52:22 PM PDT 23
Peak memory 206108 kb
Host smart-258c91c3-558a-49ba-bd8f-f75a98e8eed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249960744 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.1249960744
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.3107083455
Short name T491
Test name
Test status
Simulation time 34962546 ps
CPU time 0.8 seconds
Started Oct 11 12:52:38 PM PDT 23
Finished Oct 11 12:52:45 PM PDT 23
Peak memory 204388 kb
Host smart-77d3a6bf-360b-4fce-ab04-520932eb2531
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107083455 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.3107083455
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.787925187
Short name T131
Test name
Test status
Simulation time 45941442 ps
CPU time 0.8 seconds
Started Oct 11 12:52:28 PM PDT 23
Finished Oct 11 12:52:29 PM PDT 23
Peak memory 214492 kb
Host smart-c45cbed7-c3a9-4edf-9048-765cfad0b51e
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787925187 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.787925187
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.2501568941
Short name T170
Test name
Test status
Simulation time 65212549 ps
CPU time 0.96 seconds
Started Oct 11 12:52:20 PM PDT 23
Finished Oct 11 12:52:22 PM PDT 23
Peak memory 214664 kb
Host smart-408d26b7-134e-4a20-b04c-882f24e65e01
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501568941 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.2501568941
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.660093329
Short name T327
Test name
Test status
Simulation time 24301421 ps
CPU time 0.92 seconds
Started Oct 11 12:52:49 PM PDT 23
Finished Oct 11 12:52:53 PM PDT 23
Peak memory 215468 kb
Host smart-15b6778c-0236-42ff-aba2-5c015f5e3b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660093329 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.660093329
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.171364369
Short name T60
Test name
Test status
Simulation time 24367280 ps
CPU time 0.86 seconds
Started Oct 11 12:52:54 PM PDT 23
Finished Oct 11 12:52:55 PM PDT 23
Peak memory 205216 kb
Host smart-d8b2ad5c-a65b-4eb9-a60e-a190f8964714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171364369 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.171364369
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_regwen.1213293787
Short name T260
Test name
Test status
Simulation time 13784394 ps
CPU time 0.92 seconds
Started Oct 11 12:52:19 PM PDT 23
Finished Oct 11 12:52:21 PM PDT 23
Peak memory 205112 kb
Host smart-823dc7a6-6a3e-4f6a-81aa-acf1c43099b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213293787 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.1213293787
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.770409765
Short name T316
Test name
Test status
Simulation time 82928834 ps
CPU time 0.78 seconds
Started Oct 11 12:52:27 PM PDT 23
Finished Oct 11 12:52:28 PM PDT 23
Peak memory 204484 kb
Host smart-ae637c22-274d-47b4-8d7b-c93049c748a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770409765 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.770409765
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.2059865336
Short name T651
Test name
Test status
Simulation time 173646185 ps
CPU time 2.33 seconds
Started Oct 11 12:52:27 PM PDT 23
Finished Oct 11 12:52:29 PM PDT 23
Peak memory 205648 kb
Host smart-22b520a7-fe42-48f9-a0a5-472b88403ed9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059865336 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.2059865336
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.2820199362
Short name T641
Test name
Test status
Simulation time 1366179923698 ps
CPU time 2065.39 seconds
Started Oct 11 12:52:45 PM PDT 23
Finished Oct 11 01:27:11 PM PDT 23
Peak memory 220224 kb
Host smart-ae6516cd-c0a7-4659-b77a-f4f50480c0ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820199362 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.2820199362
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.3912548331
Short name T660
Test name
Test status
Simulation time 25435545 ps
CPU time 1.19 seconds
Started Oct 11 12:53:55 PM PDT 23
Finished Oct 11 12:53:56 PM PDT 23
Peak memory 215748 kb
Host smart-808295a4-785b-4012-8c85-38789fdf3113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912548331 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.3912548331
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/51.edn_err.237833595
Short name T11
Test name
Test status
Simulation time 20835919 ps
CPU time 1.16 seconds
Started Oct 11 12:53:08 PM PDT 23
Finished Oct 11 12:53:09 PM PDT 23
Peak memory 228576 kb
Host smart-2f7bfde1-2af9-4b46-a356-37e1141c543b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237833595 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.237833595
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/52.edn_err.2535115096
Short name T245
Test name
Test status
Simulation time 18546861 ps
CPU time 0.99 seconds
Started Oct 11 12:53:09 PM PDT 23
Finished Oct 11 12:53:11 PM PDT 23
Peak memory 214516 kb
Host smart-6530ffe9-de66-443d-9768-07f3af4f97a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535115096 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.2535115096
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/53.edn_err.3283653446
Short name T449
Test name
Test status
Simulation time 33582667 ps
CPU time 0.78 seconds
Started Oct 11 12:52:56 PM PDT 23
Finished Oct 11 12:52:57 PM PDT 23
Peak memory 215524 kb
Host smart-c5a01cd9-4c38-47c0-a3e2-3e180035fc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283653446 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.3283653446
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/54.edn_err.49133723
Short name T661
Test name
Test status
Simulation time 21958744 ps
CPU time 0.95 seconds
Started Oct 11 12:53:40 PM PDT 23
Finished Oct 11 12:53:41 PM PDT 23
Peak memory 221532 kb
Host smart-42497db7-300f-4f19-83b6-b7b8beff2430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49133723 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.49133723
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/55.edn_err.3304519435
Short name T168
Test name
Test status
Simulation time 34738072 ps
CPU time 0.88 seconds
Started Oct 11 12:53:01 PM PDT 23
Finished Oct 11 12:53:03 PM PDT 23
Peak memory 214768 kb
Host smart-632dffd0-e523-4d6c-a045-f6a64ddf76c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304519435 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.3304519435
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/56.edn_err.4177826477
Short name T567
Test name
Test status
Simulation time 25172177 ps
CPU time 1.12 seconds
Started Oct 11 12:53:10 PM PDT 23
Finished Oct 11 12:53:11 PM PDT 23
Peak memory 215936 kb
Host smart-ea5a4d9d-2095-443e-a728-562ff259a888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177826477 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.4177826477
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/57.edn_err.1217654418
Short name T49
Test name
Test status
Simulation time 22018427 ps
CPU time 1.11 seconds
Started Oct 11 12:53:52 PM PDT 23
Finished Oct 11 12:53:53 PM PDT 23
Peak memory 221568 kb
Host smart-bcd56358-835c-47f3-a1fa-ba75f4294ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217654418 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.1217654418
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/58.edn_err.2090449449
Short name T169
Test name
Test status
Simulation time 32002372 ps
CPU time 1 seconds
Started Oct 11 12:53:24 PM PDT 23
Finished Oct 11 12:53:25 PM PDT 23
Peak memory 214540 kb
Host smart-1c0b6d35-30cb-410a-ac5b-ec81df1ceb46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090449449 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2090449449
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/59.edn_err.1705349972
Short name T46
Test name
Test status
Simulation time 57615342 ps
CPU time 1.15 seconds
Started Oct 11 12:53:48 PM PDT 23
Finished Oct 11 12:53:50 PM PDT 23
Peak memory 228532 kb
Host smart-2701dc68-10b0-4d18-bc45-bdffb5fb2f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705349972 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.1705349972
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/6.edn_alert.772686976
Short name T559
Test name
Test status
Simulation time 22012365 ps
CPU time 0.97 seconds
Started Oct 11 12:52:51 PM PDT 23
Finished Oct 11 12:52:52 PM PDT 23
Peak memory 205260 kb
Host smart-95bb3c8b-ff99-457f-9850-7a55650d9b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772686976 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.772686976
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.2284889542
Short name T459
Test name
Test status
Simulation time 11884922 ps
CPU time 0.82 seconds
Started Oct 11 12:52:54 PM PDT 23
Finished Oct 11 12:52:56 PM PDT 23
Peak memory 204332 kb
Host smart-8c84c401-b044-46ed-9a86-65db75be9452
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284889542 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.2284889542
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.2830327276
Short name T33
Test name
Test status
Simulation time 12144232 ps
CPU time 0.85 seconds
Started Oct 11 12:52:36 PM PDT 23
Finished Oct 11 12:52:37 PM PDT 23
Peak memory 214456 kb
Host smart-425e825d-5d10-48bd-a25c-9eb8a7a81faf
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830327276 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.2830327276
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.1828762090
Short name T243
Test name
Test status
Simulation time 112587312 ps
CPU time 0.99 seconds
Started Oct 11 12:52:30 PM PDT 23
Finished Oct 11 12:52:32 PM PDT 23
Peak memory 214728 kb
Host smart-e5bd9e3b-a4d2-401a-a0c5-112930d4091e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828762090 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.1828762090
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.1527080551
Short name T244
Test name
Test status
Simulation time 30127122 ps
CPU time 0.8 seconds
Started Oct 11 12:53:03 PM PDT 23
Finished Oct 11 12:53:05 PM PDT 23
Peak memory 214372 kb
Host smart-f7d77e99-d61b-4050-bc65-ae551a18c7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527080551 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.1527080551
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.1964314127
Short name T78
Test name
Test status
Simulation time 30455977 ps
CPU time 1.42 seconds
Started Oct 11 12:52:50 PM PDT 23
Finished Oct 11 12:52:52 PM PDT 23
Peak memory 214464 kb
Host smart-97e975ce-9e25-4bdc-a733-755649a6febb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964314127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.1964314127
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.53678564
Short name T672
Test name
Test status
Simulation time 24906303 ps
CPU time 0.87 seconds
Started Oct 11 12:53:06 PM PDT 23
Finished Oct 11 12:53:07 PM PDT 23
Peak memory 214792 kb
Host smart-fe343fbd-eceb-4545-b8da-7a1aa6901586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53678564 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.53678564
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.4112564692
Short name T587
Test name
Test status
Simulation time 15267888 ps
CPU time 0.92 seconds
Started Oct 11 12:53:12 PM PDT 23
Finished Oct 11 12:53:15 PM PDT 23
Peak memory 204860 kb
Host smart-7b914005-f3d7-4d0f-b233-b9ae7196b0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112564692 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.4112564692
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.3753930295
Short name T492
Test name
Test status
Simulation time 38620193 ps
CPU time 0.8 seconds
Started Oct 11 12:53:13 PM PDT 23
Finished Oct 11 12:53:15 PM PDT 23
Peak memory 204992 kb
Host smart-6302345d-e78b-4af8-bd6d-24b1c7706e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753930295 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.3753930295
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.2575771696
Short name T707
Test name
Test status
Simulation time 64533474 ps
CPU time 1.74 seconds
Started Oct 11 12:52:46 PM PDT 23
Finished Oct 11 12:52:48 PM PDT 23
Peak memory 205712 kb
Host smart-c6dfecae-4b73-4a49-8b25-5d819fe5c521
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575771696 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.2575771696
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.2817484141
Short name T540
Test name
Test status
Simulation time 28020864997 ps
CPU time 603.79 seconds
Started Oct 11 12:52:36 PM PDT 23
Finished Oct 11 01:02:40 PM PDT 23
Peak memory 215900 kb
Host smart-b761ca20-5acf-4497-8ce8-ec0760288fea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817484141 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.2817484141
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.717913642
Short name T182
Test name
Test status
Simulation time 19463943 ps
CPU time 1.17 seconds
Started Oct 11 12:53:16 PM PDT 23
Finished Oct 11 12:53:18 PM PDT 23
Peak memory 228576 kb
Host smart-e827cc53-3d98-4ead-875f-465f2dc34830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717913642 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.717913642
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/61.edn_err.127326253
Short name T697
Test name
Test status
Simulation time 24919191 ps
CPU time 0.86 seconds
Started Oct 11 12:53:54 PM PDT 23
Finished Oct 11 12:53:55 PM PDT 23
Peak memory 215616 kb
Host smart-4336b43d-92b4-4e43-a488-52c1fb25d2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127326253 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.127326253
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/62.edn_err.324441124
Short name T194
Test name
Test status
Simulation time 24673231 ps
CPU time 0.91 seconds
Started Oct 11 12:53:05 PM PDT 23
Finished Oct 11 12:53:06 PM PDT 23
Peak memory 215684 kb
Host smart-46897c5f-30a4-4738-b418-707ec33005ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324441124 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.324441124
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/63.edn_err.3741629876
Short name T45
Test name
Test status
Simulation time 27476094 ps
CPU time 1.06 seconds
Started Oct 11 12:53:13 PM PDT 23
Finished Oct 11 12:53:15 PM PDT 23
Peak memory 222096 kb
Host smart-62088687-f076-4de1-8850-351e2ceb9276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741629876 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.3741629876
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/64.edn_err.4041500252
Short name T277
Test name
Test status
Simulation time 167538489 ps
CPU time 1.1 seconds
Started Oct 11 12:53:07 PM PDT 23
Finished Oct 11 12:53:09 PM PDT 23
Peak memory 214508 kb
Host smart-a7cc30a3-e27b-4375-bb19-3bbe0c38b5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041500252 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.4041500252
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/65.edn_err.2365450447
Short name T450
Test name
Test status
Simulation time 19231848 ps
CPU time 1.15 seconds
Started Oct 11 12:54:16 PM PDT 23
Finished Oct 11 12:54:18 PM PDT 23
Peak memory 221624 kb
Host smart-a2d1de95-49cc-4696-b76a-2f6fb2e3e42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365450447 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.2365450447
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/66.edn_err.276365470
Short name T460
Test name
Test status
Simulation time 23746361 ps
CPU time 0.87 seconds
Started Oct 11 12:53:26 PM PDT 23
Finished Oct 11 12:53:27 PM PDT 23
Peak memory 215724 kb
Host smart-7c5008f5-2da2-43d5-afb2-bd276cd91267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276365470 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.276365470
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/67.edn_err.2099755417
Short name T171
Test name
Test status
Simulation time 23491529 ps
CPU time 1.1 seconds
Started Oct 11 12:53:48 PM PDT 23
Finished Oct 11 12:53:50 PM PDT 23
Peak memory 214612 kb
Host smart-ac83591f-952a-4497-b03f-29271e8d0454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099755417 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.2099755417
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/68.edn_err.2733742903
Short name T175
Test name
Test status
Simulation time 65164775 ps
CPU time 1.01 seconds
Started Oct 11 12:53:35 PM PDT 23
Finished Oct 11 12:53:37 PM PDT 23
Peak memory 230264 kb
Host smart-b644cf17-6be7-4f14-b244-7cc6569d57a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733742903 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.2733742903
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/69.edn_err.2352088580
Short name T12
Test name
Test status
Simulation time 29180787 ps
CPU time 1.01 seconds
Started Oct 11 12:53:51 PM PDT 23
Finished Oct 11 12:53:52 PM PDT 23
Peak memory 222280 kb
Host smart-ed8ff8ea-d779-49f9-ae45-83bdad376534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352088580 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.2352088580
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/7.edn_alert.3092440195
Short name T643
Test name
Test status
Simulation time 32107340 ps
CPU time 0.93 seconds
Started Oct 11 12:51:15 PM PDT 23
Finished Oct 11 12:51:17 PM PDT 23
Peak memory 205272 kb
Host smart-7451c1b2-968c-4a70-b1bf-ca881cd48659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092440195 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.3092440195
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.435873190
Short name T505
Test name
Test status
Simulation time 16188111 ps
CPU time 0.88 seconds
Started Oct 11 12:51:37 PM PDT 23
Finished Oct 11 12:51:39 PM PDT 23
Peak memory 205272 kb
Host smart-d9b93a57-2105-4a73-b1dc-549c37a692fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435873190 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.435873190
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.875526103
Short name T37
Test name
Test status
Simulation time 25707485 ps
CPU time 1.05 seconds
Started Oct 11 12:51:46 PM PDT 23
Finished Oct 11 12:51:48 PM PDT 23
Peak memory 214668 kb
Host smart-134a443b-8b69-4a90-84b3-257eedcd0a7b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875526103 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_dis
able_auto_req_mode.875526103
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.1599155407
Short name T72
Test name
Test status
Simulation time 27166663 ps
CPU time 0.91 seconds
Started Oct 11 12:51:34 PM PDT 23
Finished Oct 11 12:51:36 PM PDT 23
Peak memory 215892 kb
Host smart-dc7e63ea-5297-4541-8e67-fdbee436d43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599155407 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.1599155407
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.3132372166
Short name T98
Test name
Test status
Simulation time 95968019 ps
CPU time 1.18 seconds
Started Oct 11 12:52:37 PM PDT 23
Finished Oct 11 12:52:41 PM PDT 23
Peak memory 205520 kb
Host smart-42c7fb02-e7c4-470f-8dc2-c614b58fa0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132372166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.3132372166
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.925585627
Short name T73
Test name
Test status
Simulation time 30585151 ps
CPU time 0.79 seconds
Started Oct 11 12:51:30 PM PDT 23
Finished Oct 11 12:51:31 PM PDT 23
Peak memory 214544 kb
Host smart-16c018ce-e779-4706-b488-7e77a67b5e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925585627 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.925585627
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.3156396645
Short name T306
Test name
Test status
Simulation time 26485896 ps
CPU time 0.87 seconds
Started Oct 11 12:51:15 PM PDT 23
Finished Oct 11 12:51:16 PM PDT 23
Peak memory 204772 kb
Host smart-6710c0c3-28fe-4ac1-9714-7c2b0455562a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156396645 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.3156396645
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.840369453
Short name T466
Test name
Test status
Simulation time 20896001 ps
CPU time 0.86 seconds
Started Oct 11 12:51:20 PM PDT 23
Finished Oct 11 12:51:22 PM PDT 23
Peak memory 204924 kb
Host smart-8cc75437-1456-4831-aca7-c5a91071e470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840369453 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.840369453
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.150276285
Short name T720
Test name
Test status
Simulation time 112705428 ps
CPU time 2.6 seconds
Started Oct 11 12:51:31 PM PDT 23
Finished Oct 11 12:51:34 PM PDT 23
Peak memory 205900 kb
Host smart-eeafdd7e-2238-43dc-b3db-3f23c645ade2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150276285 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.150276285
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.2514980215
Short name T701
Test name
Test status
Simulation time 66671264500 ps
CPU time 1546.16 seconds
Started Oct 11 12:51:51 PM PDT 23
Finished Oct 11 01:17:38 PM PDT 23
Peak memory 219588 kb
Host smart-d4dce696-4c48-4314-a02b-ec438acda33c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514980215 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.2514980215
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.1337819280
Short name T606
Test name
Test status
Simulation time 23096032 ps
CPU time 0.88 seconds
Started Oct 11 12:53:51 PM PDT 23
Finished Oct 11 12:53:52 PM PDT 23
Peak memory 215540 kb
Host smart-9528534a-81ff-40f6-92c8-35dce24a0aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337819280 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.1337819280
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/72.edn_err.3125678837
Short name T173
Test name
Test status
Simulation time 33184925 ps
CPU time 0.96 seconds
Started Oct 11 12:53:30 PM PDT 23
Finished Oct 11 12:53:32 PM PDT 23
Peak memory 228852 kb
Host smart-7d9588cc-058b-44f5-bcbd-f34078de5667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125678837 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.3125678837
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/73.edn_err.3120528976
Short name T636
Test name
Test status
Simulation time 57897871 ps
CPU time 1.2 seconds
Started Oct 11 12:54:13 PM PDT 23
Finished Oct 11 12:54:15 PM PDT 23
Peak memory 214636 kb
Host smart-90bf89aa-afc2-4b54-84fb-30440426f21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120528976 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.3120528976
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/74.edn_err.1592446551
Short name T642
Test name
Test status
Simulation time 22925439 ps
CPU time 0.94 seconds
Started Oct 11 12:53:38 PM PDT 23
Finished Oct 11 12:53:39 PM PDT 23
Peak memory 215676 kb
Host smart-00c097f1-a15e-4827-bf56-2d5b5298ed0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592446551 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.1592446551
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/75.edn_err.4180485484
Short name T183
Test name
Test status
Simulation time 20554684 ps
CPU time 1.02 seconds
Started Oct 11 12:53:36 PM PDT 23
Finished Oct 11 12:53:38 PM PDT 23
Peak memory 214552 kb
Host smart-660236c6-2e0e-4143-8afb-5b80ff899f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180485484 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.4180485484
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/76.edn_err.1174918034
Short name T48
Test name
Test status
Simulation time 32371933 ps
CPU time 0.95 seconds
Started Oct 11 12:54:31 PM PDT 23
Finished Oct 11 12:54:34 PM PDT 23
Peak memory 222056 kb
Host smart-83c50680-bc7e-4760-9d74-6913627b38d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174918034 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.1174918034
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/77.edn_err.964715666
Short name T330
Test name
Test status
Simulation time 18611619 ps
CPU time 0.93 seconds
Started Oct 11 12:54:31 PM PDT 23
Finished Oct 11 12:54:36 PM PDT 23
Peak memory 215496 kb
Host smart-aabb44f1-3a7b-45d2-bc2a-e4aa150a5ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964715666 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.964715666
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/78.edn_err.784129466
Short name T246
Test name
Test status
Simulation time 18391113 ps
CPU time 1.28 seconds
Started Oct 11 12:53:43 PM PDT 23
Finished Oct 11 12:53:44 PM PDT 23
Peak memory 215872 kb
Host smart-521fc78f-3a03-45c8-98a5-add9d7878fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784129466 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.784129466
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/79.edn_err.703353416
Short name T202
Test name
Test status
Simulation time 28002295 ps
CPU time 0.92 seconds
Started Oct 11 12:53:18 PM PDT 23
Finished Oct 11 12:53:20 PM PDT 23
Peak memory 221508 kb
Host smart-3a270866-52b5-4a9f-9d51-535dabead3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703353416 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.703353416
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/8.edn_alert.3144974691
Short name T301
Test name
Test status
Simulation time 18320353 ps
CPU time 1.01 seconds
Started Oct 11 12:51:28 PM PDT 23
Finished Oct 11 12:51:29 PM PDT 23
Peak memory 206044 kb
Host smart-6304d7bc-f288-4486-a37a-93afb09def74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144974691 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.3144974691
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.4190712111
Short name T322
Test name
Test status
Simulation time 26864849 ps
CPU time 0.78 seconds
Started Oct 11 12:51:35 PM PDT 23
Finished Oct 11 12:51:38 PM PDT 23
Peak memory 204564 kb
Host smart-b9107072-dab1-4ab2-8d54-0453675cd3fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190712111 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.4190712111
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.4140674836
Short name T670
Test name
Test status
Simulation time 11076975 ps
CPU time 0.83 seconds
Started Oct 11 12:52:06 PM PDT 23
Finished Oct 11 12:52:07 PM PDT 23
Peak memory 214452 kb
Host smart-439cd7b3-fcc8-4769-b544-786c64208d15
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140674836 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.4140674836
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.3205832906
Short name T523
Test name
Test status
Simulation time 79287558 ps
CPU time 0.97 seconds
Started Oct 11 12:52:19 PM PDT 23
Finished Oct 11 12:52:20 PM PDT 23
Peak memory 214612 kb
Host smart-197af93d-f05c-46ba-8d3f-d32b342ddcb6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205832906 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.3205832906
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.3675659766
Short name T616
Test name
Test status
Simulation time 23868599 ps
CPU time 1.18 seconds
Started Oct 11 12:51:29 PM PDT 23
Finished Oct 11 12:51:30 PM PDT 23
Peak memory 222168 kb
Host smart-e35246e0-a2b2-4492-b981-7897027ac6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675659766 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3675659766
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_intr.3244368016
Short name T631
Test name
Test status
Simulation time 35535035 ps
CPU time 0.93 seconds
Started Oct 11 12:52:21 PM PDT 23
Finished Oct 11 12:52:22 PM PDT 23
Peak memory 221448 kb
Host smart-c110cf51-fb39-4d48-874e-47afc769e6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244368016 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.3244368016
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_smoke.439225561
Short name T680
Test name
Test status
Simulation time 49094624 ps
CPU time 0.86 seconds
Started Oct 11 12:51:32 PM PDT 23
Finished Oct 11 12:51:33 PM PDT 23
Peak memory 204700 kb
Host smart-8fb5191c-2777-4dcb-9eb2-27e998355917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439225561 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.439225561
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.4237993128
Short name T726
Test name
Test status
Simulation time 194764923 ps
CPU time 2.22 seconds
Started Oct 11 12:51:12 PM PDT 23
Finished Oct 11 12:51:15 PM PDT 23
Peak memory 205852 kb
Host smart-a9b54743-20a6-4d5b-b5be-737b91e1cabd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237993128 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.4237993128
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.1819306765
Short name T499
Test name
Test status
Simulation time 121531413934 ps
CPU time 1151.68 seconds
Started Oct 11 12:52:14 PM PDT 23
Finished Oct 11 01:11:26 PM PDT 23
Peak memory 218372 kb
Host smart-c265a5af-71c1-4afa-8788-d9b229956331
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819306765 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.1819306765
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.2187642470
Short name T111
Test name
Test status
Simulation time 34520488 ps
CPU time 1.03 seconds
Started Oct 11 12:53:02 PM PDT 23
Finished Oct 11 12:53:04 PM PDT 23
Peak memory 215940 kb
Host smart-6c5e3bf7-6f73-4964-bf4c-110e37ffe221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187642470 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.2187642470
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/82.edn_err.2237578530
Short name T187
Test name
Test status
Simulation time 75556619 ps
CPU time 0.88 seconds
Started Oct 11 12:53:03 PM PDT 23
Finished Oct 11 12:53:04 PM PDT 23
Peak memory 221244 kb
Host smart-d7f0c7a9-7971-4cb2-8f98-7a2935472c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237578530 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.2237578530
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/83.edn_err.768075479
Short name T113
Test name
Test status
Simulation time 45873334 ps
CPU time 1.02 seconds
Started Oct 11 12:52:46 PM PDT 23
Finished Oct 11 12:52:47 PM PDT 23
Peak memory 230300 kb
Host smart-78e442ac-a7bd-42a2-a3ad-67abf8f0cf08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768075479 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.768075479
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/84.edn_err.840057632
Short name T184
Test name
Test status
Simulation time 68485066 ps
CPU time 0.91 seconds
Started Oct 11 12:52:49 PM PDT 23
Finished Oct 11 12:52:51 PM PDT 23
Peak memory 214488 kb
Host smart-3d5328c9-361d-430b-bf08-9430c8cbe8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840057632 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.840057632
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/85.edn_err.257148935
Short name T176
Test name
Test status
Simulation time 32087438 ps
CPU time 1.06 seconds
Started Oct 11 12:53:01 PM PDT 23
Finished Oct 11 12:53:03 PM PDT 23
Peak memory 215772 kb
Host smart-1b0a0150-b3ca-4760-b6c1-c73a05f7b83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257148935 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.257148935
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/86.edn_err.3214379625
Short name T655
Test name
Test status
Simulation time 21713890 ps
CPU time 0.84 seconds
Started Oct 11 12:53:19 PM PDT 23
Finished Oct 11 12:53:20 PM PDT 23
Peak memory 215560 kb
Host smart-427443d8-3921-4d81-9072-f045d24c8cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214379625 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.3214379625
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/87.edn_err.4241937366
Short name T172
Test name
Test status
Simulation time 55964297 ps
CPU time 0.99 seconds
Started Oct 11 12:53:19 PM PDT 23
Finished Oct 11 12:53:21 PM PDT 23
Peak memory 228944 kb
Host smart-760cb2b5-9284-4996-a34f-704d3f3e8093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241937366 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.4241937366
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/88.edn_err.937236809
Short name T200
Test name
Test status
Simulation time 29911852 ps
CPU time 0.9 seconds
Started Oct 11 12:53:01 PM PDT 23
Finished Oct 11 12:53:02 PM PDT 23
Peak memory 221344 kb
Host smart-4c30e0e5-39da-41ba-81c6-832b9a79380b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937236809 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.937236809
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/89.edn_err.2171548490
Short name T193
Test name
Test status
Simulation time 29571565 ps
CPU time 1.2 seconds
Started Oct 11 12:53:00 PM PDT 23
Finished Oct 11 12:53:03 PM PDT 23
Peak memory 216840 kb
Host smart-04ea17f0-5d6f-41c3-91a2-eda24b4d427d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171548490 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.2171548490
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/9.edn_alert.3695002192
Short name T291
Test name
Test status
Simulation time 30442096 ps
CPU time 0.88 seconds
Started Oct 11 12:52:07 PM PDT 23
Finished Oct 11 12:52:08 PM PDT 23
Peak memory 205228 kb
Host smart-bf9fa664-0508-4d30-8ec6-da99f45ffc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695002192 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.3695002192
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.2771303078
Short name T461
Test name
Test status
Simulation time 47945217 ps
CPU time 0.75 seconds
Started Oct 11 12:51:59 PM PDT 23
Finished Oct 11 12:52:00 PM PDT 23
Peak memory 204288 kb
Host smart-4866cfda-2b06-4b2a-bc41-ecc984850707
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771303078 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.2771303078
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.4146060757
Short name T711
Test name
Test status
Simulation time 22247922 ps
CPU time 0.8 seconds
Started Oct 11 12:53:01 PM PDT 23
Finished Oct 11 12:53:02 PM PDT 23
Peak memory 214360 kb
Host smart-dc00d2f3-3263-47a7-b789-aa80c134920e
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146060757 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.4146060757
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.3299570864
Short name T252
Test name
Test status
Simulation time 17449160 ps
CPU time 1 seconds
Started Oct 11 12:52:14 PM PDT 23
Finished Oct 11 12:52:16 PM PDT 23
Peak memory 214564 kb
Host smart-3e8b090c-c549-45a5-accc-096ad10d27ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299570864 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.3299570864
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.3022793539
Short name T669
Test name
Test status
Simulation time 19154413 ps
CPU time 1.06 seconds
Started Oct 11 12:52:15 PM PDT 23
Finished Oct 11 12:52:17 PM PDT 23
Peak memory 215636 kb
Host smart-429cd8ef-2166-4a91-a797-af61768920a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022793539 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.3022793539
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.1116428902
Short name T691
Test name
Test status
Simulation time 64312725 ps
CPU time 1.2 seconds
Started Oct 11 12:52:21 PM PDT 23
Finished Oct 11 12:52:25 PM PDT 23
Peak memory 205464 kb
Host smart-1c13b680-db83-465b-9472-90ead33725be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116428902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.1116428902
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.2898702980
Short name T452
Test name
Test status
Simulation time 34484188 ps
CPU time 0.83 seconds
Started Oct 11 12:51:37 PM PDT 23
Finished Oct 11 12:51:38 PM PDT 23
Peak memory 214572 kb
Host smart-f7e9a644-c24c-47be-83f2-3ec841233af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898702980 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.2898702980
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.1080659308
Short name T297
Test name
Test status
Simulation time 53168634 ps
CPU time 0.84 seconds
Started Oct 11 12:52:06 PM PDT 23
Finished Oct 11 12:52:08 PM PDT 23
Peak memory 204728 kb
Host smart-ec725de9-0ca0-407b-a691-8c02de7199ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080659308 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.1080659308
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.1688553723
Short name T310
Test name
Test status
Simulation time 20284164 ps
CPU time 0.85 seconds
Started Oct 11 12:52:04 PM PDT 23
Finished Oct 11 12:52:05 PM PDT 23
Peak memory 204840 kb
Host smart-8370e4aa-e607-456b-9011-a2a6d2df19ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688553723 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.1688553723
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.2552196378
Short name T454
Test name
Test status
Simulation time 1045211168 ps
CPU time 3.73 seconds
Started Oct 11 12:51:40 PM PDT 23
Finished Oct 11 12:51:44 PM PDT 23
Peak memory 205676 kb
Host smart-86dd0e21-8f44-4ea2-9efd-509000890f88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552196378 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.2552196378
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.487040205
Short name T676
Test name
Test status
Simulation time 149157325381 ps
CPU time 1768.07 seconds
Started Oct 11 12:52:14 PM PDT 23
Finished Oct 11 01:21:42 PM PDT 23
Peak memory 218520 kb
Host smart-070fbc19-19b8-4e3b-abb6-0289c69d4ba1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487040205 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.487040205
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.1616719692
Short name T326
Test name
Test status
Simulation time 33453703 ps
CPU time 1.02 seconds
Started Oct 11 12:53:29 PM PDT 23
Finished Oct 11 12:53:30 PM PDT 23
Peak memory 214636 kb
Host smart-18c958a8-f861-450b-a258-af72bc2e5897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616719692 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.1616719692
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/91.edn_err.3437877937
Short name T196
Test name
Test status
Simulation time 40901016 ps
CPU time 0.81 seconds
Started Oct 11 12:54:53 PM PDT 23
Finished Oct 11 12:54:54 PM PDT 23
Peak memory 215568 kb
Host smart-01a8655d-714f-48da-94ec-b8a914dcd5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437877937 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.3437877937
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/93.edn_err.2617461531
Short name T250
Test name
Test status
Simulation time 24521200 ps
CPU time 1.15 seconds
Started Oct 11 12:53:09 PM PDT 23
Finished Oct 11 12:53:11 PM PDT 23
Peak memory 216056 kb
Host smart-f2d3c559-e2d7-401b-98df-2f67f17b82d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617461531 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.2617461531
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/94.edn_err.3573114048
Short name T500
Test name
Test status
Simulation time 29141477 ps
CPU time 0.82 seconds
Started Oct 11 12:53:17 PM PDT 23
Finished Oct 11 12:53:18 PM PDT 23
Peak memory 215480 kb
Host smart-04e0edc0-6e41-46ac-bd32-0a1ea93611c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573114048 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.3573114048
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/95.edn_err.2818882723
Short name T5
Test name
Test status
Simulation time 20564587 ps
CPU time 1.07 seconds
Started Oct 11 12:53:33 PM PDT 23
Finished Oct 11 12:53:34 PM PDT 23
Peak memory 214548 kb
Host smart-f1a8ec51-24a7-43ec-aaf0-9dca053b9c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818882723 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.2818882723
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/96.edn_err.373588855
Short name T50
Test name
Test status
Simulation time 24795816 ps
CPU time 0.89 seconds
Started Oct 11 12:53:49 PM PDT 23
Finished Oct 11 12:53:51 PM PDT 23
Peak memory 221492 kb
Host smart-8be36f0f-fd18-4eca-b920-969392688085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373588855 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.373588855
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/97.edn_err.2494198023
Short name T488
Test name
Test status
Simulation time 66021642 ps
CPU time 0.98 seconds
Started Oct 11 12:52:37 PM PDT 23
Finished Oct 11 12:52:39 PM PDT 23
Peak memory 215752 kb
Host smart-2cb3f3ae-359f-44ae-a6b2-f51d7ed351d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494198023 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.2494198023
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/98.edn_err.2290666115
Short name T463
Test name
Test status
Simulation time 21900364 ps
CPU time 0.92 seconds
Started Oct 11 12:53:29 PM PDT 23
Finished Oct 11 12:53:31 PM PDT 23
Peak memory 215760 kb
Host smart-3290121f-c01a-45db-bd08-9f625667e3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290666115 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.2290666115
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/99.edn_err.62574738
Short name T47
Test name
Test status
Simulation time 19554833 ps
CPU time 1.15 seconds
Started Oct 11 12:52:39 PM PDT 23
Finished Oct 11 12:52:41 PM PDT 23
Peak memory 222220 kb
Host smart-93fe9137-1216-4c05-80b9-290871fb286a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62574738 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.62574738
Directory /workspace/99.edn_err/latest
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