Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.21 99.02 92.39 96.84 93.42 98.62 99.77 93.40


Total test records in report: 728
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T555 /workspace/coverage/default/38.edn_alert_test.82373506 Oct 15 01:33:14 PM PDT 23 Oct 15 01:33:15 PM PDT 23 46454583 ps
T249 /workspace/coverage/default/98.edn_err.2660771810 Oct 15 01:34:13 PM PDT 23 Oct 15 01:34:15 PM PDT 23 18243504 ps
T166 /workspace/coverage/default/37.edn_disable_auto_req_mode.1150311564 Oct 15 01:33:10 PM PDT 23 Oct 15 01:33:12 PM PDT 23 24790553 ps
T556 /workspace/coverage/default/4.edn_disable_auto_req_mode.2765482994 Oct 15 01:31:35 PM PDT 23 Oct 15 01:31:36 PM PDT 23 47270294 ps
T152 /workspace/coverage/default/25.edn_disable.3504083995 Oct 15 01:31:46 PM PDT 23 Oct 15 01:31:48 PM PDT 23 10577479 ps
T179 /workspace/coverage/default/30.edn_disable.4099137912 Oct 15 01:32:12 PM PDT 23 Oct 15 01:32:14 PM PDT 23 55929691 ps
T299 /workspace/coverage/default/10.edn_alert.2005390476 Oct 15 01:31:24 PM PDT 23 Oct 15 01:31:26 PM PDT 23 24064652 ps
T557 /workspace/coverage/default/14.edn_smoke.1914352791 Oct 15 01:31:01 PM PDT 23 Oct 15 01:31:02 PM PDT 23 13513104 ps
T177 /workspace/coverage/default/10.edn_disable.76737805 Oct 15 01:31:05 PM PDT 23 Oct 15 01:31:06 PM PDT 23 28070990 ps
T558 /workspace/coverage/default/84.edn_err.1352872213 Oct 15 01:33:01 PM PDT 23 Oct 15 01:33:03 PM PDT 23 30531060 ps
T559 /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3676318045 Oct 15 01:31:19 PM PDT 23 Oct 15 01:51:25 PM PDT 23 100358777424 ps
T560 /workspace/coverage/default/15.edn_disable_auto_req_mode.865708280 Oct 15 01:30:59 PM PDT 23 Oct 15 01:31:01 PM PDT 23 32500093 ps
T561 /workspace/coverage/default/18.edn_alert_test.3440731018 Oct 15 01:31:34 PM PDT 23 Oct 15 01:31:36 PM PDT 23 17965871 ps
T562 /workspace/coverage/default/11.edn_stress_all_with_rand_reset.3942211485 Oct 15 01:31:14 PM PDT 23 Oct 15 02:14:07 PM PDT 23 111971689725 ps
T305 /workspace/coverage/default/3.edn_regwen.1162757138 Oct 15 01:31:03 PM PDT 23 Oct 15 01:31:05 PM PDT 23 46488810 ps
T306 /workspace/coverage/default/39.edn_alert.1862617772 Oct 15 01:33:59 PM PDT 23 Oct 15 01:34:01 PM PDT 23 26455350 ps
T300 /workspace/coverage/default/33.edn_alert.196267741 Oct 15 01:31:40 PM PDT 23 Oct 15 01:31:42 PM PDT 23 125928316 ps
T253 /workspace/coverage/default/13.edn_err.3810268221 Oct 15 01:31:05 PM PDT 23 Oct 15 01:31:06 PM PDT 23 22166691 ps
T563 /workspace/coverage/default/28.edn_err.1605402918 Oct 15 01:31:41 PM PDT 23 Oct 15 01:31:43 PM PDT 23 29025216 ps
T62 /workspace/coverage/default/3.edn_sec_cm.4229215537 Oct 15 01:31:26 PM PDT 23 Oct 15 01:31:32 PM PDT 23 1374229345 ps
T564 /workspace/coverage/default/72.edn_err.4112356002 Oct 15 01:33:40 PM PDT 23 Oct 15 01:33:42 PM PDT 23 24872997 ps
T268 /workspace/coverage/default/31.edn_stress_all.3862145488 Oct 15 01:31:41 PM PDT 23 Oct 15 01:31:43 PM PDT 23 115625772 ps
T302 /workspace/coverage/default/13.edn_alert.1578663380 Oct 15 01:31:03 PM PDT 23 Oct 15 01:31:05 PM PDT 23 55018214 ps
T565 /workspace/coverage/default/48.edn_disable_auto_req_mode.375573186 Oct 15 01:32:30 PM PDT 23 Oct 15 01:32:31 PM PDT 23 30471647 ps
T566 /workspace/coverage/default/45.edn_smoke.3741135591 Oct 15 01:33:52 PM PDT 23 Oct 15 01:33:54 PM PDT 23 39940649 ps
T567 /workspace/coverage/default/21.edn_smoke.2300885063 Oct 15 01:31:39 PM PDT 23 Oct 15 01:31:41 PM PDT 23 18548252 ps
T568 /workspace/coverage/default/46.edn_disable.3594370263 Oct 15 01:34:14 PM PDT 23 Oct 15 01:34:15 PM PDT 23 14665769 ps
T569 /workspace/coverage/default/13.edn_stress_all.2450427695 Oct 15 01:31:16 PM PDT 23 Oct 15 01:31:19 PM PDT 23 253567390 ps
T570 /workspace/coverage/default/49.edn_stress_all.3952495193 Oct 15 01:32:34 PM PDT 23 Oct 15 01:32:37 PM PDT 23 58161349 ps
T571 /workspace/coverage/default/46.edn_stress_all.2672908721 Oct 15 01:33:46 PM PDT 23 Oct 15 01:33:49 PM PDT 23 183562760 ps
T155 /workspace/coverage/default/18.edn_err.4248077027 Oct 15 01:31:37 PM PDT 23 Oct 15 01:31:39 PM PDT 23 24713494 ps
T572 /workspace/coverage/default/35.edn_smoke.3164775550 Oct 15 01:31:46 PM PDT 23 Oct 15 01:31:47 PM PDT 23 21936491 ps
T188 /workspace/coverage/default/42.edn_disable.2705184948 Oct 15 01:32:33 PM PDT 23 Oct 15 01:32:35 PM PDT 23 11821803 ps
T301 /workspace/coverage/default/12.edn_alert.128442758 Oct 15 01:31:04 PM PDT 23 Oct 15 01:31:05 PM PDT 23 62508157 ps
T573 /workspace/coverage/default/49.edn_smoke.3433944769 Oct 15 01:33:03 PM PDT 23 Oct 15 01:33:05 PM PDT 23 40725089 ps
T574 /workspace/coverage/default/8.edn_stress_all_with_rand_reset.4222337868 Oct 15 01:30:59 PM PDT 23 Oct 15 01:39:07 PM PDT 23 19696366438 ps
T575 /workspace/coverage/default/36.edn_disable_auto_req_mode.1113338342 Oct 15 01:32:37 PM PDT 23 Oct 15 01:32:39 PM PDT 23 29827715 ps
T576 /workspace/coverage/default/20.edn_stress_all.1211052737 Oct 15 01:31:38 PM PDT 23 Oct 15 01:31:41 PM PDT 23 43422357 ps
T278 /workspace/coverage/default/31.edn_genbits.1901106164 Oct 15 01:31:43 PM PDT 23 Oct 15 01:31:45 PM PDT 23 73028632 ps
T156 /workspace/coverage/default/41.edn_err.1569823156 Oct 15 01:33:05 PM PDT 23 Oct 15 01:33:06 PM PDT 23 26967448 ps
T577 /workspace/coverage/default/42.edn_intr.3588729700 Oct 15 01:32:34 PM PDT 23 Oct 15 01:32:35 PM PDT 23 22227381 ps
T160 /workspace/coverage/default/35.edn_err.1052026015 Oct 15 01:32:13 PM PDT 23 Oct 15 01:32:14 PM PDT 23 84011144 ps
T235 /workspace/coverage/default/40.edn_err.523644844 Oct 15 01:32:59 PM PDT 23 Oct 15 01:33:02 PM PDT 23 51487248 ps
T578 /workspace/coverage/default/38.edn_stress_all_with_rand_reset.2012756106 Oct 15 01:33:00 PM PDT 23 Oct 15 02:02:32 PM PDT 23 407684519046 ps
T579 /workspace/coverage/default/43.edn_stress_all_with_rand_reset.298284210 Oct 15 01:33:12 PM PDT 23 Oct 15 01:56:08 PM PDT 23 114735660364 ps
T580 /workspace/coverage/default/40.edn_alert_test.366856089 Oct 15 01:32:16 PM PDT 23 Oct 15 01:32:17 PM PDT 23 44918422 ps
T581 /workspace/coverage/default/39.edn_alert_test.1883608266 Oct 15 01:34:03 PM PDT 23 Oct 15 01:34:04 PM PDT 23 76039690 ps
T582 /workspace/coverage/default/8.edn_intr.1487899602 Oct 15 01:31:32 PM PDT 23 Oct 15 01:31:35 PM PDT 23 30127685 ps
T275 /workspace/coverage/default/34.edn_stress_all.3295443528 Oct 15 01:31:43 PM PDT 23 Oct 15 01:31:47 PM PDT 23 124256784 ps
T298 /workspace/coverage/default/19.edn_alert.750178500 Oct 15 01:31:37 PM PDT 23 Oct 15 01:31:39 PM PDT 23 65945507 ps
T583 /workspace/coverage/default/42.edn_stress_all_with_rand_reset.597595741 Oct 15 01:32:32 PM PDT 23 Oct 15 01:51:33 PM PDT 23 196949125463 ps
T295 /workspace/coverage/default/4.edn_regwen.4110495746 Oct 15 01:31:37 PM PDT 23 Oct 15 01:31:39 PM PDT 23 66925141 ps
T584 /workspace/coverage/default/0.edn_alert.4121605342 Oct 15 01:30:59 PM PDT 23 Oct 15 01:31:01 PM PDT 23 19530906 ps
T585 /workspace/coverage/default/34.edn_alert_test.2166646675 Oct 15 01:32:30 PM PDT 23 Oct 15 01:32:32 PM PDT 23 65705238 ps
T304 /workspace/coverage/default/20.edn_alert.260624624 Oct 15 01:31:34 PM PDT 23 Oct 15 01:31:36 PM PDT 23 53018688 ps
T586 /workspace/coverage/default/26.edn_disable.3760200124 Oct 15 01:32:09 PM PDT 23 Oct 15 01:32:10 PM PDT 23 20209330 ps
T587 /workspace/coverage/default/93.edn_err.1915759810 Oct 15 01:32:31 PM PDT 23 Oct 15 01:32:33 PM PDT 23 18541734 ps
T303 /workspace/coverage/default/2.edn_regwen.2193198777 Oct 15 01:31:17 PM PDT 23 Oct 15 01:31:19 PM PDT 23 39486567 ps
T588 /workspace/coverage/default/16.edn_alert.3114657371 Oct 15 01:31:20 PM PDT 23 Oct 15 01:31:22 PM PDT 23 18010086 ps
T589 /workspace/coverage/default/80.edn_err.2715815077 Oct 15 01:33:10 PM PDT 23 Oct 15 01:33:11 PM PDT 23 210411022 ps
T590 /workspace/coverage/default/22.edn_alert.3411569994 Oct 15 01:31:51 PM PDT 23 Oct 15 01:31:53 PM PDT 23 17003171 ps
T591 /workspace/coverage/default/10.edn_smoke.1743347619 Oct 15 01:31:17 PM PDT 23 Oct 15 01:31:19 PM PDT 23 12137606 ps
T592 /workspace/coverage/default/2.edn_stress_all.2071917320 Oct 15 01:31:32 PM PDT 23 Oct 15 01:31:37 PM PDT 23 408287667 ps
T284 /workspace/coverage/default/12.edn_disable_auto_req_mode.3932291860 Oct 15 01:31:11 PM PDT 23 Oct 15 01:31:13 PM PDT 23 23606909 ps
T250 /workspace/coverage/default/1.edn_err.1952129558 Oct 15 01:31:36 PM PDT 23 Oct 15 01:31:38 PM PDT 23 25413965 ps
T593 /workspace/coverage/default/27.edn_disable_auto_req_mode.1361735363 Oct 15 01:32:11 PM PDT 23 Oct 15 01:32:12 PM PDT 23 26582892 ps
T183 /workspace/coverage/default/69.edn_err.563508045 Oct 15 01:33:52 PM PDT 23 Oct 15 01:33:53 PM PDT 23 22807198 ps
T594 /workspace/coverage/default/32.edn_stress_all_with_rand_reset.1070488662 Oct 15 01:31:46 PM PDT 23 Oct 15 01:44:59 PM PDT 23 32903964258 ps
T279 /workspace/coverage/default/8.edn_genbits.3669882141 Oct 15 01:31:11 PM PDT 23 Oct 15 01:31:13 PM PDT 23 67457024 ps
T595 /workspace/coverage/default/43.edn_err.2387770339 Oct 15 01:32:59 PM PDT 23 Oct 15 01:33:02 PM PDT 23 23710674 ps
T596 /workspace/coverage/default/27.edn_err.1474908605 Oct 15 01:32:10 PM PDT 23 Oct 15 01:32:12 PM PDT 23 32163153 ps
T597 /workspace/coverage/default/1.edn_regwen.3554351960 Oct 15 01:31:33 PM PDT 23 Oct 15 01:31:36 PM PDT 23 14800815 ps
T598 /workspace/coverage/default/1.edn_smoke.3736380060 Oct 15 01:31:17 PM PDT 23 Oct 15 01:31:18 PM PDT 23 67458371 ps
T599 /workspace/coverage/default/10.edn_stress_all.885514555 Oct 15 01:31:08 PM PDT 23 Oct 15 01:31:11 PM PDT 23 456762326 ps
T273 /workspace/coverage/default/43.edn_genbits.2291279280 Oct 15 01:32:33 PM PDT 23 Oct 15 01:32:34 PM PDT 23 41225308 ps
T600 /workspace/coverage/default/28.edn_intr.4128290703 Oct 15 01:32:29 PM PDT 23 Oct 15 01:32:30 PM PDT 23 27976194 ps
T289 /workspace/coverage/default/20.edn_genbits.970305317 Oct 15 01:31:40 PM PDT 23 Oct 15 01:31:42 PM PDT 23 85673047 ps
T601 /workspace/coverage/default/15.edn_alert_test.1083003680 Oct 15 01:31:17 PM PDT 23 Oct 15 01:31:18 PM PDT 23 55842947 ps
T602 /workspace/coverage/default/36.edn_err.1219457251 Oct 15 01:32:17 PM PDT 23 Oct 15 01:32:19 PM PDT 23 20253301 ps
T603 /workspace/coverage/default/41.edn_stress_all.844507841 Oct 15 01:32:13 PM PDT 23 Oct 15 01:32:15 PM PDT 23 230239542 ps
T604 /workspace/coverage/default/91.edn_err.4236956732 Oct 15 01:32:36 PM PDT 23 Oct 15 01:32:38 PM PDT 23 31499900 ps
T251 /workspace/coverage/default/17.edn_disable.1142012364 Oct 15 01:31:15 PM PDT 23 Oct 15 01:31:16 PM PDT 23 30382395 ps
T605 /workspace/coverage/default/17.edn_alert.909272450 Oct 15 01:31:30 PM PDT 23 Oct 15 01:31:31 PM PDT 23 49075176 ps
T134 /workspace/coverage/default/10.edn_intr.3444045971 Oct 15 01:30:59 PM PDT 23 Oct 15 01:31:01 PM PDT 23 52369859 ps
T606 /workspace/coverage/default/4.edn_alert.226081478 Oct 15 01:31:35 PM PDT 23 Oct 15 01:31:36 PM PDT 23 27596688 ps
T607 /workspace/coverage/default/27.edn_genbits.79697844 Oct 15 01:31:50 PM PDT 23 Oct 15 01:31:51 PM PDT 23 86723560 ps
T608 /workspace/coverage/default/23.edn_intr.1292885814 Oct 15 01:31:42 PM PDT 23 Oct 15 01:31:44 PM PDT 23 24051148 ps
T609 /workspace/coverage/default/30.edn_stress_all_with_rand_reset.3015226948 Oct 15 01:31:43 PM PDT 23 Oct 15 02:01:03 PM PDT 23 152634319726 ps
T296 /workspace/coverage/default/8.edn_regwen.597292449 Oct 15 01:30:58 PM PDT 23 Oct 15 01:31:00 PM PDT 23 15945095 ps
T135 /workspace/coverage/default/2.edn_intr.4094619809 Oct 15 01:31:02 PM PDT 23 Oct 15 01:31:03 PM PDT 23 36969855 ps
T610 /workspace/coverage/default/11.edn_smoke.1313132379 Oct 15 01:31:12 PM PDT 23 Oct 15 01:31:13 PM PDT 23 11778829 ps
T611 /workspace/coverage/default/7.edn_regwen.2027980040 Oct 15 01:30:59 PM PDT 23 Oct 15 01:31:01 PM PDT 23 14231825 ps
T612 /workspace/coverage/default/39.edn_stress_all.2108226308 Oct 15 01:33:12 PM PDT 23 Oct 15 01:33:18 PM PDT 23 206302326 ps
T265 /workspace/coverage/default/18.edn_genbits.3268559866 Oct 15 01:31:37 PM PDT 23 Oct 15 01:31:39 PM PDT 23 60137814 ps
T613 /workspace/coverage/default/0.edn_intr.1785067458 Oct 15 01:31:29 PM PDT 23 Oct 15 01:31:30 PM PDT 23 25774147 ps
T614 /workspace/coverage/default/34.edn_genbits.2023004529 Oct 15 01:32:17 PM PDT 23 Oct 15 01:32:18 PM PDT 23 158872929 ps
T615 /workspace/coverage/default/68.edn_err.1266701010 Oct 15 01:33:06 PM PDT 23 Oct 15 01:33:08 PM PDT 23 43359677 ps
T239 /workspace/coverage/default/33.edn_disable.398261029 Oct 15 01:32:28 PM PDT 23 Oct 15 01:32:30 PM PDT 23 19296560 ps
T616 /workspace/coverage/default/2.edn_alert.3319782383 Oct 15 01:31:23 PM PDT 23 Oct 15 01:31:25 PM PDT 23 89058316 ps
T617 /workspace/coverage/default/23.edn_alert.1659576996 Oct 15 01:31:41 PM PDT 23 Oct 15 01:31:43 PM PDT 23 21883663 ps
T12 /workspace/coverage/default/36.edn_genbits.3903202772 Oct 15 01:31:47 PM PDT 23 Oct 15 01:31:49 PM PDT 23 31709933 ps
T618 /workspace/coverage/default/36.edn_alert.3480173034 Oct 15 01:32:10 PM PDT 23 Oct 15 01:32:11 PM PDT 23 26358709 ps
T619 /workspace/coverage/default/0.edn_smoke.575108143 Oct 15 01:31:11 PM PDT 23 Oct 15 01:31:13 PM PDT 23 12297774 ps
T620 /workspace/coverage/default/1.edn_stress_all.2822329830 Oct 15 01:31:02 PM PDT 23 Oct 15 01:31:06 PM PDT 23 624674389 ps
T621 /workspace/coverage/default/32.edn_disable_auto_req_mode.813434286 Oct 15 01:31:46 PM PDT 23 Oct 15 01:31:47 PM PDT 23 46694016 ps
T622 /workspace/coverage/default/27.edn_disable.2866914393 Oct 15 01:32:28 PM PDT 23 Oct 15 01:32:29 PM PDT 23 73594153 ps
T623 /workspace/coverage/default/6.edn_disable.3724424811 Oct 15 01:31:01 PM PDT 23 Oct 15 01:31:03 PM PDT 23 14329044 ps
T624 /workspace/coverage/default/45.edn_disable.695294542 Oct 15 01:34:15 PM PDT 23 Oct 15 01:34:16 PM PDT 23 12234300 ps
T625 /workspace/coverage/default/10.edn_stress_all_with_rand_reset.892620036 Oct 15 01:31:03 PM PDT 23 Oct 15 01:49:13 PM PDT 23 207012497300 ps
T626 /workspace/coverage/default/45.edn_alert_test.2580241876 Oct 15 01:33:13 PM PDT 23 Oct 15 01:33:15 PM PDT 23 106959891 ps
T233 /workspace/coverage/default/21.edn_disable.2120376205 Oct 15 01:31:48 PM PDT 23 Oct 15 01:31:49 PM PDT 23 15391361 ps
T627 /workspace/coverage/default/24.edn_stress_all.2963612619 Oct 15 01:31:52 PM PDT 23 Oct 15 01:31:54 PM PDT 23 200533331 ps
T628 /workspace/coverage/default/24.edn_disable_auto_req_mode.3340104905 Oct 15 01:31:51 PM PDT 23 Oct 15 01:31:52 PM PDT 23 27269877 ps
T274 /workspace/coverage/default/42.edn_genbits.791288888 Oct 15 01:33:06 PM PDT 23 Oct 15 01:33:08 PM PDT 23 45104003 ps
T629 /workspace/coverage/default/44.edn_stress_all_with_rand_reset.880662540 Oct 15 01:33:06 PM PDT 23 Oct 15 01:45:29 PM PDT 23 95060792446 ps
T630 /workspace/coverage/default/33.edn_intr.1945067757 Oct 15 01:32:10 PM PDT 23 Oct 15 01:32:11 PM PDT 23 31159755 ps
T631 /workspace/coverage/default/4.edn_alert_test.2916026870 Oct 15 01:31:02 PM PDT 23 Oct 15 01:31:04 PM PDT 23 17067037 ps
T170 /workspace/coverage/default/6.edn_err.38150350 Oct 15 01:31:04 PM PDT 23 Oct 15 01:31:06 PM PDT 23 32128793 ps
T632 /workspace/coverage/default/59.edn_err.3553463558 Oct 15 01:32:15 PM PDT 23 Oct 15 01:32:16 PM PDT 23 42836362 ps
T633 /workspace/coverage/default/23.edn_stress_all.1601381461 Oct 15 01:31:49 PM PDT 23 Oct 15 01:31:52 PM PDT 23 555675307 ps
T634 /workspace/coverage/default/48.edn_err.4202894870 Oct 15 01:32:14 PM PDT 23 Oct 15 01:32:15 PM PDT 23 19910774 ps
T635 /workspace/coverage/default/24.edn_genbits.1946497230 Oct 15 01:31:40 PM PDT 23 Oct 15 01:31:42 PM PDT 23 18022200 ps
T636 /workspace/coverage/default/24.edn_intr.1371853699 Oct 15 01:31:45 PM PDT 23 Oct 15 01:31:46 PM PDT 23 25699002 ps
T637 /workspace/coverage/default/6.edn_stress_all.1160245727 Oct 15 01:31:07 PM PDT 23 Oct 15 01:31:08 PM PDT 23 53605056 ps
T277 /workspace/coverage/default/18.edn_stress_all_with_rand_reset.3328075512 Oct 15 01:31:35 PM PDT 23 Oct 15 01:39:09 PM PDT 23 21678791057 ps
T638 /workspace/coverage/default/1.edn_alert_test.1763792848 Oct 15 01:31:40 PM PDT 23 Oct 15 01:31:42 PM PDT 23 28103248 ps
T639 /workspace/coverage/default/34.edn_alert.1585246924 Oct 15 01:31:58 PM PDT 23 Oct 15 01:31:59 PM PDT 23 129709386 ps
T236 /workspace/coverage/default/11.edn_err.3365365653 Oct 15 01:31:02 PM PDT 23 Oct 15 01:31:04 PM PDT 23 52009618 ps
T640 /workspace/coverage/default/37.edn_stress_all.2968456674 Oct 15 01:32:13 PM PDT 23 Oct 15 01:32:16 PM PDT 23 289794160 ps
T641 /workspace/coverage/default/47.edn_stress_all.1216809394 Oct 15 01:34:03 PM PDT 23 Oct 15 01:34:05 PM PDT 23 32490703 ps
T642 /workspace/coverage/default/41.edn_smoke.1768296830 Oct 15 01:32:13 PM PDT 23 Oct 15 01:32:14 PM PDT 23 37471129 ps
T643 /workspace/coverage/default/89.edn_err.4243058194 Oct 15 01:32:34 PM PDT 23 Oct 15 01:32:35 PM PDT 23 26412050 ps
T644 /workspace/coverage/default/33.edn_smoke.771418494 Oct 15 01:32:16 PM PDT 23 Oct 15 01:32:17 PM PDT 23 18418426 ps
T645 /workspace/coverage/default/54.edn_err.1562532055 Oct 15 01:32:33 PM PDT 23 Oct 15 01:32:34 PM PDT 23 28075033 ps
T127 /workspace/coverage/default/15.edn_intr.3668791570 Oct 15 01:31:20 PM PDT 23 Oct 15 01:31:21 PM PDT 23 33091735 ps
T646 /workspace/coverage/default/35.edn_disable.2247861598 Oct 15 01:32:15 PM PDT 23 Oct 15 01:32:16 PM PDT 23 21119090 ps
T647 /workspace/coverage/default/33.edn_alert_test.207634355 Oct 15 01:32:27 PM PDT 23 Oct 15 01:32:28 PM PDT 23 18536406 ps
T648 /workspace/coverage/default/51.edn_err.2686574813 Oct 15 01:33:07 PM PDT 23 Oct 15 01:33:09 PM PDT 23 29508590 ps
T649 /workspace/coverage/default/33.edn_disable_auto_req_mode.2583537390 Oct 15 01:31:44 PM PDT 23 Oct 15 01:31:45 PM PDT 23 57963200 ps
T650 /workspace/coverage/default/47.edn_disable_auto_req_mode.4117617988 Oct 15 01:32:11 PM PDT 23 Oct 15 01:32:12 PM PDT 23 27684572 ps
T651 /workspace/coverage/default/33.edn_genbits.4049535769 Oct 15 01:32:29 PM PDT 23 Oct 15 01:32:30 PM PDT 23 131356237 ps
T652 /workspace/coverage/default/49.edn_stress_all_with_rand_reset.591839216 Oct 15 01:32:13 PM PDT 23 Oct 15 01:50:29 PM PDT 23 106739106216 ps
T653 /workspace/coverage/default/12.edn_stress_all.2654125224 Oct 15 01:31:16 PM PDT 23 Oct 15 01:31:17 PM PDT 23 140635746 ps
T654 /workspace/coverage/default/37.edn_smoke.3446578748 Oct 15 01:32:15 PM PDT 23 Oct 15 01:32:16 PM PDT 23 14055764 ps
T655 /workspace/coverage/default/47.edn_smoke.267443822 Oct 15 01:34:07 PM PDT 23 Oct 15 01:34:08 PM PDT 23 11610008 ps
T656 /workspace/coverage/default/11.edn_disable_auto_req_mode.2347800615 Oct 15 01:31:03 PM PDT 23 Oct 15 01:31:04 PM PDT 23 61013317 ps
T657 /workspace/coverage/default/19.edn_smoke.822245474 Oct 15 01:31:38 PM PDT 23 Oct 15 01:31:39 PM PDT 23 39763596 ps
T658 /workspace/coverage/default/31.edn_alert.3839726369 Oct 15 01:31:47 PM PDT 23 Oct 15 01:31:49 PM PDT 23 70242754 ps
T659 /workspace/coverage/default/20.edn_disable_auto_req_mode.1084568498 Oct 15 01:31:44 PM PDT 23 Oct 15 01:31:46 PM PDT 23 143143886 ps
T660 /workspace/coverage/default/24.edn_stress_all_with_rand_reset.3300699829 Oct 15 01:31:49 PM PDT 23 Oct 15 01:42:02 PM PDT 23 48391355238 ps
T661 /workspace/coverage/default/2.edn_smoke.3350292097 Oct 15 01:31:15 PM PDT 23 Oct 15 01:31:17 PM PDT 23 21352648 ps
T662 /workspace/coverage/default/43.edn_intr.2420499911 Oct 15 01:33:00 PM PDT 23 Oct 15 01:33:03 PM PDT 23 20634976 ps
T663 /workspace/coverage/default/11.edn_intr.653549391 Oct 15 01:31:23 PM PDT 23 Oct 15 01:31:25 PM PDT 23 24345262 ps
T664 /workspace/coverage/default/19.edn_alert_test.59602347 Oct 15 01:31:37 PM PDT 23 Oct 15 01:31:39 PM PDT 23 28066379 ps
T665 /workspace/coverage/default/28.edn_alert.797242273 Oct 15 01:31:47 PM PDT 23 Oct 15 01:31:49 PM PDT 23 35493371 ps
T666 /workspace/coverage/default/34.edn_disable_auto_req_mode.3925892879 Oct 15 01:32:16 PM PDT 23 Oct 15 01:32:18 PM PDT 23 21848329 ps
T667 /workspace/coverage/default/27.edn_alert_test.1497865262 Oct 15 01:31:42 PM PDT 23 Oct 15 01:31:44 PM PDT 23 54957780 ps
T668 /workspace/coverage/default/45.edn_intr.2115611903 Oct 15 01:33:16 PM PDT 23 Oct 15 01:33:18 PM PDT 23 26619593 ps
T669 /workspace/coverage/default/37.edn_alert.3544458670 Oct 15 01:33:05 PM PDT 23 Oct 15 01:33:07 PM PDT 23 74857593 ps
T242 /workspace/coverage/default/3.edn_err.722477025 Oct 15 01:31:28 PM PDT 23 Oct 15 01:31:30 PM PDT 23 44091188 ps
T670 /workspace/coverage/default/45.edn_disable_auto_req_mode.1268889691 Oct 15 01:34:12 PM PDT 23 Oct 15 01:34:14 PM PDT 23 58136648 ps
T671 /workspace/coverage/default/7.edn_disable.772434328 Oct 15 01:31:06 PM PDT 23 Oct 15 01:31:07 PM PDT 23 23630415 ps
T672 /workspace/coverage/default/35.edn_genbits.2291800842 Oct 15 01:32:11 PM PDT 23 Oct 15 01:32:12 PM PDT 23 34782173 ps
T673 /workspace/coverage/default/30.edn_alert.2759593929 Oct 15 01:31:39 PM PDT 23 Oct 15 01:31:42 PM PDT 23 32095292 ps
T674 /workspace/coverage/default/2.edn_disable_auto_req_mode.613808183 Oct 15 01:31:06 PM PDT 23 Oct 15 01:31:08 PM PDT 23 96727296 ps
T675 /workspace/coverage/default/5.edn_smoke.372382497 Oct 15 01:31:36 PM PDT 23 Oct 15 01:31:38 PM PDT 23 23941703 ps
T676 /workspace/coverage/default/32.edn_intr.2388947315 Oct 15 01:31:45 PM PDT 23 Oct 15 01:31:46 PM PDT 23 32571785 ps
T677 /workspace/coverage/default/38.edn_alert.2768125103 Oct 15 01:33:45 PM PDT 23 Oct 15 01:33:47 PM PDT 23 17702754 ps
T678 /workspace/coverage/default/29.edn_err.3682590435 Oct 15 01:31:39 PM PDT 23 Oct 15 01:31:42 PM PDT 23 19281226 ps
T679 /workspace/coverage/default/47.edn_disable.2939521021 Oct 15 01:32:38 PM PDT 23 Oct 15 01:32:39 PM PDT 23 19556270 ps
T680 /workspace/coverage/default/25.edn_smoke.1521649396 Oct 15 01:31:44 PM PDT 23 Oct 15 01:31:45 PM PDT 23 13053655 ps
T681 /workspace/coverage/default/16.edn_alert_test.331451778 Oct 15 01:31:30 PM PDT 23 Oct 15 01:31:31 PM PDT 23 28038080 ps
T682 /workspace/coverage/default/11.edn_genbits.459404008 Oct 15 01:31:01 PM PDT 23 Oct 15 01:31:03 PM PDT 23 70547600 ps
T683 /workspace/coverage/default/48.edn_genbits.1747554079 Oct 15 01:32:30 PM PDT 23 Oct 15 01:32:32 PM PDT 23 28106554 ps
T684 /workspace/coverage/default/6.edn_smoke.2312470270 Oct 15 01:31:20 PM PDT 23 Oct 15 01:31:21 PM PDT 23 12984566 ps
T685 /workspace/coverage/default/2.edn_alert_test.3522523214 Oct 15 01:31:04 PM PDT 23 Oct 15 01:31:05 PM PDT 23 26628272 ps
T686 /workspace/coverage/default/43.edn_alert_test.1055198034 Oct 15 01:33:36 PM PDT 23 Oct 15 01:33:37 PM PDT 23 39403996 ps
T288 /workspace/coverage/default/25.edn_genbits.3280364148 Oct 15 01:31:49 PM PDT 23 Oct 15 01:31:50 PM PDT 23 16129919 ps
T157 /workspace/coverage/default/41.edn_disable_auto_req_mode.2520649316 Oct 15 01:32:33 PM PDT 23 Oct 15 01:32:35 PM PDT 23 20730739 ps
T245 /workspace/coverage/default/25.edn_err.1888247238 Oct 15 01:31:42 PM PDT 23 Oct 15 01:31:44 PM PDT 23 19932766 ps
T687 /workspace/coverage/default/13.edn_smoke.1271916614 Oct 15 01:30:59 PM PDT 23 Oct 15 01:31:01 PM PDT 23 15129752 ps
T688 /workspace/coverage/default/48.edn_alert.2529273367 Oct 15 01:32:16 PM PDT 23 Oct 15 01:32:17 PM PDT 23 36521828 ps
T689 /workspace/coverage/default/44.edn_stress_all.2241527031 Oct 15 01:33:10 PM PDT 23 Oct 15 01:33:14 PM PDT 23 421816851 ps
T234 /workspace/coverage/default/57.edn_err.3620526174 Oct 15 01:32:34 PM PDT 23 Oct 15 01:32:35 PM PDT 23 36473603 ps
T690 /workspace/coverage/default/44.edn_disable_auto_req_mode.3358143242 Oct 15 01:33:49 PM PDT 23 Oct 15 01:33:50 PM PDT 23 21702584 ps
T276 /workspace/coverage/default/32.edn_genbits.1186596055 Oct 15 01:31:42 PM PDT 23 Oct 15 01:31:44 PM PDT 23 43687915 ps
T691 /workspace/coverage/default/3.edn_alert_test.77775140 Oct 15 01:31:31 PM PDT 23 Oct 15 01:31:33 PM PDT 23 16433895 ps
T165 /workspace/coverage/default/77.edn_err.3969650294 Oct 15 01:32:57 PM PDT 23 Oct 15 01:32:58 PM PDT 23 25108264 ps
T266 /workspace/coverage/default/19.edn_genbits.3696639155 Oct 15 01:31:21 PM PDT 23 Oct 15 01:31:22 PM PDT 23 16255974 ps
T692 /workspace/coverage/default/8.edn_disable_auto_req_mode.3381484023 Oct 15 01:31:30 PM PDT 23 Oct 15 01:31:31 PM PDT 23 66828705 ps
T693 /workspace/coverage/default/3.edn_intr.1662458154 Oct 15 01:31:15 PM PDT 23 Oct 15 01:31:17 PM PDT 23 35529539 ps
T694 /workspace/coverage/default/10.edn_err.1917667251 Oct 15 01:31:14 PM PDT 23 Oct 15 01:31:15 PM PDT 23 78879889 ps
T695 /workspace/coverage/default/35.edn_intr.3168239132 Oct 15 01:32:28 PM PDT 23 Oct 15 01:32:29 PM PDT 23 30181483 ps
T696 /workspace/coverage/default/96.edn_err.2735827180 Oct 15 01:33:08 PM PDT 23 Oct 15 01:33:10 PM PDT 23 26083709 ps
T697 /workspace/coverage/default/15.edn_err.2870056168 Oct 15 01:31:19 PM PDT 23 Oct 15 01:31:21 PM PDT 23 86527143 ps
T698 /workspace/coverage/default/46.edn_alert_test.692342623 Oct 15 01:33:07 PM PDT 23 Oct 15 01:33:09 PM PDT 23 35298954 ps
T699 /workspace/coverage/default/36.edn_intr.358337134 Oct 15 01:32:30 PM PDT 23 Oct 15 01:32:32 PM PDT 23 18685358 ps
T700 /workspace/coverage/default/7.edn_alert.3768766593 Oct 15 01:31:02 PM PDT 23 Oct 15 01:31:04 PM PDT 23 65638685 ps
T701 /workspace/coverage/default/24.edn_disable.1382933714 Oct 15 01:32:28 PM PDT 23 Oct 15 01:32:30 PM PDT 23 34901733 ps
T702 /workspace/coverage/default/19.edn_stress_all_with_rand_reset.3806610902 Oct 15 01:31:36 PM PDT 23 Oct 15 01:37:28 PM PDT 23 62799144951 ps
T147 /workspace/coverage/default/5.edn_disable.1034797171 Oct 15 01:31:21 PM PDT 23 Oct 15 01:31:22 PM PDT 23 11501830 ps
T703 /workspace/coverage/default/42.edn_disable_auto_req_mode.3442053034 Oct 15 01:32:13 PM PDT 23 Oct 15 01:32:15 PM PDT 23 146085387 ps
T704 /workspace/coverage/default/21.edn_intr.237898162 Oct 15 01:31:42 PM PDT 23 Oct 15 01:31:43 PM PDT 23 27942844 ps
T705 /workspace/coverage/default/17.edn_smoke.460659610 Oct 15 01:31:29 PM PDT 23 Oct 15 01:31:31 PM PDT 23 11921945 ps
T706 /workspace/coverage/default/16.edn_err.537854086 Oct 15 01:31:18 PM PDT 23 Oct 15 01:31:19 PM PDT 23 19003488 ps
T707 /workspace/coverage/default/28.edn_stress_all.1660272535 Oct 15 01:31:41 PM PDT 23 Oct 15 01:31:45 PM PDT 23 291561067 ps
T708 /workspace/coverage/default/0.edn_genbits.3794863017 Oct 15 01:31:14 PM PDT 23 Oct 15 01:31:15 PM PDT 23 41049079 ps
T709 /workspace/coverage/default/29.edn_genbits.219354739 Oct 15 01:31:48 PM PDT 23 Oct 15 01:31:50 PM PDT 23 58826659 ps
T710 /workspace/coverage/default/87.edn_err.3457799858 Oct 15 01:32:31 PM PDT 23 Oct 15 01:32:33 PM PDT 23 24475378 ps
T711 /workspace/coverage/default/22.edn_genbits.684919381 Oct 15 01:32:15 PM PDT 23 Oct 15 01:32:17 PM PDT 23 21800993 ps
T712 /workspace/coverage/default/43.edn_alert.2511153420 Oct 15 01:33:08 PM PDT 23 Oct 15 01:33:09 PM PDT 23 18471250 ps
T713 /workspace/coverage/default/49.edn_alert_test.404182587 Oct 15 01:32:10 PM PDT 23 Oct 15 01:32:11 PM PDT 23 22506907 ps
T714 /workspace/coverage/default/9.edn_genbits.635936571 Oct 15 01:31:30 PM PDT 23 Oct 15 01:31:32 PM PDT 23 32901991 ps
T715 /workspace/coverage/default/29.edn_intr.2994160845 Oct 15 01:31:50 PM PDT 23 Oct 15 01:31:52 PM PDT 23 22305765 ps
T716 /workspace/coverage/default/88.edn_err.982477193 Oct 15 01:32:13 PM PDT 23 Oct 15 01:32:14 PM PDT 23 18793304 ps
T717 /workspace/coverage/default/36.edn_alert_test.846818245 Oct 15 01:32:37 PM PDT 23 Oct 15 01:32:38 PM PDT 23 13311992 ps
T718 /workspace/coverage/default/46.edn_alert.43586473 Oct 15 01:33:48 PM PDT 23 Oct 15 01:33:50 PM PDT 23 16916793 ps
T719 /workspace/coverage/default/18.edn_stress_all.1964503066 Oct 15 01:31:35 PM PDT 23 Oct 15 01:31:38 PM PDT 23 61277247 ps
T720 /workspace/coverage/default/19.edn_intr.2990922669 Oct 15 01:31:40 PM PDT 23 Oct 15 01:31:42 PM PDT 23 22851493 ps
T721 /workspace/coverage/default/19.edn_disable.242576035 Oct 15 01:31:36 PM PDT 23 Oct 15 01:31:38 PM PDT 23 22801621 ps
T722 /workspace/coverage/default/3.edn_smoke.848698833 Oct 15 01:30:53 PM PDT 23 Oct 15 01:30:54 PM PDT 23 15568802 ps
T723 /workspace/coverage/default/15.edn_stress_all_with_rand_reset.4154717837 Oct 15 01:31:00 PM PDT 23 Oct 15 02:15:25 PM PDT 23 112715374793 ps
T724 /workspace/coverage/default/42.edn_err.1334487154 Oct 15 01:33:06 PM PDT 23 Oct 15 01:33:08 PM PDT 23 38897128 ps
T725 /workspace/coverage/default/22.edn_alert_test.2852252988 Oct 15 01:31:52 PM PDT 23 Oct 15 01:31:54 PM PDT 23 19218454 ps
T726 /workspace/coverage/default/60.edn_err.4248751773 Oct 15 01:32:15 PM PDT 23 Oct 15 01:32:16 PM PDT 23 24521072 ps
T727 /workspace/coverage/default/45.edn_stress_all.4236783501 Oct 15 01:33:47 PM PDT 23 Oct 15 01:33:51 PM PDT 23 498165048 ps
T728 /workspace/coverage/default/40.edn_stress_all_with_rand_reset.2661772571 Oct 15 01:31:44 PM PDT 23 Oct 15 01:41:18 PM PDT 23 98854911468 ps
T172 /workspace/coverage/default/4.edn_disable.3661792915 Oct 15 01:31:40 PM PDT 23 Oct 15 01:31:42 PM PDT 23 11700069 ps

Test location /workspace/coverage/default/4.edn_stress_all.2966164074
Short name T20
Test name
Test status
Simulation time 129179389 ps
CPU time 2.93 seconds
Started Oct 15 01:31:36 PM PDT 23
Finished Oct 15 01:31:40 PM PDT 23
Peak memory 206480 kb
Host smart-4335306c-05dd-4b0a-9551-bdabe5736610
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966164074 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.2966164074
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.1338143058
Short name T8
Test name
Test status
Simulation time 24604952 ps
CPU time 1.01 seconds
Started Oct 15 01:31:38 PM PDT 23
Finished Oct 15 01:31:39 PM PDT 23
Peak memory 215244 kb
Host smart-9ffea79c-f145-4a5f-af15-52d9287a91ed
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338143058 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.1338143058
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_genbits.1868556346
Short name T38
Test name
Test status
Simulation time 102162576 ps
CPU time 1.09 seconds
Started Oct 15 01:31:00 PM PDT 23
Finished Oct 15 01:31:02 PM PDT 23
Peak memory 205872 kb
Host smart-0cfaf285-b68a-4191-b993-878ef86fd84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868556346 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1868556346
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_sec_cm.2552967387
Short name T15
Test name
Test status
Simulation time 415231163 ps
CPU time 3.44 seconds
Started Oct 15 01:31:13 PM PDT 23
Finished Oct 15 01:31:17 PM PDT 23
Peak memory 234284 kb
Host smart-3162f5f9-af93-4706-a1a3-30e01fe14405
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552967387 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.2552967387
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/18.edn_disable.3583022917
Short name T34
Test name
Test status
Simulation time 16180075 ps
CPU time 0.81 seconds
Started Oct 15 01:31:40 PM PDT 23
Finished Oct 15 01:31:42 PM PDT 23
Peak memory 214896 kb
Host smart-65f4e764-b9a9-4230-9f3b-68a362cd9e87
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583022917 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.3583022917
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.4127191675
Short name T24
Test name
Test status
Simulation time 30788866755 ps
CPU time 602.41 seconds
Started Oct 15 01:31:44 PM PDT 23
Finished Oct 15 01:41:47 PM PDT 23
Peak memory 216864 kb
Host smart-56d2e340-881c-461b-8e63-a690cff04be3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127191675 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.4127191675
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.edn_alert.379839236
Short name T16
Test name
Test status
Simulation time 38348841 ps
CPU time 0.92 seconds
Started Oct 15 01:31:33 PM PDT 23
Finished Oct 15 01:31:36 PM PDT 23
Peak memory 206112 kb
Host smart-e4e3aca8-a12f-4b79-b7ed-4fc1859fa34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379839236 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.379839236
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/44.edn_err.664640157
Short name T14
Test name
Test status
Simulation time 20995016 ps
CPU time 1.12 seconds
Started Oct 15 01:33:45 PM PDT 23
Finished Oct 15 01:33:47 PM PDT 23
Peak memory 222888 kb
Host smart-4a3a9ee6-6eb2-4f2e-9c7e-9b8417065485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664640157 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.664640157
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.3476414986
Short name T136
Test name
Test status
Simulation time 71791822143 ps
CPU time 1521.48 seconds
Started Oct 15 01:31:44 PM PDT 23
Finished Oct 15 01:57:06 PM PDT 23
Peak memory 217780 kb
Host smart-2f60f722-7519-46b0-a78b-26e09540265d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476414986 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.3476414986
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.420771148
Short name T120
Test name
Test status
Simulation time 74989785 ps
CPU time 1.01 seconds
Started Oct 15 01:31:01 PM PDT 23
Finished Oct 15 01:31:03 PM PDT 23
Peak memory 215296 kb
Host smart-6d187eb9-112a-4988-9db3-02d743676905
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420771148 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_di
sable_auto_req_mode.420771148
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_intr.2093649584
Short name T27
Test name
Test status
Simulation time 53997743 ps
CPU time 0.79 seconds
Started Oct 15 01:33:00 PM PDT 23
Finished Oct 15 01:33:03 PM PDT 23
Peak memory 215252 kb
Host smart-99f60d52-08fc-4278-b7a5-e87b0fa48030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093649584 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2093649584
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.263275489
Short name T260
Test name
Test status
Simulation time 288161156 ps
CPU time 2.27 seconds
Started Oct 15 01:10:13 PM PDT 23
Finished Oct 15 01:10:15 PM PDT 23
Peak memory 206556 kb
Host smart-ec99a508-5b29-4468-8c92-39178c594d32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263275489 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.263275489
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.1305817140
Short name T119
Test name
Test status
Simulation time 19291088 ps
CPU time 0.92 seconds
Started Oct 15 01:31:49 PM PDT 23
Finished Oct 15 01:31:50 PM PDT 23
Peak memory 215276 kb
Host smart-62ea73b2-2d7b-4e99-b910-558603a68548
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305817140 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.1305817140
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_genbits.3580271007
Short name T10
Test name
Test status
Simulation time 35240885 ps
CPU time 1.09 seconds
Started Oct 15 01:31:37 PM PDT 23
Finished Oct 15 01:31:39 PM PDT 23
Peak memory 214904 kb
Host smart-559fc686-34b6-4418-8992-f8ae7ba92f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580271007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.3580271007
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_disable.2177802918
Short name T95
Test name
Test status
Simulation time 10539514 ps
CPU time 0.89 seconds
Started Oct 15 01:31:07 PM PDT 23
Finished Oct 15 01:31:09 PM PDT 23
Peak memory 215064 kb
Host smart-cf68c4d6-df4c-4d22-a90f-b13f6f64ccfe
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177802918 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.2177802918
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/8.edn_err.2909338773
Short name T7
Test name
Test status
Simulation time 29038685 ps
CPU time 1.12 seconds
Started Oct 15 01:31:29 PM PDT 23
Finished Oct 15 01:31:31 PM PDT 23
Peak memory 215424 kb
Host smart-5e0faae2-e4d5-4725-bd2a-d0873f9700b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909338773 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.2909338773
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/32.edn_disable.1743044820
Short name T122
Test name
Test status
Simulation time 23849698 ps
CPU time 0.88 seconds
Started Oct 15 01:31:41 PM PDT 23
Finished Oct 15 01:31:43 PM PDT 23
Peak memory 215056 kb
Host smart-61cce956-1b1e-4f7d-8a50-d82516aa3461
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743044820 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.1743044820
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/5.edn_regwen.1190425188
Short name T292
Test name
Test status
Simulation time 23283115 ps
CPU time 0.87 seconds
Started Oct 15 01:31:35 PM PDT 23
Finished Oct 15 01:31:37 PM PDT 23
Peak memory 205720 kb
Host smart-4c2a5108-d9c6-48ef-913c-6d8e3b5e5dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190425188 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.1190425188
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/39.edn_disable.1569991328
Short name T116
Test name
Test status
Simulation time 41119737 ps
CPU time 0.83 seconds
Started Oct 15 01:33:10 PM PDT 23
Finished Oct 15 01:33:12 PM PDT 23
Peak memory 215068 kb
Host smart-3998ce73-ce1c-4038-a252-86fa00084d2f
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569991328 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.1569991328
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable.1142012364
Short name T251
Test name
Test status
Simulation time 30382395 ps
CPU time 0.8 seconds
Started Oct 15 01:31:15 PM PDT 23
Finished Oct 15 01:31:16 PM PDT 23
Peak memory 215040 kb
Host smart-a01b4de0-fe23-4c77-b0f6-4fb16b77aef4
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142012364 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.1142012364
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable.3943560877
Short name T32
Test name
Test status
Simulation time 20261695 ps
CPU time 0.79 seconds
Started Oct 15 01:31:44 PM PDT 23
Finished Oct 15 01:31:45 PM PDT 23
Peak memory 215184 kb
Host smart-004074f3-4d1f-4cd4-af3b-56660acaff43
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943560877 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.3943560877
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.1814919392
Short name T206
Test name
Test status
Simulation time 23975831 ps
CPU time 0.82 seconds
Started Oct 15 01:10:38 PM PDT 23
Finished Oct 15 01:10:40 PM PDT 23
Peak memory 206424 kb
Host smart-c0257493-2c0d-4bf1-bed0-5c9f382a4ce8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814919392 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.1814919392
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/default/38.edn_intr.2087100585
Short name T128
Test name
Test status
Simulation time 26771873 ps
CPU time 0.81 seconds
Started Oct 15 01:33:15 PM PDT 23
Finished Oct 15 01:33:16 PM PDT 23
Peak memory 215312 kb
Host smart-ade58795-44ec-4f98-bcc9-ace9e1c64bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087100585 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.2087100585
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/36.edn_genbits.3903202772
Short name T12
Test name
Test status
Simulation time 31709933 ps
CPU time 1.43 seconds
Started Oct 15 01:31:47 PM PDT 23
Finished Oct 15 01:31:49 PM PDT 23
Peak memory 214916 kb
Host smart-5cf3a849-2ba2-44e7-bd7a-ebfa23e039e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903202772 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.3903202772
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.3604933570
Short name T106
Test name
Test status
Simulation time 22792055 ps
CPU time 0.95 seconds
Started Oct 15 01:31:02 PM PDT 23
Finished Oct 15 01:31:04 PM PDT 23
Peak memory 215296 kb
Host smart-74ce8488-a293-42fe-ae39-0e6a33705515
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604933570 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.3604933570
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_genbits.4008325160
Short name T11
Test name
Test status
Simulation time 66647979 ps
CPU time 1.15 seconds
Started Oct 15 01:31:30 PM PDT 23
Finished Oct 15 01:31:32 PM PDT 23
Peak memory 214928 kb
Host smart-b8d73a94-399f-4499-b801-0aeb789e1a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008325160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.4008325160
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_disable.1568667690
Short name T146
Test name
Test status
Simulation time 91823201 ps
CPU time 0.82 seconds
Started Oct 15 01:31:29 PM PDT 23
Finished Oct 15 01:31:30 PM PDT 23
Peak memory 206816 kb
Host smart-aa60e552-da44-47f3-9414-68813db970ee
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568667690 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.1568667690
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.841510833
Short name T39
Test name
Test status
Simulation time 67151368 ps
CPU time 0.99 seconds
Started Oct 15 01:31:16 PM PDT 23
Finished Oct 15 01:31:17 PM PDT 23
Peak memory 216384 kb
Host smart-15ad5d40-588d-4558-a707-dbffffdcf469
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841510833 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_di
sable_auto_req_mode.841510833
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.2366118522
Short name T238
Test name
Test status
Simulation time 68091155477 ps
CPU time 1715.12 seconds
Started Oct 15 01:31:34 PM PDT 23
Finished Oct 15 02:00:11 PM PDT 23
Peak memory 220700 kb
Host smart-f367e82e-c13a-4c5b-a77e-e455bd1da509
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366118522 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.2366118522
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_genbits.2291279280
Short name T273
Test name
Test status
Simulation time 41225308 ps
CPU time 1.21 seconds
Started Oct 15 01:32:33 PM PDT 23
Finished Oct 15 01:32:34 PM PDT 23
Peak memory 214992 kb
Host smart-86e7fe81-c296-4241-955f-a30c9edccef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291279280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.2291279280
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.865708280
Short name T560
Test name
Test status
Simulation time 32500093 ps
CPU time 1.1 seconds
Started Oct 15 01:30:59 PM PDT 23
Finished Oct 15 01:31:01 PM PDT 23
Peak memory 215396 kb
Host smart-246e76d8-cf64-4f06-9fe0-89575e1a07a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865708280 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_di
sable_auto_req_mode.865708280
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_disable.4099137912
Short name T179
Test name
Test status
Simulation time 55929691 ps
CPU time 0.81 seconds
Started Oct 15 01:32:12 PM PDT 23
Finished Oct 15 01:32:14 PM PDT 23
Peak memory 214992 kb
Host smart-04a7d6be-6479-4008-925f-2fafc298c7cb
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099137912 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.4099137912
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/11.edn_alert.259359784
Short name T297
Test name
Test status
Simulation time 21744838 ps
CPU time 0.98 seconds
Started Oct 15 01:30:57 PM PDT 23
Finished Oct 15 01:30:58 PM PDT 23
Peak memory 206200 kb
Host smart-08e73012-ba6f-4add-95c2-f1ca1e89b25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259359784 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.259359784
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert.909272450
Short name T605
Test name
Test status
Simulation time 49075176 ps
CPU time 0.89 seconds
Started Oct 15 01:31:30 PM PDT 23
Finished Oct 15 01:31:31 PM PDT 23
Peak memory 206720 kb
Host smart-25a9e624-805b-4e85-92fd-47d071cc16fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909272450 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.909272450
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert.1092320520
Short name T17
Test name
Test status
Simulation time 56838632 ps
CPU time 0.97 seconds
Started Oct 15 01:31:44 PM PDT 23
Finished Oct 15 01:31:46 PM PDT 23
Peak memory 206748 kb
Host smart-bb9c0745-6b2d-497e-9036-a987d9c7c298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092320520 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.1092320520
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/18.edn_genbits.3268559866
Short name T265
Test name
Test status
Simulation time 60137814 ps
CPU time 1.13 seconds
Started Oct 15 01:31:37 PM PDT 23
Finished Oct 15 01:31:39 PM PDT 23
Peak memory 205960 kb
Host smart-e1a4af55-6fd2-4cea-94c4-821eaa57403f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268559866 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.3268559866
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_regwen.4110495746
Short name T295
Test name
Test status
Simulation time 66925141 ps
CPU time 0.8 seconds
Started Oct 15 01:31:37 PM PDT 23
Finished Oct 15 01:31:39 PM PDT 23
Peak memory 205624 kb
Host smart-48c1c535-b1b5-4b7d-9e8a-ab61b8addd19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110495746 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.4110495746
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/42.edn_genbits.791288888
Short name T274
Test name
Test status
Simulation time 45104003 ps
CPU time 1.13 seconds
Started Oct 15 01:33:06 PM PDT 23
Finished Oct 15 01:33:08 PM PDT 23
Peak memory 215032 kb
Host smart-420e3508-1302-4d56-a6c9-23e426c14ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791288888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.791288888
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.2949150104
Short name T19
Test name
Test status
Simulation time 24319812 ps
CPU time 0.9 seconds
Started Oct 15 01:31:07 PM PDT 23
Finished Oct 15 01:31:09 PM PDT 23
Peak memory 205452 kb
Host smart-4cf27227-0391-4708-bf9d-13ff41752d36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949150104 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.2949150104
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_genbits.4090786300
Short name T115
Test name
Test status
Simulation time 32138134 ps
CPU time 0.93 seconds
Started Oct 15 01:32:09 PM PDT 23
Finished Oct 15 01:32:10 PM PDT 23
Peak memory 206044 kb
Host smart-68e33d14-48fc-428b-8298-4af0398acb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090786300 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.4090786300
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_regwen.597292449
Short name T296
Test name
Test status
Simulation time 15945095 ps
CPU time 0.89 seconds
Started Oct 15 01:30:58 PM PDT 23
Finished Oct 15 01:31:00 PM PDT 23
Peak memory 205624 kb
Host smart-f4a12825-fe31-42df-a1ba-a5c53b14a7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597292449 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.597292449
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/47.edn_intr.393363520
Short name T78
Test name
Test status
Simulation time 33715009 ps
CPU time 0.87 seconds
Started Oct 15 01:34:12 PM PDT 23
Finished Oct 15 01:34:14 PM PDT 23
Peak memory 215180 kb
Host smart-53fb582a-9f10-42f9-a522-01027a9f157a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393363520 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.393363520
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.3015591533
Short name T31
Test name
Test status
Simulation time 23793132 ps
CPU time 1.04 seconds
Started Oct 15 01:31:38 PM PDT 23
Finished Oct 15 01:31:40 PM PDT 23
Peak memory 215256 kb
Host smart-dea0eb31-8308-424e-8746-8fe0d8873e9e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015591533 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.3015591533
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_genbits.3733636849
Short name T75
Test name
Test status
Simulation time 42001152 ps
CPU time 1.05 seconds
Started Oct 15 01:31:02 PM PDT 23
Finished Oct 15 01:31:04 PM PDT 23
Peak memory 206044 kb
Host smart-8526ccf2-cf9e-4aba-83e8-0d28e64b8eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733636849 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.3733636849
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3737316145
Short name T281
Test name
Test status
Simulation time 192468946 ps
CPU time 3.7 seconds
Started Oct 15 01:10:59 PM PDT 23
Finished Oct 15 01:11:03 PM PDT 23
Peak memory 206576 kb
Host smart-a53ce4b1-ae25-44a0-b60a-e60032de17d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737316145 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.3737316145
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_regwen.3671205734
Short name T109
Test name
Test status
Simulation time 13545854 ps
CPU time 0.84 seconds
Started Oct 15 01:31:04 PM PDT 23
Finished Oct 15 01:31:05 PM PDT 23
Peak memory 205388 kb
Host smart-390a01f4-d9b2-4146-8ee0-8218c465da4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671205734 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.3671205734
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_stress_all.163935239
Short name T264
Test name
Test status
Simulation time 106144732 ps
CPU time 1.01 seconds
Started Oct 15 01:31:17 PM PDT 23
Finished Oct 15 01:31:18 PM PDT 23
Peak memory 205656 kb
Host smart-8058de53-0e12-4915-bad4-86b161ae38d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163935239 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.163935239
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_alert.2005390476
Short name T299
Test name
Test status
Simulation time 24064652 ps
CPU time 1.01 seconds
Started Oct 15 01:31:24 PM PDT 23
Finished Oct 15 01:31:26 PM PDT 23
Peak memory 205896 kb
Host smart-4683139d-7458-4930-8f52-9469c39bc7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005390476 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.2005390476
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert.1578663380
Short name T302
Test name
Test status
Simulation time 55018214 ps
CPU time 0.97 seconds
Started Oct 15 01:31:03 PM PDT 23
Finished Oct 15 01:31:05 PM PDT 23
Peak memory 206812 kb
Host smart-4dc86b79-f916-4a86-b2b8-faccc901c7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578663380 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.1578663380
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/14.edn_genbits.1957563243
Short name T74
Test name
Test status
Simulation time 17115896 ps
CPU time 0.95 seconds
Started Oct 15 01:31:28 PM PDT 23
Finished Oct 15 01:31:30 PM PDT 23
Peak memory 205684 kb
Host smart-023376be-ba11-49a9-9547-aea1d04d5a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957563243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.1957563243
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_stress_all.552511992
Short name T269
Test name
Test status
Simulation time 70987353 ps
CPU time 1.93 seconds
Started Oct 15 01:31:33 PM PDT 23
Finished Oct 15 01:31:37 PM PDT 23
Peak memory 206260 kb
Host smart-8721f77d-9752-4106-9a7c-f878604e109b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552511992 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.552511992
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_genbits.2745137942
Short name T43
Test name
Test status
Simulation time 19634647 ps
CPU time 1.17 seconds
Started Oct 15 01:31:18 PM PDT 23
Finished Oct 15 01:31:20 PM PDT 23
Peak memory 206432 kb
Host smart-5660b17f-5711-4b0c-8000-10290374866c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745137942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.2745137942
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.4154717837
Short name T723
Test name
Test status
Simulation time 112715374793 ps
CPU time 2663.04 seconds
Started Oct 15 01:31:00 PM PDT 23
Finished Oct 15 02:15:25 PM PDT 23
Peak memory 223660 kb
Host smart-c1d80127-c22b-4b77-82f0-67d4aad51d28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154717837 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.4154717837
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_genbits.970305317
Short name T289
Test name
Test status
Simulation time 85673047 ps
CPU time 0.91 seconds
Started Oct 15 01:31:40 PM PDT 23
Finished Oct 15 01:31:42 PM PDT 23
Peak memory 205820 kb
Host smart-359cff63-4eb9-45df-b0c8-8f404e18a4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970305317 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.970305317
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.2175434538
Short name T195
Test name
Test status
Simulation time 70365068694 ps
CPU time 773.43 seconds
Started Oct 15 01:31:32 PM PDT 23
Finished Oct 15 01:44:28 PM PDT 23
Peak memory 216580 kb
Host smart-7d157b4c-894d-4ed8-a9a9-07e75df94af1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175434538 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.2175434538
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.edn_regwen.1162757138
Short name T305
Test name
Test status
Simulation time 46488810 ps
CPU time 0.86 seconds
Started Oct 15 01:31:03 PM PDT 23
Finished Oct 15 01:31:05 PM PDT 23
Peak memory 205536 kb
Host smart-5c7b63a5-5b54-4384-897d-02b18f880a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162757138 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.1162757138
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/40.edn_genbits.885875151
Short name T111
Test name
Test status
Simulation time 31729972 ps
CPU time 1.38 seconds
Started Oct 15 01:34:00 PM PDT 23
Finished Oct 15 01:34:02 PM PDT 23
Peak memory 214860 kb
Host smart-d3d09b5d-285d-43b4-b02f-e2fd578bb4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885875151 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.885875151
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_genbits.553079501
Short name T261
Test name
Test status
Simulation time 24309392 ps
CPU time 1.13 seconds
Started Oct 15 01:31:37 PM PDT 23
Finished Oct 15 01:31:39 PM PDT 23
Peak memory 214844 kb
Host smart-43974846-87ae-4cca-b122-53a05f46431a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553079501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.553079501
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.878428560
Short name T125
Test name
Test status
Simulation time 22639745 ps
CPU time 1.01 seconds
Started Oct 15 01:31:43 PM PDT 23
Finished Oct 15 01:31:45 PM PDT 23
Peak memory 226324 kb
Host smart-faaf6d89-a103-46ca-a909-a6f1289407e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878428560 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.878428560
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/13.edn_disable.2406636005
Short name T69
Test name
Test status
Simulation time 47150828 ps
CPU time 0.82 seconds
Started Oct 15 01:31:10 PM PDT 23
Finished Oct 15 01:31:12 PM PDT 23
Peak memory 214980 kb
Host smart-7a7ff7e6-de5a-4fca-9248-8eea8c83e2df
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406636005 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.2406636005
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable.3195359756
Short name T149
Test name
Test status
Simulation time 66544471 ps
CPU time 0.79 seconds
Started Oct 15 01:31:28 PM PDT 23
Finished Oct 15 01:31:30 PM PDT 23
Peak memory 215028 kb
Host smart-75f8ce45-3fcc-42c5-820f-f51ba6ae6620
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195359756 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.3195359756
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable.92076511
Short name T87
Test name
Test status
Simulation time 22045899 ps
CPU time 0.83 seconds
Started Oct 15 01:31:44 PM PDT 23
Finished Oct 15 01:31:45 PM PDT 23
Peak memory 214996 kb
Host smart-bfe3fca9-03eb-4c4e-822e-15bac15edc5e
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92076511 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.92076511
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable.3504083995
Short name T152
Test name
Test status
Simulation time 10577479 ps
CPU time 0.89 seconds
Started Oct 15 01:31:46 PM PDT 23
Finished Oct 15 01:31:48 PM PDT 23
Peak memory 215048 kb
Host smart-5dac4de3-07b5-4e0a-9bea-fcb232e01e91
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504083995 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.3504083995
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/8.edn_genbits.3669882141
Short name T279
Test name
Test status
Simulation time 67457024 ps
CPU time 1.39 seconds
Started Oct 15 01:31:11 PM PDT 23
Finished Oct 15 01:31:13 PM PDT 23
Peak memory 214880 kb
Host smart-4c83700c-7fe0-4688-b364-afd94018ce6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669882141 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.3669882141
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3891541889
Short name T220
Test name
Test status
Simulation time 26801973 ps
CPU time 1.04 seconds
Started Oct 15 01:10:16 PM PDT 23
Finished Oct 15 01:10:18 PM PDT 23
Peak memory 206600 kb
Host smart-0119d3e3-64c2-4efa-932e-3847bad55f52
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891541889 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.3891541889
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3892229899
Short name T457
Test name
Test status
Simulation time 216876080 ps
CPU time 3.27 seconds
Started Oct 15 01:10:30 PM PDT 23
Finished Oct 15 01:10:34 PM PDT 23
Peak memory 206580 kb
Host smart-ed1933ab-e855-43d9-88cf-91f3862165dc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892229899 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.3892229899
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3412899760
Short name T433
Test name
Test status
Simulation time 31162496 ps
CPU time 0.8 seconds
Started Oct 15 01:10:19 PM PDT 23
Finished Oct 15 01:10:21 PM PDT 23
Peak memory 206240 kb
Host smart-dfafc1ca-89b4-43e3-b4dc-166c7f24b99d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412899760 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.3412899760
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3147694806
Short name T379
Test name
Test status
Simulation time 50335873 ps
CPU time 1.46 seconds
Started Oct 15 01:10:16 PM PDT 23
Finished Oct 15 01:10:17 PM PDT 23
Peak memory 214864 kb
Host smart-9030b2e1-1ae4-4420-b91c-b556abef812d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147694806 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.3147694806
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.661828242
Short name T454
Test name
Test status
Simulation time 14492712 ps
CPU time 0.89 seconds
Started Oct 15 01:10:34 PM PDT 23
Finished Oct 15 01:10:35 PM PDT 23
Peak memory 206556 kb
Host smart-6419c22b-7948-4074-a4c3-73c7f3f3e801
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661828242 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.661828242
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.475964374
Short name T211
Test name
Test status
Simulation time 14791733 ps
CPU time 0.89 seconds
Started Oct 15 01:10:16 PM PDT 23
Finished Oct 15 01:10:18 PM PDT 23
Peak memory 206424 kb
Host smart-06c1fa5c-a994-4426-860e-38678fb23b37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475964374 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.475964374
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3863281156
Short name T230
Test name
Test status
Simulation time 77731909 ps
CPU time 1.45 seconds
Started Oct 15 01:10:16 PM PDT 23
Finished Oct 15 01:10:18 PM PDT 23
Peak memory 206556 kb
Host smart-3fbb05f5-8ce7-40de-915f-903bf0d140ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863281156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.3863281156
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.1347933962
Short name T439
Test name
Test status
Simulation time 82043446 ps
CPU time 1.55 seconds
Started Oct 15 01:10:17 PM PDT 23
Finished Oct 15 01:10:19 PM PDT 23
Peak memory 214720 kb
Host smart-6c766faa-5c91-4b69-b2f3-fc3d50120c85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347933962 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.1347933962
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.127657064
Short name T461
Test name
Test status
Simulation time 31193010 ps
CPU time 1.2 seconds
Started Oct 15 01:10:38 PM PDT 23
Finished Oct 15 01:10:40 PM PDT 23
Peak memory 206624 kb
Host smart-68044c81-193a-4730-bf26-2a7b5948c49f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127657064 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.127657064
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.563521366
Short name T432
Test name
Test status
Simulation time 180840457 ps
CPU time 3.04 seconds
Started Oct 15 01:10:17 PM PDT 23
Finished Oct 15 01:10:20 PM PDT 23
Peak memory 206604 kb
Host smart-12c9c5a8-95d7-4980-a5d0-dd4780d4466e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563521366 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.563521366
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1756354396
Short name T450
Test name
Test status
Simulation time 49813057 ps
CPU time 0.93 seconds
Started Oct 15 01:10:29 PM PDT 23
Finished Oct 15 01:10:32 PM PDT 23
Peak memory 206596 kb
Host smart-bf2f5530-e739-49f3-a42a-b36bb14f7865
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756354396 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.1756354396
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3846040704
Short name T366
Test name
Test status
Simulation time 25153742 ps
CPU time 1.62 seconds
Started Oct 15 01:10:39 PM PDT 23
Finished Oct 15 01:10:41 PM PDT 23
Peak memory 222932 kb
Host smart-7fb7e93d-d33a-467c-bd4b-503e77b47ff9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846040704 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.3846040704
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.2589420886
Short name T453
Test name
Test status
Simulation time 27886210 ps
CPU time 0.94 seconds
Started Oct 15 01:10:16 PM PDT 23
Finished Oct 15 01:10:18 PM PDT 23
Peak memory 206492 kb
Host smart-23dd0408-de56-42cd-affc-104ff70b4ae8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589420886 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.2589420886
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.3365578761
Short name T352
Test name
Test status
Simulation time 17655450 ps
CPU time 0.96 seconds
Started Oct 15 01:10:20 PM PDT 23
Finished Oct 15 01:10:21 PM PDT 23
Peak memory 206340 kb
Host smart-b3a75c53-5a86-4f96-af6f-dfcdc925871d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365578761 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3365578761
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.3495472833
Short name T227
Test name
Test status
Simulation time 36762059 ps
CPU time 1.12 seconds
Started Oct 15 01:10:32 PM PDT 23
Finished Oct 15 01:10:34 PM PDT 23
Peak memory 206572 kb
Host smart-524bd269-77e5-4e3b-81b5-f5184c443b0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495472833 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.3495472833
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.2540023329
Short name T358
Test name
Test status
Simulation time 44086102 ps
CPU time 1.92 seconds
Started Oct 15 01:10:17 PM PDT 23
Finished Oct 15 01:10:19 PM PDT 23
Peak memory 214796 kb
Host smart-6fc249c2-325c-4dea-9673-2139514e8fd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540023329 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.2540023329
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2203398852
Short name T259
Test name
Test status
Simulation time 63167699 ps
CPU time 1.55 seconds
Started Oct 15 01:10:31 PM PDT 23
Finished Oct 15 01:10:33 PM PDT 23
Peak memory 206600 kb
Host smart-c639c84f-ea84-4166-a9aa-b358abb3a678
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203398852 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.2203398852
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1084235312
Short name T446
Test name
Test status
Simulation time 29318798 ps
CPU time 1.01 seconds
Started Oct 15 01:10:34 PM PDT 23
Finished Oct 15 01:10:36 PM PDT 23
Peak memory 214784 kb
Host smart-c7d91f33-0e56-411f-911d-8815eb1cdc6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084235312 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.1084235312
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.2677343791
Short name T428
Test name
Test status
Simulation time 14665327 ps
CPU time 0.91 seconds
Started Oct 15 01:10:32 PM PDT 23
Finished Oct 15 01:10:34 PM PDT 23
Peak memory 206504 kb
Host smart-edec90e4-0e1b-463f-9a4c-054cc2688544
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677343791 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.2677343791
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.1760607677
Short name T342
Test name
Test status
Simulation time 12187281 ps
CPU time 0.84 seconds
Started Oct 15 01:10:36 PM PDT 23
Finished Oct 15 01:10:37 PM PDT 23
Peak memory 206340 kb
Host smart-0f43eceb-bc15-488c-a585-9469e36a92a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760607677 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.1760607677
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2969627465
Short name T400
Test name
Test status
Simulation time 124811338 ps
CPU time 1.19 seconds
Started Oct 15 01:10:38 PM PDT 23
Finished Oct 15 01:10:40 PM PDT 23
Peak memory 206476 kb
Host smart-13debff6-8d88-477b-91d4-4a69af3c6ead
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969627465 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.2969627465
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.2548990320
Short name T351
Test name
Test status
Simulation time 29280407 ps
CPU time 1.89 seconds
Started Oct 15 01:10:40 PM PDT 23
Finished Oct 15 01:10:44 PM PDT 23
Peak memory 214872 kb
Host smart-66835ffa-35e0-4a8a-a7da-e5402e50dfeb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548990320 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.2548990320
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2365158483
Short name T419
Test name
Test status
Simulation time 74811004 ps
CPU time 1.83 seconds
Started Oct 15 01:10:44 PM PDT 23
Finished Oct 15 01:10:46 PM PDT 23
Peak memory 206604 kb
Host smart-3e8cb15e-d2e3-4e84-8c0e-6e66c362efa8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365158483 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.2365158483
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.323196967
Short name T418
Test name
Test status
Simulation time 27668372 ps
CPU time 1.87 seconds
Started Oct 15 01:10:40 PM PDT 23
Finished Oct 15 01:10:44 PM PDT 23
Peak memory 214788 kb
Host smart-2f029120-0309-4b5f-8d11-bbb4c68d9e29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323196967 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.323196967
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.2626851929
Short name T434
Test name
Test status
Simulation time 41503859 ps
CPU time 0.81 seconds
Started Oct 15 01:11:02 PM PDT 23
Finished Oct 15 01:11:03 PM PDT 23
Peak memory 206520 kb
Host smart-83c0a52e-3779-4077-9a1e-2b9fd250cc2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626851929 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.2626851929
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1431659626
Short name T462
Test name
Test status
Simulation time 18075860 ps
CPU time 1.13 seconds
Started Oct 15 01:10:34 PM PDT 23
Finished Oct 15 01:10:36 PM PDT 23
Peak memory 206592 kb
Host smart-14d48a1d-76e1-4924-aaaf-f87065b82b5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431659626 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.1431659626
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.2085538089
Short name T370
Test name
Test status
Simulation time 77254859 ps
CPU time 1.68 seconds
Started Oct 15 01:10:37 PM PDT 23
Finished Oct 15 01:10:40 PM PDT 23
Peak memory 214772 kb
Host smart-6b1935e5-492f-4a92-a396-e243e9cef972
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085538089 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.2085538089
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2492389225
Short name T436
Test name
Test status
Simulation time 171644634 ps
CPU time 2.38 seconds
Started Oct 15 01:10:59 PM PDT 23
Finished Oct 15 01:11:01 PM PDT 23
Peak memory 206552 kb
Host smart-a963a752-bcf8-447c-a4be-a0155c1dd4ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492389225 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.2492389225
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3827028801
Short name T207
Test name
Test status
Simulation time 26610552 ps
CPU time 1.6 seconds
Started Oct 15 01:10:46 PM PDT 23
Finished Oct 15 01:10:48 PM PDT 23
Peak memory 214928 kb
Host smart-1d11cdcb-fc87-43fe-822a-d75eb07d5f89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827028801 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.3827028801
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.4252689474
Short name T341
Test name
Test status
Simulation time 23703441 ps
CPU time 0.8 seconds
Started Oct 15 01:10:39 PM PDT 23
Finished Oct 15 01:10:40 PM PDT 23
Peak memory 206284 kb
Host smart-fea0df75-8e94-4072-a547-73fe4a1c0f84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252689474 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.4252689474
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.2370334863
Short name T339
Test name
Test status
Simulation time 16424936 ps
CPU time 0.88 seconds
Started Oct 15 01:10:32 PM PDT 23
Finished Oct 15 01:10:33 PM PDT 23
Peak memory 206432 kb
Host smart-2275eb01-67cc-4433-9801-a27b0d47d0b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370334863 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.2370334863
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3319147633
Short name T420
Test name
Test status
Simulation time 107028461 ps
CPU time 1.1 seconds
Started Oct 15 01:10:40 PM PDT 23
Finished Oct 15 01:10:43 PM PDT 23
Peak memory 206536 kb
Host smart-88ed19ec-b144-4813-a11a-a769b9ee6758
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319147633 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.3319147633
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.3684713145
Short name T431
Test name
Test status
Simulation time 412293862 ps
CPU time 3.92 seconds
Started Oct 15 01:10:33 PM PDT 23
Finished Oct 15 01:10:37 PM PDT 23
Peak memory 214816 kb
Host smart-f593ad3b-5247-42ce-9942-4b102f9fdf2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684713145 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3684713145
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1827170845
Short name T460
Test name
Test status
Simulation time 63362507 ps
CPU time 1.8 seconds
Started Oct 15 01:10:44 PM PDT 23
Finished Oct 15 01:10:47 PM PDT 23
Peak memory 206564 kb
Host smart-45135d26-dd95-420c-ac86-edcdb5b42570
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827170845 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.1827170845
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3045741092
Short name T427
Test name
Test status
Simulation time 34656318 ps
CPU time 1.32 seconds
Started Oct 15 01:11:05 PM PDT 23
Finished Oct 15 01:11:07 PM PDT 23
Peak memory 214668 kb
Host smart-d90aea2e-9080-4821-b15e-8e974dae0ef9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045741092 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.3045741092
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.864561464
Short name T406
Test name
Test status
Simulation time 16427806 ps
CPU time 0.8 seconds
Started Oct 15 01:10:45 PM PDT 23
Finished Oct 15 01:10:46 PM PDT 23
Peak memory 206364 kb
Host smart-4b5a26da-0e77-479b-8324-9cddc066ba3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864561464 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.864561464
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.2918663525
Short name T345
Test name
Test status
Simulation time 19442710 ps
CPU time 0.81 seconds
Started Oct 15 01:10:47 PM PDT 23
Finished Oct 15 01:10:48 PM PDT 23
Peak memory 206308 kb
Host smart-13dadd93-d519-4113-8e68-7ff65c244028
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918663525 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.2918663525
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.44542566
Short name T465
Test name
Test status
Simulation time 36996391 ps
CPU time 1.39 seconds
Started Oct 15 01:10:38 PM PDT 23
Finished Oct 15 01:10:40 PM PDT 23
Peak memory 206636 kb
Host smart-423d5512-3f2b-4a86-bf0b-f6ed33d1df63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44542566 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_out
standing.44542566
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.99303311
Short name T363
Test name
Test status
Simulation time 101582857 ps
CPU time 3.8 seconds
Started Oct 15 01:10:43 PM PDT 23
Finished Oct 15 01:10:47 PM PDT 23
Peak memory 214704 kb
Host smart-e7e3f4ea-5ecd-48a9-bcee-5dc24054cd41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99303311 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.99303311
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2670732101
Short name T391
Test name
Test status
Simulation time 155902319 ps
CPU time 2.34 seconds
Started Oct 15 01:10:41 PM PDT 23
Finished Oct 15 01:10:45 PM PDT 23
Peak memory 206676 kb
Host smart-614b9ea2-d12e-4655-8902-f1d36f26a27f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670732101 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.2670732101
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2901257747
Short name T424
Test name
Test status
Simulation time 16767891 ps
CPU time 1.02 seconds
Started Oct 15 01:11:04 PM PDT 23
Finished Oct 15 01:11:05 PM PDT 23
Peak memory 206592 kb
Host smart-33ff5a13-8174-47ab-9d1a-25079155e524
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901257747 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2901257747
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.604386280
Short name T209
Test name
Test status
Simulation time 98451369 ps
CPU time 0.82 seconds
Started Oct 15 01:10:38 PM PDT 23
Finished Oct 15 01:10:39 PM PDT 23
Peak memory 206240 kb
Host smart-fb453199-3493-4359-afe7-4b81b7235203
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604386280 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.604386280
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.2871028884
Short name T410
Test name
Test status
Simulation time 112123869 ps
CPU time 0.81 seconds
Started Oct 15 01:11:01 PM PDT 23
Finished Oct 15 01:11:02 PM PDT 23
Peak memory 206076 kb
Host smart-8c06ec39-06d7-49a7-932e-af997dd7adc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871028884 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.2871028884
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.312447577
Short name T396
Test name
Test status
Simulation time 55227275 ps
CPU time 0.87 seconds
Started Oct 15 01:10:39 PM PDT 23
Finished Oct 15 01:10:41 PM PDT 23
Peak memory 206444 kb
Host smart-f37b0785-9a3d-459c-9067-4988f37d8fb5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312447577 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_ou
tstanding.312447577
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.1013827130
Short name T407
Test name
Test status
Simulation time 435335353 ps
CPU time 4.05 seconds
Started Oct 15 01:10:39 PM PDT 23
Finished Oct 15 01:10:44 PM PDT 23
Peak memory 214668 kb
Host smart-c024572c-5543-46ba-94ee-a425b6228000
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013827130 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.1013827130
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3596209625
Short name T385
Test name
Test status
Simulation time 177244099 ps
CPU time 1.53 seconds
Started Oct 15 01:11:05 PM PDT 23
Finished Oct 15 01:11:07 PM PDT 23
Peak memory 206356 kb
Host smart-26be9270-9176-42f8-87d7-71c4c9ae209d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596209625 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.3596209625
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.3553089409
Short name T413
Test name
Test status
Simulation time 27069758 ps
CPU time 0.98 seconds
Started Oct 15 01:11:19 PM PDT 23
Finished Oct 15 01:11:20 PM PDT 23
Peak memory 206536 kb
Host smart-cd4b56df-372b-4b8c-8e4a-145174bdad20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553089409 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.3553089409
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.1554737588
Short name T205
Test name
Test status
Simulation time 67258823 ps
CPU time 0.88 seconds
Started Oct 15 01:11:00 PM PDT 23
Finished Oct 15 01:11:01 PM PDT 23
Peak memory 206500 kb
Host smart-611ab9db-dc9b-4daa-8381-c77a991cd25c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554737588 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.1554737588
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.2846674093
Short name T437
Test name
Test status
Simulation time 11451984 ps
CPU time 0.8 seconds
Started Oct 15 01:11:07 PM PDT 23
Finished Oct 15 01:11:08 PM PDT 23
Peak memory 206444 kb
Host smart-41b1a8f0-11bb-4aa2-a6d1-70d4cff08150
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846674093 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.2846674093
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.115488259
Short name T412
Test name
Test status
Simulation time 223567637 ps
CPU time 1.36 seconds
Started Oct 15 01:11:04 PM PDT 23
Finished Oct 15 01:11:06 PM PDT 23
Peak memory 206540 kb
Host smart-25a062bd-b358-470c-83d0-832cdba975a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115488259 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_ou
tstanding.115488259
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.799634727
Short name T390
Test name
Test status
Simulation time 52918997 ps
CPU time 2.06 seconds
Started Oct 15 01:11:03 PM PDT 23
Finished Oct 15 01:11:06 PM PDT 23
Peak memory 214844 kb
Host smart-60896be1-e2c4-44ef-a9a3-8b8ea91d467a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799634727 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.799634727
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.993438793
Short name T403
Test name
Test status
Simulation time 62043315 ps
CPU time 1.5 seconds
Started Oct 15 01:11:08 PM PDT 23
Finished Oct 15 01:11:10 PM PDT 23
Peak memory 206680 kb
Host smart-953db43a-fac0-4322-8666-5993a84fa381
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993438793 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.993438793
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3160428212
Short name T371
Test name
Test status
Simulation time 71520219 ps
CPU time 0.99 seconds
Started Oct 15 01:11:31 PM PDT 23
Finished Oct 15 01:11:33 PM PDT 23
Peak memory 214880 kb
Host smart-96c2ce87-c365-4de5-a159-a98a1b09c877
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160428212 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.3160428212
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.1454600841
Short name T425
Test name
Test status
Simulation time 104884487 ps
CPU time 0.81 seconds
Started Oct 15 01:11:00 PM PDT 23
Finished Oct 15 01:11:02 PM PDT 23
Peak memory 206604 kb
Host smart-f0b9bd07-0860-4326-a602-f3bbdba34cce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454600841 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1454600841
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3898159851
Short name T369
Test name
Test status
Simulation time 23579112 ps
CPU time 0.87 seconds
Started Oct 15 01:11:23 PM PDT 23
Finished Oct 15 01:11:24 PM PDT 23
Peak memory 206444 kb
Host smart-97cd0594-c2b5-460d-8b56-57634f4530d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898159851 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3898159851
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3260147361
Short name T226
Test name
Test status
Simulation time 40638845 ps
CPU time 0.93 seconds
Started Oct 15 01:11:23 PM PDT 23
Finished Oct 15 01:11:24 PM PDT 23
Peak memory 206632 kb
Host smart-8d93d040-8f4c-471e-bf3b-1e6a80de703c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260147361 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.3260147361
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.423893486
Short name T444
Test name
Test status
Simulation time 447025430 ps
CPU time 3.16 seconds
Started Oct 15 01:11:05 PM PDT 23
Finished Oct 15 01:11:09 PM PDT 23
Peak memory 214824 kb
Host smart-4e88bdbf-563d-4b94-8c8a-d8bf1b90ba3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423893486 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.423893486
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1744529469
Short name T411
Test name
Test status
Simulation time 335769795 ps
CPU time 1.55 seconds
Started Oct 15 01:11:50 PM PDT 23
Finished Oct 15 01:11:52 PM PDT 23
Peak memory 206532 kb
Host smart-0afce1ad-e48c-41c2-9774-3d20b0543a78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744529469 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.1744529469
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2846158588
Short name T347
Test name
Test status
Simulation time 20823619 ps
CPU time 0.9 seconds
Started Oct 15 01:10:41 PM PDT 23
Finished Oct 15 01:10:43 PM PDT 23
Peak memory 206660 kb
Host smart-28f9e816-0287-41d6-a1bb-77eed115fe26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846158588 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2846158588
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.2740855489
Short name T398
Test name
Test status
Simulation time 15073308 ps
CPU time 0.88 seconds
Started Oct 15 01:11:40 PM PDT 23
Finished Oct 15 01:11:41 PM PDT 23
Peak memory 206528 kb
Host smart-4f8733f5-cdbb-4cdb-bf4a-982a8b05a6aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740855489 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.2740855489
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.838682803
Short name T360
Test name
Test status
Simulation time 12194341 ps
CPU time 0.83 seconds
Started Oct 15 01:11:18 PM PDT 23
Finished Oct 15 01:11:19 PM PDT 23
Peak memory 206368 kb
Host smart-21659a27-954e-445e-aa57-f3b95d15746c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838682803 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.838682803
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.4116384931
Short name T459
Test name
Test status
Simulation time 17251488 ps
CPU time 1 seconds
Started Oct 15 01:10:53 PM PDT 23
Finished Oct 15 01:10:54 PM PDT 23
Peak memory 206624 kb
Host smart-e5439a02-7d3b-4cde-bfef-2b86a9587637
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116384931 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.4116384931
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.4137771344
Short name T357
Test name
Test status
Simulation time 47199131 ps
CPU time 1.76 seconds
Started Oct 15 01:11:39 PM PDT 23
Finished Oct 15 01:11:41 PM PDT 23
Peak memory 214844 kb
Host smart-2308a07c-9fb2-42d0-95ac-257bd3776e99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137771344 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.4137771344
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.555119688
Short name T361
Test name
Test status
Simulation time 168515719 ps
CPU time 1.63 seconds
Started Oct 15 01:11:38 PM PDT 23
Finished Oct 15 01:11:40 PM PDT 23
Peak memory 206440 kb
Host smart-f64714a9-39db-4269-bd6b-607a9c1d83a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555119688 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.555119688
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.4126153044
Short name T213
Test name
Test status
Simulation time 88684909 ps
CPU time 1.35 seconds
Started Oct 15 01:10:54 PM PDT 23
Finished Oct 15 01:10:56 PM PDT 23
Peak memory 214932 kb
Host smart-14345e48-2135-474a-a156-2431876f1094
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126153044 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.4126153044
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.3971794863
Short name T416
Test name
Test status
Simulation time 66453818 ps
CPU time 0.78 seconds
Started Oct 15 01:10:47 PM PDT 23
Finished Oct 15 01:10:48 PM PDT 23
Peak memory 206292 kb
Host smart-ea2cd799-acb6-4884-8b82-5c3cbb7ebe3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971794863 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.3971794863
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.836746106
Short name T463
Test name
Test status
Simulation time 16720667 ps
CPU time 0.89 seconds
Started Oct 15 01:10:42 PM PDT 23
Finished Oct 15 01:10:43 PM PDT 23
Peak memory 206416 kb
Host smart-1470d4e7-a106-4d50-be0d-44d43a25ad89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836746106 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.836746106
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.398476152
Short name T225
Test name
Test status
Simulation time 117729816 ps
CPU time 1.28 seconds
Started Oct 15 01:10:40 PM PDT 23
Finished Oct 15 01:10:43 PM PDT 23
Peak memory 206556 kb
Host smart-d0c93b68-abd1-4368-8008-9e6c79f32ab2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398476152 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_ou
tstanding.398476152
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.2483605736
Short name T389
Test name
Test status
Simulation time 25314240 ps
CPU time 1.42 seconds
Started Oct 15 01:10:38 PM PDT 23
Finished Oct 15 01:10:40 PM PDT 23
Peak memory 214856 kb
Host smart-f7fd42f0-5623-4f44-b126-b0085bc706d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483605736 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.2483605736
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.207214320
Short name T449
Test name
Test status
Simulation time 60443068 ps
CPU time 1.68 seconds
Started Oct 15 01:10:39 PM PDT 23
Finished Oct 15 01:10:41 PM PDT 23
Peak memory 206560 kb
Host smart-4ecc692e-c476-4cff-bba9-18d0ebf2499e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207214320 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.207214320
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.580329392
Short name T210
Test name
Test status
Simulation time 186007833 ps
CPU time 0.99 seconds
Started Oct 15 01:10:40 PM PDT 23
Finished Oct 15 01:10:43 PM PDT 23
Peak memory 206564 kb
Host smart-a0cbca8d-1dc6-4338-9d84-1070134d1b73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580329392 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.580329392
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.2409186343
Short name T388
Test name
Test status
Simulation time 56124766 ps
CPU time 0.84 seconds
Started Oct 15 01:10:41 PM PDT 23
Finished Oct 15 01:10:43 PM PDT 23
Peak memory 206400 kb
Host smart-0d8d5d60-811f-445a-b538-2e78fee994a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409186343 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2409186343
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.2027948189
Short name T429
Test name
Test status
Simulation time 76164010 ps
CPU time 0.83 seconds
Started Oct 15 01:10:57 PM PDT 23
Finished Oct 15 01:10:58 PM PDT 23
Peak memory 206168 kb
Host smart-44f78bfd-8bb3-4460-8d67-8ec19a89eba7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027948189 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2027948189
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.7542305
Short name T402
Test name
Test status
Simulation time 332775440 ps
CPU time 1.05 seconds
Started Oct 15 01:11:06 PM PDT 23
Finished Oct 15 01:11:08 PM PDT 23
Peak memory 206612 kb
Host smart-d8910898-ef73-4d6c-9259-c99d9ce5a781
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7542305 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_outs
tanding.7542305
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.1842218403
Short name T393
Test name
Test status
Simulation time 33773812 ps
CPU time 1.33 seconds
Started Oct 15 01:10:38 PM PDT 23
Finished Oct 15 01:10:40 PM PDT 23
Peak memory 214712 kb
Host smart-cf749762-2de2-4fa7-96c7-c131e979b8c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842218403 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1842218403
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3250909777
Short name T445
Test name
Test status
Simulation time 141537961 ps
CPU time 1.77 seconds
Started Oct 15 01:10:35 PM PDT 23
Finished Oct 15 01:10:38 PM PDT 23
Peak memory 206480 kb
Host smart-30411a26-ecd2-4082-ab90-24039e72ca16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250909777 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.3250909777
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3512503568
Short name T409
Test name
Test status
Simulation time 372964703 ps
CPU time 1.36 seconds
Started Oct 15 01:10:37 PM PDT 23
Finished Oct 15 01:10:39 PM PDT 23
Peak memory 206488 kb
Host smart-640117f9-d237-4856-a7f7-c8d545a57add
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512503568 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.3512503568
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3653261415
Short name T223
Test name
Test status
Simulation time 1309004507 ps
CPU time 6.22 seconds
Started Oct 15 01:10:35 PM PDT 23
Finished Oct 15 01:10:42 PM PDT 23
Peak memory 206552 kb
Host smart-94820ca9-f702-4735-8aab-593bf2dbf56e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653261415 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.3653261415
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3096397567
Short name T216
Test name
Test status
Simulation time 55861220 ps
CPU time 0.89 seconds
Started Oct 15 01:10:41 PM PDT 23
Finished Oct 15 01:10:43 PM PDT 23
Peak memory 206572 kb
Host smart-22004a10-2b45-46c4-9a7d-2ef2be9643d7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096397567 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.3096397567
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.387323030
Short name T208
Test name
Test status
Simulation time 65415340 ps
CPU time 1.04 seconds
Started Oct 15 01:10:38 PM PDT 23
Finished Oct 15 01:10:40 PM PDT 23
Peak memory 214728 kb
Host smart-124916c1-2f0a-4d90-a526-4a5c9b343767
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387323030 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.387323030
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.3334189246
Short name T224
Test name
Test status
Simulation time 40015428 ps
CPU time 0.84 seconds
Started Oct 15 01:10:51 PM PDT 23
Finished Oct 15 01:10:52 PM PDT 23
Peak memory 206576 kb
Host smart-50c04355-dc1f-4612-9562-fd678fd8f674
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334189246 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.3334189246
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.312050659
Short name T340
Test name
Test status
Simulation time 14236297 ps
CPU time 0.9 seconds
Started Oct 15 01:10:37 PM PDT 23
Finished Oct 15 01:10:39 PM PDT 23
Peak memory 206428 kb
Host smart-0ba616ad-29cf-4142-90ab-82102d2062f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312050659 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.312050659
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.626186697
Short name T229
Test name
Test status
Simulation time 25493341 ps
CPU time 1.18 seconds
Started Oct 15 01:10:37 PM PDT 23
Finished Oct 15 01:10:39 PM PDT 23
Peak memory 206476 kb
Host smart-1141f53f-fcbd-4d93-9f54-6e0d968c1624
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626186697 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_out
standing.626186697
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.636664295
Short name T355
Test name
Test status
Simulation time 75486514 ps
CPU time 2.84 seconds
Started Oct 15 01:10:34 PM PDT 23
Finished Oct 15 01:10:38 PM PDT 23
Peak memory 214756 kb
Host smart-c799f92d-699a-4b11-9b39-c5f723bcb9db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636664295 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.636664295
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.4245969728
Short name T280
Test name
Test status
Simulation time 449932437 ps
CPU time 2.29 seconds
Started Oct 15 01:10:19 PM PDT 23
Finished Oct 15 01:10:22 PM PDT 23
Peak memory 206552 kb
Host smart-0514521b-6792-4146-9830-e6031fed9af1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245969728 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.4245969728
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.1522628133
Short name T440
Test name
Test status
Simulation time 13527007 ps
CPU time 0.8 seconds
Started Oct 15 01:10:38 PM PDT 23
Finished Oct 15 01:10:40 PM PDT 23
Peak memory 206428 kb
Host smart-71270aee-f4f6-4bc0-8408-d106913f755e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522628133 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.1522628133
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.237078297
Short name T362
Test name
Test status
Simulation time 14248901 ps
CPU time 0.85 seconds
Started Oct 15 01:10:42 PM PDT 23
Finished Oct 15 01:10:44 PM PDT 23
Peak memory 206448 kb
Host smart-61d656f7-cacf-446f-bc56-42ca1bfb0295
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237078297 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.237078297
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.3398794516
Short name T397
Test name
Test status
Simulation time 15394366 ps
CPU time 0.87 seconds
Started Oct 15 01:10:39 PM PDT 23
Finished Oct 15 01:10:42 PM PDT 23
Peak memory 206452 kb
Host smart-e73f0f60-9e22-4263-bcb6-bc44fba3abdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398794516 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.3398794516
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.1571237672
Short name T373
Test name
Test status
Simulation time 41049658 ps
CPU time 0.82 seconds
Started Oct 15 01:10:34 PM PDT 23
Finished Oct 15 01:10:36 PM PDT 23
Peak memory 206264 kb
Host smart-ec0ceb60-766d-4a6c-941e-977437484a91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571237672 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.1571237672
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.1153820077
Short name T354
Test name
Test status
Simulation time 22321733 ps
CPU time 0.83 seconds
Started Oct 15 01:10:43 PM PDT 23
Finished Oct 15 01:10:44 PM PDT 23
Peak memory 206448 kb
Host smart-a53b3895-4866-4a53-8e05-b7df39ecb80e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153820077 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.1153820077
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.1159642319
Short name T372
Test name
Test status
Simulation time 29591605 ps
CPU time 0.88 seconds
Started Oct 15 01:10:41 PM PDT 23
Finished Oct 15 01:10:43 PM PDT 23
Peak memory 206324 kb
Host smart-744dea90-1754-4986-860c-5cce9ad69fd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159642319 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.1159642319
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.1216233462
Short name T343
Test name
Test status
Simulation time 42285975 ps
CPU time 0.84 seconds
Started Oct 15 01:10:47 PM PDT 23
Finished Oct 15 01:10:49 PM PDT 23
Peak memory 206308 kb
Host smart-ca8f02ed-8b1e-42d1-8c83-0782b7c1d1ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216233462 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.1216233462
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.3114847101
Short name T404
Test name
Test status
Simulation time 57287114 ps
CPU time 0.88 seconds
Started Oct 15 01:10:51 PM PDT 23
Finished Oct 15 01:10:52 PM PDT 23
Peak memory 206432 kb
Host smart-642c7329-a938-4452-9bcd-66f9cb6502ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114847101 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3114847101
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.2581721404
Short name T344
Test name
Test status
Simulation time 28522343 ps
CPU time 0.85 seconds
Started Oct 15 01:10:59 PM PDT 23
Finished Oct 15 01:11:00 PM PDT 23
Peak memory 206360 kb
Host smart-7a6101c5-e6b6-4b6d-a9d7-3e436c0cfca0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581721404 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2581721404
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.2476862283
Short name T421
Test name
Test status
Simulation time 50888776 ps
CPU time 0.89 seconds
Started Oct 15 01:11:05 PM PDT 23
Finished Oct 15 01:11:06 PM PDT 23
Peak memory 206324 kb
Host smart-4de93584-7890-4b06-a793-769f945d9dde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476862283 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.2476862283
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.4090826862
Short name T219
Test name
Test status
Simulation time 24872900 ps
CPU time 1.21 seconds
Started Oct 15 01:11:01 PM PDT 23
Finished Oct 15 01:11:03 PM PDT 23
Peak memory 206396 kb
Host smart-e6a697cc-ff66-473f-ab90-6ed1eb5bb427
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090826862 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.4090826862
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2319343365
Short name T218
Test name
Test status
Simulation time 514055915 ps
CPU time 3.57 seconds
Started Oct 15 01:11:04 PM PDT 23
Finished Oct 15 01:11:08 PM PDT 23
Peak memory 206560 kb
Host smart-a2a5dc61-f571-471e-a7b5-56fcd619ad44
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319343365 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.2319343365
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3041110055
Short name T215
Test name
Test status
Simulation time 53448319 ps
CPU time 0.91 seconds
Started Oct 15 01:10:40 PM PDT 23
Finished Oct 15 01:10:43 PM PDT 23
Peak memory 206468 kb
Host smart-6cdf3f55-76d2-43c4-83f5-e15e59294f56
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041110055 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.3041110055
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3888564686
Short name T386
Test name
Test status
Simulation time 26308751 ps
CPU time 1.04 seconds
Started Oct 15 01:11:01 PM PDT 23
Finished Oct 15 01:11:03 PM PDT 23
Peak memory 214680 kb
Host smart-3d032ec2-9a19-4583-8867-c2a869f71e97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888564686 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.3888564686
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.3279328277
Short name T228
Test name
Test status
Simulation time 12718918 ps
CPU time 0.85 seconds
Started Oct 15 01:11:02 PM PDT 23
Finished Oct 15 01:11:04 PM PDT 23
Peak memory 206496 kb
Host smart-4765d3b1-c676-4973-bb86-bb47669a4db3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279328277 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.3279328277
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.266841307
Short name T353
Test name
Test status
Simulation time 45128952 ps
CPU time 0.83 seconds
Started Oct 15 01:10:42 PM PDT 23
Finished Oct 15 01:10:44 PM PDT 23
Peak memory 206484 kb
Host smart-b70a1dc1-9408-4aff-8017-cfa1d1ff4518
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266841307 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.266841307
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3410951037
Short name T381
Test name
Test status
Simulation time 40866733 ps
CPU time 1.02 seconds
Started Oct 15 01:10:45 PM PDT 23
Finished Oct 15 01:10:47 PM PDT 23
Peak memory 206660 kb
Host smart-69f8680d-695b-439a-948f-1f1c408da299
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410951037 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.3410951037
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.995135606
Short name T350
Test name
Test status
Simulation time 312522624 ps
CPU time 3.1 seconds
Started Oct 15 01:10:43 PM PDT 23
Finished Oct 15 01:10:47 PM PDT 23
Peak memory 214732 kb
Host smart-d7bb774b-d993-445c-b91b-49c97279a5e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995135606 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.995135606
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3837205126
Short name T283
Test name
Test status
Simulation time 117414627 ps
CPU time 2.81 seconds
Started Oct 15 01:10:39 PM PDT 23
Finished Oct 15 01:10:42 PM PDT 23
Peak memory 206684 kb
Host smart-9d2f2907-8800-4c8c-9055-3c0a2d075b52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837205126 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.3837205126
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.2748609242
Short name T378
Test name
Test status
Simulation time 17150085 ps
CPU time 0.84 seconds
Started Oct 15 01:11:00 PM PDT 23
Finished Oct 15 01:11:01 PM PDT 23
Peak memory 206464 kb
Host smart-83c68b61-2302-47b7-8080-ce8437997add
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748609242 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2748609242
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.321902656
Short name T349
Test name
Test status
Simulation time 34185662 ps
CPU time 0.76 seconds
Started Oct 15 01:10:57 PM PDT 23
Finished Oct 15 01:10:58 PM PDT 23
Peak memory 206172 kb
Host smart-2d36af4f-573a-401a-84eb-75ec757aa790
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321902656 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.321902656
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.3749546607
Short name T448
Test name
Test status
Simulation time 16091390 ps
CPU time 0.96 seconds
Started Oct 15 01:11:01 PM PDT 23
Finished Oct 15 01:11:03 PM PDT 23
Peak memory 206380 kb
Host smart-a29b7336-4ebb-4f33-99d0-b45d01080488
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749546607 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.3749546607
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.1129481012
Short name T365
Test name
Test status
Simulation time 54888846 ps
CPU time 0.87 seconds
Started Oct 15 01:10:44 PM PDT 23
Finished Oct 15 01:10:45 PM PDT 23
Peak memory 206428 kb
Host smart-92019ba1-afef-4ad0-a9b6-e90299eac7f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129481012 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.1129481012
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.4200528763
Short name T376
Test name
Test status
Simulation time 10966629 ps
CPU time 0.83 seconds
Started Oct 15 01:10:58 PM PDT 23
Finished Oct 15 01:10:59 PM PDT 23
Peak memory 206404 kb
Host smart-d717266f-4040-4f03-a495-a1caa2f7534b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200528763 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.4200528763
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.335659103
Short name T375
Test name
Test status
Simulation time 14987601 ps
CPU time 0.85 seconds
Started Oct 15 01:10:58 PM PDT 23
Finished Oct 15 01:10:59 PM PDT 23
Peak memory 206468 kb
Host smart-8ca9806f-8f4b-4803-80f1-24b16ffb2f3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335659103 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.335659103
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.3716088429
Short name T423
Test name
Test status
Simulation time 19812724 ps
CPU time 0.89 seconds
Started Oct 15 01:11:06 PM PDT 23
Finished Oct 15 01:11:07 PM PDT 23
Peak memory 206432 kb
Host smart-c38b8bd8-ccb5-48a8-8734-51b11c50803a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716088429 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3716088429
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.972354548
Short name T356
Test name
Test status
Simulation time 36503967 ps
CPU time 0.79 seconds
Started Oct 15 01:10:57 PM PDT 23
Finished Oct 15 01:10:58 PM PDT 23
Peak memory 206176 kb
Host smart-f6e48ee1-16de-43f1-8e5b-c34ef6b5c648
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972354548 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.972354548
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.2554001259
Short name T452
Test name
Test status
Simulation time 85856773 ps
CPU time 0.77 seconds
Started Oct 15 01:10:44 PM PDT 23
Finished Oct 15 01:10:45 PM PDT 23
Peak memory 206248 kb
Host smart-0677a991-cd16-4b40-8d18-9d0e8e31f94b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554001259 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.2554001259
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.1466756623
Short name T367
Test name
Test status
Simulation time 26090491 ps
CPU time 0.8 seconds
Started Oct 15 01:10:43 PM PDT 23
Finished Oct 15 01:10:44 PM PDT 23
Peak memory 206420 kb
Host smart-35ea12a5-3a20-4bf9-923e-dd5b03b41f2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466756623 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.1466756623
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.1989198557
Short name T221
Test name
Test status
Simulation time 54967858 ps
CPU time 1.2 seconds
Started Oct 15 01:11:09 PM PDT 23
Finished Oct 15 01:11:10 PM PDT 23
Peak memory 206504 kb
Host smart-78acd8a1-7580-4079-be4e-26924528d288
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989198557 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.1989198557
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2792349178
Short name T456
Test name
Test status
Simulation time 68944048 ps
CPU time 1.98 seconds
Started Oct 15 01:11:24 PM PDT 23
Finished Oct 15 01:11:27 PM PDT 23
Peak memory 206464 kb
Host smart-84a1d0dc-1199-4061-8f3f-30719856bbd6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792349178 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.2792349178
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1272720759
Short name T217
Test name
Test status
Simulation time 45900631 ps
CPU time 0.83 seconds
Started Oct 15 01:10:56 PM PDT 23
Finished Oct 15 01:10:57 PM PDT 23
Peak memory 206268 kb
Host smart-d11ce8fe-1124-42d5-b329-ea3d0b461273
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272720759 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.1272720759
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.805800977
Short name T380
Test name
Test status
Simulation time 75702897 ps
CPU time 1.14 seconds
Started Oct 15 01:11:50 PM PDT 23
Finished Oct 15 01:11:51 PM PDT 23
Peak memory 214828 kb
Host smart-275be730-06d9-41ad-869f-5ad7912989e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805800977 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.805800977
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.303969148
Short name T458
Test name
Test status
Simulation time 20487067 ps
CPU time 0.83 seconds
Started Oct 15 01:10:58 PM PDT 23
Finished Oct 15 01:10:59 PM PDT 23
Peak memory 206240 kb
Host smart-e8fb97d6-2a25-42e9-9618-0096597a4803
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303969148 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.303969148
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.496247416
Short name T417
Test name
Test status
Simulation time 16435670 ps
CPU time 0.85 seconds
Started Oct 15 01:11:05 PM PDT 23
Finished Oct 15 01:11:07 PM PDT 23
Peak memory 206456 kb
Host smart-3022afdb-4ce5-49b0-8646-7e637006dae4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496247416 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.496247416
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1974804629
Short name T368
Test name
Test status
Simulation time 107106490 ps
CPU time 1.33 seconds
Started Oct 15 01:11:05 PM PDT 23
Finished Oct 15 01:11:07 PM PDT 23
Peak memory 206472 kb
Host smart-338756b7-e562-4ff9-a87d-ad7492c8ae2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974804629 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.1974804629
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.1674656914
Short name T415
Test name
Test status
Simulation time 294146065 ps
CPU time 2.6 seconds
Started Oct 15 01:10:56 PM PDT 23
Finished Oct 15 01:10:59 PM PDT 23
Peak memory 214720 kb
Host smart-eab15028-567d-4a7a-ac16-12426e7d2551
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674656914 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.1674656914
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.675585334
Short name T382
Test name
Test status
Simulation time 41934093 ps
CPU time 0.83 seconds
Started Oct 15 01:10:44 PM PDT 23
Finished Oct 15 01:10:45 PM PDT 23
Peak memory 206404 kb
Host smart-7b3caca7-d12f-4124-a928-8d679e3bfead
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675585334 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.675585334
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.1284540660
Short name T405
Test name
Test status
Simulation time 26930748 ps
CPU time 0.87 seconds
Started Oct 15 01:10:59 PM PDT 23
Finished Oct 15 01:11:00 PM PDT 23
Peak memory 206456 kb
Host smart-3610a5f2-358f-43b5-8dfc-f6acb450581c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284540660 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1284540660
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.413877071
Short name T359
Test name
Test status
Simulation time 94956695 ps
CPU time 0.81 seconds
Started Oct 15 01:10:44 PM PDT 23
Finished Oct 15 01:10:46 PM PDT 23
Peak memory 206256 kb
Host smart-00fa6c60-eb71-44ba-9bf2-bf2151cb21d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413877071 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.413877071
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.3200329740
Short name T401
Test name
Test status
Simulation time 15396770 ps
CPU time 0.87 seconds
Started Oct 15 01:11:02 PM PDT 23
Finished Oct 15 01:11:03 PM PDT 23
Peak memory 206356 kb
Host smart-11047a69-c464-4fdc-8605-c0c39f2a1732
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200329740 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.3200329740
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.1784926729
Short name T384
Test name
Test status
Simulation time 28486065 ps
CPU time 0.88 seconds
Started Oct 15 01:11:01 PM PDT 23
Finished Oct 15 01:11:03 PM PDT 23
Peak memory 206384 kb
Host smart-0e14355e-c78d-49bb-8170-5555ac87396e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784926729 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.1784926729
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.1106841400
Short name T392
Test name
Test status
Simulation time 45812488 ps
CPU time 0.84 seconds
Started Oct 15 01:10:45 PM PDT 23
Finished Oct 15 01:10:47 PM PDT 23
Peak memory 206408 kb
Host smart-f6dc2613-b437-490d-9a24-3aed75d5ad84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106841400 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.1106841400
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.159485286
Short name T438
Test name
Test status
Simulation time 10778107 ps
CPU time 0.81 seconds
Started Oct 15 01:11:00 PM PDT 23
Finished Oct 15 01:11:01 PM PDT 23
Peak memory 206444 kb
Host smart-5a7fb56f-7c86-454b-88e9-460020baaafa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159485286 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.159485286
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.842444783
Short name T348
Test name
Test status
Simulation time 13882641 ps
CPU time 0.85 seconds
Started Oct 15 01:10:56 PM PDT 23
Finished Oct 15 01:10:57 PM PDT 23
Peak memory 206444 kb
Host smart-dec41bc7-7a4d-410a-9605-88f7af761bb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842444783 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.842444783
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.4029504906
Short name T414
Test name
Test status
Simulation time 71120164 ps
CPU time 0.72 seconds
Started Oct 15 01:10:45 PM PDT 23
Finished Oct 15 01:10:46 PM PDT 23
Peak memory 206256 kb
Host smart-e98af430-2263-4b58-a4df-9625b542858a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029504906 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.4029504906
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.3023400323
Short name T346
Test name
Test status
Simulation time 17092251 ps
CPU time 0.93 seconds
Started Oct 15 01:10:44 PM PDT 23
Finished Oct 15 01:10:50 PM PDT 23
Peak memory 206428 kb
Host smart-195022c8-054f-4820-a1b6-204b70b25dc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023400323 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.3023400323
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2828113390
Short name T387
Test name
Test status
Simulation time 321380498 ps
CPU time 1.15 seconds
Started Oct 15 01:10:37 PM PDT 23
Finished Oct 15 01:10:39 PM PDT 23
Peak memory 214788 kb
Host smart-964aa058-caff-4b15-9898-fcce8821930f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828113390 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.2828113390
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.340646803
Short name T464
Test name
Test status
Simulation time 43262271 ps
CPU time 0.86 seconds
Started Oct 15 01:11:29 PM PDT 23
Finished Oct 15 01:11:30 PM PDT 23
Peak memory 206576 kb
Host smart-964c0e39-d085-4cdf-916d-8f7020e57853
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340646803 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.340646803
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.849907508
Short name T442
Test name
Test status
Simulation time 61512706 ps
CPU time 0.84 seconds
Started Oct 15 01:11:20 PM PDT 23
Finished Oct 15 01:11:21 PM PDT 23
Peak memory 206300 kb
Host smart-eb035ad7-e580-4974-96d1-c8220130b4ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849907508 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.849907508
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1393049788
Short name T231
Test name
Test status
Simulation time 12778624 ps
CPU time 0.92 seconds
Started Oct 15 01:11:09 PM PDT 23
Finished Oct 15 01:11:10 PM PDT 23
Peak memory 206528 kb
Host smart-dc4f61ef-e369-49b5-843a-4776530402ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393049788 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.1393049788
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.381530636
Short name T364
Test name
Test status
Simulation time 39577942 ps
CPU time 1.47 seconds
Started Oct 15 01:11:24 PM PDT 23
Finished Oct 15 01:11:26 PM PDT 23
Peak memory 214788 kb
Host smart-c993e4e9-d79a-4642-860d-e416887258ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381530636 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.381530636
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2415922999
Short name T441
Test name
Test status
Simulation time 224528218 ps
CPU time 1.7 seconds
Started Oct 15 01:11:00 PM PDT 23
Finished Oct 15 01:11:02 PM PDT 23
Peak memory 206648 kb
Host smart-a598f479-c127-42ff-a45f-dc9f4ee6d6d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415922999 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2415922999
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3494238828
Short name T199
Test name
Test status
Simulation time 62554271 ps
CPU time 1.29 seconds
Started Oct 15 01:10:40 PM PDT 23
Finished Oct 15 01:10:43 PM PDT 23
Peak memory 214760 kb
Host smart-719b2f45-d6dc-48d3-967b-4aa6ce280389
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494238828 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.3494238828
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.496147910
Short name T212
Test name
Test status
Simulation time 82094383 ps
CPU time 0.84 seconds
Started Oct 15 01:11:00 PM PDT 23
Finished Oct 15 01:11:01 PM PDT 23
Peak memory 206580 kb
Host smart-dfdaaa6f-3e32-4791-a4c0-a01109f17524
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496147910 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.496147910
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3326435617
Short name T451
Test name
Test status
Simulation time 34937404 ps
CPU time 0.8 seconds
Started Oct 15 01:10:37 PM PDT 23
Finished Oct 15 01:10:39 PM PDT 23
Peak memory 206180 kb
Host smart-ec6e2a30-4051-4172-8f94-f82b96687724
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326435617 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3326435617
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.850923885
Short name T426
Test name
Test status
Simulation time 103181759 ps
CPU time 0.91 seconds
Started Oct 15 01:10:38 PM PDT 23
Finished Oct 15 01:10:39 PM PDT 23
Peak memory 206544 kb
Host smart-b6d2823e-1cef-423e-bfd3-40286f741e7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850923885 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_out
standing.850923885
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.1605558145
Short name T202
Test name
Test status
Simulation time 59014816 ps
CPU time 1.78 seconds
Started Oct 15 01:10:37 PM PDT 23
Finished Oct 15 01:10:40 PM PDT 23
Peak memory 214792 kb
Host smart-819256e8-7681-4a7e-9889-04d093a598ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605558145 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.1605558145
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2906205186
Short name T203
Test name
Test status
Simulation time 178012884 ps
CPU time 1.57 seconds
Started Oct 15 01:10:35 PM PDT 23
Finished Oct 15 01:10:37 PM PDT 23
Peak memory 206544 kb
Host smart-fb7a98da-fcd0-4c73-be00-0cb44a0a8b38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906205186 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.2906205186
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.646690757
Short name T198
Test name
Test status
Simulation time 54953669 ps
CPU time 1.06 seconds
Started Oct 15 01:10:32 PM PDT 23
Finished Oct 15 01:10:33 PM PDT 23
Peak memory 214760 kb
Host smart-4b635211-d105-4a98-a93e-225fd4659376
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646690757 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.646690757
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.177683485
Short name T447
Test name
Test status
Simulation time 25073116 ps
CPU time 0.83 seconds
Started Oct 15 01:10:36 PM PDT 23
Finished Oct 15 01:10:37 PM PDT 23
Peak memory 206476 kb
Host smart-3eb87dc3-30e7-4880-a17c-60d88e2ed0b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177683485 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.177683485
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.1352586895
Short name T383
Test name
Test status
Simulation time 13685355 ps
CPU time 0.84 seconds
Started Oct 15 01:10:40 PM PDT 23
Finished Oct 15 01:10:43 PM PDT 23
Peak memory 206340 kb
Host smart-7c1845c8-4e72-47a9-8fad-6bc4a4f570bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352586895 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.1352586895
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1173842278
Short name T435
Test name
Test status
Simulation time 35922982 ps
CPU time 1.01 seconds
Started Oct 15 01:10:45 PM PDT 23
Finished Oct 15 01:10:46 PM PDT 23
Peak memory 206552 kb
Host smart-7431e910-2b5b-46af-a836-ba175df53be7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173842278 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.1173842278
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.2855907290
Short name T197
Test name
Test status
Simulation time 135807966 ps
CPU time 4.27 seconds
Started Oct 15 01:10:37 PM PDT 23
Finished Oct 15 01:10:41 PM PDT 23
Peak memory 214692 kb
Host smart-569129a2-4a91-48e4-9787-f32a1da02fc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855907290 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2855907290
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.336772764
Short name T282
Test name
Test status
Simulation time 115459008 ps
CPU time 2.7 seconds
Started Oct 15 01:10:39 PM PDT 23
Finished Oct 15 01:10:44 PM PDT 23
Peak memory 206524 kb
Host smart-b76bbd37-edfd-4750-a0d6-c41c24ca9624
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336772764 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.336772764
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3710880487
Short name T377
Test name
Test status
Simulation time 30619136 ps
CPU time 0.98 seconds
Started Oct 15 01:10:39 PM PDT 23
Finished Oct 15 01:10:40 PM PDT 23
Peak memory 206572 kb
Host smart-55e6f8aa-d9c3-4a40-a01b-ace4ea944362
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710880487 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3710880487
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.1538578401
Short name T455
Test name
Test status
Simulation time 16230636 ps
CPU time 0.89 seconds
Started Oct 15 01:10:34 PM PDT 23
Finished Oct 15 01:10:36 PM PDT 23
Peak memory 206652 kb
Host smart-9dc0a66a-c9fe-4f9f-9412-7ac253e3cd27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538578401 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.1538578401
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.280289806
Short name T395
Test name
Test status
Simulation time 15879736 ps
CPU time 0.86 seconds
Started Oct 15 01:10:42 PM PDT 23
Finished Oct 15 01:10:43 PM PDT 23
Peak memory 206416 kb
Host smart-f89419d7-1302-4152-95ce-6c192313aaec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280289806 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.280289806
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.4085478275
Short name T399
Test name
Test status
Simulation time 59307826 ps
CPU time 1.3 seconds
Started Oct 15 01:10:37 PM PDT 23
Finished Oct 15 01:10:39 PM PDT 23
Peak memory 206516 kb
Host smart-3d6ed710-e40a-4033-b209-cfab02cc2a6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085478275 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.4085478275
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.3036841743
Short name T422
Test name
Test status
Simulation time 46518050 ps
CPU time 3.22 seconds
Started Oct 15 01:10:41 PM PDT 23
Finished Oct 15 01:10:46 PM PDT 23
Peak memory 214804 kb
Host smart-f1056dc1-f3c3-4a2b-a841-e008315845d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036841743 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.3036841743
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1014068166
Short name T394
Test name
Test status
Simulation time 253877907 ps
CPU time 2.18 seconds
Started Oct 15 01:10:47 PM PDT 23
Finished Oct 15 01:10:50 PM PDT 23
Peak memory 206464 kb
Host smart-d839f78b-de24-4781-bc9e-488b381ea27e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014068166 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.1014068166
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.18320899
Short name T214
Test name
Test status
Simulation time 26278560 ps
CPU time 1.72 seconds
Started Oct 15 01:10:35 PM PDT 23
Finished Oct 15 01:10:37 PM PDT 23
Peak memory 214776 kb
Host smart-b8ebdc9b-cef1-4fdb-a875-4bbd3d10dcd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18320899 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.18320899
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.3632721686
Short name T222
Test name
Test status
Simulation time 11368719 ps
CPU time 0.81 seconds
Started Oct 15 01:11:01 PM PDT 23
Finished Oct 15 01:11:02 PM PDT 23
Peak memory 206460 kb
Host smart-96585af6-07aa-438f-b9d1-d40c088aade3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632721686 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3632721686
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.3140834648
Short name T374
Test name
Test status
Simulation time 57680127 ps
CPU time 0.88 seconds
Started Oct 15 01:10:34 PM PDT 23
Finished Oct 15 01:10:36 PM PDT 23
Peak memory 206396 kb
Host smart-d7819e32-e0df-4197-aa2c-a226876d4647
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140834648 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.3140834648
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3584018736
Short name T443
Test name
Test status
Simulation time 12836157 ps
CPU time 0.95 seconds
Started Oct 15 01:10:40 PM PDT 23
Finished Oct 15 01:10:43 PM PDT 23
Peak memory 206488 kb
Host smart-eb777506-b42f-45a4-82cc-5c20809c632b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584018736 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.3584018736
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.391688693
Short name T430
Test name
Test status
Simulation time 31548296 ps
CPU time 2.02 seconds
Started Oct 15 01:10:32 PM PDT 23
Finished Oct 15 01:10:34 PM PDT 23
Peak memory 214864 kb
Host smart-85d7d25a-140b-45ef-94d4-087019d5d371
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391688693 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.391688693
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2270505105
Short name T408
Test name
Test status
Simulation time 267688856 ps
CPU time 2.52 seconds
Started Oct 15 01:10:44 PM PDT 23
Finished Oct 15 01:10:47 PM PDT 23
Peak memory 206588 kb
Host smart-57b0c1a9-57f9-4a5e-b16b-02643e058f77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270505105 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.2270505105
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.4121605342
Short name T584
Test name
Test status
Simulation time 19530906 ps
CPU time 0.98 seconds
Started Oct 15 01:30:59 PM PDT 23
Finished Oct 15 01:31:01 PM PDT 23
Peak memory 205900 kb
Host smart-b32f51dd-16fa-44ed-94b4-6644b905445d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121605342 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.4121605342
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.2450017079
Short name T317
Test name
Test status
Simulation time 14000438 ps
CPU time 0.83 seconds
Started Oct 15 01:31:14 PM PDT 23
Finished Oct 15 01:31:15 PM PDT 23
Peak memory 205292 kb
Host smart-5f5d72b1-72f6-49c2-b3a1-9f6637827400
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450017079 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2450017079
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.2949572107
Short name T517
Test name
Test status
Simulation time 59327324 ps
CPU time 0.83 seconds
Started Oct 15 01:31:09 PM PDT 23
Finished Oct 15 01:31:11 PM PDT 23
Peak memory 215092 kb
Host smart-640d83eb-1721-4115-857e-bff38bb115fc
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949572107 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.2949572107
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.286967021
Short name T105
Test name
Test status
Simulation time 77107285 ps
CPU time 0.92 seconds
Started Oct 15 01:31:29 PM PDT 23
Finished Oct 15 01:31:31 PM PDT 23
Peak memory 215140 kb
Host smart-788a2996-b6e0-458c-ad3d-95338f6837b4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286967021 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_dis
able_auto_req_mode.286967021
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.640821294
Short name T168
Test name
Test status
Simulation time 35113020 ps
CPU time 0.87 seconds
Started Oct 15 01:31:02 PM PDT 23
Finished Oct 15 01:31:03 PM PDT 23
Peak memory 215496 kb
Host smart-bbb4ccf0-1f2c-4cf3-966d-dfc90c9b031c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640821294 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.640821294
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.3794863017
Short name T708
Test name
Test status
Simulation time 41049079 ps
CPU time 0.89 seconds
Started Oct 15 01:31:14 PM PDT 23
Finished Oct 15 01:31:15 PM PDT 23
Peak memory 205712 kb
Host smart-b3a0bfd3-2b06-4337-8032-edecb0db418a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794863017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.3794863017
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.1785067458
Short name T613
Test name
Test status
Simulation time 25774147 ps
CPU time 0.86 seconds
Started Oct 15 01:31:29 PM PDT 23
Finished Oct 15 01:31:30 PM PDT 23
Peak memory 215168 kb
Host smart-12cd3276-5d54-4036-a950-c11fb3f8b1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785067458 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.1785067458
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_smoke.575108143
Short name T619
Test name
Test status
Simulation time 12297774 ps
CPU time 0.88 seconds
Started Oct 15 01:31:11 PM PDT 23
Finished Oct 15 01:31:13 PM PDT 23
Peak memory 205600 kb
Host smart-0837067a-3aa9-4115-9535-ed43b910d14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575108143 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.575108143
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.3965413009
Short name T93
Test name
Test status
Simulation time 15805541021 ps
CPU time 324.87 seconds
Started Oct 15 01:31:29 PM PDT 23
Finished Oct 15 01:36:55 PM PDT 23
Peak memory 216116 kb
Host smart-76833b40-d218-43b6-819a-29657219eee6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965413009 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.3965413009
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.1351853206
Short name T256
Test name
Test status
Simulation time 60678163 ps
CPU time 0.91 seconds
Started Oct 15 01:31:33 PM PDT 23
Finished Oct 15 01:31:36 PM PDT 23
Peak memory 205972 kb
Host smart-3d27ef16-0305-4428-b5ca-f10f1930e3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351853206 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1351853206
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.1763792848
Short name T638
Test name
Test status
Simulation time 28103248 ps
CPU time 0.93 seconds
Started Oct 15 01:31:40 PM PDT 23
Finished Oct 15 01:31:42 PM PDT 23
Peak memory 205260 kb
Host smart-b5d35ad8-cab8-4e8a-a44d-85b98d7d1cc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763792848 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1763792848
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.2208254029
Short name T248
Test name
Test status
Simulation time 15222656 ps
CPU time 0.9 seconds
Started Oct 15 01:31:42 PM PDT 23
Finished Oct 15 01:31:43 PM PDT 23
Peak memory 215224 kb
Host smart-c86bdee6-b4fd-42f1-a016-7be138cff5d1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208254029 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.2208254029
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.1952129558
Short name T250
Test name
Test status
Simulation time 25413965 ps
CPU time 1.04 seconds
Started Oct 15 01:31:36 PM PDT 23
Finished Oct 15 01:31:38 PM PDT 23
Peak memory 229284 kb
Host smart-6f9652da-5474-4726-819d-54f2d4dd3a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952129558 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.1952129558
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.3832830143
Short name T123
Test name
Test status
Simulation time 97045220 ps
CPU time 1.21 seconds
Started Oct 15 01:31:34 PM PDT 23
Finished Oct 15 01:31:36 PM PDT 23
Peak memory 205616 kb
Host smart-89aa4016-2ee0-4eec-a76f-b7eff026c903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832830143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.3832830143
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.2570933277
Short name T124
Test name
Test status
Simulation time 46674047 ps
CPU time 0.79 seconds
Started Oct 15 01:31:34 PM PDT 23
Finished Oct 15 01:31:36 PM PDT 23
Peak memory 215264 kb
Host smart-70cb1284-f5fa-46b2-ae95-3ca9b6a7afa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570933277 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.2570933277
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.3554351960
Short name T597
Test name
Test status
Simulation time 14800815 ps
CPU time 0.9 seconds
Started Oct 15 01:31:33 PM PDT 23
Finished Oct 15 01:31:36 PM PDT 23
Peak memory 205744 kb
Host smart-726ab3bc-f0fb-42dc-a6e6-24c67c5ef01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554351960 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.3554351960
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.53281798
Short name T61
Test name
Test status
Simulation time 1001103482 ps
CPU time 6.16 seconds
Started Oct 15 01:31:13 PM PDT 23
Finished Oct 15 01:31:20 PM PDT 23
Peak memory 235148 kb
Host smart-09d9f9c5-e79a-466f-b5f0-f9491b8983eb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53281798 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.53281798
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.3736380060
Short name T598
Test name
Test status
Simulation time 67458371 ps
CPU time 0.87 seconds
Started Oct 15 01:31:17 PM PDT 23
Finished Oct 15 01:31:18 PM PDT 23
Peak memory 205584 kb
Host smart-123d17aa-4415-43b8-b635-0c6108f3a553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736380060 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.3736380060
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.2822329830
Short name T620
Test name
Test status
Simulation time 624674389 ps
CPU time 3.8 seconds
Started Oct 15 01:31:02 PM PDT 23
Finished Oct 15 01:31:06 PM PDT 23
Peak memory 206840 kb
Host smart-fa20897b-172b-4d5e-8c69-c67c62027f4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822329830 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.2822329830
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.1691445978
Short name T531
Test name
Test status
Simulation time 74611642795 ps
CPU time 1676.13 seconds
Started Oct 15 01:31:16 PM PDT 23
Finished Oct 15 01:59:13 PM PDT 23
Peak memory 219164 kb
Host smart-12c53afb-5a09-4635-95ab-ad6bade5b147
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691445978 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.1691445978
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert_test.4086332505
Short name T477
Test name
Test status
Simulation time 19063021 ps
CPU time 1.01 seconds
Started Oct 15 01:31:14 PM PDT 23
Finished Oct 15 01:31:15 PM PDT 23
Peak memory 205404 kb
Host smart-8c7b8a0e-028a-44ca-b02b-edebb2ba579b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086332505 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.4086332505
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.76737805
Short name T177
Test name
Test status
Simulation time 28070990 ps
CPU time 0.77 seconds
Started Oct 15 01:31:05 PM PDT 23
Finished Oct 15 01:31:06 PM PDT 23
Peak memory 215080 kb
Host smart-e9ec60b5-f570-4c1d-bbf9-a64765af569a
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76737805 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.76737805
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_err.1917667251
Short name T694
Test name
Test status
Simulation time 78879889 ps
CPU time 0.92 seconds
Started Oct 15 01:31:14 PM PDT 23
Finished Oct 15 01:31:15 PM PDT 23
Peak memory 222072 kb
Host smart-0afc523c-7355-4cbd-9400-9fa7ffb5dedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917667251 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.1917667251
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_intr.3444045971
Short name T134
Test name
Test status
Simulation time 52369859 ps
CPU time 0.8 seconds
Started Oct 15 01:30:59 PM PDT 23
Finished Oct 15 01:31:01 PM PDT 23
Peak memory 215280 kb
Host smart-8d8242fc-244a-4689-963c-64427daa6379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444045971 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.3444045971
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.1743347619
Short name T591
Test name
Test status
Simulation time 12137606 ps
CPU time 0.83 seconds
Started Oct 15 01:31:17 PM PDT 23
Finished Oct 15 01:31:19 PM PDT 23
Peak memory 205416 kb
Host smart-a34d0688-2075-48ed-bddb-02796469c621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743347619 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1743347619
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.885514555
Short name T599
Test name
Test status
Simulation time 456762326 ps
CPU time 3.1 seconds
Started Oct 15 01:31:08 PM PDT 23
Finished Oct 15 01:31:11 PM PDT 23
Peak memory 206768 kb
Host smart-05cca1ad-830a-4a7e-95ef-9863901a7b9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885514555 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.885514555
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.892620036
Short name T625
Test name
Test status
Simulation time 207012497300 ps
CPU time 1089.28 seconds
Started Oct 15 01:31:03 PM PDT 23
Finished Oct 15 01:49:13 PM PDT 23
Peak memory 217000 kb
Host smart-dacdd25d-675b-4fd4-8e54-c55cc9580806
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892620036 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.892620036
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.edn_disable.3661393183
Short name T103
Test name
Test status
Simulation time 12119904 ps
CPU time 0.87 seconds
Started Oct 15 01:31:07 PM PDT 23
Finished Oct 15 01:31:08 PM PDT 23
Peak memory 215008 kb
Host smart-a4bc955f-c4e1-46ab-8d8c-42c871b01109
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661393183 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3661393183
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.2347800615
Short name T656
Test name
Test status
Simulation time 61013317 ps
CPU time 0.95 seconds
Started Oct 15 01:31:03 PM PDT 23
Finished Oct 15 01:31:04 PM PDT 23
Peak memory 215220 kb
Host smart-2bf3a98f-f5fe-43b3-95d8-b69a4c45e529
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347800615 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.2347800615
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.3365365653
Short name T236
Test name
Test status
Simulation time 52009618 ps
CPU time 0.97 seconds
Started Oct 15 01:31:02 PM PDT 23
Finished Oct 15 01:31:04 PM PDT 23
Peak memory 215364 kb
Host smart-49f5f94b-bd4d-43c6-b617-e3e522fb2179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365365653 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.3365365653
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.459404008
Short name T682
Test name
Test status
Simulation time 70547600 ps
CPU time 1.02 seconds
Started Oct 15 01:31:01 PM PDT 23
Finished Oct 15 01:31:03 PM PDT 23
Peak memory 205664 kb
Host smart-f4371af9-75de-41f3-b9ff-9fd1eeedd30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459404008 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.459404008
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.653549391
Short name T663
Test name
Test status
Simulation time 24345262 ps
CPU time 0.89 seconds
Started Oct 15 01:31:23 PM PDT 23
Finished Oct 15 01:31:25 PM PDT 23
Peak memory 215344 kb
Host smart-84428a12-7bd7-48b8-b028-2cab1f36f093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653549391 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.653549391
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.1313132379
Short name T610
Test name
Test status
Simulation time 11778829 ps
CPU time 0.86 seconds
Started Oct 15 01:31:12 PM PDT 23
Finished Oct 15 01:31:13 PM PDT 23
Peak memory 205504 kb
Host smart-16dcad24-6875-4b0a-aeaf-36fef92356ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313132379 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.1313132379
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.626904434
Short name T204
Test name
Test status
Simulation time 34684800 ps
CPU time 0.93 seconds
Started Oct 15 01:31:00 PM PDT 23
Finished Oct 15 01:31:01 PM PDT 23
Peak memory 205648 kb
Host smart-3401bbcc-21db-4c3f-b4bd-c5e851f136ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626904434 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.626904434
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.3942211485
Short name T562
Test name
Test status
Simulation time 111971689725 ps
CPU time 2572.52 seconds
Started Oct 15 01:31:14 PM PDT 23
Finished Oct 15 02:14:07 PM PDT 23
Peak memory 224236 kb
Host smart-4b83f482-dbe6-4617-9423-22192dcfee17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942211485 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.3942211485
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.edn_alert.128442758
Short name T301
Test name
Test status
Simulation time 62508157 ps
CPU time 0.91 seconds
Started Oct 15 01:31:04 PM PDT 23
Finished Oct 15 01:31:05 PM PDT 23
Peak memory 206104 kb
Host smart-a6aff4ba-46bd-4e1a-b7fa-14cdfe1c7e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128442758 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.128442758
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.2048309568
Short name T500
Test name
Test status
Simulation time 143249625 ps
CPU time 0.85 seconds
Started Oct 15 01:31:14 PM PDT 23
Finished Oct 15 01:31:15 PM PDT 23
Peak memory 205424 kb
Host smart-1e6d42df-e79b-42b9-9ac6-379befac6638
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048309568 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2048309568
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.2216732063
Short name T77
Test name
Test status
Simulation time 11076888 ps
CPU time 0.9 seconds
Started Oct 15 01:31:00 PM PDT 23
Finished Oct 15 01:31:01 PM PDT 23
Peak memory 214972 kb
Host smart-ce1d150c-1f5d-4095-951a-86df579a01f6
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216732063 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.2216732063
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.3932291860
Short name T284
Test name
Test status
Simulation time 23606909 ps
CPU time 1 seconds
Started Oct 15 01:31:11 PM PDT 23
Finished Oct 15 01:31:13 PM PDT 23
Peak memory 215244 kb
Host smart-62464abf-eff6-4c35-8a5b-96bfe1ad8ce5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932291860 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.3932291860
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.2082923951
Short name T159
Test name
Test status
Simulation time 19359723 ps
CPU time 1.15 seconds
Started Oct 15 01:31:26 PM PDT 23
Finished Oct 15 01:31:29 PM PDT 23
Peak memory 229644 kb
Host smart-3714d60f-be74-4142-b1a0-1c0a9cd8974b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082923951 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.2082923951
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.1204283319
Short name T112
Test name
Test status
Simulation time 76260544 ps
CPU time 1.36 seconds
Started Oct 15 01:31:19 PM PDT 23
Finished Oct 15 01:31:21 PM PDT 23
Peak memory 205740 kb
Host smart-025c8b69-4157-456c-bb0e-c44b930927d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204283319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.1204283319
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.4107455459
Short name T499
Test name
Test status
Simulation time 26950399 ps
CPU time 0.99 seconds
Started Oct 15 01:30:59 PM PDT 23
Finished Oct 15 01:31:00 PM PDT 23
Peak memory 222232 kb
Host smart-05d58727-502c-4570-bc42-acdbbe05099f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107455459 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.4107455459
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.186015122
Short name T543
Test name
Test status
Simulation time 50031741 ps
CPU time 0.87 seconds
Started Oct 15 01:31:15 PM PDT 23
Finished Oct 15 01:31:16 PM PDT 23
Peak memory 205600 kb
Host smart-3f57cde0-60f9-442b-ae68-83b8eef5bd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186015122 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.186015122
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.2654125224
Short name T653
Test name
Test status
Simulation time 140635746 ps
CPU time 1.32 seconds
Started Oct 15 01:31:16 PM PDT 23
Finished Oct 15 01:31:17 PM PDT 23
Peak memory 206020 kb
Host smart-37131416-4286-4c2a-a3c9-3aa528545b3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654125224 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.2654125224
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.1089773273
Short name T494
Test name
Test status
Simulation time 151159607882 ps
CPU time 1228.57 seconds
Started Oct 15 01:31:19 PM PDT 23
Finished Oct 15 01:51:48 PM PDT 23
Peak memory 217704 kb
Host smart-ec68cd91-2888-4e74-ba7a-7aca7a6c9db6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089773273 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.1089773273
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.edn_alert_test.1877707737
Short name T313
Test name
Test status
Simulation time 14676917 ps
CPU time 0.88 seconds
Started Oct 15 01:31:33 PM PDT 23
Finished Oct 15 01:31:36 PM PDT 23
Peak memory 205380 kb
Host smart-70744a93-999e-4a05-bce1-f9ec86ecfe52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877707737 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.1877707737
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_err.3810268221
Short name T253
Test name
Test status
Simulation time 22166691 ps
CPU time 0.99 seconds
Started Oct 15 01:31:05 PM PDT 23
Finished Oct 15 01:31:06 PM PDT 23
Peak memory 222292 kb
Host smart-83aac456-a776-4fe6-b4ea-1d2cfd393ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810268221 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.3810268221
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.218700904
Short name T88
Test name
Test status
Simulation time 43902193 ps
CPU time 1.08 seconds
Started Oct 15 01:31:26 PM PDT 23
Finished Oct 15 01:31:28 PM PDT 23
Peak memory 205976 kb
Host smart-d9e67ea4-bd24-4aa1-a612-7dba83072fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218700904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.218700904
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.1576870283
Short name T52
Test name
Test status
Simulation time 39605279 ps
CPU time 0.85 seconds
Started Oct 15 01:31:03 PM PDT 23
Finished Oct 15 01:31:05 PM PDT 23
Peak memory 215096 kb
Host smart-2ed1f053-eda0-410c-b166-657952ca63c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576870283 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.1576870283
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.1271916614
Short name T687
Test name
Test status
Simulation time 15129752 ps
CPU time 0.92 seconds
Started Oct 15 01:30:59 PM PDT 23
Finished Oct 15 01:31:01 PM PDT 23
Peak memory 205628 kb
Host smart-ca8d97d2-e8f4-41c2-99d6-b4ce88cf3d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271916614 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.1271916614
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.2450427695
Short name T569
Test name
Test status
Simulation time 253567390 ps
CPU time 2.69 seconds
Started Oct 15 01:31:16 PM PDT 23
Finished Oct 15 01:31:19 PM PDT 23
Peak memory 206700 kb
Host smart-2dfe014d-444d-4546-8aa0-57d5553bdc96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450427695 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.2450427695
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.4008402511
Short name T192
Test name
Test status
Simulation time 140636992835 ps
CPU time 2402.25 seconds
Started Oct 15 01:31:01 PM PDT 23
Finished Oct 15 02:11:05 PM PDT 23
Peak memory 225848 kb
Host smart-eb7b1303-ec64-4cdd-b364-605e5dcc1cfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008402511 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.4008402511
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.edn_alert.37057831
Short name T290
Test name
Test status
Simulation time 62132777 ps
CPU time 0.92 seconds
Started Oct 15 01:31:16 PM PDT 23
Finished Oct 15 01:31:18 PM PDT 23
Peak memory 205928 kb
Host smart-5b0ea69d-d134-449d-979e-e162c9798411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37057831 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.37057831
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.127161542
Short name T467
Test name
Test status
Simulation time 32167173 ps
CPU time 0.84 seconds
Started Oct 15 01:31:32 PM PDT 23
Finished Oct 15 01:31:33 PM PDT 23
Peak memory 205964 kb
Host smart-09968980-e4f8-48e6-bb22-b078d2e33d24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127161542 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.127161542
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.2903138023
Short name T145
Test name
Test status
Simulation time 19579192 ps
CPU time 0.82 seconds
Started Oct 15 01:31:28 PM PDT 23
Finished Oct 15 01:31:30 PM PDT 23
Peak memory 215092 kb
Host smart-8024af30-a2a2-430c-b012-c9a84988c0e6
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903138023 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.2903138023
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.1836766991
Short name T73
Test name
Test status
Simulation time 33310756 ps
CPU time 0.93 seconds
Started Oct 15 01:31:21 PM PDT 23
Finished Oct 15 01:31:22 PM PDT 23
Peak memory 215188 kb
Host smart-334e0a92-36b3-4fe3-b39d-60cda23acdfd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836766991 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.1836766991
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.3724032486
Short name T45
Test name
Test status
Simulation time 19917094 ps
CPU time 1.17 seconds
Started Oct 15 01:31:29 PM PDT 23
Finished Oct 15 01:31:31 PM PDT 23
Peak memory 229396 kb
Host smart-336d701e-c353-4363-b0c2-bcd82e2e95d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724032486 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.3724032486
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_intr.4105415521
Short name T525
Test name
Test status
Simulation time 20053480 ps
CPU time 0.98 seconds
Started Oct 15 01:31:00 PM PDT 23
Finished Oct 15 01:31:02 PM PDT 23
Peak memory 215412 kb
Host smart-79edbd3a-1ecb-4ac2-b1c6-98e37d60f0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105415521 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.4105415521
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.1914352791
Short name T557
Test name
Test status
Simulation time 13513104 ps
CPU time 0.86 seconds
Started Oct 15 01:31:01 PM PDT 23
Finished Oct 15 01:31:02 PM PDT 23
Peak memory 205564 kb
Host smart-55bef26d-aa8b-46e6-9245-0259e1a814d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914352791 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.1914352791
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.1280479781
Short name T537
Test name
Test status
Simulation time 404546546906 ps
CPU time 1909.46 seconds
Started Oct 15 01:31:03 PM PDT 23
Finished Oct 15 02:02:53 PM PDT 23
Peak memory 223716 kb
Host smart-ff92354f-f2a9-47d2-90e7-bdb11127d6ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280479781 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.1280479781
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.edn_alert.1003846641
Short name T76
Test name
Test status
Simulation time 20446797 ps
CPU time 0.97 seconds
Started Oct 15 01:31:07 PM PDT 23
Finished Oct 15 01:31:08 PM PDT 23
Peak memory 206756 kb
Host smart-87c95bec-c3eb-4f9d-93e5-5a262a3f5e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003846641 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.1003846641
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.1083003680
Short name T601
Test name
Test status
Simulation time 55842947 ps
CPU time 0.97 seconds
Started Oct 15 01:31:17 PM PDT 23
Finished Oct 15 01:31:18 PM PDT 23
Peak memory 205516 kb
Host smart-0f21670f-170a-4183-9626-938339dc6c1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083003680 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.1083003680
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_err.2870056168
Short name T697
Test name
Test status
Simulation time 86527143 ps
CPU time 1.07 seconds
Started Oct 15 01:31:19 PM PDT 23
Finished Oct 15 01:31:21 PM PDT 23
Peak memory 222836 kb
Host smart-e996f8cc-f325-4001-b965-89d683edc5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870056168 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.2870056168
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_intr.3668791570
Short name T127
Test name
Test status
Simulation time 33091735 ps
CPU time 0.86 seconds
Started Oct 15 01:31:20 PM PDT 23
Finished Oct 15 01:31:21 PM PDT 23
Peak memory 215252 kb
Host smart-8da3afa4-e9e3-4708-8159-14823d9090fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668791570 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.3668791570
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.1940426497
Short name T507
Test name
Test status
Simulation time 39647482 ps
CPU time 0.78 seconds
Started Oct 15 01:31:15 PM PDT 23
Finished Oct 15 01:31:16 PM PDT 23
Peak memory 205384 kb
Host smart-06dc74b8-69a2-4696-abee-04facef8b3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940426497 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.1940426497
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.3908566079
Short name T470
Test name
Test status
Simulation time 173700454 ps
CPU time 3.46 seconds
Started Oct 15 01:31:18 PM PDT 23
Finished Oct 15 01:31:22 PM PDT 23
Peak memory 206480 kb
Host smart-9767d55a-00bc-4b52-9866-7c43c3ed231c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908566079 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.3908566079
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_alert.3114657371
Short name T588
Test name
Test status
Simulation time 18010086 ps
CPU time 1.05 seconds
Started Oct 15 01:31:20 PM PDT 23
Finished Oct 15 01:31:22 PM PDT 23
Peak memory 206376 kb
Host smart-caf9536a-7845-4911-a67a-76979269d5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114657371 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.3114657371
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.331451778
Short name T681
Test name
Test status
Simulation time 28038080 ps
CPU time 0.88 seconds
Started Oct 15 01:31:30 PM PDT 23
Finished Oct 15 01:31:31 PM PDT 23
Peak memory 205908 kb
Host smart-3b263a4b-da00-4639-aa67-0e64221df013
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331451778 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.331451778
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.277974606
Short name T96
Test name
Test status
Simulation time 35138688 ps
CPU time 0.82 seconds
Started Oct 15 01:31:16 PM PDT 23
Finished Oct 15 01:31:18 PM PDT 23
Peak memory 215036 kb
Host smart-a799f7db-15be-4dc6-8722-a0dacaa8f350
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277974606 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.277974606
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.2482429907
Short name T161
Test name
Test status
Simulation time 43907647 ps
CPU time 0.99 seconds
Started Oct 15 01:31:30 PM PDT 23
Finished Oct 15 01:31:32 PM PDT 23
Peak memory 215244 kb
Host smart-3322b3a7-e57f-45b5-8263-96acb4c0c0a0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482429907 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.2482429907
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.537854086
Short name T706
Test name
Test status
Simulation time 19003488 ps
CPU time 1.11 seconds
Started Oct 15 01:31:18 PM PDT 23
Finished Oct 15 01:31:19 PM PDT 23
Peak memory 222796 kb
Host smart-6e80cdd9-dc3e-4d87-b936-aab8e2c1177f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537854086 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.537854086
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.1399964778
Short name T42
Test name
Test status
Simulation time 23429377 ps
CPU time 1.3 seconds
Started Oct 15 01:31:32 PM PDT 23
Finished Oct 15 01:31:33 PM PDT 23
Peak memory 206360 kb
Host smart-3201804a-27be-42a0-9b9b-0b03f1f4044a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399964778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.1399964778
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.2794546893
Short name T129
Test name
Test status
Simulation time 24112682 ps
CPU time 0.83 seconds
Started Oct 15 01:31:00 PM PDT 23
Finished Oct 15 01:31:01 PM PDT 23
Peak memory 215364 kb
Host smart-eac54a41-eb66-4911-a66e-6a7c0165e5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794546893 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.2794546893
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.344716099
Short name T336
Test name
Test status
Simulation time 15109156 ps
CPU time 0.92 seconds
Started Oct 15 01:31:00 PM PDT 23
Finished Oct 15 01:31:01 PM PDT 23
Peak memory 205812 kb
Host smart-c6447646-c32e-49d3-b114-c3e5b52aaf3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344716099 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.344716099
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.1968614213
Short name T137
Test name
Test status
Simulation time 227681603 ps
CPU time 2.58 seconds
Started Oct 15 01:31:15 PM PDT 23
Finished Oct 15 01:31:19 PM PDT 23
Peak memory 206512 kb
Host smart-d39db26d-5ae0-4fbf-8718-ce3212d7341c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968614213 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.1968614213
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.1019654366
Short name T26
Test name
Test status
Simulation time 148583440340 ps
CPU time 1696.83 seconds
Started Oct 15 01:31:16 PM PDT 23
Finished Oct 15 01:59:33 PM PDT 23
Peak memory 220012 kb
Host smart-835c5848-8e65-425f-b1c1-3889e6850d4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019654366 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.1019654366
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.edn_alert_test.1274827790
Short name T329
Test name
Test status
Simulation time 77025431 ps
CPU time 0.86 seconds
Started Oct 15 01:31:38 PM PDT 23
Finished Oct 15 01:31:40 PM PDT 23
Peak memory 205380 kb
Host smart-60bedb5e-5715-41cb-9715-e65b88fba017
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274827790 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.1274827790
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_err.836578611
Short name T167
Test name
Test status
Simulation time 33465851 ps
CPU time 0.97 seconds
Started Oct 15 01:31:15 PM PDT 23
Finished Oct 15 01:31:16 PM PDT 23
Peak memory 215396 kb
Host smart-c2426f00-b08c-463a-9608-958bdf1fa23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836578611 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.836578611
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_intr.792646912
Short name T481
Test name
Test status
Simulation time 52507913 ps
CPU time 0.81 seconds
Started Oct 15 01:31:30 PM PDT 23
Finished Oct 15 01:31:32 PM PDT 23
Peak memory 215208 kb
Host smart-b821bca6-2188-4449-b064-69a363d79ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792646912 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.792646912
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.460659610
Short name T705
Test name
Test status
Simulation time 11921945 ps
CPU time 0.86 seconds
Started Oct 15 01:31:29 PM PDT 23
Finished Oct 15 01:31:31 PM PDT 23
Peak memory 205700 kb
Host smart-6e0ff916-bf8d-4dec-96ea-c5e2e4273249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460659610 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.460659610
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.975386204
Short name T72
Test name
Test status
Simulation time 1559303600 ps
CPU time 3.17 seconds
Started Oct 15 01:31:30 PM PDT 23
Finished Oct 15 01:31:33 PM PDT 23
Peak memory 206708 kb
Host smart-92c3aec7-5228-40e7-8b32-2d54ff518103
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975386204 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.975386204
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.1153297891
Short name T553
Test name
Test status
Simulation time 56570652925 ps
CPU time 353.31 seconds
Started Oct 15 01:31:30 PM PDT 23
Finished Oct 15 01:37:24 PM PDT 23
Peak memory 216396 kb
Host smart-2d7adbce-6544-4971-a0ca-89852d76491d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153297891 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.1153297891
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.edn_alert_test.3440731018
Short name T561
Test name
Test status
Simulation time 17965871 ps
CPU time 0.91 seconds
Started Oct 15 01:31:34 PM PDT 23
Finished Oct 15 01:31:36 PM PDT 23
Peak memory 205424 kb
Host smart-2bdc7048-6593-48c2-ac7f-3a247c088418
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440731018 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.3440731018
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.3424369869
Short name T140
Test name
Test status
Simulation time 30121116 ps
CPU time 1.09 seconds
Started Oct 15 01:31:23 PM PDT 23
Finished Oct 15 01:31:24 PM PDT 23
Peak memory 215332 kb
Host smart-471435df-0209-4c8a-8367-29cd5be5febb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424369869 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.3424369869
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.4248077027
Short name T155
Test name
Test status
Simulation time 24713494 ps
CPU time 1.13 seconds
Started Oct 15 01:31:37 PM PDT 23
Finished Oct 15 01:31:39 PM PDT 23
Peak memory 215176 kb
Host smart-e39146ef-5c5d-4610-839f-9a599b36d836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248077027 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.4248077027
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_intr.1034292016
Short name T515
Test name
Test status
Simulation time 21042399 ps
CPU time 1.11 seconds
Started Oct 15 01:31:37 PM PDT 23
Finished Oct 15 01:31:39 PM PDT 23
Peak memory 222756 kb
Host smart-a68f6e36-b626-4d76-97bf-fa9b28b730b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034292016 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1034292016
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.1275046172
Short name T90
Test name
Test status
Simulation time 21333985 ps
CPU time 0.82 seconds
Started Oct 15 01:31:38 PM PDT 23
Finished Oct 15 01:31:39 PM PDT 23
Peak memory 205356 kb
Host smart-f911dedb-2eed-4122-bd1b-a4edceacee78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275046172 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.1275046172
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.1964503066
Short name T719
Test name
Test status
Simulation time 61277247 ps
CPU time 1.72 seconds
Started Oct 15 01:31:35 PM PDT 23
Finished Oct 15 01:31:38 PM PDT 23
Peak memory 206492 kb
Host smart-d191fa18-34f4-44de-b4c4-8886055596a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964503066 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1964503066
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.3328075512
Short name T277
Test name
Test status
Simulation time 21678791057 ps
CPU time 452.98 seconds
Started Oct 15 01:31:35 PM PDT 23
Finished Oct 15 01:39:09 PM PDT 23
Peak memory 215180 kb
Host smart-f6bbbfae-39fc-4ba9-8416-a446b439bd82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328075512 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.3328075512
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.edn_alert.750178500
Short name T298
Test name
Test status
Simulation time 65945507 ps
CPU time 0.93 seconds
Started Oct 15 01:31:37 PM PDT 23
Finished Oct 15 01:31:39 PM PDT 23
Peak memory 206688 kb
Host smart-290f8cbc-b8aa-46ad-b5c4-9b27179f58c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750178500 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.750178500
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.59602347
Short name T664
Test name
Test status
Simulation time 28066379 ps
CPU time 0.89 seconds
Started Oct 15 01:31:37 PM PDT 23
Finished Oct 15 01:31:39 PM PDT 23
Peak memory 205312 kb
Host smart-e182a93a-f99c-4c2e-93c6-d59c479a995e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59602347 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.59602347
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.242576035
Short name T721
Test name
Test status
Simulation time 22801621 ps
CPU time 0.86 seconds
Started Oct 15 01:31:36 PM PDT 23
Finished Oct 15 01:31:38 PM PDT 23
Peak memory 214984 kb
Host smart-fb6ea7c2-c856-484e-91b2-ba733cdf556d
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242576035 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.242576035
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.607014067
Short name T33
Test name
Test status
Simulation time 240372993 ps
CPU time 1.12 seconds
Started Oct 15 01:31:37 PM PDT 23
Finished Oct 15 01:31:39 PM PDT 23
Peak memory 214760 kb
Host smart-67030c88-e7d0-4b6e-b0b9-b5739bb1bd77
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607014067 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_di
sable_auto_req_mode.607014067
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.873952776
Short name T158
Test name
Test status
Simulation time 87679619 ps
CPU time 0.94 seconds
Started Oct 15 01:31:25 PM PDT 23
Finished Oct 15 01:31:27 PM PDT 23
Peak memory 215240 kb
Host smart-b775763c-f081-4497-a20d-8f943ab251ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873952776 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.873952776
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.3696639155
Short name T266
Test name
Test status
Simulation time 16255974 ps
CPU time 0.99 seconds
Started Oct 15 01:31:21 PM PDT 23
Finished Oct 15 01:31:22 PM PDT 23
Peak memory 206296 kb
Host smart-39f307fe-963b-4d2c-a176-22586c0781ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696639155 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.3696639155
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.2990922669
Short name T720
Test name
Test status
Simulation time 22851493 ps
CPU time 0.93 seconds
Started Oct 15 01:31:40 PM PDT 23
Finished Oct 15 01:31:42 PM PDT 23
Peak memory 215400 kb
Host smart-0cf7b97c-ea68-4c22-be2a-6fe049f1cd74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990922669 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.2990922669
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.822245474
Short name T657
Test name
Test status
Simulation time 39763596 ps
CPU time 0.85 seconds
Started Oct 15 01:31:38 PM PDT 23
Finished Oct 15 01:31:39 PM PDT 23
Peak memory 205400 kb
Host smart-9e7390d1-ddba-44d1-8191-e61f793f1d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822245474 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.822245474
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.4197774404
Short name T505
Test name
Test status
Simulation time 585944878 ps
CPU time 3.28 seconds
Started Oct 15 01:31:30 PM PDT 23
Finished Oct 15 01:31:33 PM PDT 23
Peak memory 206728 kb
Host smart-826479ea-af97-4863-ba60-35b19c4e8d25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197774404 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.4197774404
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.3806610902
Short name T702
Test name
Test status
Simulation time 62799144951 ps
CPU time 351.46 seconds
Started Oct 15 01:31:36 PM PDT 23
Finished Oct 15 01:37:28 PM PDT 23
Peak memory 215168 kb
Host smart-6f50e67a-f326-4ed5-a7aa-2b0170a39e36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806610902 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.3806610902
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.edn_alert.3319782383
Short name T616
Test name
Test status
Simulation time 89058316 ps
CPU time 0.97 seconds
Started Oct 15 01:31:23 PM PDT 23
Finished Oct 15 01:31:25 PM PDT 23
Peak memory 206272 kb
Host smart-534403df-62df-46e3-b603-7c5ae5ff8f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319782383 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.3319782383
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.3522523214
Short name T685
Test name
Test status
Simulation time 26628272 ps
CPU time 0.92 seconds
Started Oct 15 01:31:04 PM PDT 23
Finished Oct 15 01:31:05 PM PDT 23
Peak memory 205836 kb
Host smart-af00bfea-13cf-4af0-a092-0ad508c22684
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522523214 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.3522523214
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.1546437854
Short name T118
Test name
Test status
Simulation time 11764181 ps
CPU time 0.83 seconds
Started Oct 15 01:31:10 PM PDT 23
Finished Oct 15 01:31:11 PM PDT 23
Peak memory 214996 kb
Host smart-7dbdf835-62d3-4356-8e00-e00b504f0695
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546437854 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.1546437854
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.613808183
Short name T674
Test name
Test status
Simulation time 96727296 ps
CPU time 1.09 seconds
Started Oct 15 01:31:06 PM PDT 23
Finished Oct 15 01:31:08 PM PDT 23
Peak memory 215208 kb
Host smart-21f3bd8f-4caa-4555-908c-db0cddcb6110
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613808183 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_dis
able_auto_req_mode.613808183
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.1861361621
Short name T6
Test name
Test status
Simulation time 30353931 ps
CPU time 0.93 seconds
Started Oct 15 01:31:16 PM PDT 23
Finished Oct 15 01:31:18 PM PDT 23
Peak memory 216436 kb
Host smart-031f342f-236d-44fb-9b8e-a6bf5b65463e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861361621 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.1861361621
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_intr.4094619809
Short name T135
Test name
Test status
Simulation time 36969855 ps
CPU time 0.83 seconds
Started Oct 15 01:31:02 PM PDT 23
Finished Oct 15 01:31:03 PM PDT 23
Peak memory 215228 kb
Host smart-755d2fbb-4620-4e95-8416-48b336df4ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094619809 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.4094619809
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.2193198777
Short name T303
Test name
Test status
Simulation time 39486567 ps
CPU time 0.79 seconds
Started Oct 15 01:31:17 PM PDT 23
Finished Oct 15 01:31:19 PM PDT 23
Peak memory 205384 kb
Host smart-12d3b3fd-602b-41c4-9e1a-8083fcb71565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193198777 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.2193198777
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.2619950672
Short name T23
Test name
Test status
Simulation time 363470096 ps
CPU time 3.61 seconds
Started Oct 15 01:31:03 PM PDT 23
Finished Oct 15 01:31:07 PM PDT 23
Peak memory 232752 kb
Host smart-26cf54be-3d54-4ece-b2ec-73c2dc54b629
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619950672 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.2619950672
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.3350292097
Short name T661
Test name
Test status
Simulation time 21352648 ps
CPU time 0.91 seconds
Started Oct 15 01:31:15 PM PDT 23
Finished Oct 15 01:31:17 PM PDT 23
Peak memory 205592 kb
Host smart-46ed18f6-27e2-4339-865c-afc5944147df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350292097 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.3350292097
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.2071917320
Short name T592
Test name
Test status
Simulation time 408287667 ps
CPU time 4.02 seconds
Started Oct 15 01:31:32 PM PDT 23
Finished Oct 15 01:31:37 PM PDT 23
Peak memory 206524 kb
Host smart-f6745ca3-5c1a-435c-915b-3f5ec1d5ae48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071917320 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.2071917320
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.3450608124
Short name T489
Test name
Test status
Simulation time 37673037046 ps
CPU time 408.55 seconds
Started Oct 15 01:31:17 PM PDT 23
Finished Oct 15 01:38:06 PM PDT 23
Peak memory 216332 kb
Host smart-e1268156-49b1-43bb-93e8-113dda068a95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450608124 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.3450608124
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.260624624
Short name T304
Test name
Test status
Simulation time 53018688 ps
CPU time 0.94 seconds
Started Oct 15 01:31:34 PM PDT 23
Finished Oct 15 01:31:36 PM PDT 23
Peak memory 206736 kb
Host smart-9028f252-69e1-4cf3-8758-022564e65c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260624624 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.260624624
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.1930404104
Short name T51
Test name
Test status
Simulation time 21336717 ps
CPU time 0.8 seconds
Started Oct 15 01:32:14 PM PDT 23
Finished Oct 15 01:32:15 PM PDT 23
Peak memory 205252 kb
Host smart-703a1090-1d53-4d61-ace7-073dddc6abe4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930404104 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.1930404104
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.3269687010
Short name T151
Test name
Test status
Simulation time 11463416 ps
CPU time 0.82 seconds
Started Oct 15 01:31:47 PM PDT 23
Finished Oct 15 01:31:49 PM PDT 23
Peak memory 215016 kb
Host smart-e7f6d2f4-8f66-4c7b-86b8-b9c5e3875f1d
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269687010 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.3269687010
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.1084568498
Short name T659
Test name
Test status
Simulation time 143143886 ps
CPU time 0.94 seconds
Started Oct 15 01:31:44 PM PDT 23
Finished Oct 15 01:31:46 PM PDT 23
Peak memory 215176 kb
Host smart-22d2bbfa-95ab-44c7-b482-a661b3faebdc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084568498 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.1084568498
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.1512525127
Short name T176
Test name
Test status
Simulation time 18691618 ps
CPU time 1.02 seconds
Started Oct 15 01:32:29 PM PDT 23
Finished Oct 15 01:32:30 PM PDT 23
Peak memory 216512 kb
Host smart-8351ab95-d6b1-4ae1-8077-5c764cb4a15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512525127 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.1512525127
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_intr.217662078
Short name T41
Test name
Test status
Simulation time 30537071 ps
CPU time 0.9 seconds
Started Oct 15 01:31:39 PM PDT 23
Finished Oct 15 01:31:42 PM PDT 23
Peak memory 215152 kb
Host smart-1b9a1100-faef-469c-9139-fb276f345485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217662078 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.217662078
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.4261285262
Short name T503
Test name
Test status
Simulation time 17348682 ps
CPU time 0.92 seconds
Started Oct 15 01:31:20 PM PDT 23
Finished Oct 15 01:31:21 PM PDT 23
Peak memory 205440 kb
Host smart-662bc808-ad67-4f92-9eb9-e57e01af1d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261285262 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.4261285262
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.1211052737
Short name T576
Test name
Test status
Simulation time 43422357 ps
CPU time 1.03 seconds
Started Oct 15 01:31:38 PM PDT 23
Finished Oct 15 01:31:41 PM PDT 23
Peak memory 206112 kb
Host smart-dd2cf007-666c-453e-8684-84eac9d64bad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211052737 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.1211052737
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_alert_test.883273403
Short name T524
Test name
Test status
Simulation time 23583298 ps
CPU time 0.86 seconds
Started Oct 15 01:31:43 PM PDT 23
Finished Oct 15 01:31:45 PM PDT 23
Peak memory 205348 kb
Host smart-6a31a479-d7f9-4acb-914f-9aec972e2956
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883273403 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.883273403
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.2120376205
Short name T233
Test name
Test status
Simulation time 15391361 ps
CPU time 0.9 seconds
Started Oct 15 01:31:48 PM PDT 23
Finished Oct 15 01:31:49 PM PDT 23
Peak memory 215232 kb
Host smart-d6a08289-a2a8-4e76-a831-3d3234b55187
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120376205 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.2120376205
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_err.2223613414
Short name T318
Test name
Test status
Simulation time 28665876 ps
CPU time 0.84 seconds
Started Oct 15 01:31:51 PM PDT 23
Finished Oct 15 01:31:52 PM PDT 23
Peak memory 216340 kb
Host smart-ccd17c5e-4f7f-47d3-abe6-633d4cf7a470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223613414 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.2223613414
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.259313911
Short name T286
Test name
Test status
Simulation time 19590208 ps
CPU time 0.98 seconds
Started Oct 15 01:31:42 PM PDT 23
Finished Oct 15 01:31:44 PM PDT 23
Peak memory 205704 kb
Host smart-55a65052-fe1b-49fc-b406-3e7eb07f9af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259313911 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.259313911
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.237898162
Short name T704
Test name
Test status
Simulation time 27942844 ps
CPU time 0.83 seconds
Started Oct 15 01:31:42 PM PDT 23
Finished Oct 15 01:31:43 PM PDT 23
Peak memory 215144 kb
Host smart-baf20381-8b4d-43dc-b942-f9fbcf07fb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237898162 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.237898162
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.2300885063
Short name T567
Test name
Test status
Simulation time 18548252 ps
CPU time 0.92 seconds
Started Oct 15 01:31:39 PM PDT 23
Finished Oct 15 01:31:41 PM PDT 23
Peak memory 205644 kb
Host smart-756ff6c8-f153-4cb1-9da5-803445f60fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300885063 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.2300885063
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.2057851876
Short name T483
Test name
Test status
Simulation time 166373457 ps
CPU time 3.59 seconds
Started Oct 15 01:32:30 PM PDT 23
Finished Oct 15 01:32:34 PM PDT 23
Peak memory 206480 kb
Host smart-622237bb-a0b0-4903-8d1e-f6d05c514f61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057851876 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.2057851876
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.2662844752
Short name T337
Test name
Test status
Simulation time 6255435234 ps
CPU time 21.78 seconds
Started Oct 15 01:32:14 PM PDT 23
Finished Oct 15 01:32:37 PM PDT 23
Peak memory 215844 kb
Host smart-1069604b-be98-4ba3-ab3a-46359a88024c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662844752 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.2662844752
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.edn_alert.3411569994
Short name T590
Test name
Test status
Simulation time 17003171 ps
CPU time 0.95 seconds
Started Oct 15 01:31:51 PM PDT 23
Finished Oct 15 01:31:53 PM PDT 23
Peak memory 206412 kb
Host smart-57866e28-71fb-4a25-a87c-d0155550422b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411569994 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.3411569994
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.2852252988
Short name T725
Test name
Test status
Simulation time 19218454 ps
CPU time 0.97 seconds
Started Oct 15 01:31:52 PM PDT 23
Finished Oct 15 01:31:54 PM PDT 23
Peak memory 206332 kb
Host smart-dca393a7-1d7c-4d2c-8158-23ecfb7e8c56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852252988 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.2852252988
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.965905379
Short name T44
Test name
Test status
Simulation time 76084037 ps
CPU time 0.9 seconds
Started Oct 15 01:31:47 PM PDT 23
Finished Oct 15 01:31:48 PM PDT 23
Peak memory 215220 kb
Host smart-c2076ae0-8563-49ed-a2e1-ca1663e4093d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965905379 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_di
sable_auto_req_mode.965905379
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.1016450033
Short name T545
Test name
Test status
Simulation time 49751734 ps
CPU time 0.93 seconds
Started Oct 15 01:31:39 PM PDT 23
Finished Oct 15 01:31:42 PM PDT 23
Peak memory 222704 kb
Host smart-37939d83-1d06-404b-83e9-e8ce355839a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016450033 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.1016450033
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.684919381
Short name T711
Test name
Test status
Simulation time 21800993 ps
CPU time 1.03 seconds
Started Oct 15 01:32:15 PM PDT 23
Finished Oct 15 01:32:17 PM PDT 23
Peak memory 206056 kb
Host smart-5849fafa-e831-4e78-b1c4-9d3b31e19610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684919381 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.684919381
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.424744234
Short name T59
Test name
Test status
Simulation time 19109807 ps
CPU time 1.04 seconds
Started Oct 15 01:32:30 PM PDT 23
Finished Oct 15 01:32:32 PM PDT 23
Peak memory 215088 kb
Host smart-a6a62ba0-ba05-453e-b344-1f345b89b798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424744234 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.424744234
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.379397270
Short name T552
Test name
Test status
Simulation time 41782056 ps
CPU time 0.9 seconds
Started Oct 15 01:31:39 PM PDT 23
Finished Oct 15 01:31:42 PM PDT 23
Peak memory 205540 kb
Host smart-64f2a47e-039c-48b1-bd85-e54063945ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379397270 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.379397270
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.169330769
Short name T540
Test name
Test status
Simulation time 206555591 ps
CPU time 3.64 seconds
Started Oct 15 01:31:41 PM PDT 23
Finished Oct 15 01:31:46 PM PDT 23
Peak memory 206672 kb
Host smart-c891f4a7-d6c4-483a-b700-5a9882205800
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169330769 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.169330769
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.301012253
Short name T504
Test name
Test status
Simulation time 39474988306 ps
CPU time 872.48 seconds
Started Oct 15 01:32:29 PM PDT 23
Finished Oct 15 01:47:02 PM PDT 23
Peak memory 223384 kb
Host smart-d9a6004f-797b-40a9-8dac-71f5b0a2441c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301012253 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.301012253
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.edn_alert.1659576996
Short name T617
Test name
Test status
Simulation time 21883663 ps
CPU time 0.91 seconds
Started Oct 15 01:31:41 PM PDT 23
Finished Oct 15 01:31:43 PM PDT 23
Peak memory 206804 kb
Host smart-798443db-fdaf-46e0-98a5-af5fe0fd59f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659576996 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.1659576996
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.2440690795
Short name T554
Test name
Test status
Simulation time 31463334 ps
CPU time 0.84 seconds
Started Oct 15 01:31:39 PM PDT 23
Finished Oct 15 01:31:42 PM PDT 23
Peak memory 206040 kb
Host smart-2bb15323-9cd7-48a9-a8d7-e443605ae1ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440690795 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.2440690795
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.1269388190
Short name T114
Test name
Test status
Simulation time 10661821 ps
CPU time 0.83 seconds
Started Oct 15 01:31:45 PM PDT 23
Finished Oct 15 01:31:47 PM PDT 23
Peak memory 214984 kb
Host smart-f07d51b5-bd3a-49ec-998f-68dfe10a4bb6
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269388190 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.1269388190
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.3150915712
Short name T530
Test name
Test status
Simulation time 52588307 ps
CPU time 0.94 seconds
Started Oct 15 01:31:40 PM PDT 23
Finished Oct 15 01:31:42 PM PDT 23
Peak memory 215244 kb
Host smart-f822c562-7d77-40c1-b7e5-01fbcb3acc73
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150915712 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.3150915712
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.1831349540
Short name T473
Test name
Test status
Simulation time 32458546 ps
CPU time 0.83 seconds
Started Oct 15 01:31:44 PM PDT 23
Finished Oct 15 01:31:46 PM PDT 23
Peak memory 216356 kb
Host smart-f0c35509-3348-46a3-8c3b-14f4c3fc928a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831349540 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.1831349540
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_intr.1292885814
Short name T608
Test name
Test status
Simulation time 24051148 ps
CPU time 1.01 seconds
Started Oct 15 01:31:42 PM PDT 23
Finished Oct 15 01:31:44 PM PDT 23
Peak memory 215116 kb
Host smart-5b7700c2-9e84-40a9-b3bd-9c2e4732c688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292885814 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.1292885814
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.2216165407
Short name T335
Test name
Test status
Simulation time 59041339 ps
CPU time 0.82 seconds
Started Oct 15 01:31:55 PM PDT 23
Finished Oct 15 01:31:56 PM PDT 23
Peak memory 205360 kb
Host smart-9a3a2a64-9aa0-49e7-b948-ccc06ce847c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216165407 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.2216165407
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.1601381461
Short name T633
Test name
Test status
Simulation time 555675307 ps
CPU time 2.97 seconds
Started Oct 15 01:31:49 PM PDT 23
Finished Oct 15 01:31:52 PM PDT 23
Peak memory 206624 kb
Host smart-2c498358-c8f0-49cd-bd8f-a0619e797c22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601381461 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.1601381461
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.49867732
Short name T518
Test name
Test status
Simulation time 134992686464 ps
CPU time 742.05 seconds
Started Oct 15 01:32:15 PM PDT 23
Finished Oct 15 01:44:37 PM PDT 23
Peak memory 216076 kb
Host smart-fdc10440-dd33-41a6-be45-90e050fd70e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49867732 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.49867732
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.edn_alert.3144725263
Short name T482
Test name
Test status
Simulation time 30588804 ps
CPU time 0.96 seconds
Started Oct 15 01:31:39 PM PDT 23
Finished Oct 15 01:31:42 PM PDT 23
Peak memory 206840 kb
Host smart-39a2a0cf-1dd8-4837-badb-32d793431465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144725263 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.3144725263
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.1082043005
Short name T548
Test name
Test status
Simulation time 26392571 ps
CPU time 0.89 seconds
Started Oct 15 01:31:49 PM PDT 23
Finished Oct 15 01:31:50 PM PDT 23
Peak memory 205956 kb
Host smart-3553b9cc-fe38-411c-b242-83aeca61c8e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082043005 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.1082043005
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.1382933714
Short name T701
Test name
Test status
Simulation time 34901733 ps
CPU time 0.8 seconds
Started Oct 15 01:32:28 PM PDT 23
Finished Oct 15 01:32:30 PM PDT 23
Peak memory 215064 kb
Host smart-595fcce2-421c-4842-af5a-bb2184e1cef0
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382933714 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1382933714
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.3340104905
Short name T628
Test name
Test status
Simulation time 27269877 ps
CPU time 1.01 seconds
Started Oct 15 01:31:51 PM PDT 23
Finished Oct 15 01:31:52 PM PDT 23
Peak memory 215264 kb
Host smart-1090a885-ff8b-4bf4-a6f0-300ad96795d5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340104905 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.3340104905
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.1970015003
Short name T243
Test name
Test status
Simulation time 29891236 ps
CPU time 1.31 seconds
Started Oct 15 01:31:46 PM PDT 23
Finished Oct 15 01:31:48 PM PDT 23
Peak memory 222924 kb
Host smart-73b5d453-65e7-4921-a7c3-12b9b176d80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970015003 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.1970015003
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.1946497230
Short name T635
Test name
Test status
Simulation time 18022200 ps
CPU time 1.14 seconds
Started Oct 15 01:31:40 PM PDT 23
Finished Oct 15 01:31:42 PM PDT 23
Peak memory 205980 kb
Host smart-cbc5cf91-42d0-4187-9c4c-b38d76c815ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946497230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1946497230
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.1371853699
Short name T636
Test name
Test status
Simulation time 25699002 ps
CPU time 0.9 seconds
Started Oct 15 01:31:45 PM PDT 23
Finished Oct 15 01:31:46 PM PDT 23
Peak memory 215140 kb
Host smart-c0e4a7e1-3389-45a0-91b4-312d16c6c378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371853699 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.1371853699
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.2669624671
Short name T534
Test name
Test status
Simulation time 15245418 ps
CPU time 0.86 seconds
Started Oct 15 01:31:45 PM PDT 23
Finished Oct 15 01:31:47 PM PDT 23
Peak memory 205540 kb
Host smart-ca773f89-51a4-4b02-ab32-c9477adb063a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669624671 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.2669624671
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.2963612619
Short name T627
Test name
Test status
Simulation time 200533331 ps
CPU time 1.5 seconds
Started Oct 15 01:31:52 PM PDT 23
Finished Oct 15 01:31:54 PM PDT 23
Peak memory 206380 kb
Host smart-b9ca9b7b-618c-4676-9b4a-e65e6f026fe9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963612619 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.2963612619
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.3300699829
Short name T660
Test name
Test status
Simulation time 48391355238 ps
CPU time 612.67 seconds
Started Oct 15 01:31:49 PM PDT 23
Finished Oct 15 01:42:02 PM PDT 23
Peak memory 216128 kb
Host smart-a5a83a01-eb40-4990-9b7d-9e2d114dda1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300699829 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.3300699829
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.edn_alert.3740728737
Short name T258
Test name
Test status
Simulation time 20430017 ps
CPU time 0.92 seconds
Started Oct 15 01:31:49 PM PDT 23
Finished Oct 15 01:31:51 PM PDT 23
Peak memory 206368 kb
Host smart-9d12116c-d2f0-4edd-9ef8-585479674607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740728737 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.3740728737
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.3130305102
Short name T479
Test name
Test status
Simulation time 71373602 ps
CPU time 0.97 seconds
Started Oct 15 01:31:44 PM PDT 23
Finished Oct 15 01:31:46 PM PDT 23
Peak memory 205620 kb
Host smart-4eaae44f-a21a-4f31-9984-cd181c4d9924
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130305102 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.3130305102
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_err.1888247238
Short name T245
Test name
Test status
Simulation time 19932766 ps
CPU time 1 seconds
Started Oct 15 01:31:42 PM PDT 23
Finished Oct 15 01:31:44 PM PDT 23
Peak memory 215564 kb
Host smart-010d22b1-a411-4e2c-ac36-7ac71d574e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888247238 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.1888247238
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.3280364148
Short name T288
Test name
Test status
Simulation time 16129919 ps
CPU time 0.98 seconds
Started Oct 15 01:31:49 PM PDT 23
Finished Oct 15 01:31:50 PM PDT 23
Peak memory 206048 kb
Host smart-34c76261-0636-44bf-acd2-b6da75c73c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280364148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3280364148
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.583488638
Short name T148
Test name
Test status
Simulation time 31472658 ps
CPU time 0.84 seconds
Started Oct 15 01:31:47 PM PDT 23
Finished Oct 15 01:31:48 PM PDT 23
Peak memory 215168 kb
Host smart-bb28c248-f8b3-42ab-ae0e-de47854b8a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583488638 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.583488638
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.1521649396
Short name T680
Test name
Test status
Simulation time 13053655 ps
CPU time 0.84 seconds
Started Oct 15 01:31:44 PM PDT 23
Finished Oct 15 01:31:45 PM PDT 23
Peak memory 205584 kb
Host smart-e4c4deb1-8267-415c-b3e4-ae64448e7bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521649396 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.1521649396
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.2751397581
Short name T468
Test name
Test status
Simulation time 386785725 ps
CPU time 3.99 seconds
Started Oct 15 01:31:47 PM PDT 23
Finished Oct 15 01:31:52 PM PDT 23
Peak memory 206680 kb
Host smart-975b7e5e-334f-4bd8-ae9a-8c87217221f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751397581 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2751397581
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.1569237980
Short name T522
Test name
Test status
Simulation time 505029579857 ps
CPU time 1198.59 seconds
Started Oct 15 01:31:50 PM PDT 23
Finished Oct 15 01:51:49 PM PDT 23
Peak memory 216068 kb
Host smart-6f2cc5ee-d202-4bc2-9f52-f9d1a106278d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569237980 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.1569237980
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.edn_alert.2103209797
Short name T294
Test name
Test status
Simulation time 30612392 ps
CPU time 0.98 seconds
Started Oct 15 01:31:42 PM PDT 23
Finished Oct 15 01:31:44 PM PDT 23
Peak memory 206740 kb
Host smart-2e2555ad-d6f0-42e4-b421-2b9bca141f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103209797 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.2103209797
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.267213612
Short name T334
Test name
Test status
Simulation time 13274765 ps
CPU time 0.84 seconds
Started Oct 15 01:31:45 PM PDT 23
Finished Oct 15 01:31:46 PM PDT 23
Peak memory 205236 kb
Host smart-4b47bb1f-d7d0-4643-adbe-05471b72fbd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267213612 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.267213612
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.3760200124
Short name T586
Test name
Test status
Simulation time 20209330 ps
CPU time 0.81 seconds
Started Oct 15 01:32:09 PM PDT 23
Finished Oct 15 01:32:10 PM PDT 23
Peak memory 215068 kb
Host smart-7eff725c-b141-4a02-9b8a-65aa0ada6631
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760200124 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.3760200124
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.2539133760
Short name T49
Test name
Test status
Simulation time 61608144 ps
CPU time 1.02 seconds
Started Oct 15 01:31:45 PM PDT 23
Finished Oct 15 01:31:46 PM PDT 23
Peak memory 215316 kb
Host smart-b57e1888-5cfe-4140-93da-4d00830dc276
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539133760 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.2539133760
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.1526061777
Short name T48
Test name
Test status
Simulation time 23916553 ps
CPU time 0.92 seconds
Started Oct 15 01:31:50 PM PDT 23
Finished Oct 15 01:31:52 PM PDT 23
Peak memory 215512 kb
Host smart-692035db-c3fc-451b-918b-5813a0e346e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526061777 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.1526061777
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.694875324
Short name T285
Test name
Test status
Simulation time 35695684 ps
CPU time 0.89 seconds
Started Oct 15 01:32:09 PM PDT 23
Finished Oct 15 01:32:10 PM PDT 23
Peak memory 205808 kb
Host smart-fbe94db8-66d6-4b46-97d3-a65dad35f953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694875324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.694875324
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_smoke.4173374524
Short name T466
Test name
Test status
Simulation time 22225644 ps
CPU time 0.93 seconds
Started Oct 15 01:31:47 PM PDT 23
Finished Oct 15 01:31:48 PM PDT 23
Peak memory 205460 kb
Host smart-22d88ed0-2c0d-405a-8aa6-d4e0430776cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173374524 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.4173374524
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.2712979936
Short name T516
Test name
Test status
Simulation time 74028580 ps
CPU time 1.89 seconds
Started Oct 15 01:31:44 PM PDT 23
Finished Oct 15 01:31:47 PM PDT 23
Peak memory 206412 kb
Host smart-2a8b793f-0f17-4c06-aa05-871430554f2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712979936 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.2712979936
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.3378322705
Short name T321
Test name
Test status
Simulation time 35837584666 ps
CPU time 430.41 seconds
Started Oct 15 01:31:46 PM PDT 23
Finished Oct 15 01:38:57 PM PDT 23
Peak memory 216388 kb
Host smart-1e93ef8b-b01a-424f-83e9-d7e18ca11f92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378322705 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.3378322705
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.edn_alert.125305833
Short name T84
Test name
Test status
Simulation time 33997982 ps
CPU time 0.94 seconds
Started Oct 15 01:31:41 PM PDT 23
Finished Oct 15 01:31:43 PM PDT 23
Peak memory 205896 kb
Host smart-7236fb77-2ff4-4624-a497-e31ee2919b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125305833 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.125305833
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.1497865262
Short name T667
Test name
Test status
Simulation time 54957780 ps
CPU time 0.9 seconds
Started Oct 15 01:31:42 PM PDT 23
Finished Oct 15 01:31:44 PM PDT 23
Peak memory 205388 kb
Host smart-8f919d54-6a06-4460-ac42-ca225a99107e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497865262 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1497865262
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.2866914393
Short name T622
Test name
Test status
Simulation time 73594153 ps
CPU time 0.76 seconds
Started Oct 15 01:32:28 PM PDT 23
Finished Oct 15 01:32:29 PM PDT 23
Peak memory 215056 kb
Host smart-4ebb9aa1-7107-42d2-89f9-678edd4f8ac3
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866914393 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.2866914393
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.1361735363
Short name T593
Test name
Test status
Simulation time 26582892 ps
CPU time 0.9 seconds
Started Oct 15 01:32:11 PM PDT 23
Finished Oct 15 01:32:12 PM PDT 23
Peak memory 215344 kb
Host smart-4540bf10-4f07-4a16-add3-2aca9f06c3f6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361735363 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.1361735363
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.1474908605
Short name T596
Test name
Test status
Simulation time 32163153 ps
CPU time 0.85 seconds
Started Oct 15 01:32:10 PM PDT 23
Finished Oct 15 01:32:12 PM PDT 23
Peak memory 216608 kb
Host smart-b5475570-5c15-44e9-aa7e-0c3d8c5d9924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474908605 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.1474908605
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.79697844
Short name T607
Test name
Test status
Simulation time 86723560 ps
CPU time 0.92 seconds
Started Oct 15 01:31:50 PM PDT 23
Finished Oct 15 01:31:51 PM PDT 23
Peak memory 205888 kb
Host smart-2ba9b6c4-d501-4198-9355-edd1252e8ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79697844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.79697844
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.3467954447
Short name T3
Test name
Test status
Simulation time 42053676 ps
CPU time 0.87 seconds
Started Oct 15 01:32:10 PM PDT 23
Finished Oct 15 01:32:12 PM PDT 23
Peak memory 214852 kb
Host smart-9d703875-74d8-4f9c-8f77-369287c62ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467954447 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.3467954447
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.3589014661
Short name T68
Test name
Test status
Simulation time 19602615 ps
CPU time 0.8 seconds
Started Oct 15 01:31:42 PM PDT 23
Finished Oct 15 01:31:43 PM PDT 23
Peak memory 205604 kb
Host smart-8718fc83-f0cd-459a-bcba-d69aee7c6487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589014661 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.3589014661
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.3037202980
Short name T312
Test name
Test status
Simulation time 144421053 ps
CPU time 2.13 seconds
Started Oct 15 01:31:46 PM PDT 23
Finished Oct 15 01:31:49 PM PDT 23
Peak memory 206408 kb
Host smart-fcb050ad-d310-4b26-94c9-528a8c483221
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037202980 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.3037202980
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.583264431
Short name T325
Test name
Test status
Simulation time 25186523537 ps
CPU time 492.53 seconds
Started Oct 15 01:31:54 PM PDT 23
Finished Oct 15 01:40:07 PM PDT 23
Peak memory 215168 kb
Host smart-e4ab6346-3cf8-46a0-9a72-2155d17b929b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583264431 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.583264431
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.edn_alert.797242273
Short name T665
Test name
Test status
Simulation time 35493371 ps
CPU time 0.97 seconds
Started Oct 15 01:31:47 PM PDT 23
Finished Oct 15 01:31:49 PM PDT 23
Peak memory 206168 kb
Host smart-3c157327-6a0d-44bf-9bfa-2e05cde653f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797242273 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.797242273
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.1250996125
Short name T324
Test name
Test status
Simulation time 50633026 ps
CPU time 0.85 seconds
Started Oct 15 01:32:10 PM PDT 23
Finished Oct 15 01:32:11 PM PDT 23
Peak memory 205384 kb
Host smart-168fd7e1-a721-48dc-9683-21f881c5726c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250996125 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.1250996125
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.759692235
Short name T86
Test name
Test status
Simulation time 35275803 ps
CPU time 0.81 seconds
Started Oct 15 01:32:11 PM PDT 23
Finished Oct 15 01:32:12 PM PDT 23
Peak memory 215044 kb
Host smart-feac6612-cf19-46b8-b54d-99a6404bb109
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759692235 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.759692235
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.3704040270
Short name T97
Test name
Test status
Simulation time 45949907 ps
CPU time 0.92 seconds
Started Oct 15 01:31:39 PM PDT 23
Finished Oct 15 01:31:42 PM PDT 23
Peak memory 215288 kb
Host smart-80b3a2a2-2faf-4d84-bac2-7112c0d33027
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704040270 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.3704040270
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.1605402918
Short name T563
Test name
Test status
Simulation time 29025216 ps
CPU time 0.85 seconds
Started Oct 15 01:31:41 PM PDT 23
Finished Oct 15 01:31:43 PM PDT 23
Peak memory 215140 kb
Host smart-7e80d169-af29-4501-a233-51990d27deb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605402918 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.1605402918
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.3721549171
Short name T91
Test name
Test status
Simulation time 14262934 ps
CPU time 0.95 seconds
Started Oct 15 01:32:29 PM PDT 23
Finished Oct 15 01:32:30 PM PDT 23
Peak memory 214860 kb
Host smart-3778d5b0-be79-434c-b15e-0e63796b63b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721549171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.3721549171
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.4128290703
Short name T600
Test name
Test status
Simulation time 27976194 ps
CPU time 0.86 seconds
Started Oct 15 01:32:29 PM PDT 23
Finished Oct 15 01:32:30 PM PDT 23
Peak memory 215088 kb
Host smart-8a076b0c-3096-4843-9d80-f9385fca40a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128290703 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.4128290703
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.3753238826
Short name T322
Test name
Test status
Simulation time 29289503 ps
CPU time 0.84 seconds
Started Oct 15 01:32:31 PM PDT 23
Finished Oct 15 01:32:32 PM PDT 23
Peak memory 205560 kb
Host smart-3554add8-65ca-481c-a920-978d928715aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753238826 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.3753238826
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.1660272535
Short name T707
Test name
Test status
Simulation time 291561067 ps
CPU time 3.29 seconds
Started Oct 15 01:31:41 PM PDT 23
Finished Oct 15 01:31:45 PM PDT 23
Peak memory 206664 kb
Host smart-b90b74f3-4a21-46ea-b402-603ede42ed03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660272535 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.1660272535
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_alert.364981869
Short name T493
Test name
Test status
Simulation time 28871085 ps
CPU time 0.95 seconds
Started Oct 15 01:32:29 PM PDT 23
Finished Oct 15 01:32:31 PM PDT 23
Peak memory 206696 kb
Host smart-69e32a47-9ffc-4ad6-a651-b1f61a47b3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364981869 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.364981869
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.1520666072
Short name T513
Test name
Test status
Simulation time 54931885 ps
CPU time 0.88 seconds
Started Oct 15 01:31:49 PM PDT 23
Finished Oct 15 01:31:50 PM PDT 23
Peak memory 205440 kb
Host smart-85c308bc-7256-4c81-88a9-2763a904f368
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520666072 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.1520666072
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.1562982160
Short name T99
Test name
Test status
Simulation time 119659230 ps
CPU time 0.93 seconds
Started Oct 15 01:31:46 PM PDT 23
Finished Oct 15 01:31:47 PM PDT 23
Peak memory 215280 kb
Host smart-786fbca8-dc33-4914-b3c0-e2543e229223
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562982160 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.1562982160
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.3682590435
Short name T678
Test name
Test status
Simulation time 19281226 ps
CPU time 1.03 seconds
Started Oct 15 01:31:39 PM PDT 23
Finished Oct 15 01:31:42 PM PDT 23
Peak memory 216576 kb
Host smart-ef1071e8-216a-40f7-9d52-be8554d0f5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682590435 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.3682590435
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.219354739
Short name T709
Test name
Test status
Simulation time 58826659 ps
CPU time 1.01 seconds
Started Oct 15 01:31:48 PM PDT 23
Finished Oct 15 01:31:50 PM PDT 23
Peak memory 214956 kb
Host smart-7091cfd5-ecce-4c4a-8b9a-21496a1b4c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219354739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.219354739
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.2994160845
Short name T715
Test name
Test status
Simulation time 22305765 ps
CPU time 1.03 seconds
Started Oct 15 01:31:50 PM PDT 23
Finished Oct 15 01:31:52 PM PDT 23
Peak memory 226444 kb
Host smart-c06352b6-6059-4566-87f6-e281af6e7a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994160845 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.2994160845
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.2383539554
Short name T323
Test name
Test status
Simulation time 17123296 ps
CPU time 0.87 seconds
Started Oct 15 01:31:43 PM PDT 23
Finished Oct 15 01:31:45 PM PDT 23
Peak memory 205616 kb
Host smart-c18221d7-4b1c-4d53-b75a-885ff6e66bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383539554 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.2383539554
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.1630773165
Short name T66
Test name
Test status
Simulation time 106663966 ps
CPU time 2.67 seconds
Started Oct 15 01:31:46 PM PDT 23
Finished Oct 15 01:31:49 PM PDT 23
Peak memory 206640 kb
Host smart-5d89ed8d-13b7-4a61-b22a-94d00a9776af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630773165 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1630773165
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.84393790
Short name T488
Test name
Test status
Simulation time 41150801198 ps
CPU time 490.3 seconds
Started Oct 15 01:31:49 PM PDT 23
Finished Oct 15 01:39:59 PM PDT 23
Peak memory 215668 kb
Host smart-22032aaa-fffd-4406-ae29-913f9d64a70b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84393790 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.84393790
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.edn_alert.3633112193
Short name T18
Test name
Test status
Simulation time 32932529 ps
CPU time 0.92 seconds
Started Oct 15 01:31:42 PM PDT 23
Finished Oct 15 01:31:44 PM PDT 23
Peak memory 205816 kb
Host smart-a05e1ab4-6e03-494a-afc0-65b63634a10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633112193 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.3633112193
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.77775140
Short name T691
Test name
Test status
Simulation time 16433895 ps
CPU time 0.95 seconds
Started Oct 15 01:31:31 PM PDT 23
Finished Oct 15 01:31:33 PM PDT 23
Peak memory 206280 kb
Host smart-f006bc04-ced0-4986-9770-bf31eb6f151c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77775140 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.77775140
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.2581959699
Short name T163
Test name
Test status
Simulation time 18453977 ps
CPU time 0.95 seconds
Started Oct 15 01:31:31 PM PDT 23
Finished Oct 15 01:31:32 PM PDT 23
Peak memory 215284 kb
Host smart-fe2bf4fc-a1e2-4cff-a36f-9bd967fe15a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581959699 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.2581959699
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.722477025
Short name T242
Test name
Test status
Simulation time 44091188 ps
CPU time 0.91 seconds
Started Oct 15 01:31:28 PM PDT 23
Finished Oct 15 01:31:30 PM PDT 23
Peak memory 215376 kb
Host smart-edd08668-f035-49ea-87e1-3724196d7f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722477025 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.722477025
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.2080348006
Short name T2
Test name
Test status
Simulation time 15064123 ps
CPU time 0.91 seconds
Started Oct 15 01:31:29 PM PDT 23
Finished Oct 15 01:31:31 PM PDT 23
Peak memory 205644 kb
Host smart-15c46fc1-33fc-43fd-ad28-18442f248680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080348006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.2080348006
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.1662458154
Short name T693
Test name
Test status
Simulation time 35529539 ps
CPU time 0.89 seconds
Started Oct 15 01:31:15 PM PDT 23
Finished Oct 15 01:31:17 PM PDT 23
Peak memory 222216 kb
Host smart-b3df3fa0-a94a-43ba-8a7f-9a80770032d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662458154 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.1662458154
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_sec_cm.4229215537
Short name T62
Test name
Test status
Simulation time 1374229345 ps
CPU time 3.81 seconds
Started Oct 15 01:31:26 PM PDT 23
Finished Oct 15 01:31:32 PM PDT 23
Peak memory 234828 kb
Host smart-4d176574-b7ee-45f9-8212-4012cb8ef7d8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229215537 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.4229215537
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.848698833
Short name T722
Test name
Test status
Simulation time 15568802 ps
CPU time 0.9 seconds
Started Oct 15 01:30:53 PM PDT 23
Finished Oct 15 01:30:54 PM PDT 23
Peak memory 205632 kb
Host smart-f77d2d1d-d9c2-47c5-b6ef-9e1b1a88d291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848698833 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.848698833
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.2410796292
Short name T89
Test name
Test status
Simulation time 563471936 ps
CPU time 3.3 seconds
Started Oct 15 01:31:33 PM PDT 23
Finished Oct 15 01:31:38 PM PDT 23
Peak memory 206792 kb
Host smart-4b175df1-9d5b-41a3-a2a7-0db1fc7c63c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410796292 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.2410796292
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3676318045
Short name T559
Test name
Test status
Simulation time 100358777424 ps
CPU time 1205.03 seconds
Started Oct 15 01:31:19 PM PDT 23
Finished Oct 15 01:51:25 PM PDT 23
Peak memory 219608 kb
Host smart-2f480d70-a993-403e-9161-996030053c1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676318045 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3676318045
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.2759593929
Short name T673
Test name
Test status
Simulation time 32095292 ps
CPU time 0.97 seconds
Started Oct 15 01:31:39 PM PDT 23
Finished Oct 15 01:31:42 PM PDT 23
Peak memory 206776 kb
Host smart-7f953332-e715-4752-936f-b02b84e13675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759593929 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.2759593929
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.63255759
Short name T107
Test name
Test status
Simulation time 24477059 ps
CPU time 0.83 seconds
Started Oct 15 01:31:40 PM PDT 23
Finished Oct 15 01:31:42 PM PDT 23
Peak memory 205312 kb
Host smart-3ad50cb2-5db8-4f0d-86eb-135b853447b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63255759 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.63255759
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.837067956
Short name T144
Test name
Test status
Simulation time 23550178 ps
CPU time 0.99 seconds
Started Oct 15 01:31:43 PM PDT 23
Finished Oct 15 01:31:44 PM PDT 23
Peak memory 215256 kb
Host smart-c41b7014-ddb3-4061-96cb-9a92c5afb3f9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837067956 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_di
sable_auto_req_mode.837067956
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.1908061710
Short name T182
Test name
Test status
Simulation time 29762946 ps
CPU time 0.83 seconds
Started Oct 15 01:31:40 PM PDT 23
Finished Oct 15 01:31:42 PM PDT 23
Peak memory 216516 kb
Host smart-7806a7fb-c69d-48b8-8958-caa1c434b14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908061710 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.1908061710
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.1134928954
Short name T272
Test name
Test status
Simulation time 33239545 ps
CPU time 0.97 seconds
Started Oct 15 01:32:30 PM PDT 23
Finished Oct 15 01:32:31 PM PDT 23
Peak memory 206384 kb
Host smart-45d080a9-696d-456b-8169-e008085f29b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134928954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.1134928954
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.1699393243
Short name T523
Test name
Test status
Simulation time 19093243 ps
CPU time 1 seconds
Started Oct 15 01:31:47 PM PDT 23
Finished Oct 15 01:31:48 PM PDT 23
Peak memory 215156 kb
Host smart-fabe9888-8de3-4abc-9ccf-7841c315ac9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699393243 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.1699393243
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.3230108790
Short name T326
Test name
Test status
Simulation time 13531329 ps
CPU time 0.88 seconds
Started Oct 15 01:32:10 PM PDT 23
Finished Oct 15 01:32:11 PM PDT 23
Peak memory 205492 kb
Host smart-08e715e3-39f3-4c21-967b-5f1ee3cbf2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230108790 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.3230108790
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.4256925563
Short name T100
Test name
Test status
Simulation time 123804294 ps
CPU time 2.36 seconds
Started Oct 15 01:31:47 PM PDT 23
Finished Oct 15 01:31:50 PM PDT 23
Peak memory 206720 kb
Host smart-89899659-9233-4ef6-9b5a-c593d714d721
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256925563 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.4256925563
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.3015226948
Short name T609
Test name
Test status
Simulation time 152634319726 ps
CPU time 1759.37 seconds
Started Oct 15 01:31:43 PM PDT 23
Finished Oct 15 02:01:03 PM PDT 23
Peak memory 220064 kb
Host smart-9e8394d7-ecae-41a0-82d9-572c3fc6ab07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015226948 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.3015226948
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.3839726369
Short name T658
Test name
Test status
Simulation time 70242754 ps
CPU time 0.99 seconds
Started Oct 15 01:31:47 PM PDT 23
Finished Oct 15 01:31:49 PM PDT 23
Peak memory 205796 kb
Host smart-28ff0109-cbd9-458a-bda6-0341a16c16c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839726369 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.3839726369
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.3904242066
Short name T474
Test name
Test status
Simulation time 18315680 ps
CPU time 0.94 seconds
Started Oct 15 01:31:43 PM PDT 23
Finished Oct 15 01:31:44 PM PDT 23
Peak memory 205972 kb
Host smart-e863c864-03e2-4b56-aa2a-464d8c776b7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904242066 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.3904242066
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.3058823037
Short name T35
Test name
Test status
Simulation time 46715380 ps
CPU time 0.79 seconds
Started Oct 15 01:31:42 PM PDT 23
Finished Oct 15 01:31:43 PM PDT 23
Peak memory 215076 kb
Host smart-80355809-d4ba-4375-9cfd-7ff8e50d1dd2
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058823037 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.3058823037
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.225852974
Short name T40
Test name
Test status
Simulation time 46358029 ps
CPU time 0.92 seconds
Started Oct 15 01:31:49 PM PDT 23
Finished Oct 15 01:31:50 PM PDT 23
Peak memory 215268 kb
Host smart-85457fa3-940c-4835-a753-e5c62f5001c0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225852974 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_di
sable_auto_req_mode.225852974
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.3432140062
Short name T153
Test name
Test status
Simulation time 53314248 ps
CPU time 0.83 seconds
Started Oct 15 01:31:39 PM PDT 23
Finished Oct 15 01:31:41 PM PDT 23
Peak memory 215204 kb
Host smart-553ad003-136c-4a6d-9e89-e9f3da0d05fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432140062 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.3432140062
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.1901106164
Short name T278
Test name
Test status
Simulation time 73028632 ps
CPU time 1.08 seconds
Started Oct 15 01:31:43 PM PDT 23
Finished Oct 15 01:31:45 PM PDT 23
Peak memory 205636 kb
Host smart-eb62282e-55ac-4490-9348-43ce8e2efcf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901106164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.1901106164
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.1554284686
Short name T490
Test name
Test status
Simulation time 20649823 ps
CPU time 1.07 seconds
Started Oct 15 01:31:42 PM PDT 23
Finished Oct 15 01:31:44 PM PDT 23
Peak memory 215280 kb
Host smart-47dcd384-13d1-43ff-a5db-4a24ca9fc7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554284686 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.1554284686
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.3815483990
Short name T538
Test name
Test status
Simulation time 82918840 ps
CPU time 0.83 seconds
Started Oct 15 01:32:16 PM PDT 23
Finished Oct 15 01:32:18 PM PDT 23
Peak memory 205344 kb
Host smart-b319f6c6-ed50-4f2e-873f-5677373506a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815483990 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.3815483990
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.3862145488
Short name T268
Test name
Test status
Simulation time 115625772 ps
CPU time 1.21 seconds
Started Oct 15 01:31:41 PM PDT 23
Finished Oct 15 01:31:43 PM PDT 23
Peak memory 206716 kb
Host smart-b1d71878-9e43-4c6b-b963-5610771486da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862145488 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.3862145488
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.4249154514
Short name T471
Test name
Test status
Simulation time 638866301322 ps
CPU time 1412.86 seconds
Started Oct 15 01:31:45 PM PDT 23
Finished Oct 15 01:55:18 PM PDT 23
Peak memory 218636 kb
Host smart-d6110043-1b35-46b8-a292-ad615d038850
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249154514 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.4249154514
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.1334537790
Short name T533
Test name
Test status
Simulation time 17080247 ps
CPU time 0.94 seconds
Started Oct 15 01:31:43 PM PDT 23
Finished Oct 15 01:31:44 PM PDT 23
Peak memory 206728 kb
Host smart-7b6fabea-b282-433e-82f6-e679545eb088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334537790 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.1334537790
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.2717061193
Short name T67
Test name
Test status
Simulation time 27702603 ps
CPU time 0.93 seconds
Started Oct 15 01:32:29 PM PDT 23
Finished Oct 15 01:32:31 PM PDT 23
Peak memory 205356 kb
Host smart-0923a8be-6565-4d51-807b-8a2a4db11d8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717061193 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.2717061193
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.813434286
Short name T621
Test name
Test status
Simulation time 46694016 ps
CPU time 0.96 seconds
Started Oct 15 01:31:46 PM PDT 23
Finished Oct 15 01:31:47 PM PDT 23
Peak memory 215280 kb
Host smart-57c675f3-8925-4bd5-bce6-6a45e040f80a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813434286 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_di
sable_auto_req_mode.813434286
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.2711647817
Short name T252
Test name
Test status
Simulation time 30007785 ps
CPU time 1.16 seconds
Started Oct 15 01:32:11 PM PDT 23
Finished Oct 15 01:32:12 PM PDT 23
Peak memory 217660 kb
Host smart-544afe86-a6d4-4a3b-bb35-1d09e4042248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711647817 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.2711647817
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.1186596055
Short name T276
Test name
Test status
Simulation time 43687915 ps
CPU time 1 seconds
Started Oct 15 01:31:42 PM PDT 23
Finished Oct 15 01:31:44 PM PDT 23
Peak memory 205736 kb
Host smart-9566a973-9f15-4e50-8f85-bb5839efb776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186596055 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.1186596055
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.2388947315
Short name T676
Test name
Test status
Simulation time 32571785 ps
CPU time 0.89 seconds
Started Oct 15 01:31:45 PM PDT 23
Finished Oct 15 01:31:46 PM PDT 23
Peak memory 215144 kb
Host smart-65374c36-e1cc-4de2-a9bc-426dd7277e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388947315 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.2388947315
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.2456109983
Short name T331
Test name
Test status
Simulation time 15416971 ps
CPU time 0.89 seconds
Started Oct 15 01:31:47 PM PDT 23
Finished Oct 15 01:31:49 PM PDT 23
Peak memory 205404 kb
Host smart-0eed4a27-ccf1-4e1c-86e2-d18c942fd9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456109983 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.2456109983
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.671869750
Short name T333
Test name
Test status
Simulation time 609894323 ps
CPU time 3.19 seconds
Started Oct 15 01:31:39 PM PDT 23
Finished Oct 15 01:31:44 PM PDT 23
Peak memory 206436 kb
Host smart-cd89b07b-17a2-4e4d-923c-095faabeaef8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671869750 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.671869750
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.1070488662
Short name T594
Test name
Test status
Simulation time 32903964258 ps
CPU time 792.7 seconds
Started Oct 15 01:31:46 PM PDT 23
Finished Oct 15 01:44:59 PM PDT 23
Peak memory 217168 kb
Host smart-1b1e17f2-ff42-42e0-9ae6-b7c5d147fba5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070488662 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.1070488662
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.196267741
Short name T300
Test name
Test status
Simulation time 125928316 ps
CPU time 0.92 seconds
Started Oct 15 01:31:40 PM PDT 23
Finished Oct 15 01:31:42 PM PDT 23
Peak memory 206092 kb
Host smart-484e04db-a959-43ae-b8e3-e48fb24a16f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196267741 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.196267741
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.207634355
Short name T647
Test name
Test status
Simulation time 18536406 ps
CPU time 0.93 seconds
Started Oct 15 01:32:27 PM PDT 23
Finished Oct 15 01:32:28 PM PDT 23
Peak memory 205452 kb
Host smart-a29c36bd-6029-4ffb-8da8-3f31b75fb57f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207634355 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.207634355
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.398261029
Short name T239
Test name
Test status
Simulation time 19296560 ps
CPU time 0.81 seconds
Started Oct 15 01:32:28 PM PDT 23
Finished Oct 15 01:32:30 PM PDT 23
Peak memory 215108 kb
Host smart-5f7e90a8-36be-4372-930f-8bf359e1a26f
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398261029 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.398261029
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.2583537390
Short name T649
Test name
Test status
Simulation time 57963200 ps
CPU time 1.12 seconds
Started Oct 15 01:31:44 PM PDT 23
Finished Oct 15 01:31:45 PM PDT 23
Peak memory 215312 kb
Host smart-a93fdaf1-fa5b-4045-a526-ca0f249380b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583537390 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.2583537390
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.3484920876
Short name T92
Test name
Test status
Simulation time 19880720 ps
CPU time 1.03 seconds
Started Oct 15 01:32:14 PM PDT 23
Finished Oct 15 01:32:15 PM PDT 23
Peak memory 216636 kb
Host smart-7403367b-7b30-4f2b-b9e4-4acf08b6b3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484920876 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.3484920876
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.4049535769
Short name T651
Test name
Test status
Simulation time 131356237 ps
CPU time 1.31 seconds
Started Oct 15 01:32:29 PM PDT 23
Finished Oct 15 01:32:30 PM PDT 23
Peak memory 205864 kb
Host smart-fcc43500-24d8-4191-a2e1-705ff8b45b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049535769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.4049535769
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.1945067757
Short name T630
Test name
Test status
Simulation time 31159755 ps
CPU time 0.8 seconds
Started Oct 15 01:32:10 PM PDT 23
Finished Oct 15 01:32:11 PM PDT 23
Peak memory 214948 kb
Host smart-2bae5224-271f-402d-ac67-bb38eb350e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945067757 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.1945067757
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.771418494
Short name T644
Test name
Test status
Simulation time 18418426 ps
CPU time 0.82 seconds
Started Oct 15 01:32:16 PM PDT 23
Finished Oct 15 01:32:17 PM PDT 23
Peak memory 205376 kb
Host smart-0a3b55ee-74b7-461b-bdfb-ff8d0ba10841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771418494 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.771418494
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.3262784956
Short name T79
Test name
Test status
Simulation time 776899178 ps
CPU time 4.11 seconds
Started Oct 15 01:32:10 PM PDT 23
Finished Oct 15 01:32:14 PM PDT 23
Peak memory 206716 kb
Host smart-eee3d5fc-3dae-4db0-b5fd-b6e04dbd8669
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262784956 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3262784956
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_alert.1585246924
Short name T639
Test name
Test status
Simulation time 129709386 ps
CPU time 0.96 seconds
Started Oct 15 01:31:58 PM PDT 23
Finished Oct 15 01:31:59 PM PDT 23
Peak memory 206068 kb
Host smart-b1c16996-f1de-4e37-8965-5549a06925ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585246924 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.1585246924
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.2166646675
Short name T585
Test name
Test status
Simulation time 65705238 ps
CPU time 0.83 seconds
Started Oct 15 01:32:30 PM PDT 23
Finished Oct 15 01:32:32 PM PDT 23
Peak memory 205412 kb
Host smart-64bd3a23-2480-4af9-9a61-008f49eceed4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166646675 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.2166646675
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.3925892879
Short name T666
Test name
Test status
Simulation time 21848329 ps
CPU time 0.95 seconds
Started Oct 15 01:32:16 PM PDT 23
Finished Oct 15 01:32:18 PM PDT 23
Peak memory 215280 kb
Host smart-f2c15b81-e8e5-4f4f-ae4b-a6663f954ba2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925892879 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.3925892879
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.1597164419
Short name T501
Test name
Test status
Simulation time 68922628 ps
CPU time 1.06 seconds
Started Oct 15 01:32:28 PM PDT 23
Finished Oct 15 01:32:29 PM PDT 23
Peak memory 217928 kb
Host smart-88b16360-a59b-4e4d-8192-0598a82ec5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597164419 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.1597164419
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.2023004529
Short name T614
Test name
Test status
Simulation time 158872929 ps
CPU time 1.11 seconds
Started Oct 15 01:32:17 PM PDT 23
Finished Oct 15 01:32:18 PM PDT 23
Peak memory 214916 kb
Host smart-fcaae8fc-514b-4e65-8ea9-f3663f6a67e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023004529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.2023004529
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.2652502458
Short name T133
Test name
Test status
Simulation time 19393656 ps
CPU time 1 seconds
Started Oct 15 01:31:43 PM PDT 23
Finished Oct 15 01:31:45 PM PDT 23
Peak memory 215356 kb
Host smart-4dbff2e0-73b4-4ea4-9f5e-b9d16b744f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652502458 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.2652502458
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.535746678
Short name T200
Test name
Test status
Simulation time 16655299 ps
CPU time 0.9 seconds
Started Oct 15 01:31:44 PM PDT 23
Finished Oct 15 01:31:46 PM PDT 23
Peak memory 205540 kb
Host smart-e61127a7-e296-446b-87f6-76f1e3969407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535746678 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.535746678
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.3295443528
Short name T275
Test name
Test status
Simulation time 124256784 ps
CPU time 2.91 seconds
Started Oct 15 01:31:43 PM PDT 23
Finished Oct 15 01:31:47 PM PDT 23
Peak memory 206644 kb
Host smart-264df969-c6bc-471b-a874-515a34fa893e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295443528 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.3295443528
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.2466908821
Short name T102
Test name
Test status
Simulation time 241898934449 ps
CPU time 1647.71 seconds
Started Oct 15 01:31:43 PM PDT 23
Finished Oct 15 01:59:12 PM PDT 23
Peak memory 221012 kb
Host smart-4ed8f9db-554e-435a-b5ec-d55857eb5f0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466908821 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.2466908821
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.1931912143
Short name T549
Test name
Test status
Simulation time 32072233 ps
CPU time 0.93 seconds
Started Oct 15 01:32:30 PM PDT 23
Finished Oct 15 01:32:32 PM PDT 23
Peak memory 206016 kb
Host smart-b1ae47c2-a92f-477f-bbe4-4e552e756a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931912143 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.1931912143
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.3138484300
Short name T514
Test name
Test status
Simulation time 28161675 ps
CPU time 0.92 seconds
Started Oct 15 01:31:49 PM PDT 23
Finished Oct 15 01:31:50 PM PDT 23
Peak memory 205356 kb
Host smart-a31891b3-0e49-4a71-ac5a-8e9abee8323e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138484300 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.3138484300
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.2247861598
Short name T646
Test name
Test status
Simulation time 21119090 ps
CPU time 0.87 seconds
Started Oct 15 01:32:15 PM PDT 23
Finished Oct 15 01:32:16 PM PDT 23
Peak memory 215048 kb
Host smart-7413959a-e388-42cf-9560-f1910166da5b
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247861598 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.2247861598
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.606503304
Short name T98
Test name
Test status
Simulation time 97791257 ps
CPU time 0.94 seconds
Started Oct 15 01:31:57 PM PDT 23
Finished Oct 15 01:31:58 PM PDT 23
Peak memory 215208 kb
Host smart-c504748e-1118-4543-b352-23fd78db8b17
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606503304 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_di
sable_auto_req_mode.606503304
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.1052026015
Short name T160
Test name
Test status
Simulation time 84011144 ps
CPU time 1.05 seconds
Started Oct 15 01:32:13 PM PDT 23
Finished Oct 15 01:32:14 PM PDT 23
Peak memory 229444 kb
Host smart-d457f330-a56d-49af-be5b-543f6660b159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052026015 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.1052026015
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.2291800842
Short name T672
Test name
Test status
Simulation time 34782173 ps
CPU time 1.14 seconds
Started Oct 15 01:32:11 PM PDT 23
Finished Oct 15 01:32:12 PM PDT 23
Peak memory 206164 kb
Host smart-08c1c769-90e0-4df1-b39f-f465f57e3d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291800842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.2291800842
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.3168239132
Short name T695
Test name
Test status
Simulation time 30181483 ps
CPU time 0.86 seconds
Started Oct 15 01:32:28 PM PDT 23
Finished Oct 15 01:32:29 PM PDT 23
Peak memory 215244 kb
Host smart-22b56503-5148-43e5-bf94-0df868bb7ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168239132 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.3168239132
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.3164775550
Short name T572
Test name
Test status
Simulation time 21936491 ps
CPU time 0.82 seconds
Started Oct 15 01:31:46 PM PDT 23
Finished Oct 15 01:31:47 PM PDT 23
Peak memory 205396 kb
Host smart-30797389-56b6-4733-842c-7b6f9ba84303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164775550 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.3164775550
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.1177084798
Short name T484
Test name
Test status
Simulation time 152338278 ps
CPU time 1.96 seconds
Started Oct 15 01:31:56 PM PDT 23
Finished Oct 15 01:31:58 PM PDT 23
Peak memory 206384 kb
Host smart-85512bdf-b63d-41b7-9438-b12e56e307c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177084798 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.1177084798
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.3712676952
Short name T541
Test name
Test status
Simulation time 583698060879 ps
CPU time 981.61 seconds
Started Oct 15 01:31:43 PM PDT 23
Finished Oct 15 01:48:06 PM PDT 23
Peak memory 216176 kb
Host smart-657e2bc2-a1c5-4945-b8ce-fcd3ef93f717
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712676952 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.3712676952
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.3480173034
Short name T618
Test name
Test status
Simulation time 26358709 ps
CPU time 0.98 seconds
Started Oct 15 01:32:10 PM PDT 23
Finished Oct 15 01:32:11 PM PDT 23
Peak memory 206456 kb
Host smart-a4d3299f-2b0a-497f-8ac3-6949da9a1353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480173034 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.3480173034
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.846818245
Short name T717
Test name
Test status
Simulation time 13311992 ps
CPU time 0.86 seconds
Started Oct 15 01:32:37 PM PDT 23
Finished Oct 15 01:32:38 PM PDT 23
Peak memory 205348 kb
Host smart-e8e26d72-b621-4d87-91d1-f2489db1afb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846818245 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.846818245
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.907367478
Short name T187
Test name
Test status
Simulation time 80419984 ps
CPU time 0.84 seconds
Started Oct 15 01:32:31 PM PDT 23
Finished Oct 15 01:32:32 PM PDT 23
Peak memory 214988 kb
Host smart-882b9b7a-e17d-487b-9684-48441d814559
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907367478 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.907367478
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.1113338342
Short name T575
Test name
Test status
Simulation time 29827715 ps
CPU time 1.08 seconds
Started Oct 15 01:32:37 PM PDT 23
Finished Oct 15 01:32:39 PM PDT 23
Peak memory 215320 kb
Host smart-4cff1be3-645e-4bda-82c1-a7c56564073c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113338342 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.1113338342
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.1219457251
Short name T602
Test name
Test status
Simulation time 20253301 ps
CPU time 1.11 seconds
Started Oct 15 01:32:17 PM PDT 23
Finished Oct 15 01:32:19 PM PDT 23
Peak memory 222748 kb
Host smart-87c90f13-d639-45c6-afe9-df01a87038bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219457251 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1219457251
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_intr.358337134
Short name T699
Test name
Test status
Simulation time 18685358 ps
CPU time 1.12 seconds
Started Oct 15 01:32:30 PM PDT 23
Finished Oct 15 01:32:32 PM PDT 23
Peak memory 222660 kb
Host smart-4e51463b-3b45-42ce-8a42-3acdc41df4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358337134 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.358337134
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.401795182
Short name T319
Test name
Test status
Simulation time 23435789 ps
CPU time 0.89 seconds
Started Oct 15 01:31:46 PM PDT 23
Finished Oct 15 01:31:48 PM PDT 23
Peak memory 205420 kb
Host smart-7905700f-5c9b-4787-8214-892cd2e81ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401795182 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.401795182
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.1248216234
Short name T101
Test name
Test status
Simulation time 232200829 ps
CPU time 4.18 seconds
Started Oct 15 01:32:12 PM PDT 23
Finished Oct 15 01:32:16 PM PDT 23
Peak memory 206764 kb
Host smart-a52ae931-96f5-47f3-9059-fd69e2e16715
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248216234 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.1248216234
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.72822928
Short name T551
Test name
Test status
Simulation time 42582859281 ps
CPU time 924.06 seconds
Started Oct 15 01:32:15 PM PDT 23
Finished Oct 15 01:47:39 PM PDT 23
Peak memory 216200 kb
Host smart-ce09c15c-1d06-46d8-b65d-8c3af9c9e8b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72822928 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.72822928
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.3544458670
Short name T669
Test name
Test status
Simulation time 74857593 ps
CPU time 0.89 seconds
Started Oct 15 01:33:05 PM PDT 23
Finished Oct 15 01:33:07 PM PDT 23
Peak memory 206048 kb
Host smart-3bbc467f-db48-4cd5-b1a4-f4237b5ca2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544458670 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.3544458670
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.2283070666
Short name T201
Test name
Test status
Simulation time 20235030 ps
CPU time 0.79 seconds
Started Oct 15 01:33:14 PM PDT 23
Finished Oct 15 01:33:15 PM PDT 23
Peak memory 205364 kb
Host smart-b267afbd-dc85-4063-8bcc-b16b06601492
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283070666 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.2283070666
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.2676438550
Short name T104
Test name
Test status
Simulation time 31694664 ps
CPU time 0.83 seconds
Started Oct 15 01:33:07 PM PDT 23
Finished Oct 15 01:33:08 PM PDT 23
Peak memory 215080 kb
Host smart-5e7605b4-f5fe-44ba-8d41-c71c7b99075d
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676438550 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.2676438550
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.1150311564
Short name T166
Test name
Test status
Simulation time 24790553 ps
CPU time 1.11 seconds
Started Oct 15 01:33:10 PM PDT 23
Finished Oct 15 01:33:12 PM PDT 23
Peak memory 215228 kb
Host smart-fbbf5ae0-d7ec-4978-acbd-c55663c682e6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150311564 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.1150311564
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.2753203435
Short name T173
Test name
Test status
Simulation time 18743224 ps
CPU time 1.02 seconds
Started Oct 15 01:32:55 PM PDT 23
Finished Oct 15 01:32:56 PM PDT 23
Peak memory 216564 kb
Host smart-76fabfa3-fe1b-468f-8c44-b4e185b13241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753203435 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.2753203435
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.3006478558
Short name T139
Test name
Test status
Simulation time 56840960 ps
CPU time 1.07 seconds
Started Oct 15 01:33:09 PM PDT 23
Finished Oct 15 01:33:11 PM PDT 23
Peak memory 214904 kb
Host smart-0aab917a-66df-4f83-b6dc-a855180b21d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006478558 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.3006478558
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_smoke.3446578748
Short name T654
Test name
Test status
Simulation time 14055764 ps
CPU time 0.86 seconds
Started Oct 15 01:32:15 PM PDT 23
Finished Oct 15 01:32:16 PM PDT 23
Peak memory 205656 kb
Host smart-2260d914-b535-48f5-b085-b130457ed77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446578748 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.3446578748
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.2968456674
Short name T640
Test name
Test status
Simulation time 289794160 ps
CPU time 2.96 seconds
Started Oct 15 01:32:13 PM PDT 23
Finished Oct 15 01:32:16 PM PDT 23
Peak memory 206724 kb
Host smart-7b13e633-4901-4453-8c75-f733c5e05095
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968456674 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.2968456674
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.2778893451
Short name T190
Test name
Test status
Simulation time 60809401462 ps
CPU time 357.64 seconds
Started Oct 15 01:33:12 PM PDT 23
Finished Oct 15 01:39:11 PM PDT 23
Peak memory 223308 kb
Host smart-623c3f16-bdfa-451d-9542-4818e189d6d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778893451 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.2778893451
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.2768125103
Short name T677
Test name
Test status
Simulation time 17702754 ps
CPU time 0.97 seconds
Started Oct 15 01:33:45 PM PDT 23
Finished Oct 15 01:33:47 PM PDT 23
Peak memory 206412 kb
Host smart-d443d147-d39c-4ca8-b95f-62aae9783d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768125103 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.2768125103
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.82373506
Short name T555
Test name
Test status
Simulation time 46454583 ps
CPU time 0.81 seconds
Started Oct 15 01:33:14 PM PDT 23
Finished Oct 15 01:33:15 PM PDT 23
Peak memory 205928 kb
Host smart-028f5680-85a6-42e8-8f92-e0f38d273a2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82373506 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.82373506
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.2491984247
Short name T29
Test name
Test status
Simulation time 17810259 ps
CPU time 0.81 seconds
Started Oct 15 01:33:47 PM PDT 23
Finished Oct 15 01:33:49 PM PDT 23
Peak memory 215064 kb
Host smart-d932bc33-5332-4f89-bea3-d0961f9e39c7
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491984247 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.2491984247
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.3325128908
Short name T141
Test name
Test status
Simulation time 49369747 ps
CPU time 1.03 seconds
Started Oct 15 01:33:14 PM PDT 23
Finished Oct 15 01:33:15 PM PDT 23
Peak memory 215252 kb
Host smart-6b131ecc-2829-400d-8e0e-7d9d2142c438
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325128908 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.3325128908
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.4092507689
Short name T244
Test name
Test status
Simulation time 30863078 ps
CPU time 0.96 seconds
Started Oct 15 01:33:47 PM PDT 23
Finished Oct 15 01:33:49 PM PDT 23
Peak memory 215500 kb
Host smart-029b67bf-1f3e-4d14-92cb-22e286628601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092507689 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.4092507689
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.3317414814
Short name T81
Test name
Test status
Simulation time 26110609 ps
CPU time 1 seconds
Started Oct 15 01:33:37 PM PDT 23
Finished Oct 15 01:33:38 PM PDT 23
Peak memory 206032 kb
Host smart-44f01f1e-3fe8-4b32-a563-5f2adbbad62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317414814 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.3317414814
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_smoke.1710000125
Short name T476
Test name
Test status
Simulation time 13384860 ps
CPU time 0.91 seconds
Started Oct 15 01:33:12 PM PDT 23
Finished Oct 15 01:33:14 PM PDT 23
Peak memory 205600 kb
Host smart-c010a4f8-3d54-499c-a19d-1c44e0ce69c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710000125 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.1710000125
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.419269640
Short name T497
Test name
Test status
Simulation time 137467363 ps
CPU time 3.04 seconds
Started Oct 15 01:33:39 PM PDT 23
Finished Oct 15 01:33:43 PM PDT 23
Peak memory 206372 kb
Host smart-566a06d1-4af1-4c2e-83cb-db74b8327649
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419269640 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.419269640
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.2012756106
Short name T578
Test name
Test status
Simulation time 407684519046 ps
CPU time 1769.5 seconds
Started Oct 15 01:33:00 PM PDT 23
Finished Oct 15 02:02:32 PM PDT 23
Peak memory 220144 kb
Host smart-5eca4559-d29e-4c48-840c-4c2a02af9bff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012756106 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.2012756106
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.1862617772
Short name T306
Test name
Test status
Simulation time 26455350 ps
CPU time 0.91 seconds
Started Oct 15 01:33:59 PM PDT 23
Finished Oct 15 01:34:01 PM PDT 23
Peak memory 206036 kb
Host smart-fea280ac-d20c-4a9c-82a0-1da0699b2989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862617772 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.1862617772
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.1883608266
Short name T581
Test name
Test status
Simulation time 76039690 ps
CPU time 0.88 seconds
Started Oct 15 01:34:03 PM PDT 23
Finished Oct 15 01:34:04 PM PDT 23
Peak memory 205168 kb
Host smart-8e2f2ec6-b7b0-42bb-bf72-0023eaa55a17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883608266 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.1883608266
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.2953051695
Short name T37
Test name
Test status
Simulation time 48336544 ps
CPU time 1.07 seconds
Started Oct 15 01:33:17 PM PDT 23
Finished Oct 15 01:33:18 PM PDT 23
Peak memory 215248 kb
Host smart-0ec28464-61f9-4456-82ea-75a52962b706
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953051695 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.2953051695
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.1078003719
Short name T291
Test name
Test status
Simulation time 18250253 ps
CPU time 0.99 seconds
Started Oct 15 01:32:33 PM PDT 23
Finished Oct 15 01:32:35 PM PDT 23
Peak memory 216540 kb
Host smart-89011dd3-3110-46a2-b0ec-9e18c8bd67d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078003719 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.1078003719
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.3864542875
Short name T80
Test name
Test status
Simulation time 61740899 ps
CPU time 1.08 seconds
Started Oct 15 01:33:15 PM PDT 23
Finished Oct 15 01:33:17 PM PDT 23
Peak memory 205780 kb
Host smart-2c2946d3-9215-489b-9eff-b7ecb56b23ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864542875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.3864542875
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.1949241126
Short name T131
Test name
Test status
Simulation time 28847478 ps
CPU time 0.81 seconds
Started Oct 15 01:33:18 PM PDT 23
Finished Oct 15 01:33:20 PM PDT 23
Peak memory 215256 kb
Host smart-b2d6a180-41af-4eff-a59c-04834de92a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949241126 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.1949241126
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.725881786
Short name T469
Test name
Test status
Simulation time 12728030 ps
CPU time 0.84 seconds
Started Oct 15 01:31:49 PM PDT 23
Finished Oct 15 01:31:50 PM PDT 23
Peak memory 205520 kb
Host smart-dcf7e211-0778-440c-a014-b420192d421a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725881786 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.725881786
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.2108226308
Short name T612
Test name
Test status
Simulation time 206302326 ps
CPU time 4.37 seconds
Started Oct 15 01:33:12 PM PDT 23
Finished Oct 15 01:33:18 PM PDT 23
Peak memory 206708 kb
Host smart-3dfc1402-d1a1-4245-91cb-c5afa003dbe1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108226308 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.2108226308
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.156517865
Short name T237
Test name
Test status
Simulation time 20929246832 ps
CPU time 228.28 seconds
Started Oct 15 01:33:17 PM PDT 23
Finished Oct 15 01:37:06 PM PDT 23
Peak memory 215256 kb
Host smart-6b0adde6-7f2d-416b-921b-8e6c15f668ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156517865 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.156517865
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.226081478
Short name T606
Test name
Test status
Simulation time 27596688 ps
CPU time 0.99 seconds
Started Oct 15 01:31:35 PM PDT 23
Finished Oct 15 01:31:36 PM PDT 23
Peak memory 206736 kb
Host smart-f377c616-9283-45f9-8e39-74df93c7b4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226081478 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.226081478
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.2916026870
Short name T631
Test name
Test status
Simulation time 17067037 ps
CPU time 0.89 seconds
Started Oct 15 01:31:02 PM PDT 23
Finished Oct 15 01:31:04 PM PDT 23
Peak memory 205416 kb
Host smart-89bf50de-bb77-410f-992e-854b9d202357
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916026870 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.2916026870
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.3661792915
Short name T172
Test name
Test status
Simulation time 11700069 ps
CPU time 0.83 seconds
Started Oct 15 01:31:40 PM PDT 23
Finished Oct 15 01:31:42 PM PDT 23
Peak memory 215032 kb
Host smart-9b140d0a-c57b-477c-be10-bb3c575f37a2
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661792915 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.3661792915
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.2765482994
Short name T556
Test name
Test status
Simulation time 47270294 ps
CPU time 0.99 seconds
Started Oct 15 01:31:35 PM PDT 23
Finished Oct 15 01:31:36 PM PDT 23
Peak memory 215212 kb
Host smart-3f9c7492-a005-470d-a557-0d7ad1efe799
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765482994 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.2765482994
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.2406139087
Short name T314
Test name
Test status
Simulation time 33251599 ps
CPU time 1 seconds
Started Oct 15 01:31:34 PM PDT 23
Finished Oct 15 01:31:36 PM PDT 23
Peak memory 215384 kb
Host smart-005e907f-e26a-466f-bbe3-7b9b1a04ddbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406139087 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.2406139087
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.3658960591
Short name T270
Test name
Test status
Simulation time 18110354 ps
CPU time 1.09 seconds
Started Oct 15 01:31:35 PM PDT 23
Finished Oct 15 01:31:37 PM PDT 23
Peak memory 206252 kb
Host smart-c351c1e8-a094-4629-9f45-625280671a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658960591 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.3658960591
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.2958631634
Short name T126
Test name
Test status
Simulation time 26363259 ps
CPU time 1.13 seconds
Started Oct 15 01:31:34 PM PDT 23
Finished Oct 15 01:31:37 PM PDT 23
Peak memory 226340 kb
Host smart-bfc00dbc-b855-402d-b1a0-cfbd5548dda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958631634 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.2958631634
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_sec_cm.4032370720
Short name T22
Test name
Test status
Simulation time 395927770 ps
CPU time 3.41 seconds
Started Oct 15 01:31:37 PM PDT 23
Finished Oct 15 01:31:41 PM PDT 23
Peak memory 233152 kb
Host smart-0c8e1c51-e4f4-404f-b689-227348278ba4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032370720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.4032370720
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.3794170295
Short name T320
Test name
Test status
Simulation time 15130785 ps
CPU time 0.9 seconds
Started Oct 15 01:31:36 PM PDT 23
Finished Oct 15 01:31:37 PM PDT 23
Peak memory 205584 kb
Host smart-82a0e0e1-8b00-42d0-b584-d6a8ae11483b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794170295 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3794170295
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_alert.3092426983
Short name T521
Test name
Test status
Simulation time 19401470 ps
CPU time 0.98 seconds
Started Oct 15 01:32:30 PM PDT 23
Finished Oct 15 01:32:32 PM PDT 23
Peak memory 206388 kb
Host smart-7064531d-25a7-4a7b-8000-36f56a01d598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092426983 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.3092426983
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.366856089
Short name T580
Test name
Test status
Simulation time 44918422 ps
CPU time 0.86 seconds
Started Oct 15 01:32:16 PM PDT 23
Finished Oct 15 01:32:17 PM PDT 23
Peak memory 205900 kb
Host smart-34fccb7d-b65d-4bf4-a30a-3d8a8074c8fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366856089 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.366856089
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.2315463678
Short name T82
Test name
Test status
Simulation time 34464327 ps
CPU time 0.8 seconds
Started Oct 15 01:32:30 PM PDT 23
Finished Oct 15 01:32:32 PM PDT 23
Peak memory 215056 kb
Host smart-d747ec22-a783-41e9-a83c-017e75815a98
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315463678 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.2315463678
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.876592603
Short name T550
Test name
Test status
Simulation time 18981443 ps
CPU time 0.97 seconds
Started Oct 15 01:32:14 PM PDT 23
Finished Oct 15 01:32:16 PM PDT 23
Peak memory 215240 kb
Host smart-774d1249-a32d-4acd-b2ff-6054787d7186
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876592603 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_di
sable_auto_req_mode.876592603
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.523644844
Short name T235
Test name
Test status
Simulation time 51487248 ps
CPU time 0.98 seconds
Started Oct 15 01:32:59 PM PDT 23
Finished Oct 15 01:33:02 PM PDT 23
Peak memory 215636 kb
Host smart-c86c5486-6b2d-4618-84b7-8543444fcd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523644844 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.523644844
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_intr.847167357
Short name T30
Test name
Test status
Simulation time 47285424 ps
CPU time 0.85 seconds
Started Oct 15 01:34:10 PM PDT 23
Finished Oct 15 01:34:11 PM PDT 23
Peak memory 215020 kb
Host smart-d9a27edf-1a98-471e-bdb6-1c2c96f13030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847167357 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.847167357
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.1614940667
Short name T332
Test name
Test status
Simulation time 181956576 ps
CPU time 0.89 seconds
Started Oct 15 01:31:50 PM PDT 23
Finished Oct 15 01:31:51 PM PDT 23
Peak memory 205684 kb
Host smart-5c62d184-08f5-4880-82b1-5f2c41277d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614940667 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.1614940667
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.1895016670
Short name T267
Test name
Test status
Simulation time 143953730 ps
CPU time 3.38 seconds
Started Oct 15 01:33:50 PM PDT 23
Finished Oct 15 01:33:54 PM PDT 23
Peak memory 206184 kb
Host smart-a0220fe9-c31c-4267-b437-2ad3a7186f96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895016670 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.1895016670
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.2661772571
Short name T728
Test name
Test status
Simulation time 98854911468 ps
CPU time 572.87 seconds
Started Oct 15 01:31:44 PM PDT 23
Finished Oct 15 01:41:18 PM PDT 23
Peak memory 215228 kb
Host smart-7ca6732e-f2dc-4258-bd38-06e21b803c9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661772571 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.2661772571
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.4209140489
Short name T121
Test name
Test status
Simulation time 20049452 ps
CPU time 0.94 seconds
Started Oct 15 01:32:32 PM PDT 23
Finished Oct 15 01:32:33 PM PDT 23
Peak memory 205864 kb
Host smart-292f98d5-3224-4372-b35a-0181389fa9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209140489 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.4209140489
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.558618140
Short name T94
Test name
Test status
Simulation time 39539869 ps
CPU time 0.78 seconds
Started Oct 15 01:32:34 PM PDT 23
Finished Oct 15 01:32:35 PM PDT 23
Peak memory 205180 kb
Host smart-c7bf4a9a-0a28-4fab-8a6c-39b738ae99b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558618140 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.558618140
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.3278732478
Short name T21
Test name
Test status
Simulation time 15634321 ps
CPU time 0.87 seconds
Started Oct 15 01:32:33 PM PDT 23
Finished Oct 15 01:32:35 PM PDT 23
Peak memory 215052 kb
Host smart-5dd04de1-baef-48df-a07e-85ac57f1a4b0
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278732478 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.3278732478
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.2520649316
Short name T157
Test name
Test status
Simulation time 20730739 ps
CPU time 1.06 seconds
Started Oct 15 01:32:33 PM PDT 23
Finished Oct 15 01:32:35 PM PDT 23
Peak memory 215308 kb
Host smart-1ba9d18d-8b99-4fd3-b4ff-a03b9b26b448
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520649316 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.2520649316
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.1569823156
Short name T156
Test name
Test status
Simulation time 26967448 ps
CPU time 1.16 seconds
Started Oct 15 01:33:05 PM PDT 23
Finished Oct 15 01:33:06 PM PDT 23
Peak memory 215692 kb
Host smart-9df12585-04b1-43ca-88f8-f63951623d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569823156 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.1569823156
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.967516139
Short name T83
Test name
Test status
Simulation time 67545345 ps
CPU time 1.31 seconds
Started Oct 15 01:32:38 PM PDT 23
Finished Oct 15 01:32:39 PM PDT 23
Peak memory 205788 kb
Host smart-88bd7d84-67be-4b6f-a8c3-c4639c262baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967516139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.967516139
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.3119440250
Short name T491
Test name
Test status
Simulation time 24956460 ps
CPU time 0.97 seconds
Started Oct 15 01:32:14 PM PDT 23
Finished Oct 15 01:32:16 PM PDT 23
Peak memory 222820 kb
Host smart-5a3f19b7-5801-4d0f-ba45-e09c312ba97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119440250 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.3119440250
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.1768296830
Short name T642
Test name
Test status
Simulation time 37471129 ps
CPU time 0.85 seconds
Started Oct 15 01:32:13 PM PDT 23
Finished Oct 15 01:32:14 PM PDT 23
Peak memory 205520 kb
Host smart-14da4513-c9d3-402a-8fc5-e8cbb58b21b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768296830 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.1768296830
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.844507841
Short name T603
Test name
Test status
Simulation time 230239542 ps
CPU time 1.26 seconds
Started Oct 15 01:32:13 PM PDT 23
Finished Oct 15 01:32:15 PM PDT 23
Peak memory 204984 kb
Host smart-7fb53512-2870-42d2-bb53-ce92678cd257
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844507841 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.844507841
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.1427991241
Short name T529
Test name
Test status
Simulation time 61001891628 ps
CPU time 1454.3 seconds
Started Oct 15 01:32:12 PM PDT 23
Finished Oct 15 01:56:27 PM PDT 23
Peak memory 219808 kb
Host smart-ad9cfb50-b6f6-49ea-9495-c4e6f723035c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427991241 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.1427991241
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.2357077163
Short name T117
Test name
Test status
Simulation time 52969861 ps
CPU time 0.95 seconds
Started Oct 15 01:32:16 PM PDT 23
Finished Oct 15 01:32:18 PM PDT 23
Peak memory 206704 kb
Host smart-530082e6-f6cb-4c3e-874d-09c98cf0f965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357077163 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.2357077163
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.4166214385
Short name T65
Test name
Test status
Simulation time 28027675 ps
CPU time 0.9 seconds
Started Oct 15 01:33:05 PM PDT 23
Finished Oct 15 01:33:07 PM PDT 23
Peak memory 205412 kb
Host smart-0c246a35-f0ab-4a3b-96e2-a6a9ba76f869
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166214385 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.4166214385
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.2705184948
Short name T188
Test name
Test status
Simulation time 11821803 ps
CPU time 0.82 seconds
Started Oct 15 01:32:33 PM PDT 23
Finished Oct 15 01:32:35 PM PDT 23
Peak memory 215044 kb
Host smart-7e42b8c2-58e8-4a56-b5a5-5235ca66b0d7
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705184948 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.2705184948
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.3442053034
Short name T703
Test name
Test status
Simulation time 146085387 ps
CPU time 0.94 seconds
Started Oct 15 01:32:13 PM PDT 23
Finished Oct 15 01:32:15 PM PDT 23
Peak memory 215196 kb
Host smart-8650db25-d4aa-4df7-a2f5-98e21bbc1e93
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442053034 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.3442053034
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.1334487154
Short name T724
Test name
Test status
Simulation time 38897128 ps
CPU time 0.83 seconds
Started Oct 15 01:33:06 PM PDT 23
Finished Oct 15 01:33:08 PM PDT 23
Peak memory 216380 kb
Host smart-03a64867-b4df-4918-91ff-4a1139713fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334487154 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.1334487154
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_intr.3588729700
Short name T577
Test name
Test status
Simulation time 22227381 ps
CPU time 0.89 seconds
Started Oct 15 01:32:34 PM PDT 23
Finished Oct 15 01:32:35 PM PDT 23
Peak memory 215416 kb
Host smart-14cacb69-819c-4095-a966-90110943d2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588729700 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.3588729700
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.3616084165
Short name T487
Test name
Test status
Simulation time 17940376 ps
CPU time 0.81 seconds
Started Oct 15 01:32:15 PM PDT 23
Finished Oct 15 01:32:17 PM PDT 23
Peak memory 205644 kb
Host smart-c630a5a5-f04f-42fe-b3be-64723441582e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616084165 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.3616084165
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.2380077227
Short name T70
Test name
Test status
Simulation time 797866904 ps
CPU time 4.31 seconds
Started Oct 15 01:32:30 PM PDT 23
Finished Oct 15 01:32:35 PM PDT 23
Peak memory 206604 kb
Host smart-ffaed1b4-db63-441c-89b8-884020148e4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380077227 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.2380077227
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.597595741
Short name T583
Test name
Test status
Simulation time 196949125463 ps
CPU time 1140.52 seconds
Started Oct 15 01:32:32 PM PDT 23
Finished Oct 15 01:51:33 PM PDT 23
Peak memory 217348 kb
Host smart-0d175261-7cf9-45d7-9f3a-372f110d765c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597595741 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.597595741
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.2511153420
Short name T712
Test name
Test status
Simulation time 18471250 ps
CPU time 0.9 seconds
Started Oct 15 01:33:08 PM PDT 23
Finished Oct 15 01:33:09 PM PDT 23
Peak memory 206756 kb
Host smart-d3b8f4e7-3914-4dfb-9889-d5ca5f23ee25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511153420 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2511153420
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.1055198034
Short name T686
Test name
Test status
Simulation time 39403996 ps
CPU time 0.79 seconds
Started Oct 15 01:33:36 PM PDT 23
Finished Oct 15 01:33:37 PM PDT 23
Peak memory 205100 kb
Host smart-2ab258e6-1a14-42eb-bd76-8a14683999b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055198034 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.1055198034
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.3902846276
Short name T150
Test name
Test status
Simulation time 15923309 ps
CPU time 0.83 seconds
Started Oct 15 01:33:38 PM PDT 23
Finished Oct 15 01:33:39 PM PDT 23
Peak memory 215080 kb
Host smart-5b094c79-4951-45d6-b2e4-7bb6fbf863fd
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902846276 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.3902846276
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.2587763226
Short name T536
Test name
Test status
Simulation time 49056064 ps
CPU time 0.91 seconds
Started Oct 15 01:33:10 PM PDT 23
Finished Oct 15 01:33:12 PM PDT 23
Peak memory 215252 kb
Host smart-e67090a0-fb95-4b91-8375-258fc7d2dbb4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587763226 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.2587763226
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.2387770339
Short name T595
Test name
Test status
Simulation time 23710674 ps
CPU time 0.84 seconds
Started Oct 15 01:32:59 PM PDT 23
Finished Oct 15 01:33:02 PM PDT 23
Peak memory 216436 kb
Host smart-8a812baa-dc73-4b03-b75b-628a889ed95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387770339 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.2387770339
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_intr.2420499911
Short name T662
Test name
Test status
Simulation time 20634976 ps
CPU time 0.98 seconds
Started Oct 15 01:33:00 PM PDT 23
Finished Oct 15 01:33:03 PM PDT 23
Peak memory 215364 kb
Host smart-f3226ec2-3e6c-4b56-922b-1ba84789b150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420499911 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.2420499911
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.734799889
Short name T309
Test name
Test status
Simulation time 12982911 ps
CPU time 0.91 seconds
Started Oct 15 01:32:35 PM PDT 23
Finished Oct 15 01:32:37 PM PDT 23
Peak memory 205616 kb
Host smart-c06229ef-1d39-4663-980b-36c89b0b7fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734799889 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.734799889
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.756106675
Short name T263
Test name
Test status
Simulation time 245089244 ps
CPU time 3 seconds
Started Oct 15 01:33:06 PM PDT 23
Finished Oct 15 01:33:09 PM PDT 23
Peak memory 206760 kb
Host smart-e8f2f279-b5b7-4b59-b9fb-4c9d9ea43f0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756106675 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.756106675
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.298284210
Short name T579
Test name
Test status
Simulation time 114735660364 ps
CPU time 1374.35 seconds
Started Oct 15 01:33:12 PM PDT 23
Finished Oct 15 01:56:08 PM PDT 23
Peak memory 220468 kb
Host smart-558a5613-c6d6-4c91-81b4-4abf85909d9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298284210 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.298284210
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.186970597
Short name T520
Test name
Test status
Simulation time 33739890 ps
CPU time 0.92 seconds
Started Oct 15 01:33:49 PM PDT 23
Finished Oct 15 01:33:50 PM PDT 23
Peak memory 206012 kb
Host smart-681194aa-1c73-47e4-a4d1-e973981f3847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186970597 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.186970597
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.3891586040
Short name T475
Test name
Test status
Simulation time 26935270 ps
CPU time 0.78 seconds
Started Oct 15 01:33:49 PM PDT 23
Finished Oct 15 01:33:50 PM PDT 23
Peak memory 205092 kb
Host smart-6a921bbf-57b2-4193-b854-c1075f0a8e00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891586040 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.3891586040
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.2167472156
Short name T50
Test name
Test status
Simulation time 26564742 ps
CPU time 0.77 seconds
Started Oct 15 01:33:40 PM PDT 23
Finished Oct 15 01:33:41 PM PDT 23
Peak memory 215004 kb
Host smart-946422bd-c7f5-4958-8210-448a86ffc691
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167472156 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.2167472156
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.3358143242
Short name T690
Test name
Test status
Simulation time 21702584 ps
CPU time 0.97 seconds
Started Oct 15 01:33:49 PM PDT 23
Finished Oct 15 01:33:50 PM PDT 23
Peak memory 215276 kb
Host smart-1e4df741-cbde-435c-9a45-770215efc2c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358143242 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.3358143242
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_genbits.1620193575
Short name T480
Test name
Test status
Simulation time 24304307 ps
CPU time 0.93 seconds
Started Oct 15 01:32:55 PM PDT 23
Finished Oct 15 01:32:56 PM PDT 23
Peak memory 206000 kb
Host smart-1c4c689d-5ab7-4c18-b6ba-51600a59c998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620193575 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.1620193575
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.2491992196
Short name T495
Test name
Test status
Simulation time 31834805 ps
CPU time 0.85 seconds
Started Oct 15 01:33:00 PM PDT 23
Finished Oct 15 01:33:03 PM PDT 23
Peak memory 215148 kb
Host smart-140ba77e-20c6-4051-b39e-d0143c71df33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491992196 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.2491992196
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.827226856
Short name T496
Test name
Test status
Simulation time 38776353 ps
CPU time 0.82 seconds
Started Oct 15 01:32:59 PM PDT 23
Finished Oct 15 01:33:01 PM PDT 23
Peak memory 205268 kb
Host smart-4963eb70-7e81-44c8-bba6-7e4235a0ccd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827226856 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.827226856
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.2241527031
Short name T689
Test name
Test status
Simulation time 421816851 ps
CPU time 3.02 seconds
Started Oct 15 01:33:10 PM PDT 23
Finished Oct 15 01:33:14 PM PDT 23
Peak memory 206480 kb
Host smart-c8faa756-5ab2-46c7-8f36-790409ac25f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241527031 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.2241527031
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.880662540
Short name T629
Test name
Test status
Simulation time 95060792446 ps
CPU time 741.95 seconds
Started Oct 15 01:33:06 PM PDT 23
Finished Oct 15 01:45:29 PM PDT 23
Peak memory 216944 kb
Host smart-04251bb5-cc6d-49de-b656-3304803b14b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880662540 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.880662540
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.293737670
Short name T535
Test name
Test status
Simulation time 28011152 ps
CPU time 0.89 seconds
Started Oct 15 01:33:50 PM PDT 23
Finished Oct 15 01:33:51 PM PDT 23
Peak memory 206300 kb
Host smart-ebc62929-73d8-4492-adc7-827f5c45e72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293737670 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.293737670
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.2580241876
Short name T626
Test name
Test status
Simulation time 106959891 ps
CPU time 0.91 seconds
Started Oct 15 01:33:13 PM PDT 23
Finished Oct 15 01:33:15 PM PDT 23
Peak memory 205468 kb
Host smart-d32a6f77-2166-4e62-95d3-aaa41eea0de6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580241876 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.2580241876
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.695294542
Short name T624
Test name
Test status
Simulation time 12234300 ps
CPU time 0.9 seconds
Started Oct 15 01:34:15 PM PDT 23
Finished Oct 15 01:34:16 PM PDT 23
Peak memory 215280 kb
Host smart-1f0a0d08-a841-4501-bb43-d13ec33e0a9e
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695294542 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.695294542
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.1268889691
Short name T670
Test name
Test status
Simulation time 58136648 ps
CPU time 0.91 seconds
Started Oct 15 01:34:12 PM PDT 23
Finished Oct 15 01:34:14 PM PDT 23
Peak memory 215208 kb
Host smart-fc8527ec-2880-4e47-aa87-1292b6e4aa6a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268889691 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.1268889691
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.129499588
Short name T316
Test name
Test status
Simulation time 29540292 ps
CPU time 1.27 seconds
Started Oct 15 01:33:51 PM PDT 23
Finished Oct 15 01:33:53 PM PDT 23
Peak memory 217816 kb
Host smart-49e9af3b-f803-47ba-96df-6f35ffe47062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129499588 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.129499588
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.3871147707
Short name T287
Test name
Test status
Simulation time 14843724 ps
CPU time 0.92 seconds
Started Oct 15 01:33:14 PM PDT 23
Finished Oct 15 01:33:16 PM PDT 23
Peak memory 205960 kb
Host smart-8409fb27-0996-44ab-a3b4-ed82cbc293b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871147707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.3871147707
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.2115611903
Short name T668
Test name
Test status
Simulation time 26619593 ps
CPU time 0.95 seconds
Started Oct 15 01:33:16 PM PDT 23
Finished Oct 15 01:33:18 PM PDT 23
Peak memory 215224 kb
Host smart-f61df6d6-84ee-4e32-9389-6c9a9ef2dcdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115611903 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.2115611903
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.3741135591
Short name T566
Test name
Test status
Simulation time 39940649 ps
CPU time 0.82 seconds
Started Oct 15 01:33:52 PM PDT 23
Finished Oct 15 01:33:54 PM PDT 23
Peak memory 205396 kb
Host smart-98cddce8-49a7-4b98-9107-f9ff77b8dfc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741135591 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.3741135591
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.4236783501
Short name T727
Test name
Test status
Simulation time 498165048 ps
CPU time 3.33 seconds
Started Oct 15 01:33:47 PM PDT 23
Finished Oct 15 01:33:51 PM PDT 23
Peak memory 206544 kb
Host smart-255d00a6-4f88-4415-9403-e8cd860721dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236783501 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.4236783501
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.662114292
Short name T25
Test name
Test status
Simulation time 21004286302 ps
CPU time 313.02 seconds
Started Oct 15 01:33:12 PM PDT 23
Finished Oct 15 01:38:26 PM PDT 23
Peak memory 215380 kb
Host smart-c1b6f8f3-3834-43a6-985c-6014bb1e2101
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662114292 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.662114292
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.43586473
Short name T718
Test name
Test status
Simulation time 16916793 ps
CPU time 1.05 seconds
Started Oct 15 01:33:48 PM PDT 23
Finished Oct 15 01:33:50 PM PDT 23
Peak memory 206760 kb
Host smart-e86d8e6d-d38a-430e-aded-57be1db00c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43586473 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.43586473
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.692342623
Short name T698
Test name
Test status
Simulation time 35298954 ps
CPU time 0.95 seconds
Started Oct 15 01:33:07 PM PDT 23
Finished Oct 15 01:33:09 PM PDT 23
Peak memory 205332 kb
Host smart-4407df8c-8312-42c4-8ba8-2949da9300e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692342623 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.692342623
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.3594370263
Short name T568
Test name
Test status
Simulation time 14665769 ps
CPU time 0.91 seconds
Started Oct 15 01:34:14 PM PDT 23
Finished Oct 15 01:34:15 PM PDT 23
Peak memory 215344 kb
Host smart-ecef18cd-da24-4992-a731-44151eb65701
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594370263 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.3594370263
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_err.2806745425
Short name T5
Test name
Test status
Simulation time 31391656 ps
CPU time 1.15 seconds
Started Oct 15 01:34:12 PM PDT 23
Finished Oct 15 01:34:14 PM PDT 23
Peak memory 222740 kb
Host smart-ad651363-2930-4a21-ace7-41e78f33e59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806745425 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.2806745425
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.2105170470
Short name T138
Test name
Test status
Simulation time 116402999 ps
CPU time 0.97 seconds
Started Oct 15 01:33:58 PM PDT 23
Finished Oct 15 01:33:59 PM PDT 23
Peak memory 215000 kb
Host smart-fb8ad1df-b98f-4e69-a296-c3856c00a46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105170470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.2105170470
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.638526257
Short name T132
Test name
Test status
Simulation time 29227432 ps
CPU time 0.88 seconds
Started Oct 15 01:34:00 PM PDT 23
Finished Oct 15 01:34:01 PM PDT 23
Peak memory 215368 kb
Host smart-91fb8ae1-93b5-412a-90e8-e80d07c279ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638526257 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.638526257
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.1466789116
Short name T338
Test name
Test status
Simulation time 25979464 ps
CPU time 0.88 seconds
Started Oct 15 01:34:13 PM PDT 23
Finished Oct 15 01:34:14 PM PDT 23
Peak memory 205680 kb
Host smart-c3e2e08b-854b-438d-9d80-02c7acc888f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466789116 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.1466789116
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.2672908721
Short name T571
Test name
Test status
Simulation time 183562760 ps
CPU time 2.14 seconds
Started Oct 15 01:33:46 PM PDT 23
Finished Oct 15 01:33:49 PM PDT 23
Peak memory 206308 kb
Host smart-343de5c9-712c-4665-b046-2ea551f46844
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672908721 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.2672908721
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.1749645189
Short name T189
Test name
Test status
Simulation time 394653945721 ps
CPU time 772.58 seconds
Started Oct 15 01:33:45 PM PDT 23
Finished Oct 15 01:46:38 PM PDT 23
Peak memory 215472 kb
Host smart-257ff8b1-0454-436c-adc9-55b591526c73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749645189 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.1749645189
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.2631165398
Short name T544
Test name
Test status
Simulation time 146978610 ps
CPU time 0.98 seconds
Started Oct 15 01:32:32 PM PDT 23
Finished Oct 15 01:32:34 PM PDT 23
Peak memory 206404 kb
Host smart-e1ac2763-477a-42c2-9e53-d1565a31156b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631165398 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2631165398
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.932055645
Short name T519
Test name
Test status
Simulation time 72822300 ps
CPU time 0.92 seconds
Started Oct 15 01:32:59 PM PDT 23
Finished Oct 15 01:33:00 PM PDT 23
Peak memory 205404 kb
Host smart-9403496b-e0b6-4247-b4cf-cd1b945679a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932055645 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.932055645
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.2939521021
Short name T679
Test name
Test status
Simulation time 19556270 ps
CPU time 0.78 seconds
Started Oct 15 01:32:38 PM PDT 23
Finished Oct 15 01:32:39 PM PDT 23
Peak memory 215060 kb
Host smart-2b223d07-1cec-4eaa-95cb-b26d35a4f2fe
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939521021 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.2939521021
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.4117617988
Short name T650
Test name
Test status
Simulation time 27684572 ps
CPU time 0.97 seconds
Started Oct 15 01:32:11 PM PDT 23
Finished Oct 15 01:32:12 PM PDT 23
Peak memory 215264 kb
Host smart-76a4fd88-390e-484f-8565-8a66416cb7ed
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117617988 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.4117617988
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.3930034009
Short name T63
Test name
Test status
Simulation time 28160040 ps
CPU time 1.16 seconds
Started Oct 15 01:32:14 PM PDT 23
Finished Oct 15 01:32:15 PM PDT 23
Peak memory 217728 kb
Host smart-c66caef1-eff6-4bcc-80d1-5901c4ba26d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930034009 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.3930034009
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.2153368449
Short name T262
Test name
Test status
Simulation time 31198604 ps
CPU time 0.94 seconds
Started Oct 15 01:33:46 PM PDT 23
Finished Oct 15 01:33:48 PM PDT 23
Peak memory 205988 kb
Host smart-d7fec9c7-a281-4d21-9a73-53ce729e5c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153368449 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.2153368449
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_smoke.267443822
Short name T655
Test name
Test status
Simulation time 11610008 ps
CPU time 0.91 seconds
Started Oct 15 01:34:07 PM PDT 23
Finished Oct 15 01:34:08 PM PDT 23
Peak memory 205552 kb
Host smart-99a5e568-4dfe-47c5-b21b-853f35f1135c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267443822 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.267443822
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.1216809394
Short name T641
Test name
Test status
Simulation time 32490703 ps
CPU time 1.18 seconds
Started Oct 15 01:34:03 PM PDT 23
Finished Oct 15 01:34:05 PM PDT 23
Peak memory 205756 kb
Host smart-f0c7436e-849e-4083-b0ec-68528d868a04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216809394 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.1216809394
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3855906297
Short name T472
Test name
Test status
Simulation time 89146730437 ps
CPU time 1922.81 seconds
Started Oct 15 01:32:13 PM PDT 23
Finished Oct 15 02:04:16 PM PDT 23
Peak memory 224152 kb
Host smart-19be108f-f207-49a4-8e5f-bae0d113b9c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855906297 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.3855906297
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.2529273367
Short name T688
Test name
Test status
Simulation time 36521828 ps
CPU time 0.95 seconds
Started Oct 15 01:32:16 PM PDT 23
Finished Oct 15 01:32:17 PM PDT 23
Peak memory 206788 kb
Host smart-7e6dcd90-4418-438f-869b-01caa98e2462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529273367 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.2529273367
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.2151047649
Short name T311
Test name
Test status
Simulation time 147557380 ps
CPU time 0.88 seconds
Started Oct 15 01:33:05 PM PDT 23
Finished Oct 15 01:33:07 PM PDT 23
Peak memory 205108 kb
Host smart-a72219c5-b7dc-4e04-828d-41c4f99f68c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151047649 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.2151047649
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.4144202006
Short name T171
Test name
Test status
Simulation time 20659330 ps
CPU time 0.83 seconds
Started Oct 15 01:32:11 PM PDT 23
Finished Oct 15 01:32:12 PM PDT 23
Peak memory 215052 kb
Host smart-fac342b5-83b0-47ba-8238-cd04675c0876
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144202006 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.4144202006
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.375573186
Short name T565
Test name
Test status
Simulation time 30471647 ps
CPU time 0.94 seconds
Started Oct 15 01:32:30 PM PDT 23
Finished Oct 15 01:32:31 PM PDT 23
Peak memory 215352 kb
Host smart-da5d7b88-83ef-4159-be45-50dc04b0e9c2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375573186 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_di
sable_auto_req_mode.375573186
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.4202894870
Short name T634
Test name
Test status
Simulation time 19910774 ps
CPU time 1.18 seconds
Started Oct 15 01:32:14 PM PDT 23
Finished Oct 15 01:32:15 PM PDT 23
Peak memory 222700 kb
Host smart-8179c4d3-968c-44dd-a10e-c28dd07b5328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202894870 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.4202894870
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.1747554079
Short name T683
Test name
Test status
Simulation time 28106554 ps
CPU time 1.18 seconds
Started Oct 15 01:32:30 PM PDT 23
Finished Oct 15 01:32:32 PM PDT 23
Peak memory 214972 kb
Host smart-89daeabb-4cc3-4910-82f7-c7261c20a05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747554079 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.1747554079
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.2389751388
Short name T546
Test name
Test status
Simulation time 21490649 ps
CPU time 0.93 seconds
Started Oct 15 01:32:12 PM PDT 23
Finished Oct 15 01:32:13 PM PDT 23
Peak memory 215308 kb
Host smart-7d4aa347-af9c-4d79-b97d-d55cd09712ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389751388 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.2389751388
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.2296740915
Short name T60
Test name
Test status
Simulation time 42819309 ps
CPU time 0.85 seconds
Started Oct 15 01:32:33 PM PDT 23
Finished Oct 15 01:32:34 PM PDT 23
Peak memory 205512 kb
Host smart-73689a69-ac5e-4447-9047-82d49b9e6da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296740915 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.2296740915
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.4135665195
Short name T271
Test name
Test status
Simulation time 1084348152 ps
CPU time 2.91 seconds
Started Oct 15 01:32:13 PM PDT 23
Finished Oct 15 01:32:16 PM PDT 23
Peak memory 206288 kb
Host smart-2021b7d5-2a25-4065-ac67-c9944d6ca23c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135665195 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.4135665195
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.502914924
Short name T193
Test name
Test status
Simulation time 46177628286 ps
CPU time 527.13 seconds
Started Oct 15 01:32:33 PM PDT 23
Finished Oct 15 01:41:20 PM PDT 23
Peak memory 216692 kb
Host smart-5a4819d7-cfd8-4bec-9c0e-f95c511f0b0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502914924 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.502914924
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.1083213635
Short name T254
Test name
Test status
Simulation time 113670407 ps
CPU time 0.95 seconds
Started Oct 15 01:32:11 PM PDT 23
Finished Oct 15 01:32:12 PM PDT 23
Peak memory 205904 kb
Host smart-f147ef74-b7a5-4b4c-bae5-0d7b91af7cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083213635 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.1083213635
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.404182587
Short name T713
Test name
Test status
Simulation time 22506907 ps
CPU time 0.82 seconds
Started Oct 15 01:32:10 PM PDT 23
Finished Oct 15 01:32:11 PM PDT 23
Peak memory 205372 kb
Host smart-6cb7b69a-00b3-440c-bbe1-71b6ddb11f9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404182587 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.404182587
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.1609200376
Short name T110
Test name
Test status
Simulation time 36470596 ps
CPU time 0.83 seconds
Started Oct 15 01:33:01 PM PDT 23
Finished Oct 15 01:33:03 PM PDT 23
Peak memory 215040 kb
Host smart-810d91e0-be82-4286-808c-d8b62b396b94
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609200376 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.1609200376
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.2631154958
Short name T9
Test name
Test status
Simulation time 25164407 ps
CPU time 0.99 seconds
Started Oct 15 01:33:03 PM PDT 23
Finished Oct 15 01:33:04 PM PDT 23
Peak memory 215288 kb
Host smart-a8cbddd7-cb22-4e5f-b90f-114374af87db
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631154958 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.2631154958
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.3616527511
Short name T310
Test name
Test status
Simulation time 38808625 ps
CPU time 1.09 seconds
Started Oct 15 01:32:13 PM PDT 23
Finished Oct 15 01:32:14 PM PDT 23
Peak memory 215564 kb
Host smart-5b727c9c-a5bb-41de-8e6e-baa4c4367dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616527511 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.3616527511
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.3610421778
Short name T542
Test name
Test status
Simulation time 46224914 ps
CPU time 0.91 seconds
Started Oct 15 01:32:36 PM PDT 23
Finished Oct 15 01:32:37 PM PDT 23
Peak memory 205580 kb
Host smart-7ee59396-7cfe-4256-a955-f50be366cce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610421778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3610421778
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.3751562666
Short name T485
Test name
Test status
Simulation time 26631556 ps
CPU time 0.94 seconds
Started Oct 15 01:32:34 PM PDT 23
Finished Oct 15 01:32:35 PM PDT 23
Peak memory 215072 kb
Host smart-206bc5b6-0589-4b4b-ab2d-4cc6b1d3a1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751562666 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.3751562666
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.3433944769
Short name T573
Test name
Test status
Simulation time 40725089 ps
CPU time 0.82 seconds
Started Oct 15 01:33:03 PM PDT 23
Finished Oct 15 01:33:05 PM PDT 23
Peak memory 205552 kb
Host smart-a718b015-4d63-432b-93e4-6c6ab8373cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433944769 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.3433944769
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.3952495193
Short name T570
Test name
Test status
Simulation time 58161349 ps
CPU time 1.6 seconds
Started Oct 15 01:32:34 PM PDT 23
Finished Oct 15 01:32:37 PM PDT 23
Peak memory 206200 kb
Host smart-44a69ba2-e014-49eb-af1a-bc43b20dc847
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952495193 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.3952495193
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.591839216
Short name T652
Test name
Test status
Simulation time 106739106216 ps
CPU time 1094.69 seconds
Started Oct 15 01:32:13 PM PDT 23
Finished Oct 15 01:50:29 PM PDT 23
Peak memory 217968 kb
Host smart-37b567f9-7b4c-42b7-8b17-4d249646ce15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591839216 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.591839216
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.1306013459
Short name T255
Test name
Test status
Simulation time 26029960 ps
CPU time 0.98 seconds
Started Oct 15 01:31:36 PM PDT 23
Finished Oct 15 01:31:38 PM PDT 23
Peak memory 206004 kb
Host smart-8baaf81a-e40c-41ed-b96e-936e4218a198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306013459 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.1306013459
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.3499530123
Short name T330
Test name
Test status
Simulation time 24312566 ps
CPU time 0.84 seconds
Started Oct 15 01:31:37 PM PDT 23
Finished Oct 15 01:31:38 PM PDT 23
Peak memory 205268 kb
Host smart-6b923866-0814-4b68-8acf-192b83da9a28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499530123 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.3499530123
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.1034797171
Short name T147
Test name
Test status
Simulation time 11501830 ps
CPU time 0.83 seconds
Started Oct 15 01:31:21 PM PDT 23
Finished Oct 15 01:31:22 PM PDT 23
Peak memory 215000 kb
Host smart-9773b06f-74be-4eb1-8da0-fe2a57f3e890
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034797171 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1034797171
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_err.1855683952
Short name T512
Test name
Test status
Simulation time 43955821 ps
CPU time 1.16 seconds
Started Oct 15 01:31:08 PM PDT 23
Finished Oct 15 01:31:10 PM PDT 23
Peak memory 222876 kb
Host smart-96a75abf-a852-4e6d-9310-77ed5d412527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855683952 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.1855683952
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_intr.299759201
Short name T54
Test name
Test status
Simulation time 18749539 ps
CPU time 1.09 seconds
Started Oct 15 01:31:29 PM PDT 23
Finished Oct 15 01:31:31 PM PDT 23
Peak memory 222240 kb
Host smart-6f948681-2a45-45e5-aa33-7963249b5f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299759201 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.299759201
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_smoke.372382497
Short name T675
Test name
Test status
Simulation time 23941703 ps
CPU time 0.92 seconds
Started Oct 15 01:31:36 PM PDT 23
Finished Oct 15 01:31:38 PM PDT 23
Peak memory 205480 kb
Host smart-ad33b56f-afbb-480f-afb7-d9cb09884dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372382497 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.372382497
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.1955949153
Short name T509
Test name
Test status
Simulation time 175053354 ps
CPU time 3.51 seconds
Started Oct 15 01:31:03 PM PDT 23
Finished Oct 15 01:31:07 PM PDT 23
Peak memory 206724 kb
Host smart-8b051e2e-2271-4c8c-bf50-5e158397e75d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955949153 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.1955949153
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.1631114377
Short name T194
Test name
Test status
Simulation time 51091054022 ps
CPU time 1109.38 seconds
Started Oct 15 01:31:12 PM PDT 23
Finished Oct 15 01:49:42 PM PDT 23
Peak memory 216300 kb
Host smart-648ec0f1-1b52-4d4b-993f-32a3be2c8627
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631114377 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.1631114377
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.1011749866
Short name T181
Test name
Test status
Simulation time 29839389 ps
CPU time 0.81 seconds
Started Oct 15 01:32:33 PM PDT 23
Finished Oct 15 01:32:34 PM PDT 23
Peak memory 216264 kb
Host smart-c14dbfea-78b1-4566-8bd2-6a8c1191a38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011749866 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.1011749866
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/51.edn_err.2686574813
Short name T648
Test name
Test status
Simulation time 29508590 ps
CPU time 1.27 seconds
Started Oct 15 01:33:07 PM PDT 23
Finished Oct 15 01:33:09 PM PDT 23
Peak memory 217712 kb
Host smart-bc5fc44d-a649-48ac-818c-731c8ae1e4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686574813 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.2686574813
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/52.edn_err.4163950215
Short name T58
Test name
Test status
Simulation time 19215955 ps
CPU time 1.08 seconds
Started Oct 15 01:32:13 PM PDT 23
Finished Oct 15 01:32:15 PM PDT 23
Peak memory 222800 kb
Host smart-ec4af6b2-ce18-4a07-bf52-540770222851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163950215 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.4163950215
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/53.edn_err.1529086864
Short name T53
Test name
Test status
Simulation time 19471369 ps
CPU time 1.12 seconds
Started Oct 15 01:32:30 PM PDT 23
Finished Oct 15 01:32:32 PM PDT 23
Peak memory 222696 kb
Host smart-b7685644-e002-4a62-b1aa-b2a2a288e985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529086864 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.1529086864
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/54.edn_err.1562532055
Short name T645
Test name
Test status
Simulation time 28075033 ps
CPU time 0.88 seconds
Started Oct 15 01:32:33 PM PDT 23
Finished Oct 15 01:32:34 PM PDT 23
Peak memory 216544 kb
Host smart-c339c921-4f49-45f0-b0c9-9445153bb7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562532055 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.1562532055
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/55.edn_err.3788421489
Short name T55
Test name
Test status
Simulation time 19436180 ps
CPU time 1.07 seconds
Started Oct 15 01:33:05 PM PDT 23
Finished Oct 15 01:33:07 PM PDT 23
Peak memory 222696 kb
Host smart-1494a2ce-4fef-4332-b616-0690697e2f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788421489 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.3788421489
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/56.edn_err.3279013529
Short name T246
Test name
Test status
Simulation time 65657887 ps
CPU time 1.02 seconds
Started Oct 15 01:32:11 PM PDT 23
Finished Oct 15 01:32:13 PM PDT 23
Peak memory 217952 kb
Host smart-029931f0-a647-4d3f-9d4d-f28c7bd4c111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279013529 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.3279013529
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/57.edn_err.3620526174
Short name T234
Test name
Test status
Simulation time 36473603 ps
CPU time 0.81 seconds
Started Oct 15 01:32:34 PM PDT 23
Finished Oct 15 01:32:35 PM PDT 23
Peak memory 216480 kb
Host smart-9e1091ac-b7b0-44b0-816e-e38edaa0353d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620526174 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.3620526174
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/58.edn_err.887524087
Short name T186
Test name
Test status
Simulation time 41396786 ps
CPU time 0.89 seconds
Started Oct 15 01:32:58 PM PDT 23
Finished Oct 15 01:32:59 PM PDT 23
Peak memory 222068 kb
Host smart-4633c180-8eae-4592-8b06-1b8bab14c6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887524087 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.887524087
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/59.edn_err.3553463558
Short name T632
Test name
Test status
Simulation time 42836362 ps
CPU time 1.08 seconds
Started Oct 15 01:32:15 PM PDT 23
Finished Oct 15 01:32:16 PM PDT 23
Peak memory 217616 kb
Host smart-bd64809a-857c-48df-a5f4-bb1adfeb0f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553463558 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.3553463558
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/6.edn_alert.343431531
Short name T293
Test name
Test status
Simulation time 83398243 ps
CPU time 1.02 seconds
Started Oct 15 01:31:03 PM PDT 23
Finished Oct 15 01:31:05 PM PDT 23
Peak memory 205824 kb
Host smart-b22cee53-38e9-4b61-ad8e-103e1940d9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343431531 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.343431531
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3935583910
Short name T307
Test name
Test status
Simulation time 57574291 ps
CPU time 0.95 seconds
Started Oct 15 01:31:12 PM PDT 23
Finished Oct 15 01:31:13 PM PDT 23
Peak memory 205428 kb
Host smart-4a211dbb-96b8-4c42-8896-5b736f3e7d46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935583910 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3935583910
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.3724424811
Short name T623
Test name
Test status
Simulation time 14329044 ps
CPU time 0.88 seconds
Started Oct 15 01:31:01 PM PDT 23
Finished Oct 15 01:31:03 PM PDT 23
Peak memory 215204 kb
Host smart-dcd5bc8b-e117-4d04-89ed-26ca232cd6a1
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724424811 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.3724424811
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.678435474
Short name T85
Test name
Test status
Simulation time 40526105 ps
CPU time 0.94 seconds
Started Oct 15 01:31:00 PM PDT 23
Finished Oct 15 01:31:02 PM PDT 23
Peak memory 215224 kb
Host smart-68264a1c-6e1b-4e16-bfa0-14ab09bec557
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678435474 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_dis
able_auto_req_mode.678435474
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.38150350
Short name T170
Test name
Test status
Simulation time 32128793 ps
CPU time 0.96 seconds
Started Oct 15 01:31:04 PM PDT 23
Finished Oct 15 01:31:06 PM PDT 23
Peak memory 222428 kb
Host smart-3383f7be-1370-4757-8f9d-29c07ea8afcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38150350 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.38150350
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.3304097387
Short name T46
Test name
Test status
Simulation time 64717899 ps
CPU time 1.01 seconds
Started Oct 15 01:31:03 PM PDT 23
Finished Oct 15 01:31:05 PM PDT 23
Peak memory 205584 kb
Host smart-c9ab8a30-66a8-4422-b3d3-23d98dfa30ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304097387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.3304097387
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.462908506
Short name T130
Test name
Test status
Simulation time 22877363 ps
CPU time 0.99 seconds
Started Oct 15 01:31:00 PM PDT 23
Finished Oct 15 01:31:02 PM PDT 23
Peak memory 226412 kb
Host smart-7f6c81ba-6412-456f-80b6-3e3428e87df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462908506 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.462908506
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.1654943567
Short name T71
Test name
Test status
Simulation time 20665902 ps
CPU time 0.83 seconds
Started Oct 15 01:31:14 PM PDT 23
Finished Oct 15 01:31:16 PM PDT 23
Peak memory 205396 kb
Host smart-3bebfd87-5673-4710-beab-86ef69789539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654943567 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.1654943567
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.2312470270
Short name T684
Test name
Test status
Simulation time 12984566 ps
CPU time 0.87 seconds
Started Oct 15 01:31:20 PM PDT 23
Finished Oct 15 01:31:21 PM PDT 23
Peak memory 205736 kb
Host smart-7a180526-5e9c-4c1b-b94a-d21cb88c4a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312470270 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.2312470270
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.1160245727
Short name T637
Test name
Test status
Simulation time 53605056 ps
CPU time 1.05 seconds
Started Oct 15 01:31:07 PM PDT 23
Finished Oct 15 01:31:08 PM PDT 23
Peak memory 206024 kb
Host smart-bc247c6c-d504-4f1e-8110-6fc8ee981a46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160245727 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.1160245727
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.209468703
Short name T196
Test name
Test status
Simulation time 40271344554 ps
CPU time 844.89 seconds
Started Oct 15 01:31:01 PM PDT 23
Finished Oct 15 01:45:07 PM PDT 23
Peak memory 215776 kb
Host smart-2e18faa8-040a-4ef4-abfc-5ee30ea2f91d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209468703 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.209468703
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.4248751773
Short name T726
Test name
Test status
Simulation time 24521072 ps
CPU time 0.93 seconds
Started Oct 15 01:32:15 PM PDT 23
Finished Oct 15 01:32:16 PM PDT 23
Peak memory 216628 kb
Host smart-11d4f3a5-2e92-43d5-affc-7c09b057a7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248751773 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.4248751773
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/61.edn_err.1693819674
Short name T56
Test name
Test status
Simulation time 77187540 ps
CPU time 0.89 seconds
Started Oct 15 01:32:59 PM PDT 23
Finished Oct 15 01:33:00 PM PDT 23
Peak memory 222108 kb
Host smart-37134886-3cb6-4ec7-8c83-f2f088cf7369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693819674 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.1693819674
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/62.edn_err.74948415
Short name T526
Test name
Test status
Simulation time 68564200 ps
CPU time 1.03 seconds
Started Oct 15 01:32:32 PM PDT 23
Finished Oct 15 01:32:34 PM PDT 23
Peak memory 217780 kb
Host smart-6b5d4514-5c7e-4cba-bd2d-05e87ab90d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74948415 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.74948415
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/63.edn_err.709247658
Short name T539
Test name
Test status
Simulation time 42480286 ps
CPU time 1.05 seconds
Started Oct 15 01:32:19 PM PDT 23
Finished Oct 15 01:32:20 PM PDT 23
Peak memory 217996 kb
Host smart-95b1b3e5-a9e1-45ee-8d2a-026d63118f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709247658 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.709247658
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/64.edn_err.2505866576
Short name T174
Test name
Test status
Simulation time 22549111 ps
CPU time 0.98 seconds
Started Oct 15 01:32:30 PM PDT 23
Finished Oct 15 01:32:32 PM PDT 23
Peak memory 222688 kb
Host smart-c4507d9d-6d3c-4aeb-b17a-91a5673af765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505866576 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.2505866576
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/65.edn_err.3489897403
Short name T185
Test name
Test status
Simulation time 21600140 ps
CPU time 1 seconds
Started Oct 15 01:32:15 PM PDT 23
Finished Oct 15 01:32:17 PM PDT 23
Peak memory 216512 kb
Host smart-366b2182-70d2-4f12-a6c7-76ed22292d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489897403 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.3489897403
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/66.edn_err.4183300705
Short name T142
Test name
Test status
Simulation time 25277940 ps
CPU time 1.22 seconds
Started Oct 15 01:32:59 PM PDT 23
Finished Oct 15 01:33:03 PM PDT 23
Peak memory 216624 kb
Host smart-1bab81b0-2408-4b4b-aed4-cffa83f4a83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183300705 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.4183300705
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/67.edn_err.4114084391
Short name T508
Test name
Test status
Simulation time 34506507 ps
CPU time 0.97 seconds
Started Oct 15 01:33:10 PM PDT 23
Finished Oct 15 01:33:12 PM PDT 23
Peak memory 222848 kb
Host smart-1477fc01-194a-44c1-afef-0feb487026ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114084391 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.4114084391
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/68.edn_err.1266701010
Short name T615
Test name
Test status
Simulation time 43359677 ps
CPU time 1.12 seconds
Started Oct 15 01:33:06 PM PDT 23
Finished Oct 15 01:33:08 PM PDT 23
Peak memory 217804 kb
Host smart-aa674f92-2d03-4c82-b8b1-50d5a615d5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266701010 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.1266701010
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/69.edn_err.563508045
Short name T183
Test name
Test status
Simulation time 22807198 ps
CPU time 0.86 seconds
Started Oct 15 01:33:52 PM PDT 23
Finished Oct 15 01:33:53 PM PDT 23
Peak memory 216484 kb
Host smart-27a2b86d-2d50-4f8a-b136-d50044500b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563508045 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.563508045
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/7.edn_alert.3768766593
Short name T700
Test name
Test status
Simulation time 65638685 ps
CPU time 0.94 seconds
Started Oct 15 01:31:02 PM PDT 23
Finished Oct 15 01:31:04 PM PDT 23
Peak memory 206860 kb
Host smart-3543754d-ae13-4cf6-94c4-03c0ec2f8c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768766593 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.3768766593
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.2005699002
Short name T486
Test name
Test status
Simulation time 33639977 ps
CPU time 0.77 seconds
Started Oct 15 01:30:56 PM PDT 23
Finished Oct 15 01:30:57 PM PDT 23
Peak memory 205128 kb
Host smart-2c374520-e365-456b-bdf8-3265e6858c2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005699002 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.2005699002
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.772434328
Short name T671
Test name
Test status
Simulation time 23630415 ps
CPU time 0.89 seconds
Started Oct 15 01:31:06 PM PDT 23
Finished Oct 15 01:31:07 PM PDT 23
Peak memory 215012 kb
Host smart-3a415fee-9f7e-43cd-9b9c-4fa224096142
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772434328 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.772434328
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.3366857858
Short name T13
Test name
Test status
Simulation time 30502585 ps
CPU time 0.93 seconds
Started Oct 15 01:31:13 PM PDT 23
Finished Oct 15 01:31:14 PM PDT 23
Peak memory 215272 kb
Host smart-e1677384-50ed-40ce-bb52-b81bd0857d73
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366857858 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.3366857858
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.3637580002
Short name T1
Test name
Test status
Simulation time 29303747 ps
CPU time 0.83 seconds
Started Oct 15 01:31:11 PM PDT 23
Finished Oct 15 01:31:12 PM PDT 23
Peak memory 216348 kb
Host smart-fa7d2383-4243-4f42-b5ec-aa08ed9cba7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637580002 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.3637580002
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_intr.531847719
Short name T492
Test name
Test status
Simulation time 19992979 ps
CPU time 1.13 seconds
Started Oct 15 01:31:00 PM PDT 23
Finished Oct 15 01:31:02 PM PDT 23
Peak memory 222872 kb
Host smart-47dcce8b-a0b5-486a-b9c2-ee1334567b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531847719 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.531847719
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.2027980040
Short name T611
Test name
Test status
Simulation time 14231825 ps
CPU time 0.86 seconds
Started Oct 15 01:30:59 PM PDT 23
Finished Oct 15 01:31:01 PM PDT 23
Peak memory 205696 kb
Host smart-0f3cfafc-fdef-43d5-a787-afa1204d6b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027980040 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.2027980040
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.2645343605
Short name T502
Test name
Test status
Simulation time 27926577 ps
CPU time 0.86 seconds
Started Oct 15 01:31:03 PM PDT 23
Finished Oct 15 01:31:05 PM PDT 23
Peak memory 205344 kb
Host smart-453ac7c9-a676-4a58-be8c-bb5b3a7ae2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645343605 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.2645343605
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.860292816
Short name T478
Test name
Test status
Simulation time 125233766 ps
CPU time 2.91 seconds
Started Oct 15 01:31:10 PM PDT 23
Finished Oct 15 01:31:13 PM PDT 23
Peak memory 206556 kb
Host smart-ea04d420-7685-4478-b59a-4acbdf2e3a92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860292816 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.860292816
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.146372379
Short name T315
Test name
Test status
Simulation time 44668581055 ps
CPU time 967.84 seconds
Started Oct 15 01:31:22 PM PDT 23
Finished Oct 15 01:47:30 PM PDT 23
Peak memory 215904 kb
Host smart-c6892033-81e0-4abe-a6a3-681dd74f6d39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146372379 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.146372379
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.1278648379
Short name T57
Test name
Test status
Simulation time 27094144 ps
CPU time 1.07 seconds
Started Oct 15 01:33:40 PM PDT 23
Finished Oct 15 01:33:42 PM PDT 23
Peak memory 222876 kb
Host smart-f22f8266-bdc5-4b5d-8433-64286ae1c888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278648379 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.1278648379
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/71.edn_err.1557831230
Short name T4
Test name
Test status
Simulation time 18930649 ps
CPU time 1.06 seconds
Started Oct 15 01:32:14 PM PDT 23
Finished Oct 15 01:32:16 PM PDT 23
Peak memory 216448 kb
Host smart-7891d064-c3cc-4559-916e-a740e549b3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557831230 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.1557831230
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/72.edn_err.4112356002
Short name T564
Test name
Test status
Simulation time 24872997 ps
CPU time 1.03 seconds
Started Oct 15 01:33:40 PM PDT 23
Finished Oct 15 01:33:42 PM PDT 23
Peak memory 216776 kb
Host smart-6e7bc8ee-9b65-4f07-a6e5-2f8e18239d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112356002 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.4112356002
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/73.edn_err.768479161
Short name T36
Test name
Test status
Simulation time 32424054 ps
CPU time 0.87 seconds
Started Oct 15 01:32:40 PM PDT 23
Finished Oct 15 01:32:41 PM PDT 23
Peak memory 216704 kb
Host smart-4f2c300a-b323-414e-8b79-f27a922413f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768479161 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.768479161
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/74.edn_err.3272495274
Short name T180
Test name
Test status
Simulation time 26881564 ps
CPU time 0.81 seconds
Started Oct 15 01:32:36 PM PDT 23
Finished Oct 15 01:32:37 PM PDT 23
Peak memory 216092 kb
Host smart-77232e9c-c7da-48f0-a082-8384a146176d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272495274 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.3272495274
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/75.edn_err.3830007732
Short name T511
Test name
Test status
Simulation time 20007901 ps
CPU time 1.1 seconds
Started Oct 15 01:33:43 PM PDT 23
Finished Oct 15 01:33:44 PM PDT 23
Peak memory 222820 kb
Host smart-c599a50c-d0ee-4610-8300-62c7634581aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830007732 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.3830007732
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/76.edn_err.2720701211
Short name T241
Test name
Test status
Simulation time 19133073 ps
CPU time 0.95 seconds
Started Oct 15 01:32:34 PM PDT 23
Finished Oct 15 01:32:35 PM PDT 23
Peak memory 216508 kb
Host smart-8ff09dfb-5575-4af8-9b47-eda273836c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720701211 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.2720701211
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/77.edn_err.3969650294
Short name T165
Test name
Test status
Simulation time 25108264 ps
CPU time 1.11 seconds
Started Oct 15 01:32:57 PM PDT 23
Finished Oct 15 01:32:58 PM PDT 23
Peak memory 229244 kb
Host smart-fb954c9a-6245-4690-84e0-d78770fa1a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969650294 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.3969650294
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/78.edn_err.2775781642
Short name T232
Test name
Test status
Simulation time 27491746 ps
CPU time 0.89 seconds
Started Oct 15 01:32:57 PM PDT 23
Finished Oct 15 01:32:58 PM PDT 23
Peak memory 215492 kb
Host smart-b59da2ff-edf9-41f6-9a8a-1a63a169f822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775781642 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.2775781642
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/79.edn_err.1732931778
Short name T162
Test name
Test status
Simulation time 24419133 ps
CPU time 1.31 seconds
Started Oct 15 01:33:15 PM PDT 23
Finished Oct 15 01:33:17 PM PDT 23
Peak memory 216632 kb
Host smart-9b23b87b-9c01-4d62-8acd-10982e65bfb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732931778 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.1732931778
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/8.edn_alert.1588249277
Short name T47
Test name
Test status
Simulation time 56138375 ps
CPU time 0.88 seconds
Started Oct 15 01:30:59 PM PDT 23
Finished Oct 15 01:31:00 PM PDT 23
Peak memory 206068 kb
Host smart-21a1ad32-093b-4650-b9e9-17ff98c493fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588249277 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.1588249277
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.1633725826
Short name T328
Test name
Test status
Simulation time 35296203 ps
CPU time 0.95 seconds
Started Oct 15 01:31:13 PM PDT 23
Finished Oct 15 01:31:14 PM PDT 23
Peak memory 206268 kb
Host smart-2d14559d-ad6b-42c9-969b-15e03b814363
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633725826 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.1633725826
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.914993940
Short name T178
Test name
Test status
Simulation time 16482955 ps
CPU time 0.85 seconds
Started Oct 15 01:31:16 PM PDT 23
Finished Oct 15 01:31:18 PM PDT 23
Peak memory 214996 kb
Host smart-1aa3a592-9c8a-427f-afee-14a1e3f06260
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914993940 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.914993940
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.3381484023
Short name T692
Test name
Test status
Simulation time 66828705 ps
CPU time 0.9 seconds
Started Oct 15 01:31:30 PM PDT 23
Finished Oct 15 01:31:31 PM PDT 23
Peak memory 215248 kb
Host smart-8c3c4442-4289-4b3c-aa39-579b4e7853c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381484023 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.3381484023
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_intr.1487899602
Short name T582
Test name
Test status
Simulation time 30127685 ps
CPU time 0.79 seconds
Started Oct 15 01:31:32 PM PDT 23
Finished Oct 15 01:31:35 PM PDT 23
Peak memory 215204 kb
Host smart-cbfc9ef8-52b7-4851-8bea-3e4e1808d8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487899602 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.1487899602
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_smoke.1996460530
Short name T108
Test name
Test status
Simulation time 18282693 ps
CPU time 0.82 seconds
Started Oct 15 01:30:59 PM PDT 23
Finished Oct 15 01:31:00 PM PDT 23
Peak memory 205616 kb
Host smart-97b17001-f6ca-4b78-93ac-2d1d1efb427f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996460530 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.1996460530
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.3929468680
Short name T547
Test name
Test status
Simulation time 35716580 ps
CPU time 1.22 seconds
Started Oct 15 01:31:07 PM PDT 23
Finished Oct 15 01:31:09 PM PDT 23
Peak memory 205868 kb
Host smart-dc9f4a33-8ff9-4596-be67-799b32681f7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929468680 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.3929468680
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.4222337868
Short name T574
Test name
Test status
Simulation time 19696366438 ps
CPU time 486.69 seconds
Started Oct 15 01:30:59 PM PDT 23
Finished Oct 15 01:39:07 PM PDT 23
Peak memory 215180 kb
Host smart-591fb8d1-d909-4270-9b28-ec10582bbf74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222337868 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.4222337868
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.2715815077
Short name T589
Test name
Test status
Simulation time 210411022 ps
CPU time 0.99 seconds
Started Oct 15 01:33:10 PM PDT 23
Finished Oct 15 01:33:11 PM PDT 23
Peak memory 216708 kb
Host smart-d62508cf-8c3a-444d-b888-5b924047b3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715815077 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.2715815077
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/81.edn_err.3270941753
Short name T175
Test name
Test status
Simulation time 20723513 ps
CPU time 1.18 seconds
Started Oct 15 01:33:08 PM PDT 23
Finished Oct 15 01:33:10 PM PDT 23
Peak memory 222676 kb
Host smart-349acd08-4a28-452c-be32-c9d56da5b316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270941753 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.3270941753
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/82.edn_err.731373155
Short name T28
Test name
Test status
Simulation time 19313714 ps
CPU time 0.93 seconds
Started Oct 15 01:33:40 PM PDT 23
Finished Oct 15 01:33:42 PM PDT 23
Peak memory 216656 kb
Host smart-b6b12378-0e0f-468b-a2d9-521f4024f410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731373155 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.731373155
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/83.edn_err.2479570612
Short name T247
Test name
Test status
Simulation time 33783586 ps
CPU time 0.89 seconds
Started Oct 15 01:32:15 PM PDT 23
Finished Oct 15 01:32:16 PM PDT 23
Peak memory 215368 kb
Host smart-a51148c4-84a8-4dd2-811a-dd20ec8702b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479570612 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.2479570612
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/84.edn_err.1352872213
Short name T558
Test name
Test status
Simulation time 30531060 ps
CPU time 0.82 seconds
Started Oct 15 01:33:01 PM PDT 23
Finished Oct 15 01:33:03 PM PDT 23
Peak memory 216384 kb
Host smart-767aee0a-9a3c-43e0-b677-e2af359d1acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352872213 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.1352872213
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/85.edn_err.1341045920
Short name T154
Test name
Test status
Simulation time 72214225 ps
CPU time 1.23 seconds
Started Oct 15 01:32:33 PM PDT 23
Finished Oct 15 01:32:35 PM PDT 23
Peak memory 228584 kb
Host smart-f8c3f6e8-2cd0-43b7-a425-e1bd84df0a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341045920 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.1341045920
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/86.edn_err.3246703098
Short name T240
Test name
Test status
Simulation time 67283652 ps
CPU time 1.04 seconds
Started Oct 15 01:32:13 PM PDT 23
Finished Oct 15 01:32:15 PM PDT 23
Peak memory 217844 kb
Host smart-74a98961-b431-4720-8fa1-bb0ad34207f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246703098 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.3246703098
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/87.edn_err.3457799858
Short name T710
Test name
Test status
Simulation time 24475378 ps
CPU time 1.12 seconds
Started Oct 15 01:32:31 PM PDT 23
Finished Oct 15 01:32:33 PM PDT 23
Peak memory 215340 kb
Host smart-e5504e9f-90e2-48d9-8233-78b490076785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457799858 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.3457799858
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/88.edn_err.982477193
Short name T716
Test name
Test status
Simulation time 18793304 ps
CPU time 0.97 seconds
Started Oct 15 01:32:13 PM PDT 23
Finished Oct 15 01:32:14 PM PDT 23
Peak memory 216568 kb
Host smart-644d1bc8-e4dd-48fa-b284-189e87b905ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982477193 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.982477193
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/89.edn_err.4243058194
Short name T643
Test name
Test status
Simulation time 26412050 ps
CPU time 0.89 seconds
Started Oct 15 01:32:34 PM PDT 23
Finished Oct 15 01:32:35 PM PDT 23
Peak memory 216592 kb
Host smart-5cfc4c88-a1bc-41dc-9c09-f71f85ea6160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243058194 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.4243058194
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/9.edn_alert.1147845489
Short name T257
Test name
Test status
Simulation time 54785031 ps
CPU time 0.9 seconds
Started Oct 15 01:31:34 PM PDT 23
Finished Oct 15 01:31:36 PM PDT 23
Peak memory 206696 kb
Host smart-7be7c914-8690-4b8d-8747-47dca919b3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147845489 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.1147845489
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.244351649
Short name T327
Test name
Test status
Simulation time 177794966 ps
CPU time 0.9 seconds
Started Oct 15 01:31:01 PM PDT 23
Finished Oct 15 01:31:02 PM PDT 23
Peak memory 205392 kb
Host smart-4ea43543-4ebe-4bb9-9b00-15c73e99075f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244351649 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.244351649
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.3642166288
Short name T113
Test name
Test status
Simulation time 16242664 ps
CPU time 0.83 seconds
Started Oct 15 01:31:04 PM PDT 23
Finished Oct 15 01:31:06 PM PDT 23
Peak memory 215020 kb
Host smart-2c785258-056a-4c53-94c5-fac0627693f8
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642166288 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.3642166288
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.1827214501
Short name T164
Test name
Test status
Simulation time 28576353 ps
CPU time 1.04 seconds
Started Oct 15 01:30:54 PM PDT 23
Finished Oct 15 01:30:56 PM PDT 23
Peak memory 215196 kb
Host smart-e3a4c85b-a003-451c-abd6-f14a9a216db5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827214501 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.1827214501
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.2733571520
Short name T498
Test name
Test status
Simulation time 25981427 ps
CPU time 0.93 seconds
Started Oct 15 01:31:15 PM PDT 23
Finished Oct 15 01:31:16 PM PDT 23
Peak memory 222588 kb
Host smart-16f447da-0d29-4fa7-8fef-82cbc32698bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733571520 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.2733571520
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.635936571
Short name T714
Test name
Test status
Simulation time 32901991 ps
CPU time 1 seconds
Started Oct 15 01:31:30 PM PDT 23
Finished Oct 15 01:31:32 PM PDT 23
Peak memory 205772 kb
Host smart-f12522ca-f204-48c1-802c-160efcce1737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635936571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.635936571
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.2515518825
Short name T308
Test name
Test status
Simulation time 26785421 ps
CPU time 0.88 seconds
Started Oct 15 01:31:33 PM PDT 23
Finished Oct 15 01:31:36 PM PDT 23
Peak memory 215224 kb
Host smart-6e5432eb-fe85-447b-a268-46ba6d752cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515518825 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.2515518825
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.2663832122
Short name T143
Test name
Test status
Simulation time 13108060 ps
CPU time 0.86 seconds
Started Oct 15 01:31:15 PM PDT 23
Finished Oct 15 01:31:17 PM PDT 23
Peak memory 205484 kb
Host smart-cfeb3440-e68e-4186-b57f-a83b5f11ca29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663832122 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.2663832122
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.1533056944
Short name T64
Test name
Test status
Simulation time 43361388 ps
CPU time 0.88 seconds
Started Oct 15 01:31:31 PM PDT 23
Finished Oct 15 01:31:32 PM PDT 23
Peak memory 205716 kb
Host smart-4453b82d-ac57-45d1-8f85-b7c613ccae04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533056944 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.1533056944
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.4186207890
Short name T527
Test name
Test status
Simulation time 119477741 ps
CPU time 2.72 seconds
Started Oct 15 01:31:33 PM PDT 23
Finished Oct 15 01:31:38 PM PDT 23
Peak memory 206260 kb
Host smart-507023a5-ae1f-4dbb-b1d7-64e0ca356f57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186207890 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.4186207890
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.602240907
Short name T191
Test name
Test status
Simulation time 34026328561 ps
CPU time 843.16 seconds
Started Oct 15 01:31:34 PM PDT 23
Finished Oct 15 01:45:38 PM PDT 23
Peak memory 215700 kb
Host smart-ccf12f00-dbd2-4ab3-acac-bf88f241578a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602240907 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.602240907
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.3033456340
Short name T510
Test name
Test status
Simulation time 28521085 ps
CPU time 1.25 seconds
Started Oct 15 01:33:00 PM PDT 23
Finished Oct 15 01:33:03 PM PDT 23
Peak memory 215268 kb
Host smart-1a7cfa6f-8062-4afa-893e-ce5284446054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033456340 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.3033456340
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/91.edn_err.4236956732
Short name T604
Test name
Test status
Simulation time 31499900 ps
CPU time 0.97 seconds
Started Oct 15 01:32:36 PM PDT 23
Finished Oct 15 01:32:38 PM PDT 23
Peak memory 216600 kb
Host smart-7bb1321c-7e25-4cb3-b52d-b01400a8c169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236956732 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.4236956732
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/92.edn_err.3546115790
Short name T528
Test name
Test status
Simulation time 24140684 ps
CPU time 1.13 seconds
Started Oct 15 01:32:57 PM PDT 23
Finished Oct 15 01:32:59 PM PDT 23
Peak memory 216680 kb
Host smart-6437cd22-94d0-4a05-9467-30e27c7bfc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546115790 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.3546115790
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/93.edn_err.1915759810
Short name T587
Test name
Test status
Simulation time 18541734 ps
CPU time 1.4 seconds
Started Oct 15 01:32:31 PM PDT 23
Finished Oct 15 01:32:33 PM PDT 23
Peak memory 222728 kb
Host smart-c13ec537-c381-4eeb-9018-3c3d0b372182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915759810 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.1915759810
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/94.edn_err.3526179661
Short name T532
Test name
Test status
Simulation time 82870581 ps
CPU time 1.04 seconds
Started Oct 15 01:33:13 PM PDT 23
Finished Oct 15 01:33:15 PM PDT 23
Peak memory 215196 kb
Host smart-189cad3b-e1fc-4cab-b1ed-0fdcfbd21d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526179661 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.3526179661
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/95.edn_err.2511277441
Short name T506
Test name
Test status
Simulation time 26010108 ps
CPU time 1.17 seconds
Started Oct 15 01:33:15 PM PDT 23
Finished Oct 15 01:33:17 PM PDT 23
Peak memory 231068 kb
Host smart-5143b372-6c4d-4d72-b9a3-9138d12d96bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511277441 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.2511277441
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/96.edn_err.2735827180
Short name T696
Test name
Test status
Simulation time 26083709 ps
CPU time 0.94 seconds
Started Oct 15 01:33:08 PM PDT 23
Finished Oct 15 01:33:10 PM PDT 23
Peak memory 216652 kb
Host smart-bd1acede-2314-4a72-9732-9c9633efedcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735827180 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.2735827180
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/97.edn_err.358498648
Short name T184
Test name
Test status
Simulation time 49340574 ps
CPU time 0.83 seconds
Started Oct 15 01:32:57 PM PDT 23
Finished Oct 15 01:32:58 PM PDT 23
Peak memory 216240 kb
Host smart-07a5f2b6-74ed-496a-aea5-33ef0688de03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358498648 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.358498648
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/98.edn_err.2660771810
Short name T249
Test name
Test status
Simulation time 18243504 ps
CPU time 1.02 seconds
Started Oct 15 01:34:13 PM PDT 23
Finished Oct 15 01:34:15 PM PDT 23
Peak memory 216660 kb
Host smart-ca6fd439-0ee7-40e5-bcd0-041a0d8b9a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660771810 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.2660771810
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/99.edn_err.3999209222
Short name T169
Test name
Test status
Simulation time 24268908 ps
CPU time 0.99 seconds
Started Oct 15 01:33:00 PM PDT 23
Finished Oct 15 01:33:03 PM PDT 23
Peak memory 222816 kb
Host smart-46cf1adf-2e35-4174-897f-14b4c0cfdd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999209222 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.3999209222
Directory /workspace/99.edn_err/latest
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