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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.16 98.64 88.52 94.40 59.21 96.62 96.83 82.93


Total test records in report: 980
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T752 /workspace/coverage/default/38.edn_stress_all_with_rand_reset.94894251867441594846313353917990708004879578708462107578197184997604875949762 Oct 29 02:07:43 PM PDT 23 Oct 29 02:25:45 PM PDT 23 41708099183 ps
T753 /workspace/coverage/default/185.edn_genbits.31187966120480948648819918935388809752937940776262166796270114779619578665227 Oct 29 02:08:43 PM PDT 23 Oct 29 02:08:46 PM PDT 23 17999183 ps
T754 /workspace/coverage/default/7.edn_disable_auto_req_mode.86034433313836139412425355653183807218879436780606348920054479618270622134706 Oct 29 02:06:56 PM PDT 23 Oct 29 02:06:57 PM PDT 23 17319183 ps
T755 /workspace/coverage/default/164.edn_genbits.18987681434091913590079367421771416791099334680262248534652349435288994522847 Oct 29 02:08:39 PM PDT 23 Oct 29 02:08:43 PM PDT 23 17999183 ps
T756 /workspace/coverage/default/158.edn_genbits.45905318205559933385276666231132322258308747536667642875242907724571800291747 Oct 29 02:10:47 PM PDT 23 Oct 29 02:10:48 PM PDT 23 17999183 ps
T757 /workspace/coverage/default/36.edn_disable_auto_req_mode.92628937007021849301604007072194982543739547975543180396343104705181225569628 Oct 29 02:08:12 PM PDT 23 Oct 29 02:08:13 PM PDT 23 17319183 ps
T758 /workspace/coverage/default/24.edn_stress_all_with_rand_reset.76074506502439217218190879386342563371109836948491110810216482277589572640826 Oct 29 02:09:40 PM PDT 23 Oct 29 02:27:08 PM PDT 23 41708099183 ps
T759 /workspace/coverage/default/243.edn_genbits.47245883484243549482405011464536776367252481165881743134711458298438920123309 Oct 29 02:10:34 PM PDT 23 Oct 29 02:10:36 PM PDT 23 17999183 ps
T760 /workspace/coverage/default/226.edn_genbits.74012107392515294923272129978260796269840771582220314897761325691940638316689 Oct 29 02:09:01 PM PDT 23 Oct 29 02:09:04 PM PDT 23 17999183 ps
T761 /workspace/coverage/default/21.edn_stress_all_with_rand_reset.35024968198911435370191269302707781103253473451294197401791319985018784757076 Oct 29 02:07:32 PM PDT 23 Oct 29 02:24:19 PM PDT 23 41708099183 ps
T762 /workspace/coverage/default/35.edn_err.95027821860816084583805148749879645029213586518855364699592527981051023661165 Oct 29 02:08:00 PM PDT 23 Oct 29 02:08:02 PM PDT 23 24963823 ps
T763 /workspace/coverage/default/14.edn_smoke.65124128131466484835384343285858869378036165383517227094280811111420455987170 Oct 29 02:07:02 PM PDT 23 Oct 29 02:07:05 PM PDT 23 13059183 ps
T764 /workspace/coverage/default/262.edn_genbits.91587007945136598509010471051549924927969675508120211228868555324912123327163 Oct 29 02:09:48 PM PDT 23 Oct 29 02:09:50 PM PDT 23 17999183 ps
T765 /workspace/coverage/default/87.edn_err.24333189428913021781912456279799149378514833391198436193085283741976228544416 Oct 29 02:08:34 PM PDT 23 Oct 29 02:08:36 PM PDT 23 24963823 ps
T766 /workspace/coverage/default/24.edn_disable.68379014927270363003874198573438460350245124661238411835050464204910328881680 Oct 29 02:07:06 PM PDT 23 Oct 29 02:07:09 PM PDT 23 12219183 ps
T767 /workspace/coverage/default/4.edn_disable.8014955656131445832768927550298471714049522083071516081594607747604867225391 Oct 29 02:06:34 PM PDT 23 Oct 29 02:06:35 PM PDT 23 12219183 ps
T768 /workspace/coverage/default/230.edn_genbits.115114291877552308050527273555627553323464923340604724385227916542215020639952 Oct 29 02:09:40 PM PDT 23 Oct 29 02:09:42 PM PDT 23 17999183 ps
T769 /workspace/coverage/default/126.edn_genbits.37155196367738954009034709307495311975428619394754205403297552107795781328321 Oct 29 02:10:05 PM PDT 23 Oct 29 02:10:07 PM PDT 23 17999183 ps
T770 /workspace/coverage/default/25.edn_stress_all_with_rand_reset.59158805256889101403191375864169788824258731062575433799813014619607842064657 Oct 29 02:07:27 PM PDT 23 Oct 29 02:25:24 PM PDT 23 41708099183 ps
T771 /workspace/coverage/default/35.edn_intr.97965838065003503299618114953223347778641191803949304160624443747927236102615 Oct 29 02:07:23 PM PDT 23 Oct 29 02:07:26 PM PDT 23 18439183 ps
T772 /workspace/coverage/default/217.edn_genbits.74142851214064660734994186271928068740047685342808976094485887492035751509280 Oct 29 02:10:46 PM PDT 23 Oct 29 02:10:48 PM PDT 23 17999183 ps
T773 /workspace/coverage/default/0.edn_regwen.109696415154103837017241574875715646846576266464368076818454238081792366618265 Oct 29 02:05:56 PM PDT 23 Oct 29 02:05:57 PM PDT 23 11759183 ps
T774 /workspace/coverage/default/64.edn_err.78926426025395099459982414092819064370117834869434000835372654644097078607025 Oct 29 02:08:40 PM PDT 23 Oct 29 02:08:44 PM PDT 23 24963823 ps
T775 /workspace/coverage/default/228.edn_genbits.62646849672480272965112743621280216526348908701290873184354936752238958090183 Oct 29 02:09:03 PM PDT 23 Oct 29 02:09:04 PM PDT 23 17999183 ps
T776 /workspace/coverage/default/0.edn_genbits.83717827309701473976758253209002092754122722454846588517678752986748173119151 Oct 29 02:05:56 PM PDT 23 Oct 29 02:05:57 PM PDT 23 17999183 ps
T777 /workspace/coverage/default/51.edn_err.113420501559450908955810669188046024819531661147769502628698378953654041003561 Oct 29 02:08:36 PM PDT 23 Oct 29 02:08:37 PM PDT 23 24963823 ps
T778 /workspace/coverage/default/69.edn_genbits.5500736508896658825800907907145890797467518159670197174351920555660531633341 Oct 29 02:08:08 PM PDT 23 Oct 29 02:08:10 PM PDT 23 17999183 ps
T779 /workspace/coverage/default/3.edn_disable_auto_req_mode.74856152391250058250791799654581631508102348181988841434142276340009253011919 Oct 29 02:06:32 PM PDT 23 Oct 29 02:06:34 PM PDT 23 17319183 ps
T780 /workspace/coverage/default/30.edn_disable.75731656136574399642723535766935976354842389683933652773354899146528903742994 Oct 29 02:07:22 PM PDT 23 Oct 29 02:07:25 PM PDT 23 12219183 ps
T781 /workspace/coverage/default/0.edn_smoke.36838917787144073672063337023914987469550952976824692097631448232457536101041 Oct 29 02:05:54 PM PDT 23 Oct 29 02:05:55 PM PDT 23 13059183 ps
T782 /workspace/coverage/default/37.edn_genbits.100892855218247894703723180643975869502122816394075635893663953306430426497214 Oct 29 02:07:36 PM PDT 23 Oct 29 02:07:37 PM PDT 23 17999183 ps
T783 /workspace/coverage/default/22.edn_disable.66903518340846650962929018684377352094957087842136530957896220684668272126129 Oct 29 02:07:59 PM PDT 23 Oct 29 02:08:00 PM PDT 23 12219183 ps
T784 /workspace/coverage/default/46.edn_alert.101561956047359690149591084572630354020385275588827798202512065649652833557095 Oct 29 02:08:10 PM PDT 23 Oct 29 02:08:11 PM PDT 23 18259183 ps
T785 /workspace/coverage/default/13.edn_stress_all_with_rand_reset.81728465647717365753245095944100308729352903732539257525146926206081842100986 Oct 29 02:07:26 PM PDT 23 Oct 29 02:25:16 PM PDT 23 41708099183 ps
T786 /workspace/coverage/default/41.edn_genbits.16639601208431994657028033075285462078986058429185020868903606556082964570469 Oct 29 02:07:41 PM PDT 23 Oct 29 02:07:43 PM PDT 23 17999183 ps
T52 /workspace/coverage/default/1.edn_sec_cm.74289543155220163800752959212431941598661744322613294418954448995302097510848 Oct 29 02:06:58 PM PDT 23 Oct 29 02:07:05 PM PDT 23 717215632 ps
T787 /workspace/coverage/default/110.edn_genbits.30119826891555376699019047223635514245907995865540152817095155462070945561341 Oct 29 02:08:48 PM PDT 23 Oct 29 02:08:50 PM PDT 23 17999183 ps
T788 /workspace/coverage/default/24.edn_err.59207577000386876503980526345778438859003497797853170886335954101657923150428 Oct 29 02:07:30 PM PDT 23 Oct 29 02:07:32 PM PDT 23 24963823 ps
T789 /workspace/coverage/default/67.edn_err.39352749840124566250542468047764740026201082570690598648815979608914184385225 Oct 29 02:09:41 PM PDT 23 Oct 29 02:09:42 PM PDT 23 24963823 ps
T790 /workspace/coverage/default/13.edn_alert_test.75308256983684589365551906736823360994100804871416797507994274886129402720953 Oct 29 02:07:33 PM PDT 23 Oct 29 02:07:34 PM PDT 23 28184990 ps
T791 /workspace/coverage/default/184.edn_genbits.103854742690142479614798001863150495757017808696350054254706797428987486497557 Oct 29 02:08:46 PM PDT 23 Oct 29 02:08:48 PM PDT 23 17999183 ps
T792 /workspace/coverage/default/34.edn_disable_auto_req_mode.8740295719253074700368115496497113778001998654330302412851061740739574993684 Oct 29 02:07:24 PM PDT 23 Oct 29 02:07:25 PM PDT 23 17319183 ps
T793 /workspace/coverage/default/40.edn_genbits.39360676446082934584355430923963487427970856588468092703408016813807502096050 Oct 29 02:07:58 PM PDT 23 Oct 29 02:08:00 PM PDT 23 17999183 ps
T794 /workspace/coverage/default/44.edn_stress_all_with_rand_reset.59923888805876681036771569493536522225965101813033395038751642437826111598062 Oct 29 02:08:04 PM PDT 23 Oct 29 02:25:15 PM PDT 23 41708099183 ps
T795 /workspace/coverage/default/42.edn_err.17116781745905814471640264472223507185503384564586674509209338220715269089129 Oct 29 02:08:35 PM PDT 23 Oct 29 02:08:36 PM PDT 23 24963823 ps
T796 /workspace/coverage/default/27.edn_stress_all.7746501002093765922198964970616351124394884729244351470435851755885712963885 Oct 29 02:07:58 PM PDT 23 Oct 29 02:08:02 PM PDT 23 154489183 ps
T797 /workspace/coverage/default/1.edn_alert.81709540525674824543451487115297868899761743798011278144368735418922560941543 Oct 29 02:06:31 PM PDT 23 Oct 29 02:06:32 PM PDT 23 18259183 ps
T798 /workspace/coverage/default/3.edn_alert.91617411659445071647437762935735718294182669534760146049573056171795634361952 Oct 29 02:06:36 PM PDT 23 Oct 29 02:06:38 PM PDT 23 18259183 ps
T799 /workspace/coverage/default/85.edn_genbits.82378761048727992450548058013068318149528220671484082149582242910337631634634 Oct 29 02:09:48 PM PDT 23 Oct 29 02:09:50 PM PDT 23 17999183 ps
T800 /workspace/coverage/default/25.edn_disable.38996778178416921097661704640607751969766642104635271870712201214150904598355 Oct 29 02:07:04 PM PDT 23 Oct 29 02:07:05 PM PDT 23 12219183 ps
T801 /workspace/coverage/default/10.edn_err.82398655333939814289208779347893906020908996404601825619235781178148901397100 Oct 29 02:07:02 PM PDT 23 Oct 29 02:07:06 PM PDT 23 24963823 ps
T802 /workspace/coverage/default/9.edn_stress_all.9649263234379547468993739819392820957433781582347307965197981877195398145328 Oct 29 02:06:54 PM PDT 23 Oct 29 02:06:58 PM PDT 23 154489183 ps
T803 /workspace/coverage/default/43.edn_disable_auto_req_mode.104643925880168141613463577804018769627473733552421101450640270537804413629488 Oct 29 02:08:06 PM PDT 23 Oct 29 02:08:07 PM PDT 23 17319183 ps
T804 /workspace/coverage/default/39.edn_stress_all_with_rand_reset.41430232119211998795307605008037315000267735544134249811983865165394650184262 Oct 29 02:08:42 PM PDT 23 Oct 29 02:26:40 PM PDT 23 41708099183 ps
T805 /workspace/coverage/default/12.edn_smoke.46180739280321889391369520048596707560644084299675589831578374966200065686991 Oct 29 02:07:28 PM PDT 23 Oct 29 02:07:30 PM PDT 23 13059183 ps
T806 /workspace/coverage/default/267.edn_genbits.12335938678386173415750774029545391289394094597761085572699328645704046390218 Oct 29 02:08:46 PM PDT 23 Oct 29 02:08:48 PM PDT 23 17999183 ps
T807 /workspace/coverage/default/12.edn_stress_all.90360915519442175699403241849756194153133603744001260807566549268481549651086 Oct 29 02:07:05 PM PDT 23 Oct 29 02:07:11 PM PDT 23 154489183 ps
T808 /workspace/coverage/default/87.edn_genbits.45778796508442796288712633066325549009960100637594708968193839917522072256544 Oct 29 02:08:35 PM PDT 23 Oct 29 02:08:37 PM PDT 23 17999183 ps
T809 /workspace/coverage/default/62.edn_err.63685350850904421340470059261795934797216017755880184869272918930712164885288 Oct 29 02:08:37 PM PDT 23 Oct 29 02:08:38 PM PDT 23 24963823 ps
T810 /workspace/coverage/default/199.edn_genbits.13441862599134490515164289672844960533045776201946881935948328100963023042518 Oct 29 02:09:47 PM PDT 23 Oct 29 02:09:49 PM PDT 23 17999183 ps
T811 /workspace/coverage/default/18.edn_genbits.20597856292085024223159109375426067824363453443444658490850040869766053883198 Oct 29 02:07:58 PM PDT 23 Oct 29 02:08:00 PM PDT 23 17999183 ps
T812 /workspace/coverage/default/145.edn_genbits.36345996340067606065698073331994326316975721999754361420934107804843410284422 Oct 29 02:10:44 PM PDT 23 Oct 29 02:10:46 PM PDT 23 17999183 ps
T813 /workspace/coverage/default/39.edn_genbits.67598478494338116326883797065869942032948940651593210659441023829099437817119 Oct 29 02:07:40 PM PDT 23 Oct 29 02:07:41 PM PDT 23 17999183 ps
T814 /workspace/coverage/default/48.edn_intr.75352484590960236330771014893656585391195532945993446156226270031812625479653 Oct 29 02:09:23 PM PDT 23 Oct 29 02:09:24 PM PDT 23 18439183 ps
T815 /workspace/coverage/default/123.edn_genbits.58927452614701849997983863321525762215449739587259712953815854547874946353414 Oct 29 02:09:41 PM PDT 23 Oct 29 02:09:42 PM PDT 23 17999183 ps
T816 /workspace/coverage/default/18.edn_alert_test.24758621186288701787051122162321253744901495151630203461834426947411020296777 Oct 29 02:06:58 PM PDT 23 Oct 29 02:06:59 PM PDT 23 28184990 ps
T817 /workspace/coverage/default/17.edn_disable_auto_req_mode.2074995998326541970814819160681841977099456129685692550695130493286217492322 Oct 29 02:07:33 PM PDT 23 Oct 29 02:07:34 PM PDT 23 17319183 ps
T818 /workspace/coverage/default/258.edn_genbits.107320647661603040493412998156323882356555137088872082564773604835654840871445 Oct 29 02:09:37 PM PDT 23 Oct 29 02:09:38 PM PDT 23 17999183 ps
T819 /workspace/coverage/default/19.edn_smoke.75009448602341990653219094406310538817568444876782086229306516306088034406058 Oct 29 02:07:00 PM PDT 23 Oct 29 02:07:05 PM PDT 23 13059183 ps
T820 /workspace/coverage/default/31.edn_err.105268234724506735337986646550567093267995449766368744880653613146909458560705 Oct 29 02:07:26 PM PDT 23 Oct 29 02:07:29 PM PDT 23 24963823 ps
T821 /workspace/coverage/default/69.edn_err.902189026257439278891926841445879671581400221254107365973515594692354856170 Oct 29 02:09:00 PM PDT 23 Oct 29 02:09:04 PM PDT 23 24963823 ps
T822 /workspace/coverage/default/30.edn_stress_all.8255203573926566122496997576937858244041141052980259321567214794311494669493 Oct 29 02:08:02 PM PDT 23 Oct 29 02:08:06 PM PDT 23 154489183 ps
T823 /workspace/coverage/default/77.edn_err.46478211369543806655675763930981847784951536596548824718350626385484169881831 Oct 29 02:08:37 PM PDT 23 Oct 29 02:08:38 PM PDT 23 24963823 ps
T824 /workspace/coverage/default/235.edn_genbits.109321017465541846100969593887145900531583550107132316416593134102617687813488 Oct 29 02:10:27 PM PDT 23 Oct 29 02:10:29 PM PDT 23 17999183 ps
T825 /workspace/coverage/default/92.edn_genbits.57696007830882820696390522331022483954609154552014239363648927093734628399808 Oct 29 02:08:13 PM PDT 23 Oct 29 02:08:15 PM PDT 23 17999183 ps
T826 /workspace/coverage/default/279.edn_genbits.94813565775496926680397158191541431228028477850479042851097996585141692190349 Oct 29 02:08:50 PM PDT 23 Oct 29 02:08:52 PM PDT 23 17999183 ps
T827 /workspace/coverage/default/38.edn_smoke.71524444765119890650812256566084036105968302825121724946379203189419164359535 Oct 29 02:07:36 PM PDT 23 Oct 29 02:07:38 PM PDT 23 13059183 ps
T828 /workspace/coverage/default/36.edn_smoke.88257241353415570992291062513550250123291537200127790884779194288693111337558 Oct 29 02:08:02 PM PDT 23 Oct 29 02:08:03 PM PDT 23 13059183 ps
T829 /workspace/coverage/default/16.edn_err.113607691576269073464212995891375533596799648465566743066154139726120060300805 Oct 29 02:07:02 PM PDT 23 Oct 29 02:07:06 PM PDT 23 24963823 ps
T830 /workspace/coverage/default/29.edn_alert_test.63592581323368602839169756543106356773834579258448972377029436793558337686508 Oct 29 02:07:07 PM PDT 23 Oct 29 02:07:09 PM PDT 23 28184990 ps
T831 /workspace/coverage/default/95.edn_genbits.107995158647689185811087343498533051991934842837035470863996734213612312888943 Oct 29 02:09:47 PM PDT 23 Oct 29 02:09:48 PM PDT 23 17999183 ps
T832 /workspace/coverage/default/44.edn_stress_all.38153236561935875963037969785652070780452479237427447157979156362472690506541 Oct 29 02:08:01 PM PDT 23 Oct 29 02:08:05 PM PDT 23 154489183 ps
T833 /workspace/coverage/default/40.edn_intr.5899151963707002763272106411820642932128674555049652103787366408288803572691 Oct 29 02:08:13 PM PDT 23 Oct 29 02:08:15 PM PDT 23 18439183 ps
T834 /workspace/coverage/default/49.edn_genbits.109683667213434138035787557335690930991280183960310135659466184048352557098976 Oct 29 02:07:50 PM PDT 23 Oct 29 02:07:52 PM PDT 23 17999183 ps
T835 /workspace/coverage/default/178.edn_genbits.108056987122178031848749762589471885494278271676249184491076080532544037418996 Oct 29 02:09:02 PM PDT 23 Oct 29 02:09:04 PM PDT 23 17999183 ps
T836 /workspace/coverage/default/177.edn_genbits.26588137925216820885174409161796508266085502091730433255836580885296277816776 Oct 29 02:08:47 PM PDT 23 Oct 29 02:08:49 PM PDT 23 17999183 ps
T837 /workspace/coverage/default/59.edn_genbits.95096577002229872925517058223646222287130503797887083694936645325317905857751 Oct 29 02:08:41 PM PDT 23 Oct 29 02:08:43 PM PDT 23 17999183 ps
T838 /workspace/coverage/default/27.edn_stress_all_with_rand_reset.63403101102284157070555657540678607997198754369427062263147160032125639461807 Oct 29 02:08:02 PM PDT 23 Oct 29 02:25:36 PM PDT 23 41708099183 ps
T839 /workspace/coverage/default/16.edn_stress_all_with_rand_reset.70621857170277320118595017242357235733315803029873995127491590275467592158352 Oct 29 02:07:32 PM PDT 23 Oct 29 02:24:58 PM PDT 23 41708099183 ps
T840 /workspace/coverage/default/9.edn_alert.89659989712539719914416543650160828611217421649554864853555125909629723620623 Oct 29 02:07:27 PM PDT 23 Oct 29 02:07:29 PM PDT 23 18259183 ps
T841 /workspace/coverage/default/8.edn_disable_auto_req_mode.111580246383126162392838993719300045326397408102096531276523761173020748037007 Oct 29 02:06:59 PM PDT 23 Oct 29 02:07:01 PM PDT 23 17319183 ps
T842 /workspace/coverage/default/19.edn_genbits.36718218926715737804379432790480370865591672792798680516446578937806771371349 Oct 29 02:07:24 PM PDT 23 Oct 29 02:07:26 PM PDT 23 17999183 ps
T843 /workspace/coverage/default/4.edn_genbits.5495089230164192055842554230122900861624493600306245414874176153510134389884 Oct 29 02:07:00 PM PDT 23 Oct 29 02:07:05 PM PDT 23 17999183 ps
T844 /workspace/coverage/default/281.edn_genbits.109662122717158286732307140119340950766164408084535674538164968111031134981891 Oct 29 02:09:49 PM PDT 23 Oct 29 02:09:50 PM PDT 23 17999183 ps
T845 /workspace/coverage/default/195.edn_genbits.90277014653400371720244347763593363516140666555078834670181192207163646441270 Oct 29 02:09:39 PM PDT 23 Oct 29 02:09:40 PM PDT 23 17999183 ps
T846 /workspace/coverage/default/20.edn_alert.94231629765293653161360355474100795105839193675552758662905927674329847394857 Oct 29 02:06:58 PM PDT 23 Oct 29 02:07:01 PM PDT 23 18259183 ps
T847 /workspace/coverage/default/0.edn_alert_test.71235063368310710838021080008411440482564116940290639401160046221319837921237 Oct 29 02:05:50 PM PDT 23 Oct 29 02:05:51 PM PDT 23 28184990 ps
T848 /workspace/coverage/default/82.edn_genbits.91529177309050090616081817240278829526062657469867788796061433867630854507175 Oct 29 02:09:47 PM PDT 23 Oct 29 02:09:48 PM PDT 23 17999183 ps
T849 /workspace/coverage/default/44.edn_intr.1913300073785471061426648688553962465751997934824399180320884556548618883934 Oct 29 02:08:05 PM PDT 23 Oct 29 02:08:06 PM PDT 23 18439183 ps
T850 /workspace/coverage/default/12.edn_disable_auto_req_mode.106515130591301208789202288501068022230181858359803934222485001747510253153403 Oct 29 02:06:57 PM PDT 23 Oct 29 02:06:59 PM PDT 23 17319183 ps
T851 /workspace/coverage/default/22.edn_smoke.76910992082599749055083670235090773857962314016952525942109617276206123440015 Oct 29 02:07:37 PM PDT 23 Oct 29 02:07:39 PM PDT 23 13059183 ps
T852 /workspace/coverage/default/31.edn_stress_all.102086122882993373021959447117025363870960324051333343395813502160165088076523 Oct 29 02:07:28 PM PDT 23 Oct 29 02:07:33 PM PDT 23 154489183 ps
T853 /workspace/coverage/default/156.edn_genbits.94030336992153305083964177733562345152316221525788069202259490383984168591129 Oct 29 02:10:49 PM PDT 23 Oct 29 02:10:50 PM PDT 23 17999183 ps
T854 /workspace/coverage/default/0.edn_stress_all_with_rand_reset.84575224830372705364390894147501685057194978518527909157932284116337917170965 Oct 29 02:05:47 PM PDT 23 Oct 29 02:24:00 PM PDT 23 41708099183 ps
T855 /workspace/coverage/default/234.edn_genbits.9359637000542047579980572289066054394432684438949974296184141611925665058715 Oct 29 02:09:50 PM PDT 23 Oct 29 02:09:52 PM PDT 23 17999183 ps
T856 /workspace/coverage/default/49.edn_stress_all.78539128057769605864154363400893966770026975817087026483503238748159289871341 Oct 29 02:07:51 PM PDT 23 Oct 29 02:07:55 PM PDT 23 154489183 ps
T857 /workspace/coverage/default/137.edn_genbits.70339649863955876837555994458606128042611638696155216013428583794610937563022 Oct 29 02:10:34 PM PDT 23 Oct 29 02:10:36 PM PDT 23 17999183 ps
T858 /workspace/coverage/default/80.edn_err.30951212622299467275497609515070667230005980201452304391337234867874177746051 Oct 29 02:08:39 PM PDT 23 Oct 29 02:08:43 PM PDT 23 24963823 ps
T859 /workspace/coverage/default/23.edn_genbits.110252973689803017492976879922702610047306389312671755678207034802974659044348 Oct 29 02:09:39 PM PDT 23 Oct 29 02:09:41 PM PDT 23 17999183 ps
T860 /workspace/coverage/default/28.edn_err.50409982791226115749351281676845547813155035922079800981267116673435019255895 Oct 29 02:07:28 PM PDT 23 Oct 29 02:07:30 PM PDT 23 24963823 ps
T861 /workspace/coverage/default/45.edn_stress_all_with_rand_reset.95387909259556755990412498099031137466758569608642226911925801009003948178481 Oct 29 02:08:03 PM PDT 23 Oct 29 02:25:50 PM PDT 23 41708099183 ps
T862 /workspace/coverage/default/7.edn_genbits.81202063185781555580495638960238994308420486424830886796734370056578614633829 Oct 29 02:06:54 PM PDT 23 Oct 29 02:06:55 PM PDT 23 17999183 ps
T863 /workspace/coverage/default/19.edn_err.78046197747123266619882563541569328418293264917263999034589284414933745154796 Oct 29 02:07:27 PM PDT 23 Oct 29 02:07:29 PM PDT 23 24963823 ps
T864 /workspace/coverage/default/28.edn_disable.13836797580687917547244027965944694854256021893653472377497433623801627211605 Oct 29 02:07:01 PM PDT 23 Oct 29 02:07:05 PM PDT 23 12219183 ps
T865 /workspace/coverage/default/152.edn_genbits.15227972436646933671213287646898695415434805871991312456352598386987273971042 Oct 29 02:10:46 PM PDT 23 Oct 29 02:10:48 PM PDT 23 17999183 ps
T866 /workspace/coverage/default/10.edn_stress_all_with_rand_reset.26953726276962118506554327442396299115646939267464173595022744899170975132511 Oct 29 02:07:22 PM PDT 23 Oct 29 02:24:19 PM PDT 23 41708099183 ps
T867 /workspace/coverage/default/26.edn_stress_all_with_rand_reset.95885416793471549774329485833857415378568175858488486050048319009753549575404 Oct 29 02:07:37 PM PDT 23 Oct 29 02:25:18 PM PDT 23 41708099183 ps
T868 /workspace/coverage/default/115.edn_genbits.20309720588753653316256611269745115581929463223935293199776581259854260937448 Oct 29 02:09:25 PM PDT 23 Oct 29 02:09:27 PM PDT 23 17999183 ps
T869 /workspace/coverage/default/6.edn_alert.91688172083364483848246649925626912457267849625628280546954985314602518398159 Oct 29 02:06:37 PM PDT 23 Oct 29 02:06:39 PM PDT 23 18259183 ps
T870 /workspace/coverage/default/259.edn_genbits.73582998242320703649926221044496675313879633431856664149482465687655199579634 Oct 29 02:09:46 PM PDT 23 Oct 29 02:09:47 PM PDT 23 17999183 ps
T871 /workspace/coverage/default/47.edn_smoke.42793725970414033290012602138399356331630123686482810990904853628253707222797 Oct 29 02:08:12 PM PDT 23 Oct 29 02:08:13 PM PDT 23 13059183 ps
T872 /workspace/coverage/default/35.edn_disable_auto_req_mode.81244718020207400348680759787370037725203269128101492625943711971979354001608 Oct 29 02:07:37 PM PDT 23 Oct 29 02:07:39 PM PDT 23 17319183 ps
T873 /workspace/coverage/default/26.edn_stress_all.5363253614610542122171067069288302421147672846938895815404160942206406548142 Oct 29 02:07:05 PM PDT 23 Oct 29 02:07:12 PM PDT 23 154489183 ps
T874 /workspace/coverage/default/86.edn_genbits.110616616353265970395675035538786221806211371815992498110681537090342642639240 Oct 29 02:08:43 PM PDT 23 Oct 29 02:08:45 PM PDT 23 17999183 ps
T875 /workspace/coverage/default/7.edn_err.43412822953955404231760005719894475775095073379526894245090110399484816504330 Oct 29 02:07:19 PM PDT 23 Oct 29 02:07:22 PM PDT 23 24963823 ps
T876 /workspace/coverage/default/39.edn_alert.13968933638024013794968891546445517577860601134661406068956808751290494885576 Oct 29 02:08:36 PM PDT 23 Oct 29 02:08:38 PM PDT 23 18259183 ps
T877 /workspace/coverage/default/36.edn_err.101419994384088355975403045275032307776495173565796924824220033010416426403336 Oct 29 02:08:04 PM PDT 23 Oct 29 02:08:05 PM PDT 23 24963823 ps
T878 /workspace/coverage/default/138.edn_genbits.13547240648986872720127725837001375307825591428130257126847712721095132021973 Oct 29 02:10:21 PM PDT 23 Oct 29 02:10:23 PM PDT 23 17999183 ps
T879 /workspace/coverage/default/122.edn_genbits.99442111168138983412509441707001177918908736819037845438701932768567311061442 Oct 29 02:09:36 PM PDT 23 Oct 29 02:09:37 PM PDT 23 17999183 ps
T880 /workspace/coverage/default/98.edn_err.61853439745099705337128166397523915704628666781398990624252768839136820127182 Oct 29 02:09:47 PM PDT 23 Oct 29 02:09:48 PM PDT 23 24963823 ps
T881 /workspace/coverage/default/71.edn_genbits.17264493295760025631641689386734465077808459506551693422294900269503651837105 Oct 29 02:08:09 PM PDT 23 Oct 29 02:08:11 PM PDT 23 17999183 ps
T882 /workspace/coverage/default/224.edn_genbits.79968158368208352747759811678398931878079896352914155854802344837343170967209 Oct 29 02:09:44 PM PDT 23 Oct 29 02:09:45 PM PDT 23 17999183 ps
T883 /workspace/coverage/default/30.edn_smoke.22361362670633529765134592437942381919705868092831203736788968078415368106144 Oct 29 02:07:29 PM PDT 23 Oct 29 02:07:31 PM PDT 23 13059183 ps
T884 /workspace/coverage/default/2.edn_genbits.95468638450234508118061655827522962242027049168921153656372964193811521556261 Oct 29 02:06:54 PM PDT 23 Oct 29 02:06:56 PM PDT 23 17999183 ps
T885 /workspace/coverage/default/63.edn_err.69193254288189173442944811907225760601046127257152695743685905075677483396177 Oct 29 02:08:42 PM PDT 23 Oct 29 02:08:44 PM PDT 23 24963823 ps
T886 /workspace/coverage/default/46.edn_disable.1813303315163001482982237112598886465385310929891469650662503856724377237915 Oct 29 02:08:02 PM PDT 23 Oct 29 02:08:04 PM PDT 23 12219183 ps
T887 /workspace/coverage/default/186.edn_genbits.113814612578408174233138877090906368696318384808102065188881069664486333609125 Oct 29 02:09:46 PM PDT 23 Oct 29 02:09:48 PM PDT 23 17999183 ps
T888 /workspace/coverage/default/48.edn_err.99667982534306472037966994384164154979612234999280635478495301877912400823615 Oct 29 02:08:06 PM PDT 23 Oct 29 02:08:07 PM PDT 23 24963823 ps
T889 /workspace/coverage/default/82.edn_err.42453620905498894619329204289559227211133258453478625049763316738615955898890 Oct 29 02:08:08 PM PDT 23 Oct 29 02:08:10 PM PDT 23 24963823 ps
T890 /workspace/coverage/default/37.edn_alert.58909265909528618167602593820255639729409255543921408194680005523335272894766 Oct 29 02:07:36 PM PDT 23 Oct 29 02:07:37 PM PDT 23 18259183 ps
T891 /workspace/coverage/default/48.edn_disable_auto_req_mode.47204040296939415439295155503937812307906982907473669808600388333748006121225 Oct 29 02:08:36 PM PDT 23 Oct 29 02:08:37 PM PDT 23 17319183 ps
T892 /workspace/coverage/default/45.edn_disable_auto_req_mode.2936601910773323011267215152160925817673131287798606539060286532086514265385 Oct 29 02:08:05 PM PDT 23 Oct 29 02:08:06 PM PDT 23 17319183 ps
T893 /workspace/coverage/default/44.edn_alert_test.78533282369860153805882907439814693816814821329167228879701341490205937587913 Oct 29 02:08:36 PM PDT 23 Oct 29 02:08:37 PM PDT 23 28184990 ps
T894 /workspace/coverage/default/41.edn_stress_all.60398371385154038860996928903472921403138821754832936905504248166270852729308 Oct 29 02:07:57 PM PDT 23 Oct 29 02:08:01 PM PDT 23 154489183 ps
T895 /workspace/coverage/default/8.edn_stress_all.49380227264781292298308209846672624610875469669428973884167085919082008097553 Oct 29 02:07:00 PM PDT 23 Oct 29 02:07:04 PM PDT 23 154489183 ps
T896 /workspace/coverage/default/47.edn_disable_auto_req_mode.114402641071507393791870256373419520303098934210141623965544565661893064718010 Oct 29 02:08:08 PM PDT 23 Oct 29 02:08:09 PM PDT 23 17319183 ps
T897 /workspace/coverage/default/45.edn_smoke.30692876330984480605469419728733510560223393531345260036653270437028005081442 Oct 29 02:08:05 PM PDT 23 Oct 29 02:08:06 PM PDT 23 13059183 ps
T898 /workspace/coverage/default/40.edn_err.22751762550957643632073239771565752573532487249210135943519435643400959232288 Oct 29 02:08:31 PM PDT 23 Oct 29 02:08:32 PM PDT 23 24963823 ps
T899 /workspace/coverage/default/237.edn_genbits.45044112511158927934773264198245027859831620942632470986306557373286826882255 Oct 29 02:09:54 PM PDT 23 Oct 29 02:09:55 PM PDT 23 17999183 ps
T900 /workspace/coverage/default/194.edn_genbits.26141642952389512173555908991668244505735358534764148686804086919233119134723 Oct 29 02:09:49 PM PDT 23 Oct 29 02:09:50 PM PDT 23 17999183 ps
T901 /workspace/coverage/default/29.edn_smoke.80936609300921471688066814907876450601582004075576492071675905254297804063377 Oct 29 02:07:02 PM PDT 23 Oct 29 02:07:05 PM PDT 23 13059183 ps
T902 /workspace/coverage/default/26.edn_genbits.49941906763473178823468047991860573728994142397107249595011693976526422159433 Oct 29 02:07:30 PM PDT 23 Oct 29 02:07:32 PM PDT 23 17999183 ps
T903 /workspace/coverage/default/106.edn_genbits.37818538676921192967328175454369526711039486115118919146294362712936632369349 Oct 29 02:09:46 PM PDT 23 Oct 29 02:09:47 PM PDT 23 17999183 ps
T904 /workspace/coverage/default/9.edn_err.19595423188032299210471816055854543657301471583350198153565572882381315502508 Oct 29 02:07:03 PM PDT 23 Oct 29 02:07:06 PM PDT 23 24963823 ps
T905 /workspace/coverage/default/21.edn_disable_auto_req_mode.101642134033297587134152919250786790194253603140140002105408609162315440861046 Oct 29 02:07:03 PM PDT 23 Oct 29 02:07:05 PM PDT 23 17319183 ps
T906 /workspace/coverage/default/91.edn_err.16078063999808788511141683591617535501283718768335733558725579787056022420328 Oct 29 02:09:23 PM PDT 23 Oct 29 02:09:24 PM PDT 23 24963823 ps
T907 /workspace/coverage/default/5.edn_err.107329703237498161613821423210206154834970894772373988881737529813727194643796 Oct 29 02:07:20 PM PDT 23 Oct 29 02:07:22 PM PDT 23 24963823 ps
T908 /workspace/coverage/default/32.edn_alert.107019965042741087008491217398513905017525111198794598064380198493297564462513 Oct 29 02:07:38 PM PDT 23 Oct 29 02:07:39 PM PDT 23 18259183 ps
T909 /workspace/coverage/default/216.edn_genbits.102746640464568827524693788327229743531820441104711058129669846734412975523906 Oct 29 02:10:44 PM PDT 23 Oct 29 02:10:46 PM PDT 23 17999183 ps
T910 /workspace/coverage/default/100.edn_genbits.31998938484334843679742673796754374852623367119670782647893840612176436071170 Oct 29 02:08:59 PM PDT 23 Oct 29 02:09:04 PM PDT 23 17999183 ps
T911 /workspace/coverage/default/269.edn_genbits.95661859708693748349184699068391693431722736879890778613106643966051313426785 Oct 29 02:08:52 PM PDT 23 Oct 29 02:08:56 PM PDT 23 17999183 ps
T912 /workspace/coverage/default/261.edn_genbits.19775676149569869092663096147214516992060486892139053692130227516166870252028 Oct 29 02:08:50 PM PDT 23 Oct 29 02:08:51 PM PDT 23 17999183 ps
T913 /workspace/coverage/default/21.edn_stress_all.50468737664164917566837474264766936407206776208449407260812880222698797973814 Oct 29 02:07:03 PM PDT 23 Oct 29 02:07:09 PM PDT 23 154489183 ps
T914 /workspace/coverage/default/33.edn_stress_all.60158781627622090034236748863373156901578393701895635875712520438905926794043 Oct 29 02:08:04 PM PDT 23 Oct 29 02:08:08 PM PDT 23 154489183 ps
T915 /workspace/coverage/default/144.edn_genbits.3223853311065853339876311765299591408975998810487529284712481021891016250244 Oct 29 02:10:52 PM PDT 23 Oct 29 02:10:53 PM PDT 23 17999183 ps
T916 /workspace/coverage/default/85.edn_err.108020167432172900605028677165876928596138563222157373711391461076971879758212 Oct 29 02:08:32 PM PDT 23 Oct 29 02:08:33 PM PDT 23 24963823 ps
T917 /workspace/coverage/default/109.edn_genbits.43447487129507958210633693698701206462366279948136724258174024741360438710806 Oct 29 02:08:57 PM PDT 23 Oct 29 02:09:02 PM PDT 23 17999183 ps
T918 /workspace/coverage/default/289.edn_genbits.77076622298535090296804583076825394896367488237397543834248512731411923983680 Oct 29 02:08:54 PM PDT 23 Oct 29 02:08:56 PM PDT 23 17999183 ps
T919 /workspace/coverage/default/163.edn_genbits.7137541528994728224393928562613829128941873058121535788635108693143720566914 Oct 29 02:08:53 PM PDT 23 Oct 29 02:08:56 PM PDT 23 17999183 ps
T920 /workspace/coverage/default/299.edn_genbits.98787362479410343394587916516181630830807926899772942012236042118987639572581 Oct 29 02:09:45 PM PDT 23 Oct 29 02:09:47 PM PDT 23 17999183 ps
T921 /workspace/coverage/default/17.edn_alert.6513438563874651652795865231783667056112734782765364888304470109948689829257 Oct 29 02:07:30 PM PDT 23 Oct 29 02:07:31 PM PDT 23 18259183 ps
T922 /workspace/coverage/default/20.edn_smoke.83573409483407538680846651385242854528461281183365353044222457129964116337952 Oct 29 02:07:29 PM PDT 23 Oct 29 02:07:30 PM PDT 23 13059183 ps
T923 /workspace/coverage/default/15.edn_genbits.28331495654344146152649192715658778427758819850391125757637826119237893431762 Oct 29 02:07:03 PM PDT 23 Oct 29 02:07:06 PM PDT 23 17999183 ps
T924 /workspace/coverage/default/2.edn_err.92842134374648953929150604196478973592320480020434419648844190082886068079816 Oct 29 02:06:57 PM PDT 23 Oct 29 02:06:58 PM PDT 23 24963823 ps
T925 /workspace/coverage/default/11.edn_intr.23302005502428046343026456031154464606043472564072468326124219227370351446621 Oct 29 02:07:00 PM PDT 23 Oct 29 02:07:05 PM PDT 23 18439183 ps
T926 /workspace/coverage/default/97.edn_genbits.19867365382414153235490997356260817372342714660668093766674809436495221922130 Oct 29 02:08:34 PM PDT 23 Oct 29 02:08:36 PM PDT 23 17999183 ps
T927 /workspace/coverage/default/73.edn_genbits.112814506854373349872420923574489628273162784837237459171323656059428009405910 Oct 29 02:08:40 PM PDT 23 Oct 29 02:08:43 PM PDT 23 17999183 ps
T928 /workspace/coverage/default/15.edn_disable_auto_req_mode.70689404389326081053513911165150957686873993591315451508881703287786070199187 Oct 29 02:07:02 PM PDT 23 Oct 29 02:07:05 PM PDT 23 17319183 ps
T929 /workspace/coverage/default/29.edn_intr.59878825200162587902817206840280322179681681926747396216114398971246220899180 Oct 29 02:07:28 PM PDT 23 Oct 29 02:07:30 PM PDT 23 18439183 ps
T930 /workspace/coverage/default/206.edn_genbits.112050179602976585747620567792663507226419011312953036763807446131468356049377 Oct 29 02:10:27 PM PDT 23 Oct 29 02:10:28 PM PDT 23 17999183 ps
T931 /workspace/coverage/default/18.edn_disable_auto_req_mode.81350487516987316300401473914648376300924123002153607098348859261139304838750 Oct 29 02:07:03 PM PDT 23 Oct 29 02:07:05 PM PDT 23 17319183 ps
T932 /workspace/coverage/default/24.edn_disable_auto_req_mode.33063094064064273120315915135020807942018310508099560535962851681048215430329 Oct 29 02:07:05 PM PDT 23 Oct 29 02:07:09 PM PDT 23 17319183 ps
T933 /workspace/coverage/default/77.edn_genbits.105260325438719154825505669782292929885798477360791436405342409749451574257734 Oct 29 02:09:22 PM PDT 23 Oct 29 02:09:23 PM PDT 23 17999183 ps
T934 /workspace/coverage/default/257.edn_genbits.87778286493859602311643192070162582186261902098901698037293563696482132383080 Oct 29 02:08:51 PM PDT 23 Oct 29 02:08:52 PM PDT 23 17999183 ps
T935 /workspace/coverage/default/28.edn_intr.94222595430659486322905019715439052162774994423004109442626269193975968713337 Oct 29 02:07:05 PM PDT 23 Oct 29 02:07:09 PM PDT 23 18439183 ps
T936 /workspace/coverage/default/26.edn_alert_test.22560365168594575351106560286835549679862737714559745824068518386345153788596 Oct 29 02:07:29 PM PDT 23 Oct 29 02:07:31 PM PDT 23 28184990 ps
T937 /workspace/coverage/default/101.edn_genbits.20061309683412184001103325234491941167905019333016721366416836341703849313888 Oct 29 02:08:37 PM PDT 23 Oct 29 02:08:39 PM PDT 23 17999183 ps
T938 /workspace/coverage/default/6.edn_alert_test.111779838329901523198209364471154585182974458902638317752226843635541200964403 Oct 29 02:06:33 PM PDT 23 Oct 29 02:06:34 PM PDT 23 28184990 ps
T939 /workspace/coverage/default/294.edn_genbits.29037299405290977391575016249431054009336895272034026528638895875313939809698 Oct 29 02:08:53 PM PDT 23 Oct 29 02:08:56 PM PDT 23 17999183 ps
T940 /workspace/coverage/default/24.edn_alert_test.91459691910781449893165064192355125849826491942272611793226841423161976935603 Oct 29 02:07:05 PM PDT 23 Oct 29 02:07:09 PM PDT 23 28184990 ps
T941 /workspace/coverage/default/38.edn_disable_auto_req_mode.25637566131373815272329910105327262937179819997021996462051996291453522105708 Oct 29 02:08:05 PM PDT 23 Oct 29 02:08:07 PM PDT 23 17319183 ps
T942 /workspace/coverage/default/23.edn_stress_all_with_rand_reset.88025986973565229123050986089416415915875276507291023438808605401802092123392 Oct 29 02:08:09 PM PDT 23 Oct 29 02:26:11 PM PDT 23 41708099183 ps
T943 /workspace/coverage/default/24.edn_stress_all.86236043859625201817814081012806351742936334248338895324566188177330167398490 Oct 29 02:09:05 PM PDT 23 Oct 29 02:09:09 PM PDT 23 154489183 ps
T944 /workspace/coverage/default/118.edn_genbits.68964842232100144296466789287527495527209791668684255323823383229319275480011 Oct 29 02:09:41 PM PDT 23 Oct 29 02:09:43 PM PDT 23 17999183 ps
T945 /workspace/coverage/default/41.edn_alert_test.26404476882634457776879377883124728310708078218406523745169064021020304301344 Oct 29 02:07:43 PM PDT 23 Oct 29 02:07:44 PM PDT 23 28184990 ps
T946 /workspace/coverage/default/22.edn_alert_test.18167371264612208734702155058682820962934712398683314465598988348070967616374 Oct 29 02:08:37 PM PDT 23 Oct 29 02:08:38 PM PDT 23 28184990 ps
T947 /workspace/coverage/default/6.edn_disable.110847000105374297324035791305337987615517023820075372594120327578570044340862 Oct 29 02:06:58 PM PDT 23 Oct 29 02:07:01 PM PDT 23 12219183 ps
T948 /workspace/coverage/default/17.edn_err.115270864194889894597632045080218251435149442868154902994198566040140316519364 Oct 29 02:07:29 PM PDT 23 Oct 29 02:07:31 PM PDT 23 24963823 ps
T949 /workspace/coverage/default/43.edn_intr.64816401332585525035844454457662640250789727141736153252587045452689071478371 Oct 29 02:08:43 PM PDT 23 Oct 29 02:08:45 PM PDT 23 18439183 ps
T950 /workspace/coverage/default/33.edn_alert.40944769595203131811230157646888732746358225817440458452766878712582973355758 Oct 29 02:07:19 PM PDT 23 Oct 29 02:07:20 PM PDT 23 18259183 ps
T951 /workspace/coverage/default/18.edn_err.30667723655635977277165540810313148249653225371651313887763861266843089744041 Oct 29 02:07:01 PM PDT 23 Oct 29 02:07:06 PM PDT 23 24963823 ps
T952 /workspace/coverage/default/182.edn_genbits.57334718370203558071654230967763856205710592574703051885879249089303136877428 Oct 29 02:09:39 PM PDT 23 Oct 29 02:09:41 PM PDT 23 17999183 ps
T953 /workspace/coverage/default/5.edn_disable.111178504565679908861295093475987318428900950392593493113910427836169622550046 Oct 29 02:07:00 PM PDT 23 Oct 29 02:07:04 PM PDT 23 12219183 ps
T954 /workspace/coverage/default/65.edn_genbits.75590274949826491246173283564726120975583997782482751461989663989125679785445 Oct 29 02:08:45 PM PDT 23 Oct 29 02:08:47 PM PDT 23 17999183 ps
T955 /workspace/coverage/default/44.edn_disable.78351045687248453288586158210899664558971270416320731549258026977425969723558 Oct 29 02:08:10 PM PDT 23 Oct 29 02:08:12 PM PDT 23 12219183 ps
T956 /workspace/coverage/default/71.edn_err.395004427850450105283086493115187744647535729913766162826770133041362443860 Oct 29 02:08:12 PM PDT 23 Oct 29 02:08:13 PM PDT 23 24963823 ps
T957 /workspace/coverage/default/30.edn_alert_test.94393960084445642672272661751850857465146766237264488476384569114352012064358 Oct 29 02:07:26 PM PDT 23 Oct 29 02:07:28 PM PDT 23 28184990 ps
T958 /workspace/coverage/default/238.edn_genbits.99010263249916845474005580181381867076496893182695139150237898653081084177970 Oct 29 02:09:46 PM PDT 23 Oct 29 02:09:48 PM PDT 23 17999183 ps
T959 /workspace/coverage/default/48.edn_smoke.35300084563825351636460079662866050642616173444003647750460763195904976591931 Oct 29 02:08:01 PM PDT 23 Oct 29 02:08:02 PM PDT 23 13059183 ps
T960 /workspace/coverage/default/21.edn_disable.40097669158179317621961916746043077212392081462067794954856067715868039290596 Oct 29 02:07:32 PM PDT 23 Oct 29 02:07:34 PM PDT 23 12219183 ps
T961 /workspace/coverage/default/293.edn_genbits.37154134917610484353999435370171770136934007986585435442377915493903048087792 Oct 29 02:08:54 PM PDT 23 Oct 29 02:08:56 PM PDT 23 17999183 ps
T962 /workspace/coverage/default/22.edn_genbits.98045062112957911406230907452312930191623820020825795296265446825131658722690 Oct 29 02:08:41 PM PDT 23 Oct 29 02:08:43 PM PDT 23 17999183 ps
T963 /workspace/coverage/default/38.edn_genbits.55614528773827376074513241802938110756749507061721645682037670839281580539212 Oct 29 02:07:32 PM PDT 23 Oct 29 02:07:34 PM PDT 23 17999183 ps
T964 /workspace/coverage/default/264.edn_genbits.85839109491559954947990176848995451468550276283257154300260860471909931540795 Oct 29 02:08:48 PM PDT 23 Oct 29 02:08:49 PM PDT 23 17999183 ps
T965 /workspace/coverage/default/11.edn_disable_auto_req_mode.112000015720942145809829159257577837633369709121944415980426604392387100549947 Oct 29 02:07:20 PM PDT 23 Oct 29 02:07:22 PM PDT 23 17319183 ps
T966 /workspace/coverage/default/7.edn_intr.114195192109303675928658392001687983199402353014011751557648120458235090505921 Oct 29 02:07:01 PM PDT 23 Oct 29 02:07:06 PM PDT 23 18439183 ps
T967 /workspace/coverage/default/17.edn_stress_all.51244429367898113847128536581976642204156187109770589497927473448434601416348 Oct 29 02:07:33 PM PDT 23 Oct 29 02:07:37 PM PDT 23 154489183 ps
T968 /workspace/coverage/default/0.edn_alert.54520020545741905531727561527153004835756537402378227991652270521198792664375 Oct 29 02:05:45 PM PDT 23 Oct 29 02:05:47 PM PDT 23 18259183 ps
T969 /workspace/coverage/default/16.edn_smoke.94258790393842972648743802351331956240311284301095348105683961276488555851137 Oct 29 02:07:29 PM PDT 23 Oct 29 02:07:30 PM PDT 23 13059183 ps
T970 /workspace/coverage/default/93.edn_err.50934449405959225949666554111766123421544878133971884870198780850575167555769 Oct 29 02:08:36 PM PDT 23 Oct 29 02:08:38 PM PDT 23 24963823 ps
T971 /workspace/coverage/default/41.edn_disable.22920285001755460887537964764301555402571565744287204328035474399839953851457 Oct 29 02:07:57 PM PDT 23 Oct 29 02:07:58 PM PDT 23 12219183 ps
T972 /workspace/coverage/default/38.edn_alert.98438203949692215077785188935664660715639799723786988154321335675639653606846 Oct 29 02:07:58 PM PDT 23 Oct 29 02:07:59 PM PDT 23 18259183 ps
T973 /workspace/coverage/default/12.edn_alert.106331496842006722640092225666608925369030746180037105396001571478663959142011 Oct 29 02:06:40 PM PDT 23 Oct 29 02:06:41 PM PDT 23 18259183 ps
T974 /workspace/coverage/default/11.edn_err.57442872470851728061831795231618839664225295650782695209157256282418654530433 Oct 29 02:06:56 PM PDT 23 Oct 29 02:06:58 PM PDT 23 24963823 ps
T975 /workspace/coverage/default/34.edn_disable.72450237036676773993374199491738702903874819820659297112951054886620898409505 Oct 29 02:08:02 PM PDT 23 Oct 29 02:08:03 PM PDT 23 12219183 ps
T976 /workspace/coverage/default/88.edn_err.40660282311234568886294504524163250039150637698719138379226940584746868942494 Oct 29 02:08:42 PM PDT 23 Oct 29 02:08:44 PM PDT 23 24963823 ps
T977 /workspace/coverage/default/20.edn_intr.80805524419299331654578843213139182394954536842701043754909545911947878363039 Oct 29 02:07:05 PM PDT 23 Oct 29 02:07:09 PM PDT 23 18439183 ps
T978 /workspace/coverage/default/75.edn_genbits.53610152909261722664555247641295078570552536580651913346374445125247943373005 Oct 29 02:08:17 PM PDT 23 Oct 29 02:08:18 PM PDT 23 17999183 ps
T979 /workspace/coverage/default/13.edn_alert.112526234241310027866327748742726263133854077814128870757388566818027507662026 Oct 29 02:06:58 PM PDT 23 Oct 29 02:07:00 PM PDT 23 18259183 ps
T980 /workspace/coverage/default/36.edn_stress_all_with_rand_reset.94403415840187266434175659842827366952876936406783323341052964379372081138896 Oct 29 02:08:06 PM PDT 23 Oct 29 02:26:25 PM PDT 23 41708099183 ps

Test location /workspace/coverage/default/193.edn_genbits.86971907567628223395276951004164352337097793700031790067354375596427699369783
Short name T39
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Oct 29 02:08:56 PM PDT 23
Finished Oct 29 02:08:58 PM PDT 23
Peak memory 205816 kb
Host smart-ef057cc7-ea9d-4aae-9905-10813eb8bbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86971907567628223395276951004164352337097793700031790067354375596427699369783 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 193.edn_genbits.86971907567628223395276951004164352337097793700031790067354375596427699369783
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.104853035112389215524897490002975231821651699128138559109567412587649832660061
Short name T1
Test name
Test status
Simulation time 41708099183 ps
CPU time 1099.22 seconds
Started Oct 29 02:06:40 PM PDT 23
Finished Oct 29 02:24:59 PM PDT 23
Peak memory 215836 kb
Host smart-577fae3f-ffe4-4b95-bcd9-3d08459be695
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104853035112389215524897490
002975231821651699128138559109567412587649832660061 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.10485303511
2389215524897490002975231821651699128138559109567412587649832660061
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.107056861061676676310122192079690781418383034129037060231527270694583931273406
Short name T21
Test name
Test status
Simulation time 17319183 ps
CPU time 0.93 seconds
Started Oct 29 02:07:00 PM PDT 23
Finished Oct 29 02:07:05 PM PDT 23
Peak memory 214872 kb
Host smart-350e2f58-3e1a-4d31-8bbd-435604e0f6c4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107056861061676676310122192079690781418383034129037060231527270694583931273406 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable_auto_req_mode.1070568610616766763101221920796907814183830341290370602315
27270694583931273406
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_sec_cm.7767238167343340096654518609776491803550841845739091306168497635567834568229
Short name T30
Test name
Test status
Simulation time 717215632 ps
CPU time 6 seconds
Started Oct 29 02:05:57 PM PDT 23
Finished Oct 29 02:06:04 PM PDT 23
Peak memory 234100 kb
Host smart-f3e70bd4-d501-40fb-a7bf-286c54a3872e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7767238167343340096654518609776491803550841845739091306168497635567834568229 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.edn_sec_cm.7767238167343340096654518609776491803550841845739091306168497635567834568229
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/30.edn_err.6366055899353946367235505976068218582874328518712761263058971151383239732115
Short name T18
Test name
Test status
Simulation time 24963823 ps
CPU time 1.22 seconds
Started Oct 29 02:07:35 PM PDT 23
Finished Oct 29 02:07:37 PM PDT 23
Peak memory 230472 kb
Host smart-5ba20c98-c237-43b2-b703-5460b4098d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6366055899353946367235505976068218582874328518712761263058971151383239732115 -assert nopostproc +UVM_TESTNAME=edn_err_te
st +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
edn_err.6366055899353946367235505976068218582874328518712761263058971151383239732115
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/12.edn_disable.5111066578017999218580987064958964163697629196395782747611789931858561799647
Short name T66
Test name
Test status
Simulation time 12219183 ps
CPU time 0.9 seconds
Started Oct 29 02:07:28 PM PDT 23
Finished Oct 29 02:07:30 PM PDT 23
Peak memory 214864 kb
Host smart-d50ee7e0-fa6d-436a-98c5-9feeaa01c776
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5111066578017999218580987064958964163697629196395782747611789931858561799647 -assert nopostproc
+UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.edn_disable.5111066578017999218580987064958964163697629196395782747611789931858561799647
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.71184947565360954445087902735727136263768949433203127742374963160416058791077
Short name T4
Test name
Test status
Simulation time 155537119 ps
CPU time 2.29 seconds
Started Oct 29 12:56:39 PM PDT 23
Finished Oct 29 12:56:41 PM PDT 23
Peak memory 206572 kb
Host smart-e3964733-d5a5-4e17-8eb9-e4adfea73a6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71184947565360954445087902735727136263768949433203127742374963160416058791077 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.71184947565360954445087902735727136263768949433203127742374963160416058791077
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/default/10.edn_alert.10165720216023218580271491217327308695548415777211664664460798733888129093353
Short name T40
Test name
Test status
Simulation time 18259183 ps
CPU time 0.97 seconds
Started Oct 29 02:07:21 PM PDT 23
Finished Oct 29 02:07:25 PM PDT 23
Peak memory 205588 kb
Host smart-cb7cccb1-9b60-46b2-ab3d-eae3a7fe505a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10165720216023218580271491217327308695548415777211664664460798733888129093353 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.edn_alert.10165720216023218580271491217327308695548415777211664664460798733888129093353
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/0.edn_intr.2303238459693772726869302969666521203031805671019971660547490552636498642810
Short name T309
Test name
Test status
Simulation time 18439183 ps
CPU time 1.11 seconds
Started Oct 29 02:05:53 PM PDT 23
Finished Oct 29 02:05:55 PM PDT 23
Peak memory 222284 kb
Host smart-26fc7da4-529a-4c41-8d60-cf449433d5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303238459693772726869302969666521203031805671019971660547490552636498642810 -assert nopostproc +UVM_TESTNAME=edn_intr_t
est +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.edn_intr.2303238459693772726869302969666521203031805671019971660547490552636498642810
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.108230542478130674470245445195729473381873175921136717004463754569566111662879
Short name T92
Test name
Test status
Simulation time 11759183 ps
CPU time 0.93 seconds
Started Oct 29 02:07:00 PM PDT 23
Finished Oct 29 02:07:05 PM PDT 23
Peak memory 205332 kb
Host smart-f1b7ea89-2c25-44ab-971f-320f7af2558e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108230542478130674470245445195729473381873175921136717004463754569566111662879 -assert nopostproc +UVM_TESTNAME=edn_smok
e_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 2.edn_regwen.108230542478130674470245445195729473381873175921136717004463754569566111662879
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/14.edn_alert_test.84891290393768829734890374732745696459072238741036152398493527782452563490265
Short name T341
Test name
Test status
Simulation time 28184990 ps
CPU time 0.95 seconds
Started Oct 29 02:06:41 PM PDT 23
Finished Oct 29 02:06:42 PM PDT 23
Peak memory 205456 kb
Host smart-6a97de32-49d0-4ea3-8e2b-b7893efbd8dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84891290393768829734890374732745696459072238741036152398493527782452563490265 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.edn_alert_test.84891290393768829734890374732745696459072238741036152398493527782452563490265
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.10196046730393770337296852699579225357102437760215906466070554352734095667868
Short name T12
Test name
Test status
Simulation time 61976116 ps
CPU time 1.33 seconds
Started Oct 29 12:57:38 PM PDT 23
Finished Oct 29 12:57:41 PM PDT 23
Peak memory 206564 kb
Host smart-672b93f0-7bbb-4b10-aa48-f0283548f709
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10196046730393770337296852699579225357102437760215906466070554352734095667868
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_outstanding.10196046730393770337296852699579225357102437760215906466070554352734095667868
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.edn_stress_all.40803390532079311294957861579528134905660855781575125578170003274978836768556
Short name T310
Test name
Test status
Simulation time 154489183 ps
CPU time 4.07 seconds
Started Oct 29 02:05:54 PM PDT 23
Finished Oct 29 02:05:58 PM PDT 23
Peak memory 206352 kb
Host smart-25388d27-3abd-4d62-8914-78b380107af9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40803390532079311294957861579528134905660855781575125578170003274978836768556 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.40803390532079311294957861579528134905660855781575125578170003274978836768556
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.55614804706649106465253206615385027246583922517369145360458288070886946210726
Short name T234
Test name
Test status
Simulation time 59184494 ps
CPU time 1.37 seconds
Started Oct 29 12:56:39 PM PDT 23
Finished Oct 29 12:56:41 PM PDT 23
Peak memory 206492 kb
Host smart-b831b5ab-a248-423f-850d-8847e61ed33d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55614804706649106465253206615385027246583922517369145360458288070886946210726 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.55614804706649106465253206615385027246583922517369145360458288070886946210726
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.19094487623626501895268499756188416974115327801031297612127825566862810331048
Short name T151
Test name
Test status
Simulation time 351971476 ps
CPU time 5.11 seconds
Started Oct 29 12:57:03 PM PDT 23
Finished Oct 29 12:57:08 PM PDT 23
Peak memory 206364 kb
Host smart-30259a51-18de-4ff7-a3a5-be87a3813a82
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19094487623626501895268499756188416974115327801031297612127825566862810331048 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.19094487623626501895268499756188416974115327801031297612127825566862810331048
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.20006662206894454768594576193545072219840706230686245616709911910623006831549
Short name T209
Test name
Test status
Simulation time 26726680 ps
CPU time 0.91 seconds
Started Oct 29 12:56:48 PM PDT 23
Finished Oct 29 12:56:49 PM PDT 23
Peak memory 206484 kb
Host smart-65b10fa5-8ba3-445c-a72c-7bad5eac7c32
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20006662206894454768594576193545072219840706230686245616709911910623006831549 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.20006662206894454768594576193545072219840706230686245616709911910623006831549
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.50596166603154518915270833840619420495781919445741445025454472405247056596822
Short name T130
Test name
Test status
Simulation time 51163789 ps
CPU time 1.37 seconds
Started Oct 29 12:57:11 PM PDT 23
Finished Oct 29 12:57:12 PM PDT 23
Peak memory 214756 kb
Host smart-b4af4080-76d9-4310-83bb-c98a93a97230
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5059616660315451891527083384061942049578191
9445741445025454472405247056596822 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.5059616660315451891527083384
0619420495781919445741445025454472405247056596822
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.79060964408246924659519040957039814470460048851462932047510990899021633944675
Short name T85
Test name
Test status
Simulation time 23247569 ps
CPU time 0.82 seconds
Started Oct 29 12:57:26 PM PDT 23
Finished Oct 29 12:57:29 PM PDT 23
Peak memory 206368 kb
Host smart-b088bea7-d3b1-4ace-8b87-fc1375e20c3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79060964408246924659519040957039814470460048851462932047510990899021633944675 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.79060964408246924659519040957039814470460048851462932047510990899021633944675
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.33714955728969449269362056803751752074816230310433632000186289318060976412751
Short name T219
Test name
Test status
Simulation time 25518366 ps
CPU time 0.83 seconds
Started Oct 29 12:57:02 PM PDT 23
Finished Oct 29 12:57:03 PM PDT 23
Peak memory 206408 kb
Host smart-ef719723-d2a7-42eb-b8c5-dc3045c20a8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33714955728969449269362056803751752074816230310433632000186289318060976412751 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 0.edn_intr_test.33714955728969449269362056803751752074816230310433632000186289318060976412751
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3312653407676401934781594626040921057899281014665857377732138024394458285166
Short name T183
Test name
Test status
Simulation time 61976116 ps
CPU time 1.31 seconds
Started Oct 29 12:57:26 PM PDT 23
Finished Oct 29 12:57:34 PM PDT 23
Peak memory 206548 kb
Host smart-8595e3c1-b35d-40cd-9db0-08cb6e0d056a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312653407676401934781594626040921057899281014665857377732138024394458285166 -
assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_outstanding.3312653407676401934781594626040921057899281014665857377732138024394458285166
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.40430770244730971052831315599862989633512581407821168676167982550881057491724
Short name T188
Test name
Test status
Simulation time 204078009 ps
CPU time 3.69 seconds
Started Oct 29 12:57:08 PM PDT 23
Finished Oct 29 12:57:12 PM PDT 23
Peak memory 214664 kb
Host smart-89cb912a-a2e3-4099-8ca5-a4f53e45ad0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40430770244730971052831315599862989633512581407821168676167982550881057491724 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 0.edn_tl_errors.40430770244730971052831315599862989633512581407821168676167982550881057491724
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.6474902708042677252718996331049541778155264675787800162783172381490719128439
Short name T165
Test name
Test status
Simulation time 59184494 ps
CPU time 1.35 seconds
Started Oct 29 12:56:39 PM PDT 23
Finished Oct 29 12:56:41 PM PDT 23
Peak memory 206368 kb
Host smart-54772336-4b56-44fd-9a51-104cbcc7d7df
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6474902708042677252718996331049541778155264675787800162783172381490719128439 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.6474902708042677252718996331049541778155264675787800162783172381490719128439
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.96410485990615766942714167394739549603161358717123964915027038017452573870013
Short name T139
Test name
Test status
Simulation time 351971476 ps
CPU time 5.07 seconds
Started Oct 29 12:57:04 PM PDT 23
Finished Oct 29 12:57:10 PM PDT 23
Peak memory 206492 kb
Host smart-3c9cf075-e9fa-45fd-b2f8-b4c4b455a08e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96410485990615766942714167394739549603161358717123964915027038017452573870013 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.96410485990615766942714167394739549603161358717123964915027038017452573870013
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.103121566323094553944085619221514926493074806803997884718523132619343022986292
Short name T141
Test name
Test status
Simulation time 26726680 ps
CPU time 0.9 seconds
Started Oct 29 12:56:39 PM PDT 23
Finished Oct 29 12:56:40 PM PDT 23
Peak memory 206468 kb
Host smart-10ba9c0e-12cc-46fd-9162-4fba14c2927a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103121566323094553944085619221514926493074806803997884718523132619343022986292 -assert nop
ostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.103121566323094553944085619221514926493074806803997884718523132619343022986292
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.57551960924363750636103524625860972781572899656346386265108654652792080176373
Short name T103
Test name
Test status
Simulation time 51163789 ps
CPU time 1.33 seconds
Started Oct 29 12:56:40 PM PDT 23
Finished Oct 29 12:56:41 PM PDT 23
Peak memory 214752 kb
Host smart-3c668b4e-81f2-44ca-a6fd-33f4ec7be78b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5755196092436375063610352462586097278157289
9656346386265108654652792080176373 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.5755196092436375063610352462
5860972781572899656346386265108654652792080176373
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.114555927064024996152638552106596665144746502172423566720161118841559020166136
Short name T11
Test name
Test status
Simulation time 23247569 ps
CPU time 0.86 seconds
Started Oct 29 12:58:23 PM PDT 23
Finished Oct 29 12:58:24 PM PDT 23
Peak memory 206252 kb
Host smart-e1fb29c1-6591-4c04-bc10-70022be66c5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114555927064024996152638552106596665144746502172423566720161118841559020166136 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.114555927064024996152638552106596665144746502172423566720161118841559020166136
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.56893261906708285033577208125130905598267707966214006151424456745430284862445
Short name T208
Test name
Test status
Simulation time 25518366 ps
CPU time 0.83 seconds
Started Oct 29 12:58:29 PM PDT 23
Finished Oct 29 12:58:30 PM PDT 23
Peak memory 206288 kb
Host smart-1d4bf96c-1922-4143-a428-17d3f5d2bd4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56893261906708285033577208125130905598267707966214006151424456745430284862445 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 1.edn_intr_test.56893261906708285033577208125130905598267707966214006151424456745430284862445
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.73803431307963662846696198889097541117483321774262227259663540209414932692425
Short name T142
Test name
Test status
Simulation time 61976116 ps
CPU time 1.3 seconds
Started Oct 29 12:56:31 PM PDT 23
Finished Oct 29 12:56:32 PM PDT 23
Peak memory 206464 kb
Host smart-bdc4754b-d851-453f-8a31-5533da6a766c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73803431307963662846696198889097541117483321774262227259663540209414932692425
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_outstanding.73803431307963662846696198889097541117483321774262227259663540209414932692425
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.10122053955991912184919749706684580467064713223669981412312974116617180081967
Short name T128
Test name
Test status
Simulation time 204078009 ps
CPU time 3.54 seconds
Started Oct 29 12:57:30 PM PDT 23
Finished Oct 29 12:57:35 PM PDT 23
Peak memory 214664 kb
Host smart-a4e0737f-d467-4695-bbce-80ca142f3500
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10122053955991912184919749706684580467064713223669981412312974116617180081967 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 1.edn_tl_errors.10122053955991912184919749706684580467064713223669981412312974116617180081967
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.30960272551377468847999347134909380026958095324779743977578885614792673421584
Short name T210
Test name
Test status
Simulation time 155537119 ps
CPU time 2.16 seconds
Started Oct 29 12:57:30 PM PDT 23
Finished Oct 29 12:57:34 PM PDT 23
Peak memory 206408 kb
Host smart-556b2eda-e25c-4213-ae57-d024d204356c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30960272551377468847999347134909380026958095324779743977578885614792673421584 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.30960272551377468847999347134909380026958095324779743977578885614792673421584
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.33738830533115934453529071161337984620035694587587148888914856513465495151926
Short name T164
Test name
Test status
Simulation time 51163789 ps
CPU time 1.27 seconds
Started Oct 29 12:57:14 PM PDT 23
Finished Oct 29 12:57:16 PM PDT 23
Peak memory 214684 kb
Host smart-0230e792-0ea3-43c8-b187-268faf0e35d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373883053311593445352907116133798462003569
4587587148888914856513465495151926 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.337388305331159344535290711
61337984620035694587587148888914856513465495151926
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.19453303561506572107179371117870693258840985175618797821855794636557609636242
Short name T214
Test name
Test status
Simulation time 23247569 ps
CPU time 0.86 seconds
Started Oct 29 12:56:47 PM PDT 23
Finished Oct 29 12:56:48 PM PDT 23
Peak memory 206484 kb
Host smart-6ee7e80a-8abb-4f6e-bfc2-39c2f536e9eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19453303561506572107179371117870693258840985175618797821855794636557609636242 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.19453303561506572107179371117870693258840985175618797821855794636557609636242
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.7365270046585201318250920195219450693399465985653158849401266881074953327124
Short name T113
Test name
Test status
Simulation time 25518366 ps
CPU time 0.85 seconds
Started Oct 29 12:57:00 PM PDT 23
Finished Oct 29 12:57:01 PM PDT 23
Peak memory 206404 kb
Host smart-3c858144-5ad1-4121-a2e8-94c535f7975a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7365270046585201318250920195219450693399465985653158849401266881074953327124 -assert nopostproc +UV
M_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.edn_intr_test.7365270046585201318250920195219450693399465985653158849401266881074953327124
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.29778572750271533991357319993122720826242747835873391404765727898597297494934
Short name T168
Test name
Test status
Simulation time 61976116 ps
CPU time 1.28 seconds
Started Oct 29 12:57:25 PM PDT 23
Finished Oct 29 12:57:29 PM PDT 23
Peak memory 206512 kb
Host smart-3c1fd4e1-7452-4745-862a-d129521d63d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29778572750271533991357319993122720826242747835873391404765727898597297494934
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_outstanding.29778572750271533991357319993122720826242747835873391404765727898597297494934
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.17518218036650096318857480977669252565874479021197897130730533029263020738888
Short name T140
Test name
Test status
Simulation time 204078009 ps
CPU time 3.85 seconds
Started Oct 29 12:56:54 PM PDT 23
Finished Oct 29 12:56:58 PM PDT 23
Peak memory 214604 kb
Host smart-4301b383-e2e6-43a5-affd-12ec7fb5a394
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17518218036650096318857480977669252565874479021197897130730533029263020738888 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 10.edn_tl_errors.17518218036650096318857480977669252565874479021197897130730533029263020738888
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.99544246289825344002359265808981797633592887845968130977681870364591743873802
Short name T199
Test name
Test status
Simulation time 155537119 ps
CPU time 2.24 seconds
Started Oct 29 12:57:15 PM PDT 23
Finished Oct 29 12:57:18 PM PDT 23
Peak memory 206516 kb
Host smart-721ea3cc-fdc9-4e6f-9709-8d3efa9dbcf5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99544246289825344002359265808981797633592887845968130977681870364591743873802 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.99544246289825344002359265808981797633592887845968130977681870364591743873802
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.72361992484035229563268137499875054089449590576800392624574203428891307040460
Short name T193
Test name
Test status
Simulation time 51163789 ps
CPU time 1.31 seconds
Started Oct 29 12:56:59 PM PDT 23
Finished Oct 29 12:57:00 PM PDT 23
Peak memory 214932 kb
Host smart-528b2859-7f8b-4772-bf27-5a2c81afc60d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7236199248403522956326813749987505408944959
0576800392624574203428891307040460 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.723619924840352295632681374
99875054089449590576800392624574203428891307040460
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.78469213116692302435743099063682364628210381973987859413649617571592601231956
Short name T102
Test name
Test status
Simulation time 23247569 ps
CPU time 0.85 seconds
Started Oct 29 12:56:58 PM PDT 23
Finished Oct 29 12:56:59 PM PDT 23
Peak memory 206400 kb
Host smart-d0cf0a46-a65b-4ae1-b1ae-1d72a07bf094
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78469213116692302435743099063682364628210381973987859413649617571592601231956 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.78469213116692302435743099063682364628210381973987859413649617571592601231956
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.35936238832470704492155674969280312480459379328311036816586101133923329666726
Short name T156
Test name
Test status
Simulation time 25518366 ps
CPU time 0.82 seconds
Started Oct 29 12:57:15 PM PDT 23
Finished Oct 29 12:57:16 PM PDT 23
Peak memory 206332 kb
Host smart-b5bea540-2e2a-4b66-be7c-6b78752244b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35936238832470704492155674969280312480459379328311036816586101133923329666726 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 11.edn_intr_test.35936238832470704492155674969280312480459379328311036816586101133923329666726
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.53267637100674751906211684088187776120498062241381388230520351602978062649520
Short name T175
Test name
Test status
Simulation time 204078009 ps
CPU time 3.84 seconds
Started Oct 29 12:57:05 PM PDT 23
Finished Oct 29 12:57:09 PM PDT 23
Peak memory 214716 kb
Host smart-c60cd23e-3071-41d5-af8c-91476dfedad9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53267637100674751906211684088187776120498062241381388230520351602978062649520 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 11.edn_tl_errors.53267637100674751906211684088187776120498062241381388230520351602978062649520
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.11030144818573968651606663188480871787661069944808156732441710260657418325902
Short name T160
Test name
Test status
Simulation time 155537119 ps
CPU time 2.17 seconds
Started Oct 29 12:56:42 PM PDT 23
Finished Oct 29 12:56:45 PM PDT 23
Peak memory 206520 kb
Host smart-ca5eb863-bebc-404d-962c-3ed061dea7ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11030144818573968651606663188480871787661069944808156732441710260657418325902 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.11030144818573968651606663188480871787661069944808156732441710260657418325902
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.106193229633357689400088810047522911950151035280337955419421357629670921460534
Short name T225
Test name
Test status
Simulation time 51163789 ps
CPU time 1.29 seconds
Started Oct 29 12:57:07 PM PDT 23
Finished Oct 29 12:57:09 PM PDT 23
Peak memory 214724 kb
Host smart-06970c3d-92c9-4e59-bd1d-7e62ad408b55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061932296333576894000888100475229119501510
35280337955419421357629670921460534 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.10619322963335768940008881
0047522911950151035280337955419421357629670921460534
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.13768539491282555253079006258543232995763213385747894168903478871886481459927
Short name T137
Test name
Test status
Simulation time 23247569 ps
CPU time 0.84 seconds
Started Oct 29 12:57:43 PM PDT 23
Finished Oct 29 12:57:48 PM PDT 23
Peak memory 206496 kb
Host smart-b4cfb1e9-f6ff-49c6-bd01-b8b1e98b4db5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13768539491282555253079006258543232995763213385747894168903478871886481459927 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.13768539491282555253079006258543232995763213385747894168903478871886481459927
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.97783495333111428719754423115270085815809696758813614119928679721744803716179
Short name T227
Test name
Test status
Simulation time 25518366 ps
CPU time 0.88 seconds
Started Oct 29 12:56:51 PM PDT 23
Finished Oct 29 12:56:52 PM PDT 23
Peak memory 206324 kb
Host smart-ca97a51f-d8eb-4826-965d-0f2346a97fb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97783495333111428719754423115270085815809696758813614119928679721744803716179 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 12.edn_intr_test.97783495333111428719754423115270085815809696758813614119928679721744803716179
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.12655808236940487624685569064922947678646295508624763434089018398402729698159
Short name T88
Test name
Test status
Simulation time 61976116 ps
CPU time 1.32 seconds
Started Oct 29 12:56:47 PM PDT 23
Finished Oct 29 12:56:49 PM PDT 23
Peak memory 206484 kb
Host smart-2e00eea3-accc-418b-869f-253783551dd9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12655808236940487624685569064922947678646295508624763434089018398402729698159
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_outstanding.12655808236940487624685569064922947678646295508624763434089018398402729698159
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.12526884054645200786094571634173373686967967306340500745652802958204118494273
Short name T2
Test name
Test status
Simulation time 204078009 ps
CPU time 3.85 seconds
Started Oct 29 12:57:13 PM PDT 23
Finished Oct 29 12:57:18 PM PDT 23
Peak memory 214672 kb
Host smart-150ce86b-12b7-4600-ad64-0af1651d7633
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12526884054645200786094571634173373686967967306340500745652802958204118494273 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 12.edn_tl_errors.12526884054645200786094571634173373686967967306340500745652802958204118494273
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.36001130055793094153876904015632413626230179309880417981570070419516807346951
Short name T197
Test name
Test status
Simulation time 155537119 ps
CPU time 2.14 seconds
Started Oct 29 12:56:56 PM PDT 23
Finished Oct 29 12:56:58 PM PDT 23
Peak memory 206536 kb
Host smart-80569235-2a8a-4190-a50d-320cdd6bf7e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36001130055793094153876904015632413626230179309880417981570070419516807346951 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.36001130055793094153876904015632413626230179309880417981570070419516807346951
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.9921844840674703026949246613481232988418079644607214390418976297670344105110
Short name T6
Test name
Test status
Simulation time 51163789 ps
CPU time 1.31 seconds
Started Oct 29 12:57:45 PM PDT 23
Finished Oct 29 12:57:48 PM PDT 23
Peak memory 214728 kb
Host smart-b0181cda-1610-4a5d-8c5f-2ef439345d88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9921844840674703026949246613481232988418079
644607214390418976297670344105110 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.9921844840674703026949246613
481232988418079644607214390418976297670344105110
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.51394334889209283600421277234767392402446454897001834742759266184631450998229
Short name T106
Test name
Test status
Simulation time 23247569 ps
CPU time 0.91 seconds
Started Oct 29 12:57:03 PM PDT 23
Finished Oct 29 12:57:05 PM PDT 23
Peak memory 205700 kb
Host smart-6d181ba1-6f6f-412b-aada-da5a0ad4059c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51394334889209283600421277234767392402446454897001834742759266184631450998229 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.51394334889209283600421277234767392402446454897001834742759266184631450998229
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.62111206889800655896432703736660966235156263931799395143950682702313264592500
Short name T184
Test name
Test status
Simulation time 25518366 ps
CPU time 0.9 seconds
Started Oct 29 12:58:14 PM PDT 23
Finished Oct 29 12:58:16 PM PDT 23
Peak memory 204880 kb
Host smart-52f16835-a96d-4e27-8cfa-85b48c76dedc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62111206889800655896432703736660966235156263931799395143950682702313264592500 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 13.edn_intr_test.62111206889800655896432703736660966235156263931799395143950682702313264592500
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.89296163952849313929509415549782576980478922636937621281716261323552157017796
Short name T81
Test name
Test status
Simulation time 61976116 ps
CPU time 1.31 seconds
Started Oct 29 12:57:28 PM PDT 23
Finished Oct 29 12:57:34 PM PDT 23
Peak memory 206548 kb
Host smart-965363ca-80a5-4de5-b25b-6fc985e7d2cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89296163952849313929509415549782576980478922636937621281716261323552157017796
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_outstanding.89296163952849313929509415549782576980478922636937621281716261323552157017796
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.57494241340550285699430442159324389178684626271111277510189823777761332044618
Short name T233
Test name
Test status
Simulation time 204078009 ps
CPU time 3.6 seconds
Started Oct 29 12:56:45 PM PDT 23
Finished Oct 29 12:56:50 PM PDT 23
Peak memory 214724 kb
Host smart-34f550d5-1eb5-4ca1-8dd3-51fe413aeeae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57494241340550285699430442159324389178684626271111277510189823777761332044618 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 13.edn_tl_errors.57494241340550285699430442159324389178684626271111277510189823777761332044618
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.59370027287811980709624823229490743618182291746803960888696836284090396276181
Short name T75
Test name
Test status
Simulation time 155537119 ps
CPU time 2.28 seconds
Started Oct 29 12:57:29 PM PDT 23
Finished Oct 29 12:57:32 PM PDT 23
Peak memory 206444 kb
Host smart-ccf229e1-3450-4492-a5ee-ad53c1e789c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59370027287811980709624823229490743618182291746803960888696836284090396276181 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.59370027287811980709624823229490743618182291746803960888696836284090396276181
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.83862050494122067568822426145600142119214509177287925592842741043747020795093
Short name T167
Test name
Test status
Simulation time 51163789 ps
CPU time 1.24 seconds
Started Oct 29 12:58:25 PM PDT 23
Finished Oct 29 12:58:26 PM PDT 23
Peak memory 214644 kb
Host smart-c46fb155-837e-486c-8d97-c85a81afec26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8386205049412206756882242614560014211921450
9177287925592842741043747020795093 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.838620504941220675688224261
45600142119214509177287925592842741043747020795093
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.90489017192693411599326589245040463159960242036420732219785816338251274000951
Short name T154
Test name
Test status
Simulation time 23247569 ps
CPU time 0.85 seconds
Started Oct 29 12:57:23 PM PDT 23
Finished Oct 29 12:57:25 PM PDT 23
Peak memory 206468 kb
Host smart-5f64264d-be84-4052-ac65-ae13270e2335
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90489017192693411599326589245040463159960242036420732219785816338251274000951 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.90489017192693411599326589245040463159960242036420732219785816338251274000951
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.108730117562607267265157266179776240441204437502884228854054073664332840220876
Short name T153
Test name
Test status
Simulation time 25518366 ps
CPU time 0.84 seconds
Started Oct 29 12:57:39 PM PDT 23
Finished Oct 29 12:57:41 PM PDT 23
Peak memory 206396 kb
Host smart-8283b26f-d9aa-46e5-a71d-b028283d7842
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108730117562607267265157266179776240441204437502884228854054073664332840220876 -assert nopostproc +
UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.edn_intr_test.108730117562607267265157266179776240441204437502884228854054073664332840220876
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.613528232679258096078100303832420756890434293918411263466212234131328029117
Short name T110
Test name
Test status
Simulation time 61976116 ps
CPU time 1.32 seconds
Started Oct 29 12:56:50 PM PDT 23
Finished Oct 29 12:56:51 PM PDT 23
Peak memory 206428 kb
Host smart-cb783a4e-6d76-4747-944b-d339291befeb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613528232679258096078100303832420756890434293918411263466212234131328029117 -a
ssert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_outstanding.613528232679258096078100303832420756890434293918411263466212234131328029117
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.42506541861002313568232415972575715516779647709296090892080971973038846947631
Short name T161
Test name
Test status
Simulation time 204078009 ps
CPU time 3.82 seconds
Started Oct 29 12:57:00 PM PDT 23
Finished Oct 29 12:57:04 PM PDT 23
Peak memory 214656 kb
Host smart-1b892868-0f94-4f5e-88d6-10e32ba90596
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42506541861002313568232415972575715516779647709296090892080971973038846947631 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 14.edn_tl_errors.42506541861002313568232415972575715516779647709296090892080971973038846947631
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.6196193744460248704263540742341248308726056149501286751227611488469445837382
Short name T159
Test name
Test status
Simulation time 155537119 ps
CPU time 2.16 seconds
Started Oct 29 12:57:31 PM PDT 23
Finished Oct 29 12:57:34 PM PDT 23
Peak memory 206520 kb
Host smart-26b5aa25-7e14-4b38-a194-00acdbd17668
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6196193744460248704263540742341248308726056149501286751227611488469445837382 -assert no
postproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.6196193744460248704263540742341248308726056149501286751227611488469445837382
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.93567324503292293601217675665084368583161452893212025481509913423847941260765
Short name T117
Test name
Test status
Simulation time 51163789 ps
CPU time 1.32 seconds
Started Oct 29 12:57:36 PM PDT 23
Finished Oct 29 12:57:38 PM PDT 23
Peak memory 214752 kb
Host smart-f31f2eaa-d240-4931-b04e-fe831f662cab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9356732450329229360121767566508436858316145
2893212025481509913423847941260765 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.935673245032922936012176756
65084368583161452893212025481509913423847941260765
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.49006113022615892899683658923991316837794876914110892807332117636249236143828
Short name T149
Test name
Test status
Simulation time 23247569 ps
CPU time 0.83 seconds
Started Oct 29 12:57:37 PM PDT 23
Finished Oct 29 12:57:39 PM PDT 23
Peak memory 206448 kb
Host smart-588e7ec3-5e4c-42b5-ad5f-c73426e006b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49006113022615892899683658923991316837794876914110892807332117636249236143828 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.49006113022615892899683658923991316837794876914110892807332117636249236143828
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.20963653253459430034361916894421634272655835792162870817987887017758669314982
Short name T180
Test name
Test status
Simulation time 25518366 ps
CPU time 0.87 seconds
Started Oct 29 12:57:26 PM PDT 23
Finished Oct 29 12:57:34 PM PDT 23
Peak memory 206444 kb
Host smart-1a784815-cecc-48b2-bc21-0fd3ed1e392d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20963653253459430034361916894421634272655835792162870817987887017758669314982 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 15.edn_intr_test.20963653253459430034361916894421634272655835792162870817987887017758669314982
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.20148587198547759218257255761610707174290093147493866674453036881280131955118
Short name T143
Test name
Test status
Simulation time 61976116 ps
CPU time 1.33 seconds
Started Oct 29 12:57:30 PM PDT 23
Finished Oct 29 12:57:33 PM PDT 23
Peak memory 206528 kb
Host smart-156c92c1-20b4-4995-be0c-c240176de362
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20148587198547759218257255761610707174290093147493866674453036881280131955118
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_outstanding.20148587198547759218257255761610707174290093147493866674453036881280131955118
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.115167603157406141534688143969554386959837671393799650256828545208420296154200
Short name T191
Test name
Test status
Simulation time 204078009 ps
CPU time 3.65 seconds
Started Oct 29 12:56:58 PM PDT 23
Finished Oct 29 12:57:02 PM PDT 23
Peak memory 214688 kb
Host smart-8076ec34-e7e9-48b1-9678-8dec54deb404
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115167603157406141534688143969554386959837671393799650256828545208420296154200 -assert nopostproc +
UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.edn_tl_errors.115167603157406141534688143969554386959837671393799650256828545208420296154200
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.115473990990064736191953668696309456984246216004274584612638340400239057050914
Short name T101
Test name
Test status
Simulation time 155537119 ps
CPU time 2.28 seconds
Started Oct 29 12:56:47 PM PDT 23
Finished Oct 29 12:56:50 PM PDT 23
Peak memory 206524 kb
Host smart-3c660d3d-0f4d-468e-a456-4b1fae841ab1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115473990990064736191953668696309456984246216004274584612638340400239057050914 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.115473990990064736191953668696309456984246216004274584612638340400239057050914
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.104456482121139201223175529565280597042355318485582533939866564222252050351858
Short name T220
Test name
Test status
Simulation time 51163789 ps
CPU time 1.31 seconds
Started Oct 29 12:57:25 PM PDT 23
Finished Oct 29 12:57:29 PM PDT 23
Peak memory 214764 kb
Host smart-d7ab5f9f-9ecb-4cc8-adbb-d904037353b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044564821211392012231755295652805970423553
18485582533939866564222252050351858 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.10445648212113920122317552
9565280597042355318485582533939866564222252050351858
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.84842876324698934014881288180053045567141205060836358681745379514708665207367
Short name T232
Test name
Test status
Simulation time 23247569 ps
CPU time 0.91 seconds
Started Oct 29 12:56:48 PM PDT 23
Finished Oct 29 12:56:49 PM PDT 23
Peak memory 206488 kb
Host smart-afd8b069-d068-4c64-a013-89a1736deb74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84842876324698934014881288180053045567141205060836358681745379514708665207367 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.84842876324698934014881288180053045567141205060836358681745379514708665207367
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.38436408894730763189945995061686422281733809272563808744155319265238654111904
Short name T157
Test name
Test status
Simulation time 25518366 ps
CPU time 0.86 seconds
Started Oct 29 12:56:49 PM PDT 23
Finished Oct 29 12:56:50 PM PDT 23
Peak memory 206388 kb
Host smart-435d9909-50c7-4eee-a535-91c66dfef3d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38436408894730763189945995061686422281733809272563808744155319265238654111904 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 16.edn_intr_test.38436408894730763189945995061686422281733809272563808744155319265238654111904
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.103192328579957965917442598954258103827822000070465109441936442736496902075825
Short name T82
Test name
Test status
Simulation time 61976116 ps
CPU time 1.34 seconds
Started Oct 29 12:57:30 PM PDT 23
Finished Oct 29 12:57:33 PM PDT 23
Peak memory 206568 kb
Host smart-c0bc2950-157e-4521-99de-c53c9d53686d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103192328579957965917442598954258103827822000070465109441936442736496902075825
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_outstanding.103192328579957965917442598954258103827822000070465109441936442736496902075825
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.98942280671078087685849748409395161559454425413742132237690892844932238994340
Short name T10
Test name
Test status
Simulation time 204078009 ps
CPU time 3.74 seconds
Started Oct 29 12:57:28 PM PDT 23
Finished Oct 29 12:57:32 PM PDT 23
Peak memory 214680 kb
Host smart-23948323-f694-4d81-b85b-dc2f3f8589bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98942280671078087685849748409395161559454425413742132237690892844932238994340 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 16.edn_tl_errors.98942280671078087685849748409395161559454425413742132237690892844932238994340
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.67134795815144627851841082613043021300203125388961916034876855374981143231824
Short name T178
Test name
Test status
Simulation time 155537119 ps
CPU time 2.24 seconds
Started Oct 29 12:58:15 PM PDT 23
Finished Oct 29 12:58:18 PM PDT 23
Peak memory 206260 kb
Host smart-f167f038-8cce-4d0e-8419-4c862e75d744
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67134795815144627851841082613043021300203125388961916034876855374981143231824 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.67134795815144627851841082613043021300203125388961916034876855374981143231824
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.51423387671327089073136109292650120850519788251744255936269868710870822881898
Short name T136
Test name
Test status
Simulation time 51163789 ps
CPU time 1.28 seconds
Started Oct 29 12:57:23 PM PDT 23
Finished Oct 29 12:57:24 PM PDT 23
Peak memory 214712 kb
Host smart-8a6adcf9-7b66-4fa2-8278-c91b84dc26a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5142338767132708907313610929265012085051978
8251744255936269868710870822881898 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.514233876713270890731361092
92650120850519788251744255936269868710870822881898
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.77134109083585655679761945346939372829008161165457419707167695116318373866842
Short name T203
Test name
Test status
Simulation time 23247569 ps
CPU time 0.84 seconds
Started Oct 29 12:57:02 PM PDT 23
Finished Oct 29 12:57:03 PM PDT 23
Peak memory 206476 kb
Host smart-ecf1bd6a-6793-476c-85ba-aabcaf265d08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77134109083585655679761945346939372829008161165457419707167695116318373866842 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.77134109083585655679761945346939372829008161165457419707167695116318373866842
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.94696141058059333839077023380149332915944583469301181188172312233608471506668
Short name T104
Test name
Test status
Simulation time 25518366 ps
CPU time 0.83 seconds
Started Oct 29 12:57:05 PM PDT 23
Finished Oct 29 12:57:06 PM PDT 23
Peak memory 206460 kb
Host smart-c224e478-1758-4b56-9dfa-946579ae70c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94696141058059333839077023380149332915944583469301181188172312233608471506668 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 17.edn_intr_test.94696141058059333839077023380149332915944583469301181188172312233608471506668
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.72005104909946280351087516563297615196055422307367456117646462431334504084705
Short name T86
Test name
Test status
Simulation time 61976116 ps
CPU time 1.33 seconds
Started Oct 29 12:57:26 PM PDT 23
Finished Oct 29 12:57:29 PM PDT 23
Peak memory 206508 kb
Host smart-c5f0813c-b874-466c-98db-aaed99de0805
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72005104909946280351087516563297615196055422307367456117646462431334504084705
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_outstanding.72005104909946280351087516563297615196055422307367456117646462431334504084705
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.113512113746979812717350814495648438186470738840036379560504804552193123552167
Short name T194
Test name
Test status
Simulation time 204078009 ps
CPU time 3.7 seconds
Started Oct 29 12:57:12 PM PDT 23
Finished Oct 29 12:57:16 PM PDT 23
Peak memory 214688 kb
Host smart-4f34de7c-51ed-4b77-9411-4e7744fe44c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113512113746979812717350814495648438186470738840036379560504804552193123552167 -assert nopostproc +
UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.edn_tl_errors.113512113746979812717350814495648438186470738840036379560504804552193123552167
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.43929749887987869845251033780356287885889737410231575423962105617526307740090
Short name T148
Test name
Test status
Simulation time 155537119 ps
CPU time 2.22 seconds
Started Oct 29 12:57:00 PM PDT 23
Finished Oct 29 12:57:03 PM PDT 23
Peak memory 206468 kb
Host smart-953e9cef-b08e-43b5-ab66-b749fb1e0256
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43929749887987869845251033780356287885889737410231575423962105617526307740090 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.43929749887987869845251033780356287885889737410231575423962105617526307740090
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.112805790077495670450068729651934206847203046899156856869062370493747599188027
Short name T198
Test name
Test status
Simulation time 51163789 ps
CPU time 1.28 seconds
Started Oct 29 12:56:49 PM PDT 23
Finished Oct 29 12:56:51 PM PDT 23
Peak memory 214736 kb
Host smart-b4f6b316-df1e-4f54-83a1-cfe7603787d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128057900774956704500687296519342068472030
46899156856869062370493747599188027 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.11280579007749567045006872
9651934206847203046899156856869062370493747599188027
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.114452237529054102928650105412654084716463158776431330387970568694845326979271
Short name T202
Test name
Test status
Simulation time 23247569 ps
CPU time 0.88 seconds
Started Oct 29 12:57:22 PM PDT 23
Finished Oct 29 12:57:23 PM PDT 23
Peak memory 206432 kb
Host smart-cc7e8e9f-093b-47e5-a230-3c0a5ea33481
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114452237529054102928650105412654084716463158776431330387970568694845326979271 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.114452237529054102928650105412654084716463158776431330387970568694845326979271
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.77061156394621278846240322516851462810278745347369691416871648345732913895384
Short name T186
Test name
Test status
Simulation time 25518366 ps
CPU time 0.82 seconds
Started Oct 29 12:58:17 PM PDT 23
Finished Oct 29 12:58:19 PM PDT 23
Peak memory 206300 kb
Host smart-c925c4a8-fa00-4bb2-a9c5-5b150c07a2b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77061156394621278846240322516851462810278745347369691416871648345732913895384 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 18.edn_intr_test.77061156394621278846240322516851462810278745347369691416871648345732913895384
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.108165938489399104818180196870389008165559364559639622885517524464631503218121
Short name T79
Test name
Test status
Simulation time 61976116 ps
CPU time 1.35 seconds
Started Oct 29 12:57:26 PM PDT 23
Finished Oct 29 12:57:29 PM PDT 23
Peak memory 206576 kb
Host smart-1f040afe-5efe-4831-b48d-3b659d590871
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108165938489399104818180196870389008165559364559639622885517524464631503218121
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_outstanding.108165938489399104818180196870389008165559364559639622885517524464631503218121
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.1116602780995490896496780366429520102535774189327721473231920800656916681446
Short name T3
Test name
Test status
Simulation time 204078009 ps
CPU time 3.63 seconds
Started Oct 29 12:57:29 PM PDT 23
Finished Oct 29 12:57:33 PM PDT 23
Peak memory 214544 kb
Host smart-841035a2-d0f4-4b06-becf-551f9e239f21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116602780995490896496780366429520102535774189327721473231920800656916681446 -assert nopostproc +UV
M_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.edn_tl_errors.1116602780995490896496780366429520102535774189327721473231920800656916681446
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.43517815615819473248077306938970310145274251645006206688997844317339193323642
Short name T76
Test name
Test status
Simulation time 155537119 ps
CPU time 2.23 seconds
Started Oct 29 12:57:00 PM PDT 23
Finished Oct 29 12:57:02 PM PDT 23
Peak memory 206552 kb
Host smart-fdd32fe2-b4f2-4cb2-b09b-fbb833b223a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43517815615819473248077306938970310145274251645006206688997844317339193323642 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.43517815615819473248077306938970310145274251645006206688997844317339193323642
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.51899251064023549778873045092002587054620440658881485972987133579312205478249
Short name T173
Test name
Test status
Simulation time 51163789 ps
CPU time 1.28 seconds
Started Oct 29 12:57:27 PM PDT 23
Finished Oct 29 12:57:29 PM PDT 23
Peak memory 214748 kb
Host smart-0d6df296-6ecd-4af7-821c-e8cc91bb1d9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5189925106402354977887304509200258705462044
0658881485972987133579312205478249 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.518992510640235497788730450
92002587054620440658881485972987133579312205478249
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.64913596566341945632475900134161006044972241961669227606022733402416739405445
Short name T179
Test name
Test status
Simulation time 23247569 ps
CPU time 0.94 seconds
Started Oct 29 12:57:01 PM PDT 23
Finished Oct 29 12:57:03 PM PDT 23
Peak memory 206476 kb
Host smart-696f721e-f0e7-4ff8-bb07-6645f518b166
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64913596566341945632475900134161006044972241961669227606022733402416739405445 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.64913596566341945632475900134161006044972241961669227606022733402416739405445
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.58367215332437175226711678154550381286160228154467246785643275569050134813131
Short name T176
Test name
Test status
Simulation time 25518366 ps
CPU time 0.86 seconds
Started Oct 29 12:56:50 PM PDT 23
Finished Oct 29 12:56:51 PM PDT 23
Peak memory 206392 kb
Host smart-67a0e73a-d542-4f43-beeb-097431646a62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58367215332437175226711678154550381286160228154467246785643275569050134813131 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 19.edn_intr_test.58367215332437175226711678154550381286160228154467246785643275569050134813131
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.405569647257454150129090892698851211673322834784709037934132494604470612862
Short name T83
Test name
Test status
Simulation time 61976116 ps
CPU time 1.36 seconds
Started Oct 29 12:57:29 PM PDT 23
Finished Oct 29 12:57:31 PM PDT 23
Peak memory 206588 kb
Host smart-dbfb485d-207c-4c2c-af46-370f27d0d510
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405569647257454150129090892698851211673322834784709037934132494604470612862 -a
ssert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_outstanding.405569647257454150129090892698851211673322834784709037934132494604470612862
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.67659051347872667024663961924972337592495700198429319452161685233649255513135
Short name T119
Test name
Test status
Simulation time 204078009 ps
CPU time 3.61 seconds
Started Oct 29 12:57:27 PM PDT 23
Finished Oct 29 12:57:32 PM PDT 23
Peak memory 214556 kb
Host smart-deda0776-8f1e-428e-aa35-905863c19f15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67659051347872667024663961924972337592495700198429319452161685233649255513135 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 19.edn_tl_errors.67659051347872667024663961924972337592495700198429319452161685233649255513135
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.103284794218280427178662755833478156397793659052347987273545799709008888653554
Short name T133
Test name
Test status
Simulation time 155537119 ps
CPU time 2.19 seconds
Started Oct 29 12:57:55 PM PDT 23
Finished Oct 29 12:57:58 PM PDT 23
Peak memory 206416 kb
Host smart-b7ae2935-cf3a-40a1-8b94-1ef61fee35dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103284794218280427178662755833478156397793659052347987273545799709008888653554 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.103284794218280427178662755833478156397793659052347987273545799709008888653554
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.69587275718995240149155802878771639009571705442828839238728628242696415825320
Short name T84
Test name
Test status
Simulation time 59184494 ps
CPU time 1.27 seconds
Started Oct 29 12:56:36 PM PDT 23
Finished Oct 29 12:56:38 PM PDT 23
Peak memory 206356 kb
Host smart-d1448b0b-14a2-479f-8c78-281fd04b50db
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69587275718995240149155802878771639009571705442828839238728628242696415825320 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.69587275718995240149155802878771639009571705442828839238728628242696415825320
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.107270068386685271721804826101403257170869370684341999541172227917371131888584
Short name T224
Test name
Test status
Simulation time 351971476 ps
CPU time 5.14 seconds
Started Oct 29 12:56:50 PM PDT 23
Finished Oct 29 12:56:55 PM PDT 23
Peak memory 206452 kb
Host smart-d163687e-9d0d-480f-8ff9-fc4ea790445f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107270068386685271721804826101403257170869370684341999541172227917371131888584 -assert nop
ostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.107270068386685271721804826101403257170869370684341999541172227917371131888584
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.95470534213950130645015828619686344221490202874544787097422154539860074167626
Short name T205
Test name
Test status
Simulation time 26726680 ps
CPU time 0.87 seconds
Started Oct 29 12:56:41 PM PDT 23
Finished Oct 29 12:56:42 PM PDT 23
Peak memory 206484 kb
Host smart-59a4c513-4282-430a-8d4f-7cb8b918c646
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95470534213950130645015828619686344221490202874544787097422154539860074167626 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.95470534213950130645015828619686344221490202874544787097422154539860074167626
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.23484533144269359579504124777638301429720152464771020355541815128531323962997
Short name T147
Test name
Test status
Simulation time 51163789 ps
CPU time 1.3 seconds
Started Oct 29 12:57:44 PM PDT 23
Finished Oct 29 12:57:48 PM PDT 23
Peak memory 214728 kb
Host smart-5fdcff6a-1713-44e3-90b6-567dc66d9b88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348453314426935957950412477763830142972015
2464771020355541815128531323962997 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.2348453314426935957950412477
7638301429720152464771020355541815128531323962997
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.11629146991188418916090907885328814356402152200051105289615929193862057937452
Short name T116
Test name
Test status
Simulation time 23247569 ps
CPU time 0.83 seconds
Started Oct 29 12:57:31 PM PDT 23
Finished Oct 29 12:57:32 PM PDT 23
Peak memory 206400 kb
Host smart-aa65da8c-9541-408d-b79f-0de12fd77ca3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11629146991188418916090907885328814356402152200051105289615929193862057937452 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.11629146991188418916090907885328814356402152200051105289615929193862057937452
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.68361863158991241713213928763514856671449944724345018732063335923999697210645
Short name T211
Test name
Test status
Simulation time 25518366 ps
CPU time 0.83 seconds
Started Oct 29 12:57:30 PM PDT 23
Finished Oct 29 12:57:32 PM PDT 23
Peak memory 206324 kb
Host smart-298f0237-1df7-4862-8ad4-d3e3b6351b66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68361863158991241713213928763514856671449944724345018732063335923999697210645 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 2.edn_intr_test.68361863158991241713213928763514856671449944724345018732063335923999697210645
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.50331791840165007313627437143286926177319313588912892473913672664025993653907
Short name T80
Test name
Test status
Simulation time 61976116 ps
CPU time 1.33 seconds
Started Oct 29 12:57:19 PM PDT 23
Finished Oct 29 12:57:21 PM PDT 23
Peak memory 206576 kb
Host smart-6eae92b1-8a34-45a0-87e3-a056a2bd1619
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50331791840165007313627437143286926177319313588912892473913672664025993653907
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_outstanding.50331791840165007313627437143286926177319313588912892473913672664025993653907
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.64063205131912551719852150006407549783376558574303185494028977606920913478203
Short name T162
Test name
Test status
Simulation time 204078009 ps
CPU time 3.63 seconds
Started Oct 29 12:56:32 PM PDT 23
Finished Oct 29 12:56:36 PM PDT 23
Peak memory 214580 kb
Host smart-e4b696bf-b503-4d85-a88e-dc90b256021e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64063205131912551719852150006407549783376558574303185494028977606920913478203 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 2.edn_tl_errors.64063205131912551719852150006407549783376558574303185494028977606920913478203
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.8293532212332191590589711717836995030007858651006857790300341972793132089454
Short name T206
Test name
Test status
Simulation time 155537119 ps
CPU time 2.29 seconds
Started Oct 29 12:56:40 PM PDT 23
Finished Oct 29 12:56:43 PM PDT 23
Peak memory 206540 kb
Host smart-d4a9e585-6a87-442b-9f34-36255b4519a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8293532212332191590589711717836995030007858651006857790300341972793132089454 -assert no
postproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.8293532212332191590589711717836995030007858651006857790300341972793132089454
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.52828746688496104203949570995548929342116993710700731187089552322088566218048
Short name T187
Test name
Test status
Simulation time 25518366 ps
CPU time 0.93 seconds
Started Oct 29 12:56:53 PM PDT 23
Finished Oct 29 12:56:54 PM PDT 23
Peak memory 206420 kb
Host smart-676ab288-cca2-4a84-ad51-1f55224d355d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52828746688496104203949570995548929342116993710700731187089552322088566218048 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 20.edn_intr_test.52828746688496104203949570995548929342116993710700731187089552322088566218048
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.82227067113794439012653903495821891228968255061518896907988494202945802773931
Short name T201
Test name
Test status
Simulation time 25518366 ps
CPU time 0.83 seconds
Started Oct 29 12:57:27 PM PDT 23
Finished Oct 29 12:57:29 PM PDT 23
Peak memory 206412 kb
Host smart-9076b887-d208-4781-a5ef-a8165facc95d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82227067113794439012653903495821891228968255061518896907988494202945802773931 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 21.edn_intr_test.82227067113794439012653903495821891228968255061518896907988494202945802773931
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.6005396432292540255456326782888225818447395736440659247401298245638622985574
Short name T129
Test name
Test status
Simulation time 25518366 ps
CPU time 0.87 seconds
Started Oct 29 12:57:17 PM PDT 23
Finished Oct 29 12:57:18 PM PDT 23
Peak memory 206400 kb
Host smart-46447229-fb93-4d61-be3c-17f0926fc1fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6005396432292540255456326782888225818447395736440659247401298245638622985574 -assert nopostproc +UV
M_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 22.edn_intr_test.6005396432292540255456326782888225818447395736440659247401298245638622985574
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.22913841533443637843215428908541370558934641394287820212879798971606624357855
Short name T181
Test name
Test status
Simulation time 25518366 ps
CPU time 0.87 seconds
Started Oct 29 12:57:16 PM PDT 23
Finished Oct 29 12:57:17 PM PDT 23
Peak memory 206328 kb
Host smart-a5245b6b-7977-42f5-b73f-bd1f9789bd78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22913841533443637843215428908541370558934641394287820212879798971606624357855 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 23.edn_intr_test.22913841533443637843215428908541370558934641394287820212879798971606624357855
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.99841091487600652527768905384575912320030547045458999116398845743146839269916
Short name T97
Test name
Test status
Simulation time 25518366 ps
CPU time 0.87 seconds
Started Oct 29 12:57:16 PM PDT 23
Finished Oct 29 12:57:18 PM PDT 23
Peak memory 206272 kb
Host smart-9ceace01-f068-4d05-aeff-c7c009a376d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99841091487600652527768905384575912320030547045458999116398845743146839269916 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 24.edn_intr_test.99841091487600652527768905384575912320030547045458999116398845743146839269916
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.18195538102865478151647811701856823600406098363980881904227235946625136188819
Short name T122
Test name
Test status
Simulation time 25518366 ps
CPU time 0.87 seconds
Started Oct 29 12:57:28 PM PDT 23
Finished Oct 29 12:57:29 PM PDT 23
Peak memory 206380 kb
Host smart-c8727274-2868-4d6f-841a-e22db8103515
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18195538102865478151647811701856823600406098363980881904227235946625136188819 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 25.edn_intr_test.18195538102865478151647811701856823600406098363980881904227235946625136188819
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.57486988639422905926763227404331875279240064915058561901179921433714939588428
Short name T163
Test name
Test status
Simulation time 25518366 ps
CPU time 0.89 seconds
Started Oct 29 12:58:14 PM PDT 23
Finished Oct 29 12:58:16 PM PDT 23
Peak memory 204772 kb
Host smart-80650dce-a4c4-4876-90d0-355738b1e010
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57486988639422905926763227404331875279240064915058561901179921433714939588428 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 26.edn_intr_test.57486988639422905926763227404331875279240064915058561901179921433714939588428
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.38108910662876305835191945270678058523781090836059342417868295191965615897701
Short name T172
Test name
Test status
Simulation time 25518366 ps
CPU time 0.88 seconds
Started Oct 29 12:57:30 PM PDT 23
Finished Oct 29 12:57:32 PM PDT 23
Peak memory 206392 kb
Host smart-f031ebda-c497-4c50-8a7b-dcadfedf3ff7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38108910662876305835191945270678058523781090836059342417868295191965615897701 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 27.edn_intr_test.38108910662876305835191945270678058523781090836059342417868295191965615897701
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.7753092051637668614789171554625708186714843500034664480404193118154562770217
Short name T212
Test name
Test status
Simulation time 25518366 ps
CPU time 0.87 seconds
Started Oct 29 12:57:28 PM PDT 23
Finished Oct 29 12:57:30 PM PDT 23
Peak memory 206384 kb
Host smart-d8bf2be6-91da-47c2-98a3-d98e28fca702
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7753092051637668614789171554625708186714843500034664480404193118154562770217 -assert nopostproc +UV
M_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 28.edn_intr_test.7753092051637668614789171554625708186714843500034664480404193118154562770217
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.66708607519947589232794463560829187161757136699756620682861359150591661273422
Short name T213
Test name
Test status
Simulation time 25518366 ps
CPU time 0.85 seconds
Started Oct 29 12:57:14 PM PDT 23
Finished Oct 29 12:57:15 PM PDT 23
Peak memory 206380 kb
Host smart-7e18e2ad-989e-4b92-a9a3-476b2a9f67cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66708607519947589232794463560829187161757136699756620682861359150591661273422 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 29.edn_intr_test.66708607519947589232794463560829187161757136699756620682861359150591661273422
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.48040588344444488779837075132782784360070870930050372670382503992561519975862
Short name T204
Test name
Test status
Simulation time 59184494 ps
CPU time 1.35 seconds
Started Oct 29 12:56:43 PM PDT 23
Finished Oct 29 12:56:45 PM PDT 23
Peak memory 206400 kb
Host smart-f2f740b7-2857-4683-b498-c9095698c913
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48040588344444488779837075132782784360070870930050372670382503992561519975862 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.48040588344444488779837075132782784360070870930050372670382503992561519975862
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.59359131648565548270046392003007586094417866984358424696162630848904129405652
Short name T99
Test name
Test status
Simulation time 351971476 ps
CPU time 5.66 seconds
Started Oct 29 12:56:55 PM PDT 23
Finished Oct 29 12:57:01 PM PDT 23
Peak memory 206508 kb
Host smart-2f42a2c4-6983-4e83-a388-963e0346db51
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59359131648565548270046392003007586094417866984358424696162630848904129405652 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.59359131648565548270046392003007586094417866984358424696162630848904129405652
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.63425675222181898971729122371008094398441780917873312295218836043937553328160
Short name T114
Test name
Test status
Simulation time 26726680 ps
CPU time 0.85 seconds
Started Oct 29 12:57:41 PM PDT 23
Finished Oct 29 12:57:48 PM PDT 23
Peak memory 206472 kb
Host smart-7fbb3051-d862-4868-afa1-0020b322cd09
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63425675222181898971729122371008094398441780917873312295218836043937553328160 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.63425675222181898971729122371008094398441780917873312295218836043937553328160
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.15537515945179267747780633409921290474791468407862268478491931904379826750405
Short name T8
Test name
Test status
Simulation time 51163789 ps
CPU time 1.37 seconds
Started Oct 29 12:57:22 PM PDT 23
Finished Oct 29 12:57:23 PM PDT 23
Peak memory 214672 kb
Host smart-7f3d7616-b8b8-4819-86de-dac26e3f29af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553751594517926774778063340992129047479146
8407862268478491931904379826750405 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.1553751594517926774778063340
9921290474791468407862268478491931904379826750405
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.98846155220255859112785048476444968213977550407579697941725561048249976978879
Short name T195
Test name
Test status
Simulation time 23247569 ps
CPU time 0.89 seconds
Started Oct 29 12:56:47 PM PDT 23
Finished Oct 29 12:56:48 PM PDT 23
Peak memory 206412 kb
Host smart-c0a2dc03-2a3f-4b36-b6bf-8a790ca1e2f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98846155220255859112785048476444968213977550407579697941725561048249976978879 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.98846155220255859112785048476444968213977550407579697941725561048249976978879
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.73983571586967237621395915631550736562808177987981041502633076588944111027406
Short name T223
Test name
Test status
Simulation time 25518366 ps
CPU time 0.85 seconds
Started Oct 29 12:57:06 PM PDT 23
Finished Oct 29 12:57:07 PM PDT 23
Peak memory 206320 kb
Host smart-e411dfbc-ff82-44b9-b112-0cfa70be2eb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73983571586967237621395915631550736562808177987981041502633076588944111027406 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 3.edn_intr_test.73983571586967237621395915631550736562808177987981041502633076588944111027406
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.22015722251744096431388243833454677621934744771107263607453282203287854553053
Short name T125
Test name
Test status
Simulation time 61976116 ps
CPU time 1.3 seconds
Started Oct 29 12:57:25 PM PDT 23
Finished Oct 29 12:57:29 PM PDT 23
Peak memory 206424 kb
Host smart-008f9bfe-6dd1-4942-8741-157ac131e18f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22015722251744096431388243833454677621934744771107263607453282203287854553053
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_outstanding.22015722251744096431388243833454677621934744771107263607453282203287854553053
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.111961024935435873605389704091928703991805375564380132189531371415601388041531
Short name T9
Test name
Test status
Simulation time 204078009 ps
CPU time 3.66 seconds
Started Oct 29 12:56:41 PM PDT 23
Finished Oct 29 12:56:45 PM PDT 23
Peak memory 214700 kb
Host smart-82713e12-6e8e-42d1-bbb9-b5deceb4cf78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111961024935435873605389704091928703991805375564380132189531371415601388041531 -assert nopostproc +
UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.edn_tl_errors.111961024935435873605389704091928703991805375564380132189531371415601388041531
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.78095899993385424729797776953835990997582122946285212108825072543950049190568
Short name T170
Test name
Test status
Simulation time 155537119 ps
CPU time 2.16 seconds
Started Oct 29 12:57:07 PM PDT 23
Finished Oct 29 12:57:09 PM PDT 23
Peak memory 206516 kb
Host smart-53e83258-d648-49d2-943a-b3d4a28d2fcd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78095899993385424729797776953835990997582122946285212108825072543950049190568 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.78095899993385424729797776953835990997582122946285212108825072543950049190568
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.36829966280054781035180473978211902818972602795924184461221252979256784630603
Short name T107
Test name
Test status
Simulation time 25518366 ps
CPU time 0.88 seconds
Started Oct 29 12:57:24 PM PDT 23
Finished Oct 29 12:57:25 PM PDT 23
Peak memory 206292 kb
Host smart-5c3bd5b9-ce47-4b2d-a944-3c155f1f397a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36829966280054781035180473978211902818972602795924184461221252979256784630603 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 30.edn_intr_test.36829966280054781035180473978211902818972602795924184461221252979256784630603
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.91582037764401817470286678684841369810581798597201957862991380239777167455301
Short name T174
Test name
Test status
Simulation time 25518366 ps
CPU time 0.96 seconds
Started Oct 29 12:58:26 PM PDT 23
Finished Oct 29 12:58:27 PM PDT 23
Peak memory 204660 kb
Host smart-0490da89-21d1-4cb1-a294-6d4bc5c8c7ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91582037764401817470286678684841369810581798597201957862991380239777167455301 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 31.edn_intr_test.91582037764401817470286678684841369810581798597201957862991380239777167455301
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.109534847314128913245185219451080751944168291791966280978769463775881983408874
Short name T152
Test name
Test status
Simulation time 25518366 ps
CPU time 0.86 seconds
Started Oct 29 12:57:11 PM PDT 23
Finished Oct 29 12:57:12 PM PDT 23
Peak memory 206400 kb
Host smart-96d44bde-0e07-44af-a773-29c6b1a0b57e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109534847314128913245185219451080751944168291791966280978769463775881983408874 -assert nopostproc +
UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 32.edn_intr_test.109534847314128913245185219451080751944168291791966280978769463775881983408874
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.37631705335946048629837149373108958780984710271084052907639396508589050095725
Short name T112
Test name
Test status
Simulation time 25518366 ps
CPU time 0.87 seconds
Started Oct 29 12:57:38 PM PDT 23
Finished Oct 29 12:57:40 PM PDT 23
Peak memory 206408 kb
Host smart-58b6576f-1d7a-4a34-9309-f2e9bebba6b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37631705335946048629837149373108958780984710271084052907639396508589050095725 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 33.edn_intr_test.37631705335946048629837149373108958780984710271084052907639396508589050095725
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.7599433795599078100977786583468238485467383582233389376239728099478948199190
Short name T155
Test name
Test status
Simulation time 25518366 ps
CPU time 0.85 seconds
Started Oct 29 12:57:27 PM PDT 23
Finished Oct 29 12:57:29 PM PDT 23
Peak memory 206372 kb
Host smart-b66834fc-5c9c-4683-87b2-46b84c1063cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7599433795599078100977786583468238485467383582233389376239728099478948199190 -assert nopostproc +UV
M_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 34.edn_intr_test.7599433795599078100977786583468238485467383582233389376239728099478948199190
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.39265840961872409830039736439889623706738872424019255237630039414234475418927
Short name T190
Test name
Test status
Simulation time 25518366 ps
CPU time 0.89 seconds
Started Oct 29 12:57:14 PM PDT 23
Finished Oct 29 12:57:16 PM PDT 23
Peak memory 206456 kb
Host smart-bbd2911b-d1c9-4587-8183-cb0ae1f96f45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39265840961872409830039736439889623706738872424019255237630039414234475418927 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 35.edn_intr_test.39265840961872409830039736439889623706738872424019255237630039414234475418927
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.108612972526580491201564785095922976259298532721836484636713942244221914000064
Short name T207
Test name
Test status
Simulation time 25518366 ps
CPU time 0.82 seconds
Started Oct 29 12:56:59 PM PDT 23
Finished Oct 29 12:57:00 PM PDT 23
Peak memory 206428 kb
Host smart-f4cc49bd-0b7d-474f-a45c-01397d5a4d2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108612972526580491201564785095922976259298532721836484636713942244221914000064 -assert nopostproc +
UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 36.edn_intr_test.108612972526580491201564785095922976259298532721836484636713942244221914000064
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.56805108315049126926356898401068201263296843244912271753355920195146865488546
Short name T120
Test name
Test status
Simulation time 25518366 ps
CPU time 0.85 seconds
Started Oct 29 12:57:16 PM PDT 23
Finished Oct 29 12:57:17 PM PDT 23
Peak memory 206440 kb
Host smart-c75aa0fa-fddb-4872-8285-963c2557d577
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56805108315049126926356898401068201263296843244912271753355920195146865488546 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 37.edn_intr_test.56805108315049126926356898401068201263296843244912271753355920195146865488546
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.68438222424064498435405970201636511597030261413187273192748103656136218678832
Short name T50
Test name
Test status
Simulation time 25518366 ps
CPU time 0.86 seconds
Started Oct 29 12:57:24 PM PDT 23
Finished Oct 29 12:57:25 PM PDT 23
Peak memory 206328 kb
Host smart-cb17679c-363e-4dfa-a90e-3fa51c6af772
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68438222424064498435405970201636511597030261413187273192748103656136218678832 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 38.edn_intr_test.68438222424064498435405970201636511597030261413187273192748103656136218678832
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.86745165966891704534211167460330073285386206790608267442674660565859268949022
Short name T144
Test name
Test status
Simulation time 25518366 ps
CPU time 1 seconds
Started Oct 29 12:58:26 PM PDT 23
Finished Oct 29 12:58:27 PM PDT 23
Peak memory 205000 kb
Host smart-9e2d40a1-17ab-4319-b49e-c1bf8cac9609
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86745165966891704534211167460330073285386206790608267442674660565859268949022 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 39.edn_intr_test.86745165966891704534211167460330073285386206790608267442674660565859268949022
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.21023981627039145682877117553072702622707776929667720425892797599167219453065
Short name T100
Test name
Test status
Simulation time 59184494 ps
CPU time 1.34 seconds
Started Oct 29 12:57:41 PM PDT 23
Finished Oct 29 12:57:48 PM PDT 23
Peak memory 206504 kb
Host smart-f1e987d3-1c4f-484a-aa92-4619e3576b0c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21023981627039145682877117553072702622707776929667720425892797599167219453065 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.21023981627039145682877117553072702622707776929667720425892797599167219453065
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.109658506630679098420089020733293586221761700682541674716126365678429237514887
Short name T49
Test name
Test status
Simulation time 351971476 ps
CPU time 4.9 seconds
Started Oct 29 12:57:26 PM PDT 23
Finished Oct 29 12:57:33 PM PDT 23
Peak memory 206480 kb
Host smart-2e05e1ec-0bb8-4564-b8da-178f23b80645
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109658506630679098420089020733293586221761700682541674716126365678429237514887 -assert nop
ostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.109658506630679098420089020733293586221761700682541674716126365678429237514887
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.100294036563274279281824139477859754351640749970159292870139811157893456442849
Short name T98
Test name
Test status
Simulation time 26726680 ps
CPU time 0.88 seconds
Started Oct 29 12:57:36 PM PDT 23
Finished Oct 29 12:57:38 PM PDT 23
Peak memory 206464 kb
Host smart-0e4c1af8-b2a2-4555-8531-6e6e0d2fc522
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100294036563274279281824139477859754351640749970159292870139811157893456442849 -assert nop
ostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.100294036563274279281824139477859754351640749970159292870139811157893456442849
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.84460544700782906182188178598059771803468942354956035204218791971747586090136
Short name T228
Test name
Test status
Simulation time 51163789 ps
CPU time 1.32 seconds
Started Oct 29 12:57:16 PM PDT 23
Finished Oct 29 12:57:18 PM PDT 23
Peak memory 214688 kb
Host smart-8151d23a-45bd-4c9e-a483-7e10dfc9b884
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8446054470078290618218817859805977180346894
2354956035204218791971747586090136 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.8446054470078290618218817859
8059771803468942354956035204218791971747586090136
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.81228981280865046111664184284194509974019774375860426705786057232770023610008
Short name T115
Test name
Test status
Simulation time 23247569 ps
CPU time 0.86 seconds
Started Oct 29 12:56:39 PM PDT 23
Finished Oct 29 12:56:41 PM PDT 23
Peak memory 206452 kb
Host smart-b5da0b16-2578-4783-b359-a225e779cc93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81228981280865046111664184284194509974019774375860426705786057232770023610008 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.81228981280865046111664184284194509974019774375860426705786057232770023610008
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.89939463917108041938285511315025100330417014103340688254447934526237974060073
Short name T185
Test name
Test status
Simulation time 25518366 ps
CPU time 0.87 seconds
Started Oct 29 12:57:13 PM PDT 23
Finished Oct 29 12:57:14 PM PDT 23
Peak memory 206344 kb
Host smart-c6edcb21-13b0-4846-909c-2f32fc923ae0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89939463917108041938285511315025100330417014103340688254447934526237974060073 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 4.edn_intr_test.89939463917108041938285511315025100330417014103340688254447934526237974060073
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.113893394867014769776032719990117886652672502598124377728621592054997488216899
Short name T192
Test name
Test status
Simulation time 61976116 ps
CPU time 1.34 seconds
Started Oct 29 12:56:57 PM PDT 23
Finished Oct 29 12:56:59 PM PDT 23
Peak memory 206552 kb
Host smart-c1e7daaa-7387-4594-a4d4-6545011e4895
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113893394867014769776032719990117886652672502598124377728621592054997488216899
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_outstanding.113893394867014769776032719990117886652672502598124377728621592054997488216899
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.9215888449757230382067408188436294266035461871681139718203303950586823322936
Short name T118
Test name
Test status
Simulation time 204078009 ps
CPU time 3.61 seconds
Started Oct 29 12:56:44 PM PDT 23
Finished Oct 29 12:56:47 PM PDT 23
Peak memory 214716 kb
Host smart-f9a8f117-1131-49d7-9384-bba3fbea88b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9215888449757230382067408188436294266035461871681139718203303950586823322936 -assert nopostproc +UV
M_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.edn_tl_errors.9215888449757230382067408188436294266035461871681139718203303950586823322936
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.61210125259502572798410774336984063541859714142827599635492632663044904315807
Short name T121
Test name
Test status
Simulation time 155537119 ps
CPU time 2.19 seconds
Started Oct 29 12:57:36 PM PDT 23
Finished Oct 29 12:57:38 PM PDT 23
Peak memory 206540 kb
Host smart-6e812d62-99d0-4d5a-b22e-6aed26153816
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61210125259502572798410774336984063541859714142827599635492632663044904315807 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.61210125259502572798410774336984063541859714142827599635492632663044904315807
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.44215362313567225839252514554921312071094068640016625794879594444796824565860
Short name T135
Test name
Test status
Simulation time 25518366 ps
CPU time 0.89 seconds
Started Oct 29 12:56:54 PM PDT 23
Finished Oct 29 12:56:56 PM PDT 23
Peak memory 206396 kb
Host smart-db66b06f-db02-42cc-81e0-b279437df19a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44215362313567225839252514554921312071094068640016625794879594444796824565860 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 40.edn_intr_test.44215362313567225839252514554921312071094068640016625794879594444796824565860
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.41826569935623382691041506322878573675549130511669320830789699877484038680343
Short name T158
Test name
Test status
Simulation time 25518366 ps
CPU time 0.82 seconds
Started Oct 29 12:57:15 PM PDT 23
Finished Oct 29 12:57:17 PM PDT 23
Peak memory 206388 kb
Host smart-1091cd60-5373-406b-a8c6-c115061534c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41826569935623382691041506322878573675549130511669320830789699877484038680343 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 41.edn_intr_test.41826569935623382691041506322878573675549130511669320830789699877484038680343
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.42765212701764647855711137929306534157864208089483161483276732736099730168226
Short name T182
Test name
Test status
Simulation time 25518366 ps
CPU time 0.84 seconds
Started Oct 29 12:56:57 PM PDT 23
Finished Oct 29 12:56:58 PM PDT 23
Peak memory 206424 kb
Host smart-5b266cf3-2eeb-4f8a-a13d-6ffb5da2597a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42765212701764647855711137929306534157864208089483161483276732736099730168226 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 42.edn_intr_test.42765212701764647855711137929306534157864208089483161483276732736099730168226
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.65399461321724024862556970338759910181893159118465238602316191735390480802960
Short name T109
Test name
Test status
Simulation time 25518366 ps
CPU time 0.88 seconds
Started Oct 29 12:57:03 PM PDT 23
Finished Oct 29 12:57:04 PM PDT 23
Peak memory 206444 kb
Host smart-81e473bc-c447-40ad-83f3-fd7903e0234f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65399461321724024862556970338759910181893159118465238602316191735390480802960 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 43.edn_intr_test.65399461321724024862556970338759910181893159118465238602316191735390480802960
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.50806375607520673974765618859312042677203656122507844628366579689668994841235
Short name T218
Test name
Test status
Simulation time 25518366 ps
CPU time 0.8 seconds
Started Oct 29 12:57:34 PM PDT 23
Finished Oct 29 12:57:35 PM PDT 23
Peak memory 206320 kb
Host smart-fd0db676-aeb5-4fe8-8f77-34fe7f2522f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50806375607520673974765618859312042677203656122507844628366579689668994841235 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 44.edn_intr_test.50806375607520673974765618859312042677203656122507844628366579689668994841235
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.104280346447437453615123395345257373612565138904190194593430327883263979294973
Short name T131
Test name
Test status
Simulation time 25518366 ps
CPU time 0.83 seconds
Started Oct 29 12:57:34 PM PDT 23
Finished Oct 29 12:57:35 PM PDT 23
Peak memory 206612 kb
Host smart-d7cd6f63-334a-41c1-900a-cfcb6326baa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104280346447437453615123395345257373612565138904190194593430327883263979294973 -assert nopostproc +
UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 45.edn_intr_test.104280346447437453615123395345257373612565138904190194593430327883263979294973
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.33108709790608953371392918364739248444366728006788058299046527682817171440471
Short name T196
Test name
Test status
Simulation time 25518366 ps
CPU time 0.83 seconds
Started Oct 29 12:57:05 PM PDT 23
Finished Oct 29 12:57:06 PM PDT 23
Peak memory 206456 kb
Host smart-b70506f9-66ab-46db-bd08-79f2acef9cc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33108709790608953371392918364739248444366728006788058299046527682817171440471 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 46.edn_intr_test.33108709790608953371392918364739248444366728006788058299046527682817171440471
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.76880643924302479729585483562132475053668355069397680069817236713872583067102
Short name T146
Test name
Test status
Simulation time 25518366 ps
CPU time 0.82 seconds
Started Oct 29 12:56:58 PM PDT 23
Finished Oct 29 12:56:59 PM PDT 23
Peak memory 206304 kb
Host smart-1d5872e2-80c9-420e-b872-0d870ee0660c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76880643924302479729585483562132475053668355069397680069817236713872583067102 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 47.edn_intr_test.76880643924302479729585483562132475053668355069397680069817236713872583067102
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.47499180227416995648056891562843661969724849127027283268535938680326353497417
Short name T105
Test name
Test status
Simulation time 25518366 ps
CPU time 0.84 seconds
Started Oct 29 12:57:18 PM PDT 23
Finished Oct 29 12:57:19 PM PDT 23
Peak memory 206360 kb
Host smart-ae788d3d-5f70-47b2-b9b2-2aedba6342b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47499180227416995648056891562843661969724849127027283268535938680326353497417 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 48.edn_intr_test.47499180227416995648056891562843661969724849127027283268535938680326353497417
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.28183842286504760181076174168876329428471996493494027407411939259668569132565
Short name T226
Test name
Test status
Simulation time 25518366 ps
CPU time 0.87 seconds
Started Oct 29 12:57:03 PM PDT 23
Finished Oct 29 12:57:05 PM PDT 23
Peak memory 205720 kb
Host smart-389fb58e-236b-4209-bbbd-958995a72edb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28183842286504760181076174168876329428471996493494027407411939259668569132565 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 49.edn_intr_test.28183842286504760181076174168876329428471996493494027407411939259668569132565
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.22942968051465133246033931327949873681646205876686074074371322649616373350543
Short name T217
Test name
Test status
Simulation time 51163789 ps
CPU time 1.29 seconds
Started Oct 29 12:57:05 PM PDT 23
Finished Oct 29 12:57:07 PM PDT 23
Peak memory 214664 kb
Host smart-b4b2413c-dfad-41a9-b41f-7010ad787cee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294296805146513324603393132794987368164620
5876686074074371322649616373350543 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.2294296805146513324603393132
7949873681646205876686074074371322649616373350543
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.42987024560842198454355444066847167718285937590408897452773553884210490614153
Short name T108
Test name
Test status
Simulation time 23247569 ps
CPU time 0.86 seconds
Started Oct 29 12:56:39 PM PDT 23
Finished Oct 29 12:56:40 PM PDT 23
Peak memory 206364 kb
Host smart-697b6c7b-8a92-4127-90d9-56cf91430dfe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42987024560842198454355444066847167718285937590408897452773553884210490614153 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.42987024560842198454355444066847167718285937590408897452773553884210490614153
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.7183367332828972346561825816716698866092621411616359379692367394260518319239
Short name T200
Test name
Test status
Simulation time 25518366 ps
CPU time 0.86 seconds
Started Oct 29 12:57:23 PM PDT 23
Finished Oct 29 12:57:25 PM PDT 23
Peak memory 206396 kb
Host smart-62f18a0c-c98a-48a4-b198-3ce7f8cfffc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7183367332828972346561825816716698866092621411616359379692367394260518319239 -assert nopostproc +UV
M_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.edn_intr_test.7183367332828972346561825816716698866092621411616359379692367394260518319239
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.50674698491360985332326265592735712485486251561861844784282158103103476903671
Short name T126
Test name
Test status
Simulation time 61976116 ps
CPU time 1.26 seconds
Started Oct 29 12:56:55 PM PDT 23
Finished Oct 29 12:56:57 PM PDT 23
Peak memory 206548 kb
Host smart-f4c5e1f3-b86e-4be4-80b3-269075d0cc19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50674698491360985332326265592735712485486251561861844784282158103103476903671
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_outstanding.50674698491360985332326265592735712485486251561861844784282158103103476903671
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.39620029443899241339927995083008630097227622887404228866734666954477085322966
Short name T77
Test name
Test status
Simulation time 204078009 ps
CPU time 3.71 seconds
Started Oct 29 12:56:37 PM PDT 23
Finished Oct 29 12:56:41 PM PDT 23
Peak memory 214676 kb
Host smart-576e65dc-ac9d-467a-b78a-196f86a1db91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39620029443899241339927995083008630097227622887404228866734666954477085322966 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.edn_tl_errors.39620029443899241339927995083008630097227622887404228866734666954477085322966
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.34899023095589845330711196105303578170956369923819083630040836732044243790627
Short name T124
Test name
Test status
Simulation time 155537119 ps
CPU time 2.24 seconds
Started Oct 29 12:57:19 PM PDT 23
Finished Oct 29 12:57:22 PM PDT 23
Peak memory 206420 kb
Host smart-1673b4f6-f3ac-4d1c-8aa6-153e5b072b95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34899023095589845330711196105303578170956369923819083630040836732044243790627 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.34899023095589845330711196105303578170956369923819083630040836732044243790627
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.26770890089001847085012512809147393203993415900835867540478854584310539601998
Short name T5
Test name
Test status
Simulation time 51163789 ps
CPU time 1.28 seconds
Started Oct 29 12:57:12 PM PDT 23
Finished Oct 29 12:57:14 PM PDT 23
Peak memory 214804 kb
Host smart-9be3ef64-77b4-41f2-bd89-b939fcfa99e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677089008900184708501251280914739320399341
5900835867540478854584310539601998 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.2677089008900184708501251280
9147393203993415900835867540478854584310539601998
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.71253212624594277716523238899214122375959284257006155754441905733902408455980
Short name T134
Test name
Test status
Simulation time 23247569 ps
CPU time 0.89 seconds
Started Oct 29 12:56:50 PM PDT 23
Finished Oct 29 12:56:51 PM PDT 23
Peak memory 206464 kb
Host smart-b9839204-ba48-4335-b8e0-c5e3c087e04c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71253212624594277716523238899214122375959284257006155754441905733902408455980 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.71253212624594277716523238899214122375959284257006155754441905733902408455980
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.86187208941265309182374419592725967264474795053755103689891575813223735141628
Short name T231
Test name
Test status
Simulation time 25518366 ps
CPU time 0.83 seconds
Started Oct 29 12:56:45 PM PDT 23
Finished Oct 29 12:56:46 PM PDT 23
Peak memory 206328 kb
Host smart-c2b80d9b-4413-4a29-87bc-f7ca7245549b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86187208941265309182374419592725967264474795053755103689891575813223735141628 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 6.edn_intr_test.86187208941265309182374419592725967264474795053755103689891575813223735141628
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.31941112090607271397326746727110519110894558852456290113309689856353580158675
Short name T145
Test name
Test status
Simulation time 61976116 ps
CPU time 1.38 seconds
Started Oct 29 12:57:05 PM PDT 23
Finished Oct 29 12:57:07 PM PDT 23
Peak memory 206596 kb
Host smart-f378874e-cf51-43ed-a7d7-50faf5da9e07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31941112090607271397326746727110519110894558852456290113309689856353580158675
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_outstanding.31941112090607271397326746727110519110894558852456290113309689856353580158675
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.69015035725871253473595114954500477240618775861802491633974310476985241813980
Short name T177
Test name
Test status
Simulation time 204078009 ps
CPU time 3.76 seconds
Started Oct 29 12:57:18 PM PDT 23
Finished Oct 29 12:57:23 PM PDT 23
Peak memory 214672 kb
Host smart-ba0841df-f093-454f-9dd6-20ff03ce44df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69015035725871253473595114954500477240618775861802491633974310476985241813980 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 6.edn_tl_errors.69015035725871253473595114954500477240618775861802491633974310476985241813980
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.40033022410172507347555815397199722814501260647830067108667677569757948745853
Short name T169
Test name
Test status
Simulation time 155537119 ps
CPU time 2.15 seconds
Started Oct 29 12:57:19 PM PDT 23
Finished Oct 29 12:57:21 PM PDT 23
Peak memory 206576 kb
Host smart-bcee5efb-a51f-45d8-be0f-809557040a63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40033022410172507347555815397199722814501260647830067108667677569757948745853 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.40033022410172507347555815397199722814501260647830067108667677569757948745853
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.93103170441864004344196695270975607663354607403171000203858687682626365483460
Short name T166
Test name
Test status
Simulation time 51163789 ps
CPU time 1.29 seconds
Started Oct 29 12:57:32 PM PDT 23
Finished Oct 29 12:57:33 PM PDT 23
Peak memory 214756 kb
Host smart-88db793a-244b-443d-bcb1-15e3c328bdf0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9310317044186400434419669527097560766335460
7403171000203858687682626365483460 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.9310317044186400434419669527
0975607663354607403171000203858687682626365483460
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.28448304955042414939303837454854160876350345673246806479715195679828422159527
Short name T222
Test name
Test status
Simulation time 23247569 ps
CPU time 0.83 seconds
Started Oct 29 12:57:23 PM PDT 23
Finished Oct 29 12:57:24 PM PDT 23
Peak memory 206524 kb
Host smart-7416d299-ed63-474d-b035-893fa0c711b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28448304955042414939303837454854160876350345673246806479715195679828422159527 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.28448304955042414939303837454854160876350345673246806479715195679828422159527
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.87206290837626692886097900042141228179129651022984814289262008429516845074294
Short name T171
Test name
Test status
Simulation time 25518366 ps
CPU time 0.83 seconds
Started Oct 29 12:56:49 PM PDT 23
Finished Oct 29 12:56:50 PM PDT 23
Peak memory 206400 kb
Host smart-1e056a32-a7c1-4ecc-a27c-168587ad7189
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87206290837626692886097900042141228179129651022984814289262008429516845074294 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 7.edn_intr_test.87206290837626692886097900042141228179129651022984814289262008429516845074294
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.112877411897784862653081416624667067311644637388739013756877337033322459789880
Short name T78
Test name
Test status
Simulation time 61976116 ps
CPU time 1.34 seconds
Started Oct 29 12:56:52 PM PDT 23
Finished Oct 29 12:56:54 PM PDT 23
Peak memory 206480 kb
Host smart-8d29c86b-7a57-4275-a8cf-e97d305f55df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112877411897784862653081416624667067311644637388739013756877337033322459789880
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_outstanding.112877411897784862653081416624667067311644637388739013756877337033322459789880
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.68532205519379902943206900351230241241076253655194488567607901280940157349560
Short name T215
Test name
Test status
Simulation time 204078009 ps
CPU time 3.88 seconds
Started Oct 29 12:57:16 PM PDT 23
Finished Oct 29 12:57:20 PM PDT 23
Peak memory 214700 kb
Host smart-17772a19-dde2-4453-83ff-d76da0d8bccd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68532205519379902943206900351230241241076253655194488567607901280940157349560 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 7.edn_tl_errors.68532205519379902943206900351230241241076253655194488567607901280940157349560
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.28892750985894480518212430120648281413639517239975917527422829630122034427348
Short name T127
Test name
Test status
Simulation time 155537119 ps
CPU time 2.2 seconds
Started Oct 29 12:57:36 PM PDT 23
Finished Oct 29 12:57:39 PM PDT 23
Peak memory 206732 kb
Host smart-0fa5ab5f-0052-48a7-aa6d-b6cd6ddebd11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28892750985894480518212430120648281413639517239975917527422829630122034427348 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.28892750985894480518212430120648281413639517239975917527422829630122034427348
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.93860469728815438049992991314521510598932530751574212665730056427314654262429
Short name T111
Test name
Test status
Simulation time 51163789 ps
CPU time 1.32 seconds
Started Oct 29 12:56:58 PM PDT 23
Finished Oct 29 12:56:59 PM PDT 23
Peak memory 214644 kb
Host smart-b200f219-3c71-4188-9519-2791c434ce7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9386046972881543804999299131452151059893253
0751574212665730056427314654262429 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.9386046972881543804999299131
4521510598932530751574212665730056427314654262429
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.58422076088417823723626093759593513696129463228511552001502410349247214743819
Short name T229
Test name
Test status
Simulation time 23247569 ps
CPU time 0.84 seconds
Started Oct 29 12:56:44 PM PDT 23
Finished Oct 29 12:56:45 PM PDT 23
Peak memory 206520 kb
Host smart-0a132952-6adc-4d0c-a465-3a80c60fe74c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58422076088417823723626093759593513696129463228511552001502410349247214743819 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.58422076088417823723626093759593513696129463228511552001502410349247214743819
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.35097585312149991731551317795121232886033394847098270616157477724372247285495
Short name T216
Test name
Test status
Simulation time 25518366 ps
CPU time 0.84 seconds
Started Oct 29 12:56:48 PM PDT 23
Finished Oct 29 12:56:49 PM PDT 23
Peak memory 206392 kb
Host smart-e6aa75cf-c419-4c72-997d-97ed8f77ce56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35097585312149991731551317795121232886033394847098270616157477724372247285495 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 8.edn_intr_test.35097585312149991731551317795121232886033394847098270616157477724372247285495
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.107221175817565081479160323196907535413693263216293521374959926465661221231923
Short name T138
Test name
Test status
Simulation time 61976116 ps
CPU time 1.26 seconds
Started Oct 29 12:57:36 PM PDT 23
Finished Oct 29 12:57:37 PM PDT 23
Peak memory 206528 kb
Host smart-69a8a19c-2626-4ea5-b4f3-8d959379a2a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107221175817565081479160323196907535413693263216293521374959926465661221231923
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_outstanding.107221175817565081479160323196907535413693263216293521374959926465661221231923
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.83667272152565141101953658817035544683768307649318078145811489267812231714667
Short name T132
Test name
Test status
Simulation time 204078009 ps
CPU time 3.69 seconds
Started Oct 29 12:57:19 PM PDT 23
Finished Oct 29 12:57:23 PM PDT 23
Peak memory 214652 kb
Host smart-75290f71-68b8-4ab3-9278-0929586ec821
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83667272152565141101953658817035544683768307649318078145811489267812231714667 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 8.edn_tl_errors.83667272152565141101953658817035544683768307649318078145811489267812231714667
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.12752149670832869480589438284257907152806627365268451324635737502121472373543
Short name T7
Test name
Test status
Simulation time 155537119 ps
CPU time 2.24 seconds
Started Oct 29 12:56:46 PM PDT 23
Finished Oct 29 12:56:48 PM PDT 23
Peak memory 206532 kb
Host smart-fb7e3742-b2cf-4a1b-a348-f3cf32bab77d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12752149670832869480589438284257907152806627365268451324635737502121472373543 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.12752149670832869480589438284257907152806627365268451324635737502121472373543
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.107344946672456627038009811536435291741912095175707446129812946250145272313108
Short name T230
Test name
Test status
Simulation time 51163789 ps
CPU time 1.26 seconds
Started Oct 29 12:57:09 PM PDT 23
Finished Oct 29 12:57:11 PM PDT 23
Peak memory 214748 kb
Host smart-d9a9af3c-ea8f-409b-a27a-fff30f46974a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073449466724566270380098115364352917419120
95175707446129812946250145272313108 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.107344946672456627038009811
536435291741912095175707446129812946250145272313108
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.40631449744148687615269072924644460009857218336245278974861687950567869259891
Short name T123
Test name
Test status
Simulation time 23247569 ps
CPU time 0.87 seconds
Started Oct 29 12:56:44 PM PDT 23
Finished Oct 29 12:56:45 PM PDT 23
Peak memory 206424 kb
Host smart-626169d4-19eb-4b01-9dcc-29986c52e93b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40631449744148687615269072924644460009857218336245278974861687950567869259891 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.40631449744148687615269072924644460009857218336245278974861687950567869259891
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.112305965022676162571416449431168970336450411092827842053840019074246034164182
Short name T150
Test name
Test status
Simulation time 25518366 ps
CPU time 0.87 seconds
Started Oct 29 12:56:49 PM PDT 23
Finished Oct 29 12:56:51 PM PDT 23
Peak memory 206428 kb
Host smart-63113fc9-29d9-4597-8dcb-306da8240427
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112305965022676162571416449431168970336450411092827842053840019074246034164182 -assert nopostproc +
UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.edn_intr_test.112305965022676162571416449431168970336450411092827842053840019074246034164182
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.28593379860408469937069149986202960479799354753801202720311787194221031774693
Short name T87
Test name
Test status
Simulation time 61976116 ps
CPU time 1.32 seconds
Started Oct 29 12:57:23 PM PDT 23
Finished Oct 29 12:57:25 PM PDT 23
Peak memory 206556 kb
Host smart-0d2e9556-f74c-4c6b-a3cb-92f13a093c81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28593379860408469937069149986202960479799354753801202720311787194221031774693
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_outstanding.28593379860408469937069149986202960479799354753801202720311787194221031774693
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.108241396410182331532781432752934478022369810930549227005953891528030507113054
Short name T221
Test name
Test status
Simulation time 204078009 ps
CPU time 3.6 seconds
Started Oct 29 12:57:09 PM PDT 23
Finished Oct 29 12:57:13 PM PDT 23
Peak memory 214720 kb
Host smart-53276416-5762-4477-8e87-f45492a229e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108241396410182331532781432752934478022369810930549227005953891528030507113054 -assert nopostproc +
UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.edn_tl_errors.108241396410182331532781432752934478022369810930549227005953891528030507113054
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.107496054069917525030670355742919997659773309936878603451631060761131069777079
Short name T189
Test name
Test status
Simulation time 155537119 ps
CPU time 2.24 seconds
Started Oct 29 12:56:51 PM PDT 23
Finished Oct 29 12:56:54 PM PDT 23
Peak memory 206484 kb
Host smart-99781732-f6d9-472a-b4cf-27023feee32d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107496054069917525030670355742919997659773309936878603451631060761131069777079 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.107496054069917525030670355742919997659773309936878603451631060761131069777079
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.54520020545741905531727561527153004835756537402378227991652270521198792664375
Short name T968
Test name
Test status
Simulation time 18259183 ps
CPU time 0.99 seconds
Started Oct 29 02:05:45 PM PDT 23
Finished Oct 29 02:05:47 PM PDT 23
Peak memory 205492 kb
Host smart-3522b5cd-6a70-49d6-89b9-bd15627d0b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54520020545741905531727561527153004835756537402378227991652270521198792664375 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.edn_alert.54520020545741905531727561527153004835756537402378227991652270521198792664375
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.71235063368310710838021080008411440482564116940290639401160046221319837921237
Short name T847
Test name
Test status
Simulation time 28184990 ps
CPU time 0.85 seconds
Started Oct 29 02:05:50 PM PDT 23
Finished Oct 29 02:05:51 PM PDT 23
Peak memory 205392 kb
Host smart-c60041f4-6b80-454a-9ec0-e965d35af990
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71235063368310710838021080008411440482564116940290639401160046221319837921237 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.edn_alert_test.71235063368310710838021080008411440482564116940290639401160046221319837921237
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.7705246508453500209947941199345118302885516974530235007452829268989663912349
Short name T374
Test name
Test status
Simulation time 12219183 ps
CPU time 0.87 seconds
Started Oct 29 02:05:51 PM PDT 23
Finished Oct 29 02:05:52 PM PDT 23
Peak memory 214876 kb
Host smart-11ab902e-76e9-4251-a876-d9ac9c0b1812
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7705246508453500209947941199345118302885516974530235007452829268989663912349 -assert nopostproc
+UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.edn_disable.7705246508453500209947941199345118302885516974530235007452829268989663912349
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.47957613740319847757878047478699073311167341766375290468201005346180055151962
Short name T475
Test name
Test status
Simulation time 17319183 ps
CPU time 0.92 seconds
Started Oct 29 02:05:54 PM PDT 23
Finished Oct 29 02:05:56 PM PDT 23
Peak memory 214876 kb
Host smart-26f57d52-ad7c-4acc-80bf-4c4a120a43f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47957613740319847757878047478699073311167341766375290468201005346180055151962 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable_auto_req_mode.47957613740319847757878047478699073311167341766375290468201
005346180055151962
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.100915149479821997530758312964221491107388246641419575177454987717897681320302
Short name T321
Test name
Test status
Simulation time 24963823 ps
CPU time 1.11 seconds
Started Oct 29 02:05:44 PM PDT 23
Finished Oct 29 02:05:46 PM PDT 23
Peak memory 230364 kb
Host smart-26fd5496-28e1-4ec9-8c3d-b22b53e46248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100915149479821997530758312964221491107388246641419575177454987717897681320302 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.edn_err.100915149479821997530758312964221491107388246641419575177454987717897681320302
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.83717827309701473976758253209002092754122722454846588517678752986748173119151
Short name T776
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:05:56 PM PDT 23
Finished Oct 29 02:05:57 PM PDT 23
Peak memory 205864 kb
Host smart-86704566-9bd9-4949-9277-f91292e8461e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83717827309701473976758253209002092754122722454846588517678752986748173119151 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.edn_genbits.83717827309701473976758253209002092754122722454846588517678752986748173119151
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_regwen.109696415154103837017241574875715646846576266464368076818454238081792366618265
Short name T773
Test name
Test status
Simulation time 11759183 ps
CPU time 0.9 seconds
Started Oct 29 02:05:56 PM PDT 23
Finished Oct 29 02:05:57 PM PDT 23
Peak memory 205328 kb
Host smart-182acd7e-a6d8-4495-b12f-7cb083fe8e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109696415154103837017241574875715646846576266464368076818454238081792366618265 -assert nopostproc +UVM_TESTNAME=edn_smok
e_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.edn_regwen.109696415154103837017241574875715646846576266464368076818454238081792366618265
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_smoke.36838917787144073672063337023914987469550952976824692097631448232457536101041
Short name T781
Test name
Test status
Simulation time 13059183 ps
CPU time 0.87 seconds
Started Oct 29 02:05:54 PM PDT 23
Finished Oct 29 02:05:55 PM PDT 23
Peak memory 205348 kb
Host smart-108d3ce7-3b2f-470b-b127-01d771d221c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36838917787144073672063337023914987469550952976824692097631448232457536101041 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.edn_smoke.36838917787144073672063337023914987469550952976824692097631448232457536101041
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.82992342116293607167215433016603866955833241420767420391613001366396786715528
Short name T378
Test name
Test status
Simulation time 154489183 ps
CPU time 4.07 seconds
Started Oct 29 02:05:51 PM PDT 23
Finished Oct 29 02:05:56 PM PDT 23
Peak memory 206360 kb
Host smart-321fa745-c130-4479-87be-70510b8c8ccc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82992342116293607167215433016603866955833241420767420391613001366396786715528 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.82992342116293607167215433016603866955833241420767420391613001366396786715528
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.84575224830372705364390894147501685057194978518527909157932284116337917170965
Short name T854
Test name
Test status
Simulation time 41708099183 ps
CPU time 1093.03 seconds
Started Oct 29 02:05:47 PM PDT 23
Finished Oct 29 02:24:00 PM PDT 23
Peak memory 215896 kb
Host smart-f7ec9078-4a2e-4c3d-aaa9-84db3d712cf7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845752248303727053643908941
47501685057194978518527909157932284116337917170965 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.845752248303
72705364390894147501685057194978518527909157932284116337917170965
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.81709540525674824543451487115297868899761743798011278144368735418922560941543
Short name T797
Test name
Test status
Simulation time 18259183 ps
CPU time 1.01 seconds
Started Oct 29 02:06:31 PM PDT 23
Finished Oct 29 02:06:32 PM PDT 23
Peak memory 205464 kb
Host smart-4b0fbffb-5a74-4f47-841a-de6930c52c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81709540525674824543451487115297868899761743798011278144368735418922560941543 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.edn_alert.81709540525674824543451487115297868899761743798011278144368735418922560941543
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.77872382559192888360375966248267105746904614849353629997566875749217168690791
Short name T742
Test name
Test status
Simulation time 28184990 ps
CPU time 0.88 seconds
Started Oct 29 02:06:32 PM PDT 23
Finished Oct 29 02:06:33 PM PDT 23
Peak memory 205640 kb
Host smart-8e29a5ee-6f21-48f5-a08d-d71ad53f78a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77872382559192888360375966248267105746904614849353629997566875749217168690791 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.edn_alert_test.77872382559192888360375966248267105746904614849353629997566875749217168690791
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.13689179459446853631543932145776368142198523053758591962829696156604283733450
Short name T364
Test name
Test status
Simulation time 12219183 ps
CPU time 0.85 seconds
Started Oct 29 02:06:33 PM PDT 23
Finished Oct 29 02:06:34 PM PDT 23
Peak memory 214864 kb
Host smart-123e3137-a945-4d32-95d4-422d3b4750c6
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13689179459446853631543932145776368142198523053758591962829696156604283733450 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.edn_disable.13689179459446853631543932145776368142198523053758591962829696156604283733450
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.100041095228260686696488223719172704823140814091938237372030694258206325421614
Short name T278
Test name
Test status
Simulation time 17319183 ps
CPU time 0.96 seconds
Started Oct 29 02:06:33 PM PDT 23
Finished Oct 29 02:06:34 PM PDT 23
Peak memory 214884 kb
Host smart-5c7bbb8b-c98a-4678-b829-3125436c02fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100041095228260686696488223719172704823140814091938237372030694258206325421614 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable_auto_req_mode.1000410952282606866964882237191727048231408140919382373720
30694258206325421614
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.61955006619931314367701380789757039473015211838261856657574539042430661174831
Short name T357
Test name
Test status
Simulation time 24963823 ps
CPU time 1.12 seconds
Started Oct 29 02:06:32 PM PDT 23
Finished Oct 29 02:06:33 PM PDT 23
Peak memory 230356 kb
Host smart-c6ef8b54-a2e2-4aec-b7f2-964a1d899a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61955006619931314367701380789757039473015211838261856657574539042430661174831 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
edn_err.61955006619931314367701380789757039473015211838261856657574539042430661174831
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.61103578662301470434074739564660340454322463295824409150249862579581328518062
Short name T519
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Oct 29 02:05:46 PM PDT 23
Finished Oct 29 02:05:47 PM PDT 23
Peak memory 205844 kb
Host smart-7356da6c-1f02-47f0-9e34-db6731fdde4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61103578662301470434074739564660340454322463295824409150249862579581328518062 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.edn_genbits.61103578662301470434074739564660340454322463295824409150249862579581328518062
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.15188180235120464217175349711338908448667554919039300523005520129290114253029
Short name T490
Test name
Test status
Simulation time 18439183 ps
CPU time 1.1 seconds
Started Oct 29 02:06:31 PM PDT 23
Finished Oct 29 02:06:33 PM PDT 23
Peak memory 222232 kb
Host smart-150962bd-e731-4de6-91d0-3c3839b1f877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15188180235120464217175349711338908448667554919039300523005520129290114253029 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.edn_intr.15188180235120464217175349711338908448667554919039300523005520129290114253029
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.10677997933408081777646502397358174561601466769186372166337173692242510693077
Short name T481
Test name
Test status
Simulation time 11759183 ps
CPU time 0.89 seconds
Started Oct 29 02:05:54 PM PDT 23
Finished Oct 29 02:05:55 PM PDT 23
Peak memory 205308 kb
Host smart-7619901e-f0e4-44cc-a986-de576cfcdb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10677997933408081777646502397358174561601466769186372166337173692242510693077 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.edn_regwen.10677997933408081777646502397358174561601466769186372166337173692242510693077
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.74289543155220163800752959212431941598661744322613294418954448995302097510848
Short name T52
Test name
Test status
Simulation time 717215632 ps
CPU time 6.17 seconds
Started Oct 29 02:06:58 PM PDT 23
Finished Oct 29 02:07:05 PM PDT 23
Peak memory 234084 kb
Host smart-af8b5935-476f-461e-b5ef-1fa3e978db1a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74289543155220163800752959212431941598661744322613294418954448995302097510848 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.edn_sec_cm.74289543155220163800752959212431941598661744322613294418954448995302097510848
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.102821317955058172855996129721589790189188780733609458400679920077391923806764
Short name T511
Test name
Test status
Simulation time 13059183 ps
CPU time 0.9 seconds
Started Oct 29 02:05:55 PM PDT 23
Finished Oct 29 02:05:56 PM PDT 23
Peak memory 205376 kb
Host smart-29f793f6-e89f-408a-a730-35e3602df718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102821317955058172855996129721589790189188780733609458400679920077391923806764 -assert nopostproc +UVM_TESTNAME=edn_smok
e_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.edn_smoke.102821317955058172855996129721589790189188780733609458400679920077391923806764
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.70334899429384270899652449773650363759708116974479500667528338271015098780554
Short name T400
Test name
Test status
Simulation time 41708099183 ps
CPU time 1081.32 seconds
Started Oct 29 02:06:18 PM PDT 23
Finished Oct 29 02:24:20 PM PDT 23
Peak memory 215788 kb
Host smart-d33fa92f-cce6-4b26-b522-f7e08cd0165d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703348994293842708996524497
73650363759708116974479500667528338271015098780554 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.703348994293
84270899652449773650363759708116974479500667528338271015098780554
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert_test.24846541220740854995072913817415623882795957026301127041916633695217659865871
Short name T642
Test name
Test status
Simulation time 28184990 ps
CPU time 0.91 seconds
Started Oct 29 02:06:39 PM PDT 23
Finished Oct 29 02:06:40 PM PDT 23
Peak memory 205516 kb
Host smart-e984266c-9eb1-4deb-9a20-47590c913d5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24846541220740854995072913817415623882795957026301127041916633695217659865871 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.edn_alert_test.24846541220740854995072913817415623882795957026301127041916633695217659865871
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.70154379784427298102206151956695097111216938322957451288482920680054418012065
Short name T502
Test name
Test status
Simulation time 12219183 ps
CPU time 0.86 seconds
Started Oct 29 02:07:02 PM PDT 23
Finished Oct 29 02:07:05 PM PDT 23
Peak memory 214764 kb
Host smart-b4d89da3-9e06-4bd1-b474-a82ea2b0db98
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70154379784427298102206151956695097111216938322957451288482920680054418012065 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.edn_disable.70154379784427298102206151956695097111216938322957451288482920680054418012065
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.29642170882873524916168860481855475357760204552250846464925450070015655681366
Short name T318
Test name
Test status
Simulation time 17319183 ps
CPU time 1 seconds
Started Oct 29 02:07:00 PM PDT 23
Finished Oct 29 02:07:01 PM PDT 23
Peak memory 214888 kb
Host smart-fcf9670f-ff0d-474e-bbba-22910d86bf82
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29642170882873524916168860481855475357760204552250846464925450070015655681366 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable_auto_req_mode.2964217088287352491616886048185547535776020455225084646492
5450070015655681366
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.82398655333939814289208779347893906020908996404601825619235781178148901397100
Short name T801
Test name
Test status
Simulation time 24963823 ps
CPU time 1.11 seconds
Started Oct 29 02:07:02 PM PDT 23
Finished Oct 29 02:07:06 PM PDT 23
Peak memory 230420 kb
Host smart-18235b29-4446-458e-bedf-56205d0c9fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82398655333939814289208779347893906020908996404601825619235781178148901397100 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.edn_err.82398655333939814289208779347893906020908996404601825619235781178148901397100
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.20162074174205892365364169876419001839496029890534454466060644976739409229723
Short name T485
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Oct 29 02:07:26 PM PDT 23
Finished Oct 29 02:07:28 PM PDT 23
Peak memory 205840 kb
Host smart-278ee215-d4a7-40bf-a546-97d0942fb277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20162074174205892365364169876419001839496029890534454466060644976739409229723 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.edn_genbits.20162074174205892365364169876419001839496029890534454466060644976739409229723
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.28730586111281475940167554116627811162188354951412092069296059404060773844423
Short name T724
Test name
Test status
Simulation time 18439183 ps
CPU time 1.11 seconds
Started Oct 29 02:06:39 PM PDT 23
Finished Oct 29 02:06:40 PM PDT 23
Peak memory 222264 kb
Host smart-843e248a-9811-4556-919e-a8e207d98c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28730586111281475940167554116627811162188354951412092069296059404060773844423 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.edn_intr.28730586111281475940167554116627811162188354951412092069296059404060773844423
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.92814650464803598527993778071468521350291875612319402323830380304758360934782
Short name T95
Test name
Test status
Simulation time 13059183 ps
CPU time 0.9 seconds
Started Oct 29 02:07:00 PM PDT 23
Finished Oct 29 02:07:05 PM PDT 23
Peak memory 205388 kb
Host smart-f37b5e22-f3fd-4064-a01a-d892ec81e7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92814650464803598527993778071468521350291875612319402323830380304758360934782 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.edn_smoke.92814650464803598527993778071468521350291875612319402323830380304758360934782
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.81614368485987921926201814958763348353611771774661443600733539284923020448573
Short name T449
Test name
Test status
Simulation time 154489183 ps
CPU time 3.84 seconds
Started Oct 29 02:06:40 PM PDT 23
Finished Oct 29 02:06:44 PM PDT 23
Peak memory 206368 kb
Host smart-b609196e-cfc4-490c-97fa-f3268ac0dc00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81614368485987921926201814958763348353611771774661443600733539284923020448573 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.81614368485987921926201814958763348353611771774661443600733539284923020448573
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.26953726276962118506554327442396299115646939267464173595022744899170975132511
Short name T866
Test name
Test status
Simulation time 41708099183 ps
CPU time 1014.8 seconds
Started Oct 29 02:07:22 PM PDT 23
Finished Oct 29 02:24:19 PM PDT 23
Peak memory 215660 kb
Host smart-ebf4d7fc-8a03-45c6-88cd-83e074b43f2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269537262769621185065543274
42396299115646939267464173595022744899170975132511 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.26953726276
962118506554327442396299115646939267464173595022744899170975132511
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.31998938484334843679742673796754374852623367119670782647893840612176436071170
Short name T910
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Oct 29 02:08:59 PM PDT 23
Finished Oct 29 02:09:04 PM PDT 23
Peak memory 205828 kb
Host smart-b01f4119-0a14-4ca3-b2b7-77a56471b524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31998938484334843679742673796754374852623367119670782647893840612176436071170 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 100.edn_genbits.31998938484334843679742673796754374852623367119670782647893840612176436071170
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.20061309683412184001103325234491941167905019333016721366416836341703849313888
Short name T937
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:08:37 PM PDT 23
Finished Oct 29 02:08:39 PM PDT 23
Peak memory 205832 kb
Host smart-ddd89e2a-1e21-44f2-9098-d8af8d702255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20061309683412184001103325234491941167905019333016721366416836341703849313888 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 101.edn_genbits.20061309683412184001103325234491941167905019333016721366416836341703849313888
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.30558656772606851474390297443427403610179225705559501913696096471947983668772
Short name T355
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:08:50 PM PDT 23
Finished Oct 29 02:08:52 PM PDT 23
Peak memory 205992 kb
Host smart-5f3ac934-1e40-487b-85f6-247852aed515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30558656772606851474390297443427403610179225705559501913696096471947983668772 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 102.edn_genbits.30558656772606851474390297443427403610179225705559501913696096471947983668772
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.73078439637508423767995238381447524812098357473347017158503724235667755906972
Short name T690
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Oct 29 02:08:43 PM PDT 23
Finished Oct 29 02:08:45 PM PDT 23
Peak memory 205840 kb
Host smart-685e196f-1651-4999-a049-aaef15a77401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73078439637508423767995238381447524812098357473347017158503724235667755906972 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 103.edn_genbits.73078439637508423767995238381447524812098357473347017158503724235667755906972
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.55097688578666173732879850909749932146303888904811380954692889516501414676581
Short name T253
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Oct 29 02:09:50 PM PDT 23
Finished Oct 29 02:09:51 PM PDT 23
Peak memory 205816 kb
Host smart-278ffe89-ab68-4a5b-8d14-21dc1cb3570a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55097688578666173732879850909749932146303888904811380954692889516501414676581 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 104.edn_genbits.55097688578666173732879850909749932146303888904811380954692889516501414676581
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.114329697530671748792159842952814586094024058258632703209519380701568977819008
Short name T740
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:08:50 PM PDT 23
Finished Oct 29 02:08:52 PM PDT 23
Peak memory 205816 kb
Host smart-23785219-91ad-432b-9aef-f444fab756d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114329697530671748792159842952814586094024058258632703209519380701568977819008 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 105.edn_genbits.114329697530671748792159842952814586094024058258632703209519380701568977819008
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.37818538676921192967328175454369526711039486115118919146294362712936632369349
Short name T903
Test name
Test status
Simulation time 17999183 ps
CPU time 1.16 seconds
Started Oct 29 02:09:46 PM PDT 23
Finished Oct 29 02:09:47 PM PDT 23
Peak memory 205868 kb
Host smart-abaf64e5-39a5-474c-86af-61626458bf8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37818538676921192967328175454369526711039486115118919146294362712936632369349 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 106.edn_genbits.37818538676921192967328175454369526711039486115118919146294362712936632369349
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.89825258691655302554323614001317922640600825833402283890344083489315608650553
Short name T390
Test name
Test status
Simulation time 17999183 ps
CPU time 1.15 seconds
Started Oct 29 02:09:25 PM PDT 23
Finished Oct 29 02:09:27 PM PDT 23
Peak memory 205848 kb
Host smart-a44ca4bb-06ab-45fc-9458-669107abafc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89825258691655302554323614001317922640600825833402283890344083489315608650553 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 107.edn_genbits.89825258691655302554323614001317922640600825833402283890344083489315608650553
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.63718323157668328471690574201078906775710316498808531838395784022102911938161
Short name T257
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Oct 29 02:08:49 PM PDT 23
Finished Oct 29 02:08:51 PM PDT 23
Peak memory 205820 kb
Host smart-bf5c2108-eb9a-4f4b-8fe5-b507ac9d0239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63718323157668328471690574201078906775710316498808531838395784022102911938161 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 108.edn_genbits.63718323157668328471690574201078906775710316498808531838395784022102911938161
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.43447487129507958210633693698701206462366279948136724258174024741360438710806
Short name T917
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:08:57 PM PDT 23
Finished Oct 29 02:09:02 PM PDT 23
Peak memory 205760 kb
Host smart-98b059b4-dce1-4570-8f17-4a1fbaa29852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43447487129507958210633693698701206462366279948136724258174024741360438710806 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 109.edn_genbits.43447487129507958210633693698701206462366279948136724258174024741360438710806
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.85372727975835816609922486854106667895946156751889530249468623284236942391086
Short name T43
Test name
Test status
Simulation time 18259183 ps
CPU time 1.01 seconds
Started Oct 29 02:06:55 PM PDT 23
Finished Oct 29 02:06:57 PM PDT 23
Peak memory 205580 kb
Host smart-0009a625-1847-4b21-a038-d0add848591b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85372727975835816609922486854106667895946156751889530249468623284236942391086 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.edn_alert.85372727975835816609922486854106667895946156751889530249468623284236942391086
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.30476636369573949125560624887969836778624500404681201510314569148168146819846
Short name T345
Test name
Test status
Simulation time 28184990 ps
CPU time 0.86 seconds
Started Oct 29 02:06:59 PM PDT 23
Finished Oct 29 02:07:01 PM PDT 23
Peak memory 205468 kb
Host smart-556eb397-7b3c-4680-9b2b-a7f4e1f32118
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30476636369573949125560624887969836778624500404681201510314569148168146819846 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.edn_alert_test.30476636369573949125560624887969836778624500404681201510314569148168146819846
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.19619164186558962213149157131249076656707144947897830368511098322667696007769
Short name T673
Test name
Test status
Simulation time 12219183 ps
CPU time 0.86 seconds
Started Oct 29 02:06:57 PM PDT 23
Finished Oct 29 02:06:59 PM PDT 23
Peak memory 214884 kb
Host smart-cff7a7d9-fd4b-4e22-b803-eb47ff6f0374
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19619164186558962213149157131249076656707144947897830368511098322667696007769 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.edn_disable.19619164186558962213149157131249076656707144947897830368511098322667696007769
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.112000015720942145809829159257577837633369709121944415980426604392387100549947
Short name T965
Test name
Test status
Simulation time 17319183 ps
CPU time 0.93 seconds
Started Oct 29 02:07:20 PM PDT 23
Finished Oct 29 02:07:22 PM PDT 23
Peak memory 214896 kb
Host smart-17622ba5-0e99-414c-a73a-a451242f24a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112000015720942145809829159257577837633369709121944415980426604392387100549947 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable_auto_req_mode.112000015720942145809829159257577837633369709121944415980
426604392387100549947
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.57442872470851728061831795231618839664225295650782695209157256282418654530433
Short name T974
Test name
Test status
Simulation time 24963823 ps
CPU time 1.16 seconds
Started Oct 29 02:06:56 PM PDT 23
Finished Oct 29 02:06:58 PM PDT 23
Peak memory 230380 kb
Host smart-a1953b51-d5de-4b40-8e7d-6ae733bec6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57442872470851728061831795231618839664225295650782695209157256282418654530433 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.edn_err.57442872470851728061831795231618839664225295650782695209157256282418654530433
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.22804018697129688215023671047977752960057584491816674390268562019460290693825
Short name T729
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:07:01 PM PDT 23
Finished Oct 29 02:07:06 PM PDT 23
Peak memory 205752 kb
Host smart-ee9d4cb1-202c-4150-ad07-01126b8f238c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22804018697129688215023671047977752960057584491816674390268562019460290693825 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.edn_genbits.22804018697129688215023671047977752960057584491816674390268562019460290693825
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.23302005502428046343026456031154464606043472564072468326124219227370351446621
Short name T925
Test name
Test status
Simulation time 18439183 ps
CPU time 1.15 seconds
Started Oct 29 02:07:00 PM PDT 23
Finished Oct 29 02:07:05 PM PDT 23
Peak memory 222248 kb
Host smart-95b9563d-4dc7-497c-a142-a99f7fdf31d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23302005502428046343026456031154464606043472564072468326124219227370351446621 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.edn_intr.23302005502428046343026456031154464606043472564072468326124219227370351446621
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.87647778140979662112262202071237295501994854097207987290218869945645231917680
Short name T311
Test name
Test status
Simulation time 13059183 ps
CPU time 0.86 seconds
Started Oct 29 02:06:42 PM PDT 23
Finished Oct 29 02:06:44 PM PDT 23
Peak memory 205388 kb
Host smart-76ba9f57-2188-4a3a-8bce-fcefd7dda968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87647778140979662112262202071237295501994854097207987290218869945645231917680 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.edn_smoke.87647778140979662112262202071237295501994854097207987290218869945645231917680
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.113044250863669287496165045356908620050993440362357129971376607938768219459196
Short name T353
Test name
Test status
Simulation time 154489183 ps
CPU time 3.91 seconds
Started Oct 29 02:06:56 PM PDT 23
Finished Oct 29 02:07:01 PM PDT 23
Peak memory 206376 kb
Host smart-cf2958b5-63a1-405e-8ae0-c45542f386f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113044250863669287496165045356908620050993440362357129971376607938768219459196 -assert nopo
stproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.113044250863669287496165045356908620050993440362357129971376607938768219459196
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.75689261269069584595564701866114071918265842762071800598502938017698574527094
Short name T307
Test name
Test status
Simulation time 41708099183 ps
CPU time 1081.27 seconds
Started Oct 29 02:07:21 PM PDT 23
Finished Oct 29 02:25:26 PM PDT 23
Peak memory 215848 kb
Host smart-c9e8bde9-f8c8-4af5-ac26-548781393f39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756892612690695845955647018
66114071918265842762071800598502938017698574527094 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.75689261269
069584595564701866114071918265842762071800598502938017698574527094
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.30119826891555376699019047223635514245907995865540152817095155462070945561341
Short name T787
Test name
Test status
Simulation time 17999183 ps
CPU time 1.16 seconds
Started Oct 29 02:08:48 PM PDT 23
Finished Oct 29 02:08:50 PM PDT 23
Peak memory 205844 kb
Host smart-ab0fb094-0a15-4bdc-add0-8cf467c32fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30119826891555376699019047223635514245907995865540152817095155462070945561341 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 110.edn_genbits.30119826891555376699019047223635514245907995865540152817095155462070945561341
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.8215499439749501704478141585391813521414780539866376557422793132416195327938
Short name T546
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:09:00 PM PDT 23
Finished Oct 29 02:09:04 PM PDT 23
Peak memory 205856 kb
Host smart-56ec1823-e9bb-40e5-a088-550a1af04d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8215499439749501704478141585391813521414780539866376557422793132416195327938 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 111.edn_genbits.8215499439749501704478141585391813521414780539866376557422793132416195327938
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.27953401644440742096616328560002998350750154698942040304034027716113200107913
Short name T322
Test name
Test status
Simulation time 17999183 ps
CPU time 1.06 seconds
Started Oct 29 02:08:42 PM PDT 23
Finished Oct 29 02:08:43 PM PDT 23
Peak memory 205828 kb
Host smart-d5bbf81c-c033-4870-85b9-2a178f9ae1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27953401644440742096616328560002998350750154698942040304034027716113200107913 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 112.edn_genbits.27953401644440742096616328560002998350750154698942040304034027716113200107913
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.88789154177151815555058626494555037225742549466047505144150823000043076912676
Short name T728
Test name
Test status
Simulation time 17999183 ps
CPU time 1.05 seconds
Started Oct 29 02:08:49 PM PDT 23
Finished Oct 29 02:08:51 PM PDT 23
Peak memory 205816 kb
Host smart-4bea1dc7-8bd3-4090-860d-f2e0e9911428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88789154177151815555058626494555037225742549466047505144150823000043076912676 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 113.edn_genbits.88789154177151815555058626494555037225742549466047505144150823000043076912676
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.49960704555501078811270388829660470573724191389109108527990573906494467995903
Short name T529
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Oct 29 02:08:47 PM PDT 23
Finished Oct 29 02:08:48 PM PDT 23
Peak memory 205856 kb
Host smart-967cabfd-1267-47c0-b588-c90403ddb775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49960704555501078811270388829660470573724191389109108527990573906494467995903 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 114.edn_genbits.49960704555501078811270388829660470573724191389109108527990573906494467995903
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.20309720588753653316256611269745115581929463223935293199776581259854260937448
Short name T868
Test name
Test status
Simulation time 17999183 ps
CPU time 1.17 seconds
Started Oct 29 02:09:25 PM PDT 23
Finished Oct 29 02:09:27 PM PDT 23
Peak memory 205848 kb
Host smart-2696f479-09b8-4307-b6ae-5bc670ebe783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20309720588753653316256611269745115581929463223935293199776581259854260937448 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 115.edn_genbits.20309720588753653316256611269745115581929463223935293199776581259854260937448
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.110664930715825492260444802031240902091386973239171827277297430532866213271627
Short name T710
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:09:23 PM PDT 23
Finished Oct 29 02:09:24 PM PDT 23
Peak memory 205832 kb
Host smart-bf25d0bb-bc60-48ee-ba25-e0447e5a11a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110664930715825492260444802031240902091386973239171827277297430532866213271627 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 116.edn_genbits.110664930715825492260444802031240902091386973239171827277297430532866213271627
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.30672612509609495425594436874806819544584982851574824962719091956591326285701
Short name T538
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Oct 29 02:09:43 PM PDT 23
Finished Oct 29 02:09:44 PM PDT 23
Peak memory 205796 kb
Host smart-bdda587c-543d-4cac-9d03-0fd34c04b8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30672612509609495425594436874806819544584982851574824962719091956591326285701 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 117.edn_genbits.30672612509609495425594436874806819544584982851574824962719091956591326285701
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.68964842232100144296466789287527495527209791668684255323823383229319275480011
Short name T944
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Oct 29 02:09:41 PM PDT 23
Finished Oct 29 02:09:43 PM PDT 23
Peak memory 205828 kb
Host smart-a2d144da-7986-4539-b55b-fc82e83ffb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68964842232100144296466789287527495527209791668684255323823383229319275480011 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 118.edn_genbits.68964842232100144296466789287527495527209791668684255323823383229319275480011
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.17579892378701545333896868262110065483168451234115334444640464038240118007587
Short name T381
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Oct 29 02:08:40 PM PDT 23
Finished Oct 29 02:08:43 PM PDT 23
Peak memory 205828 kb
Host smart-9e04abd9-1d20-4dc1-aa7f-e6989413e647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17579892378701545333896868262110065483168451234115334444640464038240118007587 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 119.edn_genbits.17579892378701545333896868262110065483168451234115334444640464038240118007587
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.106331496842006722640092225666608925369030746180037105396001571478663959142011
Short name T973
Test name
Test status
Simulation time 18259183 ps
CPU time 1.01 seconds
Started Oct 29 02:06:40 PM PDT 23
Finished Oct 29 02:06:41 PM PDT 23
Peak memory 205552 kb
Host smart-d6423001-69f2-42f3-acb7-a666e95c0a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106331496842006722640092225666608925369030746180037105396001571478663959142011 -assert nopostproc +UVM_TESTNAME=edn_aler
t_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.edn_alert.106331496842006722640092225666608925369030746180037105396001571478663959142011
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.49384533015738928091938644671710420914691252805156476530535173400829667207154
Short name T748
Test name
Test status
Simulation time 28184990 ps
CPU time 0.87 seconds
Started Oct 29 02:06:57 PM PDT 23
Finished Oct 29 02:06:58 PM PDT 23
Peak memory 205432 kb
Host smart-0a1ff8c9-c363-4efe-bc37-0867eaf95739
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49384533015738928091938644671710420914691252805156476530535173400829667207154 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.edn_alert_test.49384533015738928091938644671710420914691252805156476530535173400829667207154
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.106515130591301208789202288501068022230181858359803934222485001747510253153403
Short name T850
Test name
Test status
Simulation time 17319183 ps
CPU time 0.87 seconds
Started Oct 29 02:06:57 PM PDT 23
Finished Oct 29 02:06:59 PM PDT 23
Peak memory 214900 kb
Host smart-b85ccd62-95e7-48fd-b37b-3ce6c6577a94
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106515130591301208789202288501068022230181858359803934222485001747510253153403 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable_auto_req_mode.106515130591301208789202288501068022230181858359803934222
485001747510253153403
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.34895516089690605529534170431153767416359629907467894732733839982104349321200
Short name T668
Test name
Test status
Simulation time 24963823 ps
CPU time 1.16 seconds
Started Oct 29 02:07:00 PM PDT 23
Finished Oct 29 02:07:05 PM PDT 23
Peak memory 230452 kb
Host smart-4fded56d-fb1c-4716-a79a-66f855c2562d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34895516089690605529534170431153767416359629907467894732733839982104349321200 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.edn_err.34895516089690605529534170431153767416359629907467894732733839982104349321200
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.105181687542804575058126140984798651429877122684279480226996298689400234760241
Short name T237
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Oct 29 02:07:23 PM PDT 23
Finished Oct 29 02:07:26 PM PDT 23
Peak memory 205752 kb
Host smart-49f9b0c2-4409-41b7-9287-62140caf9b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105181687542804575058126140984798651429877122684279480226996298689400234760241 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 12.edn_genbits.105181687542804575058126140984798651429877122684279480226996298689400234760241
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.91596898427670301721605964069567107568518634612391106088006336152582034544907
Short name T54
Test name
Test status
Simulation time 18439183 ps
CPU time 1.25 seconds
Started Oct 29 02:06:40 PM PDT 23
Finished Oct 29 02:06:42 PM PDT 23
Peak memory 222352 kb
Host smart-27d71538-8144-4c9c-b3eb-0b0fcfb39011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91596898427670301721605964069567107568518634612391106088006336152582034544907 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.edn_intr.91596898427670301721605964069567107568518634612391106088006336152582034544907
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.46180739280321889391369520048596707560644084299675589831578374966200065686991
Short name T805
Test name
Test status
Simulation time 13059183 ps
CPU time 0.9 seconds
Started Oct 29 02:07:28 PM PDT 23
Finished Oct 29 02:07:30 PM PDT 23
Peak memory 205500 kb
Host smart-1f8411fb-7434-4ea3-99d8-c2fa07e3ba37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46180739280321889391369520048596707560644084299675589831578374966200065686991 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.edn_smoke.46180739280321889391369520048596707560644084299675589831578374966200065686991
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.90360915519442175699403241849756194153133603744001260807566549268481549651086
Short name T807
Test name
Test status
Simulation time 154489183 ps
CPU time 3.87 seconds
Started Oct 29 02:07:05 PM PDT 23
Finished Oct 29 02:07:11 PM PDT 23
Peak memory 206372 kb
Host smart-e8f8bad9-09d5-4991-802d-dca4d780f078
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90360915519442175699403241849756194153133603744001260807566549268481549651086 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.90360915519442175699403241849756194153133603744001260807566549268481549651086
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.49683769361522738951527293797689882200106419230438443301662462828858543794568
Short name T579
Test name
Test status
Simulation time 41708099183 ps
CPU time 1065.24 seconds
Started Oct 29 02:06:57 PM PDT 23
Finished Oct 29 02:24:42 PM PDT 23
Peak memory 215956 kb
Host smart-e2e7004c-0581-4afa-adae-cf346fee0925
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496837693615227389515272937
97689882200106419230438443301662462828858543794568 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.49683769361
522738951527293797689882200106419230438443301662462828858543794568
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.83166127932388881048566672652044876364510438081562066475114584460609512960400
Short name T61
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Oct 29 02:08:56 PM PDT 23
Finished Oct 29 02:08:58 PM PDT 23
Peak memory 205816 kb
Host smart-8e7b6077-fc2e-45f0-8e20-a2bc10d1ef8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83166127932388881048566672652044876364510438081562066475114584460609512960400 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 120.edn_genbits.83166127932388881048566672652044876364510438081562066475114584460609512960400
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.93149851032329027473710681932041726649283913607801981644985517553965942265946
Short name T514
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Oct 29 02:09:45 PM PDT 23
Finished Oct 29 02:09:47 PM PDT 23
Peak memory 205860 kb
Host smart-bb731221-0798-4248-8280-9d716e0dfd57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93149851032329027473710681932041726649283913607801981644985517553965942265946 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 121.edn_genbits.93149851032329027473710681932041726649283913607801981644985517553965942265946
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.99442111168138983412509441707001177918908736819037845438701932768567311061442
Short name T879
Test name
Test status
Simulation time 17999183 ps
CPU time 1.05 seconds
Started Oct 29 02:09:36 PM PDT 23
Finished Oct 29 02:09:37 PM PDT 23
Peak memory 205712 kb
Host smart-63691727-a38b-4804-b118-1ecc359ca2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99442111168138983412509441707001177918908736819037845438701932768567311061442 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 122.edn_genbits.99442111168138983412509441707001177918908736819037845438701932768567311061442
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.58927452614701849997983863321525762215449739587259712953815854547874946353414
Short name T815
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Oct 29 02:09:41 PM PDT 23
Finished Oct 29 02:09:42 PM PDT 23
Peak memory 205828 kb
Host smart-3c076747-af63-4f67-b95e-60bd3b10fab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58927452614701849997983863321525762215449739587259712953815854547874946353414 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 123.edn_genbits.58927452614701849997983863321525762215449739587259712953815854547874946353414
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.50553903505073131422413687047237357176402802425658013457751512226918543889243
Short name T371
Test name
Test status
Simulation time 17999183 ps
CPU time 1.05 seconds
Started Oct 29 02:08:54 PM PDT 23
Finished Oct 29 02:08:56 PM PDT 23
Peak memory 205428 kb
Host smart-0d2db4e5-cb0e-4427-a5fe-df476dc6cfa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50553903505073131422413687047237357176402802425658013457751512226918543889243 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 124.edn_genbits.50553903505073131422413687047237357176402802425658013457751512226918543889243
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.29189253649253637076401963330915539806395571939106210562394439429201178692172
Short name T372
Test name
Test status
Simulation time 17999183 ps
CPU time 1.15 seconds
Started Oct 29 02:09:43 PM PDT 23
Finished Oct 29 02:09:44 PM PDT 23
Peak memory 205832 kb
Host smart-fc33be4b-d20c-43c5-8e02-527f25d9663e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29189253649253637076401963330915539806395571939106210562394439429201178692172 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 125.edn_genbits.29189253649253637076401963330915539806395571939106210562394439429201178692172
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.37155196367738954009034709307495311975428619394754205403297552107795781328321
Short name T769
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Oct 29 02:10:05 PM PDT 23
Finished Oct 29 02:10:07 PM PDT 23
Peak memory 205860 kb
Host smart-7e8b4eeb-9bb4-4ed2-af0e-d38e1a705e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37155196367738954009034709307495311975428619394754205403297552107795781328321 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 126.edn_genbits.37155196367738954009034709307495311975428619394754205403297552107795781328321
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.69275108689267890078841655101687581631545815512872167585764891680177037830683
Short name T496
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Oct 29 02:09:40 PM PDT 23
Finished Oct 29 02:09:41 PM PDT 23
Peak memory 205852 kb
Host smart-54bc1b2b-0d4d-440b-a5b9-2bbf45906eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69275108689267890078841655101687581631545815512872167585764891680177037830683 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 127.edn_genbits.69275108689267890078841655101687581631545815512872167585764891680177037830683
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.61331513722235532349512031234063734687891945206342459161235949091068237873120
Short name T745
Test name
Test status
Simulation time 17999183 ps
CPU time 1.18 seconds
Started Oct 29 02:10:26 PM PDT 23
Finished Oct 29 02:10:28 PM PDT 23
Peak memory 205880 kb
Host smart-1e460c5e-c872-4860-a562-f266894e5d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61331513722235532349512031234063734687891945206342459161235949091068237873120 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 128.edn_genbits.61331513722235532349512031234063734687891945206342459161235949091068237873120
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.16634192746935437825486168979156489509721596639406951797231571856292330801276
Short name T284
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Oct 29 02:09:52 PM PDT 23
Finished Oct 29 02:09:53 PM PDT 23
Peak memory 205932 kb
Host smart-412eb325-5229-409f-a99e-307ba3974135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16634192746935437825486168979156489509721596639406951797231571856292330801276 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 129.edn_genbits.16634192746935437825486168979156489509721596639406951797231571856292330801276
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.112526234241310027866327748742726263133854077814128870757388566818027507662026
Short name T979
Test name
Test status
Simulation time 18259183 ps
CPU time 0.96 seconds
Started Oct 29 02:06:58 PM PDT 23
Finished Oct 29 02:07:00 PM PDT 23
Peak memory 205600 kb
Host smart-d0bdb98e-0a13-4b58-ad19-0eb025cca398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112526234241310027866327748742726263133854077814128870757388566818027507662026 -assert nopostproc +UVM_TESTNAME=edn_aler
t_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.edn_alert.112526234241310027866327748742726263133854077814128870757388566818027507662026
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.75308256983684589365551906736823360994100804871416797507994274886129402720953
Short name T790
Test name
Test status
Simulation time 28184990 ps
CPU time 0.87 seconds
Started Oct 29 02:07:33 PM PDT 23
Finished Oct 29 02:07:34 PM PDT 23
Peak memory 205484 kb
Host smart-00e2d3ea-1780-4c92-b98d-99e1bd8881e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75308256983684589365551906736823360994100804871416797507994274886129402720953 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.edn_alert_test.75308256983684589365551906736823360994100804871416797507994274886129402720953
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.20903981784514585843796163923872400436669460153412417615080572973541110057737
Short name T513
Test name
Test status
Simulation time 12219183 ps
CPU time 0.9 seconds
Started Oct 29 02:07:02 PM PDT 23
Finished Oct 29 02:07:05 PM PDT 23
Peak memory 214768 kb
Host smart-0989c06e-0a58-4487-9a1b-aea6ceec2faa
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20903981784514585843796163923872400436669460153412417615080572973541110057737 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.edn_disable.20903981784514585843796163923872400436669460153412417615080572973541110057737
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.53913257322300981456562156685400688420121590779891967687338495810249144355125
Short name T696
Test name
Test status
Simulation time 17319183 ps
CPU time 0.95 seconds
Started Oct 29 02:07:03 PM PDT 23
Finished Oct 29 02:07:05 PM PDT 23
Peak memory 214880 kb
Host smart-52dc4d69-faae-499c-be70-370af3497b3c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53913257322300981456562156685400688420121590779891967687338495810249144355125 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable_auto_req_mode.5391325732230098145656215668540068842012159077989196768733
8495810249144355125
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.98694493164094608466713456294425970172722953761932331229119964974083934941856
Short name T744
Test name
Test status
Simulation time 24963823 ps
CPU time 1.17 seconds
Started Oct 29 02:07:06 PM PDT 23
Finished Oct 29 02:07:09 PM PDT 23
Peak memory 230476 kb
Host smart-37ae5675-52b4-46b1-831e-f20cba173fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98694493164094608466713456294425970172722953761932331229119964974083934941856 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.edn_err.98694493164094608466713456294425970172722953761932331229119964974083934941856
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.110931023320404384337943409869170532276725611327560759097299408473464487241233
Short name T413
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Oct 29 02:07:30 PM PDT 23
Finished Oct 29 02:07:31 PM PDT 23
Peak memory 205836 kb
Host smart-4d1eaebe-8d99-4858-b16e-a34f20ee3e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110931023320404384337943409869170532276725611327560759097299408473464487241233 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 13.edn_genbits.110931023320404384337943409869170532276725611327560759097299408473464487241233
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.26069576374936083401398633831913591775475519707524970511569153083910318671389
Short name T493
Test name
Test status
Simulation time 18439183 ps
CPU time 1.09 seconds
Started Oct 29 02:07:04 PM PDT 23
Finished Oct 29 02:07:07 PM PDT 23
Peak memory 222252 kb
Host smart-fa6b398d-b18f-4b91-b0eb-c55ccb1b6d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26069576374936083401398633831913591775475519707524970511569153083910318671389 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.edn_intr.26069576374936083401398633831913591775475519707524970511569153083910318671389
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.95635810214169452257108817368291665812120030028914501468032778690969309853534
Short name T269
Test name
Test status
Simulation time 13059183 ps
CPU time 0.86 seconds
Started Oct 29 02:06:56 PM PDT 23
Finished Oct 29 02:06:57 PM PDT 23
Peak memory 205236 kb
Host smart-378238f8-958d-4bbd-80d0-7d89021b941b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95635810214169452257108817368291665812120030028914501468032778690969309853534 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.edn_smoke.95635810214169452257108817368291665812120030028914501468032778690969309853534
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.3846408041291933919179360271717380640792497917535240265397397058811962348487
Short name T650
Test name
Test status
Simulation time 154489183 ps
CPU time 4.09 seconds
Started Oct 29 02:06:40 PM PDT 23
Finished Oct 29 02:06:44 PM PDT 23
Peak memory 206344 kb
Host smart-577b089f-f54d-4472-98c9-af40c28ddd2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846408041291933919179360271717380640792497917535240265397397058811962348487 -assert nopost
proc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.3846408041291933919179360271717380640792497917535240265397397058811962348487
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.81728465647717365753245095944100308729352903732539257525146926206081842100986
Short name T785
Test name
Test status
Simulation time 41708099183 ps
CPU time 1068.45 seconds
Started Oct 29 02:07:26 PM PDT 23
Finished Oct 29 02:25:16 PM PDT 23
Peak memory 215848 kb
Host smart-e975d7f3-2b41-43d0-b9d6-e63e2d57e86b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817284656477173657532450959
44100308729352903732539257525146926206081842100986 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.81728465647
717365753245095944100308729352903732539257525146926206081842100986
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.55564798234588410619466940923035274657252884771951719635891190011374613671117
Short name T301
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Oct 29 02:10:31 PM PDT 23
Finished Oct 29 02:10:33 PM PDT 23
Peak memory 205784 kb
Host smart-a03c5a08-53cd-4ec8-96f6-809b71b885eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55564798234588410619466940923035274657252884771951719635891190011374613671117 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 130.edn_genbits.55564798234588410619466940923035274657252884771951719635891190011374613671117
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.5502129662612168611930548111803282582172463520384329901127475434094877214182
Short name T377
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:09:53 PM PDT 23
Finished Oct 29 02:09:55 PM PDT 23
Peak memory 205812 kb
Host smart-232c11f5-3c46-432d-bbce-629d0b50e566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5502129662612168611930548111803282582172463520384329901127475434094877214182 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 131.edn_genbits.5502129662612168611930548111803282582172463520384329901127475434094877214182
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.22531169778143441980237313201888791035190172642261554112913700340171699446656
Short name T450
Test name
Test status
Simulation time 17999183 ps
CPU time 1.05 seconds
Started Oct 29 02:10:01 PM PDT 23
Finished Oct 29 02:10:02 PM PDT 23
Peak memory 205808 kb
Host smart-67b3ba2e-a7d9-4f63-9a36-16bcdfd5304d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22531169778143441980237313201888791035190172642261554112913700340171699446656 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 132.edn_genbits.22531169778143441980237313201888791035190172642261554112913700340171699446656
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.76428826283328040135854627336240517742154586022609800101536080606000776725415
Short name T557
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Oct 29 02:09:54 PM PDT 23
Finished Oct 29 02:09:55 PM PDT 23
Peak memory 205808 kb
Host smart-8818b3eb-2779-49f6-94d7-adb0297bd3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76428826283328040135854627336240517742154586022609800101536080606000776725415 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 133.edn_genbits.76428826283328040135854627336240517742154586022609800101536080606000776725415
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.41141229601640630130936341498542735169375497206979016741191349809109311431190
Short name T505
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Oct 29 02:10:31 PM PDT 23
Finished Oct 29 02:10:33 PM PDT 23
Peak memory 205820 kb
Host smart-5b49a461-789f-498b-89fe-f7c90cf15ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41141229601640630130936341498542735169375497206979016741191349809109311431190 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 134.edn_genbits.41141229601640630130936341498542735169375497206979016741191349809109311431190
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.103605184118397429323008973655734563872736114875727799544443531878413929100349
Short name T500
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Oct 29 02:09:57 PM PDT 23
Finished Oct 29 02:09:58 PM PDT 23
Peak memory 205792 kb
Host smart-72282890-f8ba-4335-947e-0ccc552a78f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103605184118397429323008973655734563872736114875727799544443531878413929100349 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 135.edn_genbits.103605184118397429323008973655734563872736114875727799544443531878413929100349
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.115392932191429282596594706279332819569745177037356798857175095312567530648668
Short name T530
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Oct 29 02:10:34 PM PDT 23
Finished Oct 29 02:10:36 PM PDT 23
Peak memory 205848 kb
Host smart-431abd97-4fa5-41d2-9a78-a2712214a37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115392932191429282596594706279332819569745177037356798857175095312567530648668 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 136.edn_genbits.115392932191429282596594706279332819569745177037356798857175095312567530648668
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.70339649863955876837555994458606128042611638696155216013428583794610937563022
Short name T857
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:10:34 PM PDT 23
Finished Oct 29 02:10:36 PM PDT 23
Peak memory 205816 kb
Host smart-6b82629f-f57d-4137-99eb-a401d523dfb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70339649863955876837555994458606128042611638696155216013428583794610937563022 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 137.edn_genbits.70339649863955876837555994458606128042611638696155216013428583794610937563022
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.13547240648986872720127725837001375307825591428130257126847712721095132021973
Short name T878
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Oct 29 02:10:21 PM PDT 23
Finished Oct 29 02:10:23 PM PDT 23
Peak memory 205840 kb
Host smart-29ba31f6-0e37-43ad-8721-d02a5cc7e0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13547240648986872720127725837001375307825591428130257126847712721095132021973 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 138.edn_genbits.13547240648986872720127725837001375307825591428130257126847712721095132021973
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.84787584060520809827139316312214821841467414811447934690639446181363091758133
Short name T442
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Oct 29 02:10:34 PM PDT 23
Finished Oct 29 02:10:36 PM PDT 23
Peak memory 205828 kb
Host smart-333f0547-4b6d-4f4d-b958-b7a0fd13e617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84787584060520809827139316312214821841467414811447934690639446181363091758133 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 139.edn_genbits.84787584060520809827139316312214821841467414811447934690639446181363091758133
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.20679879945556976409197064444184980612160325499523363912986303655935045143236
Short name T401
Test name
Test status
Simulation time 18259183 ps
CPU time 0.97 seconds
Started Oct 29 02:07:07 PM PDT 23
Finished Oct 29 02:07:09 PM PDT 23
Peak memory 205612 kb
Host smart-9818bc20-2772-4f0e-a8b6-10d7eb114ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20679879945556976409197064444184980612160325499523363912986303655935045143236 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.edn_alert.20679879945556976409197064444184980612160325499523363912986303655935045143236
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_disable.97148776102379170945171374607074910693156138132922517878453008311772501510490
Short name T603
Test name
Test status
Simulation time 12219183 ps
CPU time 0.88 seconds
Started Oct 29 02:07:05 PM PDT 23
Finished Oct 29 02:07:08 PM PDT 23
Peak memory 214848 kb
Host smart-33db70a8-0c06-4ec2-b46d-b8eb7c7f2f1b
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97148776102379170945171374607074910693156138132922517878453008311772501510490 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.edn_disable.97148776102379170945171374607074910693156138132922517878453008311772501510490
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.91504787522247105579108189461468568745944249951887723098102465151137182805229
Short name T566
Test name
Test status
Simulation time 17319183 ps
CPU time 0.94 seconds
Started Oct 29 02:08:09 PM PDT 23
Finished Oct 29 02:08:10 PM PDT 23
Peak memory 214852 kb
Host smart-7d90456b-34bf-42eb-a6a6-cf2581d6f136
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91504787522247105579108189461468568745944249951887723098102465151137182805229 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable_auto_req_mode.9150478752224710557910818946146856874594424995188772309810
2465151137182805229
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.37678824900364929109011571144907796407953029851395401442187984223417951644552
Short name T463
Test name
Test status
Simulation time 24963823 ps
CPU time 1.15 seconds
Started Oct 29 02:07:29 PM PDT 23
Finished Oct 29 02:07:31 PM PDT 23
Peak memory 230616 kb
Host smart-c58c4edc-fb67-4a55-89e6-2f69bc351c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37678824900364929109011571144907796407953029851395401442187984223417951644552 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.edn_err.37678824900364929109011571144907796407953029851395401442187984223417951644552
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.81882026879566656504809356080943221242680273486236264177460037325748371873428
Short name T391
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Oct 29 02:07:06 PM PDT 23
Finished Oct 29 02:07:09 PM PDT 23
Peak memory 205828 kb
Host smart-fb4ee348-e8ae-4c5d-ac40-d3d002a2b662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81882026879566656504809356080943221242680273486236264177460037325748371873428 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.edn_genbits.81882026879566656504809356080943221242680273486236264177460037325748371873428
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.27657896092663486312903772863188770271712054482978140354486046774819922093930
Short name T608
Test name
Test status
Simulation time 18439183 ps
CPU time 1.18 seconds
Started Oct 29 02:07:04 PM PDT 23
Finished Oct 29 02:07:07 PM PDT 23
Peak memory 222276 kb
Host smart-9236c120-12cf-48f3-8b3d-175b7789334f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27657896092663486312903772863188770271712054482978140354486046774819922093930 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.edn_intr.27657896092663486312903772863188770271712054482978140354486046774819922093930
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.65124128131466484835384343285858869378036165383517227094280811111420455987170
Short name T763
Test name
Test status
Simulation time 13059183 ps
CPU time 0.87 seconds
Started Oct 29 02:07:02 PM PDT 23
Finished Oct 29 02:07:05 PM PDT 23
Peak memory 205348 kb
Host smart-7868872d-1523-4b4d-9095-3b0f252b9dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65124128131466484835384343285858869378036165383517227094280811111420455987170 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.edn_smoke.65124128131466484835384343285858869378036165383517227094280811111420455987170
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.78170595299788726396652842998214194236387289531853691949702673223482784377212
Short name T613
Test name
Test status
Simulation time 154489183 ps
CPU time 3.87 seconds
Started Oct 29 02:07:31 PM PDT 23
Finished Oct 29 02:07:36 PM PDT 23
Peak memory 206356 kb
Host smart-d51c9725-685d-4b4f-839c-dae19b5a8552
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78170595299788726396652842998214194236387289531853691949702673223482784377212 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.78170595299788726396652842998214194236387289531853691949702673223482784377212
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.89285586664990947518755637302038049940585667936057149281045368068885659991531
Short name T686
Test name
Test status
Simulation time 41708099183 ps
CPU time 1092.88 seconds
Started Oct 29 02:07:31 PM PDT 23
Finished Oct 29 02:25:45 PM PDT 23
Peak memory 215864 kb
Host smart-f2668728-fcc8-41c6-be36-c08dcd26de48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892855866649909475187556373
02038049940585667936057149281045368068885659991531 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.89285586664
990947518755637302038049940585667936057149281045368068885659991531
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.17169577910901386926946283228513058980935728870014341396692179595320328348894
Short name T319
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Oct 29 02:10:47 PM PDT 23
Finished Oct 29 02:10:49 PM PDT 23
Peak memory 205828 kb
Host smart-66a80f9c-4503-4d4d-a571-73d4c78dd65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17169577910901386926946283228513058980935728870014341396692179595320328348894 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 140.edn_genbits.17169577910901386926946283228513058980935728870014341396692179595320328348894
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.73602792889862463490687517185189069528924601994574853077214240274769433261807
Short name T559
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Oct 29 02:10:49 PM PDT 23
Finished Oct 29 02:10:51 PM PDT 23
Peak memory 205796 kb
Host smart-b0b89a52-6683-40bd-a6e4-8ae38b1c6bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73602792889862463490687517185189069528924601994574853077214240274769433261807 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 141.edn_genbits.73602792889862463490687517185189069528924601994574853077214240274769433261807
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.59747441174166616915182770113029773188961117592799577223670655812724996613515
Short name T676
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Oct 29 02:10:40 PM PDT 23
Finished Oct 29 02:10:42 PM PDT 23
Peak memory 205856 kb
Host smart-d2f329da-07ec-4715-9f9c-3350f57796a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59747441174166616915182770113029773188961117592799577223670655812724996613515 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 142.edn_genbits.59747441174166616915182770113029773188961117592799577223670655812724996613515
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.36984381557181947879092293296012812368132088917926085652429932405711634771518
Short name T520
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:10:54 PM PDT 23
Finished Oct 29 02:10:56 PM PDT 23
Peak memory 205824 kb
Host smart-5e6c3768-5a1a-453f-89f4-84cb433969d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36984381557181947879092293296012812368132088917926085652429932405711634771518 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 143.edn_genbits.36984381557181947879092293296012812368132088917926085652429932405711634771518
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.3223853311065853339876311765299591408975998810487529284712481021891016250244
Short name T915
Test name
Test status
Simulation time 17999183 ps
CPU time 1.06 seconds
Started Oct 29 02:10:52 PM PDT 23
Finished Oct 29 02:10:53 PM PDT 23
Peak memory 205804 kb
Host smart-d53ee9b3-9764-4505-ad6c-08a39ea5d249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223853311065853339876311765299591408975998810487529284712481021891016250244 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 144.edn_genbits.3223853311065853339876311765299591408975998810487529284712481021891016250244
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.36345996340067606065698073331994326316975721999754361420934107804843410284422
Short name T812
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:10:44 PM PDT 23
Finished Oct 29 02:10:46 PM PDT 23
Peak memory 205836 kb
Host smart-24201b24-464e-41a4-85e3-683b810a5fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36345996340067606065698073331994326316975721999754361420934107804843410284422 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 145.edn_genbits.36345996340067606065698073331994326316975721999754361420934107804843410284422
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.3572708283743763125602765530241038453257486848090663915837954035276634538631
Short name T527
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Oct 29 02:10:51 PM PDT 23
Finished Oct 29 02:10:52 PM PDT 23
Peak memory 205760 kb
Host smart-092e3119-f4ae-453f-a54b-3eb124439907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572708283743763125602765530241038453257486848090663915837954035276634538631 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 146.edn_genbits.3572708283743763125602765530241038453257486848090663915837954035276634538631
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.22589829981632351859377189934664972239928375243051481022479701744684090444508
Short name T236
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Oct 29 02:10:48 PM PDT 23
Finished Oct 29 02:10:49 PM PDT 23
Peak memory 205816 kb
Host smart-41ab2e5a-524e-4e45-a80a-7455906f88a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22589829981632351859377189934664972239928375243051481022479701744684090444508 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 147.edn_genbits.22589829981632351859377189934664972239928375243051481022479701744684090444508
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.48156934256079525531440787721410329723344059332983813722823136263083364059996
Short name T544
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Oct 29 02:10:45 PM PDT 23
Finished Oct 29 02:10:46 PM PDT 23
Peak memory 205844 kb
Host smart-bc973d1e-7d0e-48f3-99bf-f841b28240c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48156934256079525531440787721410329723344059332983813722823136263083364059996 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 148.edn_genbits.48156934256079525531440787721410329723344059332983813722823136263083364059996
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.8407954208069619346606979963871582265895701638281764515807938228213952213517
Short name T295
Test name
Test status
Simulation time 17999183 ps
CPU time 1.06 seconds
Started Oct 29 02:10:44 PM PDT 23
Finished Oct 29 02:10:46 PM PDT 23
Peak memory 205936 kb
Host smart-147d852f-8b86-4647-8596-c3c19d25e297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8407954208069619346606979963871582265895701638281764515807938228213952213517 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 149.edn_genbits.8407954208069619346606979963871582265895701638281764515807938228213952213517
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.84085098849689333255842407337003979273804120841701590367905268290004597173945
Short name T679
Test name
Test status
Simulation time 18259183 ps
CPU time 0.94 seconds
Started Oct 29 02:06:41 PM PDT 23
Finished Oct 29 02:06:42 PM PDT 23
Peak memory 205588 kb
Host smart-675e00bd-b9d3-4633-bd5f-19e441f1451d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84085098849689333255842407337003979273804120841701590367905268290004597173945 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.edn_alert.84085098849689333255842407337003979273804120841701590367905268290004597173945
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.33074604267206051705004499628815068175257330507166880953209280816708330437363
Short name T649
Test name
Test status
Simulation time 28184990 ps
CPU time 0.86 seconds
Started Oct 29 02:06:40 PM PDT 23
Finished Oct 29 02:06:41 PM PDT 23
Peak memory 205508 kb
Host smart-4b62c6c8-323d-4c6b-bc1f-af95454a7614
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33074604267206051705004499628815068175257330507166880953209280816708330437363 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.edn_alert_test.33074604267206051705004499628815068175257330507166880953209280816708330437363
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.111554141463926284414384738591760341094842973438634959585026634584007607027090
Short name T64
Test name
Test status
Simulation time 12219183 ps
CPU time 0.89 seconds
Started Oct 29 02:06:57 PM PDT 23
Finished Oct 29 02:06:59 PM PDT 23
Peak memory 214788 kb
Host smart-a089814d-a77c-47cb-87e9-2ec85f3ed17b
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111554141463926284414384738591760341094842973438634959585026634584007607027090 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 15.edn_disable.111554141463926284414384738591760341094842973438634959585026634584007607027090
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.70689404389326081053513911165150957686873993591315451508881703287786070199187
Short name T928
Test name
Test status
Simulation time 17319183 ps
CPU time 1 seconds
Started Oct 29 02:07:02 PM PDT 23
Finished Oct 29 02:07:05 PM PDT 23
Peak memory 214908 kb
Host smart-23b4e744-ca1f-4241-b837-755b83675d1b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70689404389326081053513911165150957686873993591315451508881703287786070199187 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable_auto_req_mode.7068940438932608105351391116515095768687399359131545150888
1703287786070199187
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.80573212551842880160807461695408516913721481082088691540467785634939197516850
Short name T429
Test name
Test status
Simulation time 24963823 ps
CPU time 1.14 seconds
Started Oct 29 02:06:41 PM PDT 23
Finished Oct 29 02:06:43 PM PDT 23
Peak memory 230416 kb
Host smart-eb85c3d0-387c-422b-9bb6-d6b8508e4ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80573212551842880160807461695408516913721481082088691540467785634939197516850 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.edn_err.80573212551842880160807461695408516913721481082088691540467785634939197516850
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.28331495654344146152649192715658778427758819850391125757637826119237893431762
Short name T923
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Oct 29 02:07:03 PM PDT 23
Finished Oct 29 02:07:06 PM PDT 23
Peak memory 205796 kb
Host smart-10e581c4-8d28-4cd4-baa4-1d3e86919d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28331495654344146152649192715658778427758819850391125757637826119237893431762 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.edn_genbits.28331495654344146152649192715658778427758819850391125757637826119237893431762
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.52817734090018798221788988083579946129445073537229639665049588691729196388811
Short name T379
Test name
Test status
Simulation time 18439183 ps
CPU time 1.16 seconds
Started Oct 29 02:06:58 PM PDT 23
Finished Oct 29 02:07:00 PM PDT 23
Peak memory 222240 kb
Host smart-2a9cd10d-d6b0-4a93-b6cb-b8af28137797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52817734090018798221788988083579946129445073537229639665049588691729196388811 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.edn_intr.52817734090018798221788988083579946129445073537229639665049588691729196388811
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.69050062657267165718165198494745211295223291373656404887691233698776737178080
Short name T472
Test name
Test status
Simulation time 13059183 ps
CPU time 0.89 seconds
Started Oct 29 02:06:56 PM PDT 23
Finished Oct 29 02:06:57 PM PDT 23
Peak memory 205340 kb
Host smart-7c3cace5-d5e7-49e1-9ca9-b991aa80e0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69050062657267165718165198494745211295223291373656404887691233698776737178080 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.edn_smoke.69050062657267165718165198494745211295223291373656404887691233698776737178080
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.38814917093170663018931472209608790260920749158086071667867957139274741152628
Short name T572
Test name
Test status
Simulation time 154489183 ps
CPU time 4.05 seconds
Started Oct 29 02:06:42 PM PDT 23
Finished Oct 29 02:06:47 PM PDT 23
Peak memory 206384 kb
Host smart-b769ff52-7499-4cc8-bae7-da3fd4fcee65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38814917093170663018931472209608790260920749158086071667867957139274741152628 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.38814917093170663018931472209608790260920749158086071667867957139274741152628
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.109170974383960380824630156338304418216891602401064854402222664942796093317494
Short name T658
Test name
Test status
Simulation time 41708099183 ps
CPU time 1101.46 seconds
Started Oct 29 02:07:00 PM PDT 23
Finished Oct 29 02:25:25 PM PDT 23
Peak memory 215880 kb
Host smart-92cbb8a4-7b4a-451d-9e8a-e27dc6b773e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109170974383960380824630156
338304418216891602401064854402222664942796093317494 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.1091709743
83960380824630156338304418216891602401064854402222664942796093317494
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.45961930974299727862772991489958334816370859467909454179936630851202189860568
Short name T350
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Oct 29 02:10:43 PM PDT 23
Finished Oct 29 02:10:45 PM PDT 23
Peak memory 205828 kb
Host smart-12109eec-1f8f-47a8-b9e0-7b10a6d83a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45961930974299727862772991489958334816370859467909454179936630851202189860568 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 150.edn_genbits.45961930974299727862772991489958334816370859467909454179936630851202189860568
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.95096151517095027635131347721462012086306214943110400441798704159222290491265
Short name T277
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:09:54 PM PDT 23
Finished Oct 29 02:09:55 PM PDT 23
Peak memory 205852 kb
Host smart-3f95fac5-4154-40bb-8e83-7d6706b24955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95096151517095027635131347721462012086306214943110400441798704159222290491265 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 151.edn_genbits.95096151517095027635131347721462012086306214943110400441798704159222290491265
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.15227972436646933671213287646898695415434805871991312456352598386987273971042
Short name T865
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Oct 29 02:10:46 PM PDT 23
Finished Oct 29 02:10:48 PM PDT 23
Peak memory 205712 kb
Host smart-02081285-a428-4261-ad6d-7a896ffeb9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15227972436646933671213287646898695415434805871991312456352598386987273971042 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 152.edn_genbits.15227972436646933671213287646898695415434805871991312456352598386987273971042
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.57257450728719470641941777457841321281099965570773665875942908900313135367189
Short name T700
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Oct 29 02:10:44 PM PDT 23
Finished Oct 29 02:10:46 PM PDT 23
Peak memory 205828 kb
Host smart-ff1c58bf-a4c9-4220-b6cc-a152f208f1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57257450728719470641941777457841321281099965570773665875942908900313135367189 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 153.edn_genbits.57257450728719470641941777457841321281099965570773665875942908900313135367189
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.45075974422437067216955286080675420735430381735471125463184145134342574645463
Short name T661
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Oct 29 02:10:42 PM PDT 23
Finished Oct 29 02:10:43 PM PDT 23
Peak memory 205808 kb
Host smart-71cfccb7-96c1-4673-8f30-519c003acadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45075974422437067216955286080675420735430381735471125463184145134342574645463 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 154.edn_genbits.45075974422437067216955286080675420735430381735471125463184145134342574645463
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.92709350840635519660010639744573607154226110291995202987640414895190405055282
Short name T517
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:10:47 PM PDT 23
Finished Oct 29 02:10:48 PM PDT 23
Peak memory 205820 kb
Host smart-b02ce5a4-8235-4012-972d-879d4e7c4d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92709350840635519660010639744573607154226110291995202987640414895190405055282 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 155.edn_genbits.92709350840635519660010639744573607154226110291995202987640414895190405055282
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.94030336992153305083964177733562345152316221525788069202259490383984168591129
Short name T853
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Oct 29 02:10:49 PM PDT 23
Finished Oct 29 02:10:50 PM PDT 23
Peak memory 205820 kb
Host smart-d0e506bf-7136-4bf4-be4f-cd77571dd046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94030336992153305083964177733562345152316221525788069202259490383984168591129 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 156.edn_genbits.94030336992153305083964177733562345152316221525788069202259490383984168591129
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.91652216156021584874864879044643274261265380607713148608914309020185071102686
Short name T635
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Oct 29 02:10:32 PM PDT 23
Finished Oct 29 02:10:36 PM PDT 23
Peak memory 205852 kb
Host smart-e20fa687-0a91-4d94-9f28-c279cf40647c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91652216156021584874864879044643274261265380607713148608914309020185071102686 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 157.edn_genbits.91652216156021584874864879044643274261265380607713148608914309020185071102686
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.45905318205559933385276666231132322258308747536667642875242907724571800291747
Short name T756
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Oct 29 02:10:47 PM PDT 23
Finished Oct 29 02:10:48 PM PDT 23
Peak memory 205860 kb
Host smart-09580321-aba0-4b8e-a8af-72a2d8aa6e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45905318205559933385276666231132322258308747536667642875242907724571800291747 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 158.edn_genbits.45905318205559933385276666231132322258308747536667642875242907724571800291747
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.73729790481292320455713436950591804975485851793747235678994196599271950126661
Short name T567
Test name
Test status
Simulation time 17999183 ps
CPU time 1.06 seconds
Started Oct 29 02:08:50 PM PDT 23
Finished Oct 29 02:08:51 PM PDT 23
Peak memory 205816 kb
Host smart-0452a6c7-6afc-4986-9fdf-e99ea92015f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73729790481292320455713436950591804975485851793747235678994196599271950126661 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 159.edn_genbits.73729790481292320455713436950591804975485851793747235678994196599271950126661
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.10853055006249431392862952461348047900327339748687108695488335809531864149712
Short name T437
Test name
Test status
Simulation time 18259183 ps
CPU time 1 seconds
Started Oct 29 02:07:05 PM PDT 23
Finished Oct 29 02:07:09 PM PDT 23
Peak memory 205516 kb
Host smart-ae639084-c6c5-4a83-994b-8e68ece9f7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10853055006249431392862952461348047900327339748687108695488335809531864149712 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.edn_alert.10853055006249431392862952461348047900327339748687108695488335809531864149712
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.21870799101574433094167329423208949557451080062673864924416002746085696910283
Short name T506
Test name
Test status
Simulation time 28184990 ps
CPU time 0.88 seconds
Started Oct 29 02:07:02 PM PDT 23
Finished Oct 29 02:07:05 PM PDT 23
Peak memory 205476 kb
Host smart-21d344f4-43bd-4133-ac92-2fa0efa7a954
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21870799101574433094167329423208949557451080062673864924416002746085696910283 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.edn_alert_test.21870799101574433094167329423208949557451080062673864924416002746085696910283
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.98573800819625882864040321161710920512694241287993392830827161803796681661689
Short name T27
Test name
Test status
Simulation time 12219183 ps
CPU time 0.86 seconds
Started Oct 29 02:07:07 PM PDT 23
Finished Oct 29 02:07:09 PM PDT 23
Peak memory 214880 kb
Host smart-b02fab58-1bad-4f44-b2eb-48675c13b282
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98573800819625882864040321161710920512694241287993392830827161803796681661689 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.edn_disable.98573800819625882864040321161710920512694241287993392830827161803796681661689
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.65450556232438083432642754568481946329380670647735291518856325385826705411398
Short name T698
Test name
Test status
Simulation time 17319183 ps
CPU time 0.9 seconds
Started Oct 29 02:07:03 PM PDT 23
Finished Oct 29 02:07:05 PM PDT 23
Peak memory 214840 kb
Host smart-973f7aa7-6690-4bf6-80a9-8fea45185e4a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65450556232438083432642754568481946329380670647735291518856325385826705411398 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable_auto_req_mode.6545055623243808343264275456848194632938067064773529151885
6325385826705411398
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.113607691576269073464212995891375533596799648465566743066154139726120060300805
Short name T829
Test name
Test status
Simulation time 24963823 ps
CPU time 1.2 seconds
Started Oct 29 02:07:02 PM PDT 23
Finished Oct 29 02:07:06 PM PDT 23
Peak memory 230420 kb
Host smart-da9dfa0f-0e13-4c45-bcf2-59e3829c8625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113607691576269073464212995891375533596799648465566743066154139726120060300805 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.edn_err.113607691576269073464212995891375533596799648465566743066154139726120060300805
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.62928385947472111799325026404844730400683565010567170372121985207218758935790
Short name T422
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Oct 29 02:07:03 PM PDT 23
Finished Oct 29 02:07:06 PM PDT 23
Peak memory 205828 kb
Host smart-f591868c-14e8-448f-a6aa-ad19a77fe493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62928385947472111799325026404844730400683565010567170372121985207218758935790 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.edn_genbits.62928385947472111799325026404844730400683565010567170372121985207218758935790
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.103867616837353279219664581487451524489305231672990774084284290490587931671293
Short name T654
Test name
Test status
Simulation time 18439183 ps
CPU time 1.09 seconds
Started Oct 29 02:07:29 PM PDT 23
Finished Oct 29 02:07:31 PM PDT 23
Peak memory 222264 kb
Host smart-359bdf8f-1594-492f-9b96-90e307243354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103867616837353279219664581487451524489305231672990774084284290490587931671293 -assert nopostproc +UVM_TESTNAME=edn_intr
_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.edn_intr.103867616837353279219664581487451524489305231672990774084284290490587931671293
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.94258790393842972648743802351331956240311284301095348105683961276488555851137
Short name T969
Test name
Test status
Simulation time 13059183 ps
CPU time 0.88 seconds
Started Oct 29 02:07:29 PM PDT 23
Finished Oct 29 02:07:30 PM PDT 23
Peak memory 205384 kb
Host smart-8dfc3497-1728-4d87-818f-f6ef4a0f1f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94258790393842972648743802351331956240311284301095348105683961276488555851137 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.edn_smoke.94258790393842972648743802351331956240311284301095348105683961276488555851137
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.79613694848735906769279236141765450985624420679210385830497100007119743242139
Short name T96
Test name
Test status
Simulation time 154489183 ps
CPU time 4 seconds
Started Oct 29 02:06:59 PM PDT 23
Finished Oct 29 02:07:04 PM PDT 23
Peak memory 206304 kb
Host smart-ede9490c-40fd-4f5e-94c1-cb0be900ccab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79613694848735906769279236141765450985624420679210385830497100007119743242139 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.79613694848735906769279236141765450985624420679210385830497100007119743242139
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.70621857170277320118595017242357235733315803029873995127491590275467592158352
Short name T839
Test name
Test status
Simulation time 41708099183 ps
CPU time 1045.18 seconds
Started Oct 29 02:07:32 PM PDT 23
Finished Oct 29 02:24:58 PM PDT 23
Peak memory 215844 kb
Host smart-1f322af5-9be9-492e-b8ed-e9e640452c73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706218571702773201185950172
42357235733315803029873995127491590275467592158352 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.70621857170
277320118595017242357235733315803029873995127491590275467592158352
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.81872326292529411604138691999730613622630844697503652927319677965839765741754
Short name T44
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:09:53 PM PDT 23
Finished Oct 29 02:09:55 PM PDT 23
Peak memory 205852 kb
Host smart-28e58778-145f-46a4-9fc4-e301ef3131a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81872326292529411604138691999730613622630844697503652927319677965839765741754 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 160.edn_genbits.81872326292529411604138691999730613622630844697503652927319677965839765741754
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.29331340937203701590675722723364878731107318661979647459209309188595432183699
Short name T599
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:08:44 PM PDT 23
Finished Oct 29 02:08:47 PM PDT 23
Peak memory 205812 kb
Host smart-86a7ec77-62f8-46bb-aa85-80ce4aa832b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29331340937203701590675722723364878731107318661979647459209309188595432183699 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 161.edn_genbits.29331340937203701590675722723364878731107318661979647459209309188595432183699
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.114949193712013564994896111459844475018283774646451715609051923207142936819042
Short name T648
Test name
Test status
Simulation time 17999183 ps
CPU time 1.06 seconds
Started Oct 29 02:09:46 PM PDT 23
Finished Oct 29 02:09:48 PM PDT 23
Peak memory 205632 kb
Host smart-05073a91-1f68-4186-8293-93b21b34f180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114949193712013564994896111459844475018283774646451715609051923207142936819042 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 162.edn_genbits.114949193712013564994896111459844475018283774646451715609051923207142936819042
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.7137541528994728224393928562613829128941873058121535788635108693143720566914
Short name T919
Test name
Test status
Simulation time 17999183 ps
CPU time 1.16 seconds
Started Oct 29 02:08:53 PM PDT 23
Finished Oct 29 02:08:56 PM PDT 23
Peak memory 205864 kb
Host smart-4af46694-5fe5-4482-9ba8-295d5394c3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7137541528994728224393928562613829128941873058121535788635108693143720566914 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 163.edn_genbits.7137541528994728224393928562613829128941873058121535788635108693143720566914
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.18987681434091913590079367421771416791099334680262248534652349435288994522847
Short name T755
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Oct 29 02:08:39 PM PDT 23
Finished Oct 29 02:08:43 PM PDT 23
Peak memory 205712 kb
Host smart-030b0161-0212-4391-bc68-d91d9afd423f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18987681434091913590079367421771416791099334680262248534652349435288994522847 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 164.edn_genbits.18987681434091913590079367421771416791099334680262248534652349435288994522847
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.31697924222738001992704179629700668510212976696227523441883117400704920031264
Short name T272
Test name
Test status
Simulation time 17999183 ps
CPU time 1.15 seconds
Started Oct 29 02:08:38 PM PDT 23
Finished Oct 29 02:08:39 PM PDT 23
Peak memory 205800 kb
Host smart-ce6aea52-9f5c-469c-b289-9870ac096203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31697924222738001992704179629700668510212976696227523441883117400704920031264 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 165.edn_genbits.31697924222738001992704179629700668510212976696227523441883117400704920031264
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.83613366057987595930488904587534075891054215897593693607203919808628270918776
Short name T682
Test name
Test status
Simulation time 17999183 ps
CPU time 1.16 seconds
Started Oct 29 02:08:44 PM PDT 23
Finished Oct 29 02:08:46 PM PDT 23
Peak memory 205816 kb
Host smart-ae3402a6-e209-4df6-9622-05d1b36c9066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83613366057987595930488904587534075891054215897593693607203919808628270918776 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 166.edn_genbits.83613366057987595930488904587534075891054215897593693607203919808628270918776
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.47108346686199297012301620109282205948572079903959430559304651478192695196243
Short name T479
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Oct 29 02:09:47 PM PDT 23
Finished Oct 29 02:09:49 PM PDT 23
Peak memory 205824 kb
Host smart-205d42d3-54bb-4b15-97f3-bc0cba5a0923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47108346686199297012301620109282205948572079903959430559304651478192695196243 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 167.edn_genbits.47108346686199297012301620109282205948572079903959430559304651478192695196243
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.66629408309041621850253033381822278271010840271536183824935705297730061492763
Short name T376
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:09:21 PM PDT 23
Finished Oct 29 02:09:22 PM PDT 23
Peak memory 205840 kb
Host smart-fc12e2ee-f85a-43cd-ae28-47b9c9ecfe59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66629408309041621850253033381822278271010840271536183824935705297730061492763 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 168.edn_genbits.66629408309041621850253033381822278271010840271536183824935705297730061492763
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.8143517069354127143453587750630262569080599536739687722305953420920635049391
Short name T428
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Oct 29 02:09:46 PM PDT 23
Finished Oct 29 02:09:48 PM PDT 23
Peak memory 205832 kb
Host smart-36045992-6f85-4e3f-a22d-627cf17713c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8143517069354127143453587750630262569080599536739687722305953420920635049391 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 169.edn_genbits.8143517069354127143453587750630262569080599536739687722305953420920635049391
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.6513438563874651652795865231783667056112734782765364888304470109948689829257
Short name T921
Test name
Test status
Simulation time 18259183 ps
CPU time 0.96 seconds
Started Oct 29 02:07:30 PM PDT 23
Finished Oct 29 02:07:31 PM PDT 23
Peak memory 205560 kb
Host smart-d689162c-e202-4aea-b598-3aebd3c2374f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6513438563874651652795865231783667056112734782765364888304470109948689829257 -assert nopostproc +UVM_TESTNAME=edn_alert_
test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.edn_alert.6513438563874651652795865231783667056112734782765364888304470109948689829257
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.25898777565576517774014475554126581711544492291506653523038592395833353025374
Short name T452
Test name
Test status
Simulation time 28184990 ps
CPU time 0.89 seconds
Started Oct 29 02:07:34 PM PDT 23
Finished Oct 29 02:07:36 PM PDT 23
Peak memory 205484 kb
Host smart-7f130b51-93ab-4a66-be1c-218dfdc26b94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25898777565576517774014475554126581711544492291506653523038592395833353025374 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.edn_alert_test.25898777565576517774014475554126581711544492291506653523038592395833353025374
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.6832182122321794137411792559958539099368081180671428864986398382273536555003
Short name T510
Test name
Test status
Simulation time 12219183 ps
CPU time 0.84 seconds
Started Oct 29 02:07:04 PM PDT 23
Finished Oct 29 02:07:05 PM PDT 23
Peak memory 214872 kb
Host smart-ec51fa00-ebb2-4d9e-ae04-dfa9996cee74
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6832182122321794137411792559958539099368081180671428864986398382273536555003 -assert nopostproc
+UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.edn_disable.6832182122321794137411792559958539099368081180671428864986398382273536555003
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.2074995998326541970814819160681841977099456129685692550695130493286217492322
Short name T817
Test name
Test status
Simulation time 17319183 ps
CPU time 0.97 seconds
Started Oct 29 02:07:33 PM PDT 23
Finished Oct 29 02:07:34 PM PDT 23
Peak memory 214944 kb
Host smart-7f10aed5-38a3-44e6-b104-98ea9fd21a2e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074995998326541970814819160681841977099456129685692550695130493286217492322 -assert nopostproc
+UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable_auto_req_mode.20749959983265419708148191606818419770994561296856925506951
30493286217492322
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.115270864194889894597632045080218251435149442868154902994198566040140316519364
Short name T948
Test name
Test status
Simulation time 24963823 ps
CPU time 1.11 seconds
Started Oct 29 02:07:29 PM PDT 23
Finished Oct 29 02:07:31 PM PDT 23
Peak memory 230492 kb
Host smart-2792779d-e8f8-4b68-a320-80ae08b9174e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115270864194889894597632045080218251435149442868154902994198566040140316519364 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.edn_err.115270864194889894597632045080218251435149442868154902994198566040140316519364
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.44201854288133452636007976310284513964386815930724438277166642981076894445280
Short name T499
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Oct 29 02:07:28 PM PDT 23
Finished Oct 29 02:07:30 PM PDT 23
Peak memory 205736 kb
Host smart-e4e8e4b5-84f4-44d4-8abe-069a266a1b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44201854288133452636007976310284513964386815930724438277166642981076894445280 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.edn_genbits.44201854288133452636007976310284513964386815930724438277166642981076894445280
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.3420486035376488649319355988094380400256116019916477068743207625697036281867
Short name T646
Test name
Test status
Simulation time 18439183 ps
CPU time 1.15 seconds
Started Oct 29 02:08:00 PM PDT 23
Finished Oct 29 02:08:02 PM PDT 23
Peak memory 222260 kb
Host smart-37ee3061-71aa-4c4c-9218-41f57e7e3f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420486035376488649319355988094380400256116019916477068743207625697036281867 -assert nopostproc +UVM_TESTNAME=edn_intr_t
est +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.edn_intr.3420486035376488649319355988094380400256116019916477068743207625697036281867
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.1496795612446776593042755286189997771348885280833368992817237794784416429268
Short name T243
Test name
Test status
Simulation time 13059183 ps
CPU time 0.89 seconds
Started Oct 29 02:07:33 PM PDT 23
Finished Oct 29 02:07:35 PM PDT 23
Peak memory 205236 kb
Host smart-d91ab96d-4d6f-4e71-b4a8-875c9cd5bb4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496795612446776593042755286189997771348885280833368992817237794784416429268 -assert nopostproc +UVM_TESTNAME=edn_smoke_
test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.edn_smoke.1496795612446776593042755286189997771348885280833368992817237794784416429268
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.51244429367898113847128536581976642204156187109770589497927473448434601416348
Short name T967
Test name
Test status
Simulation time 154489183 ps
CPU time 4.05 seconds
Started Oct 29 02:07:33 PM PDT 23
Finished Oct 29 02:07:37 PM PDT 23
Peak memory 206360 kb
Host smart-87fd555e-1486-4622-89e2-507ae0c2d870
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51244429367898113847128536581976642204156187109770589497927473448434601416348 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.51244429367898113847128536581976642204156187109770589497927473448434601416348
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.36930799285177272583861714302572795394027865986185042112946573911977216517005
Short name T441
Test name
Test status
Simulation time 41708099183 ps
CPU time 1032.22 seconds
Started Oct 29 02:07:03 PM PDT 23
Finished Oct 29 02:24:17 PM PDT 23
Peak memory 215852 kb
Host smart-f88653c3-50e3-4663-8c27-42b16be43a4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369307992851772725838617143
02572795394027865986185042112946573911977216517005 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.36930799285
177272583861714302572795394027865986185042112946573911977216517005
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.110281541182804901742359562993661078876940982124412678538631340852227614193649
Short name T631
Test name
Test status
Simulation time 17999183 ps
CPU time 1.05 seconds
Started Oct 29 02:08:41 PM PDT 23
Finished Oct 29 02:08:43 PM PDT 23
Peak memory 205828 kb
Host smart-4b8ad91c-4a58-45cb-a81c-cd5b338d78a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110281541182804901742359562993661078876940982124412678538631340852227614193649 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 170.edn_genbits.110281541182804901742359562993661078876940982124412678538631340852227614193649
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.51339319712814355308526145590137082421490990461319613301007501771381006855301
Short name T568
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Oct 29 02:08:43 PM PDT 23
Finished Oct 29 02:08:45 PM PDT 23
Peak memory 205816 kb
Host smart-00a73d60-0757-47c6-91b5-dde68ebfa37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51339319712814355308526145590137082421490990461319613301007501771381006855301 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 171.edn_genbits.51339319712814355308526145590137082421490990461319613301007501771381006855301
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.92551001313740538346964758538469766315741818057517796304048434286574543173366
Short name T458
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Oct 29 02:08:48 PM PDT 23
Finished Oct 29 02:08:50 PM PDT 23
Peak memory 205820 kb
Host smart-b3cf3d72-ba78-4e6d-9b1d-6dc8614d2c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92551001313740538346964758538469766315741818057517796304048434286574543173366 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 172.edn_genbits.92551001313740538346964758538469766315741818057517796304048434286574543173366
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.85125067564510531497717571142282522755820821639560254496912595770344006900608
Short name T262
Test name
Test status
Simulation time 17999183 ps
CPU time 1.15 seconds
Started Oct 29 02:09:41 PM PDT 23
Finished Oct 29 02:09:42 PM PDT 23
Peak memory 205880 kb
Host smart-3141ec4e-2cf0-4f03-a815-95e76f28019f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85125067564510531497717571142282522755820821639560254496912595770344006900608 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 173.edn_genbits.85125067564510531497717571142282522755820821639560254496912595770344006900608
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.5280420019651058979702302687085645825406779561859063157573245268132656198101
Short name T251
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Oct 29 02:09:04 PM PDT 23
Finished Oct 29 02:09:06 PM PDT 23
Peak memory 205872 kb
Host smart-cd41cc03-e298-4f96-9bbf-01f90ef9e563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5280420019651058979702302687085645825406779561859063157573245268132656198101 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 174.edn_genbits.5280420019651058979702302687085645825406779561859063157573245268132656198101
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.57500668586967039134703628189553569843789846398578932674348380179136277069517
Short name T382
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Oct 29 02:08:36 PM PDT 23
Finished Oct 29 02:08:37 PM PDT 23
Peak memory 205880 kb
Host smart-15004fc3-9bd3-4556-bc0d-651def342aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57500668586967039134703628189553569843789846398578932674348380179136277069517 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 175.edn_genbits.57500668586967039134703628189553569843789846398578932674348380179136277069517
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.98396090405296755509784558431036075364527905472646616323710023934653024767864
Short name T448
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:08:50 PM PDT 23
Finished Oct 29 02:08:51 PM PDT 23
Peak memory 205844 kb
Host smart-3eebe533-8288-49a2-80b2-c15053739f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98396090405296755509784558431036075364527905472646616323710023934653024767864 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 176.edn_genbits.98396090405296755509784558431036075364527905472646616323710023934653024767864
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.26588137925216820885174409161796508266085502091730433255836580885296277816776
Short name T836
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Oct 29 02:08:47 PM PDT 23
Finished Oct 29 02:08:49 PM PDT 23
Peak memory 205812 kb
Host smart-968771ed-dfdd-45ca-8399-c7a74623877f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26588137925216820885174409161796508266085502091730433255836580885296277816776 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 177.edn_genbits.26588137925216820885174409161796508266085502091730433255836580885296277816776
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.108056987122178031848749762589471885494278271676249184491076080532544037418996
Short name T835
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Oct 29 02:09:02 PM PDT 23
Finished Oct 29 02:09:04 PM PDT 23
Peak memory 205828 kb
Host smart-994bbe4c-b50b-4d67-bb2f-cdba51e51c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108056987122178031848749762589471885494278271676249184491076080532544037418996 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 178.edn_genbits.108056987122178031848749762589471885494278271676249184491076080532544037418996
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.50619920226248844028346149386899976964559909111628964829066744444179371505288
Short name T256
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Oct 29 02:08:45 PM PDT 23
Finished Oct 29 02:08:47 PM PDT 23
Peak memory 205844 kb
Host smart-136f2db4-f483-49ff-86b2-7d0bd6465357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50619920226248844028346149386899976964559909111628964829066744444179371505288 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 179.edn_genbits.50619920226248844028346149386899976964559909111628964829066744444179371505288
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.63783831659002245321413696692766079121297218312720130188373679224442953346115
Short name T380
Test name
Test status
Simulation time 18259183 ps
CPU time 1 seconds
Started Oct 29 02:08:03 PM PDT 23
Finished Oct 29 02:08:05 PM PDT 23
Peak memory 205560 kb
Host smart-f61c7df2-09a0-4f0d-93b7-86096690507d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63783831659002245321413696692766079121297218312720130188373679224442953346115 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.edn_alert.63783831659002245321413696692766079121297218312720130188373679224442953346115
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.24758621186288701787051122162321253744901495151630203461834426947411020296777
Short name T816
Test name
Test status
Simulation time 28184990 ps
CPU time 0.86 seconds
Started Oct 29 02:06:58 PM PDT 23
Finished Oct 29 02:06:59 PM PDT 23
Peak memory 205504 kb
Host smart-35d9f0a7-e74f-4af0-a1ac-3d6da11619af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24758621186288701787051122162321253744901495151630203461834426947411020296777 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.edn_alert_test.24758621186288701787051122162321253744901495151630203461834426947411020296777
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.24500002999304228460042869972802142571475457310271232822041737751670332091262
Short name T67
Test name
Test status
Simulation time 12219183 ps
CPU time 0.87 seconds
Started Oct 29 02:07:27 PM PDT 23
Finished Oct 29 02:07:29 PM PDT 23
Peak memory 214936 kb
Host smart-8755b599-ddcd-4e4b-9ca3-5caba7fa04c8
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24500002999304228460042869972802142571475457310271232822041737751670332091262 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.edn_disable.24500002999304228460042869972802142571475457310271232822041737751670332091262
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.81350487516987316300401473914648376300924123002153607098348859261139304838750
Short name T931
Test name
Test status
Simulation time 17319183 ps
CPU time 0.94 seconds
Started Oct 29 02:07:03 PM PDT 23
Finished Oct 29 02:07:05 PM PDT 23
Peak memory 214896 kb
Host smart-1385031e-8ffd-4738-8f0f-3d0b7181dce9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81350487516987316300401473914648376300924123002153607098348859261139304838750 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable_auto_req_mode.8135048751698731630040147391464837630092412300215360709834
8859261139304838750
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.30667723655635977277165540810313148249653225371651313887763861266843089744041
Short name T951
Test name
Test status
Simulation time 24963823 ps
CPU time 1.19 seconds
Started Oct 29 02:07:01 PM PDT 23
Finished Oct 29 02:07:06 PM PDT 23
Peak memory 230324 kb
Host smart-1b61ebd4-5adb-4d96-8337-38938006632b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30667723655635977277165540810313148249653225371651313887763861266843089744041 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.edn_err.30667723655635977277165540810313148249653225371651313887763861266843089744041
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.20597856292085024223159109375426067824363453443444658490850040869766053883198
Short name T811
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Oct 29 02:07:58 PM PDT 23
Finished Oct 29 02:08:00 PM PDT 23
Peak memory 205844 kb
Host smart-41de4170-5301-49bd-8edd-d8114d8f4cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20597856292085024223159109375426067824363453443444658490850040869766053883198 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.edn_genbits.20597856292085024223159109375426067824363453443444658490850040869766053883198
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.42424606614442342771917222686762415213179465838533456751281030239650109793605
Short name T639
Test name
Test status
Simulation time 18439183 ps
CPU time 1.1 seconds
Started Oct 29 02:07:47 PM PDT 23
Finished Oct 29 02:07:48 PM PDT 23
Peak memory 222264 kb
Host smart-3f2dd09b-bfd1-4dd3-b7f5-d4c87d16815d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42424606614442342771917222686762415213179465838533456751281030239650109793605 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.edn_intr.42424606614442342771917222686762415213179465838533456751281030239650109793605
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.13169631383817183335378218095997131985430870091023738285240367154512330195220
Short name T470
Test name
Test status
Simulation time 13059183 ps
CPU time 0.89 seconds
Started Oct 29 02:07:39 PM PDT 23
Finished Oct 29 02:07:41 PM PDT 23
Peak memory 205376 kb
Host smart-26f4e438-1fff-4990-8abc-e5d5c2795b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13169631383817183335378218095997131985430870091023738285240367154512330195220 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.edn_smoke.13169631383817183335378218095997131985430870091023738285240367154512330195220
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.9656968083271356037011519328264703319634017545181969526982372241740132219906
Short name T275
Test name
Test status
Simulation time 154489183 ps
CPU time 3.73 seconds
Started Oct 29 02:08:59 PM PDT 23
Finished Oct 29 02:09:06 PM PDT 23
Peak memory 206388 kb
Host smart-633b9dfb-4285-41e9-9853-e3e388d77ffa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9656968083271356037011519328264703319634017545181969526982372241740132219906 -assert nopost
proc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.9656968083271356037011519328264703319634017545181969526982372241740132219906
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.41976937056819653357239519131325506091614634904303036281184976656352992437871
Short name T59
Test name
Test status
Simulation time 41708099183 ps
CPU time 1093.53 seconds
Started Oct 29 02:07:57 PM PDT 23
Finished Oct 29 02:26:11 PM PDT 23
Peak memory 215792 kb
Host smart-133a503b-31d7-4afb-8e98-9526fb6d7d03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419769370568196533572395191
31325506091614634904303036281184976656352992437871 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.41976937056
819653357239519131325506091614634904303036281184976656352992437871
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.5684205312474606248981203063050427194612523153002824126569222761508887022057
Short name T271
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Oct 29 02:08:44 PM PDT 23
Finished Oct 29 02:08:46 PM PDT 23
Peak memory 205828 kb
Host smart-2ca20f31-be13-4efd-b303-f127e96b27e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5684205312474606248981203063050427194612523153002824126569222761508887022057 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 180.edn_genbits.5684205312474606248981203063050427194612523153002824126569222761508887022057
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.15949574675806056432095822720658419528012235740116879862185890205415172233059
Short name T288
Test name
Test status
Simulation time 17999183 ps
CPU time 1.05 seconds
Started Oct 29 02:08:41 PM PDT 23
Finished Oct 29 02:08:43 PM PDT 23
Peak memory 205828 kb
Host smart-ea6c40bb-7151-4cca-9e4b-4d6b2687d6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15949574675806056432095822720658419528012235740116879862185890205415172233059 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 181.edn_genbits.15949574675806056432095822720658419528012235740116879862185890205415172233059
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.57334718370203558071654230967763856205710592574703051885879249089303136877428
Short name T952
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Oct 29 02:09:39 PM PDT 23
Finished Oct 29 02:09:41 PM PDT 23
Peak memory 205796 kb
Host smart-1f329f4a-087f-43c7-be2c-4c83511b785e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57334718370203558071654230967763856205710592574703051885879249089303136877428 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 182.edn_genbits.57334718370203558071654230967763856205710592574703051885879249089303136877428
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.83337427588544831818070417160827307733992467580039168202701121935442665641488
Short name T242
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Oct 29 02:08:47 PM PDT 23
Finished Oct 29 02:08:49 PM PDT 23
Peak memory 205812 kb
Host smart-cc79e841-b595-44c8-a73a-2c71e1afbcba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83337427588544831818070417160827307733992467580039168202701121935442665641488 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 183.edn_genbits.83337427588544831818070417160827307733992467580039168202701121935442665641488
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.103854742690142479614798001863150495757017808696350054254706797428987486497557
Short name T791
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:08:46 PM PDT 23
Finished Oct 29 02:08:48 PM PDT 23
Peak memory 205856 kb
Host smart-845d0bc1-dbf6-48c9-851e-f120e057ad16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103854742690142479614798001863150495757017808696350054254706797428987486497557 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 184.edn_genbits.103854742690142479614798001863150495757017808696350054254706797428987486497557
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.31187966120480948648819918935388809752937940776262166796270114779619578665227
Short name T753
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:08:43 PM PDT 23
Finished Oct 29 02:08:46 PM PDT 23
Peak memory 205836 kb
Host smart-46345733-7eea-4450-abb5-501d8b87160b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31187966120480948648819918935388809752937940776262166796270114779619578665227 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 185.edn_genbits.31187966120480948648819918935388809752937940776262166796270114779619578665227
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.113814612578408174233138877090906368696318384808102065188881069664486333609125
Short name T887
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Oct 29 02:09:46 PM PDT 23
Finished Oct 29 02:09:48 PM PDT 23
Peak memory 205912 kb
Host smart-7de7b946-bd06-409b-9a8f-dd496d6de79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113814612578408174233138877090906368696318384808102065188881069664486333609125 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 186.edn_genbits.113814612578408174233138877090906368696318384808102065188881069664486333609125
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.70779284044323405612763679666750554209778523144760120382365724660672961812378
Short name T656
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Oct 29 02:08:41 PM PDT 23
Finished Oct 29 02:08:43 PM PDT 23
Peak memory 205912 kb
Host smart-2bee8ff3-9249-4093-86d2-b19b99a1620c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70779284044323405612763679666750554209778523144760120382365724660672961812378 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 187.edn_genbits.70779284044323405612763679666750554209778523144760120382365724660672961812378
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.3468857341916424838339842822441105700709192364526527768699742944060540159427
Short name T611
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Oct 29 02:08:52 PM PDT 23
Finished Oct 29 02:08:56 PM PDT 23
Peak memory 205864 kb
Host smart-1c5a0642-e0a8-4b1f-a58e-022ac68fe17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468857341916424838339842822441105700709192364526527768699742944060540159427 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 188.edn_genbits.3468857341916424838339842822441105700709192364526527768699742944060540159427
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.554224288076370532571683836467973632397430827345915286404527180128088654493
Short name T550
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Oct 29 02:09:35 PM PDT 23
Finished Oct 29 02:09:36 PM PDT 23
Peak memory 205768 kb
Host smart-ec2dc348-1724-45df-97f5-9af9224af9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554224288076370532571683836467973632397430827345915286404527180128088654493 -assert nopostproc +UVM_TESTNAME=edn_genbits
_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 189.edn_genbits.554224288076370532571683836467973632397430827345915286404527180128088654493
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.76377676798872166431314302392798432792220238990152370359278252974096035613829
Short name T574
Test name
Test status
Simulation time 18259183 ps
CPU time 0.99 seconds
Started Oct 29 02:07:29 PM PDT 23
Finished Oct 29 02:07:30 PM PDT 23
Peak memory 205592 kb
Host smart-68d5aafb-27ba-439a-bbca-b160cd8e9ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76377676798872166431314302392798432792220238990152370359278252974096035613829 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.edn_alert.76377676798872166431314302392798432792220238990152370359278252974096035613829
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.113927146899754968297655136827206850359416267918564993367235466558959894185286
Short name T581
Test name
Test status
Simulation time 28184990 ps
CPU time 0.89 seconds
Started Oct 29 02:07:23 PM PDT 23
Finished Oct 29 02:07:25 PM PDT 23
Peak memory 205508 kb
Host smart-d1375590-42bb-4809-80ae-b66d883da6f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113927146899754968297655136827206850359416267918564993367235466558959894185286 -assert nopostp
roc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 19.edn_alert_test.113927146899754968297655136827206850359416267918564993367235466558959894185286
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.45779005505228608001125535195738493258323383361216761940427532219453681861779
Short name T666
Test name
Test status
Simulation time 12219183 ps
CPU time 0.88 seconds
Started Oct 29 02:07:05 PM PDT 23
Finished Oct 29 02:07:08 PM PDT 23
Peak memory 214888 kb
Host smart-5ca39d2a-19ac-4b91-bd92-cf2688228752
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45779005505228608001125535195738493258323383361216761940427532219453681861779 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.edn_disable.45779005505228608001125535195738493258323383361216761940427532219453681861779
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.37106733643650189602482160138915994969419194991757264384012852183427534987899
Short name T23
Test name
Test status
Simulation time 17319183 ps
CPU time 0.91 seconds
Started Oct 29 02:07:23 PM PDT 23
Finished Oct 29 02:07:25 PM PDT 23
Peak memory 214972 kb
Host smart-2247d73f-01dd-4ac7-bad3-724c9b57f466
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37106733643650189602482160138915994969419194991757264384012852183427534987899 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable_auto_req_mode.3710673364365018960248216013891599496941919499175726438401
2852183427534987899
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.78046197747123266619882563541569328418293264917263999034589284414933745154796
Short name T863
Test name
Test status
Simulation time 24963823 ps
CPU time 1.13 seconds
Started Oct 29 02:07:27 PM PDT 23
Finished Oct 29 02:07:29 PM PDT 23
Peak memory 230416 kb
Host smart-299fd6e4-0a29-4e57-bd7b-9e4c69f6717b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78046197747123266619882563541569328418293264917263999034589284414933745154796 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.edn_err.78046197747123266619882563541569328418293264917263999034589284414933745154796
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.36718218926715737804379432790480370865591672792798680516446578937806771371349
Short name T842
Test name
Test status
Simulation time 17999183 ps
CPU time 1.15 seconds
Started Oct 29 02:07:24 PM PDT 23
Finished Oct 29 02:07:26 PM PDT 23
Peak memory 205832 kb
Host smart-b3f2e440-feac-49b8-9a08-bcdbd9f133af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36718218926715737804379432790480370865591672792798680516446578937806771371349 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.edn_genbits.36718218926715737804379432790480370865591672792798680516446578937806771371349
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.17214792406508423825317555351353709156300052059733613963773524309228648484456
Short name T478
Test name
Test status
Simulation time 18439183 ps
CPU time 1.13 seconds
Started Oct 29 02:06:58 PM PDT 23
Finished Oct 29 02:07:00 PM PDT 23
Peak memory 222272 kb
Host smart-8d3bda11-1130-4186-8ca8-87df236c208c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17214792406508423825317555351353709156300052059733613963773524309228648484456 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.edn_intr.17214792406508423825317555351353709156300052059733613963773524309228648484456
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.75009448602341990653219094406310538817568444876782086229306516306088034406058
Short name T819
Test name
Test status
Simulation time 13059183 ps
CPU time 0.87 seconds
Started Oct 29 02:07:00 PM PDT 23
Finished Oct 29 02:07:05 PM PDT 23
Peak memory 205388 kb
Host smart-78d9d702-9847-4244-9626-0685b222e2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75009448602341990653219094406310538817568444876782086229306516306088034406058 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.edn_smoke.75009448602341990653219094406310538817568444876782086229306516306088034406058
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.10929926166462075538191278644985149219874746257608333272739813790983421567199
Short name T602
Test name
Test status
Simulation time 154489183 ps
CPU time 3.85 seconds
Started Oct 29 02:06:56 PM PDT 23
Finished Oct 29 02:07:00 PM PDT 23
Peak memory 206312 kb
Host smart-d425d734-454e-48f9-8da2-ce91eb317b42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10929926166462075538191278644985149219874746257608333272739813790983421567199 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.10929926166462075538191278644985149219874746257608333272739813790983421567199
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.69455355900669886401238249827492170073935747648416272954576258653127903672075
Short name T680
Test name
Test status
Simulation time 41708099183 ps
CPU time 1083.06 seconds
Started Oct 29 02:07:06 PM PDT 23
Finished Oct 29 02:25:11 PM PDT 23
Peak memory 215860 kb
Host smart-b11005d0-e394-4bcc-b6ae-4b2c1590353a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694553559006698864012382498
27492170073935747648416272954576258653127903672075 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.69455355900
669886401238249827492170073935747648416272954576258653127903672075
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.102131794593311149710954975744947932858218925236944655167991280277347857814389
Short name T507
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Oct 29 02:08:57 PM PDT 23
Finished Oct 29 02:08:59 PM PDT 23
Peak memory 205816 kb
Host smart-854a709b-e374-474f-9cff-3a76152b8ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102131794593311149710954975744947932858218925236944655167991280277347857814389 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 190.edn_genbits.102131794593311149710954975744947932858218925236944655167991280277347857814389
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.1900780951272849291408924780912797836851212548845361014156712603267231288145
Short name T662
Test name
Test status
Simulation time 17999183 ps
CPU time 1.22 seconds
Started Oct 29 02:08:50 PM PDT 23
Finished Oct 29 02:08:52 PM PDT 23
Peak memory 205996 kb
Host smart-fa532e2d-50b6-414b-82a7-3d00dba69497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900780951272849291408924780912797836851212548845361014156712603267231288145 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 191.edn_genbits.1900780951272849291408924780912797836851212548845361014156712603267231288145
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.69549222371735232174855610505881377706572308345082122491158183925147201601561
Short name T285
Test name
Test status
Simulation time 17999183 ps
CPU time 1.15 seconds
Started Oct 29 02:09:04 PM PDT 23
Finished Oct 29 02:09:06 PM PDT 23
Peak memory 205852 kb
Host smart-424e9870-7875-4b7e-8654-7745fc812a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69549222371735232174855610505881377706572308345082122491158183925147201601561 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 192.edn_genbits.69549222371735232174855610505881377706572308345082122491158183925147201601561
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.26141642952389512173555908991668244505735358534764148686804086919233119134723
Short name T900
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Oct 29 02:09:49 PM PDT 23
Finished Oct 29 02:09:50 PM PDT 23
Peak memory 205828 kb
Host smart-e5ca29d8-ed5a-414d-a236-5579fa77834d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26141642952389512173555908991668244505735358534764148686804086919233119134723 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 194.edn_genbits.26141642952389512173555908991668244505735358534764148686804086919233119134723
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.90277014653400371720244347763593363516140666555078834670181192207163646441270
Short name T845
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Oct 29 02:09:39 PM PDT 23
Finished Oct 29 02:09:40 PM PDT 23
Peak memory 205820 kb
Host smart-c099652d-a8b5-4128-a23a-70fe8cfeebca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90277014653400371720244347763593363516140666555078834670181192207163646441270 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 195.edn_genbits.90277014653400371720244347763593363516140666555078834670181192207163646441270
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.75956177814659600138668291276150363550548567923284229475834053784436626350199
Short name T684
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:09:50 PM PDT 23
Finished Oct 29 02:09:51 PM PDT 23
Peak memory 205828 kb
Host smart-fb55a7d4-97e2-477b-a22c-b046f1015728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75956177814659600138668291276150363550548567923284229475834053784436626350199 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 196.edn_genbits.75956177814659600138668291276150363550548567923284229475834053784436626350199
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.114572488211975189494169978025180098771319065945341559105863076405605981486143
Short name T365
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Oct 29 02:08:52 PM PDT 23
Finished Oct 29 02:08:56 PM PDT 23
Peak memory 205828 kb
Host smart-2d97107f-03bf-4be8-9f18-2e129d7f75fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114572488211975189494169978025180098771319065945341559105863076405605981486143 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 197.edn_genbits.114572488211975189494169978025180098771319065945341559105863076405605981486143
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.102537568388500277167541248136432485712786714570413308892541205496634375882012
Short name T578
Test name
Test status
Simulation time 17999183 ps
CPU time 1.16 seconds
Started Oct 29 02:10:27 PM PDT 23
Finished Oct 29 02:10:30 PM PDT 23
Peak memory 205792 kb
Host smart-79449f5b-0ab2-4c1b-bd7b-1fe1afd31d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102537568388500277167541248136432485712786714570413308892541205496634375882012 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 198.edn_genbits.102537568388500277167541248136432485712786714570413308892541205496634375882012
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.13441862599134490515164289672844960533045776201946881935948328100963023042518
Short name T810
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Oct 29 02:09:47 PM PDT 23
Finished Oct 29 02:09:49 PM PDT 23
Peak memory 205816 kb
Host smart-dfa90ddd-6ef6-4638-b0f7-16e1a39e7e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13441862599134490515164289672844960533045776201946881935948328100963023042518 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 199.edn_genbits.13441862599134490515164289672844960533045776201946881935948328100963023042518
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.33874814517392367543558699820903586092241235138795219905171394430364053328850
Short name T281
Test name
Test status
Simulation time 18259183 ps
CPU time 0.99 seconds
Started Oct 29 02:06:29 PM PDT 23
Finished Oct 29 02:06:31 PM PDT 23
Peak memory 205640 kb
Host smart-48dc283a-8cbc-43f2-80c4-11ce3586902d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33874814517392367543558699820903586092241235138795219905171394430364053328850 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.edn_alert.33874814517392367543558699820903586092241235138795219905171394430364053328850
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.8418176384717860091102469358531253247417853784506468595885878049738364925193
Short name T597
Test name
Test status
Simulation time 28184990 ps
CPU time 0.91 seconds
Started Oct 29 02:06:57 PM PDT 23
Finished Oct 29 02:06:58 PM PDT 23
Peak memory 205396 kb
Host smart-32dbaa58-36a4-4878-aada-934ec2cde7e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8418176384717860091102469358531253247417853784506468595885878049738364925193 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.edn_alert_test.8418176384717860091102469358531253247417853784506468595885878049738364925193
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.83643029351534353698734866127334612527050096584284414391718569984658894876562
Short name T65
Test name
Test status
Simulation time 12219183 ps
CPU time 0.87 seconds
Started Oct 29 02:06:19 PM PDT 23
Finished Oct 29 02:06:20 PM PDT 23
Peak memory 214820 kb
Host smart-21b9e2bd-5342-4c92-a44d-6c599ff995a7
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83643029351534353698734866127334612527050096584284414391718569984658894876562 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.edn_disable.83643029351534353698734866127334612527050096584284414391718569984658894876562
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.6259618063455849323279225597993282075565566557344609871404823636588577633924
Short name T609
Test name
Test status
Simulation time 17319183 ps
CPU time 0.95 seconds
Started Oct 29 02:06:32 PM PDT 23
Finished Oct 29 02:06:33 PM PDT 23
Peak memory 214796 kb
Host smart-657bb854-7f60-4031-a94e-5bc8976008b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6259618063455849323279225597993282075565566557344609871404823636588577633924 -assert nopostproc
+UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable_auto_req_mode.625961806345584932327922559799328207556556655734460987140482
3636588577633924
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.92842134374648953929150604196478973592320480020434419648844190082886068079816
Short name T924
Test name
Test status
Simulation time 24963823 ps
CPU time 1.15 seconds
Started Oct 29 02:06:57 PM PDT 23
Finished Oct 29 02:06:58 PM PDT 23
Peak memory 230424 kb
Host smart-af503832-c277-4c48-87b6-0a2a5ead43e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92842134374648953929150604196478973592320480020434419648844190082886068079816 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
edn_err.92842134374648953929150604196478973592320480020434419648844190082886068079816
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.95468638450234508118061655827522962242027049168921153656372964193811521556261
Short name T884
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Oct 29 02:06:54 PM PDT 23
Finished Oct 29 02:06:56 PM PDT 23
Peak memory 205860 kb
Host smart-37a25c4e-240e-4451-9bb8-84b7a6d44f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95468638450234508118061655827522962242027049168921153656372964193811521556261 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.edn_genbits.95468638450234508118061655827522962242027049168921153656372964193811521556261
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.4189122040257869040380582884641272586683952296450693298852369875789906904241
Short name T495
Test name
Test status
Simulation time 18439183 ps
CPU time 1.14 seconds
Started Oct 29 02:06:20 PM PDT 23
Finished Oct 29 02:06:22 PM PDT 23
Peak memory 222312 kb
Host smart-50a00465-262a-4af1-b360-70ed4d2e3c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189122040257869040380582884641272586683952296450693298852369875789906904241 -assert nopostproc +UVM_TESTNAME=edn_intr_t
est +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.edn_intr.4189122040257869040380582884641272586683952296450693298852369875789906904241
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_sec_cm.98987224995367346776640350014677642467563808477316232126967396145266229676664
Short name T29
Test name
Test status
Simulation time 717215632 ps
CPU time 6.07 seconds
Started Oct 29 02:06:58 PM PDT 23
Finished Oct 29 02:07:06 PM PDT 23
Peak memory 234008 kb
Host smart-95b2a94f-91e3-4d1b-9dc6-f90b70257ee9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98987224995367346776640350014677642467563808477316232126967396145266229676664 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.edn_sec_cm.98987224995367346776640350014677642467563808477316232126967396145266229676664
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.112270250650455572344094900137553054766976641813122838505623272969990954982378
Short name T373
Test name
Test status
Simulation time 13059183 ps
CPU time 0.86 seconds
Started Oct 29 02:06:57 PM PDT 23
Finished Oct 29 02:06:58 PM PDT 23
Peak memory 205352 kb
Host smart-8a65dc10-ae9d-453e-983a-3a323fcf2b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112270250650455572344094900137553054766976641813122838505623272969990954982378 -assert nopostproc +UVM_TESTNAME=edn_smok
e_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.edn_smoke.112270250650455572344094900137553054766976641813122838505623272969990954982378
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.84328056298093034524075067388430396907551732416819468913589481697129047349864
Short name T582
Test name
Test status
Simulation time 154489183 ps
CPU time 3.97 seconds
Started Oct 29 02:06:32 PM PDT 23
Finished Oct 29 02:06:36 PM PDT 23
Peak memory 206272 kb
Host smart-938ae878-fa37-47b0-8815-5fdff05754c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84328056298093034524075067388430396907551732416819468913589481697129047349864 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.84328056298093034524075067388430396907551732416819468913589481697129047349864
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.62852907802617059502575279932222595147424108039364175060523300992852172085938
Short name T737
Test name
Test status
Simulation time 41708099183 ps
CPU time 1093.93 seconds
Started Oct 29 02:06:18 PM PDT 23
Finished Oct 29 02:24:32 PM PDT 23
Peak memory 215896 kb
Host smart-b462b648-8ff4-46d6-b5dd-ae8b2243f7a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628529078026170595025752799
32222595147424108039364175060523300992852172085938 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.628529078026
17059502575279932222595147424108039364175060523300992852172085938
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.94231629765293653161360355474100795105839193675552758662905927674329847394857
Short name T846
Test name
Test status
Simulation time 18259183 ps
CPU time 0.99 seconds
Started Oct 29 02:06:58 PM PDT 23
Finished Oct 29 02:07:01 PM PDT 23
Peak memory 205552 kb
Host smart-100bd4e6-62a2-4e3f-9c7d-73c6d8fa2141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94231629765293653161360355474100795105839193675552758662905927674329847394857 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 20.edn_alert.94231629765293653161360355474100795105839193675552758662905927674329847394857
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.24723184939631314607966503891280687379205585158736726575518143738913259886420
Short name T329
Test name
Test status
Simulation time 28184990 ps
CPU time 0.95 seconds
Started Oct 29 02:07:24 PM PDT 23
Finished Oct 29 02:07:25 PM PDT 23
Peak memory 205428 kb
Host smart-67190d2c-7d4b-45c9-b6d3-68eddb90bf7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24723184939631314607966503891280687379205585158736726575518143738913259886420 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.edn_alert_test.24723184939631314607966503891280687379205585158736726575518143738913259886420
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.50834507142864605510466016820610883637102279443964036851229353748558160213957
Short name T731
Test name
Test status
Simulation time 12219183 ps
CPU time 0.87 seconds
Started Oct 29 02:07:01 PM PDT 23
Finished Oct 29 02:07:05 PM PDT 23
Peak memory 214828 kb
Host smart-418b5592-8d6a-4b89-80fd-e29534a29ed1
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50834507142864605510466016820610883637102279443964036851229353748558160213957 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.edn_disable.50834507142864605510466016820610883637102279443964036851229353748558160213957
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.86131822417232413447175986499765747198319410157416425552503049286254794983665
Short name T402
Test name
Test status
Simulation time 17319183 ps
CPU time 0.97 seconds
Started Oct 29 02:06:58 PM PDT 23
Finished Oct 29 02:07:01 PM PDT 23
Peak memory 214836 kb
Host smart-5c085896-5d83-4bd5-b2a1-efcf03838ede
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86131822417232413447175986499765747198319410157416425552503049286254794983665 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable_auto_req_mode.8613182241723241344717598649976574719831941015741642555250
3049286254794983665
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.100685722194532918345085091224304676182197684605891241572840608637904526102321
Short name T601
Test name
Test status
Simulation time 24963823 ps
CPU time 1.14 seconds
Started Oct 29 02:07:26 PM PDT 23
Finished Oct 29 02:07:29 PM PDT 23
Peak memory 230400 kb
Host smart-1f32d949-bb23-41ab-8a27-4a7f7c92d61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100685722194532918345085091224304676182197684605891241572840608637904526102321 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.edn_err.100685722194532918345085091224304676182197684605891241572840608637904526102321
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.60583528402566898086628159508939008603554526914097011974965267274846273060660
Short name T616
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Oct 29 02:07:28 PM PDT 23
Finished Oct 29 02:07:30 PM PDT 23
Peak memory 205876 kb
Host smart-6ce01af1-4a62-43ab-94ce-ff8053a39c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60583528402566898086628159508939008603554526914097011974965267274846273060660 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.edn_genbits.60583528402566898086628159508939008603554526914097011974965267274846273060660
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.80805524419299331654578843213139182394954536842701043754909545911947878363039
Short name T977
Test name
Test status
Simulation time 18439183 ps
CPU time 1.14 seconds
Started Oct 29 02:07:05 PM PDT 23
Finished Oct 29 02:07:09 PM PDT 23
Peak memory 222308 kb
Host smart-cf7a599d-a51b-48f9-872e-c0b0f243cc7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80805524419299331654578843213139182394954536842701043754909545911947878363039 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.edn_intr.80805524419299331654578843213139182394954536842701043754909545911947878363039
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.83573409483407538680846651385242854528461281183365353044222457129964116337952
Short name T922
Test name
Test status
Simulation time 13059183 ps
CPU time 0.93 seconds
Started Oct 29 02:07:29 PM PDT 23
Finished Oct 29 02:07:30 PM PDT 23
Peak memory 205388 kb
Host smart-b897fc8e-26c4-4f63-b45a-c073ea18259a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83573409483407538680846651385242854528461281183365353044222457129964116337952 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 20.edn_smoke.83573409483407538680846651385242854528461281183365353044222457129964116337952
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.15058220650377295414368797354333680531591178763421695854293894846494769043114
Short name T563
Test name
Test status
Simulation time 154489183 ps
CPU time 4.04 seconds
Started Oct 29 02:07:28 PM PDT 23
Finished Oct 29 02:07:33 PM PDT 23
Peak memory 206408 kb
Host smart-522ecfc2-803c-45af-97ee-0bc584ee2b05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15058220650377295414368797354333680531591178763421695854293894846494769043114 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.15058220650377295414368797354333680531591178763421695854293894846494769043114
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.80102098454015105770479854115937229726867826695810748300402943629523567071439
Short name T663
Test name
Test status
Simulation time 41708099183 ps
CPU time 1063.02 seconds
Started Oct 29 02:07:28 PM PDT 23
Finished Oct 29 02:25:11 PM PDT 23
Peak memory 215892 kb
Host smart-859cb4c8-6b56-479e-82d4-e1d5471181e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801020984540151057704798541
15937229726867826695810748300402943629523567071439 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.80102098454
015105770479854115937229726867826695810748300402943629523567071439
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.50291954248493494973038077237639497822974620403778735603444499348938787154553
Short name T558
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Oct 29 02:09:45 PM PDT 23
Finished Oct 29 02:09:47 PM PDT 23
Peak memory 205780 kb
Host smart-7bdc6536-24ef-4a96-8303-f8eac212beda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50291954248493494973038077237639497822974620403778735603444499348938787154553 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 200.edn_genbits.50291954248493494973038077237639497822974620403778735603444499348938787154553
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.37623451901952691324876998167505998830401717697956656954774472105822243675053
Short name T24
Test name
Test status
Simulation time 17999183 ps
CPU time 1.05 seconds
Started Oct 29 02:09:47 PM PDT 23
Finished Oct 29 02:09:49 PM PDT 23
Peak memory 205764 kb
Host smart-c5731fa9-56d8-4437-a5f8-5d0953c9dcbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37623451901952691324876998167505998830401717697956656954774472105822243675053 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 201.edn_genbits.37623451901952691324876998167505998830401717697956656954774472105822243675053
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.41766125652808596804177800436770064428731324816826055287646548738354282447714
Short name T42
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:09:51 PM PDT 23
Finished Oct 29 02:09:52 PM PDT 23
Peak memory 205896 kb
Host smart-bd03f58e-bcfe-49c0-bd3b-7484a4b8bcee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41766125652808596804177800436770064428731324816826055287646548738354282447714 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 202.edn_genbits.41766125652808596804177800436770064428731324816826055287646548738354282447714
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.48785707987416046335238454381756863448637802421735022851194657571743627449502
Short name T723
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:10:35 PM PDT 23
Finished Oct 29 02:10:37 PM PDT 23
Peak memory 205828 kb
Host smart-a4b5487f-bd99-49b4-8cb7-46ce2feca6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48785707987416046335238454381756863448637802421735022851194657571743627449502 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 203.edn_genbits.48785707987416046335238454381756863448637802421735022851194657571743627449502
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.48154396469895318438633861735853965873495265311536712883333316361766470219010
Short name T709
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Oct 29 02:09:52 PM PDT 23
Finished Oct 29 02:09:53 PM PDT 23
Peak memory 205908 kb
Host smart-cb39607e-a355-4c8a-8394-b665e9d3a7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48154396469895318438633861735853965873495265311536712883333316361766470219010 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 204.edn_genbits.48154396469895318438633861735853965873495265311536712883333316361766470219010
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.11473073907730833621832585484986774977478325884364790578673364454071994745787
Short name T491
Test name
Test status
Simulation time 17999183 ps
CPU time 1.16 seconds
Started Oct 29 02:09:56 PM PDT 23
Finished Oct 29 02:09:57 PM PDT 23
Peak memory 205792 kb
Host smart-780e2ddf-112c-4bf6-ade0-6000ab12dbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11473073907730833621832585484986774977478325884364790578673364454071994745787 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 205.edn_genbits.11473073907730833621832585484986774977478325884364790578673364454071994745787
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.112050179602976585747620567792663507226419011312953036763807446131468356049377
Short name T930
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:10:27 PM PDT 23
Finished Oct 29 02:10:28 PM PDT 23
Peak memory 205764 kb
Host smart-6b868e06-4f5f-4aa9-94fa-53e3ecd00d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112050179602976585747620567792663507226419011312953036763807446131468356049377 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 206.edn_genbits.112050179602976585747620567792663507226419011312953036763807446131468356049377
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.37259225196234984803874347510486544037173494476792614727016925340120726179681
Short name T248
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Oct 29 02:10:03 PM PDT 23
Finished Oct 29 02:10:04 PM PDT 23
Peak memory 205808 kb
Host smart-7efa08fb-9d6f-4ff6-8946-35c0c204cbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37259225196234984803874347510486544037173494476792614727016925340120726179681 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 207.edn_genbits.37259225196234984803874347510486544037173494476792614727016925340120726179681
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.61733336179178658854631959081004399604640016574092381387005664182844240979985
Short name T712
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:10:11 PM PDT 23
Finished Oct 29 02:10:12 PM PDT 23
Peak memory 205808 kb
Host smart-b3eaac34-380b-44ce-871c-8257e69af5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61733336179178658854631959081004399604640016574092381387005664182844240979985 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 208.edn_genbits.61733336179178658854631959081004399604640016574092381387005664182844240979985
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.80842764738708816085300848993633442740617306393936879337040736797812127864757
Short name T320
Test name
Test status
Simulation time 17999183 ps
CPU time 1.15 seconds
Started Oct 29 02:10:35 PM PDT 23
Finished Oct 29 02:10:37 PM PDT 23
Peak memory 205852 kb
Host smart-2891392d-3bd0-4333-900d-0a08b4756f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80842764738708816085300848993633442740617306393936879337040736797812127864757 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 209.edn_genbits.80842764738708816085300848993633442740617306393936879337040736797812127864757
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.84432161040846583155045508818968109289983341482395016879580371688884453210467
Short name T736
Test name
Test status
Simulation time 18259183 ps
CPU time 0.96 seconds
Started Oct 29 02:07:06 PM PDT 23
Finished Oct 29 02:07:09 PM PDT 23
Peak memory 205468 kb
Host smart-9425780f-13db-469d-81cc-d62e37769700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84432161040846583155045508818968109289983341482395016879580371688884453210467 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 21.edn_alert.84432161040846583155045508818968109289983341482395016879580371688884453210467
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.106286779380911865812210086621399688410171837214387249803725862004209382582056
Short name T293
Test name
Test status
Simulation time 28184990 ps
CPU time 0.9 seconds
Started Oct 29 02:08:05 PM PDT 23
Finished Oct 29 02:08:06 PM PDT 23
Peak memory 205492 kb
Host smart-3341b482-0611-44fc-b9b9-0670427bca13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106286779380911865812210086621399688410171837214387249803725862004209382582056 -assert nopostp
roc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 21.edn_alert_test.106286779380911865812210086621399688410171837214387249803725862004209382582056
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.40097669158179317621961916746043077212392081462067794954856067715868039290596
Short name T960
Test name
Test status
Simulation time 12219183 ps
CPU time 0.83 seconds
Started Oct 29 02:07:32 PM PDT 23
Finished Oct 29 02:07:34 PM PDT 23
Peak memory 214688 kb
Host smart-4eabff15-011b-45e5-8377-e1327ccb42e1
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40097669158179317621961916746043077212392081462067794954856067715868039290596 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.edn_disable.40097669158179317621961916746043077212392081462067794954856067715868039290596
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.101642134033297587134152919250786790194253603140140002105408609162315440861046
Short name T905
Test name
Test status
Simulation time 17319183 ps
CPU time 0.93 seconds
Started Oct 29 02:07:03 PM PDT 23
Finished Oct 29 02:07:05 PM PDT 23
Peak memory 214924 kb
Host smart-fde5cb96-1c5d-4abc-9fc9-73f517cc2a62
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101642134033297587134152919250786790194253603140140002105408609162315440861046 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable_auto_req_mode.101642134033297587134152919250786790194253603140140002105
408609162315440861046
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.98342840794647615140054449310549945006417056357018329874566830474019646545446
Short name T720
Test name
Test status
Simulation time 24963823 ps
CPU time 1.1 seconds
Started Oct 29 02:07:06 PM PDT 23
Finished Oct 29 02:07:09 PM PDT 23
Peak memory 230372 kb
Host smart-52095010-653b-43e6-8b78-6cc9140df7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98342840794647615140054449310549945006417056357018329874566830474019646545446 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.edn_err.98342840794647615140054449310549945006417056357018329874566830474019646545446
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.81657031484588859938592349534929185310387730377793480134618186910424722223545
Short name T274
Test name
Test status
Simulation time 17999183 ps
CPU time 1.06 seconds
Started Oct 29 02:07:27 PM PDT 23
Finished Oct 29 02:07:29 PM PDT 23
Peak memory 205808 kb
Host smart-47d203ed-bba2-41fc-9c0a-147907cedd0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81657031484588859938592349534929185310387730377793480134618186910424722223545 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.edn_genbits.81657031484588859938592349534929185310387730377793480134618186910424722223545
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.274101102453728027906915162031400178446142529955456079138280302634124013226
Short name T16
Test name
Test status
Simulation time 18439183 ps
CPU time 1.1 seconds
Started Oct 29 02:07:39 PM PDT 23
Finished Oct 29 02:07:40 PM PDT 23
Peak memory 222260 kb
Host smart-35d41bf0-d163-435c-a3ff-e7192bf74fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274101102453728027906915162031400178446142529955456079138280302634124013226 -assert nopostproc +UVM_TESTNAME=edn_intr_te
st +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.edn_intr.274101102453728027906915162031400178446142529955456079138280302634124013226
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.81466559660858995257228567560487444474264266728672823462880721534954434547175
Short name T327
Test name
Test status
Simulation time 13059183 ps
CPU time 0.85 seconds
Started Oct 29 02:07:04 PM PDT 23
Finished Oct 29 02:07:05 PM PDT 23
Peak memory 205300 kb
Host smart-274e7d89-e473-476c-8c64-40e8520ba7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81466559660858995257228567560487444474264266728672823462880721534954434547175 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 21.edn_smoke.81466559660858995257228567560487444474264266728672823462880721534954434547175
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.50468737664164917566837474264766936407206776208449407260812880222698797973814
Short name T913
Test name
Test status
Simulation time 154489183 ps
CPU time 4.35 seconds
Started Oct 29 02:07:03 PM PDT 23
Finished Oct 29 02:07:09 PM PDT 23
Peak memory 206288 kb
Host smart-886f6a29-59c2-4bd1-8355-02a61ad83665
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50468737664164917566837474264766936407206776208449407260812880222698797973814 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.50468737664164917566837474264766936407206776208449407260812880222698797973814
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.35024968198911435370191269302707781103253473451294197401791319985018784757076
Short name T761
Test name
Test status
Simulation time 41708099183 ps
CPU time 1006.28 seconds
Started Oct 29 02:07:32 PM PDT 23
Finished Oct 29 02:24:19 PM PDT 23
Peak memory 215844 kb
Host smart-97b48c35-d8d6-49c0-abfd-8ee8a295e585
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350249681989114353701912693
02707781103253473451294197401791319985018784757076 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.35024968198
911435370191269302707781103253473451294197401791319985018784757076
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.18376583655468036835306927547093969038256038245600509066037846551652400696898
Short name T518
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:10:52 PM PDT 23
Finished Oct 29 02:10:54 PM PDT 23
Peak memory 205844 kb
Host smart-93e4a830-07fd-404b-abfc-f469785233e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18376583655468036835306927547093969038256038245600509066037846551652400696898 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 210.edn_genbits.18376583655468036835306927547093969038256038245600509066037846551652400696898
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.23567336631830053727767562525919693235225195693577171731092507435934103439989
Short name T487
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:10:06 PM PDT 23
Finished Oct 29 02:10:07 PM PDT 23
Peak memory 205844 kb
Host smart-d165d93a-be8b-4159-81ad-243f046e4944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23567336631830053727767562525919693235225195693577171731092507435934103439989 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 211.edn_genbits.23567336631830053727767562525919693235225195693577171731092507435934103439989
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.42201896444192301243824763167843263242125007788264148718768153771446093791885
Short name T596
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Oct 29 02:10:20 PM PDT 23
Finished Oct 29 02:10:22 PM PDT 23
Peak memory 205840 kb
Host smart-60d9a437-bf4f-4648-af14-3eecdc169115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42201896444192301243824763167843263242125007788264148718768153771446093791885 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 212.edn_genbits.42201896444192301243824763167843263242125007788264148718768153771446093791885
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.10072484811769106373857655779405390543429783963955886399748325838924952096801
Short name T595
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Oct 29 02:10:09 PM PDT 23
Finished Oct 29 02:10:10 PM PDT 23
Peak memory 205816 kb
Host smart-0278609b-ea62-48e2-99fe-190cbefd29b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10072484811769106373857655779405390543429783963955886399748325838924952096801 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 213.edn_genbits.10072484811769106373857655779405390543429783963955886399748325838924952096801
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.60472487270831760526078319288805212865682739465091708097249013857069011922747
Short name T484
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Oct 29 02:10:10 PM PDT 23
Finished Oct 29 02:10:12 PM PDT 23
Peak memory 205808 kb
Host smart-ae6f83b2-7bc8-483a-8d12-5afb94080f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60472487270831760526078319288805212865682739465091708097249013857069011922747 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 214.edn_genbits.60472487270831760526078319288805212865682739465091708097249013857069011922747
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.78949862966257815173099937877563088791753052841074858740273744615777509560152
Short name T619
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Oct 29 02:10:39 PM PDT 23
Finished Oct 29 02:10:40 PM PDT 23
Peak memory 205856 kb
Host smart-a3beb2a9-2427-4e8f-b497-ae0a0f33713f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78949862966257815173099937877563088791753052841074858740273744615777509560152 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 215.edn_genbits.78949862966257815173099937877563088791753052841074858740273744615777509560152
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.102746640464568827524693788327229743531820441104711058129669846734412975523906
Short name T909
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Oct 29 02:10:44 PM PDT 23
Finished Oct 29 02:10:46 PM PDT 23
Peak memory 205828 kb
Host smart-2281016e-1ac2-478e-b3db-81eb03df6d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102746640464568827524693788327229743531820441104711058129669846734412975523906 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 216.edn_genbits.102746640464568827524693788327229743531820441104711058129669846734412975523906
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.74142851214064660734994186271928068740047685342808976094485887492035751509280
Short name T772
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Oct 29 02:10:46 PM PDT 23
Finished Oct 29 02:10:48 PM PDT 23
Peak memory 205752 kb
Host smart-a13da1e0-577e-4b8d-a175-79d3ec3e4cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74142851214064660734994186271928068740047685342808976094485887492035751509280 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 217.edn_genbits.74142851214064660734994186271928068740047685342808976094485887492035751509280
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.54508200470140257687416256837766138049206011641555915864768731910478242644831
Short name T436
Test name
Test status
Simulation time 17999183 ps
CPU time 1.15 seconds
Started Oct 29 02:10:37 PM PDT 23
Finished Oct 29 02:10:40 PM PDT 23
Peak memory 205808 kb
Host smart-f4c5eb15-c631-4c12-b154-b3d8e1f452f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54508200470140257687416256837766138049206011641555915864768731910478242644831 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 218.edn_genbits.54508200470140257687416256837766138049206011641555915864768731910478242644831
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.52124243134304319379917988967272462106085248195452134436235575505336843837853
Short name T477
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Oct 29 02:10:50 PM PDT 23
Finished Oct 29 02:10:51 PM PDT 23
Peak memory 205852 kb
Host smart-f58587a0-36ad-43e9-b573-2f0f3b1f07b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52124243134304319379917988967272462106085248195452134436235575505336843837853 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 219.edn_genbits.52124243134304319379917988967272462106085248195452134436235575505336843837853
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.16264671011075912432465479779594915332011914455548066905775497388171457474005
Short name T634
Test name
Test status
Simulation time 18259183 ps
CPU time 0.94 seconds
Started Oct 29 02:08:29 PM PDT 23
Finished Oct 29 02:08:31 PM PDT 23
Peak memory 205588 kb
Host smart-8ffc0fc4-42d1-4cb6-95b2-25c6e8d19d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16264671011075912432465479779594915332011914455548066905775497388171457474005 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 22.edn_alert.16264671011075912432465479779594915332011914455548066905775497388171457474005
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.18167371264612208734702155058682820962934712398683314465598988348070967616374
Short name T946
Test name
Test status
Simulation time 28184990 ps
CPU time 0.93 seconds
Started Oct 29 02:08:37 PM PDT 23
Finished Oct 29 02:08:38 PM PDT 23
Peak memory 205568 kb
Host smart-4cf768d2-dcbc-4724-9953-822cc7d720fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18167371264612208734702155058682820962934712398683314465598988348070967616374 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.edn_alert_test.18167371264612208734702155058682820962934712398683314465598988348070967616374
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.66903518340846650962929018684377352094957087842136530957896220684668272126129
Short name T783
Test name
Test status
Simulation time 12219183 ps
CPU time 0.87 seconds
Started Oct 29 02:07:59 PM PDT 23
Finished Oct 29 02:08:00 PM PDT 23
Peak memory 214880 kb
Host smart-2afd82bf-7e81-4851-818b-9f3edb183820
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66903518340846650962929018684377352094957087842136530957896220684668272126129 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.edn_disable.66903518340846650962929018684377352094957087842136530957896220684668272126129
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.1443331007016610652489345988692039916347554027122315029830338450549339783405
Short name T336
Test name
Test status
Simulation time 17319183 ps
CPU time 0.98 seconds
Started Oct 29 02:08:05 PM PDT 23
Finished Oct 29 02:08:07 PM PDT 23
Peak memory 214912 kb
Host smart-802e5e42-0b07-49e2-a277-0aecc698a310
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443331007016610652489345988692039916347554027122315029830338450549339783405 -assert nopostproc
+UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable_auto_req_mode.14433310070166106524893459886920399163475540271223150298303
38450549339783405
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.35705504805131739436929213611991478988848591350854602634073134432296112144381
Short name T416
Test name
Test status
Simulation time 24963823 ps
CPU time 1.14 seconds
Started Oct 29 02:08:04 PM PDT 23
Finished Oct 29 02:08:06 PM PDT 23
Peak memory 230340 kb
Host smart-26755d2b-eaa4-4e55-9c26-bd56cd039518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35705504805131739436929213611991478988848591350854602634073134432296112144381 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.edn_err.35705504805131739436929213611991478988848591350854602634073134432296112144381
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.98045062112957911406230907452312930191623820020825795296265446825131658722690
Short name T962
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Oct 29 02:08:41 PM PDT 23
Finished Oct 29 02:08:43 PM PDT 23
Peak memory 205900 kb
Host smart-af306fe3-f252-46a0-af4e-f00b1e839a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98045062112957911406230907452312930191623820020825795296265446825131658722690 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.edn_genbits.98045062112957911406230907452312930191623820020825795296265446825131658722690
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.115030209524801406031819715277941708548193347998995410572460406597555961513103
Short name T398
Test name
Test status
Simulation time 18439183 ps
CPU time 1.17 seconds
Started Oct 29 02:08:03 PM PDT 23
Finished Oct 29 02:08:04 PM PDT 23
Peak memory 222268 kb
Host smart-2389c491-35ab-41a7-8cf6-0c1a38653c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115030209524801406031819715277941708548193347998995410572460406597555961513103 -assert nopostproc +UVM_TESTNAME=edn_intr
_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.edn_intr.115030209524801406031819715277941708548193347998995410572460406597555961513103
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.76910992082599749055083670235090773857962314016952525942109617276206123440015
Short name T851
Test name
Test status
Simulation time 13059183 ps
CPU time 0.88 seconds
Started Oct 29 02:07:37 PM PDT 23
Finished Oct 29 02:07:39 PM PDT 23
Peak memory 205344 kb
Host smart-71f2dcd7-2a63-40c8-ab6f-f366e417d5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76910992082599749055083670235090773857962314016952525942109617276206123440015 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 22.edn_smoke.76910992082599749055083670235090773857962314016952525942109617276206123440015
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.66332386088215468251627049095785719089660461858230594798513539916234485927917
Short name T73
Test name
Test status
Simulation time 154489183 ps
CPU time 4.05 seconds
Started Oct 29 02:07:45 PM PDT 23
Finished Oct 29 02:07:49 PM PDT 23
Peak memory 206384 kb
Host smart-34e4587e-4afd-4596-a670-d68689fa3039
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66332386088215468251627049095785719089660461858230594798513539916234485927917 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.66332386088215468251627049095785719089660461858230594798513539916234485927917
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.3178376672243997447387401202076725538009797597077475561809600125220300507891
Short name T405
Test name
Test status
Simulation time 41708099183 ps
CPU time 1067.49 seconds
Started Oct 29 02:08:04 PM PDT 23
Finished Oct 29 02:25:52 PM PDT 23
Peak memory 215864 kb
Host smart-2a48ddb2-d6bb-4297-b632-fdcb890ea2dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317837667224399744738740120
2076725538009797597077475561809600125220300507891 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.317837667224
3997447387401202076725538009797597077475561809600125220300507891
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.37303616741630752756086785304127224102034787488894542191639222586679234207370
Short name T706
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Oct 29 02:10:51 PM PDT 23
Finished Oct 29 02:10:52 PM PDT 23
Peak memory 205748 kb
Host smart-202be888-e762-44ac-bd6f-3bcff39545a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37303616741630752756086785304127224102034787488894542191639222586679234207370 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 220.edn_genbits.37303616741630752756086785304127224102034787488894542191639222586679234207370
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.23863567236614265347254096258906301618163344595652954770576275404772299211976
Short name T337
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Oct 29 02:10:46 PM PDT 23
Finished Oct 29 02:10:47 PM PDT 23
Peak memory 205856 kb
Host smart-82af97a3-3d50-4b0c-8c8f-28aa06528956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23863567236614265347254096258906301618163344595652954770576275404772299211976 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 221.edn_genbits.23863567236614265347254096258906301618163344595652954770576275404772299211976
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.110667677071239735681178357623215261276879818039089356102543835122393556215270
Short name T426
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Oct 29 02:10:52 PM PDT 23
Finished Oct 29 02:10:53 PM PDT 23
Peak memory 205844 kb
Host smart-79dc6071-78c9-40c3-9a3a-c0b567b931a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110667677071239735681178357623215261276879818039089356102543835122393556215270 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 222.edn_genbits.110667677071239735681178357623215261276879818039089356102543835122393556215270
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.76289001859360908215762133686275261508729269893234764265937805613733099272788
Short name T691
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Oct 29 02:10:34 PM PDT 23
Finished Oct 29 02:10:36 PM PDT 23
Peak memory 205840 kb
Host smart-cd0cbc9e-c476-4f9d-9740-e4991a8b2cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76289001859360908215762133686275261508729269893234764265937805613733099272788 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 223.edn_genbits.76289001859360908215762133686275261508729269893234764265937805613733099272788
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.79968158368208352747759811678398931878079896352914155854802344837343170967209
Short name T882
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Oct 29 02:09:44 PM PDT 23
Finished Oct 29 02:09:45 PM PDT 23
Peak memory 205712 kb
Host smart-5e2e9b96-3a78-49de-ae81-79c4bba240f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79968158368208352747759811678398931878079896352914155854802344837343170967209 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 224.edn_genbits.79968158368208352747759811678398931878079896352914155854802344837343170967209
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.66772685572872376815466948331369495047494590507670455816615694419783232774375
Short name T671
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:09:49 PM PDT 23
Finished Oct 29 02:09:51 PM PDT 23
Peak memory 205816 kb
Host smart-1bc2784c-8f16-48a1-8868-f4e7f807ba2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66772685572872376815466948331369495047494590507670455816615694419783232774375 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 225.edn_genbits.66772685572872376815466948331369495047494590507670455816615694419783232774375
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.74012107392515294923272129978260796269840771582220314897761325691940638316689
Short name T760
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Oct 29 02:09:01 PM PDT 23
Finished Oct 29 02:09:04 PM PDT 23
Peak memory 205840 kb
Host smart-3584c7f1-3ea1-4894-bb88-ff8492532817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74012107392515294923272129978260796269840771582220314897761325691940638316689 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 226.edn_genbits.74012107392515294923272129978260796269840771582220314897761325691940638316689
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.38021135354178641117123555957409509659835900850701446442888958418667582272835
Short name T338
Test name
Test status
Simulation time 17999183 ps
CPU time 1.06 seconds
Started Oct 29 02:08:42 PM PDT 23
Finished Oct 29 02:08:45 PM PDT 23
Peak memory 205808 kb
Host smart-fb4ca9e8-f647-4fa1-b454-0782f9ecff8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38021135354178641117123555957409509659835900850701446442888958418667582272835 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 227.edn_genbits.38021135354178641117123555957409509659835900850701446442888958418667582272835
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.62646849672480272965112743621280216526348908701290873184354936752238958090183
Short name T775
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Oct 29 02:09:03 PM PDT 23
Finished Oct 29 02:09:04 PM PDT 23
Peak memory 205860 kb
Host smart-a716d8b4-e217-4817-9593-9e83116200ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62646849672480272965112743621280216526348908701290873184354936752238958090183 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 228.edn_genbits.62646849672480272965112743621280216526348908701290873184354936752238958090183
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.79157761200251968153180343312555689250260113830408222001510522167935044932409
Short name T497
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Oct 29 02:08:50 PM PDT 23
Finished Oct 29 02:08:51 PM PDT 23
Peak memory 205844 kb
Host smart-47c19f9b-6bce-429b-8f2f-97babf8d20ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79157761200251968153180343312555689250260113830408222001510522167935044932409 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 229.edn_genbits.79157761200251968153180343312555689250260113830408222001510522167935044932409
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.75381850019419751218888994861659405673398043205405360136033878825342964832212
Short name T296
Test name
Test status
Simulation time 18259183 ps
CPU time 0.98 seconds
Started Oct 29 02:07:28 PM PDT 23
Finished Oct 29 02:07:29 PM PDT 23
Peak memory 205528 kb
Host smart-1d951751-a398-4115-8833-7f173927f76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75381850019419751218888994861659405673398043205405360136033878825342964832212 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 23.edn_alert.75381850019419751218888994861659405673398043205405360136033878825342964832212
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.18149339592942491250336981876269599541481065022874754515958299080578037974194
Short name T576
Test name
Test status
Simulation time 28184990 ps
CPU time 0.82 seconds
Started Oct 29 02:09:41 PM PDT 23
Finished Oct 29 02:09:42 PM PDT 23
Peak memory 205504 kb
Host smart-b8f6503c-9850-4df3-87a2-813d35a04ea4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18149339592942491250336981876269599541481065022874754515958299080578037974194 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.edn_alert_test.18149339592942491250336981876269599541481065022874754515958299080578037974194
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.61678514980872167258389898567309634710331064475510119702395042273060228429348
Short name T638
Test name
Test status
Simulation time 12219183 ps
CPU time 0.86 seconds
Started Oct 29 02:08:36 PM PDT 23
Finished Oct 29 02:08:37 PM PDT 23
Peak memory 214832 kb
Host smart-82faab0d-3620-4a68-98dc-e78c69d2efb8
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61678514980872167258389898567309634710331064475510119702395042273060228429348 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.edn_disable.61678514980872167258389898567309634710331064475510119702395042273060228429348
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.79256035907408066214997697829394336617470795566261460396472730943145279180227
Short name T340
Test name
Test status
Simulation time 17319183 ps
CPU time 0.9 seconds
Started Oct 29 02:08:57 PM PDT 23
Finished Oct 29 02:09:03 PM PDT 23
Peak memory 214792 kb
Host smart-ae673555-57c2-4c26-abe6-44a7650854ce
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79256035907408066214997697829394336617470795566261460396472730943145279180227 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable_auto_req_mode.7925603590740806621499769782939433661747079556626146039647
2730943145279180227
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.47632451308304515885146451264675545249923172411758481891221182030036885858424
Short name T387
Test name
Test status
Simulation time 24963823 ps
CPU time 1.1 seconds
Started Oct 29 02:08:40 PM PDT 23
Finished Oct 29 02:08:43 PM PDT 23
Peak memory 230460 kb
Host smart-9bde0fd2-909d-40f8-87cf-3e7750f7d269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47632451308304515885146451264675545249923172411758481891221182030036885858424 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.edn_err.47632451308304515885146451264675545249923172411758481891221182030036885858424
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.110252973689803017492976879922702610047306389312671755678207034802974659044348
Short name T859
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Oct 29 02:09:39 PM PDT 23
Finished Oct 29 02:09:41 PM PDT 23
Peak memory 205932 kb
Host smart-b5047766-6075-4b9a-b484-9b9b921d8f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110252973689803017492976879922702610047306389312671755678207034802974659044348 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 23.edn_genbits.110252973689803017492976879922702610047306389312671755678207034802974659044348
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.2954454714754405112916619664467399033026744894470963712077515117114858879387
Short name T739
Test name
Test status
Simulation time 18439183 ps
CPU time 1.14 seconds
Started Oct 29 02:09:04 PM PDT 23
Finished Oct 29 02:09:06 PM PDT 23
Peak memory 222320 kb
Host smart-a8d97917-6a90-48aa-8add-aa13771890ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954454714754405112916619664467399033026744894470963712077515117114858879387 -assert nopostproc +UVM_TESTNAME=edn_intr_t
est +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.edn_intr.2954454714754405112916619664467399033026744894470963712077515117114858879387
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.11748755459284399789576532413766814095405081720998691869486060821488977196121
Short name T241
Test name
Test status
Simulation time 13059183 ps
CPU time 0.87 seconds
Started Oct 29 02:08:34 PM PDT 23
Finished Oct 29 02:08:35 PM PDT 23
Peak memory 205384 kb
Host smart-ecfe550d-e007-41bb-941e-6a238551b18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11748755459284399789576532413766814095405081720998691869486060821488977196121 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 23.edn_smoke.11748755459284399789576532413766814095405081720998691869486060821488977196121
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.16831065860942545986909665117039723199874738315789648402455867054160652517358
Short name T604
Test name
Test status
Simulation time 154489183 ps
CPU time 4.04 seconds
Started Oct 29 02:08:09 PM PDT 23
Finished Oct 29 02:08:14 PM PDT 23
Peak memory 206324 kb
Host smart-0f6ab400-03d6-4c6b-8cbf-8635a640e002
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16831065860942545986909665117039723199874738315789648402455867054160652517358 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.16831065860942545986909665117039723199874738315789648402455867054160652517358
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.88025986973565229123050986089416415915875276507291023438808605401802092123392
Short name T942
Test name
Test status
Simulation time 41708099183 ps
CPU time 1081.84 seconds
Started Oct 29 02:08:09 PM PDT 23
Finished Oct 29 02:26:11 PM PDT 23
Peak memory 215852 kb
Host smart-303616fb-b018-4bac-bc8e-5f98179b1c50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880259869735652291230509860
89416415915875276507291023438808605401802092123392 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.88025986973
565229123050986089416415915875276507291023438808605401802092123392
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.115114291877552308050527273555627553323464923340604724385227916542215020639952
Short name T768
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Oct 29 02:09:40 PM PDT 23
Finished Oct 29 02:09:42 PM PDT 23
Peak memory 205840 kb
Host smart-29ea4135-880f-4922-b761-c6ad14c99464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115114291877552308050527273555627553323464923340604724385227916542215020639952 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 230.edn_genbits.115114291877552308050527273555627553323464923340604724385227916542215020639952
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.65693177518933927366136846334225846651813172703856590133755370901169789407996
Short name T665
Test name
Test status
Simulation time 17999183 ps
CPU time 1.16 seconds
Started Oct 29 02:09:43 PM PDT 23
Finished Oct 29 02:09:45 PM PDT 23
Peak memory 205796 kb
Host smart-5a10c934-c5dd-4042-8ad2-ef0c73a2a042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65693177518933927366136846334225846651813172703856590133755370901169789407996 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 231.edn_genbits.65693177518933927366136846334225846651813172703856590133755370901169789407996
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.5549452647995730565497720203040954029407168625352181513362374921086303540689
Short name T238
Test name
Test status
Simulation time 17999183 ps
CPU time 1.06 seconds
Started Oct 29 02:08:49 PM PDT 23
Finished Oct 29 02:08:51 PM PDT 23
Peak memory 205828 kb
Host smart-30221513-d42d-4f4b-b094-53ecbfe07c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5549452647995730565497720203040954029407168625352181513362374921086303540689 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 232.edn_genbits.5549452647995730565497720203040954029407168625352181513362374921086303540689
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.113306514605237319184372996556731808020798873324072927371999252856365712988860
Short name T89
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Oct 29 02:09:49 PM PDT 23
Finished Oct 29 02:09:51 PM PDT 23
Peak memory 205836 kb
Host smart-e5a35d50-1b1e-4dde-bcd9-557d0569b87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113306514605237319184372996556731808020798873324072927371999252856365712988860 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 233.edn_genbits.113306514605237319184372996556731808020798873324072927371999252856365712988860
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.9359637000542047579980572289066054394432684438949974296184141611925665058715
Short name T855
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Oct 29 02:09:50 PM PDT 23
Finished Oct 29 02:09:52 PM PDT 23
Peak memory 205832 kb
Host smart-8d3b1ca9-45bb-4e64-b8a3-1bf16c0471bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9359637000542047579980572289066054394432684438949974296184141611925665058715 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 234.edn_genbits.9359637000542047579980572289066054394432684438949974296184141611925665058715
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.109321017465541846100969593887145900531583550107132316416593134102617687813488
Short name T824
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:10:27 PM PDT 23
Finished Oct 29 02:10:29 PM PDT 23
Peak memory 205748 kb
Host smart-86e027c6-c4bc-4436-bd5c-58e59d9198a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109321017465541846100969593887145900531583550107132316416593134102617687813488 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 235.edn_genbits.109321017465541846100969593887145900531583550107132316416593134102617687813488
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.89451723296688485791687133315140187210318684127728752184843618041733713505617
Short name T539
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Oct 29 02:09:46 PM PDT 23
Finished Oct 29 02:09:48 PM PDT 23
Peak memory 205900 kb
Host smart-bbfd37a5-b4cb-4648-9a7b-38c65957068c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89451723296688485791687133315140187210318684127728752184843618041733713505617 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 236.edn_genbits.89451723296688485791687133315140187210318684127728752184843618041733713505617
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.45044112511158927934773264198245027859831620942632470986306557373286826882255
Short name T899
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Oct 29 02:09:54 PM PDT 23
Finished Oct 29 02:09:55 PM PDT 23
Peak memory 205808 kb
Host smart-d4f62593-8f44-49de-92e9-7384406ae6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45044112511158927934773264198245027859831620942632470986306557373286826882255 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 237.edn_genbits.45044112511158927934773264198245027859831620942632470986306557373286826882255
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.99010263249916845474005580181381867076496893182695139150237898653081084177970
Short name T958
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Oct 29 02:09:46 PM PDT 23
Finished Oct 29 02:09:48 PM PDT 23
Peak memory 205828 kb
Host smart-a717554b-4b58-418d-b8e9-7817c51fd221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99010263249916845474005580181381867076496893182695139150237898653081084177970 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 238.edn_genbits.99010263249916845474005580181381867076496893182695139150237898653081084177970
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.28409512510312413717818258402002946897152936254965887968404593589982352874375
Short name T561
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Oct 29 02:10:07 PM PDT 23
Finished Oct 29 02:10:08 PM PDT 23
Peak memory 205848 kb
Host smart-7af5af2e-fdd3-4b05-829f-47d1b452b78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28409512510312413717818258402002946897152936254965887968404593589982352874375 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 239.edn_genbits.28409512510312413717818258402002946897152936254965887968404593589982352874375
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.85017363193041064306655564437708169159032162417363597368018581924011894807906
Short name T664
Test name
Test status
Simulation time 18259183 ps
CPU time 1.01 seconds
Started Oct 29 02:08:43 PM PDT 23
Finished Oct 29 02:08:45 PM PDT 23
Peak memory 205544 kb
Host smart-a5eaccf4-ac8d-428b-9aaf-d9c46b175456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85017363193041064306655564437708169159032162417363597368018581924011894807906 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 24.edn_alert.85017363193041064306655564437708169159032162417363597368018581924011894807906
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.91459691910781449893165064192355125849826491942272611793226841423161976935603
Short name T940
Test name
Test status
Simulation time 28184990 ps
CPU time 0.9 seconds
Started Oct 29 02:07:05 PM PDT 23
Finished Oct 29 02:07:09 PM PDT 23
Peak memory 204828 kb
Host smart-3491419c-d30f-4e28-a7c4-91f8e4cc9fc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91459691910781449893165064192355125849826491942272611793226841423161976935603 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.edn_alert_test.91459691910781449893165064192355125849826491942272611793226841423161976935603
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.68379014927270363003874198573438460350245124661238411835050464204910328881680
Short name T766
Test name
Test status
Simulation time 12219183 ps
CPU time 0.84 seconds
Started Oct 29 02:07:06 PM PDT 23
Finished Oct 29 02:07:09 PM PDT 23
Peak memory 214892 kb
Host smart-aed42621-e3f6-47e0-9b86-05d98faa9828
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68379014927270363003874198573438460350245124661238411835050464204910328881680 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.edn_disable.68379014927270363003874198573438460350245124661238411835050464204910328881680
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.33063094064064273120315915135020807942018310508099560535962851681048215430329
Short name T932
Test name
Test status
Simulation time 17319183 ps
CPU time 0.92 seconds
Started Oct 29 02:07:05 PM PDT 23
Finished Oct 29 02:07:09 PM PDT 23
Peak memory 214076 kb
Host smart-aeaa5dba-dfbc-49ab-bc27-376a0a3ffe29
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33063094064064273120315915135020807942018310508099560535962851681048215430329 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable_auto_req_mode.3306309406406427312031591513502080794201831050809956053596
2851681048215430329
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.59207577000386876503980526345778438859003497797853170886335954101657923150428
Short name T788
Test name
Test status
Simulation time 24963823 ps
CPU time 1.19 seconds
Started Oct 29 02:07:30 PM PDT 23
Finished Oct 29 02:07:32 PM PDT 23
Peak memory 230460 kb
Host smart-5e6ef06e-6985-4395-a130-df4a57051501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59207577000386876503980526345778438859003497797853170886335954101657923150428 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.edn_err.59207577000386876503980526345778438859003497797853170886335954101657923150428
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.27638422349198830520851238424517273237786963223964444471479195873462735465202
Short name T708
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Oct 29 02:09:09 PM PDT 23
Finished Oct 29 02:09:10 PM PDT 23
Peak memory 205852 kb
Host smart-049e9287-0c21-46e4-8866-4529e18aa552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27638422349198830520851238424517273237786963223964444471479195873462735465202 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.edn_genbits.27638422349198830520851238424517273237786963223964444471479195873462735465202
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.28713909039189045979045240200231699664016480576820813388870168172967073250665
Short name T607
Test name
Test status
Simulation time 18439183 ps
CPU time 1.13 seconds
Started Oct 29 02:09:48 PM PDT 23
Finished Oct 29 02:09:50 PM PDT 23
Peak memory 222268 kb
Host smart-b73e3137-1111-495a-b2b9-960a62263d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28713909039189045979045240200231699664016480576820813388870168172967073250665 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.edn_intr.28713909039189045979045240200231699664016480576820813388870168172967073250665
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.95175103961059449691330318146725941174864843062183866002604678363428998057861
Short name T521
Test name
Test status
Simulation time 13059183 ps
CPU time 0.87 seconds
Started Oct 29 02:09:48 PM PDT 23
Finished Oct 29 02:09:50 PM PDT 23
Peak memory 205288 kb
Host smart-516a2f1f-f358-41a4-a54b-83c7af3927ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95175103961059449691330318146725941174864843062183866002604678363428998057861 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 24.edn_smoke.95175103961059449691330318146725941174864843062183866002604678363428998057861
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.86236043859625201817814081012806351742936334248338895324566188177330167398490
Short name T943
Test name
Test status
Simulation time 154489183 ps
CPU time 4.06 seconds
Started Oct 29 02:09:05 PM PDT 23
Finished Oct 29 02:09:09 PM PDT 23
Peak memory 206364 kb
Host smart-6526c213-dda6-4a34-9b0f-e0a4c4b0dedf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86236043859625201817814081012806351742936334248338895324566188177330167398490 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.86236043859625201817814081012806351742936334248338895324566188177330167398490
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.76074506502439217218190879386342563371109836948491110810216482277589572640826
Short name T758
Test name
Test status
Simulation time 41708099183 ps
CPU time 1047.27 seconds
Started Oct 29 02:09:40 PM PDT 23
Finished Oct 29 02:27:08 PM PDT 23
Peak memory 215864 kb
Host smart-b6742ddd-cd9d-45a5-989c-9238864bfe62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760745065024392172181908793
86342563371109836948491110810216482277589572640826 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.76074506502
439217218190879386342563371109836948491110810216482277589572640826
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.49921004000845865410747000587829121644053385320304692259547899057574395811385
Short name T367
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Oct 29 02:09:49 PM PDT 23
Finished Oct 29 02:09:51 PM PDT 23
Peak memory 205816 kb
Host smart-7b5d8549-32cb-4550-b3db-b20e01041fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49921004000845865410747000587829121644053385320304692259547899057574395811385 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 240.edn_genbits.49921004000845865410747000587829121644053385320304692259547899057574395811385
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.51435114399490754253725789346531838538656570836958339477860220463862047054756
Short name T63
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Oct 29 02:09:57 PM PDT 23
Finished Oct 29 02:09:58 PM PDT 23
Peak memory 205792 kb
Host smart-a3df0466-8955-4793-aa9f-4f334cd213a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51435114399490754253725789346531838538656570836958339477860220463862047054756 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 241.edn_genbits.51435114399490754253725789346531838538656570836958339477860220463862047054756
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.83280979868329711807659282414595994830014008799323889052255142131401651269235
Short name T541
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Oct 29 02:09:50 PM PDT 23
Finished Oct 29 02:09:51 PM PDT 23
Peak memory 205824 kb
Host smart-75755582-63d1-4df9-a463-bfa6a6b4b07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83280979868329711807659282414595994830014008799323889052255142131401651269235 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 242.edn_genbits.83280979868329711807659282414595994830014008799323889052255142131401651269235
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.47245883484243549482405011464536776367252481165881743134711458298438920123309
Short name T759
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Oct 29 02:10:34 PM PDT 23
Finished Oct 29 02:10:36 PM PDT 23
Peak memory 205828 kb
Host smart-a035285b-5b96-4adb-9650-a96830beb9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47245883484243549482405011464536776367252481165881743134711458298438920123309 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 243.edn_genbits.47245883484243549482405011464536776367252481165881743134711458298438920123309
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.539376433678486819086702003811700668503735988558746463959252357742384258698
Short name T623
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Oct 29 02:10:07 PM PDT 23
Finished Oct 29 02:10:08 PM PDT 23
Peak memory 205856 kb
Host smart-71506227-cfeb-4a7b-be2d-cd55180275de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539376433678486819086702003811700668503735988558746463959252357742384258698 -assert nopostproc +UVM_TESTNAME=edn_genbits
_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 244.edn_genbits.539376433678486819086702003811700668503735988558746463959252357742384258698
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.53081962404359369051063758575549517350009335173555205727236494919722365179718
Short name T537
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Oct 29 02:10:39 PM PDT 23
Finished Oct 29 02:10:40 PM PDT 23
Peak memory 205844 kb
Host smart-cef19d8e-c5fc-4e98-9240-4f19baa286c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53081962404359369051063758575549517350009335173555205727236494919722365179718 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 245.edn_genbits.53081962404359369051063758575549517350009335173555205727236494919722365179718
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.102858866986373835579729797763334328265910965351035576702672961232532017764960
Short name T667
Test name
Test status
Simulation time 17999183 ps
CPU time 1.06 seconds
Started Oct 29 02:10:04 PM PDT 23
Finished Oct 29 02:10:05 PM PDT 23
Peak memory 205776 kb
Host smart-43737d71-754b-441b-a6ab-13a18b8182ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102858866986373835579729797763334328265910965351035576702672961232532017764960 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 246.edn_genbits.102858866986373835579729797763334328265910965351035576702672961232532017764960
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.106830622932863233339598374074152891007432280115782508163682325153900865411406
Short name T655
Test name
Test status
Simulation time 17999183 ps
CPU time 1.18 seconds
Started Oct 29 02:10:54 PM PDT 23
Finished Oct 29 02:10:56 PM PDT 23
Peak memory 205808 kb
Host smart-40b96262-176d-4229-ae25-9ed45353bb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106830622932863233339598374074152891007432280115782508163682325153900865411406 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 247.edn_genbits.106830622932863233339598374074152891007432280115782508163682325153900865411406
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.2975570416395307635946699781029630210487196233927162822197862417878723561243
Short name T328
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Oct 29 02:10:34 PM PDT 23
Finished Oct 29 02:10:36 PM PDT 23
Peak memory 205844 kb
Host smart-3202d303-42f6-4c30-b3b1-8a09a6fa4dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975570416395307635946699781029630210487196233927162822197862417878723561243 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 248.edn_genbits.2975570416395307635946699781029630210487196233927162822197862417878723561243
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.1036726793545456975108564013121240289740216558427583327715614336433160316457
Short name T622
Test name
Test status
Simulation time 17999183 ps
CPU time 1.06 seconds
Started Oct 29 02:10:35 PM PDT 23
Finished Oct 29 02:10:36 PM PDT 23
Peak memory 205844 kb
Host smart-133eb0be-22a1-4d66-a2e2-21c19f8a63e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036726793545456975108564013121240289740216558427583327715614336433160316457 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 249.edn_genbits.1036726793545456975108564013121240289740216558427583327715614336433160316457
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.91375695332257048510356815933732771031300797275134547461607356137716370618804
Short name T560
Test name
Test status
Simulation time 18259183 ps
CPU time 0.99 seconds
Started Oct 29 02:07:03 PM PDT 23
Finished Oct 29 02:07:05 PM PDT 23
Peak memory 205508 kb
Host smart-ad7cedff-b64c-49ff-91d3-ed289a6fda3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91375695332257048510356815933732771031300797275134547461607356137716370618804 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 25.edn_alert.91375695332257048510356815933732771031300797275134547461607356137716370618804
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.105250395807616373216118281952678080503303804501369854887775178767728304875496
Short name T417
Test name
Test status
Simulation time 28184990 ps
CPU time 0.86 seconds
Started Oct 29 02:07:29 PM PDT 23
Finished Oct 29 02:07:30 PM PDT 23
Peak memory 205416 kb
Host smart-aeccb579-5a64-456c-a574-61abf3d8903d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105250395807616373216118281952678080503303804501369854887775178767728304875496 -assert nopostp
roc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 25.edn_alert_test.105250395807616373216118281952678080503303804501369854887775178767728304875496
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.38996778178416921097661704640607751969766642104635271870712201214150904598355
Short name T800
Test name
Test status
Simulation time 12219183 ps
CPU time 0.9 seconds
Started Oct 29 02:07:04 PM PDT 23
Finished Oct 29 02:07:05 PM PDT 23
Peak memory 214824 kb
Host smart-9841cc6a-4f60-45cc-b45c-9388a5d10a56
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38996778178416921097661704640607751969766642104635271870712201214150904598355 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.edn_disable.38996778178416921097661704640607751969766642104635271870712201214150904598355
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.67990116369202786297164183557753732338373379640119177368884187364877772040245
Short name T465
Test name
Test status
Simulation time 17319183 ps
CPU time 0.94 seconds
Started Oct 29 02:07:05 PM PDT 23
Finished Oct 29 02:07:09 PM PDT 23
Peak memory 214928 kb
Host smart-7e021353-60db-4c3f-9d29-466142d66a1d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67990116369202786297164183557753732338373379640119177368884187364877772040245 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable_auto_req_mode.6799011636920278629716418355775373233837337964011917736888
4187364877772040245
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.99888481901324371091846337732478971149802989572788256246429212306670416121802
Short name T509
Test name
Test status
Simulation time 24963823 ps
CPU time 1.18 seconds
Started Oct 29 02:07:05 PM PDT 23
Finished Oct 29 02:07:09 PM PDT 23
Peak memory 230464 kb
Host smart-6f07b54d-69f6-4a08-b884-1da74444bf2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99888481901324371091846337732478971149802989572788256246429212306670416121802 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.edn_err.99888481901324371091846337732478971149802989572788256246429212306670416121802
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.71907965972551804723546514191255441109455251944151050462994332312920740214640
Short name T250
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Oct 29 02:07:05 PM PDT 23
Finished Oct 29 02:07:09 PM PDT 23
Peak memory 205844 kb
Host smart-a07b4e4d-6515-4c90-a658-bb01281b81fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71907965972551804723546514191255441109455251944151050462994332312920740214640 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.edn_genbits.71907965972551804723546514191255441109455251944151050462994332312920740214640
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.40198426155001073865396090186477641462820795894825467131045766153864552919078
Short name T303
Test name
Test status
Simulation time 18439183 ps
CPU time 1.18 seconds
Started Oct 29 02:07:03 PM PDT 23
Finished Oct 29 02:07:06 PM PDT 23
Peak memory 222264 kb
Host smart-f33f6d59-77a7-422e-b206-3e30c0f4cc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40198426155001073865396090186477641462820795894825467131045766153864552919078 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.edn_intr.40198426155001073865396090186477641462820795894825467131045766153864552919078
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.67812077483393688944515138846527592240822917313218561095901854246240566218964
Short name T525
Test name
Test status
Simulation time 13059183 ps
CPU time 0.92 seconds
Started Oct 29 02:07:04 PM PDT 23
Finished Oct 29 02:07:07 PM PDT 23
Peak memory 205288 kb
Host smart-0605467b-18b5-4b4d-b654-c2108d750061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67812077483393688944515138846527592240822917313218561095901854246240566218964 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 25.edn_smoke.67812077483393688944515138846527592240822917313218561095901854246240566218964
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.27044407245719909776797375888208687619806911993457938536707043382808499904812
Short name T57
Test name
Test status
Simulation time 154489183 ps
CPU time 3.94 seconds
Started Oct 29 02:07:30 PM PDT 23
Finished Oct 29 02:07:35 PM PDT 23
Peak memory 206380 kb
Host smart-adbabb87-a0bc-439b-92f9-d1861061c308
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27044407245719909776797375888208687619806911993457938536707043382808499904812 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.27044407245719909776797375888208687619806911993457938536707043382808499904812
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.59158805256889101403191375864169788824258731062575433799813014619607842064657
Short name T770
Test name
Test status
Simulation time 41708099183 ps
CPU time 1076.37 seconds
Started Oct 29 02:07:27 PM PDT 23
Finished Oct 29 02:25:24 PM PDT 23
Peak memory 215916 kb
Host smart-8151c2f8-1292-47a3-b6f5-5e088d8c7815
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591588052568891014031913758
64169788824258731062575433799813014619607842064657 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.59158805256
889101403191375864169788824258731062575433799813014619607842064657
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.107150711456427483420003185659620659806318860987133221541443362022266775380298
Short name T273
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Oct 29 02:08:49 PM PDT 23
Finished Oct 29 02:08:51 PM PDT 23
Peak memory 205844 kb
Host smart-2b704b53-d662-4703-8a32-89448319d180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107150711456427483420003185659620659806318860987133221541443362022266775380298 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 250.edn_genbits.107150711456427483420003185659620659806318860987133221541443362022266775380298
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.62648930893588575375230927619827585265882689761199792414001467561172707330183
Short name T730
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Oct 29 02:08:51 PM PDT 23
Finished Oct 29 02:08:55 PM PDT 23
Peak memory 205920 kb
Host smart-f7f69f37-d384-4bed-8ee7-e7124b3bd480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62648930893588575375230927619827585265882689761199792414001467561172707330183 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 251.edn_genbits.62648930893588575375230927619827585265882689761199792414001467561172707330183
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.104626938809800441344610200340932581147659786094036860651185787622973178939997
Short name T343
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Oct 29 02:08:50 PM PDT 23
Finished Oct 29 02:08:52 PM PDT 23
Peak memory 205844 kb
Host smart-e9e184be-0764-4f0e-939d-2cd75a4a8254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104626938809800441344610200340932581147659786094036860651185787622973178939997 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 252.edn_genbits.104626938809800441344610200340932581147659786094036860651185787622973178939997
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.82669679288251713161169940726861350097517436065412295759084475797083391670739
Short name T289
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Oct 29 02:09:47 PM PDT 23
Finished Oct 29 02:09:48 PM PDT 23
Peak memory 205660 kb
Host smart-b51377dc-a219-49f8-a840-426788e3629c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82669679288251713161169940726861350097517436065412295759084475797083391670739 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 253.edn_genbits.82669679288251713161169940726861350097517436065412295759084475797083391670739
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.83171453313928990077091943695790374703666713371711487664711973645735571542738
Short name T564
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Oct 29 02:09:44 PM PDT 23
Finished Oct 29 02:09:46 PM PDT 23
Peak memory 205844 kb
Host smart-bbf6d600-db1e-4e70-b6e5-cd89112df76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83171453313928990077091943695790374703666713371711487664711973645735571542738 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 254.edn_genbits.83171453313928990077091943695790374703666713371711487664711973645735571542738
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.87387335809556388182854652252915403078294211715412444853978363742605410038000
Short name T705
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Oct 29 02:09:40 PM PDT 23
Finished Oct 29 02:09:41 PM PDT 23
Peak memory 205732 kb
Host smart-5009fb66-8b34-4e12-9fef-09ca5b8184ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87387335809556388182854652252915403078294211715412444853978363742605410038000 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 255.edn_genbits.87387335809556388182854652252915403078294211715412444853978363742605410038000
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.7500399800533002540710367491004726325155763010241673002348581854121632913075
Short name T349
Test name
Test status
Simulation time 17999183 ps
CPU time 1.05 seconds
Started Oct 29 02:09:22 PM PDT 23
Finished Oct 29 02:09:23 PM PDT 23
Peak memory 205732 kb
Host smart-ac430f6b-290f-4612-922a-ca4ea939989d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7500399800533002540710367491004726325155763010241673002348581854121632913075 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 256.edn_genbits.7500399800533002540710367491004726325155763010241673002348581854121632913075
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.87778286493859602311643192070162582186261902098901698037293563696482132383080
Short name T934
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Oct 29 02:08:51 PM PDT 23
Finished Oct 29 02:08:52 PM PDT 23
Peak memory 205920 kb
Host smart-882b5d54-9149-4ddf-99e1-e8162973bf94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87778286493859602311643192070162582186261902098901698037293563696482132383080 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 257.edn_genbits.87778286493859602311643192070162582186261902098901698037293563696482132383080
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.107320647661603040493412998156323882356555137088872082564773604835654840871445
Short name T818
Test name
Test status
Simulation time 17999183 ps
CPU time 1.16 seconds
Started Oct 29 02:09:37 PM PDT 23
Finished Oct 29 02:09:38 PM PDT 23
Peak memory 206036 kb
Host smart-9467e140-796d-484a-9a4e-5ede84be1f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107320647661603040493412998156323882356555137088872082564773604835654840871445 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 258.edn_genbits.107320647661603040493412998156323882356555137088872082564773604835654840871445
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.73582998242320703649926221044496675313879633431856664149482465687655199579634
Short name T870
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Oct 29 02:09:46 PM PDT 23
Finished Oct 29 02:09:47 PM PDT 23
Peak memory 205872 kb
Host smart-cb0bea6f-2cb9-46b9-bd2f-2d5e8477ba11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73582998242320703649926221044496675313879633431856664149482465687655199579634 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 259.edn_genbits.73582998242320703649926221044496675313879633431856664149482465687655199579634
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.39777334051659208162405210662734577116572493032767094806229879772517774143176
Short name T287
Test name
Test status
Simulation time 18259183 ps
CPU time 1 seconds
Started Oct 29 02:07:08 PM PDT 23
Finished Oct 29 02:07:10 PM PDT 23
Peak memory 205612 kb
Host smart-abc688b5-c172-4d3f-8b4a-91082ea4e7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39777334051659208162405210662734577116572493032767094806229879772517774143176 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 26.edn_alert.39777334051659208162405210662734577116572493032767094806229879772517774143176
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.22560365168594575351106560286835549679862737714559745824068518386345153788596
Short name T936
Test name
Test status
Simulation time 28184990 ps
CPU time 0.84 seconds
Started Oct 29 02:07:29 PM PDT 23
Finished Oct 29 02:07:31 PM PDT 23
Peak memory 205424 kb
Host smart-2c8d1958-0275-45d8-8b04-eb018a6d7150
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22560365168594575351106560286835549679862737714559745824068518386345153788596 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.edn_alert_test.22560365168594575351106560286835549679862737714559745824068518386345153788596
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.87095341326838568149223993536653674445874983647463322129469824379203532792267
Short name T482
Test name
Test status
Simulation time 12219183 ps
CPU time 0.87 seconds
Started Oct 29 02:07:06 PM PDT 23
Finished Oct 29 02:07:09 PM PDT 23
Peak memory 214800 kb
Host smart-fa5c6c82-b89d-4bf2-8c20-ba0134210b12
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87095341326838568149223993536653674445874983647463322129469824379203532792267 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.edn_disable.87095341326838568149223993536653674445874983647463322129469824379203532792267
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.55487570732228817221255817278811787278425302898120748201227379625473210256817
Short name T474
Test name
Test status
Simulation time 17319183 ps
CPU time 0.94 seconds
Started Oct 29 02:07:33 PM PDT 23
Finished Oct 29 02:07:35 PM PDT 23
Peak memory 214880 kb
Host smart-4378fd41-966d-4e88-974f-095e03aba70e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55487570732228817221255817278811787278425302898120748201227379625473210256817 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable_auto_req_mode.5548757073222881722125581727881178727842530289812074820122
7379625473210256817
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.14312063526879017373444276945170061569003525650797027342939203802385191938003
Short name T620
Test name
Test status
Simulation time 24963823 ps
CPU time 1.16 seconds
Started Oct 29 02:07:32 PM PDT 23
Finished Oct 29 02:07:34 PM PDT 23
Peak memory 230492 kb
Host smart-4df3b62f-9f55-44a1-bb80-5e8429aaa37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14312063526879017373444276945170061569003525650797027342939203802385191938003 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.edn_err.14312063526879017373444276945170061569003525650797027342939203802385191938003
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.49941906763473178823468047991860573728994142397107249595011693976526422159433
Short name T902
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:07:30 PM PDT 23
Finished Oct 29 02:07:32 PM PDT 23
Peak memory 205768 kb
Host smart-299009d0-a664-4b99-aa31-37a13dbed474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49941906763473178823468047991860573728994142397107249595011693976526422159433 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.edn_genbits.49941906763473178823468047991860573728994142397107249595011693976526422159433
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.102174195934247094860334759547324421184597077819352291373821365019725105718546
Short name T630
Test name
Test status
Simulation time 18439183 ps
CPU time 1.1 seconds
Started Oct 29 02:07:04 PM PDT 23
Finished Oct 29 02:07:07 PM PDT 23
Peak memory 222220 kb
Host smart-bfbefb75-1020-4432-95cf-455a4ca790ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102174195934247094860334759547324421184597077819352291373821365019725105718546 -assert nopostproc +UVM_TESTNAME=edn_intr
_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.edn_intr.102174195934247094860334759547324421184597077819352291373821365019725105718546
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.106137141011022591248670678292697449694206612602568588728696462319265213869729
Short name T641
Test name
Test status
Simulation time 13059183 ps
CPU time 0.89 seconds
Started Oct 29 02:07:34 PM PDT 23
Finished Oct 29 02:07:35 PM PDT 23
Peak memory 205244 kb
Host smart-bd17a529-4bf2-4d94-8aa9-a7cd7746eaca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106137141011022591248670678292697449694206612602568588728696462319265213869729 -assert nopostproc +UVM_TESTNAME=edn_smok
e_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 26.edn_smoke.106137141011022591248670678292697449694206612602568588728696462319265213869729
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.5363253614610542122171067069288302421147672846938895815404160942206406548142
Short name T873
Test name
Test status
Simulation time 154489183 ps
CPU time 4.09 seconds
Started Oct 29 02:07:05 PM PDT 23
Finished Oct 29 02:07:12 PM PDT 23
Peak memory 206344 kb
Host smart-d856ab09-aa61-4772-ba24-9d84efd1dce2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5363253614610542122171067069288302421147672846938895815404160942206406548142 -assert nopost
proc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.5363253614610542122171067069288302421147672846938895815404160942206406548142
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.95885416793471549774329485833857415378568175858488486050048319009753549575404
Short name T867
Test name
Test status
Simulation time 41708099183 ps
CPU time 1060.38 seconds
Started Oct 29 02:07:37 PM PDT 23
Finished Oct 29 02:25:18 PM PDT 23
Peak memory 215816 kb
Host smart-65322bb4-f968-4ee3-9bab-efc3aaf2b230
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958854167934715497743294858
33857415378568175858488486050048319009753549575404 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.95885416793
471549774329485833857415378568175858488486050048319009753549575404
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.74344958560866423906717709922561255253381601858953662507499201163511736240324
Short name T266
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Oct 29 02:08:49 PM PDT 23
Finished Oct 29 02:08:51 PM PDT 23
Peak memory 205820 kb
Host smart-56f72887-0ff2-47cc-93ee-6de0b54d06b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74344958560866423906717709922561255253381601858953662507499201163511736240324 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 260.edn_genbits.74344958560866423906717709922561255253381601858953662507499201163511736240324
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.19775676149569869092663096147214516992060486892139053692130227516166870252028
Short name T912
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Oct 29 02:08:50 PM PDT 23
Finished Oct 29 02:08:51 PM PDT 23
Peak memory 205844 kb
Host smart-f197ab7b-6ac0-4a42-b378-b01a1567fb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19775676149569869092663096147214516992060486892139053692130227516166870252028 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 261.edn_genbits.19775676149569869092663096147214516992060486892139053692130227516166870252028
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.91587007945136598509010471051549924927969675508120211228868555324912123327163
Short name T764
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Oct 29 02:09:48 PM PDT 23
Finished Oct 29 02:09:50 PM PDT 23
Peak memory 205768 kb
Host smart-b5f9cfc3-bf5d-4878-a125-3892538ffe48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91587007945136598509010471051549924927969675508120211228868555324912123327163 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 262.edn_genbits.91587007945136598509010471051549924927969675508120211228868555324912123327163
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.68421784567395451390406674110523803604742399516350660112894365337736578649135
Short name T263
Test name
Test status
Simulation time 17999183 ps
CPU time 1.04 seconds
Started Oct 29 02:09:37 PM PDT 23
Finished Oct 29 02:09:38 PM PDT 23
Peak memory 205760 kb
Host smart-f7461658-9a87-48c3-a688-0d762e297027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68421784567395451390406674110523803604742399516350660112894365337736578649135 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 263.edn_genbits.68421784567395451390406674110523803604742399516350660112894365337736578649135
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.85839109491559954947990176848995451468550276283257154300260860471909931540795
Short name T964
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Oct 29 02:08:48 PM PDT 23
Finished Oct 29 02:08:49 PM PDT 23
Peak memory 205812 kb
Host smart-a6f12e15-fdf3-4666-9830-7af4e87c3c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85839109491559954947990176848995451468550276283257154300260860471909931540795 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 264.edn_genbits.85839109491559954947990176848995451468550276283257154300260860471909931540795
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.101231443124612320138176977613713286297512553176917607214817909217236231905613
Short name T466
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:08:53 PM PDT 23
Finished Oct 29 02:08:56 PM PDT 23
Peak memory 205852 kb
Host smart-16fab352-1137-4362-8472-1b59ba1ff1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101231443124612320138176977613713286297512553176917607214817909217236231905613 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 265.edn_genbits.101231443124612320138176977613713286297512553176917607214817909217236231905613
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.58085391927514406149883538244256509151154891731938271916737465314835389590006
Short name T732
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Oct 29 02:09:47 PM PDT 23
Finished Oct 29 02:09:48 PM PDT 23
Peak memory 205828 kb
Host smart-e6781049-dff5-4844-b1d6-6ca6b7eb5ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58085391927514406149883538244256509151154891731938271916737465314835389590006 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 266.edn_genbits.58085391927514406149883538244256509151154891731938271916737465314835389590006
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.12335938678386173415750774029545391289394094597761085572699328645704046390218
Short name T806
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:08:46 PM PDT 23
Finished Oct 29 02:08:48 PM PDT 23
Peak memory 205832 kb
Host smart-5e626e45-e5ae-4e0e-8ec5-10bbe4d43c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12335938678386173415750774029545391289394094597761085572699328645704046390218 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 267.edn_genbits.12335938678386173415750774029545391289394094597761085572699328645704046390218
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.70881093520931314756282692557863390273301387574429418862403452249578321465272
Short name T306
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Oct 29 02:08:51 PM PDT 23
Finished Oct 29 02:08:52 PM PDT 23
Peak memory 205920 kb
Host smart-3bc54cb4-34d9-4a9a-8906-35f94f6c05f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70881093520931314756282692557863390273301387574429418862403452249578321465272 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 268.edn_genbits.70881093520931314756282692557863390273301387574429418862403452249578321465272
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.95661859708693748349184699068391693431722736879890778613106643966051313426785
Short name T911
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Oct 29 02:08:52 PM PDT 23
Finished Oct 29 02:08:56 PM PDT 23
Peak memory 205852 kb
Host smart-727fa720-1812-4dba-9b47-a824f541c05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95661859708693748349184699068391693431722736879890778613106643966051313426785 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 269.edn_genbits.95661859708693748349184699068391693431722736879890778613106643966051313426785
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.68984798933935545795135548588233130570924519281714804548295142426066639723766
Short name T473
Test name
Test status
Simulation time 18259183 ps
CPU time 0.97 seconds
Started Oct 29 02:07:29 PM PDT 23
Finished Oct 29 02:07:31 PM PDT 23
Peak memory 205584 kb
Host smart-74dd28d1-e358-45bb-a788-dfcf9dbec5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68984798933935545795135548588233130570924519281714804548295142426066639723766 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 27.edn_alert.68984798933935545795135548588233130570924519281714804548295142426066639723766
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.27277797622294637335008027219441855126748397191238957631292980349416658911028
Short name T606
Test name
Test status
Simulation time 28184990 ps
CPU time 0.85 seconds
Started Oct 29 02:07:04 PM PDT 23
Finished Oct 29 02:07:07 PM PDT 23
Peak memory 205500 kb
Host smart-a19ed058-511f-45ba-a895-5cf904c5df22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27277797622294637335008027219441855126748397191238957631292980349416658911028 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.edn_alert_test.27277797622294637335008027219441855126748397191238957631292980349416658911028
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.87072153367309041014978305026461384283218977463538536121784396106269183135096
Short name T53
Test name
Test status
Simulation time 12219183 ps
CPU time 0.87 seconds
Started Oct 29 02:07:06 PM PDT 23
Finished Oct 29 02:07:09 PM PDT 23
Peak memory 214880 kb
Host smart-820bb63a-4cbd-4476-a83a-3284431ca6cc
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87072153367309041014978305026461384283218977463538536121784396106269183135096 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.edn_disable.87072153367309041014978305026461384283218977463538536121784396106269183135096
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.60443463729724209550766013362875243880883266117890097375815766204315728117644
Short name T657
Test name
Test status
Simulation time 17319183 ps
CPU time 0.91 seconds
Started Oct 29 02:07:28 PM PDT 23
Finished Oct 29 02:07:29 PM PDT 23
Peak memory 214904 kb
Host smart-59f3717c-91f2-4802-a112-3842bc9276ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60443463729724209550766013362875243880883266117890097375815766204315728117644 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable_auto_req_mode.6044346372972420955076601336287524388088326611789009737581
5766204315728117644
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.23190139097865601922062324983981227432707674601618563359881729637104032717719
Short name T549
Test name
Test status
Simulation time 24963823 ps
CPU time 1.13 seconds
Started Oct 29 02:07:27 PM PDT 23
Finished Oct 29 02:07:29 PM PDT 23
Peak memory 230440 kb
Host smart-ce680972-67d3-4818-b3f3-c9a6de324550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23190139097865601922062324983981227432707674601618563359881729637104032717719 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.edn_err.23190139097865601922062324983981227432707674601618563359881729637104032717719
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.55699683745712445327442733030764393825815074298782549570227285486115265251317
Short name T71
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:07:07 PM PDT 23
Finished Oct 29 02:07:09 PM PDT 23
Peak memory 205824 kb
Host smart-337d5690-b5db-4c60-8c34-577978ba5cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55699683745712445327442733030764393825815074298782549570227285486115265251317 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.edn_genbits.55699683745712445327442733030764393825815074298782549570227285486115265251317
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.75342317397047966789335837524893718625736443988092326103828045924908133954089
Short name T532
Test name
Test status
Simulation time 18439183 ps
CPU time 1.15 seconds
Started Oct 29 02:07:05 PM PDT 23
Finished Oct 29 02:07:08 PM PDT 23
Peak memory 222296 kb
Host smart-9237e2ff-2a86-4ab6-9f07-912424429087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75342317397047966789335837524893718625736443988092326103828045924908133954089 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.edn_intr.75342317397047966789335837524893718625736443988092326103828045924908133954089
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.495234715741534788559265470751562789154994443637786864667877271439379485306
Short name T270
Test name
Test status
Simulation time 13059183 ps
CPU time 0.89 seconds
Started Oct 29 02:07:05 PM PDT 23
Finished Oct 29 02:07:09 PM PDT 23
Peak memory 205268 kb
Host smart-d2364402-a088-44e8-84d4-c7d0b7e41744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495234715741534788559265470751562789154994443637786864667877271439379485306 -assert nopostproc +UVM_TESTNAME=edn_smoke_t
est +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.edn_smoke.495234715741534788559265470751562789154994443637786864667877271439379485306
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.7746501002093765922198964970616351124394884729244351470435851755885712963885
Short name T796
Test name
Test status
Simulation time 154489183 ps
CPU time 4.04 seconds
Started Oct 29 02:07:58 PM PDT 23
Finished Oct 29 02:08:02 PM PDT 23
Peak memory 206400 kb
Host smart-276e4217-7c13-4b48-841f-d2be2c2e9d8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7746501002093765922198964970616351124394884729244351470435851755885712963885 -assert nopost
proc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.7746501002093765922198964970616351124394884729244351470435851755885712963885
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.63403101102284157070555657540678607997198754369427062263147160032125639461807
Short name T838
Test name
Test status
Simulation time 41708099183 ps
CPU time 1054.04 seconds
Started Oct 29 02:08:02 PM PDT 23
Finished Oct 29 02:25:36 PM PDT 23
Peak memory 215864 kb
Host smart-1706e3c4-dba3-48e8-b66f-c49b9daa5c8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634031011022841570705556575
40678607997198754369427062263147160032125639461807 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.63403101102
284157070555657540678607997198754369427062263147160032125639461807
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.89112178277415334179129558626852756078079723812057765979504356863531779800030
Short name T369
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Oct 29 02:09:48 PM PDT 23
Finished Oct 29 02:09:50 PM PDT 23
Peak memory 205852 kb
Host smart-1a87d1c1-fccb-4f62-8ff3-8e88a56e475c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89112178277415334179129558626852756078079723812057765979504356863531779800030 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 270.edn_genbits.89112178277415334179129558626852756078079723812057765979504356863531779800030
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.115692529710405844933765494106379388484145152925932068484316536153611558884923
Short name T13
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Oct 29 02:09:47 PM PDT 23
Finished Oct 29 02:09:49 PM PDT 23
Peak memory 205772 kb
Host smart-498b1cc8-2ee7-40d3-8dfe-78e9997527e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115692529710405844933765494106379388484145152925932068484316536153611558884923 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 271.edn_genbits.115692529710405844933765494106379388484145152925932068484316536153611558884923
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.70243918066297610958432681022341037922569418400390906462503760971908010369214
Short name T471
Test name
Test status
Simulation time 17999183 ps
CPU time 1.06 seconds
Started Oct 29 02:09:24 PM PDT 23
Finished Oct 29 02:09:25 PM PDT 23
Peak memory 205848 kb
Host smart-cce9bfa0-2205-42c9-850d-fe3c1346ee51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70243918066297610958432681022341037922569418400390906462503760971908010369214 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 272.edn_genbits.70243918066297610958432681022341037922569418400390906462503760971908010369214
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.43603715729857614754128731162225088231135683861359499743745368767092073151451
Short name T677
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Oct 29 02:09:47 PM PDT 23
Finished Oct 29 02:09:49 PM PDT 23
Peak memory 205796 kb
Host smart-feb08e1c-7bea-4300-a4c9-370795d522e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43603715729857614754128731162225088231135683861359499743745368767092073151451 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 273.edn_genbits.43603715729857614754128731162225088231135683861359499743745368767092073151451
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.82645508794055500176624045626771090374676384459592847174916871040592128215953
Short name T298
Test name
Test status
Simulation time 17999183 ps
CPU time 1.06 seconds
Started Oct 29 02:08:48 PM PDT 23
Finished Oct 29 02:08:50 PM PDT 23
Peak memory 205844 kb
Host smart-a5e7d858-0b13-4482-97a6-30428263fe15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82645508794055500176624045626771090374676384459592847174916871040592128215953 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 274.edn_genbits.82645508794055500176624045626771090374676384459592847174916871040592128215953
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.48754921784377704884850882785454949582732177299607148069163124874039865463517
Short name T573
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Oct 29 02:08:49 PM PDT 23
Finished Oct 29 02:08:51 PM PDT 23
Peak memory 205844 kb
Host smart-56522042-5f32-4c7f-b9d4-d80e70829db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48754921784377704884850882785454949582732177299607148069163124874039865463517 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 275.edn_genbits.48754921784377704884850882785454949582732177299607148069163124874039865463517
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.33680946945651724447864695281386945127207442229118889208583643559695266621961
Short name T565
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Oct 29 02:08:47 PM PDT 23
Finished Oct 29 02:08:48 PM PDT 23
Peak memory 205848 kb
Host smart-40828e49-b97b-4a87-8850-6ca63c8549b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33680946945651724447864695281386945127207442229118889208583643559695266621961 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 276.edn_genbits.33680946945651724447864695281386945127207442229118889208583643559695266621961
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.51227471029049157260173598538030924701723085902888643255137600330466704959867
Short name T368
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:09:40 PM PDT 23
Finished Oct 29 02:09:41 PM PDT 23
Peak memory 205772 kb
Host smart-fab9c637-980b-4a74-8e96-0fec30e397e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51227471029049157260173598538030924701723085902888643255137600330466704959867 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 277.edn_genbits.51227471029049157260173598538030924701723085902888643255137600330466704959867
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.21475184062006732000764761920345847525786165055675980966533127509373291987657
Short name T692
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Oct 29 02:08:57 PM PDT 23
Finished Oct 29 02:08:59 PM PDT 23
Peak memory 205816 kb
Host smart-99f66185-edfd-4565-861c-3fde12cf4186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21475184062006732000764761920345847525786165055675980966533127509373291987657 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 278.edn_genbits.21475184062006732000764761920345847525786165055675980966533127509373291987657
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.94813565775496926680397158191541431228028477850479042851097996585141692190349
Short name T826
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Oct 29 02:08:50 PM PDT 23
Finished Oct 29 02:08:52 PM PDT 23
Peak memory 205920 kb
Host smart-ac671b50-198b-45aa-ab6a-9a57a2d4ce5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94813565775496926680397158191541431228028477850479042851097996585141692190349 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 279.edn_genbits.94813565775496926680397158191541431228028477850479042851097996585141692190349
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.63283968479315560425769013448083918435921156128874962878407240348300701903618
Short name T685
Test name
Test status
Simulation time 18259183 ps
CPU time 1 seconds
Started Oct 29 02:07:05 PM PDT 23
Finished Oct 29 02:07:09 PM PDT 23
Peak memory 205580 kb
Host smart-af9cd552-51a0-43de-8dc6-e2882d02e95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63283968479315560425769013448083918435921156128874962878407240348300701903618 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 28.edn_alert.63283968479315560425769013448083918435921156128874962878407240348300701903618
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.70410319150324657270602196287635858343686687873676443969787943402762733101750
Short name T489
Test name
Test status
Simulation time 28184990 ps
CPU time 0.85 seconds
Started Oct 29 02:07:28 PM PDT 23
Finished Oct 29 02:07:30 PM PDT 23
Peak memory 205500 kb
Host smart-45ca4a74-c222-40a2-b70e-a568e8694fce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70410319150324657270602196287635858343686687873676443969787943402762733101750 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.edn_alert_test.70410319150324657270602196287635858343686687873676443969787943402762733101750
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.13836797580687917547244027965944694854256021893653472377497433623801627211605
Short name T864
Test name
Test status
Simulation time 12219183 ps
CPU time 0.86 seconds
Started Oct 29 02:07:01 PM PDT 23
Finished Oct 29 02:07:05 PM PDT 23
Peak memory 214828 kb
Host smart-f84267fd-728c-4036-9e60-f828fa8f1ac7
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13836797580687917547244027965944694854256021893653472377497433623801627211605 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.edn_disable.13836797580687917547244027965944694854256021893653472377497433623801627211605
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.11047557201493260853867354726647041906511572497894954099074013051939503934014
Short name T534
Test name
Test status
Simulation time 17319183 ps
CPU time 0.9 seconds
Started Oct 29 02:07:30 PM PDT 23
Finished Oct 29 02:07:31 PM PDT 23
Peak memory 214892 kb
Host smart-6a8dfc91-ac53-4cab-bac9-222454f04b5b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11047557201493260853867354726647041906511572497894954099074013051939503934014 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable_auto_req_mode.1104755720149326085386735472664704190651157249789495409907
4013051939503934014
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.50409982791226115749351281676845547813155035922079800981267116673435019255895
Short name T860
Test name
Test status
Simulation time 24963823 ps
CPU time 1.13 seconds
Started Oct 29 02:07:28 PM PDT 23
Finished Oct 29 02:07:30 PM PDT 23
Peak memory 230404 kb
Host smart-1976a540-cf9a-49ab-b71d-91f040a55c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50409982791226115749351281676845547813155035922079800981267116673435019255895 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.edn_err.50409982791226115749351281676845547813155035922079800981267116673435019255895
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.3559979779941902378614436366397291724981329593591995893523132905297965029986
Short name T455
Test name
Test status
Simulation time 17999183 ps
CPU time 1.15 seconds
Started Oct 29 02:07:29 PM PDT 23
Finished Oct 29 02:07:30 PM PDT 23
Peak memory 205756 kb
Host smart-2e031caa-2f48-40fc-841b-7a7a793943c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559979779941902378614436366397291724981329593591995893523132905297965029986 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.edn_genbits.3559979779941902378614436366397291724981329593591995893523132905297965029986
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.94222595430659486322905019715439052162774994423004109442626269193975968713337
Short name T935
Test name
Test status
Simulation time 18439183 ps
CPU time 1.12 seconds
Started Oct 29 02:07:05 PM PDT 23
Finished Oct 29 02:07:09 PM PDT 23
Peak memory 222360 kb
Host smart-a6d099bf-9ffb-41b8-9b09-4e5b1d89715a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94222595430659486322905019715439052162774994423004109442626269193975968713337 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.edn_intr.94222595430659486322905019715439052162774994423004109442626269193975968713337
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.101411937497917129911751270523492993079121590910360712740068792220869062554426
Short name T617
Test name
Test status
Simulation time 13059183 ps
CPU time 0.86 seconds
Started Oct 29 02:07:29 PM PDT 23
Finished Oct 29 02:07:31 PM PDT 23
Peak memory 205412 kb
Host smart-0503f121-c7e4-4346-b23d-efb3de2a6598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101411937497917129911751270523492993079121590910360712740068792220869062554426 -assert nopostproc +UVM_TESTNAME=edn_smok
e_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.edn_smoke.101411937497917129911751270523492993079121590910360712740068792220869062554426
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.91978966233325604755152597768173098053299453036224854530416443930334563903397
Short name T17
Test name
Test status
Simulation time 154489183 ps
CPU time 3.89 seconds
Started Oct 29 02:07:04 PM PDT 23
Finished Oct 29 02:07:08 PM PDT 23
Peak memory 206448 kb
Host smart-8fa13119-ac15-4699-87e4-5a7a6049f67b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91978966233325604755152597768173098053299453036224854530416443930334563903397 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.91978966233325604755152597768173098053299453036224854530416443930334563903397
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.19414271929263159680854819397163604986274227417549502203650611970468870783945
Short name T583
Test name
Test status
Simulation time 41708099183 ps
CPU time 1071.26 seconds
Started Oct 29 02:07:28 PM PDT 23
Finished Oct 29 02:25:20 PM PDT 23
Peak memory 215816 kb
Host smart-f7fc5efa-2737-408a-8896-89faf84ecf5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194142719292631596808548193
97163604986274227417549502203650611970468870783945 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.19414271929
263159680854819397163604986274227417549502203650611970468870783945
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.7942302979171332463301962013099093588545506347661516008963940433915142423589
Short name T456
Test name
Test status
Simulation time 17999183 ps
CPU time 1.15 seconds
Started Oct 29 02:09:39 PM PDT 23
Finished Oct 29 02:09:41 PM PDT 23
Peak memory 205832 kb
Host smart-bac891e0-0a66-48dd-a93d-38773b9827e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7942302979171332463301962013099093588545506347661516008963940433915142423589 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 280.edn_genbits.7942302979171332463301962013099093588545506347661516008963940433915142423589
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.109662122717158286732307140119340950766164408084535674538164968111031134981891
Short name T844
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Oct 29 02:09:49 PM PDT 23
Finished Oct 29 02:09:50 PM PDT 23
Peak memory 205848 kb
Host smart-5466c95b-8c5e-4c23-8287-b463629bdc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109662122717158286732307140119340950766164408084535674538164968111031134981891 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 281.edn_genbits.109662122717158286732307140119340950766164408084535674538164968111031134981891
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.8047131902118237098619203196614738522876119168336401790080255468688308748173
Short name T406
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Oct 29 02:09:42 PM PDT 23
Finished Oct 29 02:09:43 PM PDT 23
Peak memory 205864 kb
Host smart-baec4e20-5160-4860-99e9-95b17978d9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8047131902118237098619203196614738522876119168336401790080255468688308748173 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 282.edn_genbits.8047131902118237098619203196614738522876119168336401790080255468688308748173
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.88574852368763427578889498310609553363814455630054078792208169313172339872208
Short name T522
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Oct 29 02:09:49 PM PDT 23
Finished Oct 29 02:09:51 PM PDT 23
Peak memory 205836 kb
Host smart-e46bc1a9-7218-4964-9d35-d03cca183006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88574852368763427578889498310609553363814455630054078792208169313172339872208 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 283.edn_genbits.88574852368763427578889498310609553363814455630054078792208169313172339872208
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.30730613309424368545573460859126125898086479084911155410682957004919131994006
Short name T451
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:08:57 PM PDT 23
Finished Oct 29 02:08:59 PM PDT 23
Peak memory 205816 kb
Host smart-0f3274cd-4c30-44fd-a3c6-8c19451f030f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30730613309424368545573460859126125898086479084911155410682957004919131994006 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 284.edn_genbits.30730613309424368545573460859126125898086479084911155410682957004919131994006
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.70422213553120587503457413484215596782391392495815765111821588835335896938928
Short name T332
Test name
Test status
Simulation time 17999183 ps
CPU time 1.15 seconds
Started Oct 29 02:09:34 PM PDT 23
Finished Oct 29 02:09:35 PM PDT 23
Peak memory 205860 kb
Host smart-616e6713-d0a0-4b13-88fd-942720a50fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70422213553120587503457413484215596782391392495815765111821588835335896938928 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 285.edn_genbits.70422213553120587503457413484215596782391392495815765111821588835335896938928
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.38199233021029836523236246718865261252884408002615409423433868028398452169253
Short name T335
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Oct 29 02:09:49 PM PDT 23
Finished Oct 29 02:09:51 PM PDT 23
Peak memory 205836 kb
Host smart-af22b397-7c1f-4ce7-8cb3-b6624fb23664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38199233021029836523236246718865261252884408002615409423433868028398452169253 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 286.edn_genbits.38199233021029836523236246718865261252884408002615409423433868028398452169253
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.93863779248608561899266202219927882418804856124271527221531923124485643459262
Short name T498
Test name
Test status
Simulation time 17999183 ps
CPU time 1.16 seconds
Started Oct 29 02:09:45 PM PDT 23
Finished Oct 29 02:09:47 PM PDT 23
Peak memory 205872 kb
Host smart-cb543c79-5b5f-403f-9df0-a23a432b321f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93863779248608561899266202219927882418804856124271527221531923124485643459262 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 287.edn_genbits.93863779248608561899266202219927882418804856124271527221531923124485643459262
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.44671273486884231448103572923006749535197111308978264888109410785805994308008
Short name T591
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Oct 29 02:09:55 PM PDT 23
Finished Oct 29 02:09:56 PM PDT 23
Peak memory 205828 kb
Host smart-b4b11c5f-216e-4c4d-949f-cdddfcd618b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44671273486884231448103572923006749535197111308978264888109410785805994308008 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 288.edn_genbits.44671273486884231448103572923006749535197111308978264888109410785805994308008
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.77076622298535090296804583076825394896367488237397543834248512731411923983680
Short name T918
Test name
Test status
Simulation time 17999183 ps
CPU time 1.06 seconds
Started Oct 29 02:08:54 PM PDT 23
Finished Oct 29 02:08:56 PM PDT 23
Peak memory 205484 kb
Host smart-f0762f4d-d71e-4b51-97c9-d3403d3b1642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77076622298535090296804583076825394896367488237397543834248512731411923983680 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 289.edn_genbits.77076622298535090296804583076825394896367488237397543834248512731411923983680
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.102245082105022370752624816648267278137945346439698674682161737498789084480293
Short name T715
Test name
Test status
Simulation time 18259183 ps
CPU time 0.99 seconds
Started Oct 29 02:07:05 PM PDT 23
Finished Oct 29 02:07:08 PM PDT 23
Peak memory 205636 kb
Host smart-5b0d2b8c-a71c-4dcb-956a-78b50837ba44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102245082105022370752624816648267278137945346439698674682161737498789084480293 -assert nopostproc +UVM_TESTNAME=edn_aler
t_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 29.edn_alert.102245082105022370752624816648267278137945346439698674682161737498789084480293
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.63592581323368602839169756543106356773834579258448972377029436793558337686508
Short name T830
Test name
Test status
Simulation time 28184990 ps
CPU time 0.9 seconds
Started Oct 29 02:07:07 PM PDT 23
Finished Oct 29 02:07:09 PM PDT 23
Peak memory 205532 kb
Host smart-5f1a7eed-b58e-4d61-ba23-a029fa7d12ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63592581323368602839169756543106356773834579258448972377029436793558337686508 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.edn_alert_test.63592581323368602839169756543106356773834579258448972377029436793558337686508
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.103418029426070153263486451339268194190961981363650904084980174602601475751788
Short name T670
Test name
Test status
Simulation time 12219183 ps
CPU time 0.91 seconds
Started Oct 29 02:07:32 PM PDT 23
Finished Oct 29 02:07:33 PM PDT 23
Peak memory 214856 kb
Host smart-515543e5-15f3-4353-9df4-0b94097bccfe
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103418029426070153263486451339268194190961981363650904084980174602601475751788 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 29.edn_disable.103418029426070153263486451339268194190961981363650904084980174602601475751788
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.58518742462496849041698874946907904966861421883344312848795691472676913880157
Short name T480
Test name
Test status
Simulation time 17319183 ps
CPU time 0.95 seconds
Started Oct 29 02:07:08 PM PDT 23
Finished Oct 29 02:07:09 PM PDT 23
Peak memory 214964 kb
Host smart-d85f3141-6241-4005-8e38-8733c1a7b53c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58518742462496849041698874946907904966861421883344312848795691472676913880157 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable_auto_req_mode.5851874246249684904169887494690790496686142188334431284879
5691472676913880157
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.113754040908474794004633410955952556637019623668045076460344909089920105986983
Short name T628
Test name
Test status
Simulation time 24963823 ps
CPU time 1.11 seconds
Started Oct 29 02:07:28 PM PDT 23
Finished Oct 29 02:07:30 PM PDT 23
Peak memory 230440 kb
Host smart-74e2254b-0f82-4391-9914-ab23f51adda8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113754040908474794004633410955952556637019623668045076460344909089920105986983 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.edn_err.113754040908474794004633410955952556637019623668045076460344909089920105986983
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.78685924893813101779660554491143318759521284840322419720359664398713500137113
Short name T488
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Oct 29 02:07:02 PM PDT 23
Finished Oct 29 02:07:06 PM PDT 23
Peak memory 205744 kb
Host smart-faa2899f-4edb-4708-a13d-665f68c7df8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78685924893813101779660554491143318759521284840322419720359664398713500137113 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.edn_genbits.78685924893813101779660554491143318759521284840322419720359664398713500137113
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.59878825200162587902817206840280322179681681926747396216114398971246220899180
Short name T929
Test name
Test status
Simulation time 18439183 ps
CPU time 1.14 seconds
Started Oct 29 02:07:28 PM PDT 23
Finished Oct 29 02:07:30 PM PDT 23
Peak memory 222208 kb
Host smart-77fda40c-1cfd-4bde-be22-b579537ca369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59878825200162587902817206840280322179681681926747396216114398971246220899180 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.edn_intr.59878825200162587902817206840280322179681681926747396216114398971246220899180
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.80936609300921471688066814907876450601582004075576492071675905254297804063377
Short name T901
Test name
Test status
Simulation time 13059183 ps
CPU time 0.86 seconds
Started Oct 29 02:07:02 PM PDT 23
Finished Oct 29 02:07:05 PM PDT 23
Peak memory 205348 kb
Host smart-f73ce8df-19d4-4b66-97c5-97ded991170a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80936609300921471688066814907876450601582004075576492071675905254297804063377 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 29.edn_smoke.80936609300921471688066814907876450601582004075576492071675905254297804063377
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.104865084663535792097582948806771795809892047600741060783143798296330291139705
Short name T383
Test name
Test status
Simulation time 154489183 ps
CPU time 3.99 seconds
Started Oct 29 02:07:28 PM PDT 23
Finished Oct 29 02:07:33 PM PDT 23
Peak memory 206520 kb
Host smart-02cc7034-c4d8-44c4-bd56-bc89d5675f22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104865084663535792097582948806771795809892047600741060783143798296330291139705 -assert nopo
stproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.104865084663535792097582948806771795809892047600741060783143798296330291139705
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.42226147345649197934925208332505919545780611129325932490992792931549395288594
Short name T386
Test name
Test status
Simulation time 41708099183 ps
CPU time 1026.92 seconds
Started Oct 29 02:07:31 PM PDT 23
Finished Oct 29 02:24:39 PM PDT 23
Peak memory 215844 kb
Host smart-c3a6f6b5-ffd0-4de0-887a-475986b0bc7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422261473456491979349252083
32505919545780611129325932490992792931549395288594 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.42226147345
649197934925208332505919545780611129325932490992792931549395288594
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.32298672008268382947855451723799395093040135535340985386100776067035754736019
Short name T433
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Oct 29 02:08:50 PM PDT 23
Finished Oct 29 02:08:52 PM PDT 23
Peak memory 205876 kb
Host smart-d467895c-6f14-454b-832f-94397e23430e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32298672008268382947855451723799395093040135535340985386100776067035754736019 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 290.edn_genbits.32298672008268382947855451723799395093040135535340985386100776067035754736019
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.91767137634328347255672328814935664525073428039326089981107349103955785074986
Short name T427
Test name
Test status
Simulation time 17999183 ps
CPU time 1.06 seconds
Started Oct 29 02:08:53 PM PDT 23
Finished Oct 29 02:08:56 PM PDT 23
Peak memory 205788 kb
Host smart-3e27541a-948a-4e5d-9088-19676a7fd2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91767137634328347255672328814935664525073428039326089981107349103955785074986 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 291.edn_genbits.91767137634328347255672328814935664525073428039326089981107349103955785074986
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.39354951590504747296393292225198042579080716265850564694216305169261124176126
Short name T72
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:09:50 PM PDT 23
Finished Oct 29 02:09:51 PM PDT 23
Peak memory 205836 kb
Host smart-0b84744d-f9da-48e9-8ce9-4922cffc9293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39354951590504747296393292225198042579080716265850564694216305169261124176126 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 292.edn_genbits.39354951590504747296393292225198042579080716265850564694216305169261124176126
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.37154134917610484353999435370171770136934007986585435442377915493903048087792
Short name T961
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Oct 29 02:08:54 PM PDT 23
Finished Oct 29 02:08:56 PM PDT 23
Peak memory 205844 kb
Host smart-ee247b57-1115-486c-bce8-850ca25ce30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37154134917610484353999435370171770136934007986585435442377915493903048087792 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 293.edn_genbits.37154134917610484353999435370171770136934007986585435442377915493903048087792
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.29037299405290977391575016249431054009336895272034026528638895875313939809698
Short name T939
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:08:53 PM PDT 23
Finished Oct 29 02:08:56 PM PDT 23
Peak memory 205888 kb
Host smart-ba074c11-eb26-4d92-821b-309b3fb624ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29037299405290977391575016249431054009336895272034026528638895875313939809698 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 294.edn_genbits.29037299405290977391575016249431054009336895272034026528638895875313939809698
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.6845855347045200859330651816138209329778175649532834503985136518069842551822
Short name T339
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Oct 29 02:08:55 PM PDT 23
Finished Oct 29 02:08:56 PM PDT 23
Peak memory 205912 kb
Host smart-d4eab6f4-79a7-49b2-add8-6cc4aa6ec5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6845855347045200859330651816138209329778175649532834503985136518069842551822 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 295.edn_genbits.6845855347045200859330651816138209329778175649532834503985136518069842551822
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.45232548463104063013319241513738122915637600810330446621436681642711438596327
Short name T636
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Oct 29 02:09:47 PM PDT 23
Finished Oct 29 02:09:49 PM PDT 23
Peak memory 205788 kb
Host smart-6ff0619d-33ec-4bcc-809e-e9eb7f2d2d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45232548463104063013319241513738122915637600810330446621436681642711438596327 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 296.edn_genbits.45232548463104063013319241513738122915637600810330446621436681642711438596327
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.73161010055783648013420953316007822251628761743721094124579176180861407460260
Short name T626
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Oct 29 02:09:50 PM PDT 23
Finished Oct 29 02:09:51 PM PDT 23
Peak memory 205828 kb
Host smart-d4eb5ba8-b0f6-4751-ae91-9f4e30fbdd3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73161010055783648013420953316007822251628761743721094124579176180861407460260 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 297.edn_genbits.73161010055783648013420953316007822251628761743721094124579176180861407460260
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.49047882821710597318759601460703181134518072562795261610338244480012742492013
Short name T660
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Oct 29 02:09:42 PM PDT 23
Finished Oct 29 02:09:44 PM PDT 23
Peak memory 205924 kb
Host smart-64cc78b8-d4cd-4bab-ade4-54d03f77bb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49047882821710597318759601460703181134518072562795261610338244480012742492013 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 298.edn_genbits.49047882821710597318759601460703181134518072562795261610338244480012742492013
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.98787362479410343394587916516181630830807926899772942012236042118987639572581
Short name T920
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:09:45 PM PDT 23
Finished Oct 29 02:09:47 PM PDT 23
Peak memory 205816 kb
Host smart-af02c136-8b9f-46e5-932c-060102c0daf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98787362479410343394587916516181630830807926899772942012236042118987639572581 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 299.edn_genbits.98787362479410343394587916516181630830807926899772942012236042118987639572581
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.91617411659445071647437762935735718294182669534760146049573056171795634361952
Short name T798
Test name
Test status
Simulation time 18259183 ps
CPU time 1.01 seconds
Started Oct 29 02:06:36 PM PDT 23
Finished Oct 29 02:06:38 PM PDT 23
Peak memory 205508 kb
Host smart-4ca40d29-5c14-4519-a285-ab218678d49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91617411659445071647437762935735718294182669534760146049573056171795634361952 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.edn_alert.91617411659445071647437762935735718294182669534760146049573056171795634361952
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.89076499152075229969340400483620634675704442476532679340791933139365297415741
Short name T647
Test name
Test status
Simulation time 28184990 ps
CPU time 0.87 seconds
Started Oct 29 02:06:41 PM PDT 23
Finished Oct 29 02:06:42 PM PDT 23
Peak memory 205528 kb
Host smart-02a725aa-8afa-4d15-9558-853978bebdef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89076499152075229969340400483620634675704442476532679340791933139365297415741 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.edn_alert_test.89076499152075229969340400483620634675704442476532679340791933139365297415741
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.3109669927754408916321095185687104018201563396253452750498776760313203909048
Short name T577
Test name
Test status
Simulation time 12219183 ps
CPU time 0.88 seconds
Started Oct 29 02:07:19 PM PDT 23
Finished Oct 29 02:07:21 PM PDT 23
Peak memory 214944 kb
Host smart-beb75af8-33ec-40f3-9630-c876dba38537
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109669927754408916321095185687104018201563396253452750498776760313203909048 -assert nopostproc
+UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.edn_disable.3109669927754408916321095185687104018201563396253452750498776760313203909048
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.74856152391250058250791799654581631508102348181988841434142276340009253011919
Short name T779
Test name
Test status
Simulation time 17319183 ps
CPU time 0.92 seconds
Started Oct 29 02:06:32 PM PDT 23
Finished Oct 29 02:06:34 PM PDT 23
Peak memory 214968 kb
Host smart-c67c88e3-51de-4dff-a1f9-ca28b9a573c0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74856152391250058250791799654581631508102348181988841434142276340009253011919 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable_auto_req_mode.74856152391250058250791799654581631508102348181988841434142
276340009253011919
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.69245826371633993654493707342224316250693167203166090917561808552842052380912
Short name T570
Test name
Test status
Simulation time 24963823 ps
CPU time 1.17 seconds
Started Oct 29 02:07:03 PM PDT 23
Finished Oct 29 02:07:06 PM PDT 23
Peak memory 230492 kb
Host smart-74b1db47-d8b1-451b-85f5-dbf9efc76372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69245826371633993654493707342224316250693167203166090917561808552842052380912 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
edn_err.69245826371633993654493707342224316250693167203166090917561808552842052380912
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.80853802086032397874537401640150661606715023577408481734572431584309477634613
Short name T420
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Oct 29 02:06:35 PM PDT 23
Finished Oct 29 02:06:37 PM PDT 23
Peak memory 205872 kb
Host smart-b966461d-8ad5-469a-ad35-0fc03ea82972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80853802086032397874537401640150661606715023577408481734572431584309477634613 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.edn_genbits.80853802086032397874537401640150661606715023577408481734572431584309477634613
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.86438765057305394712446337682150037948755680450943659177892943113771346145634
Short name T415
Test name
Test status
Simulation time 18439183 ps
CPU time 1.12 seconds
Started Oct 29 02:06:58 PM PDT 23
Finished Oct 29 02:07:00 PM PDT 23
Peak memory 222168 kb
Host smart-540b4b0c-7c3c-4cbc-abb8-c14c2b1d93a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86438765057305394712446337682150037948755680450943659177892943113771346145634 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.edn_intr.86438765057305394712446337682150037948755680450943659177892943113771346145634
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.44548038249059395984314308331629756367977423532700659746942868188086692535367
Short name T94
Test name
Test status
Simulation time 11759183 ps
CPU time 0.85 seconds
Started Oct 29 02:06:34 PM PDT 23
Finished Oct 29 02:06:36 PM PDT 23
Peak memory 205300 kb
Host smart-df22aa9e-d7ee-464e-a1f8-22fd978769e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44548038249059395984314308331629756367977423532700659746942868188086692535367 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.edn_regwen.44548038249059395984314308331629756367977423532700659746942868188086692535367
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.66360354516117410584719102706021821936035575354320855073032149324826477144529
Short name T51
Test name
Test status
Simulation time 717215632 ps
CPU time 5.97 seconds
Started Oct 29 02:06:56 PM PDT 23
Finished Oct 29 02:07:03 PM PDT 23
Peak memory 234076 kb
Host smart-b3509169-2879-4c7e-a131-9ed65a4a88b6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66360354516117410584719102706021821936035575354320855073032149324826477144529 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.edn_sec_cm.66360354516117410584719102706021821936035575354320855073032149324826477144529
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.106869648464381871759530039417912427407588193611267222551902045560251480217013
Short name T438
Test name
Test status
Simulation time 13059183 ps
CPU time 0.89 seconds
Started Oct 29 02:06:19 PM PDT 23
Finished Oct 29 02:06:20 PM PDT 23
Peak memory 205264 kb
Host smart-ad04d3ac-36e6-4b70-847d-33471e6f03d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106869648464381871759530039417912427407588193611267222551902045560251480217013 -assert nopostproc +UVM_TESTNAME=edn_smok
e_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.edn_smoke.106869648464381871759530039417912427407588193611267222551902045560251480217013
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.99055291321519651948771092075492359744043855923384341014102297427304889012553
Short name T356
Test name
Test status
Simulation time 154489183 ps
CPU time 3.85 seconds
Started Oct 29 02:06:32 PM PDT 23
Finished Oct 29 02:06:36 PM PDT 23
Peak memory 206308 kb
Host smart-c2e9cdf8-e625-466e-b5d6-e3746d29d5c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99055291321519651948771092075492359744043855923384341014102297427304889012553 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.99055291321519651948771092075492359744043855923384341014102297427304889012553
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.35072236945044018179656576520894542909591079954348300230612080651625962716559
Short name T681
Test name
Test status
Simulation time 41708099183 ps
CPU time 1039.92 seconds
Started Oct 29 02:06:32 PM PDT 23
Finished Oct 29 02:23:52 PM PDT 23
Peak memory 215848 kb
Host smart-71291188-a1c9-4a2a-b9d4-166c26e6c5af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350722369450440181796565765
20894542909591079954348300230612080651625962716559 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.350722369450
44018179656576520894542909591079954348300230612080651625962716559
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.61453902117339712794026121258230724458974243483473601544156755028372515755971
Short name T404
Test name
Test status
Simulation time 18259183 ps
CPU time 0.98 seconds
Started Oct 29 02:07:37 PM PDT 23
Finished Oct 29 02:07:39 PM PDT 23
Peak memory 205612 kb
Host smart-bd528322-9847-4628-8206-3d0d1c53e438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61453902117339712794026121258230724458974243483473601544156755028372515755971 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 30.edn_alert.61453902117339712794026121258230724458974243483473601544156755028372515755971
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.94393960084445642672272661751850857465146766237264488476384569114352012064358
Short name T957
Test name
Test status
Simulation time 28184990 ps
CPU time 0.86 seconds
Started Oct 29 02:07:26 PM PDT 23
Finished Oct 29 02:07:28 PM PDT 23
Peak memory 205472 kb
Host smart-b85df2f7-6e71-446c-a8e0-9391d2776b9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94393960084445642672272661751850857465146766237264488476384569114352012064358 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.edn_alert_test.94393960084445642672272661751850857465146766237264488476384569114352012064358
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.75731656136574399642723535766935976354842389683933652773354899146528903742994
Short name T780
Test name
Test status
Simulation time 12219183 ps
CPU time 0.87 seconds
Started Oct 29 02:07:22 PM PDT 23
Finished Oct 29 02:07:25 PM PDT 23
Peak memory 214900 kb
Host smart-0f1b1990-49c8-4507-8c8f-7250317d616d
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75731656136574399642723535766935976354842389683933652773354899146528903742994 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.edn_disable.75731656136574399642723535766935976354842389683933652773354899146528903742994
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.89964823429372745143932974946764103317000202299372302704526571628899530824020
Short name T512
Test name
Test status
Simulation time 17319183 ps
CPU time 0.98 seconds
Started Oct 29 02:07:21 PM PDT 23
Finished Oct 29 02:07:25 PM PDT 23
Peak memory 214936 kb
Host smart-5e3593cb-14ed-4bfa-b065-53690555f6e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89964823429372745143932974946764103317000202299372302704526571628899530824020 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable_auto_req_mode.8996482342937274514393297494676410331700020229937230270452
6571628899530824020
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_genbits.86559183573598113403785095312294616534701608059916653648116389322684449944206
Short name T707
Test name
Test status
Simulation time 17999183 ps
CPU time 1.04 seconds
Started Oct 29 02:07:32 PM PDT 23
Finished Oct 29 02:07:34 PM PDT 23
Peak memory 205816 kb
Host smart-32a549f1-af10-4e13-afba-5f3d4a73fb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86559183573598113403785095312294616534701608059916653648116389322684449944206 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.edn_genbits.86559183573598113403785095312294616534701608059916653648116389322684449944206
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.94225832407859503055918014595897809762161827030366001669441967876053053878945
Short name T632
Test name
Test status
Simulation time 18439183 ps
CPU time 1.15 seconds
Started Oct 29 02:08:02 PM PDT 23
Finished Oct 29 02:08:03 PM PDT 23
Peak memory 222280 kb
Host smart-2db93360-5b48-48c9-87d3-da27fc6af2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94225832407859503055918014595897809762161827030366001669441967876053053878945 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.edn_intr.94225832407859503055918014595897809762161827030366001669441967876053053878945
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.22361362670633529765134592437942381919705868092831203736788968078415368106144
Short name T883
Test name
Test status
Simulation time 13059183 ps
CPU time 0.88 seconds
Started Oct 29 02:07:29 PM PDT 23
Finished Oct 29 02:07:31 PM PDT 23
Peak memory 205280 kb
Host smart-c9e57b5b-25a8-4bda-b87e-7b0181ceccc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22361362670633529765134592437942381919705868092831203736788968078415368106144 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 30.edn_smoke.22361362670633529765134592437942381919705868092831203736788968078415368106144
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.8255203573926566122496997576937858244041141052980259321567214794311494669493
Short name T822
Test name
Test status
Simulation time 154489183 ps
CPU time 3.92 seconds
Started Oct 29 02:08:02 PM PDT 23
Finished Oct 29 02:08:06 PM PDT 23
Peak memory 206364 kb
Host smart-cc499648-66d0-4a29-b376-8a7db4c1b29a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8255203573926566122496997576937858244041141052980259321567214794311494669493 -assert nopost
proc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.8255203573926566122496997576937858244041141052980259321567214794311494669493
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.69177257735311453419195239049160166285345063433338946997056178880182158126064
Short name T397
Test name
Test status
Simulation time 41708099183 ps
CPU time 1042.56 seconds
Started Oct 29 02:09:46 PM PDT 23
Finished Oct 29 02:27:10 PM PDT 23
Peak memory 215936 kb
Host smart-8c6dbe7d-e360-4cc1-af7b-6c0877c6ba21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691772577353114534191952390
49160166285345063433338946997056178880182158126064 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.69177257735
311453419195239049160166285345063433338946997056178880182158126064
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.16651053141819458036088709233925646404371901157879413950922190388157998243476
Short name T15
Test name
Test status
Simulation time 18259183 ps
CPU time 0.98 seconds
Started Oct 29 02:07:35 PM PDT 23
Finished Oct 29 02:07:37 PM PDT 23
Peak memory 205440 kb
Host smart-7eada1f3-1835-4f7e-92b1-830df6b50eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16651053141819458036088709233925646404371901157879413950922190388157998243476 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 31.edn_alert.16651053141819458036088709233925646404371901157879413950922190388157998243476
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.99725574283572727126334501488328615106049757572961165197690661968757391396215
Short name T411
Test name
Test status
Simulation time 28184990 ps
CPU time 0.87 seconds
Started Oct 29 02:07:39 PM PDT 23
Finished Oct 29 02:07:40 PM PDT 23
Peak memory 205500 kb
Host smart-3d1350a8-30d8-41ee-a0f5-c56cfefee6be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99725574283572727126334501488328615106049757572961165197690661968757391396215 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.edn_alert_test.99725574283572727126334501488328615106049757572961165197690661968757391396215
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.16566922927400233874985550304938408668046896732012835354803426423461928900384
Short name T702
Test name
Test status
Simulation time 12219183 ps
CPU time 0.91 seconds
Started Oct 29 02:07:32 PM PDT 23
Finished Oct 29 02:07:34 PM PDT 23
Peak memory 214924 kb
Host smart-3b20d55a-3167-49c2-8b40-207a234d3e08
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16566922927400233874985550304938408668046896732012835354803426423461928900384 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.edn_disable.16566922927400233874985550304938408668046896732012835354803426423461928900384
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.19173973717504995690074673128830518820911564212740679760068227397175506074136
Short name T610
Test name
Test status
Simulation time 17319183 ps
CPU time 0.95 seconds
Started Oct 29 02:07:36 PM PDT 23
Finished Oct 29 02:07:37 PM PDT 23
Peak memory 214904 kb
Host smart-fb1b40cb-fa13-4ed7-8969-0cb5249cd52f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19173973717504995690074673128830518820911564212740679760068227397175506074136 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable_auto_req_mode.1917397371750499569007467312883051882091156421274067976006
8227397175506074136
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.105268234724506735337986646550567093267995449766368744880653613146909458560705
Short name T820
Test name
Test status
Simulation time 24963823 ps
CPU time 1.19 seconds
Started Oct 29 02:07:26 PM PDT 23
Finished Oct 29 02:07:29 PM PDT 23
Peak memory 230440 kb
Host smart-ab19e7f0-2e67-424a-b8d9-99f5bd5a9ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105268234724506735337986646550567093267995449766368744880653613146909458560705 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.edn_err.105268234724506735337986646550567093267995449766368744880653613146909458560705
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.25428939962026150736494053072788742249623214486287720588479720838883840274832
Short name T640
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Oct 29 02:07:38 PM PDT 23
Finished Oct 29 02:07:39 PM PDT 23
Peak memory 205812 kb
Host smart-7b11d4e0-5e4e-4220-b46f-f1273307133e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25428939962026150736494053072788742249623214486287720588479720838883840274832 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.edn_genbits.25428939962026150736494053072788742249623214486287720588479720838883840274832
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.34455530238949930817301974236446872729464139345320357138261864098704788025908
Short name T389
Test name
Test status
Simulation time 18439183 ps
CPU time 1.12 seconds
Started Oct 29 02:07:23 PM PDT 23
Finished Oct 29 02:07:26 PM PDT 23
Peak memory 222304 kb
Host smart-8eb77638-2539-4b2e-80d1-2aa557ad8fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34455530238949930817301974236446872729464139345320357138261864098704788025908 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.edn_intr.34455530238949930817301974236446872729464139345320357138261864098704788025908
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.560702698723967271201673175325225138638862392299894997258003268060336548915
Short name T689
Test name
Test status
Simulation time 13059183 ps
CPU time 0.89 seconds
Started Oct 29 02:07:23 PM PDT 23
Finished Oct 29 02:07:25 PM PDT 23
Peak memory 205348 kb
Host smart-684f622e-54b0-43d3-bafd-4f27b6430f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560702698723967271201673175325225138638862392299894997258003268060336548915 -assert nopostproc +UVM_TESTNAME=edn_smoke_t
est +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.edn_smoke.560702698723967271201673175325225138638862392299894997258003268060336548915
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.102086122882993373021959447117025363870960324051333343395813502160165088076523
Short name T852
Test name
Test status
Simulation time 154489183 ps
CPU time 4 seconds
Started Oct 29 02:07:28 PM PDT 23
Finished Oct 29 02:07:33 PM PDT 23
Peak memory 206320 kb
Host smart-01a8b4c2-12d9-4b41-ae54-ff0b92f53395
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102086122882993373021959447117025363870960324051333343395813502160165088076523 -assert nopo
stproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.102086122882993373021959447117025363870960324051333343395813502160165088076523
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.19432954005189917600241741610616066376620453843495436273864690131828873773001
Short name T624
Test name
Test status
Simulation time 41708099183 ps
CPU time 1081.03 seconds
Started Oct 29 02:07:23 PM PDT 23
Finished Oct 29 02:25:26 PM PDT 23
Peak memory 215860 kb
Host smart-817ab36c-6858-4bed-97c9-566d6a0e6da6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194329540051899176002417416
10616066376620453843495436273864690131828873773001 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.19432954005
189917600241741610616066376620453843495436273864690131828873773001
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.107019965042741087008491217398513905017525111198794598064380198493297564462513
Short name T908
Test name
Test status
Simulation time 18259183 ps
CPU time 0.95 seconds
Started Oct 29 02:07:38 PM PDT 23
Finished Oct 29 02:07:39 PM PDT 23
Peak memory 205556 kb
Host smart-09ca9317-3745-4c7b-a1bb-537c04d3e24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107019965042741087008491217398513905017525111198794598064380198493297564462513 -assert nopostproc +UVM_TESTNAME=edn_aler
t_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 32.edn_alert.107019965042741087008491217398513905017525111198794598064380198493297564462513
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.57838749971273350305026713575779447187303124096278805836690601959311457456740
Short name T492
Test name
Test status
Simulation time 28184990 ps
CPU time 0.86 seconds
Started Oct 29 02:07:37 PM PDT 23
Finished Oct 29 02:07:39 PM PDT 23
Peak memory 205468 kb
Host smart-98901d1a-a836-432c-9c98-5589d79531e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57838749971273350305026713575779447187303124096278805836690601959311457456740 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.edn_alert_test.57838749971273350305026713575779447187303124096278805836690601959311457456740
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.33817022048276629470826046428850549853832233393179881066248595906597651601397
Short name T453
Test name
Test status
Simulation time 12219183 ps
CPU time 0.85 seconds
Started Oct 29 02:07:33 PM PDT 23
Finished Oct 29 02:07:34 PM PDT 23
Peak memory 214852 kb
Host smart-c0731514-65b2-4b3f-9e9d-32a27d4c2c70
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33817022048276629470826046428850549853832233393179881066248595906597651601397 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.edn_disable.33817022048276629470826046428850549853832233393179881066248595906597651601397
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.46245353811407523194961286491484379809995044827023683925840769519752503487066
Short name T323
Test name
Test status
Simulation time 17319183 ps
CPU time 0.92 seconds
Started Oct 29 02:07:31 PM PDT 23
Finished Oct 29 02:07:33 PM PDT 23
Peak memory 214876 kb
Host smart-d155bf72-cd9d-4f2f-ad8a-f69b8da60f09
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46245353811407523194961286491484379809995044827023683925840769519752503487066 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable_auto_req_mode.4624535381140752319496128649148437980999504482702368392584
0769519752503487066
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.110216381008609945353789832478382815972538309653739200029741209698834296235022
Short name T612
Test name
Test status
Simulation time 24963823 ps
CPU time 1.11 seconds
Started Oct 29 02:07:25 PM PDT 23
Finished Oct 29 02:07:27 PM PDT 23
Peak memory 230424 kb
Host smart-b63c3459-238f-4b13-b701-20c1987e0cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110216381008609945353789832478382815972538309653739200029741209698834296235022 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.edn_err.110216381008609945353789832478382815972538309653739200029741209698834296235022
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.77534536747832610453049171184993356187097065500264276516736754338267104383192
Short name T290
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:07:33 PM PDT 23
Finished Oct 29 02:07:34 PM PDT 23
Peak memory 205712 kb
Host smart-c36c21b6-ec80-4f77-b162-fe20a0615c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77534536747832610453049171184993356187097065500264276516736754338267104383192 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.edn_genbits.77534536747832610453049171184993356187097065500264276516736754338267104383192
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.83935458428980047737617551980049205366290470264599276626647235006062966055422
Short name T32
Test name
Test status
Simulation time 18439183 ps
CPU time 1.13 seconds
Started Oct 29 02:07:21 PM PDT 23
Finished Oct 29 02:07:25 PM PDT 23
Peak memory 222296 kb
Host smart-4fcd9be2-d766-4d3f-b31e-3a1785ccfe8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83935458428980047737617551980049205366290470264599276626647235006062966055422 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.edn_intr.83935458428980047737617551980049205366290470264599276626647235006062966055422
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.112494779953963193235449857924039894122737986306779419883658552645968643109052
Short name T90
Test name
Test status
Simulation time 13059183 ps
CPU time 0.88 seconds
Started Oct 29 02:07:27 PM PDT 23
Finished Oct 29 02:07:29 PM PDT 23
Peak memory 205328 kb
Host smart-2409b467-7208-4e04-a9a0-97eae717c615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112494779953963193235449857924039894122737986306779419883658552645968643109052 -assert nopostproc +UVM_TESTNAME=edn_smok
e_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 32.edn_smoke.112494779953963193235449857924039894122737986306779419883658552645968643109052
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.25371962667807623012851868724735908172382564263466857245137341587929208550222
Short name T439
Test name
Test status
Simulation time 154489183 ps
CPU time 3.94 seconds
Started Oct 29 02:07:32 PM PDT 23
Finished Oct 29 02:07:36 PM PDT 23
Peak memory 206344 kb
Host smart-4d5f3e70-16f9-419d-a60a-f0d037afcdaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25371962667807623012851868724735908172382564263466857245137341587929208550222 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.25371962667807623012851868724735908172382564263466857245137341587929208550222
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.109658088902489039112127977303843411403800363908640413420146115082818567420928
Short name T486
Test name
Test status
Simulation time 41708099183 ps
CPU time 1070.41 seconds
Started Oct 29 02:07:23 PM PDT 23
Finished Oct 29 02:25:15 PM PDT 23
Peak memory 215876 kb
Host smart-9cff7de8-dc1f-4f96-97c7-9b616443649c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109658088902489039112127977
303843411403800363908640413420146115082818567420928 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.1096580889
02489039112127977303843411403800363908640413420146115082818567420928
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.40944769595203131811230157646888732746358225817440458452766878712582973355758
Short name T950
Test name
Test status
Simulation time 18259183 ps
CPU time 0.96 seconds
Started Oct 29 02:07:19 PM PDT 23
Finished Oct 29 02:07:20 PM PDT 23
Peak memory 205584 kb
Host smart-880516b0-3c71-49a7-ad52-83fffcab63ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40944769595203131811230157646888732746358225817440458452766878712582973355758 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 33.edn_alert.40944769595203131811230157646888732746358225817440458452766878712582973355758
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.100345058519068101948899055731581811061673703325722870529634482559476740757947
Short name T286
Test name
Test status
Simulation time 28184990 ps
CPU time 0.9 seconds
Started Oct 29 02:07:36 PM PDT 23
Finished Oct 29 02:07:38 PM PDT 23
Peak memory 205528 kb
Host smart-0d2a53ea-c6f4-4272-8f0c-a55312019b28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100345058519068101948899055731581811061673703325722870529634482559476740757947 -assert nopostp
roc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 33.edn_alert_test.100345058519068101948899055731581811061673703325722870529634482559476740757947
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.59969376779479660999393835705005294459620229624918152123666923034479332663043
Short name T747
Test name
Test status
Simulation time 12219183 ps
CPU time 0.86 seconds
Started Oct 29 02:07:34 PM PDT 23
Finished Oct 29 02:07:35 PM PDT 23
Peak memory 214864 kb
Host smart-6522b62e-2e75-407f-9c33-28ad14a52dd6
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59969376779479660999393835705005294459620229624918152123666923034479332663043 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.edn_disable.59969376779479660999393835705005294459620229624918152123666923034479332663043
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.53570599265330303828752410283922537481653656986537276693481580232862215786061
Short name T697
Test name
Test status
Simulation time 17319183 ps
CPU time 0.92 seconds
Started Oct 29 02:07:36 PM PDT 23
Finished Oct 29 02:07:37 PM PDT 23
Peak memory 214940 kb
Host smart-f2177523-c8b0-48df-8b8d-8a04692eea04
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53570599265330303828752410283922537481653656986537276693481580232862215786061 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable_auto_req_mode.5357059926533030382875241028392253748165365698653727669348
1580232862215786061
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.41506900029620160131369622603324827649978638818193247880251405106682553402004
Short name T252
Test name
Test status
Simulation time 24963823 ps
CPU time 1.1 seconds
Started Oct 29 02:07:25 PM PDT 23
Finished Oct 29 02:07:27 PM PDT 23
Peak memory 230420 kb
Host smart-2c9f894d-d79b-484b-b624-0d704dd769f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41506900029620160131369622603324827649978638818193247880251405106682553402004 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.edn_err.41506900029620160131369622603324827649978638818193247880251405106682553402004
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.31383187046298411527174795057935574195797458095117792537236083774042620911745
Short name T240
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Oct 29 02:07:38 PM PDT 23
Finished Oct 29 02:07:39 PM PDT 23
Peak memory 205856 kb
Host smart-8ebf1f8e-a49d-476b-80d2-23f062d0d7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31383187046298411527174795057935574195797458095117792537236083774042620911745 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.edn_genbits.31383187046298411527174795057935574195797458095117792537236083774042620911745
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.112239754494721324463225766784163069894501493573200354015895975764932104242761
Short name T324
Test name
Test status
Simulation time 18439183 ps
CPU time 1.06 seconds
Started Oct 29 02:07:34 PM PDT 23
Finished Oct 29 02:07:35 PM PDT 23
Peak memory 222104 kb
Host smart-12405a45-6832-4f12-9c85-ff24f2aeed39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112239754494721324463225766784163069894501493573200354015895975764932104242761 -assert nopostproc +UVM_TESTNAME=edn_intr
_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.edn_intr.112239754494721324463225766784163069894501493573200354015895975764932104242761
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.50631707762889684678340607581118758888776050804832784545962347245412370206184
Short name T548
Test name
Test status
Simulation time 13059183 ps
CPU time 0.86 seconds
Started Oct 29 02:07:37 PM PDT 23
Finished Oct 29 02:07:38 PM PDT 23
Peak memory 205332 kb
Host smart-8793c5e2-0237-441f-ab28-e64dd998cc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50631707762889684678340607581118758888776050804832784545962347245412370206184 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 33.edn_smoke.50631707762889684678340607581118758888776050804832784545962347245412370206184
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.60158781627622090034236748863373156901578393701895635875712520438905926794043
Short name T914
Test name
Test status
Simulation time 154489183 ps
CPU time 3.93 seconds
Started Oct 29 02:08:04 PM PDT 23
Finished Oct 29 02:08:08 PM PDT 23
Peak memory 206376 kb
Host smart-50b9b43d-6c64-404a-b86f-7bf9cea779fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60158781627622090034236748863373156901578393701895635875712520438905926794043 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.60158781627622090034236748863373156901578393701895635875712520438905926794043
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.60605858729264215653162478083394885479569429982328681305534412296576131473861
Short name T721
Test name
Test status
Simulation time 41708099183 ps
CPU time 1043.49 seconds
Started Oct 29 02:07:35 PM PDT 23
Finished Oct 29 02:25:00 PM PDT 23
Peak memory 215740 kb
Host smart-2d1c01c9-4dd4-462a-9f22-fa3cb8645490
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606058587292642156531624780
83394885479569429982328681305534412296576131473861 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.60605858729
264215653162478083394885479569429982328681305534412296576131473861
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.46415175388300456870582769725841005117937263708705696121383565488456277046977
Short name T358
Test name
Test status
Simulation time 18259183 ps
CPU time 0.98 seconds
Started Oct 29 02:07:35 PM PDT 23
Finished Oct 29 02:07:37 PM PDT 23
Peak memory 205580 kb
Host smart-36554695-17e2-44c9-a3b1-cd7864db2884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46415175388300456870582769725841005117937263708705696121383565488456277046977 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 34.edn_alert.46415175388300456870582769725841005117937263708705696121383565488456277046977
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.4679530881768658067906468339253151431040820755783322135955551059035221148525
Short name T503
Test name
Test status
Simulation time 28184990 ps
CPU time 0.86 seconds
Started Oct 29 02:07:21 PM PDT 23
Finished Oct 29 02:07:25 PM PDT 23
Peak memory 205372 kb
Host smart-117e4740-67d6-48cb-a7e8-b83fae866fa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4679530881768658067906468339253151431040820755783322135955551059035221148525 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.edn_alert_test.4679530881768658067906468339253151431040820755783322135955551059035221148525
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.72450237036676773993374199491738702903874819820659297112951054886620898409505
Short name T975
Test name
Test status
Simulation time 12219183 ps
CPU time 0.9 seconds
Started Oct 29 02:08:02 PM PDT 23
Finished Oct 29 02:08:03 PM PDT 23
Peak memory 214824 kb
Host smart-b7f14c69-198d-4d78-a536-02497c1360df
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72450237036676773993374199491738702903874819820659297112951054886620898409505 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.edn_disable.72450237036676773993374199491738702903874819820659297112951054886620898409505
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.8740295719253074700368115496497113778001998654330302412851061740739574993684
Short name T792
Test name
Test status
Simulation time 17319183 ps
CPU time 0.95 seconds
Started Oct 29 02:07:24 PM PDT 23
Finished Oct 29 02:07:25 PM PDT 23
Peak memory 214916 kb
Host smart-8c849570-8f4a-46de-a47f-e7533c101f01
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8740295719253074700368115496497113778001998654330302412851061740739574993684 -assert nopostproc
+UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable_auto_req_mode.87402957192530747003681154964971137780019986543303024128510
61740739574993684
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.80049672143162575343179436154866450438630121467919592520769281307900175151990
Short name T462
Test name
Test status
Simulation time 24963823 ps
CPU time 1.11 seconds
Started Oct 29 02:07:24 PM PDT 23
Finished Oct 29 02:07:26 PM PDT 23
Peak memory 230432 kb
Host smart-99b1a1f6-00e0-4112-94fc-3c2de08ae3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80049672143162575343179436154866450438630121467919592520769281307900175151990 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.edn_err.80049672143162575343179436154866450438630121467919592520769281307900175151990
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.25091749551436388444108027581104807414049226793192829543096823127136250019564
Short name T536
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Oct 29 02:07:24 PM PDT 23
Finished Oct 29 02:07:26 PM PDT 23
Peak memory 205876 kb
Host smart-84934a8f-e28f-4854-8caa-c6ee3c59edf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25091749551436388444108027581104807414049226793192829543096823127136250019564 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.edn_genbits.25091749551436388444108027581104807414049226793192829543096823127136250019564
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.73888075015471957783758807196703030575970705781494126208566109106933037661983
Short name T551
Test name
Test status
Simulation time 18439183 ps
CPU time 1.17 seconds
Started Oct 29 02:07:34 PM PDT 23
Finished Oct 29 02:07:36 PM PDT 23
Peak memory 222240 kb
Host smart-4beb0176-d99d-418c-aa9e-367945024aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73888075015471957783758807196703030575970705781494126208566109106933037661983 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.edn_intr.73888075015471957783758807196703030575970705781494126208566109106933037661983
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.90764529327248156270372978846473257879577774406982232661326590989057025823974
Short name T459
Test name
Test status
Simulation time 13059183 ps
CPU time 0.86 seconds
Started Oct 29 02:07:34 PM PDT 23
Finished Oct 29 02:07:35 PM PDT 23
Peak memory 205228 kb
Host smart-7668cd45-87f2-4af1-b252-2e121bbb70ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90764529327248156270372978846473257879577774406982232661326590989057025823974 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 34.edn_smoke.90764529327248156270372978846473257879577774406982232661326590989057025823974
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.85763903794408149022412735040500186628991670627924025679278360100769733155486
Short name T523
Test name
Test status
Simulation time 154489183 ps
CPU time 4.09 seconds
Started Oct 29 02:07:25 PM PDT 23
Finished Oct 29 02:07:30 PM PDT 23
Peak memory 206344 kb
Host smart-fcb08d9a-62e7-44bf-a2bc-6cb2fbbd9065
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85763903794408149022412735040500186628991670627924025679278360100769733155486 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.85763903794408149022412735040500186628991670627924025679278360100769733155486
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.48035163148450243910358380293487914664827401671340497962208460092734073931543
Short name T562
Test name
Test status
Simulation time 41708099183 ps
CPU time 1083.68 seconds
Started Oct 29 02:07:34 PM PDT 23
Finished Oct 29 02:25:38 PM PDT 23
Peak memory 215840 kb
Host smart-33fb85b5-e043-43a8-bc95-fa3332c2c440
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480351631484502439103583802
93487914664827401671340497962208460092734073931543 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.48035163148
450243910358380293487914664827401671340497962208460092734073931543
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.80859659579331036484257502480746896040315600061845334940638407510227435265534
Short name T734
Test name
Test status
Simulation time 18259183 ps
CPU time 1 seconds
Started Oct 29 02:07:37 PM PDT 23
Finished Oct 29 02:07:39 PM PDT 23
Peak memory 205576 kb
Host smart-62ecf97b-49d7-46b2-99fa-d7d68840a363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80859659579331036484257502480746896040315600061845334940638407510227435265534 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 35.edn_alert.80859659579331036484257502480746896040315600061845334940638407510227435265534
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.89144011458546979426805678894852448391534569785118491727911390059348858939694
Short name T60
Test name
Test status
Simulation time 28184990 ps
CPU time 0.87 seconds
Started Oct 29 02:07:38 PM PDT 23
Finished Oct 29 02:07:39 PM PDT 23
Peak memory 205476 kb
Host smart-5a10a527-de7b-449a-af76-1f1a03cbc615
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89144011458546979426805678894852448391534569785118491727911390059348858939694 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.edn_alert_test.89144011458546979426805678894852448391534569785118491727911390059348858939694
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.38415471870866681120050925028620846802100790445362340778969517211874774874733
Short name T738
Test name
Test status
Simulation time 12219183 ps
CPU time 0.88 seconds
Started Oct 29 02:07:28 PM PDT 23
Finished Oct 29 02:07:29 PM PDT 23
Peak memory 214824 kb
Host smart-be9ec61f-bb07-4753-9178-16fa9b481200
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38415471870866681120050925028620846802100790445362340778969517211874774874733 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.edn_disable.38415471870866681120050925028620846802100790445362340778969517211874774874733
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.81244718020207400348680759787370037725203269128101492625943711971979354001608
Short name T872
Test name
Test status
Simulation time 17319183 ps
CPU time 0.93 seconds
Started Oct 29 02:07:37 PM PDT 23
Finished Oct 29 02:07:39 PM PDT 23
Peak memory 214860 kb
Host smart-2b7c1771-dda3-4de6-83a9-5ed53c13961b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81244718020207400348680759787370037725203269128101492625943711971979354001608 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable_auto_req_mode.8124471802020740034868075978737003772520326912810149262594
3711971979354001608
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.95027821860816084583805148749879645029213586518855364699592527981051023661165
Short name T762
Test name
Test status
Simulation time 24963823 ps
CPU time 1.14 seconds
Started Oct 29 02:08:00 PM PDT 23
Finished Oct 29 02:08:02 PM PDT 23
Peak memory 230452 kb
Host smart-cdec86ef-11b2-464e-815f-6b8d8bb32260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95027821860816084583805148749879645029213586518855364699592527981051023661165 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.edn_err.95027821860816084583805148749879645029213586518855364699592527981051023661165
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.56960229380154645569941176878520188283673909085021658833798762847259044267003
Short name T727
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Oct 29 02:07:32 PM PDT 23
Finished Oct 29 02:07:34 PM PDT 23
Peak memory 205888 kb
Host smart-0b1584ab-7441-41da-9118-ed15deb050f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56960229380154645569941176878520188283673909085021658833798762847259044267003 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.edn_genbits.56960229380154645569941176878520188283673909085021658833798762847259044267003
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.97965838065003503299618114953223347778641191803949304160624443747927236102615
Short name T771
Test name
Test status
Simulation time 18439183 ps
CPU time 1.16 seconds
Started Oct 29 02:07:23 PM PDT 23
Finished Oct 29 02:07:26 PM PDT 23
Peak memory 222248 kb
Host smart-fb4a989e-3f3c-4ef6-b628-878a94382dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97965838065003503299618114953223347778641191803949304160624443747927236102615 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.edn_intr.97965838065003503299618114953223347778641191803949304160624443747927236102615
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.47410897686367818707625130671589705603339515064788488838993270905044968564556
Short name T392
Test name
Test status
Simulation time 13059183 ps
CPU time 0.89 seconds
Started Oct 29 02:07:38 PM PDT 23
Finished Oct 29 02:07:40 PM PDT 23
Peak memory 205352 kb
Host smart-767f94c5-d706-4567-a053-b283692ce375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47410897686367818707625130671589705603339515064788488838993270905044968564556 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 35.edn_smoke.47410897686367818707625130671589705603339515064788488838993270905044968564556
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.115416887434524339635867056125631856890929539156041574063492507387430771435608
Short name T695
Test name
Test status
Simulation time 154489183 ps
CPU time 4.08 seconds
Started Oct 29 02:07:21 PM PDT 23
Finished Oct 29 02:07:28 PM PDT 23
Peak memory 206312 kb
Host smart-3bf5aec1-2f24-4433-93b1-19a37831994f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115416887434524339635867056125631856890929539156041574063492507387430771435608 -assert nopo
stproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.115416887434524339635867056125631856890929539156041574063492507387430771435608
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.31416236090808992649840624149996383854346071345574045571423713355864437856559
Short name T598
Test name
Test status
Simulation time 41708099183 ps
CPU time 1027.13 seconds
Started Oct 29 02:07:46 PM PDT 23
Finished Oct 29 02:24:54 PM PDT 23
Peak memory 215832 kb
Host smart-5d6c1866-aa5d-4829-bc0d-2769b24ca3f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314162360908089926498406241
49996383854346071345574045571423713355864437856559 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.31416236090
808992649840624149996383854346071345574045571423713355864437856559
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.21474272518683906621863248503392493143714224339484115366308788822851838446383
Short name T687
Test name
Test status
Simulation time 18259183 ps
CPU time 0.97 seconds
Started Oct 29 02:08:03 PM PDT 23
Finished Oct 29 02:08:04 PM PDT 23
Peak memory 205616 kb
Host smart-69b58aa7-fd8f-4282-9b0b-d795b9249c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21474272518683906621863248503392493143714224339484115366308788822851838446383 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 36.edn_alert.21474272518683906621863248503392493143714224339484115366308788822851838446383
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.3141685915828880984034191236342314882810647545904976478820353958823068102821
Short name T46
Test name
Test status
Simulation time 28184990 ps
CPU time 0.9 seconds
Started Oct 29 02:08:08 PM PDT 23
Finished Oct 29 02:08:09 PM PDT 23
Peak memory 205472 kb
Host smart-52978c1b-d16f-4048-9435-b16830d19443
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141685915828880984034191236342314882810647545904976478820353958823068102821 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.edn_alert_test.3141685915828880984034191236342314882810647545904976478820353958823068102821
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.83924121236010257199466049666465592179801046831912120972266418308588598785605
Short name T555
Test name
Test status
Simulation time 12219183 ps
CPU time 0.87 seconds
Started Oct 29 02:08:03 PM PDT 23
Finished Oct 29 02:08:04 PM PDT 23
Peak memory 214868 kb
Host smart-5e332463-d5fe-4b89-b8e5-cc5bb3fa1062
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83924121236010257199466049666465592179801046831912120972266418308588598785605 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.edn_disable.83924121236010257199466049666465592179801046831912120972266418308588598785605
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.92628937007021849301604007072194982543739547975543180396343104705181225569628
Short name T757
Test name
Test status
Simulation time 17319183 ps
CPU time 0.94 seconds
Started Oct 29 02:08:12 PM PDT 23
Finished Oct 29 02:08:13 PM PDT 23
Peak memory 214864 kb
Host smart-b1504fd7-2eb4-403b-9663-35dc250bb705
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92628937007021849301604007072194982543739547975543180396343104705181225569628 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable_auto_req_mode.9262893700702184930160400707219498254373954797554318039634
3104705181225569628
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.101419994384088355975403045275032307776495173565796924824220033010416426403336
Short name T877
Test name
Test status
Simulation time 24963823 ps
CPU time 1.11 seconds
Started Oct 29 02:08:04 PM PDT 23
Finished Oct 29 02:08:05 PM PDT 23
Peak memory 230368 kb
Host smart-37db4022-3894-40ae-a8e1-2adba0ba95dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101419994384088355975403045275032307776495173565796924824220033010416426403336 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.edn_err.101419994384088355975403045275032307776495173565796924824220033010416426403336
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.82101849053726909509703976782910935829567344756664924668112265070610362373045
Short name T412
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:08:03 PM PDT 23
Finished Oct 29 02:08:05 PM PDT 23
Peak memory 205824 kb
Host smart-9347783c-f746-4e10-9a29-16ea218b02ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82101849053726909509703976782910935829567344756664924668112265070610362373045 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.edn_genbits.82101849053726909509703976782910935829567344756664924668112265070610362373045
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.36735218611469568531373491236281311417409605771804725827211439145311292460506
Short name T330
Test name
Test status
Simulation time 18439183 ps
CPU time 1.19 seconds
Started Oct 29 02:08:06 PM PDT 23
Finished Oct 29 02:08:07 PM PDT 23
Peak memory 222284 kb
Host smart-23e763db-0ea2-4873-98ea-ad5e04c9187f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36735218611469568531373491236281311417409605771804725827211439145311292460506 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.edn_intr.36735218611469568531373491236281311417409605771804725827211439145311292460506
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.88257241353415570992291062513550250123291537200127790884779194288693111337558
Short name T828
Test name
Test status
Simulation time 13059183 ps
CPU time 0.87 seconds
Started Oct 29 02:08:02 PM PDT 23
Finished Oct 29 02:08:03 PM PDT 23
Peak memory 205352 kb
Host smart-bc163e96-fc5a-427e-8845-e0489f4053af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88257241353415570992291062513550250123291537200127790884779194288693111337558 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 36.edn_smoke.88257241353415570992291062513550250123291537200127790884779194288693111337558
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.35548109755410933847023328531705286352643048424733407587932648978783281155715
Short name T659
Test name
Test status
Simulation time 154489183 ps
CPU time 3.96 seconds
Started Oct 29 02:07:44 PM PDT 23
Finished Oct 29 02:07:48 PM PDT 23
Peak memory 206384 kb
Host smart-9bab8906-e6a2-46ad-a5a6-5a01e2466ff6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35548109755410933847023328531705286352643048424733407587932648978783281155715 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.35548109755410933847023328531705286352643048424733407587932648978783281155715
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.94403415840187266434175659842827366952876936406783323341052964379372081138896
Short name T980
Test name
Test status
Simulation time 41708099183 ps
CPU time 1098.87 seconds
Started Oct 29 02:08:06 PM PDT 23
Finished Oct 29 02:26:25 PM PDT 23
Peak memory 215884 kb
Host smart-990fd09d-45e9-4ad4-9b00-451626827fd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944034158401872664341756598
42827366952876936406783323341052964379372081138896 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.94403415840
187266434175659842827366952876936406783323341052964379372081138896
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.58909265909528618167602593820255639729409255543921408194680005523335272894766
Short name T890
Test name
Test status
Simulation time 18259183 ps
CPU time 0.99 seconds
Started Oct 29 02:07:36 PM PDT 23
Finished Oct 29 02:07:37 PM PDT 23
Peak memory 205580 kb
Host smart-d5bb5c82-1420-4b7f-b6fd-add38385ccbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58909265909528618167602593820255639729409255543921408194680005523335272894766 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 37.edn_alert.58909265909528618167602593820255639729409255543921408194680005523335272894766
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.3249917724990201393984448853050421282708225846808910870336281132070655027809
Short name T725
Test name
Test status
Simulation time 28184990 ps
CPU time 0.87 seconds
Started Oct 29 02:07:36 PM PDT 23
Finished Oct 29 02:07:37 PM PDT 23
Peak memory 205512 kb
Host smart-72aa0864-05ed-4065-ac7f-37fa88d35a31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249917724990201393984448853050421282708225846808910870336281132070655027809 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.edn_alert_test.3249917724990201393984448853050421282708225846808910870336281132070655027809
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.33032182329289910279242934534868631861130626149197554638859355675395475814391
Short name T385
Test name
Test status
Simulation time 12219183 ps
CPU time 0.86 seconds
Started Oct 29 02:07:36 PM PDT 23
Finished Oct 29 02:07:37 PM PDT 23
Peak memory 214916 kb
Host smart-fef0475a-376d-4e01-bf50-89834187e4e8
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33032182329289910279242934534868631861130626149197554638859355675395475814391 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.edn_disable.33032182329289910279242934534868631861130626149197554638859355675395475814391
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.60984264354894354529594099011927612473648512585258511825856705921286251874031
Short name T424
Test name
Test status
Simulation time 17319183 ps
CPU time 0.97 seconds
Started Oct 29 02:07:37 PM PDT 23
Finished Oct 29 02:07:39 PM PDT 23
Peak memory 214904 kb
Host smart-34bf03d9-f5d7-43f0-bd4d-3d4727ad4192
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60984264354894354529594099011927612473648512585258511825856705921286251874031 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable_auto_req_mode.6098426435489435452959409901192761247364851258525851182585
6705921286251874031
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.43447053940900976386758149480733136821856718011854145025309104918865945057785
Short name T531
Test name
Test status
Simulation time 24963823 ps
CPU time 1.15 seconds
Started Oct 29 02:07:37 PM PDT 23
Finished Oct 29 02:07:39 PM PDT 23
Peak memory 230484 kb
Host smart-efc23a1a-7cee-4320-886d-38d480120b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43447053940900976386758149480733136821856718011854145025309104918865945057785 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.edn_err.43447053940900976386758149480733136821856718011854145025309104918865945057785
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.100892855218247894703723180643975869502122816394075635893663953306430426497214
Short name T782
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Oct 29 02:07:36 PM PDT 23
Finished Oct 29 02:07:37 PM PDT 23
Peak memory 205848 kb
Host smart-77e3e11f-8fad-4932-a2ef-169c6cdf303d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100892855218247894703723180643975869502122816394075635893663953306430426497214 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 37.edn_genbits.100892855218247894703723180643975869502122816394075635893663953306430426497214
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.55968791122054939933349470368630527741127459907236588388561864497995513219267
Short name T637
Test name
Test status
Simulation time 18439183 ps
CPU time 1.12 seconds
Started Oct 29 02:07:37 PM PDT 23
Finished Oct 29 02:07:39 PM PDT 23
Peak memory 222296 kb
Host smart-23960fc3-26df-4e65-a720-4db9fa1c0053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55968791122054939933349470368630527741127459907236588388561864497995513219267 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.edn_intr.55968791122054939933349470368630527741127459907236588388561864497995513219267
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.37857254643099465818942182517789292637996610124856235325093173205814319037800
Short name T703
Test name
Test status
Simulation time 13059183 ps
CPU time 0.88 seconds
Started Oct 29 02:07:28 PM PDT 23
Finished Oct 29 02:07:30 PM PDT 23
Peak memory 205324 kb
Host smart-62e75b0e-8dd2-46b1-ab6c-fc4fbc2e856c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37857254643099465818942182517789292637996610124856235325093173205814319037800 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 37.edn_smoke.37857254643099465818942182517789292637996610124856235325093173205814319037800
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.56080468964442374035345299062120065854569049340244965334387617082128532441091
Short name T483
Test name
Test status
Simulation time 154489183 ps
CPU time 3.99 seconds
Started Oct 29 02:07:39 PM PDT 23
Finished Oct 29 02:07:43 PM PDT 23
Peak memory 206348 kb
Host smart-d3250b41-e6aa-4a21-af4a-4d0a4c5e8558
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56080468964442374035345299062120065854569049340244965334387617082128532441091 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.56080468964442374035345299062120065854569049340244965334387617082128532441091
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.27715728949088342044966813669527642745074133837484180941243714654860270393979
Short name T633
Test name
Test status
Simulation time 41708099183 ps
CPU time 1062.05 seconds
Started Oct 29 02:07:38 PM PDT 23
Finished Oct 29 02:25:21 PM PDT 23
Peak memory 215828 kb
Host smart-fc0ec9a3-7594-4e01-8b07-ff86f455c6c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277157289490883420449668136
69527642745074133837484180941243714654860270393979 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.27715728949
088342044966813669527642745074133837484180941243714654860270393979
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.98438203949692215077785188935664660715639799723786988154321335675639653606846
Short name T972
Test name
Test status
Simulation time 18259183 ps
CPU time 0.98 seconds
Started Oct 29 02:07:58 PM PDT 23
Finished Oct 29 02:07:59 PM PDT 23
Peak memory 205560 kb
Host smart-e79d520f-4db1-49c9-9000-5c59fc454ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98438203949692215077785188935664660715639799723786988154321335675639653606846 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 38.edn_alert.98438203949692215077785188935664660715639799723786988154321335675639653606846
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.113861626438078997763457444113179026863341817881040277828990653978998176006193
Short name T469
Test name
Test status
Simulation time 28184990 ps
CPU time 0.89 seconds
Started Oct 29 02:07:41 PM PDT 23
Finished Oct 29 02:07:42 PM PDT 23
Peak memory 205420 kb
Host smart-642653e6-0dbf-4367-a854-ead5cbe695d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113861626438078997763457444113179026863341817881040277828990653978998176006193 -assert nopostp
roc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 38.edn_alert_test.113861626438078997763457444113179026863341817881040277828990653978998176006193
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.52112037072224293434341443668426859660614366565542452344878393196687857547660
Short name T590
Test name
Test status
Simulation time 12219183 ps
CPU time 0.94 seconds
Started Oct 29 02:07:39 PM PDT 23
Finished Oct 29 02:07:40 PM PDT 23
Peak memory 214880 kb
Host smart-8fdfc69a-7416-4da0-8741-9cd21802e4f4
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52112037072224293434341443668426859660614366565542452344878393196687857547660 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.edn_disable.52112037072224293434341443668426859660614366565542452344878393196687857547660
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.25637566131373815272329910105327262937179819997021996462051996291453522105708
Short name T941
Test name
Test status
Simulation time 17319183 ps
CPU time 0.98 seconds
Started Oct 29 02:08:05 PM PDT 23
Finished Oct 29 02:08:07 PM PDT 23
Peak memory 214940 kb
Host smart-eee0383a-be5e-4b33-9f3d-c57df079d20c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25637566131373815272329910105327262937179819997021996462051996291453522105708 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable_auto_req_mode.2563756613137381527232991010532726293717981999702199646205
1996291453522105708
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.91893742554701567066133074960964931971770552682157224512813514952544924558065
Short name T316
Test name
Test status
Simulation time 24963823 ps
CPU time 1.12 seconds
Started Oct 29 02:07:37 PM PDT 23
Finished Oct 29 02:07:39 PM PDT 23
Peak memory 230492 kb
Host smart-54569024-9eeb-4006-9b1d-08e9a177f35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91893742554701567066133074960964931971770552682157224512813514952544924558065 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.edn_err.91893742554701567066133074960964931971770552682157224512813514952544924558065
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.55614528773827376074513241802938110756749507061721645682037670839281580539212
Short name T963
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Oct 29 02:07:32 PM PDT 23
Finished Oct 29 02:07:34 PM PDT 23
Peak memory 205816 kb
Host smart-17e89f74-02b2-471a-8178-826d8fcb425c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55614528773827376074513241802938110756749507061721645682037670839281580539212 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.edn_genbits.55614528773827376074513241802938110756749507061721645682037670839281580539212
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.75311673113276104605730494050394133456554141061735646684469304311213409751970
Short name T346
Test name
Test status
Simulation time 18439183 ps
CPU time 1.08 seconds
Started Oct 29 02:07:25 PM PDT 23
Finished Oct 29 02:07:27 PM PDT 23
Peak memory 222240 kb
Host smart-b76a1ae5-8362-44eb-bb07-6c1b4df488de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75311673113276104605730494050394133456554141061735646684469304311213409751970 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.edn_intr.75311673113276104605730494050394133456554141061735646684469304311213409751970
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.71524444765119890650812256566084036105968302825121724946379203189419164359535
Short name T827
Test name
Test status
Simulation time 13059183 ps
CPU time 0.83 seconds
Started Oct 29 02:07:36 PM PDT 23
Finished Oct 29 02:07:38 PM PDT 23
Peak memory 205356 kb
Host smart-e12b8587-a436-42a4-a05e-0185f6f0fb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71524444765119890650812256566084036105968302825121724946379203189419164359535 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 38.edn_smoke.71524444765119890650812256566084036105968302825121724946379203189419164359535
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.32505760301019201304623740341541338210162043490769211292848734645170808447135
Short name T352
Test name
Test status
Simulation time 154489183 ps
CPU time 4.06 seconds
Started Oct 29 02:07:35 PM PDT 23
Finished Oct 29 02:07:40 PM PDT 23
Peak memory 206240 kb
Host smart-1c169177-0748-49d4-a7e0-7e82fa9fff6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32505760301019201304623740341541338210162043490769211292848734645170808447135 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.32505760301019201304623740341541338210162043490769211292848734645170808447135
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.94894251867441594846313353917990708004879578708462107578197184997604875949762
Short name T752
Test name
Test status
Simulation time 41708099183 ps
CPU time 1081.45 seconds
Started Oct 29 02:07:43 PM PDT 23
Finished Oct 29 02:25:45 PM PDT 23
Peak memory 215868 kb
Host smart-4c0b89d4-64b2-4b45-8d29-0ec88d741683
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948942518674415948463133539
17990708004879578708462107578197184997604875949762 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.94894251867
441594846313353917990708004879578708462107578197184997604875949762
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.13968933638024013794968891546445517577860601134661406068956808751290494885576
Short name T876
Test name
Test status
Simulation time 18259183 ps
CPU time 1.01 seconds
Started Oct 29 02:08:36 PM PDT 23
Finished Oct 29 02:08:38 PM PDT 23
Peak memory 205524 kb
Host smart-9f754957-3c36-46ac-835c-2e06ad88da6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13968933638024013794968891546445517577860601134661406068956808751290494885576 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 39.edn_alert.13968933638024013794968891546445517577860601134661406068956808751290494885576
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.49887977849684833891109470758138244403546040339575706459503854696543174925858
Short name T55
Test name
Test status
Simulation time 28184990 ps
CPU time 0.87 seconds
Started Oct 29 02:08:04 PM PDT 23
Finished Oct 29 02:08:05 PM PDT 23
Peak memory 205532 kb
Host smart-02d2aabf-c7c8-471b-847a-e2ccad3a1bb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49887977849684833891109470758138244403546040339575706459503854696543174925858 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.edn_alert_test.49887977849684833891109470758138244403546040339575706459503854696543174925858
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.11246317836748008136240606176233856938418326659688023735447209613347991828344
Short name T543
Test name
Test status
Simulation time 12219183 ps
CPU time 0.87 seconds
Started Oct 29 02:08:04 PM PDT 23
Finished Oct 29 02:08:05 PM PDT 23
Peak memory 214876 kb
Host smart-cfe65641-b0ff-455d-bcf9-d6c87e3d8f49
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11246317836748008136240606176233856938418326659688023735447209613347991828344 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.edn_disable.11246317836748008136240606176233856938418326659688023735447209613347991828344
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.52607058579504613942775472433242204726617208094451425188617619460418917471887
Short name T421
Test name
Test status
Simulation time 17319183 ps
CPU time 0.92 seconds
Started Oct 29 02:08:01 PM PDT 23
Finished Oct 29 02:08:02 PM PDT 23
Peak memory 214892 kb
Host smart-1f58fa84-c18d-49b2-a31b-b4ed2f578f38
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52607058579504613942775472433242204726617208094451425188617619460418917471887 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable_auto_req_mode.5260705857950461394277547243324220472661720809445142518861
7619460418917471887
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.5344542108335033832017512427586030810229131254138379800952724194226131468524
Short name T447
Test name
Test status
Simulation time 24963823 ps
CPU time 1.11 seconds
Started Oct 29 02:08:01 PM PDT 23
Finished Oct 29 02:08:02 PM PDT 23
Peak memory 230336 kb
Host smart-71c75443-2e4f-4b21-b6c9-5a3d549fb37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5344542108335033832017512427586030810229131254138379800952724194226131468524 -assert nopostproc +UVM_TESTNAME=edn_err_te
st +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
edn_err.5344542108335033832017512427586030810229131254138379800952724194226131468524
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.67598478494338116326883797065869942032948940651593210659441023829099437817119
Short name T813
Test name
Test status
Simulation time 17999183 ps
CPU time 1.06 seconds
Started Oct 29 02:07:40 PM PDT 23
Finished Oct 29 02:07:41 PM PDT 23
Peak memory 205832 kb
Host smart-499b9a05-367c-4088-9b48-9a99b55ddee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67598478494338116326883797065869942032948940651593210659441023829099437817119 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.edn_genbits.67598478494338116326883797065869942032948940651593210659441023829099437817119
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.41352440929351797089310220384185199045161327837248441573748145801322023503587
Short name T440
Test name
Test status
Simulation time 18439183 ps
CPU time 1.13 seconds
Started Oct 29 02:07:41 PM PDT 23
Finished Oct 29 02:07:42 PM PDT 23
Peak memory 222300 kb
Host smart-aa0baa91-4432-4353-b448-38741b1fdb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41352440929351797089310220384185199045161327837248441573748145801322023503587 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.edn_intr.41352440929351797089310220384185199045161327837248441573748145801322023503587
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.4972422126089650752471964078648162255568370585409251458536221526198045387219
Short name T244
Test name
Test status
Simulation time 13059183 ps
CPU time 0.88 seconds
Started Oct 29 02:07:42 PM PDT 23
Finished Oct 29 02:07:43 PM PDT 23
Peak memory 205412 kb
Host smart-25379dad-b786-46db-90bc-f2538e7c8552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4972422126089650752471964078648162255568370585409251458536221526198045387219 -assert nopostproc +UVM_TESTNAME=edn_smoke_
test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.edn_smoke.4972422126089650752471964078648162255568370585409251458536221526198045387219
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.26821465658272268700017585249927224881380201695980952550980597530139625437084
Short name T652
Test name
Test status
Simulation time 154489183 ps
CPU time 3.95 seconds
Started Oct 29 02:08:41 PM PDT 23
Finished Oct 29 02:08:46 PM PDT 23
Peak memory 206296 kb
Host smart-bce1aabc-ca53-4319-9cb0-d7ded5fd857c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26821465658272268700017585249927224881380201695980952550980597530139625437084 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.26821465658272268700017585249927224881380201695980952550980597530139625437084
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.41430232119211998795307605008037315000267735544134249811983865165394650184262
Short name T804
Test name
Test status
Simulation time 41708099183 ps
CPU time 1076.76 seconds
Started Oct 29 02:08:42 PM PDT 23
Finished Oct 29 02:26:40 PM PDT 23
Peak memory 215860 kb
Host smart-8569a2b6-7235-4866-9d24-d28f531e2fa5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414302321192119987953076050
08037315000267735544134249811983865165394650184262 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.41430232119
211998795307605008037315000267735544134249811983865165394650184262
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.62317623152876802586515965953923088082070198849787152819978143253749887036031
Short name T651
Test name
Test status
Simulation time 18259183 ps
CPU time 0.98 seconds
Started Oct 29 02:06:33 PM PDT 23
Finished Oct 29 02:06:34 PM PDT 23
Peak memory 205440 kb
Host smart-48ddc07c-d6ac-4843-9eb0-f11a551f212e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62317623152876802586515965953923088082070198849787152819978143253749887036031 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.edn_alert.62317623152876802586515965953923088082070198849787152819978143253749887036031
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.13987303578733025094338957553890343438495757895989971326613255806183428311364
Short name T260
Test name
Test status
Simulation time 28184990 ps
CPU time 0.91 seconds
Started Oct 29 02:06:33 PM PDT 23
Finished Oct 29 02:06:34 PM PDT 23
Peak memory 205492 kb
Host smart-00fd58eb-be19-41cd-a1b6-710865358545
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13987303578733025094338957553890343438495757895989971326613255806183428311364 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.edn_alert_test.13987303578733025094338957553890343438495757895989971326613255806183428311364
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.8014955656131445832768927550298471714049522083071516081594607747604867225391
Short name T767
Test name
Test status
Simulation time 12219183 ps
CPU time 0.91 seconds
Started Oct 29 02:06:34 PM PDT 23
Finished Oct 29 02:06:35 PM PDT 23
Peak memory 214932 kb
Host smart-1eee42e8-3afa-4bc8-8e4f-0199b479e770
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8014955656131445832768927550298471714049522083071516081594607747604867225391 -assert nopostproc
+UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.edn_disable.8014955656131445832768927550298471714049522083071516081594607747604867225391
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.102863097048330829866438854461028376384496239664712535591536953922113988147722
Short name T399
Test name
Test status
Simulation time 17319183 ps
CPU time 0.94 seconds
Started Oct 29 02:06:22 PM PDT 23
Finished Oct 29 02:06:23 PM PDT 23
Peak memory 214880 kb
Host smart-502266d4-5027-4541-a2f0-ecea0c4591aa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102863097048330829866438854461028376384496239664712535591536953922113988147722 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable_auto_req_mode.1028630970483308298664388544610283763844962396647125355915
36953922113988147722
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.28883840505800607542374526201113873013291863769633580982885157839153698252975
Short name T526
Test name
Test status
Simulation time 24963823 ps
CPU time 1.13 seconds
Started Oct 29 02:06:34 PM PDT 23
Finished Oct 29 02:06:35 PM PDT 23
Peak memory 230492 kb
Host smart-9f76b35f-3e62-47c1-be0d-ed4dd0016775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28883840505800607542374526201113873013291863769633580982885157839153698252975 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
edn_err.28883840505800607542374526201113873013291863769633580982885157839153698252975
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.5495089230164192055842554230122900861624493600306245414874176153510134389884
Short name T843
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Oct 29 02:07:00 PM PDT 23
Finished Oct 29 02:07:05 PM PDT 23
Peak memory 205868 kb
Host smart-3394585f-9d48-40df-9002-2f6b797e7084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5495089230164192055842554230122900861624493600306245414874176153510134389884 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.edn_genbits.5495089230164192055842554230122900861624493600306245414874176153510134389884
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.65342563326820491280173775524968498361419075227097375102274750786655563625983
Short name T476
Test name
Test status
Simulation time 18439183 ps
CPU time 1.11 seconds
Started Oct 29 02:07:00 PM PDT 23
Finished Oct 29 02:07:05 PM PDT 23
Peak memory 222248 kb
Host smart-64da3048-a012-401d-a301-e228e667ec15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65342563326820491280173775524968498361419075227097375102274750786655563625983 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.edn_intr.65342563326820491280173775524968498361419075227097375102274750786655563625983
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.38322869037164645826242850653620145589485215075162732063375042393657862272688
Short name T675
Test name
Test status
Simulation time 11759183 ps
CPU time 0.86 seconds
Started Oct 29 02:06:58 PM PDT 23
Finished Oct 29 02:07:00 PM PDT 23
Peak memory 205240 kb
Host smart-8e1c1a54-4760-4475-8800-68762e27ed23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38322869037164645826242850653620145589485215075162732063375042393657862272688 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.edn_regwen.38322869037164645826242850653620145589485215075162732063375042393657862272688
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.82460088760692960843937776555342879822596435954251299085184330621394580929777
Short name T31
Test name
Test status
Simulation time 717215632 ps
CPU time 5.86 seconds
Started Oct 29 02:06:55 PM PDT 23
Finished Oct 29 02:07:01 PM PDT 23
Peak memory 234096 kb
Host smart-120b8711-ce57-4395-a874-fbbcd87bb972
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82460088760692960843937776555342879822596435954251299085184330621394580929777 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.edn_sec_cm.82460088760692960843937776555342879822596435954251299085184330621394580929777
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.41192839190044316152040429012330192566556708693167031664781180604603654411718
Short name T239
Test name
Test status
Simulation time 13059183 ps
CPU time 0.88 seconds
Started Oct 29 02:06:33 PM PDT 23
Finished Oct 29 02:06:34 PM PDT 23
Peak memory 205272 kb
Host smart-5cd19f3a-d5fd-4493-a646-003ed5e79205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41192839190044316152040429012330192566556708693167031664781180604603654411718 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.edn_smoke.41192839190044316152040429012330192566556708693167031664781180604603654411718
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.64438565622267602769154280871423389635685654150773084254745973018085390157232
Short name T629
Test name
Test status
Simulation time 154489183 ps
CPU time 4.07 seconds
Started Oct 29 02:06:57 PM PDT 23
Finished Oct 29 02:07:02 PM PDT 23
Peak memory 206316 kb
Host smart-f9897760-babc-4d97-8996-35fb1a6b9a33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64438565622267602769154280871423389635685654150773084254745973018085390157232 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.64438565622267602769154280871423389635685654150773084254745973018085390157232
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.82924671180184544640988532636375405001646737461338767367511404738623478295406
Short name T627
Test name
Test status
Simulation time 41708099183 ps
CPU time 1058.39 seconds
Started Oct 29 02:06:54 PM PDT 23
Finished Oct 29 02:24:33 PM PDT 23
Peak memory 215864 kb
Host smart-4509fee6-7e2d-41ff-a3d5-87223e5614f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829246711801845446409885326
36375405001646737461338767367511404738623478295406 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.829246711801
84544640988532636375405001646737461338767367511404738623478295406
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.62065151635301204130081330424805175678414464381322147284023176674394237001628
Short name T586
Test name
Test status
Simulation time 18259183 ps
CPU time 0.98 seconds
Started Oct 29 02:07:42 PM PDT 23
Finished Oct 29 02:07:43 PM PDT 23
Peak memory 205624 kb
Host smart-0f19c646-dd20-4b9d-961f-a215653c237c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62065151635301204130081330424805175678414464381322147284023176674394237001628 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 40.edn_alert.62065151635301204130081330424805175678414464381322147284023176674394237001628
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.59213570602393896080315218835741812619026171803473033984866773360169966998485
Short name T688
Test name
Test status
Simulation time 28184990 ps
CPU time 0.86 seconds
Started Oct 29 02:07:43 PM PDT 23
Finished Oct 29 02:07:45 PM PDT 23
Peak memory 205492 kb
Host smart-d39b4fe7-aa23-434e-a0cd-4feeabec61d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59213570602393896080315218835741812619026171803473033984866773360169966998485 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.edn_alert_test.59213570602393896080315218835741812619026171803473033984866773360169966998485
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.76742883499743807232048704934248100245982296653341435211118826823823838043316
Short name T743
Test name
Test status
Simulation time 12219183 ps
CPU time 0.85 seconds
Started Oct 29 02:08:40 PM PDT 23
Finished Oct 29 02:08:43 PM PDT 23
Peak memory 214888 kb
Host smart-fae8e810-3b82-4b1e-abb4-e05a84af8890
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76742883499743807232048704934248100245982296653341435211118826823823838043316 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.edn_disable.76742883499743807232048704934248100245982296653341435211118826823823838043316
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.10268543776097380822502866829210557447638584711752147202963865926049027057618
Short name T460
Test name
Test status
Simulation time 17319183 ps
CPU time 0.9 seconds
Started Oct 29 02:08:04 PM PDT 23
Finished Oct 29 02:08:05 PM PDT 23
Peak memory 214908 kb
Host smart-fbb57919-be46-4813-931c-7c4267529a47
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10268543776097380822502866829210557447638584711752147202963865926049027057618 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable_auto_req_mode.1026854377609738082250286682921055744763858471175214720296
3865926049027057618
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.22751762550957643632073239771565752573532487249210135943519435643400959232288
Short name T898
Test name
Test status
Simulation time 24963823 ps
CPU time 1.13 seconds
Started Oct 29 02:08:31 PM PDT 23
Finished Oct 29 02:08:32 PM PDT 23
Peak memory 230388 kb
Host smart-3e1879cb-34bf-4a87-8a9c-8cbf308a4355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22751762550957643632073239771565752573532487249210135943519435643400959232288 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.edn_err.22751762550957643632073239771565752573532487249210135943519435643400959232288
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.39360676446082934584355430923963487427970856588468092703408016813807502096050
Short name T793
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Oct 29 02:07:58 PM PDT 23
Finished Oct 29 02:08:00 PM PDT 23
Peak memory 205712 kb
Host smart-82099a17-c913-47b0-8cd2-92e26f8b8ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39360676446082934584355430923963487427970856588468092703408016813807502096050 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.edn_genbits.39360676446082934584355430923963487427970856588468092703408016813807502096050
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.5899151963707002763272106411820642932128674555049652103787366408288803572691
Short name T833
Test name
Test status
Simulation time 18439183 ps
CPU time 1.14 seconds
Started Oct 29 02:08:13 PM PDT 23
Finished Oct 29 02:08:15 PM PDT 23
Peak memory 222224 kb
Host smart-e30a1c08-7c89-4e03-a1e0-3f8c818fa9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5899151963707002763272106411820642932128674555049652103787366408288803572691 -assert nopostproc +UVM_TESTNAME=edn_intr_t
est +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.edn_intr.5899151963707002763272106411820642932128674555049652103787366408288803572691
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.48153300884408577748589843332944705719270590520627866673944991737912001677700
Short name T25
Test name
Test status
Simulation time 13059183 ps
CPU time 0.88 seconds
Started Oct 29 02:08:30 PM PDT 23
Finished Oct 29 02:08:31 PM PDT 23
Peak memory 205340 kb
Host smart-019d7348-0c00-4c8f-b4f3-002adadad2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48153300884408577748589843332944705719270590520627866673944991737912001677700 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 40.edn_smoke.48153300884408577748589843332944705719270590520627866673944991737912001677700
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.17620486649973597847119280282697864341817794122200878554904819770714765540450
Short name T542
Test name
Test status
Simulation time 154489183 ps
CPU time 3.94 seconds
Started Oct 29 02:07:43 PM PDT 23
Finished Oct 29 02:07:48 PM PDT 23
Peak memory 206380 kb
Host smart-7fa9f863-f7ce-4062-adc1-31aa61ef3c62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17620486649973597847119280282697864341817794122200878554904819770714765540450 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.17620486649973597847119280282697864341817794122200878554904819770714765540450
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.58754364864412130177341168540375993756861357474798851252061407796990266031541
Short name T45
Test name
Test status
Simulation time 41708099183 ps
CPU time 1079.31 seconds
Started Oct 29 02:08:04 PM PDT 23
Finished Oct 29 02:26:03 PM PDT 23
Peak memory 215832 kb
Host smart-4ceba709-baca-4afc-899b-a33d647be15f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587543648644121301773411685
40375993756861357474798851252061407796990266031541 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.58754364864
412130177341168540375993756861357474798851252061407796990266031541
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.40711844549917407195438523867371285179712819054847636974674339615709812547342
Short name T396
Test name
Test status
Simulation time 18259183 ps
CPU time 1.03 seconds
Started Oct 29 02:08:06 PM PDT 23
Finished Oct 29 02:08:07 PM PDT 23
Peak memory 205592 kb
Host smart-17192a10-240d-4567-b637-e75b02bf9622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40711844549917407195438523867371285179712819054847636974674339615709812547342 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 41.edn_alert.40711844549917407195438523867371285179712819054847636974674339615709812547342
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.26404476882634457776879377883124728310708078218406523745169064021020304301344
Short name T945
Test name
Test status
Simulation time 28184990 ps
CPU time 0.86 seconds
Started Oct 29 02:07:43 PM PDT 23
Finished Oct 29 02:07:44 PM PDT 23
Peak memory 205484 kb
Host smart-2ff25240-6e02-4015-a5a8-d20361eb6ef5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26404476882634457776879377883124728310708078218406523745169064021020304301344 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.edn_alert_test.26404476882634457776879377883124728310708078218406523745169064021020304301344
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.22920285001755460887537964764301555402571565744287204328035474399839953851457
Short name T971
Test name
Test status
Simulation time 12219183 ps
CPU time 0.84 seconds
Started Oct 29 02:07:57 PM PDT 23
Finished Oct 29 02:07:58 PM PDT 23
Peak memory 214780 kb
Host smart-763645c1-eda7-4ce1-8909-be4a7acd72c4
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22920285001755460887537964764301555402571565744287204328035474399839953851457 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.edn_disable.22920285001755460887537964764301555402571565744287204328035474399839953851457
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.65122272656624601188721974582241458123758418282368171804213676244604773920895
Short name T444
Test name
Test status
Simulation time 17319183 ps
CPU time 0.93 seconds
Started Oct 29 02:08:02 PM PDT 23
Finished Oct 29 02:08:03 PM PDT 23
Peak memory 214904 kb
Host smart-f01933be-01fd-48ee-bd18-039d41d774a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65122272656624601188721974582241458123758418282368171804213676244604773920895 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable_auto_req_mode.6512227265662460118872197458224145812375841828236817180421
3676244604773920895
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.58509684569992744829459786206314313441968576491607085404286849461871041128254
Short name T644
Test name
Test status
Simulation time 24963823 ps
CPU time 1.16 seconds
Started Oct 29 02:09:01 PM PDT 23
Finished Oct 29 02:09:04 PM PDT 23
Peak memory 230340 kb
Host smart-edcf8772-9f49-46fc-b6d5-4f1ee9d1ce74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58509684569992744829459786206314313441968576491607085404286849461871041128254 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.edn_err.58509684569992744829459786206314313441968576491607085404286849461871041128254
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.16639601208431994657028033075285462078986058429185020868903606556082964570469
Short name T786
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:07:41 PM PDT 23
Finished Oct 29 02:07:43 PM PDT 23
Peak memory 205884 kb
Host smart-7a40f465-581b-4a09-9dd3-0fb6cb5ef031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16639601208431994657028033075285462078986058429185020868903606556082964570469 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.edn_genbits.16639601208431994657028033075285462078986058429185020868903606556082964570469
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.58887446482843773105342144059402926741986495408998728668680007091229520090595
Short name T388
Test name
Test status
Simulation time 18439183 ps
CPU time 1.12 seconds
Started Oct 29 02:08:02 PM PDT 23
Finished Oct 29 02:08:03 PM PDT 23
Peak memory 222272 kb
Host smart-d4b8bec3-4c0a-40d5-8e61-a3bb599e0960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58887446482843773105342144059402926741986495408998728668680007091229520090595 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.edn_intr.58887446482843773105342144059402926741986495408998728668680007091229520090595
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.74082171732395118753082044281479124378194780926560206560085278769933015222243
Short name T445
Test name
Test status
Simulation time 13059183 ps
CPU time 0.87 seconds
Started Oct 29 02:08:05 PM PDT 23
Finished Oct 29 02:08:06 PM PDT 23
Peak memory 205348 kb
Host smart-40626b1e-fad2-452a-b6e4-5efc3b334c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74082171732395118753082044281479124378194780926560206560085278769933015222243 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 41.edn_smoke.74082171732395118753082044281479124378194780926560206560085278769933015222243
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.60398371385154038860996928903472921403138821754832936905504248166270852729308
Short name T894
Test name
Test status
Simulation time 154489183 ps
CPU time 3.96 seconds
Started Oct 29 02:07:57 PM PDT 23
Finished Oct 29 02:08:01 PM PDT 23
Peak memory 206464 kb
Host smart-00386373-cf30-4ea2-a862-423736d8d965
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60398371385154038860996928903472921403138821754832936905504248166270852729308 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.60398371385154038860996928903472921403138821754832936905504248166270852729308
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.26457957044084813742350831972972230983965278599735519106186823418211791999480
Short name T464
Test name
Test status
Simulation time 41708099183 ps
CPU time 1068.01 seconds
Started Oct 29 02:08:33 PM PDT 23
Finished Oct 29 02:26:21 PM PDT 23
Peak memory 215816 kb
Host smart-aa533da4-ca41-4153-b067-1f09c53d95fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264579570440848137423508319
72972230983965278599735519106186823418211791999480 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.26457957044
084813742350831972972230983965278599735519106186823418211791999480
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.10005253299467826269779748548437849710620530008422731431160462463008770297068
Short name T594
Test name
Test status
Simulation time 18259183 ps
CPU time 1.03 seconds
Started Oct 29 02:08:35 PM PDT 23
Finished Oct 29 02:08:36 PM PDT 23
Peak memory 205516 kb
Host smart-0f0804c1-8f98-4978-b300-7c5e4e911348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10005253299467826269779748548437849710620530008422731431160462463008770297068 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 42.edn_alert.10005253299467826269779748548437849710620530008422731431160462463008770297068
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.63310641713251460661220948663386367753886100532629790933549171785534972417130
Short name T47
Test name
Test status
Simulation time 28184990 ps
CPU time 0.85 seconds
Started Oct 29 02:09:24 PM PDT 23
Finished Oct 29 02:09:25 PM PDT 23
Peak memory 205476 kb
Host smart-e09ae77a-bab6-4ecb-b4d7-17bcd3f99092
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63310641713251460661220948663386367753886100532629790933549171785534972417130 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.edn_alert_test.63310641713251460661220948663386367753886100532629790933549171785534972417130
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.93949212728166272429059689715232965840305136401713223839538724439695568648146
Short name T407
Test name
Test status
Simulation time 12219183 ps
CPU time 0.88 seconds
Started Oct 29 02:08:30 PM PDT 23
Finished Oct 29 02:08:32 PM PDT 23
Peak memory 214784 kb
Host smart-c0efba37-6759-40ea-a33f-0ab8868f4a5c
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93949212728166272429059689715232965840305136401713223839538724439695568648146 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.edn_disable.93949212728166272429059689715232965840305136401713223839538724439695568648146
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.27305692921554394980358280009022984893735447687584694771409311148186154928067
Short name T535
Test name
Test status
Simulation time 17319183 ps
CPU time 0.89 seconds
Started Oct 29 02:08:43 PM PDT 23
Finished Oct 29 02:08:45 PM PDT 23
Peak memory 214876 kb
Host smart-e39c17bf-b20e-4463-803c-7aa605c7c004
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27305692921554394980358280009022984893735447687584694771409311148186154928067 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable_auto_req_mode.2730569292155439498035828000902298489373544768758469477140
9311148186154928067
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.17116781745905814471640264472223507185503384564586674509209338220715269089129
Short name T795
Test name
Test status
Simulation time 24963823 ps
CPU time 1.13 seconds
Started Oct 29 02:08:35 PM PDT 23
Finished Oct 29 02:08:36 PM PDT 23
Peak memory 230428 kb
Host smart-604da2f2-8329-49eb-9570-e3443054a0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17116781745905814471640264472223507185503384564586674509209338220715269089129 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.edn_err.17116781745905814471640264472223507185503384564586674509209338220715269089129
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.103515380157020605299598713834428699287844225957562288520709202822762032951780
Short name T645
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Oct 29 02:08:39 PM PDT 23
Finished Oct 29 02:08:43 PM PDT 23
Peak memory 205740 kb
Host smart-1ee9bf99-e257-4b7a-a56f-f78415e1dbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103515380157020605299598713834428699287844225957562288520709202822762032951780 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 42.edn_genbits.103515380157020605299598713834428699287844225957562288520709202822762032951780
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.60127995572575949058563561517422683850239789744347822588873605771072691194151
Short name T249
Test name
Test status
Simulation time 18439183 ps
CPU time 1.11 seconds
Started Oct 29 02:08:41 PM PDT 23
Finished Oct 29 02:08:43 PM PDT 23
Peak memory 222224 kb
Host smart-2eb4d1b3-8b75-4446-9048-95f78ef72b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60127995572575949058563561517422683850239789744347822588873605771072691194151 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.edn_intr.60127995572575949058563561517422683850239789744347822588873605771072691194151
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.49854742905925629241954544335300941237505237897848363645511719313470250919187
Short name T717
Test name
Test status
Simulation time 13059183 ps
CPU time 0.85 seconds
Started Oct 29 02:08:40 PM PDT 23
Finished Oct 29 02:08:43 PM PDT 23
Peak memory 205252 kb
Host smart-df343ed6-9411-440a-aca0-6fd5c039d300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49854742905925629241954544335300941237505237897848363645511719313470250919187 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 42.edn_smoke.49854742905925629241954544335300941237505237897848363645511719313470250919187
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.26481287085118481086330235394292362056131324683856022045989015056148593538346
Short name T735
Test name
Test status
Simulation time 154489183 ps
CPU time 3.89 seconds
Started Oct 29 02:08:38 PM PDT 23
Finished Oct 29 02:08:46 PM PDT 23
Peak memory 206240 kb
Host smart-04ed8734-b515-4640-8adf-d7fc77057a64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26481287085118481086330235394292362056131324683856022045989015056148593538346 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.26481287085118481086330235394292362056131324683856022045989015056148593538346
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.92279285335596793113312257058630630508710423996499505221260660116125619105984
Short name T294
Test name
Test status
Simulation time 41708099183 ps
CPU time 1052.56 seconds
Started Oct 29 02:08:36 PM PDT 23
Finished Oct 29 02:26:10 PM PDT 23
Peak memory 215868 kb
Host smart-2c7ff537-2581-4bea-a85b-c9cab6af9da6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922792853355967931133122570
58630630508710423996499505221260660116125619105984 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.92279285335
596793113312257058630630508710423996499505221260660116125619105984
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.59704538398419677367009223636230479083439094088282915279329937727437946308737
Short name T569
Test name
Test status
Simulation time 18259183 ps
CPU time 1 seconds
Started Oct 29 02:08:06 PM PDT 23
Finished Oct 29 02:08:07 PM PDT 23
Peak memory 205524 kb
Host smart-a605aa66-3d2a-4f30-9868-72ebe998fe46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59704538398419677367009223636230479083439094088282915279329937727437946308737 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 43.edn_alert.59704538398419677367009223636230479083439094088282915279329937727437946308737
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.80647054909198696034131235863268520862383026442904924493326788407963866497865
Short name T344
Test name
Test status
Simulation time 28184990 ps
CPU time 0.86 seconds
Started Oct 29 02:07:46 PM PDT 23
Finished Oct 29 02:07:47 PM PDT 23
Peak memory 205504 kb
Host smart-debf68b0-a664-48f4-bf77-d67796aca464
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80647054909198696034131235863268520862383026442904924493326788407963866497865 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.edn_alert_test.80647054909198696034131235863268520862383026442904924493326788407963866497865
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.101038352439870849763107210023318564543499259679428174046118877585785223572751
Short name T69
Test name
Test status
Simulation time 12219183 ps
CPU time 0.91 seconds
Started Oct 29 02:08:06 PM PDT 23
Finished Oct 29 02:08:07 PM PDT 23
Peak memory 214856 kb
Host smart-1d493cbb-5e71-47b6-87ee-1dd14425e95c
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101038352439870849763107210023318564543499259679428174046118877585785223572751 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 43.edn_disable.101038352439870849763107210023318564543499259679428174046118877585785223572751
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.104643925880168141613463577804018769627473733552421101450640270537804413629488
Short name T803
Test name
Test status
Simulation time 17319183 ps
CPU time 0.98 seconds
Started Oct 29 02:08:06 PM PDT 23
Finished Oct 29 02:08:07 PM PDT 23
Peak memory 214884 kb
Host smart-1a727f86-625a-4fc3-b8bb-15b545d28174
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104643925880168141613463577804018769627473733552421101450640270537804413629488 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable_auto_req_mode.104643925880168141613463577804018769627473733552421101450
640270537804413629488
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.62565568555553287766677073909864281852811470174766717833070292841303790176095
Short name T457
Test name
Test status
Simulation time 24963823 ps
CPU time 1.14 seconds
Started Oct 29 02:07:44 PM PDT 23
Finished Oct 29 02:07:45 PM PDT 23
Peak memory 230412 kb
Host smart-497b20ec-ca06-443b-a2a2-eee6333f2dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62565568555553287766677073909864281852811470174766717833070292841303790176095 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.edn_err.62565568555553287766677073909864281852811470174766717833070292841303790176095
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.2540491150808834712110992346498074819113453595089524823125890197776875723362
Short name T751
Test name
Test status
Simulation time 17999183 ps
CPU time 1.25 seconds
Started Oct 29 02:08:47 PM PDT 23
Finished Oct 29 02:08:48 PM PDT 23
Peak memory 205876 kb
Host smart-2c7dcba4-cdfc-4e80-93e8-f3b846bb6b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540491150808834712110992346498074819113453595089524823125890197776875723362 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.edn_genbits.2540491150808834712110992346498074819113453595089524823125890197776875723362
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.64816401332585525035844454457662640250789727141736153252587045452689071478371
Short name T949
Test name
Test status
Simulation time 18439183 ps
CPU time 1.1 seconds
Started Oct 29 02:08:43 PM PDT 23
Finished Oct 29 02:08:45 PM PDT 23
Peak memory 222256 kb
Host smart-3af93190-7b85-4f06-859f-764ad3efb46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64816401332585525035844454457662640250789727141736153252587045452689071478371 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.edn_intr.64816401332585525035844454457662640250789727141736153252587045452689071478371
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.67558894890331926710215783678636241718523163576900882448866642072816947058213
Short name T504
Test name
Test status
Simulation time 13059183 ps
CPU time 0.9 seconds
Started Oct 29 02:09:37 PM PDT 23
Finished Oct 29 02:09:38 PM PDT 23
Peak memory 205372 kb
Host smart-df97078c-38da-441f-8f5c-3c5d4d2ce81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67558894890331926710215783678636241718523163576900882448866642072816947058213 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 43.edn_smoke.67558894890331926710215783678636241718523163576900882448866642072816947058213
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.75342937977892306244965972597168286854195541299981788488531030000954438324163
Short name T419
Test name
Test status
Simulation time 154489183 ps
CPU time 3.99 seconds
Started Oct 29 02:08:49 PM PDT 23
Finished Oct 29 02:08:53 PM PDT 23
Peak memory 206348 kb
Host smart-50acbf32-e236-491c-8e8d-2b33065d75fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75342937977892306244965972597168286854195541299981788488531030000954438324163 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.75342937977892306244965972597168286854195541299981788488531030000954438324163
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.49511716490831756407851113173708576532417840185273252495327367344202282378453
Short name T258
Test name
Test status
Simulation time 41708099183 ps
CPU time 1077.76 seconds
Started Oct 29 02:08:59 PM PDT 23
Finished Oct 29 02:27:01 PM PDT 23
Peak memory 215820 kb
Host smart-2f12b850-b426-4590-9b89-28e5744d4342
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495117164908317564078511131
73708576532417840185273252495327367344202282378453 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.49511716490
831756407851113173708576532417840185273252495327367344202282378453
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.687888337106657473786038980179984748719119756569354431493105112481477436820
Short name T305
Test name
Test status
Simulation time 18259183 ps
CPU time 1.04 seconds
Started Oct 29 02:08:39 PM PDT 23
Finished Oct 29 02:08:43 PM PDT 23
Peak memory 205000 kb
Host smart-589aee6d-bd1d-4c7e-b7fe-04c230a4bd98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687888337106657473786038980179984748719119756569354431493105112481477436820 -assert nopostproc +UVM_TESTNAME=edn_alert_t
est +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.edn_alert.687888337106657473786038980179984748719119756569354431493105112481477436820
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.78533282369860153805882907439814693816814821329167228879701341490205937587913
Short name T893
Test name
Test status
Simulation time 28184990 ps
CPU time 0.9 seconds
Started Oct 29 02:08:36 PM PDT 23
Finished Oct 29 02:08:37 PM PDT 23
Peak memory 205444 kb
Host smart-0e780be5-44a6-4a0d-b54d-bc30f0a0c4a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78533282369860153805882907439814693816814821329167228879701341490205937587913 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.edn_alert_test.78533282369860153805882907439814693816814821329167228879701341490205937587913
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.78351045687248453288586158210899664558971270416320731549258026977425969723558
Short name T955
Test name
Test status
Simulation time 12219183 ps
CPU time 0.87 seconds
Started Oct 29 02:08:10 PM PDT 23
Finished Oct 29 02:08:12 PM PDT 23
Peak memory 214880 kb
Host smart-2c15a514-a7a8-464d-add8-11ceb5e0d388
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78351045687248453288586158210899664558971270416320731549258026977425969723558 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.edn_disable.78351045687248453288586158210899664558971270416320731549258026977425969723558
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.12216429949955438859572289291163987805991979230885321366283645366558054956313
Short name T283
Test name
Test status
Simulation time 17319183 ps
CPU time 0.91 seconds
Started Oct 29 02:09:01 PM PDT 23
Finished Oct 29 02:09:04 PM PDT 23
Peak memory 214780 kb
Host smart-5890db1e-b57f-4690-8a14-fff717c9b839
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12216429949955438859572289291163987805991979230885321366283645366558054956313 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable_auto_req_mode.1221642994995543885957228929116398780599197923088532136628
3645366558054956313
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.46565539731156823452616574652171439034494863121282217503607057612809027111903
Short name T351
Test name
Test status
Simulation time 24963823 ps
CPU time 1.1 seconds
Started Oct 29 02:07:42 PM PDT 23
Finished Oct 29 02:07:44 PM PDT 23
Peak memory 230436 kb
Host smart-ee072474-32b7-47b9-b129-acd5704867bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46565539731156823452616574652171439034494863121282217503607057612809027111903 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.edn_err.46565539731156823452616574652171439034494863121282217503607057612809027111903
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.55999035044741194715172004419489989388108770082905612370693274674300339461131
Short name T370
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Oct 29 02:08:07 PM PDT 23
Finished Oct 29 02:08:09 PM PDT 23
Peak memory 205824 kb
Host smart-914246bf-56a5-453b-8b06-4454da6e7bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55999035044741194715172004419489989388108770082905612370693274674300339461131 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.edn_genbits.55999035044741194715172004419489989388108770082905612370693274674300339461131
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.1913300073785471061426648688553962465751997934824399180320884556548618883934
Short name T849
Test name
Test status
Simulation time 18439183 ps
CPU time 1.14 seconds
Started Oct 29 02:08:05 PM PDT 23
Finished Oct 29 02:08:06 PM PDT 23
Peak memory 222268 kb
Host smart-e32e4f40-3ad3-402b-aad8-c20e90a834a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913300073785471061426648688553962465751997934824399180320884556548618883934 -assert nopostproc +UVM_TESTNAME=edn_intr_t
est +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.edn_intr.1913300073785471061426648688553962465751997934824399180320884556548618883934
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.34918453207577076473226105623942649388075823000852598730465792487954249499855
Short name T361
Test name
Test status
Simulation time 13059183 ps
CPU time 0.94 seconds
Started Oct 29 02:08:42 PM PDT 23
Finished Oct 29 02:08:45 PM PDT 23
Peak memory 205412 kb
Host smart-e63283e0-4111-435a-932d-2427c56f12b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34918453207577076473226105623942649388075823000852598730465792487954249499855 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 44.edn_smoke.34918453207577076473226105623942649388075823000852598730465792487954249499855
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.38153236561935875963037969785652070780452479237427447157979156362472690506541
Short name T832
Test name
Test status
Simulation time 154489183 ps
CPU time 4.04 seconds
Started Oct 29 02:08:01 PM PDT 23
Finished Oct 29 02:08:05 PM PDT 23
Peak memory 206356 kb
Host smart-5f771c5d-89ca-4a71-b84a-611a2cf1e5e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38153236561935875963037969785652070780452479237427447157979156362472690506541 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.38153236561935875963037969785652070780452479237427447157979156362472690506541
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.59923888805876681036771569493536522225965101813033395038751642437826111598062
Short name T794
Test name
Test status
Simulation time 41708099183 ps
CPU time 1030.07 seconds
Started Oct 29 02:08:04 PM PDT 23
Finished Oct 29 02:25:15 PM PDT 23
Peak memory 215744 kb
Host smart-636f1db5-123e-4215-bd54-b655d093643b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599238888058766810367715694
93536522225965101813033395038751642437826111598062 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.59923888805
876681036771569493536522225965101813033395038751642437826111598062
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.38485029426946760344884412074109812953868318738070389272431528311368358832588
Short name T524
Test name
Test status
Simulation time 18259183 ps
CPU time 0.99 seconds
Started Oct 29 02:08:35 PM PDT 23
Finished Oct 29 02:08:36 PM PDT 23
Peak memory 205620 kb
Host smart-34ee228d-cbc6-42af-a159-dd39f1352568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38485029426946760344884412074109812953868318738070389272431528311368358832588 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 45.edn_alert.38485029426946760344884412074109812953868318738070389272431528311368358832588
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.36450589097443260038253589283660783710542684667439591592182741587540592137329
Short name T363
Test name
Test status
Simulation time 28184990 ps
CPU time 0.88 seconds
Started Oct 29 02:08:32 PM PDT 23
Finished Oct 29 02:08:33 PM PDT 23
Peak memory 205504 kb
Host smart-961a52c9-8fad-4ead-bf0d-2321336d85bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36450589097443260038253589283660783710542684667439591592182741587540592137329 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.edn_alert_test.36450589097443260038253589283660783710542684667439591592182741587540592137329
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.107145403805328618088486901977945362257903474898963410936113982330245778501105
Short name T28
Test name
Test status
Simulation time 12219183 ps
CPU time 0.88 seconds
Started Oct 29 02:09:03 PM PDT 23
Finished Oct 29 02:09:04 PM PDT 23
Peak memory 214924 kb
Host smart-a0bcb76e-ff57-4397-976d-52c5384483af
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107145403805328618088486901977945362257903474898963410936113982330245778501105 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 45.edn_disable.107145403805328618088486901977945362257903474898963410936113982330245778501105
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.2936601910773323011267215152160925817673131287798606539060286532086514265385
Short name T892
Test name
Test status
Simulation time 17319183 ps
CPU time 0.92 seconds
Started Oct 29 02:08:05 PM PDT 23
Finished Oct 29 02:08:06 PM PDT 23
Peak memory 214896 kb
Host smart-0fe8ea49-888d-4c50-ba42-a5605e587053
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936601910773323011267215152160925817673131287798606539060286532086514265385 -assert nopostproc
+UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable_auto_req_mode.29366019107733230112672151521609258176731312877986065390602
86532086514265385
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.35990774262853952540771998755118723464065327266710775471675042671805781762961
Short name T254
Test name
Test status
Simulation time 24963823 ps
CPU time 1.18 seconds
Started Oct 29 02:08:03 PM PDT 23
Finished Oct 29 02:08:05 PM PDT 23
Peak memory 230412 kb
Host smart-e8964900-f132-471c-97db-4aa6a03152dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35990774262853952540771998755118723464065327266710775471675042671805781762961 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.edn_err.35990774262853952540771998755118723464065327266710775471675042671805781762961
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.37365255998691103849299550166462811327484853698588124423674388896284135333717
Short name T443
Test name
Test status
Simulation time 17999183 ps
CPU time 1.05 seconds
Started Oct 29 02:07:47 PM PDT 23
Finished Oct 29 02:07:48 PM PDT 23
Peak memory 205816 kb
Host smart-d8d41c0a-6013-47a4-ad81-60f660d6cf7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37365255998691103849299550166462811327484853698588124423674388896284135333717 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.edn_genbits.37365255998691103849299550166462811327484853698588124423674388896284135333717
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.69712836875270187443466406791738758116167601810234019486391406835849187930712
Short name T414
Test name
Test status
Simulation time 18439183 ps
CPU time 1.16 seconds
Started Oct 29 02:08:04 PM PDT 23
Finished Oct 29 02:08:06 PM PDT 23
Peak memory 222348 kb
Host smart-d9d3a4e3-1344-4174-8590-ffeb533be31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69712836875270187443466406791738758116167601810234019486391406835849187930712 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.edn_intr.69712836875270187443466406791738758116167601810234019486391406835849187930712
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.30692876330984480605469419728733510560223393531345260036653270437028005081442
Short name T897
Test name
Test status
Simulation time 13059183 ps
CPU time 0.9 seconds
Started Oct 29 02:08:05 PM PDT 23
Finished Oct 29 02:08:06 PM PDT 23
Peak memory 205372 kb
Host smart-18e91692-f7db-465e-8407-24c08660cb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30692876330984480605469419728733510560223393531345260036653270437028005081442 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 45.edn_smoke.30692876330984480605469419728733510560223393531345260036653270437028005081442
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.60560201327291368217509757815478259332428588570825249388211063377464370621322
Short name T454
Test name
Test status
Simulation time 154489183 ps
CPU time 4.07 seconds
Started Oct 29 02:08:35 PM PDT 23
Finished Oct 29 02:08:39 PM PDT 23
Peak memory 206308 kb
Host smart-e4ae7781-a751-43db-968e-f183c0463e2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60560201327291368217509757815478259332428588570825249388211063377464370621322 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.60560201327291368217509757815478259332428588570825249388211063377464370621322
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.95387909259556755990412498099031137466758569608642226911925801009003948178481
Short name T861
Test name
Test status
Simulation time 41708099183 ps
CPU time 1066.03 seconds
Started Oct 29 02:08:03 PM PDT 23
Finished Oct 29 02:25:50 PM PDT 23
Peak memory 215876 kb
Host smart-8f501f75-4050-4260-a696-dc7a01f4603b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953879092595567559904124980
99031137466758569608642226911925801009003948178481 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.95387909259
556755990412498099031137466758569608642226911925801009003948178481
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.101561956047359690149591084572630354020385275588827798202512065649652833557095
Short name T784
Test name
Test status
Simulation time 18259183 ps
CPU time 0.98 seconds
Started Oct 29 02:08:10 PM PDT 23
Finished Oct 29 02:08:11 PM PDT 23
Peak memory 205576 kb
Host smart-8cb6f8a9-dd0e-4335-8779-a07c19f5e436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101561956047359690149591084572630354020385275588827798202512065649652833557095 -assert nopostproc +UVM_TESTNAME=edn_aler
t_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 46.edn_alert.101561956047359690149591084572630354020385275588827798202512065649652833557095
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.29858670531941645619173271010972294248687239877194896386129972434419312204789
Short name T683
Test name
Test status
Simulation time 28184990 ps
CPU time 0.86 seconds
Started Oct 29 02:08:37 PM PDT 23
Finished Oct 29 02:08:38 PM PDT 23
Peak memory 205536 kb
Host smart-6b95536d-36f2-4b35-9de7-332441a87b2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29858670531941645619173271010972294248687239877194896386129972434419312204789 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.edn_alert_test.29858670531941645619173271010972294248687239877194896386129972434419312204789
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.1813303315163001482982237112598886465385310929891469650662503856724377237915
Short name T886
Test name
Test status
Simulation time 12219183 ps
CPU time 0.86 seconds
Started Oct 29 02:08:02 PM PDT 23
Finished Oct 29 02:08:04 PM PDT 23
Peak memory 214864 kb
Host smart-4518fb8e-3b7b-4015-b53d-0f012ec7d1e9
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813303315163001482982237112598886465385310929891469650662503856724377237915 -assert nopostproc
+UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.edn_disable.1813303315163001482982237112598886465385310929891469650662503856724377237915
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.105672586969145209685278636573988788768775677268322890131594092852613598979861
Short name T418
Test name
Test status
Simulation time 17319183 ps
CPU time 0.97 seconds
Started Oct 29 02:08:06 PM PDT 23
Finished Oct 29 02:08:07 PM PDT 23
Peak memory 214896 kb
Host smart-cc4e75a5-1d07-4b09-ad4c-49a5ad840b8d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105672586969145209685278636573988788768775677268322890131594092852613598979861 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable_auto_req_mode.105672586969145209685278636573988788768775677268322890131
594092852613598979861
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.30481506916488821870674449063761369140097279763823523104561535419337204847028
Short name T19
Test name
Test status
Simulation time 24963823 ps
CPU time 1.2 seconds
Started Oct 29 02:08:10 PM PDT 23
Finished Oct 29 02:08:11 PM PDT 23
Peak memory 230460 kb
Host smart-56a54fde-c22a-41cb-a3cb-1f42b35b9f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30481506916488821870674449063761369140097279763823523104561535419337204847028 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.edn_err.30481506916488821870674449063761369140097279763823523104561535419337204847028
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.105428443287386577768270158773741183757426594943152843701181125703962376972736
Short name T553
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Oct 29 02:08:06 PM PDT 23
Finished Oct 29 02:08:07 PM PDT 23
Peak memory 205864 kb
Host smart-5da5ebc4-5f33-4328-946d-397f89643c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105428443287386577768270158773741183757426594943152843701181125703962376972736 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 46.edn_genbits.105428443287386577768270158773741183757426594943152843701181125703962376972736
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.64653587557923518176153134478916154505224927406144961115631696475298306298567
Short name T38
Test name
Test status
Simulation time 18439183 ps
CPU time 1.09 seconds
Started Oct 29 02:07:46 PM PDT 23
Finished Oct 29 02:07:48 PM PDT 23
Peak memory 222264 kb
Host smart-0ef4ec19-a89e-47bb-98d8-cac3a0916dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64653587557923518176153134478916154505224927406144961115631696475298306298567 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.edn_intr.64653587557923518176153134478916154505224927406144961115631696475298306298567
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.9001662948459538376860972290795706240672834862862430551152416508329820144448
Short name T384
Test name
Test status
Simulation time 13059183 ps
CPU time 0.91 seconds
Started Oct 29 02:08:46 PM PDT 23
Finished Oct 29 02:08:47 PM PDT 23
Peak memory 205324 kb
Host smart-a0a8ee84-9640-407a-8146-ed9e6479fa19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9001662948459538376860972290795706240672834862862430551152416508329820144448 -assert nopostproc +UVM_TESTNAME=edn_smoke_
test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.edn_smoke.9001662948459538376860972290795706240672834862862430551152416508329820144448
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.18269050684669054043637060397670546550183495107242328936858617539711750180032
Short name T722
Test name
Test status
Simulation time 154489183 ps
CPU time 3.97 seconds
Started Oct 29 02:08:41 PM PDT 23
Finished Oct 29 02:08:46 PM PDT 23
Peak memory 206356 kb
Host smart-35a0b9ae-44ef-4218-b360-b848e7acfeba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18269050684669054043637060397670546550183495107242328936858617539711750180032 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.18269050684669054043637060397670546550183495107242328936858617539711750180032
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.18365221564507264737667078246652552281796466289965124994134121416448546319707
Short name T701
Test name
Test status
Simulation time 41708099183 ps
CPU time 1066.28 seconds
Started Oct 29 02:08:00 PM PDT 23
Finished Oct 29 02:25:46 PM PDT 23
Peak memory 215760 kb
Host smart-9cd3b268-41d4-4e06-aad9-af772ed4129c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183652215645072647376670782
46652552281796466289965124994134121416448546319707 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.18365221564
507264737667078246652552281796466289965124994134121416448546319707
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.52890644017254836355362448232734561468668289509256658351839336162433395033968
Short name T694
Test name
Test status
Simulation time 18259183 ps
CPU time 0.99 seconds
Started Oct 29 02:07:50 PM PDT 23
Finished Oct 29 02:07:51 PM PDT 23
Peak memory 205552 kb
Host smart-2b55c5ac-e41d-4b24-bb8c-50e602ea131d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52890644017254836355362448232734561468668289509256658351839336162433395033968 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 47.edn_alert.52890644017254836355362448232734561468668289509256658351839336162433395033968
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.113921271092456270072339870672703866605598063901939840593878794389317000097647
Short name T614
Test name
Test status
Simulation time 28184990 ps
CPU time 0.89 seconds
Started Oct 29 02:08:32 PM PDT 23
Finished Oct 29 02:08:33 PM PDT 23
Peak memory 205420 kb
Host smart-9a75799c-8cc2-4b1a-9ee1-05c5802d5ff7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113921271092456270072339870672703866605598063901939840593878794389317000097647 -assert nopostp
roc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 47.edn_alert_test.113921271092456270072339870672703866605598063901939840593878794389317000097647
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.70054801506559736139726536227181748650710570430496568709827844023855405553499
Short name T70
Test name
Test status
Simulation time 12219183 ps
CPU time 0.85 seconds
Started Oct 29 02:07:47 PM PDT 23
Finished Oct 29 02:07:48 PM PDT 23
Peak memory 214852 kb
Host smart-750a9963-c6e1-4dc1-9e42-898443348038
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70054801506559736139726536227181748650710570430496568709827844023855405553499 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.edn_disable.70054801506559736139726536227181748650710570430496568709827844023855405553499
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.114402641071507393791870256373419520303098934210141623965544565661893064718010
Short name T896
Test name
Test status
Simulation time 17319183 ps
CPU time 0.92 seconds
Started Oct 29 02:08:08 PM PDT 23
Finished Oct 29 02:08:09 PM PDT 23
Peak memory 214880 kb
Host smart-67a433f8-36f4-484b-8d1b-d916e217f2a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114402641071507393791870256373419520303098934210141623965544565661893064718010 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable_auto_req_mode.114402641071507393791870256373419520303098934210141623965
544565661893064718010
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.109374035910188645526757980971429480032282517812486600061701540092691855448915
Short name T35
Test name
Test status
Simulation time 24963823 ps
CPU time 1.15 seconds
Started Oct 29 02:08:12 PM PDT 23
Finished Oct 29 02:08:13 PM PDT 23
Peak memory 230428 kb
Host smart-4d1c6517-ad79-4838-8a25-c842b7930e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109374035910188645526757980971429480032282517812486600061701540092691855448915 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.edn_err.109374035910188645526757980971429480032282517812486600061701540092691855448915
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.74425378384960034584021104131767546140905192722008281159681139113422105324232
Short name T264
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Oct 29 02:08:03 PM PDT 23
Finished Oct 29 02:08:04 PM PDT 23
Peak memory 205824 kb
Host smart-0d356f19-c408-4bed-b285-7f2f5a7910ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74425378384960034584021104131767546140905192722008281159681139113422105324232 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.edn_genbits.74425378384960034584021104131767546140905192722008281159681139113422105324232
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.21036572744553651642143816298774869710534825968348197770388144569815312081360
Short name T618
Test name
Test status
Simulation time 18439183 ps
CPU time 1.1 seconds
Started Oct 29 02:08:35 PM PDT 23
Finished Oct 29 02:08:36 PM PDT 23
Peak memory 222240 kb
Host smart-76f91c2a-9a41-47e5-9f67-5ddd04eb78d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21036572744553651642143816298774869710534825968348197770388144569815312081360 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.edn_intr.21036572744553651642143816298774869710534825968348197770388144569815312081360
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.42793725970414033290012602138399356331630123686482810990904853628253707222797
Short name T871
Test name
Test status
Simulation time 13059183 ps
CPU time 0.87 seconds
Started Oct 29 02:08:12 PM PDT 23
Finished Oct 29 02:08:13 PM PDT 23
Peak memory 205340 kb
Host smart-213c5306-196d-4a43-8d6d-1a2aa72817bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42793725970414033290012602138399356331630123686482810990904853628253707222797 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 47.edn_smoke.42793725970414033290012602138399356331630123686482810990904853628253707222797
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.49237501854514672624504638106904347942362980875234847278267122519303124989471
Short name T435
Test name
Test status
Simulation time 154489183 ps
CPU time 3.78 seconds
Started Oct 29 02:08:35 PM PDT 23
Finished Oct 29 02:08:39 PM PDT 23
Peak memory 206276 kb
Host smart-66af6722-a1d6-4e81-af3f-ad54f93280e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49237501854514672624504638106904347942362980875234847278267122519303124989471 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.49237501854514672624504638106904347942362980875234847278267122519303124989471
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.24873335179907700603319770438699775550523508346084822310750162936057483015790
Short name T713
Test name
Test status
Simulation time 41708099183 ps
CPU time 1064.48 seconds
Started Oct 29 02:08:02 PM PDT 23
Finished Oct 29 02:25:47 PM PDT 23
Peak memory 215828 kb
Host smart-553a29dd-afcc-45f4-bb5c-cbb71fa12caa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248733351799077006033197704
38699775550523508346084822310750162936057483015790 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.24873335179
907700603319770438699775550523508346084822310750162936057483015790
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.53283368741927140039502452552841391261005394603183916353425950381479345719148
Short name T621
Test name
Test status
Simulation time 18259183 ps
CPU time 1.07 seconds
Started Oct 29 02:08:06 PM PDT 23
Finished Oct 29 02:08:07 PM PDT 23
Peak memory 205572 kb
Host smart-a3cf6f34-9e40-41b9-84b4-e91d02a0d643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53283368741927140039502452552841391261005394603183916353425950381479345719148 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 48.edn_alert.53283368741927140039502452552841391261005394603183916353425950381479345719148
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.49948979042266493488930074014988623416075318747887152446202475952746191374685
Short name T292
Test name
Test status
Simulation time 28184990 ps
CPU time 0.89 seconds
Started Oct 29 02:08:12 PM PDT 23
Finished Oct 29 02:08:13 PM PDT 23
Peak memory 205488 kb
Host smart-7f46ae1d-4738-4306-b535-4fa40159332e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49948979042266493488930074014988623416075318747887152446202475952746191374685 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.edn_alert_test.49948979042266493488930074014988623416075318747887152446202475952746191374685
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.16783099098896327720644242853953014987033100511980287929250685760689371004870
Short name T68
Test name
Test status
Simulation time 12219183 ps
CPU time 0.91 seconds
Started Oct 29 02:07:51 PM PDT 23
Finished Oct 29 02:07:52 PM PDT 23
Peak memory 214852 kb
Host smart-0d0a3b37-ad1a-4291-833f-2784342e0a16
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16783099098896327720644242853953014987033100511980287929250685760689371004870 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.edn_disable.16783099098896327720644242853953014987033100511980287929250685760689371004870
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.47204040296939415439295155503937812307906982907473669808600388333748006121225
Short name T891
Test name
Test status
Simulation time 17319183 ps
CPU time 0.91 seconds
Started Oct 29 02:08:36 PM PDT 23
Finished Oct 29 02:08:37 PM PDT 23
Peak memory 214944 kb
Host smart-49902b6e-4023-4aa3-bbb8-934f520d2e7a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47204040296939415439295155503937812307906982907473669808600388333748006121225 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable_auto_req_mode.4720404029693941543929515550393781230790698290747366980860
0388333748006121225
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.99667982534306472037966994384164154979612234999280635478495301877912400823615
Short name T888
Test name
Test status
Simulation time 24963823 ps
CPU time 1.15 seconds
Started Oct 29 02:08:06 PM PDT 23
Finished Oct 29 02:08:07 PM PDT 23
Peak memory 230420 kb
Host smart-05358844-c51b-421e-9655-eb4c303984a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99667982534306472037966994384164154979612234999280635478495301877912400823615 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.edn_err.99667982534306472037966994384164154979612234999280635478495301877912400823615
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.48789612420787645681325792670092694131385495174855705879082591698053918727479
Short name T326
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Oct 29 02:08:43 PM PDT 23
Finished Oct 29 02:08:45 PM PDT 23
Peak memory 205844 kb
Host smart-d21400d1-c081-434a-959e-7e70236942f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48789612420787645681325792670092694131385495174855705879082591698053918727479 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.edn_genbits.48789612420787645681325792670092694131385495174855705879082591698053918727479
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.75352484590960236330771014893656585391195532945993446156226270031812625479653
Short name T814
Test name
Test status
Simulation time 18439183 ps
CPU time 1.21 seconds
Started Oct 29 02:09:23 PM PDT 23
Finished Oct 29 02:09:24 PM PDT 23
Peak memory 222188 kb
Host smart-e4fc3f70-d936-40ed-9dc8-107f019a29e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75352484590960236330771014893656585391195532945993446156226270031812625479653 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.edn_intr.75352484590960236330771014893656585391195532945993446156226270031812625479653
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.35300084563825351636460079662866050642616173444003647750460763195904976591931
Short name T959
Test name
Test status
Simulation time 13059183 ps
CPU time 0.88 seconds
Started Oct 29 02:08:01 PM PDT 23
Finished Oct 29 02:08:02 PM PDT 23
Peak memory 205344 kb
Host smart-297b7879-bcbc-44f3-909a-53be3162a54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35300084563825351636460079662866050642616173444003647750460763195904976591931 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 48.edn_smoke.35300084563825351636460079662866050642616173444003647750460763195904976591931
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.50825479651958895619918268225719133890338487187828141189615999111088413927885
Short name T314
Test name
Test status
Simulation time 154489183 ps
CPU time 4.05 seconds
Started Oct 29 02:07:50 PM PDT 23
Finished Oct 29 02:07:54 PM PDT 23
Peak memory 206344 kb
Host smart-e97689d4-b6fa-42fd-bd58-09d1260ba6ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50825479651958895619918268225719133890338487187828141189615999111088413927885 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.50825479651958895619918268225719133890338487187828141189615999111088413927885
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.54333853248050145691844927433728815026816614188670015029023105575170187256860
Short name T556
Test name
Test status
Simulation time 41708099183 ps
CPU time 1062.49 seconds
Started Oct 29 02:08:09 PM PDT 23
Finished Oct 29 02:25:52 PM PDT 23
Peak memory 215852 kb
Host smart-1fe576f7-679c-4fbd-b640-b395026e066d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543338532480501456918449274
33728815026816614188670015029023105575170187256860 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.54333853248
050145691844927433728815026816614188670015029023105575170187256860
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.97116753280784126381180052256751394141956865186893644613162517321378815223863
Short name T726
Test name
Test status
Simulation time 18259183 ps
CPU time 0.98 seconds
Started Oct 29 02:08:09 PM PDT 23
Finished Oct 29 02:08:10 PM PDT 23
Peak memory 205524 kb
Host smart-7551ae4c-aa41-49d1-b22f-8c9b670c034f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97116753280784126381180052256751394141956865186893644613162517321378815223863 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 49.edn_alert.97116753280784126381180052256751394141956865186893644613162517321378815223863
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.108901581389183835535981663129040802271156320961994099387794809930072458514390
Short name T592
Test name
Test status
Simulation time 28184990 ps
CPU time 0.9 seconds
Started Oct 29 02:08:41 PM PDT 23
Finished Oct 29 02:08:43 PM PDT 23
Peak memory 205476 kb
Host smart-f455e14d-d0e4-4aea-bcef-1afb64e73f02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108901581389183835535981663129040802271156320961994099387794809930072458514390 -assert nopostp
roc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 49.edn_alert_test.108901581389183835535981663129040802271156320961994099387794809930072458514390
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.61198425819408022825100886478819557177299297775418476508678497974046052716137
Short name T587
Test name
Test status
Simulation time 12219183 ps
CPU time 0.86 seconds
Started Oct 29 02:08:41 PM PDT 23
Finished Oct 29 02:08:43 PM PDT 23
Peak memory 214804 kb
Host smart-94fc8bbe-3aca-4746-a2ef-f4995a4e423c
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61198425819408022825100886478819557177299297775418476508678497974046052716137 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.edn_disable.61198425819408022825100886478819557177299297775418476508678497974046052716137
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.111141281582750958304141537326918295179178702106159595586376106269522084506510
Short name T432
Test name
Test status
Simulation time 17319183 ps
CPU time 0.86 seconds
Started Oct 29 02:07:45 PM PDT 23
Finished Oct 29 02:07:46 PM PDT 23
Peak memory 214864 kb
Host smart-f599782d-20d2-46dd-ad2a-ce54bea50759
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111141281582750958304141537326918295179178702106159595586376106269522084506510 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable_auto_req_mode.111141281582750958304141537326918295179178702106159595586
376106269522084506510
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.56852626709802333637543557174691992918628306894740270914797260775743150191661
Short name T716
Test name
Test status
Simulation time 24963823 ps
CPU time 1.09 seconds
Started Oct 29 02:07:45 PM PDT 23
Finished Oct 29 02:07:46 PM PDT 23
Peak memory 230420 kb
Host smart-8d2ef244-3618-4090-9d55-e3bb9b965368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56852626709802333637543557174691992918628306894740270914797260775743150191661 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.edn_err.56852626709802333637543557174691992918628306894740270914797260775743150191661
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.109683667213434138035787557335690930991280183960310135659466184048352557098976
Short name T834
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Oct 29 02:07:50 PM PDT 23
Finished Oct 29 02:07:52 PM PDT 23
Peak memory 205820 kb
Host smart-fb3658c5-dea4-403c-8785-9297ed234b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109683667213434138035787557335690930991280183960310135659466184048352557098976 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 49.edn_genbits.109683667213434138035787557335690930991280183960310135659466184048352557098976
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.48710072886937571677098718755980432174282378029374838361416545155028191709222
Short name T33
Test name
Test status
Simulation time 18439183 ps
CPU time 1.15 seconds
Started Oct 29 02:08:02 PM PDT 23
Finished Oct 29 02:08:04 PM PDT 23
Peak memory 222220 kb
Host smart-3e76bcfc-d24e-4927-9efc-e0dbe604f585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48710072886937571677098718755980432174282378029374838361416545155028191709222 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.edn_intr.48710072886937571677098718755980432174282378029374838361416545155028191709222
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.60837443666321150762729620125325392667910992443011508404230924012460041318681
Short name T261
Test name
Test status
Simulation time 13059183 ps
CPU time 0.89 seconds
Started Oct 29 02:08:33 PM PDT 23
Finished Oct 29 02:08:34 PM PDT 23
Peak memory 205372 kb
Host smart-1f427c3b-91f2-4c78-9366-518c405c5797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60837443666321150762729620125325392667910992443011508404230924012460041318681 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 49.edn_smoke.60837443666321150762729620125325392667910992443011508404230924012460041318681
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.78539128057769605864154363400893966770026975817087026483503238748159289871341
Short name T856
Test name
Test status
Simulation time 154489183 ps
CPU time 4.07 seconds
Started Oct 29 02:07:51 PM PDT 23
Finished Oct 29 02:07:55 PM PDT 23
Peak memory 206344 kb
Host smart-f3f874e6-5c89-4120-87d1-47561cafdaf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78539128057769605864154363400893966770026975817087026483503238748159289871341 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.78539128057769605864154363400893966770026975817087026483503238748159289871341
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.69467040762956440228913621920955056860504439975110990959952471342927810343114
Short name T575
Test name
Test status
Simulation time 41708099183 ps
CPU time 1074.37 seconds
Started Oct 29 02:08:08 PM PDT 23
Finished Oct 29 02:26:03 PM PDT 23
Peak memory 215880 kb
Host smart-5ed14d85-2468-4f8a-9aea-097e88ba3454
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694670407629564402289136219
20955056860504439975110990959952471342927810343114 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.69467040762
956440228913621920955056860504439975110990959952471342927810343114
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.26300304882490141277823620341851198526955130948353043354148997814040426152287
Short name T300
Test name
Test status
Simulation time 18259183 ps
CPU time 0.97 seconds
Started Oct 29 02:06:36 PM PDT 23
Finished Oct 29 02:06:37 PM PDT 23
Peak memory 205712 kb
Host smart-fd2e5648-32ac-4e21-bbd9-8b84a6cb72b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26300304882490141277823620341851198526955130948353043354148997814040426152287 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.edn_alert.26300304882490141277823620341851198526955130948353043354148997814040426152287
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.5602545224815666805674494625930018584501853682158962221589037027959968114663
Short name T584
Test name
Test status
Simulation time 28184990 ps
CPU time 0.87 seconds
Started Oct 29 02:06:33 PM PDT 23
Finished Oct 29 02:06:34 PM PDT 23
Peak memory 205508 kb
Host smart-127c7341-0ee9-4c24-a907-caa60ee4c99c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5602545224815666805674494625930018584501853682158962221589037027959968114663 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.edn_alert_test.5602545224815666805674494625930018584501853682158962221589037027959968114663
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.111178504565679908861295093475987318428900950392593493113910427836169622550046
Short name T953
Test name
Test status
Simulation time 12219183 ps
CPU time 0.89 seconds
Started Oct 29 02:07:00 PM PDT 23
Finished Oct 29 02:07:04 PM PDT 23
Peak memory 214856 kb
Host smart-e2c736ad-a060-4703-af9a-243f307c5e14
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111178504565679908861295093475987318428900950392593493113910427836169622550046 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 5.edn_disable.111178504565679908861295093475987318428900950392593493113910427836169622550046
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.101218672698896049035107614064523033478931350057770055908641490801682084290306
Short name T22
Test name
Test status
Simulation time 17319183 ps
CPU time 0.93 seconds
Started Oct 29 02:07:29 PM PDT 23
Finished Oct 29 02:07:31 PM PDT 23
Peak memory 214888 kb
Host smart-5b8607bd-fc96-4063-9c5b-a3a67fe71218
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101218672698896049035107614064523033478931350057770055908641490801682084290306 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable_auto_req_mode.1012186726988960490351076140645230334789313500577700559086
41490801682084290306
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.107329703237498161613821423210206154834970894772373988881737529813727194643796
Short name T907
Test name
Test status
Simulation time 24963823 ps
CPU time 1.17 seconds
Started Oct 29 02:07:20 PM PDT 23
Finished Oct 29 02:07:22 PM PDT 23
Peak memory 230444 kb
Host smart-ee802c14-a01f-4954-a8bc-6f423c1aa6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107329703237498161613821423210206154834970894772373988881737529813727194643796 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.edn_err.107329703237498161613821423210206154834970894772373988881737529813727194643796
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.85840408904913307784570912681345071995782426272873193497946889228000191584421
Short name T409
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Oct 29 02:06:36 PM PDT 23
Finished Oct 29 02:06:38 PM PDT 23
Peak memory 205848 kb
Host smart-c151f975-84b3-42f4-a982-a5cf6c28634c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85840408904913307784570912681345071995782426272873193497946889228000191584421 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.edn_genbits.85840408904913307784570912681345071995782426272873193497946889228000191584421
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.80097839100518799002778263566924237264066508268764273538800411060076825958697
Short name T733
Test name
Test status
Simulation time 18439183 ps
CPU time 1.15 seconds
Started Oct 29 02:06:34 PM PDT 23
Finished Oct 29 02:06:36 PM PDT 23
Peak memory 222236 kb
Host smart-74e6121b-2d06-4949-895a-cd70f832f5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80097839100518799002778263566924237264066508268764273538800411060076825958697 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.edn_intr.80097839100518799002778263566924237264066508268764273538800411060076825958697
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.97052815574574278422220590111680441186251922611695975202274605083883724704509
Short name T431
Test name
Test status
Simulation time 11759183 ps
CPU time 0.88 seconds
Started Oct 29 02:06:55 PM PDT 23
Finished Oct 29 02:06:56 PM PDT 23
Peak memory 205268 kb
Host smart-3d9f33b4-8626-42f1-b36f-0afbca4b1d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97052815574574278422220590111680441186251922611695975202274605083883724704509 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.edn_regwen.97052815574574278422220590111680441186251922611695975202274605083883724704509
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.85003620960158139902651518846529820629178545351381764945851475005049219670461
Short name T280
Test name
Test status
Simulation time 13059183 ps
CPU time 0.87 seconds
Started Oct 29 02:06:32 PM PDT 23
Finished Oct 29 02:06:33 PM PDT 23
Peak memory 205268 kb
Host smart-4651e923-60ba-4058-969f-a6b664d39048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85003620960158139902651518846529820629178545351381764945851475005049219670461 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.edn_smoke.85003620960158139902651518846529820629178545351381764945851475005049219670461
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.66735021404042139643556179732502577005260766889480677991561581040164063420923
Short name T245
Test name
Test status
Simulation time 154489183 ps
CPU time 3.94 seconds
Started Oct 29 02:06:32 PM PDT 23
Finished Oct 29 02:06:36 PM PDT 23
Peak memory 206296 kb
Host smart-ceae19b9-5cb3-4fb2-9a97-1b67d0755968
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66735021404042139643556179732502577005260766889480677991561581040164063420923 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.66735021404042139643556179732502577005260766889480677991561581040164063420923
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.107224797562026266149536322457530923703727144152412380485751823416383099787001
Short name T672
Test name
Test status
Simulation time 41708099183 ps
CPU time 1101.8 seconds
Started Oct 29 02:06:34 PM PDT 23
Finished Oct 29 02:24:57 PM PDT 23
Peak memory 215812 kb
Host smart-f2a2e245-9f16-4eb2-9a8e-93e7e62d7d88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107224797562026266149536322
457530923703727144152412380485751823416383099787001 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.10722479756
2026266149536322457530923703727144152412380485751823416383099787001
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.34987754786917844916605299495416659175097589722013524635567616016313460697595
Short name T508
Test name
Test status
Simulation time 24963823 ps
CPU time 1.17 seconds
Started Oct 29 02:09:24 PM PDT 23
Finished Oct 29 02:09:26 PM PDT 23
Peak memory 230496 kb
Host smart-65efb7bc-fa4d-4ed8-b6a4-00298c481514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34987754786917844916605299495416659175097589722013524635567616016313460697595 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50
.edn_err.34987754786917844916605299495416659175097589722013524635567616016313460697595
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.5983073981594120372879737129312811313998248468444664404504468821642458478114
Short name T554
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:07:45 PM PDT 23
Finished Oct 29 02:07:47 PM PDT 23
Peak memory 205820 kb
Host smart-7b855989-9765-44de-94ba-92228cd78169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5983073981594120372879737129312811313998248468444664404504468821642458478114 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 50.edn_genbits.5983073981594120372879737129312811313998248468444664404504468821642458478114
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.113420501559450908955810669188046024819531661147769502628698378953654041003561
Short name T777
Test name
Test status
Simulation time 24963823 ps
CPU time 1.09 seconds
Started Oct 29 02:08:36 PM PDT 23
Finished Oct 29 02:08:37 PM PDT 23
Peak memory 230268 kb
Host smart-68fe4607-1c13-479e-a8e3-97ea43e11275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113420501559450908955810669188046024819531661147769502628698378953654041003561 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
1.edn_err.113420501559450908955810669188046024819531661147769502628698378953654041003561
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.24859121521810751308203145362361070205563144248054116601754876477762483150623
Short name T430
Test name
Test status
Simulation time 17999183 ps
CPU time 1.15 seconds
Started Oct 29 02:08:05 PM PDT 23
Finished Oct 29 02:08:06 PM PDT 23
Peak memory 205852 kb
Host smart-95e603e9-09fc-43e0-ac8f-452c8230f8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24859121521810751308203145362361070205563144248054116601754876477762483150623 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 51.edn_genbits.24859121521810751308203145362361070205563144248054116601754876477762483150623
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.76201901218148578248935498712338302005154612219323129006540307332550603485672
Short name T279
Test name
Test status
Simulation time 24963823 ps
CPU time 1.16 seconds
Started Oct 29 02:09:02 PM PDT 23
Finished Oct 29 02:09:04 PM PDT 23
Peak memory 230460 kb
Host smart-80cdcf42-3505-4588-8da1-926fb249462f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76201901218148578248935498712338302005154612219323129006540307332550603485672 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52
.edn_err.76201901218148578248935498712338302005154612219323129006540307332550603485672
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.17610849781701127960479977308781763619510471678002413624684546972705576501055
Short name T297
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Oct 29 02:08:11 PM PDT 23
Finished Oct 29 02:08:13 PM PDT 23
Peak memory 205852 kb
Host smart-3421e9cb-91ac-44d8-828e-c1010dac0e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17610849781701127960479977308781763619510471678002413624684546972705576501055 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 52.edn_genbits.17610849781701127960479977308781763619510471678002413624684546972705576501055
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.80345445541270260312426022176461375471979252570111535690800955832766740862434
Short name T501
Test name
Test status
Simulation time 24963823 ps
CPU time 1.19 seconds
Started Oct 29 02:08:11 PM PDT 23
Finished Oct 29 02:08:13 PM PDT 23
Peak memory 230424 kb
Host smart-39fd30a7-397d-4e74-ba6c-635216c88f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80345445541270260312426022176461375471979252570111535690800955832766740862434 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53
.edn_err.80345445541270260312426022176461375471979252570111535690800955832766740862434
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.4103738406903972790676265793791634336022679586172368235335302340217615575900
Short name T749
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:08:04 PM PDT 23
Finished Oct 29 02:08:06 PM PDT 23
Peak memory 205808 kb
Host smart-b922d5ea-4554-4928-b047-aa32ef0ee341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103738406903972790676265793791634336022679586172368235335302340217615575900 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 53.edn_genbits.4103738406903972790676265793791634336022679586172368235335302340217615575900
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.625805390100237642665563674656547180245539540051690626625438548085862744243
Short name T37
Test name
Test status
Simulation time 24963823 ps
CPU time 1.11 seconds
Started Oct 29 02:09:47 PM PDT 23
Finished Oct 29 02:09:48 PM PDT 23
Peak memory 230456 kb
Host smart-85243234-7bf8-4075-9025-9f5fc7b60429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625805390100237642665563674656547180245539540051690626625438548085862744243 -assert nopostproc +UVM_TESTNAME=edn_err_tes
t +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.e
dn_err.625805390100237642665563674656547180245539540051690626625438548085862744243
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.70636230905988112695488339029619923078998360708176772053826110519663981957193
Short name T276
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Oct 29 02:08:08 PM PDT 23
Finished Oct 29 02:08:09 PM PDT 23
Peak memory 205768 kb
Host smart-9102c225-05bd-4d7e-bc8b-523adbe0d62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70636230905988112695488339029619923078998360708176772053826110519663981957193 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 54.edn_genbits.70636230905988112695488339029619923078998360708176772053826110519663981957193
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.52018945155046751226060326361728073151354000955604082094237777841585252603513
Short name T515
Test name
Test status
Simulation time 24963823 ps
CPU time 1.21 seconds
Started Oct 29 02:08:12 PM PDT 23
Finished Oct 29 02:08:13 PM PDT 23
Peak memory 230428 kb
Host smart-51a3f17b-381e-4bd8-afd5-2025dcded3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52018945155046751226060326361728073151354000955604082094237777841585252603513 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55
.edn_err.52018945155046751226060326361728073151354000955604082094237777841585252603513
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.22051664667124106156047388754470059936147921889155638302489663024070091207797
Short name T589
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Oct 29 02:08:36 PM PDT 23
Finished Oct 29 02:08:37 PM PDT 23
Peak memory 205832 kb
Host smart-518df666-d411-4b24-9186-739b93799056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22051664667124106156047388754470059936147921889155638302489663024070091207797 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 55.edn_genbits.22051664667124106156047388754470059936147921889155638302489663024070091207797
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.80007812646322131184529289771040884677988305015056632341671194851443890123844
Short name T362
Test name
Test status
Simulation time 24963823 ps
CPU time 1.12 seconds
Started Oct 29 02:09:45 PM PDT 23
Finished Oct 29 02:09:47 PM PDT 23
Peak memory 230452 kb
Host smart-6957fe16-c4ef-46ec-ac52-6985d6786731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80007812646322131184529289771040884677988305015056632341671194851443890123844 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56
.edn_err.80007812646322131184529289771040884677988305015056632341671194851443890123844
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.83783773890957417435168337594796803988243674512269430039142321924425060813115
Short name T552
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Oct 29 02:09:08 PM PDT 23
Finished Oct 29 02:09:09 PM PDT 23
Peak memory 205828 kb
Host smart-52fade13-fb78-4ae3-862b-e0efa7f44149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83783773890957417435168337594796803988243674512269430039142321924425060813115 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 56.edn_genbits.83783773890957417435168337594796803988243674512269430039142321924425060813115
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.100859928720278231513946205806765530859933807988387024375450796255578541966429
Short name T615
Test name
Test status
Simulation time 24963823 ps
CPU time 1.14 seconds
Started Oct 29 02:08:47 PM PDT 23
Finished Oct 29 02:08:49 PM PDT 23
Peak memory 230452 kb
Host smart-bef31323-cf57-4ec3-99e9-28c873b31400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100859928720278231513946205806765530859933807988387024375450796255578541966429 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
7.edn_err.100859928720278231513946205806765530859933807988387024375450796255578541966429
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.3738298852711565328300878147156825931820387576669050805494859688981394930958
Short name T741
Test name
Test status
Simulation time 17999183 ps
CPU time 1.19 seconds
Started Oct 29 02:08:34 PM PDT 23
Finished Oct 29 02:08:35 PM PDT 23
Peak memory 205896 kb
Host smart-f7b6c86d-fc8c-4fbe-847d-49aa39c4f3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738298852711565328300878147156825931820387576669050805494859688981394930958 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 57.edn_genbits.3738298852711565328300878147156825931820387576669050805494859688981394930958
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.18743205605561550699302597947995157235075434966438966004393503681835787621914
Short name T540
Test name
Test status
Simulation time 24963823 ps
CPU time 1.13 seconds
Started Oct 29 02:09:38 PM PDT 23
Finished Oct 29 02:09:40 PM PDT 23
Peak memory 230448 kb
Host smart-e25f2fc0-c141-4ee2-80ab-643968937734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18743205605561550699302597947995157235075434966438966004393503681835787621914 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58
.edn_err.18743205605561550699302597947995157235075434966438966004393503681835787621914
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.97124975712381720951658925041453604748492972910059895187434134718912128381761
Short name T348
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Oct 29 02:08:35 PM PDT 23
Finished Oct 29 02:08:36 PM PDT 23
Peak memory 205876 kb
Host smart-f3e30298-05da-40f3-b826-21802514df66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97124975712381720951658925041453604748492972910059895187434134718912128381761 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 58.edn_genbits.97124975712381720951658925041453604748492972910059895187434134718912128381761
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.4096177555630369276757342843765655788488413156475765786675177341170674115487
Short name T366
Test name
Test status
Simulation time 24963823 ps
CPU time 1.24 seconds
Started Oct 29 02:08:09 PM PDT 23
Finished Oct 29 02:08:10 PM PDT 23
Peak memory 230436 kb
Host smart-764a1ddb-4a29-4c85-ae77-2d882a09a5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096177555630369276757342843765655788488413156475765786675177341170674115487 -assert nopostproc +UVM_TESTNAME=edn_err_te
st +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.
edn_err.4096177555630369276757342843765655788488413156475765786675177341170674115487
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.95096577002229872925517058223646222287130503797887083694936645325317905857751
Short name T837
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Oct 29 02:08:41 PM PDT 23
Finished Oct 29 02:08:43 PM PDT 23
Peak memory 205816 kb
Host smart-b0b39475-20f5-4b8f-9861-f501409b1728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95096577002229872925517058223646222287130503797887083694936645325317905857751 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 59.edn_genbits.95096577002229872925517058223646222287130503797887083694936645325317905857751
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.91688172083364483848246649925626912457267849625628280546954985314602518398159
Short name T869
Test name
Test status
Simulation time 18259183 ps
CPU time 1.02 seconds
Started Oct 29 02:06:37 PM PDT 23
Finished Oct 29 02:06:39 PM PDT 23
Peak memory 205464 kb
Host smart-f04fb8ef-6e9c-44c9-8260-01ea11f106e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91688172083364483848246649925626912457267849625628280546954985314602518398159 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.edn_alert.91688172083364483848246649925626912457267849625628280546954985314602518398159
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.111779838329901523198209364471154585182974458902638317752226843635541200964403
Short name T938
Test name
Test status
Simulation time 28184990 ps
CPU time 0.92 seconds
Started Oct 29 02:06:33 PM PDT 23
Finished Oct 29 02:06:34 PM PDT 23
Peak memory 205528 kb
Host smart-879ef38a-6529-4e1f-9d30-672f0115e1ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111779838329901523198209364471154585182974458902638317752226843635541200964403 -assert nopostp
roc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 6.edn_alert_test.111779838329901523198209364471154585182974458902638317752226843635541200964403
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.110847000105374297324035791305337987615517023820075372594120327578570044340862
Short name T947
Test name
Test status
Simulation time 12219183 ps
CPU time 0.88 seconds
Started Oct 29 02:06:58 PM PDT 23
Finished Oct 29 02:07:01 PM PDT 23
Peak memory 214904 kb
Host smart-edb9c2f1-0f20-40c8-aa14-f23c651bd8d5
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110847000105374297324035791305337987615517023820075372594120327578570044340862 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 6.edn_disable.110847000105374297324035791305337987615517023820075372594120327578570044340862
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_err.31747276127107671425482710889298500507346917310136488883641680825031707880925
Short name T291
Test name
Test status
Simulation time 24963823 ps
CPU time 1.18 seconds
Started Oct 29 02:06:41 PM PDT 23
Finished Oct 29 02:06:43 PM PDT 23
Peak memory 230460 kb
Host smart-cb408c3e-3208-4770-b83f-4603b310b277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31747276127107671425482710889298500507346917310136488883641680825031707880925 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
edn_err.31747276127107671425482710889298500507346917310136488883641680825031707880925
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.100181646810092074915799785555823322151160917415076770834952531317170787625039
Short name T265
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Oct 29 02:07:24 PM PDT 23
Finished Oct 29 02:07:26 PM PDT 23
Peak memory 205844 kb
Host smart-16ebd8f5-d16a-4b2f-8591-e3d4f4e46a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100181646810092074915799785555823322151160917415076770834952531317170787625039 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 6.edn_genbits.100181646810092074915799785555823322151160917415076770834952531317170787625039
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.100389138468903166395175496926661072654657759486581939776113542642895574382076
Short name T342
Test name
Test status
Simulation time 18439183 ps
CPU time 1.11 seconds
Started Oct 29 02:07:00 PM PDT 23
Finished Oct 29 02:07:05 PM PDT 23
Peak memory 222176 kb
Host smart-9933400b-71da-4cd4-85f4-82173f1c3e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100389138468903166395175496926661072654657759486581939776113542642895574382076 -assert nopostproc +UVM_TESTNAME=edn_intr
_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.edn_intr.100389138468903166395175496926661072654657759486581939776113542642895574382076
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.76314892161492758557759066182425871468650181474263999238045109636705477538813
Short name T408
Test name
Test status
Simulation time 11759183 ps
CPU time 0.86 seconds
Started Oct 29 02:06:56 PM PDT 23
Finished Oct 29 02:06:57 PM PDT 23
Peak memory 205312 kb
Host smart-cc056c63-8618-4de2-a3e1-e728a1c31f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76314892161492758557759066182425871468650181474263999238045109636705477538813 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.edn_regwen.76314892161492758557759066182425871468650181474263999238045109636705477538813
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.5486741244763546001714959920956148464322311466194396703374688274155676830501
Short name T468
Test name
Test status
Simulation time 13059183 ps
CPU time 0.88 seconds
Started Oct 29 02:06:33 PM PDT 23
Finished Oct 29 02:06:35 PM PDT 23
Peak memory 205296 kb
Host smart-ed7e7644-4003-4eee-89ae-2ddb609ca8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5486741244763546001714959920956148464322311466194396703374688274155676830501 -assert nopostproc +UVM_TESTNAME=edn_smoke_
test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.edn_smoke.5486741244763546001714959920956148464322311466194396703374688274155676830501
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.79317839504215381306865167175449001054227536208539947435514121198404957278090
Short name T653
Test name
Test status
Simulation time 154489183 ps
CPU time 3.81 seconds
Started Oct 29 02:07:00 PM PDT 23
Finished Oct 29 02:07:04 PM PDT 23
Peak memory 206344 kb
Host smart-db69d909-cea7-493f-8f37-62f9ce931027
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79317839504215381306865167175449001054227536208539947435514121198404957278090 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.79317839504215381306865167175449001054227536208539947435514121198404957278090
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/60.edn_err.94962690464448226169229405324260927915075633382057069297737883069454194241683
Short name T593
Test name
Test status
Simulation time 24963823 ps
CPU time 1.11 seconds
Started Oct 29 02:08:40 PM PDT 23
Finished Oct 29 02:08:43 PM PDT 23
Peak memory 230460 kb
Host smart-dd39869b-2810-47a7-a016-0b3ab50744fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94962690464448226169229405324260927915075633382057069297737883069454194241683 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60
.edn_err.94962690464448226169229405324260927915075633382057069297737883069454194241683
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.79410932358825082566353914726629243288495811988759852322979650767356909817884
Short name T625
Test name
Test status
Simulation time 17999183 ps
CPU time 1.15 seconds
Started Oct 29 02:08:13 PM PDT 23
Finished Oct 29 02:08:14 PM PDT 23
Peak memory 205808 kb
Host smart-0872a07f-da1e-4431-a3b9-46ca94ef8416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79410932358825082566353914726629243288495811988759852322979650767356909817884 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 60.edn_genbits.79410932358825082566353914726629243288495811988759852322979650767356909817884
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.86611833766316849245995557092364500867684694226077427825314494254876683786657
Short name T547
Test name
Test status
Simulation time 24963823 ps
CPU time 1.18 seconds
Started Oct 29 02:09:05 PM PDT 23
Finished Oct 29 02:09:06 PM PDT 23
Peak memory 230424 kb
Host smart-1bb848b3-b06e-408b-a580-528361641a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86611833766316849245995557092364500867684694226077427825314494254876683786657 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61
.edn_err.86611833766316849245995557092364500867684694226077427825314494254876683786657
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.68111165200814559563946903251827432212865852102719911041191568116174606038203
Short name T41
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:09:23 PM PDT 23
Finished Oct 29 02:09:24 PM PDT 23
Peak memory 205844 kb
Host smart-aa6e2e0a-261f-4270-b6a9-b3cfa4399e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68111165200814559563946903251827432212865852102719911041191568116174606038203 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 61.edn_genbits.68111165200814559563946903251827432212865852102719911041191568116174606038203
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.63685350850904421340470059261795934797216017755880184869272918930712164885288
Short name T809
Test name
Test status
Simulation time 24963823 ps
CPU time 1.15 seconds
Started Oct 29 02:08:37 PM PDT 23
Finished Oct 29 02:08:38 PM PDT 23
Peak memory 230460 kb
Host smart-b87ed2d8-9077-4714-8d10-0a03e853ac3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63685350850904421340470059261795934797216017755880184869272918930712164885288 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62
.edn_err.63685350850904421340470059261795934797216017755880184869272918930712164885288
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.26602378310681779517283745251339994001541494242973370479373238353394405917847
Short name T56
Test name
Test status
Simulation time 17999183 ps
CPU time 1.05 seconds
Started Oct 29 02:09:20 PM PDT 23
Finished Oct 29 02:09:21 PM PDT 23
Peak memory 205808 kb
Host smart-39008cbd-b52f-4ee5-816f-bef1b26aff54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26602378310681779517283745251339994001541494242973370479373238353394405917847 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 62.edn_genbits.26602378310681779517283745251339994001541494242973370479373238353394405917847
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.69193254288189173442944811907225760601046127257152695743685905075677483396177
Short name T885
Test name
Test status
Simulation time 24963823 ps
CPU time 1.16 seconds
Started Oct 29 02:08:42 PM PDT 23
Finished Oct 29 02:08:44 PM PDT 23
Peak memory 230440 kb
Host smart-87007d7a-b6be-41ea-afc2-3152e177087f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69193254288189173442944811907225760601046127257152695743685905075677483396177 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63
.edn_err.69193254288189173442944811907225760601046127257152695743685905075677483396177
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.40168656258600489425220342194007788418086188594591099701313707423420726755337
Short name T516
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Oct 29 02:08:09 PM PDT 23
Finished Oct 29 02:08:10 PM PDT 23
Peak memory 205768 kb
Host smart-78653119-4b83-46a4-943d-a293afd94779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40168656258600489425220342194007788418086188594591099701313707423420726755337 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 63.edn_genbits.40168656258600489425220342194007788418086188594591099701313707423420726755337
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.78926426025395099459982414092819064370117834869434000835372654644097078607025
Short name T774
Test name
Test status
Simulation time 24963823 ps
CPU time 1.15 seconds
Started Oct 29 02:08:40 PM PDT 23
Finished Oct 29 02:08:44 PM PDT 23
Peak memory 230548 kb
Host smart-a3be0a53-7947-4bb3-831e-eef514334af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78926426025395099459982414092819064370117834869434000835372654644097078607025 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64
.edn_err.78926426025395099459982414092819064370117834869434000835372654644097078607025
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.111363978472616710442139101003939794549437401477533258589337231323104462548596
Short name T403
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Oct 29 02:08:42 PM PDT 23
Finished Oct 29 02:08:44 PM PDT 23
Peak memory 205916 kb
Host smart-be471760-e5e6-4880-ab78-9858a45d6aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111363978472616710442139101003939794549437401477533258589337231323104462548596 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 64.edn_genbits.111363978472616710442139101003939794549437401477533258589337231323104462548596
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.73629979828121910864162821981991876250373305032334139995636888127318987158307
Short name T600
Test name
Test status
Simulation time 24963823 ps
CPU time 1.09 seconds
Started Oct 29 02:08:41 PM PDT 23
Finished Oct 29 02:08:43 PM PDT 23
Peak memory 230328 kb
Host smart-f133e793-971f-412a-9b9e-8992a9203010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73629979828121910864162821981991876250373305032334139995636888127318987158307 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65
.edn_err.73629979828121910864162821981991876250373305032334139995636888127318987158307
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.75590274949826491246173283564726120975583997782482751461989663989125679785445
Short name T954
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Oct 29 02:08:45 PM PDT 23
Finished Oct 29 02:08:47 PM PDT 23
Peak memory 205856 kb
Host smart-212404cd-e423-435c-82df-de11b08dd052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75590274949826491246173283564726120975583997782482751461989663989125679785445 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 65.edn_genbits.75590274949826491246173283564726120975583997782482751461989663989125679785445
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.18694998542697534876997691369785843241578480460278346944947164007281772829947
Short name T750
Test name
Test status
Simulation time 24963823 ps
CPU time 1.15 seconds
Started Oct 29 02:09:02 PM PDT 23
Finished Oct 29 02:09:04 PM PDT 23
Peak memory 230504 kb
Host smart-0b9334dc-073d-404d-8a2d-222d83dfd57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18694998542697534876997691369785843241578480460278346944947164007281772829947 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66
.edn_err.18694998542697534876997691369785843241578480460278346944947164007281772829947
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.29259052418271258365990382632233196089395138149639115837681551497757869638563
Short name T423
Test name
Test status
Simulation time 17999183 ps
CPU time 1.16 seconds
Started Oct 29 02:08:41 PM PDT 23
Finished Oct 29 02:08:43 PM PDT 23
Peak memory 205900 kb
Host smart-2b02db78-22c9-408e-b821-de44b21865bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29259052418271258365990382632233196089395138149639115837681551497757869638563 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 66.edn_genbits.29259052418271258365990382632233196089395138149639115837681551497757869638563
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.39352749840124566250542468047764740026201082570690598648815979608914184385225
Short name T789
Test name
Test status
Simulation time 24963823 ps
CPU time 1.14 seconds
Started Oct 29 02:09:41 PM PDT 23
Finished Oct 29 02:09:42 PM PDT 23
Peak memory 230400 kb
Host smart-10f92eee-c0ae-418b-961f-fc0e74fa5631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39352749840124566250542468047764740026201082570690598648815979608914184385225 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67
.edn_err.39352749840124566250542468047764740026201082570690598648815979608914184385225
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.115097900928349383170591385966207083638869216005120051089988118143050813351628
Short name T528
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Oct 29 02:08:35 PM PDT 23
Finished Oct 29 02:08:36 PM PDT 23
Peak memory 205832 kb
Host smart-bbfa8af4-732f-4c3b-8226-eda4c354c73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115097900928349383170591385966207083638869216005120051089988118143050813351628 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 67.edn_genbits.115097900928349383170591385966207083638869216005120051089988118143050813351628
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.49039954428568845073874003331175360410964801614067842862062003456130681390907
Short name T393
Test name
Test status
Simulation time 24963823 ps
CPU time 1.11 seconds
Started Oct 29 02:08:42 PM PDT 23
Finished Oct 29 02:08:44 PM PDT 23
Peak memory 230460 kb
Host smart-963a1252-2149-467c-b3f4-cea67a566ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49039954428568845073874003331175360410964801614067842862062003456130681390907 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68
.edn_err.49039954428568845073874003331175360410964801614067842862062003456130681390907
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.70509681959198753856690409076767216326501326283366419441352589665003034119645
Short name T347
Test name
Test status
Simulation time 17999183 ps
CPU time 1.17 seconds
Started Oct 29 02:08:12 PM PDT 23
Finished Oct 29 02:08:14 PM PDT 23
Peak memory 205796 kb
Host smart-bc90b6d7-7fd9-4278-a68c-2437eb742f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70509681959198753856690409076767216326501326283366419441352589665003034119645 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 68.edn_genbits.70509681959198753856690409076767216326501326283366419441352589665003034119645
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.902189026257439278891926841445879671581400221254107365973515594692354856170
Short name T821
Test name
Test status
Simulation time 24963823 ps
CPU time 1.19 seconds
Started Oct 29 02:09:00 PM PDT 23
Finished Oct 29 02:09:04 PM PDT 23
Peak memory 230404 kb
Host smart-36704157-d014-4caf-9a84-d2984e12a33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902189026257439278891926841445879671581400221254107365973515594692354856170 -assert nopostproc +UVM_TESTNAME=edn_err_tes
t +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.e
dn_err.902189026257439278891926841445879671581400221254107365973515594692354856170
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.5500736508896658825800907907145890797467518159670197174351920555660531633341
Short name T778
Test name
Test status
Simulation time 17999183 ps
CPU time 1.19 seconds
Started Oct 29 02:08:08 PM PDT 23
Finished Oct 29 02:08:10 PM PDT 23
Peak memory 205780 kb
Host smart-753248b9-0818-46da-a87a-18e7f75b7586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5500736508896658825800907907145890797467518159670197174351920555660531633341 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 69.edn_genbits.5500736508896658825800907907145890797467518159670197174351920555660531633341
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.57822151827888774553673580488585823049039590222610131627320893272059050729859
Short name T461
Test name
Test status
Simulation time 18259183 ps
CPU time 0.98 seconds
Started Oct 29 02:07:29 PM PDT 23
Finished Oct 29 02:07:31 PM PDT 23
Peak memory 205580 kb
Host smart-8ea86a30-088c-4104-9cd9-fffe0ad740d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57822151827888774553673580488585823049039590222610131627320893272059050729859 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.edn_alert.57822151827888774553673580488585823049039590222610131627320893272059050729859
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.55404839219497043000877839923972465065392548816757781639456405911539518343251
Short name T360
Test name
Test status
Simulation time 28184990 ps
CPU time 0.86 seconds
Started Oct 29 02:06:38 PM PDT 23
Finished Oct 29 02:06:39 PM PDT 23
Peak memory 205492 kb
Host smart-0abd963b-aa7b-409b-9ba9-a288eacf183d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55404839219497043000877839923972465065392548816757781639456405911539518343251 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.edn_alert_test.55404839219497043000877839923972465065392548816757781639456405911539518343251
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.7601076253801125342991165622672084885422658289475952456127499278776943117150
Short name T571
Test name
Test status
Simulation time 12219183 ps
CPU time 0.92 seconds
Started Oct 29 02:06:32 PM PDT 23
Finished Oct 29 02:06:33 PM PDT 23
Peak memory 214868 kb
Host smart-846b729d-ab6c-44fa-be15-e8004c6c92b2
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7601076253801125342991165622672084885422658289475952456127499278776943117150 -assert nopostproc
+UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.edn_disable.7601076253801125342991165622672084885422658289475952456127499278776943117150
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.86034433313836139412425355653183807218879436780606348920054479618270622134706
Short name T754
Test name
Test status
Simulation time 17319183 ps
CPU time 0.94 seconds
Started Oct 29 02:06:56 PM PDT 23
Finished Oct 29 02:06:57 PM PDT 23
Peak memory 214784 kb
Host smart-bd31b836-1774-4bdd-8e3c-1774d9cd54de
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86034433313836139412425355653183807218879436780606348920054479618270622134706 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable_auto_req_mode.86034433313836139412425355653183807218879436780606348920054
479618270622134706
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.43412822953955404231760005719894475775095073379526894245090110399484816504330
Short name T875
Test name
Test status
Simulation time 24963823 ps
CPU time 1.13 seconds
Started Oct 29 02:07:19 PM PDT 23
Finished Oct 29 02:07:22 PM PDT 23
Peak memory 230424 kb
Host smart-fdcd2bba-37c3-41f1-9249-ae99e4bee1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43412822953955404231760005719894475775095073379526894245090110399484816504330 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
edn_err.43412822953955404231760005719894475775095073379526894245090110399484816504330
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.81202063185781555580495638960238994308420486424830886796734370056578614633829
Short name T862
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Oct 29 02:06:54 PM PDT 23
Finished Oct 29 02:06:55 PM PDT 23
Peak memory 205872 kb
Host smart-d19cb05e-eea8-42ad-9765-22718036ff09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81202063185781555580495638960238994308420486424830886796734370056578614633829 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.edn_genbits.81202063185781555580495638960238994308420486424830886796734370056578614633829
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.114195192109303675928658392001687983199402353014011751557648120458235090505921
Short name T966
Test name
Test status
Simulation time 18439183 ps
CPU time 1.1 seconds
Started Oct 29 02:07:01 PM PDT 23
Finished Oct 29 02:07:06 PM PDT 23
Peak memory 222232 kb
Host smart-17ec77eb-03e0-46eb-ac6c-2b54144183c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114195192109303675928658392001687983199402353014011751557648120458235090505921 -assert nopostproc +UVM_TESTNAME=edn_intr
_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.edn_intr.114195192109303675928658392001687983199402353014011751557648120458235090505921
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.60181175529132952483992794841136391670147367893492590674032237883731750731238
Short name T93
Test name
Test status
Simulation time 11759183 ps
CPU time 0.86 seconds
Started Oct 29 02:06:40 PM PDT 23
Finished Oct 29 02:06:41 PM PDT 23
Peak memory 205168 kb
Host smart-528ac44b-b41e-4208-b82a-6a95aadc6b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60181175529132952483992794841136391670147367893492590674032237883731750731238 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.edn_regwen.60181175529132952483992794841136391670147367893492590674032237883731750731238
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.17884038697329818184546368209642279216214114623949903332032522169137786176693
Short name T394
Test name
Test status
Simulation time 13059183 ps
CPU time 0.84 seconds
Started Oct 29 02:06:53 PM PDT 23
Finished Oct 29 02:06:54 PM PDT 23
Peak memory 205260 kb
Host smart-ac76ad29-dfc3-44ca-adc4-eca3d18a3ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17884038697329818184546368209642279216214114623949903332032522169137786176693 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.edn_smoke.17884038697329818184546368209642279216214114623949903332032522169137786176693
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.27480431976251856675475718477718087828457580881371367270236080358233528160753
Short name T580
Test name
Test status
Simulation time 154489183 ps
CPU time 3.87 seconds
Started Oct 29 02:07:00 PM PDT 23
Finished Oct 29 02:07:04 PM PDT 23
Peak memory 206344 kb
Host smart-714ebbcc-7248-4199-abd4-2bcb75e790bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27480431976251856675475718477718087828457580881371367270236080358233528160753 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.27480431976251856675475718477718087828457580881371367270236080358233528160753
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.94582592842713565714162409783197793337121779712715506240119460476604999278065
Short name T331
Test name
Test status
Simulation time 41708099183 ps
CPU time 1077.02 seconds
Started Oct 29 02:06:36 PM PDT 23
Finished Oct 29 02:24:33 PM PDT 23
Peak memory 215836 kb
Host smart-1494f48d-d72a-496f-9574-a59e12fe61ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945825928427135657141624097
83197793337121779712715506240119460476604999278065 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.945825928427
13565714162409783197793337121779712715506240119460476604999278065
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.96692895628764068972097905043030280934527039875041147645730701178323758914768
Short name T588
Test name
Test status
Simulation time 24963823 ps
CPU time 1.12 seconds
Started Oct 29 02:08:42 PM PDT 23
Finished Oct 29 02:08:44 PM PDT 23
Peak memory 230528 kb
Host smart-40732438-f53d-4866-9120-1f2abe1ae09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96692895628764068972097905043030280934527039875041147645730701178323758914768 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70
.edn_err.96692895628764068972097905043030280934527039875041147645730701178323758914768
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.96584034809088518699197175450900038825141809797806643630988216209850918749817
Short name T302
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Oct 29 02:09:46 PM PDT 23
Finished Oct 29 02:09:47 PM PDT 23
Peak memory 205868 kb
Host smart-03354767-2cd5-449f-bf51-6fb216ece82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96584034809088518699197175450900038825141809797806643630988216209850918749817 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 70.edn_genbits.96584034809088518699197175450900038825141809797806643630988216209850918749817
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.395004427850450105283086493115187744647535729913766162826770133041362443860
Short name T956
Test name
Test status
Simulation time 24963823 ps
CPU time 1.13 seconds
Started Oct 29 02:08:12 PM PDT 23
Finished Oct 29 02:08:13 PM PDT 23
Peak memory 230420 kb
Host smart-3f5a2ea5-7541-4169-b99a-bffd096ba75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395004427850450105283086493115187744647535729913766162826770133041362443860 -assert nopostproc +UVM_TESTNAME=edn_err_tes
t +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.e
dn_err.395004427850450105283086493115187744647535729913766162826770133041362443860
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.17264493295760025631641689386734465077808459506551693422294900269503651837105
Short name T881
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Oct 29 02:08:09 PM PDT 23
Finished Oct 29 02:08:11 PM PDT 23
Peak memory 205788 kb
Host smart-e26fdf2d-02c6-4cf9-83ef-8156e7416403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17264493295760025631641689386734465077808459506551693422294900269503651837105 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 71.edn_genbits.17264493295760025631641689386734465077808459506551693422294900269503651837105
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.76562534875357573578129976475360725722343802164793551754040820420569724934352
Short name T434
Test name
Test status
Simulation time 24963823 ps
CPU time 1.11 seconds
Started Oct 29 02:08:06 PM PDT 23
Finished Oct 29 02:08:07 PM PDT 23
Peak memory 230464 kb
Host smart-106ecb1d-8709-4e8f-ba91-4bb71a18664f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76562534875357573578129976475360725722343802164793551754040820420569724934352 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72
.edn_err.76562534875357573578129976475360725722343802164793551754040820420569724934352
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.37496499853282660721679100977392185270953474667036740435538373312615814847697
Short name T334
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:08:50 PM PDT 23
Finished Oct 29 02:08:51 PM PDT 23
Peak memory 205992 kb
Host smart-d6f4f97e-118d-4362-9240-3ade2ba1b91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37496499853282660721679100977392185270953474667036740435538373312615814847697 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 72.edn_genbits.37496499853282660721679100977392185270953474667036740435538373312615814847697
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.68014372184543800822575492949253454712985281997405839539414345027349003268192
Short name T20
Test name
Test status
Simulation time 24963823 ps
CPU time 1.13 seconds
Started Oct 29 02:08:36 PM PDT 23
Finished Oct 29 02:08:37 PM PDT 23
Peak memory 230440 kb
Host smart-2447fb89-b0d7-4641-82f1-f5a9d6f5e652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68014372184543800822575492949253454712985281997405839539414345027349003268192 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73
.edn_err.68014372184543800822575492949253454712985281997405839539414345027349003268192
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.112814506854373349872420923574489628273162784837237459171323656059428009405910
Short name T927
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Oct 29 02:08:40 PM PDT 23
Finished Oct 29 02:08:43 PM PDT 23
Peak memory 205720 kb
Host smart-8a8c367c-81d9-4024-8fbb-5345d554bb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112814506854373349872420923574489628273162784837237459171323656059428009405910 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 73.edn_genbits.112814506854373349872420923574489628273162784837237459171323656059428009405910
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.31693146140565148783008781787731627681010409763082773099287658872798788866158
Short name T325
Test name
Test status
Simulation time 24963823 ps
CPU time 1.17 seconds
Started Oct 29 02:08:45 PM PDT 23
Finished Oct 29 02:08:47 PM PDT 23
Peak memory 230492 kb
Host smart-831619ff-c6ad-42bf-89e1-aa94fb53a357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31693146140565148783008781787731627681010409763082773099287658872798788866158 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74
.edn_err.31693146140565148783008781787731627681010409763082773099287658872798788866158
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.15860829401349840128455721328071106387967373257998052372277318055033100721829
Short name T425
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Oct 29 02:08:29 PM PDT 23
Finished Oct 29 02:08:31 PM PDT 23
Peak memory 205860 kb
Host smart-9c1f9d12-5596-45f1-a3ab-a88a0073352e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15860829401349840128455721328071106387967373257998052372277318055033100721829 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 74.edn_genbits.15860829401349840128455721328071106387967373257998052372277318055033100721829
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.83619501376440919530938216177474213117463094773312880638518160464371974812206
Short name T268
Test name
Test status
Simulation time 24963823 ps
CPU time 1.13 seconds
Started Oct 29 02:08:36 PM PDT 23
Finished Oct 29 02:08:38 PM PDT 23
Peak memory 230476 kb
Host smart-60c2fc9b-fe47-44e4-8f30-ca706b823f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83619501376440919530938216177474213117463094773312880638518160464371974812206 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75
.edn_err.83619501376440919530938216177474213117463094773312880638518160464371974812206
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.53610152909261722664555247641295078570552536580651913346374445125247943373005
Short name T978
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Oct 29 02:08:17 PM PDT 23
Finished Oct 29 02:08:18 PM PDT 23
Peak memory 205808 kb
Host smart-cba4ec8f-3e82-4714-8c40-5c52eab3fb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53610152909261722664555247641295078570552536580651913346374445125247943373005 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 75.edn_genbits.53610152909261722664555247641295078570552536580651913346374445125247943373005
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.86599532035686265944398592813805806070783609289497179042047584337686674065231
Short name T304
Test name
Test status
Simulation time 24963823 ps
CPU time 1.2 seconds
Started Oct 29 02:08:10 PM PDT 23
Finished Oct 29 02:08:11 PM PDT 23
Peak memory 230436 kb
Host smart-5877f014-658f-47bd-8ee5-618dc4d7d8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86599532035686265944398592813805806070783609289497179042047584337686674065231 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76
.edn_err.86599532035686265944398592813805806070783609289497179042047584337686674065231
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.40424815475841654394383066807137914630198223627646404081143093648428364635488
Short name T704
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Oct 29 02:08:39 PM PDT 23
Finished Oct 29 02:08:43 PM PDT 23
Peak memory 205832 kb
Host smart-4a32645c-2fca-4d6c-8529-8bcde751a28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40424815475841654394383066807137914630198223627646404081143093648428364635488 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 76.edn_genbits.40424815475841654394383066807137914630198223627646404081143093648428364635488
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.46478211369543806655675763930981847784951536596548824718350626385484169881831
Short name T823
Test name
Test status
Simulation time 24963823 ps
CPU time 1.12 seconds
Started Oct 29 02:08:37 PM PDT 23
Finished Oct 29 02:08:38 PM PDT 23
Peak memory 230560 kb
Host smart-21af0449-f043-4943-a217-1181b3fb87b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46478211369543806655675763930981847784951536596548824718350626385484169881831 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77
.edn_err.46478211369543806655675763930981847784951536596548824718350626385484169881831
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.105260325438719154825505669782292929885798477360791436405342409749451574257734
Short name T933
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Oct 29 02:09:22 PM PDT 23
Finished Oct 29 02:09:23 PM PDT 23
Peak memory 205860 kb
Host smart-2cd4479b-f916-49f7-876e-b9c9815f36a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105260325438719154825505669782292929885798477360791436405342409749451574257734 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 77.edn_genbits.105260325438719154825505669782292929885798477360791436405342409749451574257734
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.106615881710752536954055912885732846458214590128701384345736419768018133768463
Short name T36
Test name
Test status
Simulation time 24963823 ps
CPU time 1.14 seconds
Started Oct 29 02:08:32 PM PDT 23
Finished Oct 29 02:08:33 PM PDT 23
Peak memory 230412 kb
Host smart-226e4249-dc94-400e-8ab3-9303e624c26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106615881710752536954055912885732846458214590128701384345736419768018133768463 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
8.edn_err.106615881710752536954055912885732846458214590128701384345736419768018133768463
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.28981252235561933817903802661219180123931685711073882269053979703742647983004
Short name T62
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Oct 29 02:08:40 PM PDT 23
Finished Oct 29 02:08:43 PM PDT 23
Peak memory 205852 kb
Host smart-fde8415a-9134-480c-85cf-a12b34c6544d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28981252235561933817903802661219180123931685711073882269053979703742647983004 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 78.edn_genbits.28981252235561933817903802661219180123931685711073882269053979703742647983004
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.35602459853820582941268587678905234509998577218360969926904003128192087892517
Short name T585
Test name
Test status
Simulation time 24963823 ps
CPU time 1.17 seconds
Started Oct 29 02:09:16 PM PDT 23
Finished Oct 29 02:09:17 PM PDT 23
Peak memory 230412 kb
Host smart-1908ce60-84a3-4bfe-8e1e-e6b7703c91d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35602459853820582941268587678905234509998577218360969926904003128192087892517 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79
.edn_err.35602459853820582941268587678905234509998577218360969926904003128192087892517
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.71438750066691397529578145437528720901099663538844350113318008148293881182544
Short name T315
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:08:08 PM PDT 23
Finished Oct 29 02:08:10 PM PDT 23
Peak memory 205812 kb
Host smart-df564db7-64bd-4204-89d3-16904c4d4da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71438750066691397529578145437528720901099663538844350113318008148293881182544 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 79.edn_genbits.71438750066691397529578145437528720901099663538844350113318008148293881182544
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.88607338999736480894002086613779445669720660872960017250162842179666464052958
Short name T317
Test name
Test status
Simulation time 18259183 ps
CPU time 1.06 seconds
Started Oct 29 02:06:38 PM PDT 23
Finished Oct 29 02:06:39 PM PDT 23
Peak memory 205560 kb
Host smart-67d411e2-91ed-464e-b616-e869dfc27db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88607338999736480894002086613779445669720660872960017250162842179666464052958 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.edn_alert.88607338999736480894002086613779445669720660872960017250162842179666464052958
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.80891101814491530577974049573707329960492642588907313277490768356356939428415
Short name T48
Test name
Test status
Simulation time 28184990 ps
CPU time 0.91 seconds
Started Oct 29 02:06:58 PM PDT 23
Finished Oct 29 02:07:00 PM PDT 23
Peak memory 205428 kb
Host smart-fb3a3d69-ef8f-4244-a390-ab0890957dec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80891101814491530577974049573707329960492642588907313277490768356356939428415 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.edn_alert_test.80891101814491530577974049573707329960492642588907313277490768356356939428415
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.8696018052053498510411375980973560030096926576713223259340989646976217378767
Short name T669
Test name
Test status
Simulation time 12219183 ps
CPU time 0.86 seconds
Started Oct 29 02:06:37 PM PDT 23
Finished Oct 29 02:06:38 PM PDT 23
Peak memory 214916 kb
Host smart-e6eb6d21-c760-45a7-b546-ba5d2c36ae08
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8696018052053498510411375980973560030096926576713223259340989646976217378767 -assert nopostproc
+UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.edn_disable.8696018052053498510411375980973560030096926576713223259340989646976217378767
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.111580246383126162392838993719300045326397408102096531276523761173020748037007
Short name T841
Test name
Test status
Simulation time 17319183 ps
CPU time 0.9 seconds
Started Oct 29 02:06:59 PM PDT 23
Finished Oct 29 02:07:01 PM PDT 23
Peak memory 214936 kb
Host smart-57d971c4-fc04-4c9e-9d16-a4140de0243c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111580246383126162392838993719300045326397408102096531276523761173020748037007 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable_auto_req_mode.1115802463831261623928389937193000453263974081020965312765
23761173020748037007
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.19778442910737132912557369359020389786803826932809950394373766909528455112461
Short name T446
Test name
Test status
Simulation time 24963823 ps
CPU time 1.15 seconds
Started Oct 29 02:06:40 PM PDT 23
Finished Oct 29 02:06:41 PM PDT 23
Peak memory 230424 kb
Host smart-2ae2c2d9-752f-4c2c-8ab5-7dd84e87fe01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19778442910737132912557369359020389786803826932809950394373766909528455112461 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
edn_err.19778442910737132912557369359020389786803826932809950394373766909528455112461
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.9144720493757361630863902685281533246177007525714819800922440428596679305286
Short name T494
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Oct 29 02:06:36 PM PDT 23
Finished Oct 29 02:06:38 PM PDT 23
Peak memory 205668 kb
Host smart-42c7720d-e98f-4d6c-90c5-54ee97f5c4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9144720493757361630863902685281533246177007525714819800922440428596679305286 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.edn_genbits.9144720493757361630863902685281533246177007525714819800922440428596679305286
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.71226916214948925633069655667226639393613921265685796014707605729215920377990
Short name T533
Test name
Test status
Simulation time 18439183 ps
CPU time 1.11 seconds
Started Oct 29 02:07:27 PM PDT 23
Finished Oct 29 02:07:29 PM PDT 23
Peak memory 222280 kb
Host smart-f5ab3e87-07e4-4186-988d-b7327b1cef0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71226916214948925633069655667226639393613921265685796014707605729215920377990 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.edn_intr.71226916214948925633069655667226639393613921265685796014707605729215920377990
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.78660368638928989075734766941378826344310489615540428941286073366754535562946
Short name T410
Test name
Test status
Simulation time 11759183 ps
CPU time 0.83 seconds
Started Oct 29 02:06:58 PM PDT 23
Finished Oct 29 02:07:00 PM PDT 23
Peak memory 205348 kb
Host smart-19ad42af-87c9-4103-826b-78b92d7255f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78660368638928989075734766941378826344310489615540428941286073366754535562946 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.edn_regwen.78660368638928989075734766941378826344310489615540428941286073366754535562946
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.89339188079705642545557215023580191471680956697127412996663574435739384978186
Short name T312
Test name
Test status
Simulation time 13059183 ps
CPU time 0.88 seconds
Started Oct 29 02:07:03 PM PDT 23
Finished Oct 29 02:07:05 PM PDT 23
Peak memory 205344 kb
Host smart-3ba3395a-0d3d-455e-8c4a-57ce3e9795d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89339188079705642545557215023580191471680956697127412996663574435739384978186 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.edn_smoke.89339188079705642545557215023580191471680956697127412996663574435739384978186
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.49380227264781292298308209846672624610875469669428973884167085919082008097553
Short name T895
Test name
Test status
Simulation time 154489183 ps
CPU time 3.96 seconds
Started Oct 29 02:07:00 PM PDT 23
Finished Oct 29 02:07:04 PM PDT 23
Peak memory 206344 kb
Host smart-7ee1588b-4344-4945-af86-c2e0b783bf25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49380227264781292298308209846672624610875469669428973884167085919082008097553 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.49380227264781292298308209846672624610875469669428973884167085919082008097553
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.44615006133399496818647837671407279796064767427650743190973225162593257353264
Short name T719
Test name
Test status
Simulation time 41708099183 ps
CPU time 1089.48 seconds
Started Oct 29 02:06:40 PM PDT 23
Finished Oct 29 02:24:50 PM PDT 23
Peak memory 215856 kb
Host smart-82bed46c-1e88-4d89-8cf5-e0f5c30fc33e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446150061333994968186478376
71407279796064767427650743190973225162593257353264 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.446150061333
99496818647837671407279796064767427650743190973225162593257353264
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.30951212622299467275497609515070667230005980201452304391337234867874177746051
Short name T858
Test name
Test status
Simulation time 24963823 ps
CPU time 1.16 seconds
Started Oct 29 02:08:39 PM PDT 23
Finished Oct 29 02:08:43 PM PDT 23
Peak memory 229940 kb
Host smart-9680b5ce-5225-4a2c-8f73-fc9ccc0142a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30951212622299467275497609515070667230005980201452304391337234867874177746051 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80
.edn_err.30951212622299467275497609515070667230005980201452304391337234867874177746051
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.80900157711642284983197112050128571669517160276936998844171137456695050026891
Short name T267
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Oct 29 02:08:35 PM PDT 23
Finished Oct 29 02:08:36 PM PDT 23
Peak memory 205852 kb
Host smart-d2efd18e-476d-4476-9aae-9b60e29d91f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80900157711642284983197112050128571669517160276936998844171137456695050026891 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 80.edn_genbits.80900157711642284983197112050128571669517160276936998844171137456695050026891
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.61619913610349154181099262976948936548267928218922185342251089193261165584137
Short name T91
Test name
Test status
Simulation time 24963823 ps
CPU time 1.16 seconds
Started Oct 29 02:08:33 PM PDT 23
Finished Oct 29 02:08:35 PM PDT 23
Peak memory 230492 kb
Host smart-4931e14f-7e3e-42c1-9d46-ebf6c2203a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61619913610349154181099262976948936548267928218922185342251089193261165584137 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81
.edn_err.61619913610349154181099262976948936548267928218922185342251089193261165584137
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.104951719824970582860065585912769434295055638775344905428100267975431998527225
Short name T354
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Oct 29 02:08:41 PM PDT 23
Finished Oct 29 02:08:43 PM PDT 23
Peak memory 205856 kb
Host smart-416ae0b8-a35c-4936-bf8a-0c43dd2b05fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104951719824970582860065585912769434295055638775344905428100267975431998527225 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 81.edn_genbits.104951719824970582860065585912769434295055638775344905428100267975431998527225
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.42453620905498894619329204289559227211133258453478625049763316738615955898890
Short name T889
Test name
Test status
Simulation time 24963823 ps
CPU time 1.14 seconds
Started Oct 29 02:08:08 PM PDT 23
Finished Oct 29 02:08:10 PM PDT 23
Peak memory 230436 kb
Host smart-cbb970bf-6458-45b3-8f83-5e53e9f8b9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42453620905498894619329204289559227211133258453478625049763316738615955898890 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82
.edn_err.42453620905498894619329204289559227211133258453478625049763316738615955898890
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.91529177309050090616081817240278829526062657469867788796061433867630854507175
Short name T848
Test name
Test status
Simulation time 17999183 ps
CPU time 1.18 seconds
Started Oct 29 02:09:47 PM PDT 23
Finished Oct 29 02:09:48 PM PDT 23
Peak memory 205816 kb
Host smart-512c1352-931b-4a72-9af1-f940d27cdb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91529177309050090616081817240278829526062657469867788796061433867630854507175 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 82.edn_genbits.91529177309050090616081817240278829526062657469867788796061433867630854507175
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.1262358540692966747977031178104140410033870517669915412395636504697163883124
Short name T308
Test name
Test status
Simulation time 24963823 ps
CPU time 1.15 seconds
Started Oct 29 02:08:39 PM PDT 23
Finished Oct 29 02:08:43 PM PDT 23
Peak memory 230416 kb
Host smart-b85baa91-2729-45b3-b2bd-6f7db0ed349d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262358540692966747977031178104140410033870517669915412395636504697163883124 -assert nopostproc +UVM_TESTNAME=edn_err_te
st +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.
edn_err.1262358540692966747977031178104140410033870517669915412395636504697163883124
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.30679135565369649279093847349553191700473489403836740736877831071219216176529
Short name T255
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Oct 29 02:08:46 PM PDT 23
Finished Oct 29 02:08:48 PM PDT 23
Peak memory 205848 kb
Host smart-61a4bc47-ddb8-45d1-8ddf-4d2b4e3400e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30679135565369649279093847349553191700473489403836740736877831071219216176529 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 83.edn_genbits.30679135565369649279093847349553191700473489403836740736877831071219216176529
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.67151648608615864016319042652262299260576104743635779345847388211079584198301
Short name T58
Test name
Test status
Simulation time 24963823 ps
CPU time 1.13 seconds
Started Oct 29 02:08:10 PM PDT 23
Finished Oct 29 02:08:12 PM PDT 23
Peak memory 230420 kb
Host smart-e89a5467-016d-42d9-a9c5-61099216281f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67151648608615864016319042652262299260576104743635779345847388211079584198301 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84
.edn_err.67151648608615864016319042652262299260576104743635779345847388211079584198301
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.103761948191480406209587690174437958847443990690858171096601576165498930196838
Short name T718
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Oct 29 02:08:34 PM PDT 23
Finished Oct 29 02:08:35 PM PDT 23
Peak memory 205836 kb
Host smart-cc0153ff-3ffd-4b4c-95ab-a4b281656718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103761948191480406209587690174437958847443990690858171096601576165498930196838 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 84.edn_genbits.103761948191480406209587690174437958847443990690858171096601576165498930196838
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.108020167432172900605028677165876928596138563222157373711391461076971879758212
Short name T916
Test name
Test status
Simulation time 24963823 ps
CPU time 1.2 seconds
Started Oct 29 02:08:32 PM PDT 23
Finished Oct 29 02:08:33 PM PDT 23
Peak memory 230424 kb
Host smart-5ac881f1-c6fd-4a0f-bdc6-3c543f6277ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108020167432172900605028677165876928596138563222157373711391461076971879758212 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
5.edn_err.108020167432172900605028677165876928596138563222157373711391461076971879758212
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.82378761048727992450548058013068318149528220671484082149582242910337631634634
Short name T799
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Oct 29 02:09:48 PM PDT 23
Finished Oct 29 02:09:50 PM PDT 23
Peak memory 205768 kb
Host smart-fe293a4c-51e6-4c76-89a7-1e0485cb00f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82378761048727992450548058013068318149528220671484082149582242910337631634634 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 85.edn_genbits.82378761048727992450548058013068318149528220671484082149582242910337631634634
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.102607148397326604990861158304204002715576164880678070034463701850811682452090
Short name T674
Test name
Test status
Simulation time 24963823 ps
CPU time 1.17 seconds
Started Oct 29 02:08:12 PM PDT 23
Finished Oct 29 02:08:14 PM PDT 23
Peak memory 230412 kb
Host smart-30606cb3-5955-4f8d-9095-197a5740e339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102607148397326604990861158304204002715576164880678070034463701850811682452090 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
6.edn_err.102607148397326604990861158304204002715576164880678070034463701850811682452090
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.110616616353265970395675035538786221806211371815992498110681537090342642639240
Short name T874
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Oct 29 02:08:43 PM PDT 23
Finished Oct 29 02:08:45 PM PDT 23
Peak memory 205848 kb
Host smart-529be4fa-5d1f-4465-b28d-2a3603ae153b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110616616353265970395675035538786221806211371815992498110681537090342642639240 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 86.edn_genbits.110616616353265970395675035538786221806211371815992498110681537090342642639240
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.24333189428913021781912456279799149378514833391198436193085283741976228544416
Short name T765
Test name
Test status
Simulation time 24963823 ps
CPU time 1.19 seconds
Started Oct 29 02:08:34 PM PDT 23
Finished Oct 29 02:08:36 PM PDT 23
Peak memory 230392 kb
Host smart-8a103497-65b8-4861-93fb-9f85e95299cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24333189428913021781912456279799149378514833391198436193085283741976228544416 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87
.edn_err.24333189428913021781912456279799149378514833391198436193085283741976228544416
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.45778796508442796288712633066325549009960100637594708968193839917522072256544
Short name T808
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Oct 29 02:08:35 PM PDT 23
Finished Oct 29 02:08:37 PM PDT 23
Peak memory 205760 kb
Host smart-188cfa06-5a3a-4165-9b7f-5ce54bd77fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45778796508442796288712633066325549009960100637594708968193839917522072256544 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 87.edn_genbits.45778796508442796288712633066325549009960100637594708968193839917522072256544
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.40660282311234568886294504524163250039150637698719138379226940584746868942494
Short name T976
Test name
Test status
Simulation time 24963823 ps
CPU time 1.12 seconds
Started Oct 29 02:08:42 PM PDT 23
Finished Oct 29 02:08:44 PM PDT 23
Peak memory 230460 kb
Host smart-009eced2-9e06-4e31-9a04-c022804c512c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40660282311234568886294504524163250039150637698719138379226940584746868942494 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88
.edn_err.40660282311234568886294504524163250039150637698719138379226940584746868942494
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.57053717956756016039771256569438987667158237752245518819293500502047136022228
Short name T333
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Oct 29 02:08:37 PM PDT 23
Finished Oct 29 02:08:38 PM PDT 23
Peak memory 205772 kb
Host smart-380c418e-0a31-45d3-8ba6-05ff88c58966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57053717956756016039771256569438987667158237752245518819293500502047136022228 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 88.edn_genbits.57053717956756016039771256569438987667158237752245518819293500502047136022228
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.113007834229473560692879063536837413857640876241238399547842813845125230525810
Short name T545
Test name
Test status
Simulation time 24963823 ps
CPU time 1.14 seconds
Started Oct 29 02:08:11 PM PDT 23
Finished Oct 29 02:08:12 PM PDT 23
Peak memory 230456 kb
Host smart-03c8d5a4-db91-4fe5-8f23-8198a9331cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113007834229473560692879063536837413857640876241238399547842813845125230525810 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
9.edn_err.113007834229473560692879063536837413857640876241238399547842813845125230525810
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.107263260931718061986246626653938766671392554541062751858000137741895858737228
Short name T643
Test name
Test status
Simulation time 17999183 ps
CPU time 1.16 seconds
Started Oct 29 02:08:48 PM PDT 23
Finished Oct 29 02:08:50 PM PDT 23
Peak memory 205848 kb
Host smart-68a37236-d948-46c2-bd08-fc54fb7dd73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107263260931718061986246626653938766671392554541062751858000137741895858737228 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 89.edn_genbits.107263260931718061986246626653938766671392554541062751858000137741895858737228
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.89659989712539719914416543650160828611217421649554864853555125909629723620623
Short name T840
Test name
Test status
Simulation time 18259183 ps
CPU time 0.98 seconds
Started Oct 29 02:07:27 PM PDT 23
Finished Oct 29 02:07:29 PM PDT 23
Peak memory 205536 kb
Host smart-bf69ac04-b6cd-45d3-b87b-05f9fe620097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89659989712539719914416543650160828611217421649554864853555125909629723620623 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.edn_alert.89659989712539719914416543650160828611217421649554864853555125909629723620623
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.14127481907964023589860588590514231331476437605221739161313802713778986704434
Short name T375
Test name
Test status
Simulation time 28184990 ps
CPU time 0.86 seconds
Started Oct 29 02:07:23 PM PDT 23
Finished Oct 29 02:07:25 PM PDT 23
Peak memory 205456 kb
Host smart-91977c03-573f-4d6b-86f8-20edbbab6a34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14127481907964023589860588590514231331476437605221739161313802713778986704434 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.edn_alert_test.14127481907964023589860588590514231331476437605221739161313802713778986704434
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.48821332233633368287814462922507263059588897653845845499304620054763982428393
Short name T26
Test name
Test status
Simulation time 12219183 ps
CPU time 0.84 seconds
Started Oct 29 02:07:03 PM PDT 23
Finished Oct 29 02:07:05 PM PDT 23
Peak memory 214884 kb
Host smart-169f3a50-e29d-44be-b5e0-96c125e2bf65
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48821332233633368287814462922507263059588897653845845499304620054763982428393 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.edn_disable.48821332233633368287814462922507263059588897653845845499304620054763982428393
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.39585735675659411575731480025070703030179056679280944569991252662952809397165
Short name T693
Test name
Test status
Simulation time 17319183 ps
CPU time 0.9 seconds
Started Oct 29 02:06:39 PM PDT 23
Finished Oct 29 02:06:40 PM PDT 23
Peak memory 214928 kb
Host smart-d8f3e8f7-6a82-44e8-a762-f9da2a9009c2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39585735675659411575731480025070703030179056679280944569991252662952809397165 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable_auto_req_mode.39585735675659411575731480025070703030179056679280944569991
252662952809397165
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.19595423188032299210471816055854543657301471583350198153565572882381315502508
Short name T904
Test name
Test status
Simulation time 24963823 ps
CPU time 1.18 seconds
Started Oct 29 02:07:03 PM PDT 23
Finished Oct 29 02:07:06 PM PDT 23
Peak memory 230364 kb
Host smart-a109d6d8-729c-40de-8ea2-2cb86699a6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19595423188032299210471816055854543657301471583350198153565572882381315502508 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
edn_err.19595423188032299210471816055854543657301471583350198153565572882381315502508
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.30783373966538582565657134963997164161428070036862255733279787743991486263017
Short name T678
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Oct 29 02:06:56 PM PDT 23
Finished Oct 29 02:06:57 PM PDT 23
Peak memory 205936 kb
Host smart-430015c7-a3a8-4741-b7c3-b8a8ea22c60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30783373966538582565657134963997164161428070036862255733279787743991486263017 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.edn_genbits.30783373966538582565657134963997164161428070036862255733279787743991486263017
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.77406246399418085598395720981134342858905609246061709943407451102020687736412
Short name T313
Test name
Test status
Simulation time 18439183 ps
CPU time 1.12 seconds
Started Oct 29 02:07:24 PM PDT 23
Finished Oct 29 02:07:26 PM PDT 23
Peak memory 222336 kb
Host smart-dede3414-0fb1-42ff-b9d1-ddd120bdaf12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77406246399418085598395720981134342858905609246061709943407451102020687736412 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.edn_intr.77406246399418085598395720981134342858905609246061709943407451102020687736412
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.81204568484121454394958752098710670885807416425253242758503751742779635698844
Short name T467
Test name
Test status
Simulation time 11759183 ps
CPU time 0.82 seconds
Started Oct 29 02:06:53 PM PDT 23
Finished Oct 29 02:06:54 PM PDT 23
Peak memory 205228 kb
Host smart-f73e60c5-c67b-4ec6-93dd-83740e1d818d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81204568484121454394958752098710670885807416425253242758503751742779635698844 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.edn_regwen.81204568484121454394958752098710670885807416425253242758503751742779635698844
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.101106869050982011603781494929082279869449689054667774290597596791058946225208
Short name T714
Test name
Test status
Simulation time 13059183 ps
CPU time 0.89 seconds
Started Oct 29 02:07:20 PM PDT 23
Finished Oct 29 02:07:22 PM PDT 23
Peak memory 205280 kb
Host smart-a75a513f-8ca8-4ca6-b4ec-032334bc0090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101106869050982011603781494929082279869449689054667774290597596791058946225208 -assert nopostproc +UVM_TESTNAME=edn_smok
e_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.edn_smoke.101106869050982011603781494929082279869449689054667774290597596791058946225208
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.9649263234379547468993739819392820957433781582347307965197981877195398145328
Short name T802
Test name
Test status
Simulation time 154489183 ps
CPU time 3.81 seconds
Started Oct 29 02:06:54 PM PDT 23
Finished Oct 29 02:06:58 PM PDT 23
Peak memory 206400 kb
Host smart-c4359731-4e2a-43be-b67a-a470e787950b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9649263234379547468993739819392820957433781582347307965197981877195398145328 -assert nopost
proc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.9649263234379547468993739819392820957433781582347307965197981877195398145328
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.53331610110889733042440557473856530951761434639227473059521290885860800429056
Short name T34
Test name
Test status
Simulation time 41708099183 ps
CPU time 1109.2 seconds
Started Oct 29 02:06:55 PM PDT 23
Finished Oct 29 02:25:24 PM PDT 23
Peak memory 215792 kb
Host smart-a949cd30-a085-46e6-91b5-e0396665e5e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533316101108897330424405574
73856530951761434639227473059521290885860800429056 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.533316101108
89733042440557473856530951761434639227473059521290885860800429056
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.46946834681799938724477137498281585725036041554296683848968033113210922050751
Short name T605
Test name
Test status
Simulation time 24963823 ps
CPU time 1.13 seconds
Started Oct 29 02:08:42 PM PDT 23
Finished Oct 29 02:08:44 PM PDT 23
Peak memory 230528 kb
Host smart-08cd9faf-72c4-4b16-a0f4-715117e39ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46946834681799938724477137498281585725036041554296683848968033113210922050751 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90
.edn_err.46946834681799938724477137498281585725036041554296683848968033113210922050751
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.9538568386380099067086335057396353764554167784540574275935821640506236480025
Short name T235
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Oct 29 02:08:47 PM PDT 23
Finished Oct 29 02:08:49 PM PDT 23
Peak memory 205864 kb
Host smart-a4b4fb5b-df78-49b7-b51b-9d8af1b052ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9538568386380099067086335057396353764554167784540574275935821640506236480025 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 90.edn_genbits.9538568386380099067086335057396353764554167784540574275935821640506236480025
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.16078063999808788511141683591617535501283718768335733558725579787056022420328
Short name T906
Test name
Test status
Simulation time 24963823 ps
CPU time 1.13 seconds
Started Oct 29 02:09:23 PM PDT 23
Finished Oct 29 02:09:24 PM PDT 23
Peak memory 230464 kb
Host smart-0d1ee0d8-4033-4a5a-bfe5-d2704e103a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16078063999808788511141683591617535501283718768335733558725579787056022420328 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91
.edn_err.16078063999808788511141683591617535501283718768335733558725579787056022420328
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.89826260751921194237033508543389360564173807083253703892711798147916116842104
Short name T282
Test name
Test status
Simulation time 17999183 ps
CPU time 1.04 seconds
Started Oct 29 02:08:36 PM PDT 23
Finished Oct 29 02:08:37 PM PDT 23
Peak memory 205672 kb
Host smart-df76269e-fc3f-401d-a901-a78c750372a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89826260751921194237033508543389360564173807083253703892711798147916116842104 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 91.edn_genbits.89826260751921194237033508543389360564173807083253703892711798147916116842104
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.71896826834184093996469938540962772281748418345574448501386935935962724038274
Short name T699
Test name
Test status
Simulation time 24963823 ps
CPU time 1.15 seconds
Started Oct 29 02:08:06 PM PDT 23
Finished Oct 29 02:08:07 PM PDT 23
Peak memory 230416 kb
Host smart-a3d49498-d4be-4682-b497-c98c4ce2efe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71896826834184093996469938540962772281748418345574448501386935935962724038274 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92
.edn_err.71896826834184093996469938540962772281748418345574448501386935935962724038274
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.57696007830882820696390522331022483954609154552014239363648927093734628399808
Short name T825
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Oct 29 02:08:13 PM PDT 23
Finished Oct 29 02:08:15 PM PDT 23
Peak memory 205808 kb
Host smart-bb43f9cf-beac-424b-a07c-0e9f7808ad58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57696007830882820696390522331022483954609154552014239363648927093734628399808 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 92.edn_genbits.57696007830882820696390522331022483954609154552014239363648927093734628399808
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.50934449405959225949666554111766123421544878133971884870198780850575167555769
Short name T970
Test name
Test status
Simulation time 24963823 ps
CPU time 1.15 seconds
Started Oct 29 02:08:36 PM PDT 23
Finished Oct 29 02:08:38 PM PDT 23
Peak memory 230492 kb
Host smart-ad573ecd-f004-44a8-9814-d2f88d559670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50934449405959225949666554111766123421544878133971884870198780850575167555769 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93
.edn_err.50934449405959225949666554111766123421544878133971884870198780850575167555769
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.6538478991679999359607001281326048410602619407394537783109401951084320594351
Short name T247
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Oct 29 02:08:07 PM PDT 23
Finished Oct 29 02:08:09 PM PDT 23
Peak memory 205824 kb
Host smart-eeeb14a9-1ef7-4b17-b624-7addd083719b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6538478991679999359607001281326048410602619407394537783109401951084320594351 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 93.edn_genbits.6538478991679999359607001281326048410602619407394537783109401951084320594351
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.69486636438784738775137425204389430569682723289184831910853664471957309884544
Short name T746
Test name
Test status
Simulation time 24963823 ps
CPU time 1.15 seconds
Started Oct 29 02:09:47 PM PDT 23
Finished Oct 29 02:09:48 PM PDT 23
Peak memory 230412 kb
Host smart-a8367cf1-4bca-40b7-a26a-8ea25e41dc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69486636438784738775137425204389430569682723289184831910853664471957309884544 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94
.edn_err.69486636438784738775137425204389430569682723289184831910853664471957309884544
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.80468247363911676040993863636364121988596206237547957937246868337364972575285
Short name T14
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Oct 29 02:09:48 PM PDT 23
Finished Oct 29 02:09:50 PM PDT 23
Peak memory 205824 kb
Host smart-e62e2952-b7a9-4336-baab-a6828cb78229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80468247363911676040993863636364121988596206237547957937246868337364972575285 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 94.edn_genbits.80468247363911676040993863636364121988596206237547957937246868337364972575285
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.90428095380683698633129543907206494954967419726300882291086567990462237970421
Short name T359
Test name
Test status
Simulation time 24963823 ps
CPU time 1.14 seconds
Started Oct 29 02:08:40 PM PDT 23
Finished Oct 29 02:08:43 PM PDT 23
Peak memory 230356 kb
Host smart-1dcffce9-3741-4551-b7cc-8db23e1ef26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90428095380683698633129543907206494954967419726300882291086567990462237970421 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95
.edn_err.90428095380683698633129543907206494954967419726300882291086567990462237970421
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.107995158647689185811087343498533051991934842837035470863996734213612312888943
Short name T831
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Oct 29 02:09:47 PM PDT 23
Finished Oct 29 02:09:48 PM PDT 23
Peak memory 205828 kb
Host smart-74e00f40-10b0-4107-b573-e1cf62fb8875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107995158647689185811087343498533051991934842837035470863996734213612312888943 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 95.edn_genbits.107995158647689185811087343498533051991934842837035470863996734213612312888943
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.60039862573514039578401714641969179163882867118674109503556096349767914607101
Short name T259
Test name
Test status
Simulation time 24963823 ps
CPU time 1.17 seconds
Started Oct 29 02:08:43 PM PDT 23
Finished Oct 29 02:08:45 PM PDT 23
Peak memory 230368 kb
Host smart-a3d901a1-29c7-4f77-adcb-955f01273ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60039862573514039578401714641969179163882867118674109503556096349767914607101 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96
.edn_err.60039862573514039578401714641969179163882867118674109503556096349767914607101
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.15472016321470783523501560498611268292871748628392381065113635033315396498046
Short name T74
Test name
Test status
Simulation time 17999183 ps
CPU time 1.06 seconds
Started Oct 29 02:08:49 PM PDT 23
Finished Oct 29 02:08:51 PM PDT 23
Peak memory 205844 kb
Host smart-916671e3-727d-4f64-b0af-071ff28a137b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15472016321470783523501560498611268292871748628392381065113635033315396498046 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 96.edn_genbits.15472016321470783523501560498611268292871748628392381065113635033315396498046
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.82340445071381812915622531249450389907973716934480697543996161492726549549649
Short name T711
Test name
Test status
Simulation time 24963823 ps
CPU time 1.12 seconds
Started Oct 29 02:08:44 PM PDT 23
Finished Oct 29 02:08:47 PM PDT 23
Peak memory 230560 kb
Host smart-d4e18816-1c2c-4935-9a4f-3d6e75d297db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82340445071381812915622531249450389907973716934480697543996161492726549549649 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97
.edn_err.82340445071381812915622531249450389907973716934480697543996161492726549549649
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.19867365382414153235490997356260817372342714660668093766674809436495221922130
Short name T926
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Oct 29 02:08:34 PM PDT 23
Finished Oct 29 02:08:36 PM PDT 23
Peak memory 205760 kb
Host smart-0eae7159-3474-4dba-8b05-88f20f560c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19867365382414153235490997356260817372342714660668093766674809436495221922130 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 97.edn_genbits.19867365382414153235490997356260817372342714660668093766674809436495221922130
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.61853439745099705337128166397523915704628666781398990624252768839136820127182
Short name T880
Test name
Test status
Simulation time 24963823 ps
CPU time 1.13 seconds
Started Oct 29 02:09:47 PM PDT 23
Finished Oct 29 02:09:48 PM PDT 23
Peak memory 230448 kb
Host smart-4cbff714-2225-4c48-a19c-513a917d701c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61853439745099705337128166397523915704628666781398990624252768839136820127182 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98
.edn_err.61853439745099705337128166397523915704628666781398990624252768839136820127182
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.59530141526377800807194474878268055853398742550536782580689399316360891996440
Short name T246
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Oct 29 02:08:42 PM PDT 23
Finished Oct 29 02:08:44 PM PDT 23
Peak memory 205912 kb
Host smart-b1d1f10c-4275-47e4-b6bb-2a6fdc0a6ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59530141526377800807194474878268055853398742550536782580689399316360891996440 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 98.edn_genbits.59530141526377800807194474878268055853398742550536782580689399316360891996440
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.111343250668671399912770555066677076369603792156825703163253679067709647713624
Short name T299
Test name
Test status
Simulation time 24963823 ps
CPU time 1.12 seconds
Started Oct 29 02:09:02 PM PDT 23
Finished Oct 29 02:09:04 PM PDT 23
Peak memory 230448 kb
Host smart-a31b4907-092f-416c-bde4-7143e13c4802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111343250668671399912770555066677076369603792156825703163253679067709647713624 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
9.edn_err.111343250668671399912770555066677076369603792156825703163253679067709647713624
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.4050070278136146434171929595321021897311498599010492827028604986945439293693
Short name T395
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Oct 29 02:09:06 PM PDT 23
Finished Oct 29 02:09:08 PM PDT 23
Peak memory 205868 kb
Host smart-8b74101c-9952-48b6-926f-389849058cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050070278136146434171929595321021897311498599010492827028604986945439293693 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 99.edn_genbits.4050070278136146434171929595321021897311498599010492827028604986945439293693
Directory /workspace/99.edn_genbits/latest
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