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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.16 98.64 88.52 94.40 59.21 96.62 96.83 82.93


Total test records in report: 980
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T753 /workspace/coverage/default/21.edn_alert_test.57165059605681410588152921570602991923030556128571440363197619017507106906797 Nov 01 02:26:54 PM PDT 23 Nov 01 02:27:01 PM PDT 23 28184990 ps
T754 /workspace/coverage/default/40.edn_stress_all_with_rand_reset.47796121585121968155513776418657155948549415568941993064228454395113226448683 Nov 01 02:26:54 PM PDT 23 Nov 01 02:45:22 PM PDT 23 41708099183 ps
T755 /workspace/coverage/default/48.edn_smoke.106551503353443562646957374216167464625558688073185999202023106449609254294253 Nov 01 02:27:29 PM PDT 23 Nov 01 02:27:43 PM PDT 23 13059183 ps
T756 /workspace/coverage/default/263.edn_genbits.23425721563031117426935407002269655932264944594980560219118300250019465515706 Nov 01 02:27:54 PM PDT 23 Nov 01 02:27:59 PM PDT 23 17999183 ps
T757 /workspace/coverage/default/94.edn_genbits.85713951869358113281655035366629494010169883066043093629716178985095844874240 Nov 01 02:27:19 PM PDT 23 Nov 01 02:27:35 PM PDT 23 17999183 ps
T758 /workspace/coverage/default/41.edn_intr.107406514643281874904286773956231569890313283999712413023509560342716448297237 Nov 01 02:26:56 PM PDT 23 Nov 01 02:27:06 PM PDT 23 18439183 ps
T759 /workspace/coverage/default/11.edn_disable.49025720475895124278075817779820946703256303575000337708855309289051574220173 Nov 01 02:27:21 PM PDT 23 Nov 01 02:27:36 PM PDT 23 12219183 ps
T760 /workspace/coverage/default/148.edn_genbits.19671320156869097202461782223915706632434969015376978867179675644854077783481 Nov 01 02:27:04 PM PDT 23 Nov 01 02:27:19 PM PDT 23 17999183 ps
T761 /workspace/coverage/default/29.edn_disable_auto_req_mode.16636395020448292318560505407864839237619327084895459161334490151049321578041 Nov 01 02:27:21 PM PDT 23 Nov 01 02:27:36 PM PDT 23 17319183 ps
T762 /workspace/coverage/default/7.edn_smoke.11548393898355521940952601558353252297436324045092980647690072189787573521919 Nov 01 02:26:51 PM PDT 23 Nov 01 02:26:54 PM PDT 23 13059183 ps
T763 /workspace/coverage/default/38.edn_disable_auto_req_mode.108724320950430673309005415482156275025428748105996142443639279205970246062069 Nov 01 02:26:59 PM PDT 23 Nov 01 02:27:12 PM PDT 23 17319183 ps
T764 /workspace/coverage/default/10.edn_stress_all.34998714917236968790857478336822980795730192212004279691573985585407585268024 Nov 01 02:26:51 PM PDT 23 Nov 01 02:26:58 PM PDT 23 154489183 ps
T765 /workspace/coverage/default/31.edn_alert.87743540335778846640722512417045104817615430253103544435603063893277228714221 Nov 01 02:26:53 PM PDT 23 Nov 01 02:27:00 PM PDT 23 18259183 ps
T766 /workspace/coverage/default/178.edn_genbits.36629014066099071134449097723032015833916735324133979939657398472637142744732 Nov 01 02:27:23 PM PDT 23 Nov 01 02:27:38 PM PDT 23 17999183 ps
T767 /workspace/coverage/default/8.edn_regwen.93276703315387219590455207048496393728702846054756903369373362527960838061554 Nov 01 02:26:36 PM PDT 23 Nov 01 02:26:38 PM PDT 23 11759183 ps
T768 /workspace/coverage/default/5.edn_alert.96740253276857160725483241283284736664065392710466724029320547156240154874135 Nov 01 02:26:39 PM PDT 23 Nov 01 02:26:44 PM PDT 23 18259183 ps
T769 /workspace/coverage/default/195.edn_genbits.43749803027829883382110202760948976990202824434345490966211661938910121424308 Nov 01 02:27:46 PM PDT 23 Nov 01 02:27:54 PM PDT 23 17999183 ps
T770 /workspace/coverage/default/8.edn_genbits.109086130369089630901049396895583093231561907354547802618756258087989745938600 Nov 01 02:25:51 PM PDT 23 Nov 01 02:25:58 PM PDT 23 17999183 ps
T771 /workspace/coverage/default/218.edn_genbits.49813908086810275263535273775446408571920022894227038178421862820125183947189 Nov 01 02:27:54 PM PDT 23 Nov 01 02:27:59 PM PDT 23 17999183 ps
T772 /workspace/coverage/default/159.edn_genbits.59543595972271198041835025300092729127519315620899958411687537221702376922735 Nov 01 02:26:56 PM PDT 23 Nov 01 02:27:05 PM PDT 23 17999183 ps
T773 /workspace/coverage/default/214.edn_genbits.61076746683866914551847889203218934868122604550046205179248539164039167948175 Nov 01 02:27:49 PM PDT 23 Nov 01 02:27:54 PM PDT 23 17999183 ps
T774 /workspace/coverage/default/18.edn_stress_all.42129488052058404237554319384799242151558050558240807932823342097679219970443 Nov 01 02:27:19 PM PDT 23 Nov 01 02:27:37 PM PDT 23 154489183 ps
T775 /workspace/coverage/default/77.edn_genbits.12592648950751677015176521465960231827263856415015803151539634616728334380089 Nov 01 02:27:05 PM PDT 23 Nov 01 02:27:22 PM PDT 23 17999183 ps
T776 /workspace/coverage/default/21.edn_err.95353607247031633698132067434471778266733144573786908274535608900117023585596 Nov 01 02:26:47 PM PDT 23 Nov 01 02:26:51 PM PDT 23 24963823 ps
T777 /workspace/coverage/default/95.edn_genbits.19017861997837641814333398113237144608758988730621182634498330616973582530820 Nov 01 02:26:57 PM PDT 23 Nov 01 02:27:09 PM PDT 23 17999183 ps
T778 /workspace/coverage/default/39.edn_stress_all_with_rand_reset.89205873384181872768877319875814153135936016332292491373418443497434845464560 Nov 01 02:27:09 PM PDT 23 Nov 01 02:45:30 PM PDT 23 41708099183 ps
T779 /workspace/coverage/default/34.edn_intr.59864123858828059008250924173405331718586304755572568685392908456725869973664 Nov 01 02:27:13 PM PDT 23 Nov 01 02:27:30 PM PDT 23 18439183 ps
T780 /workspace/coverage/default/18.edn_stress_all_with_rand_reset.112267551909639323557334603908702762332855087643313156837557331726160027531299 Nov 01 02:27:10 PM PDT 23 Nov 01 02:45:40 PM PDT 23 41708099183 ps
T781 /workspace/coverage/default/6.edn_stress_all_with_rand_reset.11863397896650457722085137086544439853684898646957706075159357648743028435275 Nov 01 02:26:39 PM PDT 23 Nov 01 02:45:02 PM PDT 23 41708099183 ps
T782 /workspace/coverage/default/197.edn_genbits.69547926877831067687496029480250545551545521295260614347539837764146323645660 Nov 01 02:27:27 PM PDT 23 Nov 01 02:27:43 PM PDT 23 17999183 ps
T783 /workspace/coverage/default/47.edn_intr.43167908516032462454017840044167115515780817830283683035006433597104644236700 Nov 01 02:27:32 PM PDT 23 Nov 01 02:27:46 PM PDT 23 18439183 ps
T784 /workspace/coverage/default/41.edn_stress_all_with_rand_reset.53948634442236273175804374333233892271836531921509414210806160604617817199439 Nov 01 02:27:04 PM PDT 23 Nov 01 02:45:34 PM PDT 23 41708099183 ps
T785 /workspace/coverage/default/47.edn_err.42657451542590105200020526112428481813734965779000962819846252490684569486341 Nov 01 02:27:23 PM PDT 23 Nov 01 02:27:37 PM PDT 23 24963823 ps
T786 /workspace/coverage/default/7.edn_disable_auto_req_mode.78169797045592047605798364729325400313325497420246061623006041933588337756764 Nov 01 02:26:50 PM PDT 23 Nov 01 02:26:53 PM PDT 23 17319183 ps
T787 /workspace/coverage/default/150.edn_genbits.14142286740532515607187558863759624170532896571738939459085616168090557706778 Nov 01 02:27:05 PM PDT 23 Nov 01 02:27:21 PM PDT 23 17999183 ps
T788 /workspace/coverage/default/36.edn_alert.83246060344809741220834573644202307758367041407068143021321453495227749140025 Nov 01 02:27:24 PM PDT 23 Nov 01 02:27:39 PM PDT 23 18259183 ps
T789 /workspace/coverage/default/140.edn_genbits.845517080180392498429471419591092092861339132748592889712965742077574183187 Nov 01 02:27:00 PM PDT 23 Nov 01 02:27:15 PM PDT 23 17999183 ps
T790 /workspace/coverage/default/60.edn_genbits.24693744157788920174159730191378847931810022623216771797028015183309877140853 Nov 01 02:27:18 PM PDT 23 Nov 01 02:27:33 PM PDT 23 17999183 ps
T791 /workspace/coverage/default/42.edn_disable.82027011282143453637895202699295111312810197435540201961490951780061016513015 Nov 01 03:00:52 PM PDT 23 Nov 01 03:00:54 PM PDT 23 12219183 ps
T792 /workspace/coverage/default/69.edn_genbits.66560289355729695779674127560742218966597547529425784555041957206846691945287 Nov 01 02:26:56 PM PDT 23 Nov 01 02:27:06 PM PDT 23 17999183 ps
T793 /workspace/coverage/default/85.edn_genbits.7865836963315865278086950974370562449046497483855608474048052069609674942280 Nov 01 02:27:26 PM PDT 23 Nov 01 02:27:40 PM PDT 23 17999183 ps
T794 /workspace/coverage/default/119.edn_genbits.83971633563196869719860325607305648598998896451139882288943503418563241265967 Nov 01 02:27:54 PM PDT 23 Nov 01 02:27:59 PM PDT 23 17999183 ps
T795 /workspace/coverage/default/29.edn_stress_all_with_rand_reset.16062446855679961773282281459106796961950594198830464961213130254522294264160 Nov 01 02:26:57 PM PDT 23 Nov 01 02:44:59 PM PDT 23 41708099183 ps
T796 /workspace/coverage/default/17.edn_alert.68272354415859218535571298608946545232763594045208555406645583567051948011560 Nov 01 02:26:59 PM PDT 23 Nov 01 02:27:12 PM PDT 23 18259183 ps
T797 /workspace/coverage/default/13.edn_intr.7108747768904666117686582462251356990606579123713881196470671209138527613715 Nov 01 02:26:36 PM PDT 23 Nov 01 02:26:39 PM PDT 23 18439183 ps
T798 /workspace/coverage/default/200.edn_genbits.110296964989069193950433401758487068061606484590469712786105930001945658416433 Nov 01 02:27:24 PM PDT 23 Nov 01 02:27:39 PM PDT 23 17999183 ps
T799 /workspace/coverage/default/68.edn_err.12063460349545215115120788990398573835064366958130302622612756285091233119513 Nov 01 02:26:53 PM PDT 23 Nov 01 02:26:59 PM PDT 23 24963823 ps
T800 /workspace/coverage/default/42.edn_genbits.18282135466948066800142742573930866322841434286969056479458782425154442336800 Nov 01 02:26:57 PM PDT 23 Nov 01 02:27:09 PM PDT 23 17999183 ps
T801 /workspace/coverage/default/14.edn_alert.74680233265624256132095767335326124820457888972688137805289719287833678198330 Nov 01 02:26:42 PM PDT 23 Nov 01 02:26:47 PM PDT 23 18259183 ps
T802 /workspace/coverage/default/235.edn_genbits.39225872485503403524451739583370135442478723163194482422709540295921817587632 Nov 01 02:27:56 PM PDT 23 Nov 01 02:28:02 PM PDT 23 17999183 ps
T803 /workspace/coverage/default/49.edn_genbits.40154442958379180883558283151915919539028620034312113036655874308103599048548 Nov 01 02:26:51 PM PDT 23 Nov 01 02:26:55 PM PDT 23 17999183 ps
T804 /workspace/coverage/default/110.edn_genbits.19365752469658204182375031655579809623712867699831469033013743675172035879858 Nov 01 02:27:15 PM PDT 23 Nov 01 02:27:30 PM PDT 23 17999183 ps
T805 /workspace/coverage/default/19.edn_genbits.71682919698970833799035926049753900666082375749479037189083382261648745328074 Nov 01 02:26:37 PM PDT 23 Nov 01 02:26:39 PM PDT 23 17999183 ps
T806 /workspace/coverage/default/44.edn_stress_all_with_rand_reset.52550609985539898835132392590533194928172172372523081497678337050948430663507 Nov 01 02:26:53 PM PDT 23 Nov 01 02:45:04 PM PDT 23 41708099183 ps
T807 /workspace/coverage/default/12.edn_alert_test.19585236055778259691210991319168721554101208016613043217921475740978962503173 Nov 01 02:26:02 PM PDT 23 Nov 01 02:26:08 PM PDT 23 28184990 ps
T808 /workspace/coverage/default/112.edn_genbits.372909549688418041853900271042450775233087570081486936094997619494631401547 Nov 01 02:27:14 PM PDT 23 Nov 01 02:27:30 PM PDT 23 17999183 ps
T809 /workspace/coverage/default/205.edn_genbits.98076509990446550699073557798088266758441268908998403524779050697953894976846 Nov 01 02:27:50 PM PDT 23 Nov 01 02:27:55 PM PDT 23 17999183 ps
T810 /workspace/coverage/default/22.edn_disable_auto_req_mode.69904832095786305071346227018484470971740120461581830887707516341264398922421 Nov 01 02:27:04 PM PDT 23 Nov 01 02:27:20 PM PDT 23 17319183 ps
T811 /workspace/coverage/default/20.edn_err.928874515134203764323430649868793024217695793401866733374706819517829920435 Nov 01 02:26:40 PM PDT 23 Nov 01 02:26:47 PM PDT 23 24963823 ps
T812 /workspace/coverage/default/238.edn_genbits.56539304461585694210861584461389511930478734239048606352203498008169889168529 Nov 01 02:27:55 PM PDT 23 Nov 01 02:27:59 PM PDT 23 17999183 ps
T813 /workspace/coverage/default/25.edn_disable_auto_req_mode.21405176574946725109192435365408360004237230525665216275275405521573569888719 Nov 01 02:26:32 PM PDT 23 Nov 01 02:26:34 PM PDT 23 17319183 ps
T814 /workspace/coverage/default/106.edn_genbits.84360848365555370199413817176230917396106388336338007908725121641150463686396 Nov 01 02:27:02 PM PDT 23 Nov 01 02:27:17 PM PDT 23 17999183 ps
T815 /workspace/coverage/default/44.edn_err.20477057154902053083916474021974394493980397671926676501246309195360345471323 Nov 01 02:27:10 PM PDT 23 Nov 01 02:27:26 PM PDT 23 24963823 ps
T816 /workspace/coverage/default/84.edn_genbits.71415369150856378693039979128017715116100118133694447087287555592184318818682 Nov 01 02:27:04 PM PDT 23 Nov 01 02:27:21 PM PDT 23 17999183 ps
T817 /workspace/coverage/default/15.edn_alert.107985991768259931799127889526253621096279749854557632149928387257331052088307 Nov 01 02:26:51 PM PDT 23 Nov 01 02:26:54 PM PDT 23 18259183 ps
T818 /workspace/coverage/default/1.edn_stress_all_with_rand_reset.2740463061704795081174747340015034233848542567507504381193991025693492119206 Nov 01 02:25:28 PM PDT 23 Nov 01 02:42:47 PM PDT 23 41708099183 ps
T819 /workspace/coverage/default/1.edn_disable_auto_req_mode.103012890969882242329530813207474276993638279912598814310869009681732672009517 Nov 01 02:25:44 PM PDT 23 Nov 01 02:25:47 PM PDT 23 17319183 ps
T820 /workspace/coverage/default/44.edn_stress_all.96840580708681667702019609353104748905206094269369404732794785692251539690370 Nov 01 02:27:24 PM PDT 23 Nov 01 02:27:41 PM PDT 23 154489183 ps
T821 /workspace/coverage/default/25.edn_alert_test.40426758053307625531342832790702540937747001060186012698176284094146665599638 Nov 01 02:26:40 PM PDT 23 Nov 01 02:26:45 PM PDT 23 28184990 ps
T822 /workspace/coverage/default/231.edn_genbits.82936022158806138471264368333516063492202769932206217253354322524261721037098 Nov 01 02:27:56 PM PDT 23 Nov 01 02:28:01 PM PDT 23 17999183 ps
T823 /workspace/coverage/default/10.edn_alert.58982306483450721830648462957800005796645174034307043924367781371074688915262 Nov 01 02:26:41 PM PDT 23 Nov 01 02:26:47 PM PDT 23 18259183 ps
T824 /workspace/coverage/default/25.edn_disable.104652152905166690435577103891363147569397172362123584362093522433394684831545 Nov 01 02:26:34 PM PDT 23 Nov 01 02:26:35 PM PDT 23 12219183 ps
T825 /workspace/coverage/default/248.edn_genbits.111205827812052851621018720535268138791645839311013950371205973670793975716781 Nov 01 02:28:14 PM PDT 23 Nov 01 02:28:16 PM PDT 23 17999183 ps
T826 /workspace/coverage/default/9.edn_disable_auto_req_mode.87277547704375002427115411980881005740400793669622050038169706242371694374 Nov 01 02:26:52 PM PDT 23 Nov 01 02:26:58 PM PDT 23 17319183 ps
T827 /workspace/coverage/default/24.edn_alert.61859258846912477141209436291993249752461309552008442744953452056022536870504 Nov 01 02:26:41 PM PDT 23 Nov 01 02:26:46 PM PDT 23 18259183 ps
T828 /workspace/coverage/default/30.edn_stress_all_with_rand_reset.31637128207690658419834863943088150504965393296236950577592625329277770711941 Nov 01 02:27:14 PM PDT 23 Nov 01 02:44:41 PM PDT 23 41708099183 ps
T829 /workspace/coverage/default/129.edn_genbits.102528291591963984064298127716608995951917005891556902659933400699821389317613 Nov 01 02:27:30 PM PDT 23 Nov 01 02:27:45 PM PDT 23 17999183 ps
T830 /workspace/coverage/default/19.edn_stress_all_with_rand_reset.3278254350978753822791724019122196534850905637197496588649113667975731794948 Nov 01 02:26:05 PM PDT 23 Nov 01 02:44:22 PM PDT 23 41708099183 ps
T831 /workspace/coverage/default/130.edn_genbits.13453194233104376135855646890990112051512155250899207201973628813308924425388 Nov 01 02:27:19 PM PDT 23 Nov 01 02:27:35 PM PDT 23 17999183 ps
T832 /workspace/coverage/default/25.edn_stress_all_with_rand_reset.12239259958872063614618990091608882797654856440899334483230083433263029577658 Nov 01 02:26:39 PM PDT 23 Nov 01 02:44:40 PM PDT 23 41708099183 ps
T833 /workspace/coverage/default/22.edn_disable.111739172875371240001943014080987761730199381710989332272407165811239101514054 Nov 01 02:26:56 PM PDT 23 Nov 01 02:27:05 PM PDT 23 12219183 ps
T834 /workspace/coverage/default/147.edn_genbits.15752165518571052740201191890237262698208916236845204690656723043585770283904 Nov 01 02:27:06 PM PDT 23 Nov 01 02:27:22 PM PDT 23 17999183 ps
T46 /workspace/coverage/default/1.edn_sec_cm.107232142829027529716417749428211189073251621578339548118597648157274983179618 Nov 01 02:25:45 PM PDT 23 Nov 01 02:25:53 PM PDT 23 717215632 ps
T835 /workspace/coverage/default/38.edn_intr.15537953816886102850849967207670970169603320548689033713354208845958615523292 Nov 01 02:26:51 PM PDT 23 Nov 01 02:26:55 PM PDT 23 18439183 ps
T836 /workspace/coverage/default/91.edn_err.64694172444006095132295997024002463147840992510090560912858261733416125314988 Nov 01 02:27:21 PM PDT 23 Nov 01 02:27:36 PM PDT 23 24963823 ps
T837 /workspace/coverage/default/27.edn_stress_all_with_rand_reset.33816200837729859368922480093876140956639537175007974741334306538582170128965 Nov 01 02:26:52 PM PDT 23 Nov 01 02:45:43 PM PDT 23 41708099183 ps
T838 /workspace/coverage/default/298.edn_genbits.55921461034970765695726821390391900167626860894678644563091982285544990119459 Nov 01 02:28:45 PM PDT 23 Nov 01 02:28:50 PM PDT 23 17999183 ps
T839 /workspace/coverage/default/24.edn_disable.30922393470604743218336977525019277527803658315525435096428252208687068666522 Nov 01 02:26:41 PM PDT 23 Nov 01 02:26:46 PM PDT 23 12219183 ps
T840 /workspace/coverage/default/46.edn_smoke.87853134188161799449184382701121956833525407452263595118717094784570822564795 Nov 01 02:27:02 PM PDT 23 Nov 01 02:27:17 PM PDT 23 13059183 ps
T841 /workspace/coverage/default/2.edn_alert_test.37444632147582109709029384917156160717718913509760351249321113603506828520316 Nov 01 02:25:49 PM PDT 23 Nov 01 02:25:58 PM PDT 23 28184990 ps
T842 /workspace/coverage/default/287.edn_genbits.72606988179508179322609882267742236181215919720145600861988363470814366909843 Nov 01 02:28:12 PM PDT 23 Nov 01 02:28:14 PM PDT 23 17999183 ps
T843 /workspace/coverage/default/89.edn_err.8487882871080120813041223137073106239870968923973056915805983344568446828479 Nov 01 02:27:13 PM PDT 23 Nov 01 02:27:30 PM PDT 23 24963823 ps
T844 /workspace/coverage/default/45.edn_stress_all_with_rand_reset.104605027600499447943383934381936297686943066832689859318959859920504835988698 Nov 01 02:27:01 PM PDT 23 Nov 01 02:45:16 PM PDT 23 41708099183 ps
T845 /workspace/coverage/default/30.edn_disable_auto_req_mode.13625179969717260427593710017245028088104096482498120985911813681063798446500 Nov 01 02:27:03 PM PDT 23 Nov 01 02:27:19 PM PDT 23 17319183 ps
T846 /workspace/coverage/default/11.edn_stress_all_with_rand_reset.23148113086791364839207769158691538326846770630480721976247698877206470498425 Nov 01 02:26:52 PM PDT 23 Nov 01 02:44:23 PM PDT 23 41708099183 ps
T847 /workspace/coverage/default/52.edn_genbits.100775272706978419238966102796554040753439497183558679739435352282227505421239 Nov 01 02:27:16 PM PDT 23 Nov 01 02:27:31 PM PDT 23 17999183 ps
T848 /workspace/coverage/default/19.edn_disable.39947176576395238194068257922829123280813639235809839275257637277817579274743 Nov 01 02:26:37 PM PDT 23 Nov 01 02:26:39 PM PDT 23 12219183 ps
T849 /workspace/coverage/default/250.edn_genbits.5023636329423349929028273818112564078612858129654267205277892423810344300248 Nov 01 02:27:58 PM PDT 23 Nov 01 02:28:04 PM PDT 23 17999183 ps
T850 /workspace/coverage/default/11.edn_err.99506681660868727904609898109839382084884793400459489693581470107678236294966 Nov 01 02:27:14 PM PDT 23 Nov 01 02:27:30 PM PDT 23 24963823 ps
T851 /workspace/coverage/default/13.edn_err.82081852306126434194890468631538986377932635188116778881844570634318817770123 Nov 01 02:26:36 PM PDT 23 Nov 01 02:26:38 PM PDT 23 24963823 ps
T852 /workspace/coverage/default/11.edn_alert.56884455962580170745782242105881920112591381843480341063287709291691835787237 Nov 01 02:26:56 PM PDT 23 Nov 01 02:27:07 PM PDT 23 18259183 ps
T853 /workspace/coverage/default/40.edn_err.36928543673774328795315663609319837774353705242675456986286427915032649234906 Nov 01 02:26:55 PM PDT 23 Nov 01 02:27:04 PM PDT 23 24963823 ps
T854 /workspace/coverage/default/32.edn_err.113850612200385744632906605431889743483622563648679002845526466960578691181961 Nov 01 02:26:52 PM PDT 23 Nov 01 02:26:58 PM PDT 23 24963823 ps
T855 /workspace/coverage/default/49.edn_alert_test.53924379899428320102230247605793767304979855222689124635521650873463479259192 Nov 01 02:27:20 PM PDT 23 Nov 01 02:27:35 PM PDT 23 28184990 ps
T856 /workspace/coverage/default/23.edn_disable_auto_req_mode.112680953728462884037344599035048518438782910787451626314181592916884540828777 Nov 01 02:26:02 PM PDT 23 Nov 01 02:26:08 PM PDT 23 17319183 ps
T857 /workspace/coverage/default/17.edn_stress_all.87620479782462344113920549446060101707160464943200174698848965375070372976457 Nov 01 02:26:54 PM PDT 23 Nov 01 02:27:04 PM PDT 23 154489183 ps
T858 /workspace/coverage/default/78.edn_err.104152581179369044579559049567653435489485649928136794277062318263392946254241 Nov 01 02:27:08 PM PDT 23 Nov 01 02:27:25 PM PDT 23 24963823 ps
T859 /workspace/coverage/default/62.edn_err.45760151504513944165616469742588595597985131898283542994248571733870815002133 Nov 01 02:27:07 PM PDT 23 Nov 01 02:27:27 PM PDT 23 24963823 ps
T860 /workspace/coverage/default/16.edn_alert_test.100516333816950937019618882451470631412174350947243328159490486655044087787371 Nov 01 02:27:13 PM PDT 23 Nov 01 02:27:30 PM PDT 23 28184990 ps
T861 /workspace/coverage/default/269.edn_genbits.42298623856331286788913886013187951720030251839973618672655066401970689172086 Nov 01 02:27:57 PM PDT 23 Nov 01 02:28:03 PM PDT 23 17999183 ps
T862 /workspace/coverage/default/42.edn_stress_all.102207256797268574603006300182560783871168034650539687756147835165386164445197 Nov 01 02:27:04 PM PDT 23 Nov 01 02:27:23 PM PDT 23 154489183 ps
T863 /workspace/coverage/default/90.edn_genbits.51251152240511228567775957162915441375128138262955143334115378564437109731608 Nov 01 02:27:24 PM PDT 23 Nov 01 02:27:39 PM PDT 23 17999183 ps
T864 /workspace/coverage/default/240.edn_genbits.48789304759455564172568218421608347695494880129755837343941363646447916764332 Nov 01 02:28:09 PM PDT 23 Nov 01 02:28:11 PM PDT 23 17999183 ps
T865 /workspace/coverage/default/86.edn_err.45464500321045066521179872464795064500023287431875863829588945931032825985564 Nov 01 02:27:17 PM PDT 23 Nov 01 02:27:32 PM PDT 23 24963823 ps
T866 /workspace/coverage/default/18.edn_alert_test.18381300638264993352531231030784294594024394846733502134358986772879026673222 Nov 01 02:26:38 PM PDT 23 Nov 01 02:26:40 PM PDT 23 28184990 ps
T867 /workspace/coverage/default/3.edn_alert_test.105851593586657216451533300965120458537299073809418625157910780633371205370034 Nov 01 02:25:52 PM PDT 23 Nov 01 02:25:58 PM PDT 23 28184990 ps
T868 /workspace/coverage/default/33.edn_stress_all.29597569346034238675488890877788228562095024042682749229771854829122437341950 Nov 01 02:26:51 PM PDT 23 Nov 01 02:26:58 PM PDT 23 154489183 ps
T869 /workspace/coverage/default/32.edn_alert.8948043484077889150368813607549667990987420117413096650995989343082444411978 Nov 01 02:26:52 PM PDT 23 Nov 01 02:26:58 PM PDT 23 18259183 ps
T870 /workspace/coverage/default/224.edn_genbits.112241292569535869928643919356245928503772738687193168571626571082169149125493 Nov 01 02:27:56 PM PDT 23 Nov 01 02:28:01 PM PDT 23 17999183 ps
T871 /workspace/coverage/default/202.edn_genbits.39420120726081196738328012853985267673447509925381222220561509801054098527182 Nov 01 02:27:55 PM PDT 23 Nov 01 02:27:59 PM PDT 23 17999183 ps
T872 /workspace/coverage/default/245.edn_genbits.67468642321601482957660055292233790126998551112223062514637075014261425610995 Nov 01 02:28:02 PM PDT 23 Nov 01 02:28:07 PM PDT 23 17999183 ps
T873 /workspace/coverage/default/14.edn_err.99304393855059322678954326804086153631659739641438797611650193655421170232393 Nov 01 02:26:45 PM PDT 23 Nov 01 02:26:50 PM PDT 23 24963823 ps
T874 /workspace/coverage/default/41.edn_disable.32378754263460585116459494580140892617763850363682820425177095766296839997398 Nov 01 02:27:00 PM PDT 23 Nov 01 02:27:13 PM PDT 23 12219183 ps
T875 /workspace/coverage/default/14.edn_disable_auto_req_mode.64321989324726553089055624940783178847059635847272971241088923771508583343851 Nov 01 02:26:41 PM PDT 23 Nov 01 02:26:46 PM PDT 23 17319183 ps
T876 /workspace/coverage/default/79.edn_genbits.69972186432175984235286405559071888823762226136988791754775655971160370882747 Nov 01 02:27:09 PM PDT 23 Nov 01 02:27:26 PM PDT 23 17999183 ps
T877 /workspace/coverage/default/36.edn_genbits.107081218118125120209070104070953178504699565720717423656453836347241382540904 Nov 01 02:27:01 PM PDT 23 Nov 01 02:27:16 PM PDT 23 17999183 ps
T878 /workspace/coverage/default/149.edn_genbits.41483369123747490307354739479566894209785232873475436556868717684877905434164 Nov 01 02:27:07 PM PDT 23 Nov 01 02:27:23 PM PDT 23 17999183 ps
T879 /workspace/coverage/default/0.edn_alert_test.92720063166081192481364246085983604085517766445533634620872847895999275634894 Nov 01 02:25:29 PM PDT 23 Nov 01 02:25:31 PM PDT 23 28184990 ps
T880 /workspace/coverage/default/8.edn_disable_auto_req_mode.37638868522823795067110770480672073580251189719162005358133739310248789764347 Nov 01 02:26:03 PM PDT 23 Nov 01 02:26:08 PM PDT 23 17319183 ps
T881 /workspace/coverage/default/5.edn_smoke.10695388146327691662459874410511842306342022752467384910848655212140527873767 Nov 01 02:26:09 PM PDT 23 Nov 01 02:26:14 PM PDT 23 13059183 ps
T882 /workspace/coverage/default/47.edn_alert.7412665659435246932597527047203107370332430869163245155073840677954613870339 Nov 01 02:27:56 PM PDT 23 Nov 01 02:28:01 PM PDT 23 18259183 ps
T883 /workspace/coverage/default/236.edn_genbits.79427094596802737043478439511187046403277414481234401298960611649620186640642 Nov 01 02:27:59 PM PDT 23 Nov 01 02:28:05 PM PDT 23 17999183 ps
T884 /workspace/coverage/default/8.edn_alert.19289682457984368783918433866699629787447519410724780317571392862346447533183 Nov 01 02:25:53 PM PDT 23 Nov 01 02:26:01 PM PDT 23 18259183 ps
T885 /workspace/coverage/default/17.edn_alert_test.3437914330948981268557321576488574388631180584531640516232207501431599365450 Nov 01 02:26:32 PM PDT 23 Nov 01 02:26:33 PM PDT 23 28184990 ps
T886 /workspace/coverage/default/1.edn_stress_all.102160932637536879983381293608669663319395098931479249483525912529369586046526 Nov 01 02:25:35 PM PDT 23 Nov 01 02:25:40 PM PDT 23 154489183 ps
T887 /workspace/coverage/default/122.edn_genbits.67785536555454343207598350803333554222008051185605418933531549794512872077373 Nov 01 02:28:10 PM PDT 23 Nov 01 02:28:12 PM PDT 23 17999183 ps
T888 /workspace/coverage/default/98.edn_err.30345946414667468819708914525266190898616387980709658337483076874619490844220 Nov 01 02:27:00 PM PDT 23 Nov 01 02:27:13 PM PDT 23 24963823 ps
T889 /workspace/coverage/default/295.edn_genbits.28354820845349198957647590044150506097535111300803807256405998606009911625603 Nov 01 02:28:18 PM PDT 23 Nov 01 02:28:20 PM PDT 23 17999183 ps
T890 /workspace/coverage/default/37.edn_disable.66645411952566843428668719076285465130418253668175416662708628066627986323618 Nov 01 02:26:54 PM PDT 23 Nov 01 02:27:01 PM PDT 23 12219183 ps
T891 /workspace/coverage/default/47.edn_disable.50214286244485093857384349870261634925757872231944316507884749479619723291863 Nov 01 02:27:57 PM PDT 23 Nov 01 02:28:03 PM PDT 23 12219183 ps
T892 /workspace/coverage/default/75.edn_err.66713067085150276032880481554281048197628881459791670018936682218216022579261 Nov 01 02:27:17 PM PDT 23 Nov 01 02:27:32 PM PDT 23 24963823 ps
T893 /workspace/coverage/default/99.edn_genbits.94812329571765201841403244289536333335112226405097860407370000034108485149282 Nov 01 02:27:04 PM PDT 23 Nov 01 02:27:20 PM PDT 23 17999183 ps
T894 /workspace/coverage/default/272.edn_genbits.51832395431385418918121096000217381461928195108892860490644888973842670004990 Nov 01 02:27:53 PM PDT 23 Nov 01 02:27:57 PM PDT 23 17999183 ps
T895 /workspace/coverage/default/17.edn_stress_all_with_rand_reset.115637712051816726370441528135720710716040537351288945585268775795292635752459 Nov 01 02:27:03 PM PDT 23 Nov 01 02:45:14 PM PDT 23 41708099183 ps
T896 /workspace/coverage/default/93.edn_genbits.13595614652049290589290996944281429245294316186740277919368246818463864063100 Nov 01 02:27:20 PM PDT 23 Nov 01 02:27:35 PM PDT 23 17999183 ps
T897 /workspace/coverage/default/144.edn_genbits.114995292966781633572577952990112392339735291667892111065181023873238237602486 Nov 01 02:26:58 PM PDT 23 Nov 01 02:27:10 PM PDT 23 17999183 ps
T898 /workspace/coverage/default/217.edn_genbits.42241178482903102724510011162984027566151734618608847499263537930995823427200 Nov 01 02:27:56 PM PDT 23 Nov 01 02:28:02 PM PDT 23 17999183 ps
T899 /workspace/coverage/default/54.edn_genbits.54333702650949138019784186244731601998987220994280382226839242693798333585757 Nov 01 02:27:12 PM PDT 23 Nov 01 02:27:29 PM PDT 23 17999183 ps
T900 /workspace/coverage/default/16.edn_disable_auto_req_mode.96642301943439560959448526505786475215249596719016399803115850671354044916532 Nov 01 02:26:57 PM PDT 23 Nov 01 02:27:08 PM PDT 23 17319183 ps
T901 /workspace/coverage/default/8.edn_stress_all_with_rand_reset.30288729829634542198603467648108281074663045391073448896856828568500511904295 Nov 01 02:26:37 PM PDT 23 Nov 01 02:44:59 PM PDT 23 41708099183 ps
T902 /workspace/coverage/default/11.edn_genbits.3940548841021268640758123147416517160066516340437663448837905102892227198832 Nov 01 02:26:58 PM PDT 23 Nov 01 02:27:10 PM PDT 23 17999183 ps
T903 /workspace/coverage/default/12.edn_genbits.74641651993128873054053157088303803798039838415390638336795759834454969652336 Nov 01 02:26:59 PM PDT 23 Nov 01 02:27:12 PM PDT 23 17999183 ps
T904 /workspace/coverage/default/28.edn_stress_all.7996926464034241803806835099506467875038326939104705088312048011756740563292 Nov 01 02:26:50 PM PDT 23 Nov 01 02:26:56 PM PDT 23 154489183 ps
T905 /workspace/coverage/default/142.edn_genbits.25132845817395345680009822423983936766860811940905769024659605661495878712953 Nov 01 02:26:55 PM PDT 23 Nov 01 02:27:02 PM PDT 23 17999183 ps
T906 /workspace/coverage/default/21.edn_alert.27702660933258017664167009403452520443405754280615268013522244370527063282386 Nov 01 02:26:49 PM PDT 23 Nov 01 02:26:52 PM PDT 23 18259183 ps
T907 /workspace/coverage/default/31.edn_smoke.29664284252019697136193743775279264764646575146749651218132304445051125384328 Nov 01 02:27:09 PM PDT 23 Nov 01 02:27:26 PM PDT 23 13059183 ps
T908 /workspace/coverage/default/47.edn_disable_auto_req_mode.1496715826999622183069034894648753372885240278135034237356982202568815827828 Nov 01 02:27:14 PM PDT 23 Nov 01 02:27:30 PM PDT 23 17319183 ps
T909 /workspace/coverage/default/211.edn_genbits.110906604635799696902131505934717204579752178438480769137383233643453468944649 Nov 01 02:27:53 PM PDT 23 Nov 01 02:27:58 PM PDT 23 17999183 ps
T910 /workspace/coverage/default/35.edn_alert_test.99846097327417418523362316954600951509123868507018663586466241230033534734161 Nov 01 02:27:18 PM PDT 23 Nov 01 02:27:33 PM PDT 23 28184990 ps
T911 /workspace/coverage/default/279.edn_genbits.113417204760591087564440789062634321524682820597362936048606439491957911063457 Nov 01 02:28:03 PM PDT 23 Nov 01 02:28:07 PM PDT 23 17999183 ps
T912 /workspace/coverage/default/179.edn_genbits.10919375743714818157391247872343666037675100096612728074815011506663452121724 Nov 01 02:27:20 PM PDT 23 Nov 01 02:27:35 PM PDT 23 17999183 ps
T913 /workspace/coverage/default/12.edn_err.101758496551893347136841474675537833094990002897597100044577250303379728343618 Nov 01 02:26:42 PM PDT 23 Nov 01 02:26:48 PM PDT 23 24963823 ps
T914 /workspace/coverage/default/5.edn_genbits.73175101393858996168607542873799693286777380838974088671218678003515973820288 Nov 01 02:26:30 PM PDT 23 Nov 01 02:26:33 PM PDT 23 17999183 ps
T915 /workspace/coverage/default/19.edn_smoke.79129579094423716869834363253944337574400588974169966030808833733292619987543 Nov 01 02:26:06 PM PDT 23 Nov 01 02:26:11 PM PDT 23 13059183 ps
T916 /workspace/coverage/default/10.edn_genbits.112058002541423032614183085876490552461312731660862408723853339568595178898310 Nov 01 02:26:52 PM PDT 23 Nov 01 02:26:57 PM PDT 23 17999183 ps
T917 /workspace/coverage/default/229.edn_genbits.39049447718559638475109803755674919841100584291668764532383346108794320048812 Nov 01 02:27:59 PM PDT 23 Nov 01 02:28:05 PM PDT 23 17999183 ps
T918 /workspace/coverage/default/4.edn_disable_auto_req_mode.80581746005518018142221703973724281255243491607702052274929923588608602086270 Nov 01 02:26:44 PM PDT 23 Nov 01 02:26:50 PM PDT 23 17319183 ps
T919 /workspace/coverage/default/31.edn_disable_auto_req_mode.14258325429309772144492024275680536104410354342324710460522620294081167207149 Nov 01 02:26:38 PM PDT 23 Nov 01 02:26:41 PM PDT 23 17319183 ps
T920 /workspace/coverage/default/40.edn_intr.14583621606834982992852398618054906907788002824630533883037096606817477320581 Nov 01 02:27:02 PM PDT 23 Nov 01 02:27:17 PM PDT 23 18439183 ps
T921 /workspace/coverage/default/82.edn_err.81474994807473168165700722815155482702416814417626980070809877447450158891934 Nov 01 02:27:15 PM PDT 23 Nov 01 02:27:30 PM PDT 23 24963823 ps
T922 /workspace/coverage/default/20.edn_stress_all.52783967613568882168091623160140224404213981469292927368340114224942372297129 Nov 01 02:26:07 PM PDT 23 Nov 01 02:26:16 PM PDT 23 154489183 ps
T923 /workspace/coverage/default/49.edn_intr.89811849978106553564973354886438683189413944187727973787407957783576189692026 Nov 01 02:26:55 PM PDT 23 Nov 01 02:27:05 PM PDT 23 18439183 ps
T924 /workspace/coverage/default/45.edn_genbits.14473859946158156929289612527536135205665148084035737827671153966088183172443 Nov 01 02:26:59 PM PDT 23 Nov 01 02:27:11 PM PDT 23 17999183 ps
T925 /workspace/coverage/default/29.edn_err.41175571889706414459492372599470731329119749909343523696668267765502115961097 Nov 01 02:27:16 PM PDT 23 Nov 01 02:27:31 PM PDT 23 24963823 ps
T926 /workspace/coverage/default/9.edn_alert_test.69298428045660065975146543641125251228902948925869606297471550932238706093219 Nov 01 02:26:40 PM PDT 23 Nov 01 02:26:45 PM PDT 23 28184990 ps
T927 /workspace/coverage/default/17.edn_genbits.81595658011659278609245253021422542663866353532094313909562952679111753541491 Nov 01 02:26:59 PM PDT 23 Nov 01 02:27:11 PM PDT 23 17999183 ps
T928 /workspace/coverage/default/50.edn_genbits.75150263013416970250094135094991248156883473701889146806816850426252156922434 Nov 01 02:27:22 PM PDT 23 Nov 01 02:27:37 PM PDT 23 17999183 ps
T929 /workspace/coverage/default/6.edn_genbits.50356774340798284758638957359501328067937995380444749457469932706547185381933 Nov 01 02:26:49 PM PDT 23 Nov 01 02:26:53 PM PDT 23 17999183 ps
T930 /workspace/coverage/default/1.edn_disable.115785199104052555637232652702712576051903159322941341936702383393163300767674 Nov 01 02:25:40 PM PDT 23 Nov 01 02:25:43 PM PDT 23 12219183 ps
T931 /workspace/coverage/default/100.edn_genbits.43071622269924847793286912130040929499530078309646670826161488616614930882580 Nov 01 02:27:04 PM PDT 23 Nov 01 02:27:19 PM PDT 23 17999183 ps
T932 /workspace/coverage/default/225.edn_genbits.115171262457258291469483227896874371162239017150608831715372915423782313009842 Nov 01 02:27:58 PM PDT 23 Nov 01 02:28:04 PM PDT 23 17999183 ps
T933 /workspace/coverage/default/242.edn_genbits.105948887569011725695050157585981115601404852059882227699277017026171988205272 Nov 01 02:28:02 PM PDT 23 Nov 01 02:28:07 PM PDT 23 17999183 ps
T934 /workspace/coverage/default/44.edn_smoke.2021501134257176916459536975334557045444513623849674451782770433693337157670 Nov 01 02:26:59 PM PDT 23 Nov 01 02:27:11 PM PDT 23 13059183 ps
T935 /workspace/coverage/default/3.edn_regwen.63049477260640066234848272102862558543531254063339464767101040771892597304329 Nov 01 02:25:49 PM PDT 23 Nov 01 02:25:58 PM PDT 23 11759183 ps
T936 /workspace/coverage/default/101.edn_genbits.96148466342106512223522431682044678210308968850237862692382657478125546489850 Nov 01 02:27:02 PM PDT 23 Nov 01 02:27:17 PM PDT 23 17999183 ps
T937 /workspace/coverage/default/30.edn_smoke.57308135626096693616035646515218439048363327424117732271314690607733051435456 Nov 01 02:27:09 PM PDT 23 Nov 01 02:27:26 PM PDT 23 13059183 ps
T47 /workspace/coverage/default/2.edn_sec_cm.33469853543819872458139030803694883646118892872505108695518966694708742587922 Nov 01 02:25:49 PM PDT 23 Nov 01 02:26:03 PM PDT 23 717215632 ps
T938 /workspace/coverage/default/29.edn_disable.105563070505280295825786316500396924571585635899864772854544347122345928088712 Nov 01 02:27:04 PM PDT 23 Nov 01 02:27:19 PM PDT 23 12219183 ps
T939 /workspace/coverage/default/32.edn_alert_test.12610819309415062077310332319763279713414150920651330947644298569653106691998 Nov 01 02:26:49 PM PDT 23 Nov 01 02:26:52 PM PDT 23 28184990 ps
T940 /workspace/coverage/default/32.edn_disable.12914803041702383608878904457770837711769606450610597344199830052603782159828 Nov 01 02:26:42 PM PDT 23 Nov 01 02:26:47 PM PDT 23 12219183 ps
T941 /workspace/coverage/default/4.edn_intr.89595967017147317825082610668960346123990372258394915022284728732395279627925 Nov 01 02:26:38 PM PDT 23 Nov 01 02:26:43 PM PDT 23 18439183 ps
T942 /workspace/coverage/default/2.edn_genbits.85260760511083634758009735429269209204925580921772812671521469110250341630782 Nov 01 02:25:45 PM PDT 23 Nov 01 02:25:48 PM PDT 23 17999183 ps
T943 /workspace/coverage/default/51.edn_err.49195464887480719000340386135332418016248083611930017435777471496127923789889 Nov 01 02:27:00 PM PDT 23 Nov 01 02:27:14 PM PDT 23 24963823 ps
T944 /workspace/coverage/default/40.edn_smoke.46966294800952184899502183657794211733589801560975049883795270548651467846458 Nov 01 02:27:09 PM PDT 23 Nov 01 02:27:26 PM PDT 23 13059183 ps
T945 /workspace/coverage/default/26.edn_stress_all.5514954251361955455907090748941571123852952454246970949020880256561282187058 Nov 01 02:26:30 PM PDT 23 Nov 01 02:26:35 PM PDT 23 154489183 ps
T946 /workspace/coverage/default/28.edn_smoke.78844820250119828198639298842634418575607449192860957580602864954415476589596 Nov 01 02:26:38 PM PDT 23 Nov 01 02:26:43 PM PDT 23 13059183 ps
T947 /workspace/coverage/default/8.edn_err.80803781439217015376850037490354371903952567800873347239637580850566511859971 Nov 01 02:26:04 PM PDT 23 Nov 01 02:26:08 PM PDT 23 24963823 ps
T948 /workspace/coverage/default/43.edn_genbits.40941458721894310666349756724141660885707090081718946144771540638881350172599 Nov 01 02:27:04 PM PDT 23 Nov 01 02:27:20 PM PDT 23 17999183 ps
T949 /workspace/coverage/default/36.edn_alert_test.32500623787308169473205242544862863841403508639874389909922383637172684398421 Nov 01 02:26:38 PM PDT 23 Nov 01 02:26:40 PM PDT 23 28184990 ps
T950 /workspace/coverage/default/31.edn_err.93000218953468136850176454684452584812472443932745894415169738241200766328133 Nov 01 02:26:39 PM PDT 23 Nov 01 02:26:44 PM PDT 23 24963823 ps
T951 /workspace/coverage/default/174.edn_genbits.35832100119754386860861355211943569593383288292064610677784857172353052922350 Nov 01 02:27:24 PM PDT 23 Nov 01 02:27:38 PM PDT 23 17999183 ps
T952 /workspace/coverage/default/32.edn_intr.47492129762523026158143172795023622954546156565013604814448480923173450264464 Nov 01 02:26:40 PM PDT 23 Nov 01 02:26:46 PM PDT 23 18439183 ps
T953 /workspace/coverage/default/44.edn_genbits.109825038594106767319316760455536116157828350166618422594824024997598571363185 Nov 01 02:26:56 PM PDT 23 Nov 01 02:27:05 PM PDT 23 17999183 ps
T954 /workspace/coverage/default/32.edn_genbits.94873125628588403072550874049218771548196238578780407650238497057513599857355 Nov 01 02:26:44 PM PDT 23 Nov 01 02:26:50 PM PDT 23 17999183 ps
T955 /workspace/coverage/default/158.edn_genbits.17963693736476240734085945115661072162520176802523076497535671284591029364243 Nov 01 02:27:10 PM PDT 23 Nov 01 02:27:26 PM PDT 23 17999183 ps
T956 /workspace/coverage/default/11.edn_alert_test.112187487766572065025089693482695866122513838290217771469991276210566473260532 Nov 01 02:27:21 PM PDT 23 Nov 01 02:27:35 PM PDT 23 28184990 ps
T957 /workspace/coverage/default/8.edn_alert_test.94069708849508966625260948555146370780890758832700231896589931681971931923678 Nov 01 02:26:34 PM PDT 23 Nov 01 02:26:36 PM PDT 23 28184990 ps
T958 /workspace/coverage/default/40.edn_disable.86104884051956449144331168922461366077415383983581221394523055942824034880977 Nov 01 02:27:03 PM PDT 23 Nov 01 02:27:18 PM PDT 23 12219183 ps
T959 /workspace/coverage/default/54.edn_err.98932587223836073516362142712951911748232232883910358627276539913339688359543 Nov 01 02:26:57 PM PDT 23 Nov 01 02:27:09 PM PDT 23 24963823 ps
T960 /workspace/coverage/default/0.edn_disable.105788515316939463957783125337194031475895266610619965670302988595024232299695 Nov 01 02:25:26 PM PDT 23 Nov 01 02:25:29 PM PDT 23 12219183 ps
T961 /workspace/coverage/default/48.edn_err.64708073754692750868922897718005185913284180260776330545114743088893365883139 Nov 01 02:27:18 PM PDT 23 Nov 01 02:27:34 PM PDT 23 24963823 ps
T962 /workspace/coverage/default/105.edn_genbits.26816381765644901745096156602118898331286525248546846966349218848660924822585 Nov 01 02:27:09 PM PDT 23 Nov 01 02:27:26 PM PDT 23 17999183 ps
T963 /workspace/coverage/default/38.edn_alert.52579613332578790308579178100488794768001858701760431657407356923691733288063 Nov 01 02:27:09 PM PDT 23 Nov 01 02:27:26 PM PDT 23 18259183 ps
T964 /workspace/coverage/default/21.edn_stress_all.13527849990192183993826307094260111167475200129093509418915555185856556207332 Nov 01 02:26:50 PM PDT 23 Nov 01 02:26:57 PM PDT 23 154489183 ps
T965 /workspace/coverage/default/32.edn_smoke.58446472590697262589972857453000949757721208011192784737116301966178096067667 Nov 01 02:26:51 PM PDT 23 Nov 01 02:26:55 PM PDT 23 13059183 ps
T966 /workspace/coverage/default/2.edn_err.98685405926092317659875323017737504948248172377853988917779898790805494539415 Nov 01 02:25:50 PM PDT 23 Nov 01 02:25:58 PM PDT 23 24963823 ps
T967 /workspace/coverage/default/41.edn_stress_all.13145194104404439217892398411557877838163275572768200788592834450398213492758 Nov 01 02:26:55 PM PDT 23 Nov 01 02:27:07 PM PDT 23 154489183 ps
T968 /workspace/coverage/default/201.edn_genbits.8212329613208890608134790971851451406746895925107782540168009690717906430938 Nov 01 02:27:13 PM PDT 23 Nov 01 02:27:30 PM PDT 23 17999183 ps
T969 /workspace/coverage/default/48.edn_stress_all.28980866823512805289976976632449385985101630759685212484999729673492354785924 Nov 01 02:27:21 PM PDT 23 Nov 01 02:27:39 PM PDT 23 154489183 ps
T970 /workspace/coverage/default/5.edn_stress_all_with_rand_reset.57669555072270624483961288496246465865571267240334150013870894466862429771 Nov 01 02:27:04 PM PDT 23 Nov 01 02:45:01 PM PDT 23 41708099183 ps
T971 /workspace/coverage/default/7.edn_stress_all.51693013808067786041916309997774518419578285680333606085642930097494063896439 Nov 01 02:27:02 PM PDT 23 Nov 01 02:27:20 PM PDT 23 154489183 ps
T972 /workspace/coverage/default/44.edn_disable.56122519111699677191885025902694378032667153313116938637843042937765831814582 Nov 01 02:27:06 PM PDT 23 Nov 01 02:27:21 PM PDT 23 12219183 ps
T973 /workspace/coverage/default/11.edn_disable_auto_req_mode.40994720295861535670787957831146517445048145969719661097737687059782773106751 Nov 01 02:26:59 PM PDT 23 Nov 01 02:27:12 PM PDT 23 17319183 ps
T974 /workspace/coverage/default/35.edn_intr.87837794903647165485794183273556688996138748154224697496060765022520879721265 Nov 01 02:27:12 PM PDT 23 Nov 01 02:27:29 PM PDT 23 18439183 ps
T975 /workspace/coverage/default/22.edn_err.6076237577302011829121412876554002946704031674654337149699039164307466086427 Nov 01 02:26:58 PM PDT 23 Nov 01 02:27:10 PM PDT 23 24963823 ps
T976 /workspace/coverage/default/1.edn_smoke.49600493042901205537864324388689081359172446222907683478482564929329228886184 Nov 01 02:25:31 PM PDT 23 Nov 01 02:25:34 PM PDT 23 13059183 ps
T977 /workspace/coverage/default/10.edn_alert_test.99810936681338500510074234266244932729891794794422085800627930490694754832315 Nov 01 02:26:52 PM PDT 23 Nov 01 02:26:57 PM PDT 23 28184990 ps
T978 /workspace/coverage/default/280.edn_genbits.83654648322393922527158061432217768196121856423940019087894120162491567246214 Nov 01 02:27:57 PM PDT 23 Nov 01 02:28:02 PM PDT 23 17999183 ps
T979 /workspace/coverage/default/1.edn_alert_test.62818911400013492151602271152874450207847209905056868476712206748922759116621 Nov 01 02:25:43 PM PDT 23 Nov 01 02:25:45 PM PDT 23 28184990 ps
T980 /workspace/coverage/default/94.edn_err.84298539149737287260499979229725438276212376257645816593627731250665229492153 Nov 01 02:27:02 PM PDT 23 Nov 01 02:27:17 PM PDT 23 24963823 ps

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.41283720349647603720842230075665006992731711143714308651931238497590460861247
Short name T2
Test name
Test status
Simulation time 41708099183 ps
CPU time 1077.16 seconds
Started Nov 01 02:26:45 PM PDT 23
Finished Nov 01 02:44:47 PM PDT 23
Peak memory 215916 kb
Host smart-47f10c71-c80d-4c57-98de-cfa9cf425127
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412837203496476037208422300
75665006992731711143714308651931238497590460861247 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.41283720349
647603720842230075665006992731711143714308651931238497590460861247
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/206.edn_genbits.100839703559516437679881535699173289453782836177617169877682277574279451331050
Short name T16
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:27:55 PM PDT 23
Finished Nov 01 02:28:00 PM PDT 23
Peak memory 205880 kb
Host smart-124a084c-e351-46e7-80f2-0b4812f77fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100839703559516437679881535699173289453782836177617169877682277574279451331050 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 206.edn_genbits.100839703559516437679881535699173289453782836177617169877682277574279451331050
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.13557192323313978996402987061527472929093408979004727952816642577119181849555
Short name T22
Test name
Test status
Simulation time 17319183 ps
CPU time 0.93 seconds
Started Nov 01 02:27:27 PM PDT 23
Finished Nov 01 02:27:42 PM PDT 23
Peak memory 214664 kb
Host smart-da389b15-2824-4f67-9f4b-3a39610b0023
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13557192323313978996402987061527472929093408979004727952816642577119181849555 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable_auto_req_mode.1355719232331397899640298706152747292909340897900472795281
6642577119181849555
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_sec_cm.88339970801648664057191274275742913310308345396643112187426384050041946288383
Short name T30
Test name
Test status
Simulation time 717215632 ps
CPU time 5.97 seconds
Started Nov 01 02:25:51 PM PDT 23
Finished Nov 01 02:26:03 PM PDT 23
Peak memory 234012 kb
Host smart-afd13e2a-e79f-4d08-a35d-1519e2b6f305
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88339970801648664057191274275742913310308345396643112187426384050041946288383 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.edn_sec_cm.88339970801648664057191274275742913310308345396643112187426384050041946288383
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/29.edn_intr.13527238767729303368905231657583412996173687438300121457596208463709764573300
Short name T26
Test name
Test status
Simulation time 18439183 ps
CPU time 1.11 seconds
Started Nov 01 02:27:04 PM PDT 23
Finished Nov 01 02:27:19 PM PDT 23
Peak memory 222360 kb
Host smart-5f12f2ef-52ab-498f-90aa-51903e852572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13527238767729303368905231657583412996173687438300121457596208463709764573300 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.edn_intr.13527238767729303368905231657583412996173687438300121457596208463709764573300
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/12.edn_disable.101567227626818212241759035604093815151967197937998981084435357190224994085347
Short name T59
Test name
Test status
Simulation time 12219183 ps
CPU time 0.87 seconds
Started Nov 01 02:26:38 PM PDT 23
Finished Nov 01 02:26:42 PM PDT 23
Peak memory 214980 kb
Host smart-714b041c-0fd4-46e6-b20f-009239c24105
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101567227626818212241759035604093815151967197937998981084435357190224994085347 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 12.edn_disable.101567227626818212241759035604093815151967197937998981084435357190224994085347
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.108680137141747488246764835187104966609255726408619105263902432664082197753914
Short name T6
Test name
Test status
Simulation time 155537119 ps
CPU time 2.2 seconds
Started Nov 01 02:44:02 PM PDT 23
Finished Nov 01 02:44:08 PM PDT 23
Peak memory 206616 kb
Host smart-0d272c48-5e1f-4364-be23-d6ed46b1d0da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108680137141747488246764835187104966609255726408619105263902432664082197753914 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.108680137141747488246764835187104966609255726408619105263902432664082197753914
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/default/13.edn_alert.78021040601449399344042316684983259357357793980389969567751677415137672798597
Short name T42
Test name
Test status
Simulation time 18259183 ps
CPU time 0.99 seconds
Started Nov 01 02:26:01 PM PDT 23
Finished Nov 01 02:26:08 PM PDT 23
Peak memory 205620 kb
Host smart-2f5eb74e-7542-4197-9296-967376db59e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78021040601449399344042316684983259357357793980389969567751677415137672798597 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.edn_alert.78021040601449399344042316684983259357357793980389969567751677415137672798597
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/9.edn_regwen.32091947843041653896684288676016999229482734946291039345797756643416867931894
Short name T92
Test name
Test status
Simulation time 11759183 ps
CPU time 0.9 seconds
Started Nov 01 02:26:07 PM PDT 23
Finished Nov 01 02:26:12 PM PDT 23
Peak memory 205376 kb
Host smart-56118397-1196-4f2a-abda-9daf535c5033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32091947843041653896684288676016999229482734946291039345797756643416867931894 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.edn_regwen.32091947843041653896684288676016999229482734946291039345797756643416867931894
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/18.edn_err.113136401267020155764044234065221976902010346774236160997488561010134908333982
Short name T35
Test name
Test status
Simulation time 24963823 ps
CPU time 1.16 seconds
Started Nov 01 02:26:37 PM PDT 23
Finished Nov 01 02:26:39 PM PDT 23
Peak memory 230496 kb
Host smart-294f3ce2-e737-4de4-a91a-661c72bbae99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113136401267020155764044234065221976902010346774236160997488561010134908333982 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.edn_err.113136401267020155764044234065221976902010346774236160997488561010134908333982
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.45810650617237046525515207468744094535439372136190991271588721188068876207187
Short name T70
Test name
Test status
Simulation time 61976116 ps
CPU time 1.27 seconds
Started Nov 01 02:43:26 PM PDT 23
Finished Nov 01 02:43:30 PM PDT 23
Peak memory 206568 kb
Host smart-0da3ef45-b075-477a-b390-84cbb1ff01e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45810650617237046525515207468744094535439372136190991271588721188068876207187
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_outstanding.45810650617237046525515207468744094535439372136190991271588721188068876207187
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/default/23.edn_alert_test.109534551488697335952992722735725307818730740658928014781386484822413227634734
Short name T282
Test name
Test status
Simulation time 28184990 ps
CPU time 0.93 seconds
Started Nov 01 02:26:37 PM PDT 23
Finished Nov 01 02:26:40 PM PDT 23
Peak memory 205540 kb
Host smart-38bdd205-49be-4240-9f30-d4455126e57e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109534551488697335952992722735725307818730740658928014781386484822413227634734 -assert nopostp
roc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 23.edn_alert_test.109534551488697335952992722735725307818730740658928014781386484822413227634734
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_stress_all.16472788614991963360291692594631474860210043182544551855099135016585409060171
Short name T376
Test name
Test status
Simulation time 154489183 ps
CPU time 4.17 seconds
Started Nov 01 02:25:48 PM PDT 23
Finished Nov 01 02:26:01 PM PDT 23
Peak memory 206432 kb
Host smart-06b3c435-137a-4ef6-8202-67d885867164
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16472788614991963360291692594631474860210043182544551855099135016585409060171 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.16472788614991963360291692594631474860210043182544551855099135016585409060171
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.114271250953093582399611792413736589618008501839602515278546226766315367583814
Short name T161
Test name
Test status
Simulation time 59184494 ps
CPU time 1.28 seconds
Started Nov 01 02:42:38 PM PDT 23
Finished Nov 01 02:42:42 PM PDT 23
Peak memory 206496 kb
Host smart-7b1e0051-9d08-4a09-94df-1cbd04ae0b4b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114271250953093582399611792413736589618008501839602515278546226766315367583814 -assert nop
ostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.114271250953093582399611792413736589618008501839602515278546226766315367583814
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.89019889383239209576233228038761508566828691161756107512738832125670243324967
Short name T99
Test name
Test status
Simulation time 351971476 ps
CPU time 4.9 seconds
Started Nov 01 02:42:32 PM PDT 23
Finished Nov 01 02:42:41 PM PDT 23
Peak memory 206592 kb
Host smart-95b61225-439f-4dc2-baba-83e25bb5860c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89019889383239209576233228038761508566828691161756107512738832125670243324967 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.89019889383239209576233228038761508566828691161756107512738832125670243324967
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.84754052855275680135809602446307757755196423798541985371915546304544138469181
Short name T221
Test name
Test status
Simulation time 26726680 ps
CPU time 0.87 seconds
Started Nov 01 02:42:35 PM PDT 23
Finished Nov 01 02:42:39 PM PDT 23
Peak memory 206568 kb
Host smart-988f8a4e-6a7f-445a-9ae5-baabf8411fe9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84754052855275680135809602446307757755196423798541985371915546304544138469181 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.84754052855275680135809602446307757755196423798541985371915546304544138469181
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.63814146179104590457306991910572712690729563041062057480738757315426819432021
Short name T199
Test name
Test status
Simulation time 51163789 ps
CPU time 1.29 seconds
Started Nov 01 02:42:36 PM PDT 23
Finished Nov 01 02:42:40 PM PDT 23
Peak memory 214756 kb
Host smart-ff93f586-a585-43ac-9816-65304802f0e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6381414617910459045730699191057271269072956
3041062057480738757315426819432021 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.6381414617910459045730699191
0572712690729563041062057480738757315426819432021
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.96027996842664645245544980117350217106353244600402816773939639301892423877529
Short name T78
Test name
Test status
Simulation time 23247569 ps
CPU time 0.87 seconds
Started Nov 01 02:42:39 PM PDT 23
Finished Nov 01 02:42:46 PM PDT 23
Peak memory 206504 kb
Host smart-6adf9f5a-e402-4363-9acf-b0104126d634
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96027996842664645245544980117350217106353244600402816773939639301892423877529 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.96027996842664645245544980117350217106353244600402816773939639301892423877529
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.110212653107126853351546626943916281691534711131514981437758733541512228647660
Short name T79
Test name
Test status
Simulation time 25518366 ps
CPU time 0.84 seconds
Started Nov 01 02:42:36 PM PDT 23
Finished Nov 01 02:42:39 PM PDT 23
Peak memory 206500 kb
Host smart-6064bad6-9fdd-429e-857d-804c7b5897a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110212653107126853351546626943916281691534711131514981437758733541512228647660 -assert nopostproc +
UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.edn_intr_test.110212653107126853351546626943916281691534711131514981437758733541512228647660
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.62033792476595423957572956269187356273925985791817696615020501259101350249776
Short name T82
Test name
Test status
Simulation time 61976116 ps
CPU time 1.35 seconds
Started Nov 01 02:42:39 PM PDT 23
Finished Nov 01 02:42:47 PM PDT 23
Peak memory 206608 kb
Host smart-d73d12c2-c197-40e7-99fd-15dc6faa2709
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62033792476595423957572956269187356273925985791817696615020501259101350249776
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_outstanding.62033792476595423957572956269187356273925985791817696615020501259101350249776
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.882084379376018749671456170104121232491613734094850589292976267393794501065
Short name T153
Test name
Test status
Simulation time 204078009 ps
CPU time 3.67 seconds
Started Nov 01 02:42:33 PM PDT 23
Finished Nov 01 02:42:40 PM PDT 23
Peak memory 214776 kb
Host smart-77f22d7c-5fe1-438a-b7ff-629e11afce53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882084379376018749671456170104121232491613734094850589292976267393794501065 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.edn_tl_errors.882084379376018749671456170104121232491613734094850589292976267393794501065
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.83414608371656223001053557172950319249474246695792752064921166684138289097845
Short name T227
Test name
Test status
Simulation time 155537119 ps
CPU time 2.18 seconds
Started Nov 01 02:42:39 PM PDT 23
Finished Nov 01 02:42:47 PM PDT 23
Peak memory 206548 kb
Host smart-4592d6a4-6268-4a1a-9b4f-b81c3dcbd05e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83414608371656223001053557172950319249474246695792752064921166684138289097845 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.83414608371656223001053557172950319249474246695792752064921166684138289097845
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1244240092469691793962166737669714644830060948205211232708868397978295476597
Short name T84
Test name
Test status
Simulation time 59184494 ps
CPU time 1.4 seconds
Started Nov 01 02:42:39 PM PDT 23
Finished Nov 01 02:42:46 PM PDT 23
Peak memory 206540 kb
Host smart-b586fad3-fcc1-4897-8af1-ae6628c67d08
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244240092469691793962166737669714644830060948205211232708868397978295476597 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.1244240092469691793962166737669714644830060948205211232708868397978295476597
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.48541144099246938355322629472387800164673465130032733180926811738852935674595
Short name T194
Test name
Test status
Simulation time 351971476 ps
CPU time 5.1 seconds
Started Nov 01 02:42:39 PM PDT 23
Finished Nov 01 02:42:50 PM PDT 23
Peak memory 206560 kb
Host smart-d28776a7-bef1-441a-a158-d369d65dbb69
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48541144099246938355322629472387800164673465130032733180926811738852935674595 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.48541144099246938355322629472387800164673465130032733180926811738852935674595
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.55797334672215941236501357154789614421703888834899842253191347517880349717501
Short name T220
Test name
Test status
Simulation time 26726680 ps
CPU time 0.87 seconds
Started Nov 01 02:42:39 PM PDT 23
Finished Nov 01 02:42:45 PM PDT 23
Peak memory 206544 kb
Host smart-757b124d-cf3c-458a-9688-049fa3af515d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55797334672215941236501357154789614421703888834899842253191347517880349717501 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.55797334672215941236501357154789614421703888834899842253191347517880349717501
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.30396018294790020246384474760300187442090850559670930441485807390602504905370
Short name T173
Test name
Test status
Simulation time 51163789 ps
CPU time 1.24 seconds
Started Nov 01 02:42:39 PM PDT 23
Finished Nov 01 02:42:46 PM PDT 23
Peak memory 214816 kb
Host smart-43464020-79a4-4a26-b69b-60eb18e7ad0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039601829479002024638447476030018744209085
0559670930441485807390602504905370 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.3039601829479002024638447476
0300187442090850559670930441485807390602504905370
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.82149541270141785586118433998928596297428218369706825226700610362753017367320
Short name T223
Test name
Test status
Simulation time 23247569 ps
CPU time 0.87 seconds
Started Nov 01 02:42:39 PM PDT 23
Finished Nov 01 02:42:46 PM PDT 23
Peak memory 206556 kb
Host smart-9ae78d5d-50fe-4377-b297-8b52696d2751
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82149541270141785586118433998928596297428218369706825226700610362753017367320 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.82149541270141785586118433998928596297428218369706825226700610362753017367320
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.66519059272924158075320680179980403873380220343861055125758731380733907004741
Short name T168
Test name
Test status
Simulation time 25518366 ps
CPU time 0.85 seconds
Started Nov 01 02:42:39 PM PDT 23
Finished Nov 01 02:42:45 PM PDT 23
Peak memory 206476 kb
Host smart-2b2edfe0-8035-4bc2-a64b-47396d3aa37d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66519059272924158075320680179980403873380220343861055125758731380733907004741 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 1.edn_intr_test.66519059272924158075320680179980403873380220343861055125758731380733907004741
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.108156334684858335761854724725691626687970242155567148716036199455830097121871
Short name T206
Test name
Test status
Simulation time 61976116 ps
CPU time 1.25 seconds
Started Nov 01 02:42:40 PM PDT 23
Finished Nov 01 02:42:47 PM PDT 23
Peak memory 206468 kb
Host smart-15ec77fd-dd86-4b5b-8c48-291854155af2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108156334684858335761854724725691626687970242155567148716036199455830097121871
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_outstanding.108156334684858335761854724725691626687970242155567148716036199455830097121871
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.11548043898452122785331650543825321117364276006830472689088585896598015707604
Short name T3
Test name
Test status
Simulation time 204078009 ps
CPU time 3.65 seconds
Started Nov 01 02:42:38 PM PDT 23
Finished Nov 01 02:42:47 PM PDT 23
Peak memory 214708 kb
Host smart-de23e4b9-fca5-43f6-a106-47dc4fae4c79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11548043898452122785331650543825321117364276006830472689088585896598015707604 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 1.edn_tl_errors.11548043898452122785331650543825321117364276006830472689088585896598015707604
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.80839289557793521764746349835511224948316420437947982659654052828524014279809
Short name T191
Test name
Test status
Simulation time 155537119 ps
CPU time 2.11 seconds
Started Nov 01 02:42:40 PM PDT 23
Finished Nov 01 02:42:48 PM PDT 23
Peak memory 206444 kb
Host smart-a830a38c-140a-49df-8f64-2dc1477933d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80839289557793521764746349835511224948316420437947982659654052828524014279809 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.80839289557793521764746349835511224948316420437947982659654052828524014279809
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.57048993811074599611660369724058962864763024964544330647333564596089299261211
Short name T107
Test name
Test status
Simulation time 51163789 ps
CPU time 1.28 seconds
Started Nov 01 02:43:53 PM PDT 23
Finished Nov 01 02:43:56 PM PDT 23
Peak memory 214816 kb
Host smart-a2b012f7-6904-4db1-a7d9-7221a2a52d6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5704899381107459961166036972405896286476302
4964544330647333564596089299261211 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.570489938110745996116603697
24058962864763024964544330647333564596089299261211
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.53731058055961949001186390681484585151342078203935057179424042738165479494024
Short name T138
Test name
Test status
Simulation time 23247569 ps
CPU time 0.83 seconds
Started Nov 01 02:43:54 PM PDT 23
Finished Nov 01 02:43:56 PM PDT 23
Peak memory 206532 kb
Host smart-ca3c13e1-40af-4012-a2a3-957210f3464e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53731058055961949001186390681484585151342078203935057179424042738165479494024 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.53731058055961949001186390681484585151342078203935057179424042738165479494024
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.18999862197405503114299482577395589894927030371536358110681369626260875557176
Short name T137
Test name
Test status
Simulation time 25518366 ps
CPU time 0.83 seconds
Started Nov 01 02:43:24 PM PDT 23
Finished Nov 01 02:43:27 PM PDT 23
Peak memory 206472 kb
Host smart-e7c6ec19-dda9-4f0a-a0cd-0e6a568e2500
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18999862197405503114299482577395589894927030371536358110681369626260875557176 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 10.edn_intr_test.18999862197405503114299482577395589894927030371536358110681369626260875557176
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.77902915270881686433645428312785023008820164641061442575797066645781631203101
Short name T158
Test name
Test status
Simulation time 204078009 ps
CPU time 3.76 seconds
Started Nov 01 02:43:24 PM PDT 23
Finished Nov 01 02:43:29 PM PDT 23
Peak memory 214636 kb
Host smart-88fc0bcc-7b06-4502-983d-1d1f48870ce8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77902915270881686433645428312785023008820164641061442575797066645781631203101 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 10.edn_tl_errors.77902915270881686433645428312785023008820164641061442575797066645781631203101
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.56857108716069410050510853039336369412778132944791970257096541669743664663969
Short name T10
Test name
Test status
Simulation time 155537119 ps
CPU time 2.19 seconds
Started Nov 01 02:43:23 PM PDT 23
Finished Nov 01 02:43:27 PM PDT 23
Peak memory 206548 kb
Host smart-d39fb0a1-cc6d-4c84-a2de-d216e148e5b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56857108716069410050510853039336369412778132944791970257096541669743664663969 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.56857108716069410050510853039336369412778132944791970257096541669743664663969
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.25321036650879965078807368099895024870874998282443734476420277460681674988220
Short name T131
Test name
Test status
Simulation time 51163789 ps
CPU time 1.26 seconds
Started Nov 01 02:43:54 PM PDT 23
Finished Nov 01 02:43:56 PM PDT 23
Peak memory 214784 kb
Host smart-b36f5e40-f7ef-40f5-bc57-e12631ef1585
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532103665087996507880736809989502487087499
8282443734476420277460681674988220 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.253210366508799650788073680
99895024870874998282443734476420277460681674988220
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.60308444670797813131822164827698471135272861189613023156051671231534034681944
Short name T214
Test name
Test status
Simulation time 23247569 ps
CPU time 0.9 seconds
Started Nov 01 02:43:53 PM PDT 23
Finished Nov 01 02:43:55 PM PDT 23
Peak memory 206440 kb
Host smart-c6717adf-05a8-40c6-9a58-5e64ab7bcf22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60308444670797813131822164827698471135272861189613023156051671231534034681944 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.60308444670797813131822164827698471135272861189613023156051671231534034681944
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.41713350300406948339214792176250111622471812623971952175143977494231834017737
Short name T211
Test name
Test status
Simulation time 25518366 ps
CPU time 0.82 seconds
Started Nov 01 02:43:19 PM PDT 23
Finished Nov 01 02:43:21 PM PDT 23
Peak memory 206444 kb
Host smart-57cee7bf-5e5a-4cdb-b7bc-d0f8500dda89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41713350300406948339214792176250111622471812623971952175143977494231834017737 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 11.edn_intr_test.41713350300406948339214792176250111622471812623971952175143977494231834017737
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.8011240257740695767762440165713710808496592747393378845178782488286504299774
Short name T232
Test name
Test status
Simulation time 61976116 ps
CPU time 1.29 seconds
Started Nov 01 02:43:24 PM PDT 23
Finished Nov 01 02:43:27 PM PDT 23
Peak memory 206536 kb
Host smart-183a4649-acb8-443c-861e-e9bd8b6a4ae5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8011240257740695767762440165713710808496592747393378845178782488286504299774 -
assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_outstanding.8011240257740695767762440165713710808496592747393378845178782488286504299774
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.11681130421040844486688266976062252909249571316621996218491794371967460387887
Short name T147
Test name
Test status
Simulation time 204078009 ps
CPU time 3.67 seconds
Started Nov 01 02:43:26 PM PDT 23
Finished Nov 01 02:43:32 PM PDT 23
Peak memory 214760 kb
Host smart-c2552ee8-ba33-4d02-949b-0a3bd81a056a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11681130421040844486688266976062252909249571316621996218491794371967460387887 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 11.edn_tl_errors.11681130421040844486688266976062252909249571316621996218491794371967460387887
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.30364669829648526206090329432665768626969566856540195475616139943248825114275
Short name T201
Test name
Test status
Simulation time 155537119 ps
CPU time 2.19 seconds
Started Nov 01 02:43:23 PM PDT 23
Finished Nov 01 02:43:27 PM PDT 23
Peak memory 206600 kb
Host smart-b73ea284-2e29-49b0-b143-7c86a9afe0b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30364669829648526206090329432665768626969566856540195475616139943248825114275 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.30364669829648526206090329432665768626969566856540195475616139943248825114275
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.55530786901616981230222206285713745946359072806666112520118028460673046604665
Short name T205
Test name
Test status
Simulation time 51163789 ps
CPU time 1.28 seconds
Started Nov 01 02:43:30 PM PDT 23
Finished Nov 01 02:43:33 PM PDT 23
Peak memory 214808 kb
Host smart-b2fb96b1-28eb-441d-af62-1a2b2bd5c90a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5553078690161698123022220628571374594635907
2806666112520118028460673046604665 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.555307869016169812302222062
85713745946359072806666112520118028460673046604665
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.44769951226016323760004080270084762335639646431631633308102386272592436859779
Short name T136
Test name
Test status
Simulation time 23247569 ps
CPU time 0.83 seconds
Started Nov 01 02:43:21 PM PDT 23
Finished Nov 01 02:43:23 PM PDT 23
Peak memory 206524 kb
Host smart-5600a7ff-eb6e-48f8-af54-e2804fb37f0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44769951226016323760004080270084762335639646431631633308102386272592436859779 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.44769951226016323760004080270084762335639646431631633308102386272592436859779
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.102976683688232895260685678638264797787241332904399266124126599860812709826409
Short name T177
Test name
Test status
Simulation time 25518366 ps
CPU time 0.83 seconds
Started Nov 01 02:43:20 PM PDT 23
Finished Nov 01 02:43:23 PM PDT 23
Peak memory 206496 kb
Host smart-5deb1a90-9911-4019-bc21-15305e705fdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102976683688232895260685678638264797787241332904399266124126599860812709826409 -assert nopostproc +
UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.edn_intr_test.102976683688232895260685678638264797787241332904399266124126599860812709826409
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1818036046941263883964018099096114947791094129440293010390796514660724139705
Short name T170
Test name
Test status
Simulation time 61976116 ps
CPU time 1.37 seconds
Started Nov 01 02:44:00 PM PDT 23
Finished Nov 01 02:44:03 PM PDT 23
Peak memory 206680 kb
Host smart-ce0325ed-e45c-4f44-89b3-fbe4df47658e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818036046941263883964018099096114947791094129440293010390796514660724139705 -
assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_outstanding.1818036046941263883964018099096114947791094129440293010390796514660724139705
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.64837472950771955364634409115292441876267281328302918319150614517522596214242
Short name T188
Test name
Test status
Simulation time 204078009 ps
CPU time 3.63 seconds
Started Nov 01 02:43:23 PM PDT 23
Finished Nov 01 02:43:29 PM PDT 23
Peak memory 214864 kb
Host smart-1f68c745-f95c-4e91-896c-7e29b6e556b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64837472950771955364634409115292441876267281328302918319150614517522596214242 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 12.edn_tl_errors.64837472950771955364634409115292441876267281328302918319150614517522596214242
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.60028595859872048840826812906641022198786871422420304318326786284642560023487
Short name T120
Test name
Test status
Simulation time 155537119 ps
CPU time 2.25 seconds
Started Nov 01 02:43:55 PM PDT 23
Finished Nov 01 02:43:59 PM PDT 23
Peak memory 206568 kb
Host smart-23e882a2-56ba-432d-bac9-ec43b7f02015
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60028595859872048840826812906641022198786871422420304318326786284642560023487 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.60028595859872048840826812906641022198786871422420304318326786284642560023487
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.30827105661671538273980972995531706138262376527219904335786766480172862435530
Short name T189
Test name
Test status
Simulation time 51163789 ps
CPU time 1.33 seconds
Started Nov 01 02:43:55 PM PDT 23
Finished Nov 01 02:43:58 PM PDT 23
Peak memory 214784 kb
Host smart-4231d7d3-5f88-41e5-89e6-a7c4c0a4aedb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082710566167153827398097299553170613826237
6527219904335786766480172862435530 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.308271056616715382739809729
95531706138262376527219904335786766480172862435530
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.4728180244698436228627641305935832803038734106936729845239460416817029416692
Short name T126
Test name
Test status
Simulation time 23247569 ps
CPU time 0.86 seconds
Started Nov 01 02:43:25 PM PDT 23
Finished Nov 01 02:43:28 PM PDT 23
Peak memory 206500 kb
Host smart-e06024f7-8605-4104-bcd6-73824814fefe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4728180244698436228627641305935832803038734106936729845239460416817029416692 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.4728180244698436228627641305935832803038734106936729845239460416817029416692
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.114412845916649847740349877702983892773657762583627874275018983509774920505956
Short name T115
Test name
Test status
Simulation time 25518366 ps
CPU time 0.84 seconds
Started Nov 01 02:43:25 PM PDT 23
Finished Nov 01 02:43:28 PM PDT 23
Peak memory 206448 kb
Host smart-10ab472a-c141-40ab-b99a-93a0168e2900
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114412845916649847740349877702983892773657762583627874275018983509774920505956 -assert nopostproc +
UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.edn_intr_test.114412845916649847740349877702983892773657762583627874275018983509774920505956
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.101982336082622192287268768284754163709201171227137523727318294715599061365940
Short name T202
Test name
Test status
Simulation time 61976116 ps
CPU time 1.23 seconds
Started Nov 01 02:43:54 PM PDT 23
Finished Nov 01 02:43:57 PM PDT 23
Peak memory 206684 kb
Host smart-1af79182-ccfb-43a8-a2a2-945f44b52c0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101982336082622192287268768284754163709201171227137523727318294715599061365940
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_outstanding.101982336082622192287268768284754163709201171227137523727318294715599061365940
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.101161013679689743592716676357933116975278631370542642508893942276179177036751
Short name T122
Test name
Test status
Simulation time 204078009 ps
CPU time 3.81 seconds
Started Nov 01 02:43:55 PM PDT 23
Finished Nov 01 02:44:01 PM PDT 23
Peak memory 214716 kb
Host smart-f1ad923b-a6bb-47a0-80fa-908127e4b8c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101161013679689743592716676357933116975278631370542642508893942276179177036751 -assert nopostproc +
UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.edn_tl_errors.101161013679689743592716676357933116975278631370542642508893942276179177036751
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.107366767159467647897919105524493179551070522863470796129872354721592725825473
Short name T118
Test name
Test status
Simulation time 155537119 ps
CPU time 2.23 seconds
Started Nov 01 02:43:29 PM PDT 23
Finished Nov 01 02:43:33 PM PDT 23
Peak memory 206608 kb
Host smart-a7b9e6c3-b2c3-4ee0-89ec-69495ab0b2e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107366767159467647897919105524493179551070522863470796129872354721592725825473 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.107366767159467647897919105524493179551070522863470796129872354721592725825473
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.73942075251619004956135850341501367278706849621208865473846419519483409523252
Short name T124
Test name
Test status
Simulation time 51163789 ps
CPU time 1.33 seconds
Started Nov 01 02:44:03 PM PDT 23
Finished Nov 01 02:44:07 PM PDT 23
Peak memory 214764 kb
Host smart-d837cc38-9f35-4c11-812e-d5cba47b3140
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7394207525161900495613585034150136727870684
9621208865473846419519483409523252 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.739420752516190049561358503
41501367278706849621208865473846419519483409523252
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.2420580515862912117696521113951324417640729745459481311323686688991375727096
Short name T225
Test name
Test status
Simulation time 23247569 ps
CPU time 0.83 seconds
Started Nov 01 02:44:05 PM PDT 23
Finished Nov 01 02:44:09 PM PDT 23
Peak memory 206544 kb
Host smart-70ecdb41-054b-4601-b52e-4efbbe6449c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420580515862912117696521113951324417640729745459481311323686688991375727096 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.2420580515862912117696521113951324417640729745459481311323686688991375727096
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.24875681382581061977268982030080316909244349903325408634040277662011638897485
Short name T102
Test name
Test status
Simulation time 25518366 ps
CPU time 0.84 seconds
Started Nov 01 02:44:01 PM PDT 23
Finished Nov 01 02:44:05 PM PDT 23
Peak memory 206396 kb
Host smart-b5d3d750-a273-43e5-9ece-06c50253e5e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24875681382581061977268982030080316909244349903325408634040277662011638897485 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 14.edn_intr_test.24875681382581061977268982030080316909244349903325408634040277662011638897485
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.95787254604024580676836522333547309432474524823657044150938542885162608592772
Short name T183
Test name
Test status
Simulation time 61976116 ps
CPU time 1.32 seconds
Started Nov 01 02:44:04 PM PDT 23
Finished Nov 01 02:44:09 PM PDT 23
Peak memory 206472 kb
Host smart-59f99a6f-f2ac-4f18-bde7-3e0fbb4267e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95787254604024580676836522333547309432474524823657044150938542885162608592772
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_outstanding.95787254604024580676836522333547309432474524823657044150938542885162608592772
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.2202415080243084534352501649140273621454754285338479726120115555556170063955
Short name T200
Test name
Test status
Simulation time 204078009 ps
CPU time 3.68 seconds
Started Nov 01 02:43:59 PM PDT 23
Finished Nov 01 02:44:03 PM PDT 23
Peak memory 214676 kb
Host smart-239f92df-6976-4c01-a413-3341f092fe50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202415080243084534352501649140273621454754285338479726120115555556170063955 -assert nopostproc +UV
M_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.edn_tl_errors.2202415080243084534352501649140273621454754285338479726120115555556170063955
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.100799115358858132441093892895875981798600573530060596589866392699541170974770
Short name T133
Test name
Test status
Simulation time 155537119 ps
CPU time 2.21 seconds
Started Nov 01 02:44:00 PM PDT 23
Finished Nov 01 02:44:03 PM PDT 23
Peak memory 206544 kb
Host smart-303b5c72-3cdc-44c6-b103-e3183174387c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100799115358858132441093892895875981798600573530060596589866392699541170974770 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.100799115358858132441093892895875981798600573530060596589866392699541170974770
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.99754332055645955253525098854415813698246739713154477754123197125946239384459
Short name T108
Test name
Test status
Simulation time 51163789 ps
CPU time 1.31 seconds
Started Nov 01 02:44:05 PM PDT 23
Finished Nov 01 02:44:09 PM PDT 23
Peak memory 214872 kb
Host smart-0e05597c-eac0-4209-8801-309f34088424
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9975433205564595525352509885441581369824673
9713154477754123197125946239384459 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.997543320556459552535250988
54415813698246739713154477754123197125946239384459
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.15416596429542494087980455744368672260908955457226782391854973078569325670906
Short name T181
Test name
Test status
Simulation time 23247569 ps
CPU time 0.88 seconds
Started Nov 01 02:44:01 PM PDT 23
Finished Nov 01 02:44:05 PM PDT 23
Peak memory 206584 kb
Host smart-9ca13e25-e7f5-4c79-894a-015d082e002e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15416596429542494087980455744368672260908955457226782391854973078569325670906 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.15416596429542494087980455744368672260908955457226782391854973078569325670906
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.105321708963921423507968422018222748778339069715143000905376513433294023358076
Short name T235
Test name
Test status
Simulation time 25518366 ps
CPU time 0.88 seconds
Started Nov 01 02:44:04 PM PDT 23
Finished Nov 01 02:44:08 PM PDT 23
Peak memory 206440 kb
Host smart-2b3b9498-a3aa-4197-8e19-fcc279b1cd7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105321708963921423507968422018222748778339069715143000905376513433294023358076 -assert nopostproc +
UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.edn_intr_test.105321708963921423507968422018222748778339069715143000905376513433294023358076
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.112911712598517569438124604264090471232835861279473441897957038550840632473822
Short name T75
Test name
Test status
Simulation time 61976116 ps
CPU time 1.33 seconds
Started Nov 01 02:44:06 PM PDT 23
Finished Nov 01 02:44:11 PM PDT 23
Peak memory 206632 kb
Host smart-f341e35a-83d9-4ab0-97d4-46fe0fa330df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112911712598517569438124604264090471232835861279473441897957038550840632473822
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_outstanding.112911712598517569438124604264090471232835861279473441897957038550840632473822
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.108648732631046583795251531456674679367795986470302929092292457962166002471578
Short name T193
Test name
Test status
Simulation time 204078009 ps
CPU time 3.73 seconds
Started Nov 01 02:44:04 PM PDT 23
Finished Nov 01 02:44:10 PM PDT 23
Peak memory 214756 kb
Host smart-e27854a1-d167-4986-aafb-7073c20077f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108648732631046583795251531456674679367795986470302929092292457962166002471578 -assert nopostproc +
UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.edn_tl_errors.108648732631046583795251531456674679367795986470302929092292457962166002471578
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.28116932036420633236269527922209777267923286806302120813478519705879888823872
Short name T176
Test name
Test status
Simulation time 51163789 ps
CPU time 1.38 seconds
Started Nov 01 02:44:06 PM PDT 23
Finished Nov 01 02:44:11 PM PDT 23
Peak memory 214824 kb
Host smart-9fd12f8a-363a-4e7b-a8b6-ba66961d2831
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811693203642063323626952792220977726792328
6806302120813478519705879888823872 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.281169320364206332362695279
22209777267923286806302120813478519705879888823872
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.99380462742249727623102512717359061069255671020386266964900932210586797288245
Short name T178
Test name
Test status
Simulation time 23247569 ps
CPU time 0.87 seconds
Started Nov 01 02:44:05 PM PDT 23
Finished Nov 01 02:44:09 PM PDT 23
Peak memory 206576 kb
Host smart-fc962d77-37f1-4a21-93fe-f8ca42f0db18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99380462742249727623102512717359061069255671020386266964900932210586797288245 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.99380462742249727623102512717359061069255671020386266964900932210586797288245
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.104032783652274317608501717521891060063763051876003416804101628158266267891083
Short name T77
Test name
Test status
Simulation time 25518366 ps
CPU time 0.9 seconds
Started Nov 01 02:44:08 PM PDT 23
Finished Nov 01 02:44:13 PM PDT 23
Peak memory 206348 kb
Host smart-a9217ec1-ecfd-440f-b560-4201300294f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104032783652274317608501717521891060063763051876003416804101628158266267891083 -assert nopostproc +
UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.edn_intr_test.104032783652274317608501717521891060063763051876003416804101628158266267891083
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.91504020534749565003164491204955670796762666036257584288532004376389400314242
Short name T236
Test name
Test status
Simulation time 61976116 ps
CPU time 1.29 seconds
Started Nov 01 02:44:06 PM PDT 23
Finished Nov 01 02:44:11 PM PDT 23
Peak memory 206536 kb
Host smart-b76ac28a-f2a3-4bd3-b96f-e22b3c805b75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91504020534749565003164491204955670796762666036257584288532004376389400314242
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_outstanding.91504020534749565003164491204955670796762666036257584288532004376389400314242
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.106263286623253964869445845043732960992085081319950694478052659756941124993622
Short name T117
Test name
Test status
Simulation time 204078009 ps
CPU time 3.86 seconds
Started Nov 01 02:44:04 PM PDT 23
Finished Nov 01 02:44:11 PM PDT 23
Peak memory 214700 kb
Host smart-2d5c3021-2f1c-4d67-84bb-23e38ff54fa9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106263286623253964869445845043732960992085081319950694478052659756941124993622 -assert nopostproc +
UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.edn_tl_errors.106263286623253964869445845043732960992085081319950694478052659756941124993622
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.67629430544615427681343004166525698966163874269247552294017525238840650589458
Short name T197
Test name
Test status
Simulation time 155537119 ps
CPU time 2.16 seconds
Started Nov 01 02:44:04 PM PDT 23
Finished Nov 01 02:44:10 PM PDT 23
Peak memory 206616 kb
Host smart-f3359c3a-28dc-4b9f-ac13-db6b0c12223f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67629430544615427681343004166525698966163874269247552294017525238840650589458 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.67629430544615427681343004166525698966163874269247552294017525238840650589458
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.14877606868056976249611912273907063509101113487223259431423519926184595573034
Short name T228
Test name
Test status
Simulation time 51163789 ps
CPU time 1.3 seconds
Started Nov 01 02:44:06 PM PDT 23
Finished Nov 01 02:44:11 PM PDT 23
Peak memory 214812 kb
Host smart-834627d1-4c77-4509-be15-ff4ae4572136
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487760686805697624961191227390706350910111
3487223259431423519926184595573034 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.148776068680569762496119122
73907063509101113487223259431423519926184595573034
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.92179019558821160516486943839692167251092477210716494477831087594186000837722
Short name T121
Test name
Test status
Simulation time 23247569 ps
CPU time 0.86 seconds
Started Nov 01 02:44:08 PM PDT 23
Finished Nov 01 02:44:12 PM PDT 23
Peak memory 206552 kb
Host smart-75cab921-09db-4575-9cf8-ec9d1e738c48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92179019558821160516486943839692167251092477210716494477831087594186000837722 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.92179019558821160516486943839692167251092477210716494477831087594186000837722
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.51213327019422842264324342761196786843987286406701832247682720267149429733336
Short name T180
Test name
Test status
Simulation time 25518366 ps
CPU time 0.84 seconds
Started Nov 01 02:44:07 PM PDT 23
Finished Nov 01 02:44:12 PM PDT 23
Peak memory 206272 kb
Host smart-2c43f1bb-a324-4522-aa22-9cb96a27e0e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51213327019422842264324342761196786843987286406701832247682720267149429733336 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 17.edn_intr_test.51213327019422842264324342761196786843987286406701832247682720267149429733336
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.254986869066227567900060763254291872634257273925496761142925686413167240170
Short name T226
Test name
Test status
Simulation time 61976116 ps
CPU time 1.34 seconds
Started Nov 01 02:44:06 PM PDT 23
Finished Nov 01 02:44:11 PM PDT 23
Peak memory 206524 kb
Host smart-7b705947-2c5d-4377-8ec6-0649d8e399f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254986869066227567900060763254291872634257273925496761142925686413167240170 -a
ssert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_outstanding.254986869066227567900060763254291872634257273925496761142925686413167240170
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.71042829601354014069412485509888199948155772622178223620544202122981705270078
Short name T7
Test name
Test status
Simulation time 204078009 ps
CPU time 3.77 seconds
Started Nov 01 02:44:09 PM PDT 23
Finished Nov 01 02:44:16 PM PDT 23
Peak memory 214744 kb
Host smart-0a586808-df84-450a-bfa7-fcb3ef107067
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71042829601354014069412485509888199948155772622178223620544202122981705270078 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 17.edn_tl_errors.71042829601354014069412485509888199948155772622178223620544202122981705270078
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.70311153163130445410338056791869941011368427225045465066300658389211423945983
Short name T215
Test name
Test status
Simulation time 155537119 ps
CPU time 2.24 seconds
Started Nov 01 02:44:07 PM PDT 23
Finished Nov 01 02:44:14 PM PDT 23
Peak memory 206400 kb
Host smart-71c83a97-504c-446a-b009-ad5492e782fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70311153163130445410338056791869941011368427225045465066300658389211423945983 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.70311153163130445410338056791869941011368427225045465066300658389211423945983
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.16384951171823782933950650008346261086377673428265086520691975585840325472318
Short name T128
Test name
Test status
Simulation time 51163789 ps
CPU time 1.26 seconds
Started Nov 01 02:44:08 PM PDT 23
Finished Nov 01 02:44:13 PM PDT 23
Peak memory 214716 kb
Host smart-34cf886e-1338-4bb0-a100-64eff4dc6316
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638495117182378293395065000834626108637767
3428265086520691975585840325472318 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.163849511718237829339506500
08346261086377673428265086520691975585840325472318
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.26569777058514966469223945213765466285721057772340598294486759153374940649495
Short name T186
Test name
Test status
Simulation time 23247569 ps
CPU time 0.88 seconds
Started Nov 01 02:44:08 PM PDT 23
Finished Nov 01 02:44:12 PM PDT 23
Peak memory 206552 kb
Host smart-d623a8a2-174e-4332-a0ac-14177e387328
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26569777058514966469223945213765466285721057772340598294486759153374940649495 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.26569777058514966469223945213765466285721057772340598294486759153374940649495
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.1069570822237241728789327206673821752078905713456600912433037566473530089017
Short name T155
Test name
Test status
Simulation time 25518366 ps
CPU time 0.88 seconds
Started Nov 01 02:44:08 PM PDT 23
Finished Nov 01 02:44:13 PM PDT 23
Peak memory 206476 kb
Host smart-b5cc4d6c-281d-4f4e-bbfe-559cf86668a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069570822237241728789327206673821752078905713456600912433037566473530089017 -assert nopostproc +UV
M_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.edn_intr_test.1069570822237241728789327206673821752078905713456600912433037566473530089017
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.54353578127612889171228631967078254824691371434995386457550001094829404877753
Short name T69
Test name
Test status
Simulation time 61976116 ps
CPU time 1.31 seconds
Started Nov 01 02:44:01 PM PDT 23
Finished Nov 01 02:44:04 PM PDT 23
Peak memory 206892 kb
Host smart-77977392-a7ff-4f43-8e90-ccc98e361418
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54353578127612889171228631967078254824691371434995386457550001094829404877753
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_outstanding.54353578127612889171228631967078254824691371434995386457550001094829404877753
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.24255393708896661434500198565756682725446325769020089103493626750118838491410
Short name T130
Test name
Test status
Simulation time 204078009 ps
CPU time 3.68 seconds
Started Nov 01 02:44:04 PM PDT 23
Finished Nov 01 02:44:10 PM PDT 23
Peak memory 214780 kb
Host smart-17281567-6e5c-479e-af95-e365e3409558
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24255393708896661434500198565756682725446325769020089103493626750118838491410 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 18.edn_tl_errors.24255393708896661434500198565756682725446325769020089103493626750118838491410
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.18021001862018158538180800606548531483242565201380349137138430568919033947534
Short name T141
Test name
Test status
Simulation time 155537119 ps
CPU time 2.19 seconds
Started Nov 01 02:44:08 PM PDT 23
Finished Nov 01 02:44:14 PM PDT 23
Peak memory 206604 kb
Host smart-3180f51e-21ef-4610-b12f-1cd9cd3bab12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18021001862018158538180800606548531483242565201380349137138430568919033947534 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.18021001862018158538180800606548531483242565201380349137138430568919033947534
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.51838560074717045812227649292951549233559255564059092151745920515757443581685
Short name T231
Test name
Test status
Simulation time 51163789 ps
CPU time 1.27 seconds
Started Nov 01 02:43:23 PM PDT 23
Finished Nov 01 02:43:26 PM PDT 23
Peak memory 214724 kb
Host smart-8ce40182-fe65-421c-86b0-85398a82c372
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5183856007471704581222764929295154923355925
5564059092151745920515757443581685 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.518385600747170458122276492
92951549233559255564059092151745920515757443581685
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.31361769407537934455765889282292306338156135456834915186657939310472927491931
Short name T182
Test name
Test status
Simulation time 23247569 ps
CPU time 0.86 seconds
Started Nov 01 02:43:27 PM PDT 23
Finished Nov 01 02:43:30 PM PDT 23
Peak memory 206556 kb
Host smart-98f16b32-b43d-4450-96f8-39f611442deb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31361769407537934455765889282292306338156135456834915186657939310472927491931 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.31361769407537934455765889282292306338156135456834915186657939310472927491931
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.30722813668510764916696229431352255784428599258104489494090612848016425072589
Short name T210
Test name
Test status
Simulation time 25518366 ps
CPU time 0.9 seconds
Started Nov 01 02:44:04 PM PDT 23
Finished Nov 01 02:44:09 PM PDT 23
Peak memory 206484 kb
Host smart-7be7c13e-e3dc-428a-aa7e-46d4b73d48f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30722813668510764916696229431352255784428599258104489494090612848016425072589 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 19.edn_intr_test.30722813668510764916696229431352255784428599258104489494090612848016425072589
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.115099286662064331661410827697766055430995262325531888091473365590199449738857
Short name T80
Test name
Test status
Simulation time 61976116 ps
CPU time 1.31 seconds
Started Nov 01 02:43:22 PM PDT 23
Finished Nov 01 02:43:26 PM PDT 23
Peak memory 206708 kb
Host smart-523aced1-0b4c-42f7-9ce2-fb6cf94a391d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115099286662064331661410827697766055430995262325531888091473365590199449738857
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_outstanding.115099286662064331661410827697766055430995262325531888091473365590199449738857
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.104631324428019174705199537701174406416958737871613975884073039816948973893892
Short name T143
Test name
Test status
Simulation time 204078009 ps
CPU time 3.63 seconds
Started Nov 01 02:44:09 PM PDT 23
Finished Nov 01 02:44:16 PM PDT 23
Peak memory 214688 kb
Host smart-4a6d4970-846e-4070-9cc0-7bba3af1926b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104631324428019174705199537701174406416958737871613975884073039816948973893892 -assert nopostproc +
UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.edn_tl_errors.104631324428019174705199537701174406416958737871613975884073039816948973893892
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.39344548835601074001363307542386239321236831292135912143896247513839854358822
Short name T203
Test name
Test status
Simulation time 155537119 ps
CPU time 2.26 seconds
Started Nov 01 02:44:02 PM PDT 23
Finished Nov 01 02:44:08 PM PDT 23
Peak memory 206640 kb
Host smart-c660c077-2944-4e66-ad0f-fe8b52b13142
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39344548835601074001363307542386239321236831292135912143896247513839854358822 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.39344548835601074001363307542386239321236831292135912143896247513839854358822
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.28753937441215884374877088755616712637621747469303925727634744095056107080915
Short name T157
Test name
Test status
Simulation time 59184494 ps
CPU time 1.34 seconds
Started Nov 01 02:42:39 PM PDT 23
Finished Nov 01 02:42:47 PM PDT 23
Peak memory 206568 kb
Host smart-fb3f360c-ddc4-4c8d-ba20-63b54fb9ff02
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28753937441215884374877088755616712637621747469303925727634744095056107080915 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.28753937441215884374877088755616712637621747469303925727634744095056107080915
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.38124414966567074043367419660833341435359626904887838870989400140333981185418
Short name T216
Test name
Test status
Simulation time 351971476 ps
CPU time 5.2 seconds
Started Nov 01 02:42:41 PM PDT 23
Finished Nov 01 02:42:52 PM PDT 23
Peak memory 206564 kb
Host smart-ec83ac15-cdbd-4006-a56d-0b1dc80d9e9b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38124414966567074043367419660833341435359626904887838870989400140333981185418 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.38124414966567074043367419660833341435359626904887838870989400140333981185418
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.22531018265460873616161044870693038123695758962461671795355053173352637099268
Short name T148
Test name
Test status
Simulation time 26726680 ps
CPU time 0.87 seconds
Started Nov 01 02:42:40 PM PDT 23
Finished Nov 01 02:42:47 PM PDT 23
Peak memory 206564 kb
Host smart-ad987d25-2bb8-4c8d-a83a-a8f4e11eaf83
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22531018265460873616161044870693038123695758962461671795355053173352637099268 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.22531018265460873616161044870693038123695758962461671795355053173352637099268
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.87685877629546552355217180866906977378315539082681272008418647967394874935556
Short name T165
Test name
Test status
Simulation time 51163789 ps
CPU time 1.29 seconds
Started Nov 01 02:42:41 PM PDT 23
Finished Nov 01 02:42:48 PM PDT 23
Peak memory 214808 kb
Host smart-02a0a445-9f85-475f-ac88-5fc1b12a0db8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8768587762954655235521718086690697737831553
9082681272008418647967394874935556 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.8768587762954655235521718086
6906977378315539082681272008418647967394874935556
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.95493388602911626703540454250589139720671425852895355144605157892285849573507
Short name T218
Test name
Test status
Simulation time 23247569 ps
CPU time 0.84 seconds
Started Nov 01 02:42:41 PM PDT 23
Finished Nov 01 02:42:47 PM PDT 23
Peak memory 206548 kb
Host smart-7bc85ed3-4899-4274-8869-cfc56353e6ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95493388602911626703540454250589139720671425852895355144605157892285849573507 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.95493388602911626703540454250589139720671425852895355144605157892285849573507
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.99939014008908334464970260196183777130439587667991567357749392041030181337466
Short name T219
Test name
Test status
Simulation time 25518366 ps
CPU time 0.84 seconds
Started Nov 01 02:42:40 PM PDT 23
Finished Nov 01 02:42:47 PM PDT 23
Peak memory 206492 kb
Host smart-57325eb3-67ac-422a-bd2a-e7b320cc6772
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99939014008908334464970260196183777130439587667991567357749392041030181337466 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 2.edn_intr_test.99939014008908334464970260196183777130439587667991567357749392041030181337466
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.112028912724689867583720823568787837619714639511725796426956746130626079744833
Short name T230
Test name
Test status
Simulation time 61976116 ps
CPU time 1.23 seconds
Started Nov 01 02:42:44 PM PDT 23
Finished Nov 01 02:42:48 PM PDT 23
Peak memory 206440 kb
Host smart-7433854e-5fe6-4dee-8961-91b208741b93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112028912724689867583720823568787837619714639511725796426956746130626079744833
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_outstanding.112028912724689867583720823568787837619714639511725796426956746130626079744833
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.90791353928019404281419097660458281069829059921799289678743816936817223187714
Short name T171
Test name
Test status
Simulation time 204078009 ps
CPU time 3.87 seconds
Started Nov 01 02:42:40 PM PDT 23
Finished Nov 01 02:42:50 PM PDT 23
Peak memory 214760 kb
Host smart-23c28f6f-f112-4123-b56f-6f5f4a8c2039
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90791353928019404281419097660458281069829059921799289678743816936817223187714 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 2.edn_tl_errors.90791353928019404281419097660458281069829059921799289678743816936817223187714
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.46126464830463089962793000315567620828885179170454534412288865216439614951825
Short name T187
Test name
Test status
Simulation time 155537119 ps
CPU time 2.34 seconds
Started Nov 01 02:42:41 PM PDT 23
Finished Nov 01 02:42:49 PM PDT 23
Peak memory 206612 kb
Host smart-0a4da914-d693-4da7-a148-b5482944ff9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46126464830463089962793000315567620828885179170454534412288865216439614951825 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.46126464830463089962793000315567620828885179170454534412288865216439614951825
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.109348040722525586833087783805955309489757788131657605219023304223850360330438
Short name T229
Test name
Test status
Simulation time 25518366 ps
CPU time 0.83 seconds
Started Nov 01 02:43:23 PM PDT 23
Finished Nov 01 02:43:26 PM PDT 23
Peak memory 206396 kb
Host smart-1d371a8d-aad7-469b-a04a-3ae99da405bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109348040722525586833087783805955309489757788131657605219023304223850360330438 -assert nopostproc +
UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 20.edn_intr_test.109348040722525586833087783805955309489757788131657605219023304223850360330438
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.99995902487843662382591561828044993444881066659919836477269092434401149291291
Short name T149
Test name
Test status
Simulation time 25518366 ps
CPU time 0.84 seconds
Started Nov 01 02:43:28 PM PDT 23
Finished Nov 01 02:43:30 PM PDT 23
Peak memory 206516 kb
Host smart-0d02d98c-bf3b-4d09-8829-b23d42a3baf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99995902487843662382591561828044993444881066659919836477269092434401149291291 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 21.edn_intr_test.99995902487843662382591561828044993444881066659919836477269092434401149291291
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.22942417431847283700103197840635094378648103796313243875625406874998251799868
Short name T162
Test name
Test status
Simulation time 25518366 ps
CPU time 0.83 seconds
Started Nov 01 02:43:22 PM PDT 23
Finished Nov 01 02:43:24 PM PDT 23
Peak memory 206472 kb
Host smart-88751beb-90ba-47d7-b2b7-b33ccfcbe38c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22942417431847283700103197840635094378648103796313243875625406874998251799868 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 22.edn_intr_test.22942417431847283700103197840635094378648103796313243875625406874998251799868
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.9204970130400486560805917818263233223496645495995474619703388597022761315637
Short name T104
Test name
Test status
Simulation time 25518366 ps
CPU time 0.84 seconds
Started Nov 01 02:43:55 PM PDT 23
Finished Nov 01 02:43:58 PM PDT 23
Peak memory 206440 kb
Host smart-9d7a6a54-f2f4-4f3c-adf4-bd0c1481b042
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9204970130400486560805917818263233223496645495995474619703388597022761315637 -assert nopostproc +UV
M_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 23.edn_intr_test.9204970130400486560805917818263233223496645495995474619703388597022761315637
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.14070127361391197279579986599240367797513538872078005058176135932072423296470
Short name T139
Test name
Test status
Simulation time 25518366 ps
CPU time 0.86 seconds
Started Nov 01 02:43:55 PM PDT 23
Finished Nov 01 02:43:57 PM PDT 23
Peak memory 206488 kb
Host smart-fd464163-d992-4255-a59a-feea4be4e670
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14070127361391197279579986599240367797513538872078005058176135932072423296470 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 24.edn_intr_test.14070127361391197279579986599240367797513538872078005058176135932072423296470
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.70937412564506948205609191383722184993125861968975602791033385865724961199736
Short name T233
Test name
Test status
Simulation time 25518366 ps
CPU time 0.85 seconds
Started Nov 01 02:43:31 PM PDT 23
Finished Nov 01 02:43:33 PM PDT 23
Peak memory 206560 kb
Host smart-d89e2f98-7d56-44a9-86f3-c53798d8a55a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70937412564506948205609191383722184993125861968975602791033385865724961199736 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 25.edn_intr_test.70937412564506948205609191383722184993125861968975602791033385865724961199736
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.14435049486692933730956145437055647432204951327350716639510848206268008278058
Short name T98
Test name
Test status
Simulation time 25518366 ps
CPU time 0.86 seconds
Started Nov 01 02:43:54 PM PDT 23
Finished Nov 01 02:43:57 PM PDT 23
Peak memory 206440 kb
Host smart-5e45f0ed-cad2-42c5-ae73-947288abb7d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14435049486692933730956145437055647432204951327350716639510848206268008278058 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 26.edn_intr_test.14435049486692933730956145437055647432204951327350716639510848206268008278058
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.76000917484658756968738743952781478019558780893688140102809775609723539479931
Short name T101
Test name
Test status
Simulation time 25518366 ps
CPU time 0.83 seconds
Started Nov 01 02:43:52 PM PDT 23
Finished Nov 01 02:43:54 PM PDT 23
Peak memory 206472 kb
Host smart-acfa6aa3-2079-4779-b90a-742f0d679276
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76000917484658756968738743952781478019558780893688140102809775609723539479931 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 27.edn_intr_test.76000917484658756968738743952781478019558780893688140102809775609723539479931
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.99405138046989787396226247363634889750074829920024370351012194184139729185368
Short name T198
Test name
Test status
Simulation time 25518366 ps
CPU time 0.83 seconds
Started Nov 01 02:43:23 PM PDT 23
Finished Nov 01 02:43:25 PM PDT 23
Peak memory 206436 kb
Host smart-6602205c-1e72-4066-ab7e-451ae7588265
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99405138046989787396226247363634889750074829920024370351012194184139729185368 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 28.edn_intr_test.99405138046989787396226247363634889750074829920024370351012194184139729185368
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.58830807768724565444819002551004261542974563823727332442595050524136710152201
Short name T129
Test name
Test status
Simulation time 25518366 ps
CPU time 0.88 seconds
Started Nov 01 02:43:29 PM PDT 23
Finished Nov 01 02:43:32 PM PDT 23
Peak memory 206488 kb
Host smart-29a1ece2-b12d-49be-81bf-c8859a5e3388
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58830807768724565444819002551004261542974563823727332442595050524136710152201 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 29.edn_intr_test.58830807768724565444819002551004261542974563823727332442595050524136710152201
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.86844087066547994827682693779192161863442366109938641830630582043121147194662
Short name T213
Test name
Test status
Simulation time 59184494 ps
CPU time 1.3 seconds
Started Nov 01 02:42:42 PM PDT 23
Finished Nov 01 02:42:48 PM PDT 23
Peak memory 206332 kb
Host smart-e4d04e9f-ecb1-45f7-8bb9-c7b8c5991b96
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86844087066547994827682693779192161863442366109938641830630582043121147194662 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.86844087066547994827682693779192161863442366109938641830630582043121147194662
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.108146045043427698487486278196655876145046875276145924575181928260198035843857
Short name T222
Test name
Test status
Simulation time 351971476 ps
CPU time 4.8 seconds
Started Nov 01 02:42:43 PM PDT 23
Finished Nov 01 02:42:52 PM PDT 23
Peak memory 206332 kb
Host smart-334df351-6f13-497c-863d-0280b62f774a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108146045043427698487486278196655876145046875276145924575181928260198035843857 -assert nop
ostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.108146045043427698487486278196655876145046875276145924575181928260198035843857
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.110908722839102089408366613240045523984828595241527531240643580664098150976841
Short name T71
Test name
Test status
Simulation time 26726680 ps
CPU time 0.87 seconds
Started Nov 01 02:42:44 PM PDT 23
Finished Nov 01 02:42:48 PM PDT 23
Peak memory 206376 kb
Host smart-283a0c93-ca21-428f-ab31-b27e4d689e04
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110908722839102089408366613240045523984828595241527531240643580664098150976841 -assert nop
ostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.110908722839102089408366613240045523984828595241527531240643580664098150976841
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.45408101053962651303251293293876987404411574698459078095436459875671643905177
Short name T105
Test name
Test status
Simulation time 51163789 ps
CPU time 1.3 seconds
Started Nov 01 02:43:25 PM PDT 23
Finished Nov 01 02:43:28 PM PDT 23
Peak memory 214824 kb
Host smart-d6637034-ceae-4482-82f4-a2f3b8282914
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4540810105396265130325129329387698740441157
4698459078095436459875671643905177 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.4540810105396265130325129329
3876987404411574698459078095436459875671643905177
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.54500476692249341840359927445876483148642521973133369316975056413256652647110
Short name T196
Test name
Test status
Simulation time 23247569 ps
CPU time 0.82 seconds
Started Nov 01 02:42:44 PM PDT 23
Finished Nov 01 02:42:48 PM PDT 23
Peak memory 206360 kb
Host smart-ebe472d8-edd4-4043-b4a7-3da34ed79820
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54500476692249341840359927445876483148642521973133369316975056413256652647110 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.54500476692249341840359927445876483148642521973133369316975056413256652647110
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.21669273984925167680181757231277897214098341554808721656703821541233141465843
Short name T114
Test name
Test status
Simulation time 25518366 ps
CPU time 0.81 seconds
Started Nov 01 02:42:42 PM PDT 23
Finished Nov 01 02:42:48 PM PDT 23
Peak memory 206264 kb
Host smart-c93cf169-a085-4338-be8e-699466d37e09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21669273984925167680181757231277897214098341554808721656703821541233141465843 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 3.edn_intr_test.21669273984925167680181757231277897214098341554808721656703821541233141465843
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.20600013242010884987341680125472694760723711529897230724285339799406643828405
Short name T83
Test name
Test status
Simulation time 61976116 ps
CPU time 1.31 seconds
Started Nov 01 02:43:40 PM PDT 23
Finished Nov 01 02:43:42 PM PDT 23
Peak memory 206624 kb
Host smart-00a66e71-568b-40a3-a9e0-3ca491f4d116
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20600013242010884987341680125472694760723711529897230724285339799406643828405
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_outstanding.20600013242010884987341680125472694760723711529897230724285339799406643828405
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.82194412658222447688935478249120782008665517304996944516672333284966217996960
Short name T179
Test name
Test status
Simulation time 204078009 ps
CPU time 3.53 seconds
Started Nov 01 02:42:44 PM PDT 23
Finished Nov 01 02:42:51 PM PDT 23
Peak memory 214576 kb
Host smart-013f65d5-9311-4d80-b299-582346762750
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82194412658222447688935478249120782008665517304996944516672333284966217996960 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 3.edn_tl_errors.82194412658222447688935478249120782008665517304996944516672333284966217996960
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.20728819555566465764611911483859489775941484014666410636406374525744925998902
Short name T9
Test name
Test status
Simulation time 155537119 ps
CPU time 2.16 seconds
Started Nov 01 02:42:41 PM PDT 23
Finished Nov 01 02:42:49 PM PDT 23
Peak memory 206580 kb
Host smart-66a1627b-a34b-4462-b64d-9ad3da622241
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20728819555566465764611911483859489775941484014666410636406374525744925998902 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.20728819555566465764611911483859489775941484014666410636406374525744925998902
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.68969146697724253163783371067708990214370493999449655146435648901903735044945
Short name T140
Test name
Test status
Simulation time 25518366 ps
CPU time 0.83 seconds
Started Nov 01 02:43:31 PM PDT 23
Finished Nov 01 02:43:33 PM PDT 23
Peak memory 206448 kb
Host smart-352502c4-268e-4aba-9467-78a30b31a171
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68969146697724253163783371067708990214370493999449655146435648901903735044945 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 30.edn_intr_test.68969146697724253163783371067708990214370493999449655146435648901903735044945
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.115613917072017385570869004100397714883908818540189225705322708146064880177177
Short name T109
Test name
Test status
Simulation time 25518366 ps
CPU time 0.84 seconds
Started Nov 01 02:43:27 PM PDT 23
Finished Nov 01 02:43:30 PM PDT 23
Peak memory 206512 kb
Host smart-2c735ef1-c035-440b-b486-db452b88e5cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115613917072017385570869004100397714883908818540189225705322708146064880177177 -assert nopostproc +
UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 31.edn_intr_test.115613917072017385570869004100397714883908818540189225705322708146064880177177
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.56768480407885527266683936395806692711073834931720320136202509307263826057334
Short name T212
Test name
Test status
Simulation time 25518366 ps
CPU time 0.83 seconds
Started Nov 01 02:44:00 PM PDT 23
Finished Nov 01 02:44:01 PM PDT 23
Peak memory 206412 kb
Host smart-89f29245-f67e-42b4-9f7b-6156adfff1b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56768480407885527266683936395806692711073834931720320136202509307263826057334 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 32.edn_intr_test.56768480407885527266683936395806692711073834931720320136202509307263826057334
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.71961880922135129032241175943090685366861760909730590015432700043587173571117
Short name T185
Test name
Test status
Simulation time 25518366 ps
CPU time 0.84 seconds
Started Nov 01 02:44:03 PM PDT 23
Finished Nov 01 02:44:07 PM PDT 23
Peak memory 206492 kb
Host smart-4ec6d1d9-ec57-4963-a2fc-12617c6eaf98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71961880922135129032241175943090685366861760909730590015432700043587173571117 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 33.edn_intr_test.71961880922135129032241175943090685366861760909730590015432700043587173571117
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.65657242517883106229459097276511703163416379500774840270289340744882351985839
Short name T163
Test name
Test status
Simulation time 25518366 ps
CPU time 0.82 seconds
Started Nov 01 02:43:30 PM PDT 23
Finished Nov 01 02:43:33 PM PDT 23
Peak memory 206312 kb
Host smart-6f4f78d7-eb96-4fe2-99e8-4a4ea7658e5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65657242517883106229459097276511703163416379500774840270289340744882351985839 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 34.edn_intr_test.65657242517883106229459097276511703163416379500774840270289340744882351985839
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.91280554922669644809016851912827432246416485585061787595642209671532621344826
Short name T172
Test name
Test status
Simulation time 25518366 ps
CPU time 0.83 seconds
Started Nov 01 02:44:00 PM PDT 23
Finished Nov 01 02:44:02 PM PDT 23
Peak memory 206516 kb
Host smart-d11a18b3-c23d-4cba-b60d-b7859c9620f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91280554922669644809016851912827432246416485585061787595642209671532621344826 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 35.edn_intr_test.91280554922669644809016851912827432246416485585061787595642209671532621344826
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.45229306987485117362582788430176924291436842179635898618683031924688339880903
Short name T192
Test name
Test status
Simulation time 25518366 ps
CPU time 0.82 seconds
Started Nov 01 02:44:01 PM PDT 23
Finished Nov 01 02:44:03 PM PDT 23
Peak memory 206512 kb
Host smart-59b64588-079b-4df5-b963-3274c5db843a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45229306987485117362582788430176924291436842179635898618683031924688339880903 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 36.edn_intr_test.45229306987485117362582788430176924291436842179635898618683031924688339880903
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.5661974973506887457394139590337078465024023245774802508045099427118431105200
Short name T134
Test name
Test status
Simulation time 25518366 ps
CPU time 0.83 seconds
Started Nov 01 02:44:01 PM PDT 23
Finished Nov 01 02:44:03 PM PDT 23
Peak memory 206476 kb
Host smart-fd8320b5-72f3-4050-b0ed-352232b72792
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5661974973506887457394139590337078465024023245774802508045099427118431105200 -assert nopostproc +UV
M_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 37.edn_intr_test.5661974973506887457394139590337078465024023245774802508045099427118431105200
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.101125422274808613400989049026001225664249104634455592952785802555540299101638
Short name T184
Test name
Test status
Simulation time 25518366 ps
CPU time 0.87 seconds
Started Nov 01 02:44:06 PM PDT 23
Finished Nov 01 02:44:10 PM PDT 23
Peak memory 206504 kb
Host smart-eab641b2-5d88-41ea-94a2-d8e9f4b1fd8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101125422274808613400989049026001225664249104634455592952785802555540299101638 -assert nopostproc +
UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 38.edn_intr_test.101125422274808613400989049026001225664249104634455592952785802555540299101638
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.114977197887630068902105116013926858829794974706999791962027928099359288634398
Short name T119
Test name
Test status
Simulation time 25518366 ps
CPU time 0.85 seconds
Started Nov 01 02:44:02 PM PDT 23
Finished Nov 01 02:44:06 PM PDT 23
Peak memory 206600 kb
Host smart-93f7a3b5-9061-476f-ae6b-8dbd490e9399
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114977197887630068902105116013926858829794974706999791962027928099359288634398 -assert nopostproc +
UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 39.edn_intr_test.114977197887630068902105116013926858829794974706999791962027928099359288634398
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.33299435825185548863273309515811870485598038630096438990868750614992010701755
Short name T145
Test name
Test status
Simulation time 59184494 ps
CPU time 1.36 seconds
Started Nov 01 02:43:22 PM PDT 23
Finished Nov 01 02:43:25 PM PDT 23
Peak memory 206544 kb
Host smart-f668f228-6c9d-4e7e-9ee1-994abaad2346
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33299435825185548863273309515811870485598038630096438990868750614992010701755 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.33299435825185548863273309515811870485598038630096438990868750614992010701755
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.77348770912550573955824944250770577078012528020565673979055980130380801934346
Short name T151
Test name
Test status
Simulation time 351971476 ps
CPU time 5.02 seconds
Started Nov 01 02:44:00 PM PDT 23
Finished Nov 01 02:44:07 PM PDT 23
Peak memory 206600 kb
Host smart-791eb48d-560a-480e-b9b2-a190df2409ea
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77348770912550573955824944250770577078012528020565673979055980130380801934346 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.77348770912550573955824944250770577078012528020565673979055980130380801934346
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.36176266927760989734843756693731405370057741700131744023897186244160050875758
Short name T73
Test name
Test status
Simulation time 26726680 ps
CPU time 0.91 seconds
Started Nov 01 02:43:24 PM PDT 23
Finished Nov 01 02:43:26 PM PDT 23
Peak memory 206512 kb
Host smart-a598bbaf-26ef-4f39-8caf-98093447d02f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36176266927760989734843756693731405370057741700131744023897186244160050875758 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.36176266927760989734843756693731405370057741700131744023897186244160050875758
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.74675372458646612465341817798353497914267030850935428065775428904311366590150
Short name T167
Test name
Test status
Simulation time 51163789 ps
CPU time 1.3 seconds
Started Nov 01 02:43:26 PM PDT 23
Finished Nov 01 02:43:30 PM PDT 23
Peak memory 214916 kb
Host smart-3b8b95d2-71b1-4d2c-b10c-c8656b6cc129
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7467537245864661246534181779835349791426703
0850935428065775428904311366590150 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.7467537245864661246534181779
8353497914267030850935428065775428904311366590150
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.18789592778701964568427961759255039127182003149140693780362678289280706406208
Short name T76
Test name
Test status
Simulation time 23247569 ps
CPU time 0.84 seconds
Started Nov 01 02:43:31 PM PDT 23
Finished Nov 01 02:43:33 PM PDT 23
Peak memory 206624 kb
Host smart-2e763f68-a04a-4526-874b-582ce191bf6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18789592778701964568427961759255039127182003149140693780362678289280706406208 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.18789592778701964568427961759255039127182003149140693780362678289280706406208
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.104062261540400805320031644282943312998836769400476510882262946012393801913893
Short name T100
Test name
Test status
Simulation time 25518366 ps
CPU time 0.86 seconds
Started Nov 01 02:43:55 PM PDT 23
Finished Nov 01 02:43:57 PM PDT 23
Peak memory 206484 kb
Host smart-a29c2fc4-ac53-4682-a603-ae27a1639e76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104062261540400805320031644282943312998836769400476510882262946012393801913893 -assert nopostproc +
UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.edn_intr_test.104062261540400805320031644282943312998836769400476510882262946012393801913893
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.36794447969877271105798216096838855601266641029486852835662152517445747778213
Short name T195
Test name
Test status
Simulation time 61976116 ps
CPU time 1.31 seconds
Started Nov 01 02:43:54 PM PDT 23
Finished Nov 01 02:43:56 PM PDT 23
Peak memory 206508 kb
Host smart-e95b0332-2f78-40d1-94e1-84ffd504aff4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36794447969877271105798216096838855601266641029486852835662152517445747778213
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_outstanding.36794447969877271105798216096838855601266641029486852835662152517445747778213
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.39000528596476264624366983333681854039593075784349927841921846481849108612239
Short name T190
Test name
Test status
Simulation time 204078009 ps
CPU time 3.72 seconds
Started Nov 01 02:43:21 PM PDT 23
Finished Nov 01 02:43:27 PM PDT 23
Peak memory 214728 kb
Host smart-45cb94fd-88e0-4fa1-b512-0fb6b2d3d4e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39000528596476264624366983333681854039593075784349927841921846481849108612239 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 4.edn_tl_errors.39000528596476264624366983333681854039593075784349927841921846481849108612239
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.92952030346601900153043228780071020983552634972366731045591024757636586895310
Short name T144
Test name
Test status
Simulation time 155537119 ps
CPU time 2.2 seconds
Started Nov 01 02:43:26 PM PDT 23
Finished Nov 01 02:43:31 PM PDT 23
Peak memory 206608 kb
Host smart-d0f00d28-8fc6-4173-aa67-fc595fd77062
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92952030346601900153043228780071020983552634972366731045591024757636586895310 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.92952030346601900153043228780071020983552634972366731045591024757636586895310
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.29873202519704411332357087564516500295479515647860579357111153399934286479277
Short name T103
Test name
Test status
Simulation time 25518366 ps
CPU time 0.83 seconds
Started Nov 01 02:44:02 PM PDT 23
Finished Nov 01 02:44:06 PM PDT 23
Peak memory 206384 kb
Host smart-0cd75bc5-18ef-423a-8df2-3311f6a7b3a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29873202519704411332357087564516500295479515647860579357111153399934286479277 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 40.edn_intr_test.29873202519704411332357087564516500295479515647860579357111153399934286479277
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.28234503255140828117645992654594266893040007718363919218392489511863280215556
Short name T159
Test name
Test status
Simulation time 25518366 ps
CPU time 0.81 seconds
Started Nov 01 02:44:05 PM PDT 23
Finished Nov 01 02:44:09 PM PDT 23
Peak memory 206496 kb
Host smart-f0583f65-e653-49dc-b610-abe578519640
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28234503255140828117645992654594266893040007718363919218392489511863280215556 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 41.edn_intr_test.28234503255140828117645992654594266893040007718363919218392489511863280215556
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.33904566082771994035250093626299789023118324387507842871486619638489355596861
Short name T142
Test name
Test status
Simulation time 25518366 ps
CPU time 0.84 seconds
Started Nov 01 02:44:01 PM PDT 23
Finished Nov 01 02:44:05 PM PDT 23
Peak memory 206452 kb
Host smart-7bdc15ea-2a67-4f6d-9646-c6967b66acf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33904566082771994035250093626299789023118324387507842871486619638489355596861 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 42.edn_intr_test.33904566082771994035250093626299789023118324387507842871486619638489355596861
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.28318298599328117621554201708582995499193410544168184613893920136365521767586
Short name T166
Test name
Test status
Simulation time 25518366 ps
CPU time 0.82 seconds
Started Nov 01 02:44:05 PM PDT 23
Finished Nov 01 02:44:09 PM PDT 23
Peak memory 206492 kb
Host smart-1c4b0871-3ba9-483e-8468-340a07e75eb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28318298599328117621554201708582995499193410544168184613893920136365521767586 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 43.edn_intr_test.28318298599328117621554201708582995499193410544168184613893920136365521767586
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.57863598531633530499744032285464591642616039922497955867314678897937391003485
Short name T123
Test name
Test status
Simulation time 25518366 ps
CPU time 0.87 seconds
Started Nov 01 02:44:06 PM PDT 23
Finished Nov 01 02:44:10 PM PDT 23
Peak memory 206508 kb
Host smart-0c78459a-3d85-42e8-9eff-61610cfb1903
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57863598531633530499744032285464591642616039922497955867314678897937391003485 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 44.edn_intr_test.57863598531633530499744032285464591642616039922497955867314678897937391003485
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.53999104141845326106828709326284103186218338719700890605678666878691587213537
Short name T224
Test name
Test status
Simulation time 25518366 ps
CPU time 0.82 seconds
Started Nov 01 02:44:06 PM PDT 23
Finished Nov 01 02:44:11 PM PDT 23
Peak memory 206480 kb
Host smart-74dd1aff-c62d-4896-943b-329de02ff0a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53999104141845326106828709326284103186218338719700890605678666878691587213537 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 45.edn_intr_test.53999104141845326106828709326284103186218338719700890605678666878691587213537
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.85827771275234631463248470932743611449552618387328152055059746393226964256857
Short name T111
Test name
Test status
Simulation time 25518366 ps
CPU time 0.84 seconds
Started Nov 01 02:44:05 PM PDT 23
Finished Nov 01 02:44:09 PM PDT 23
Peak memory 206496 kb
Host smart-3e083e19-ff62-4f19-838e-061c25cbffd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85827771275234631463248470932743611449552618387328152055059746393226964256857 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 46.edn_intr_test.85827771275234631463248470932743611449552618387328152055059746393226964256857
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.104492179497753476814057922045447517479320826855453980245291509746671816240276
Short name T146
Test name
Test status
Simulation time 25518366 ps
CPU time 0.85 seconds
Started Nov 01 02:44:05 PM PDT 23
Finished Nov 01 02:44:09 PM PDT 23
Peak memory 206496 kb
Host smart-07aef1f4-4afb-479a-a602-47efe5060397
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104492179497753476814057922045447517479320826855453980245291509746671816240276 -assert nopostproc +
UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 47.edn_intr_test.104492179497753476814057922045447517479320826855453980245291509746671816240276
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.38146968679451937236765726298303121185722651807067715828122699149543784405245
Short name T164
Test name
Test status
Simulation time 25518366 ps
CPU time 0.89 seconds
Started Nov 01 02:44:06 PM PDT 23
Finished Nov 01 02:44:11 PM PDT 23
Peak memory 206388 kb
Host smart-b79abd38-b7cd-41c0-902d-b0d2322e08c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38146968679451937236765726298303121185722651807067715828122699149543784405245 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 48.edn_intr_test.38146968679451937236765726298303121185722651807067715828122699149543784405245
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.34799690763589146554239729257550493635995545855721377306023375302552593518979
Short name T106
Test name
Test status
Simulation time 25518366 ps
CPU time 0.92 seconds
Started Nov 01 02:44:08 PM PDT 23
Finished Nov 01 02:44:13 PM PDT 23
Peak memory 206496 kb
Host smart-ebdda355-8593-4399-b28c-cedbb3c751ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34799690763589146554239729257550493635995545855721377306023375302552593518979 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 49.edn_intr_test.34799690763589146554239729257550493635995545855721377306023375302552593518979
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.45695408673480813233785524642800307548040260819256086587677982046884543976210
Short name T208
Test name
Test status
Simulation time 51163789 ps
CPU time 1.3 seconds
Started Nov 01 02:43:23 PM PDT 23
Finished Nov 01 02:43:27 PM PDT 23
Peak memory 214688 kb
Host smart-6488bea7-7ddb-4af5-b54a-eb37ced4c3a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4569540867348081323378552464280030754804026
0819256086587677982046884543976210 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.4569540867348081323378552464
2800307548040260819256086587677982046884543976210
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.112456137538633882055056123809428755644581166966996503026471221220565277451753
Short name T217
Test name
Test status
Simulation time 23247569 ps
CPU time 0.86 seconds
Started Nov 01 02:43:21 PM PDT 23
Finished Nov 01 02:43:23 PM PDT 23
Peak memory 206652 kb
Host smart-183bb5b1-5b45-4633-a1c0-5114a5c8973d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112456137538633882055056123809428755644581166966996503026471221220565277451753 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.112456137538633882055056123809428755644581166966996503026471221220565277451753
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.16753747728594609956796564383754314652092852212307345533687151188567978471223
Short name T110
Test name
Test status
Simulation time 25518366 ps
CPU time 0.83 seconds
Started Nov 01 02:43:28 PM PDT 23
Finished Nov 01 02:43:30 PM PDT 23
Peak memory 206472 kb
Host smart-5dedb5cb-066e-4662-a086-2908b7ac6b06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16753747728594609956796564383754314652092852212307345533687151188567978471223 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.edn_intr_test.16753747728594609956796564383754314652092852212307345533687151188567978471223
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.88546292613718633131771223585399710537264793107271062617408361487088490677377
Short name T72
Test name
Test status
Simulation time 61976116 ps
CPU time 1.34 seconds
Started Nov 01 02:43:53 PM PDT 23
Finished Nov 01 02:43:55 PM PDT 23
Peak memory 206692 kb
Host smart-12da772a-c4bb-4242-8f34-2c36cf65b804
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88546292613718633131771223585399710537264793107271062617408361487088490677377
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_outstanding.88546292613718633131771223585399710537264793107271062617408361487088490677377
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.38138080510158282116809349922188429951728810068168954153457260909660727104794
Short name T156
Test name
Test status
Simulation time 204078009 ps
CPU time 3.77 seconds
Started Nov 01 02:43:26 PM PDT 23
Finished Nov 01 02:43:32 PM PDT 23
Peak memory 214632 kb
Host smart-f6efb172-30e7-45a6-8ae7-1948be45cc93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38138080510158282116809349922188429951728810068168954153457260909660727104794 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.edn_tl_errors.38138080510158282116809349922188429951728810068168954153457260909660727104794
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.113029394665063542942844372912195693682406642691101670343207060646621952824633
Short name T174
Test name
Test status
Simulation time 155537119 ps
CPU time 2.17 seconds
Started Nov 01 02:43:22 PM PDT 23
Finished Nov 01 02:43:27 PM PDT 23
Peak memory 206564 kb
Host smart-4ee5a655-d29a-46f8-a7b7-cc92e87a10eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113029394665063542942844372912195693682406642691101670343207060646621952824633 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.113029394665063542942844372912195693682406642691101670343207060646621952824633
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.98656672238350848019033594228619126186953253378920324383997364849834526419858
Short name T113
Test name
Test status
Simulation time 51163789 ps
CPU time 1.31 seconds
Started Nov 01 02:43:22 PM PDT 23
Finished Nov 01 02:43:25 PM PDT 23
Peak memory 214820 kb
Host smart-ef281511-ccbd-46f7-9525-e8b72931bf64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9865667223835084801903359422861912618695325
3378920324383997364849834526419858 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.9865667223835084801903359422
8619126186953253378920324383997364849834526419858
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.88349541422483220747859646291121678629247245085455064722126281937176576550721
Short name T175
Test name
Test status
Simulation time 23247569 ps
CPU time 0.84 seconds
Started Nov 01 02:43:53 PM PDT 23
Finished Nov 01 02:43:55 PM PDT 23
Peak memory 206496 kb
Host smart-0e22ad85-94cf-4e71-9900-e14c92baefa8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88349541422483220747859646291121678629247245085455064722126281937176576550721 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.88349541422483220747859646291121678629247245085455064722126281937176576550721
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.86116122645509056886695795533731296712560689725593291428832395832119020389660
Short name T112
Test name
Test status
Simulation time 25518366 ps
CPU time 0.82 seconds
Started Nov 01 02:43:29 PM PDT 23
Finished Nov 01 02:43:31 PM PDT 23
Peak memory 206480 kb
Host smart-4ee4928e-563d-4000-8f67-f1494ec310f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86116122645509056886695795533731296712560689725593291428832395832119020389660 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 6.edn_intr_test.86116122645509056886695795533731296712560689725593291428832395832119020389660
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.20778024641113625254077145716233901499663778536362218546611583930234934197177
Short name T81
Test name
Test status
Simulation time 61976116 ps
CPU time 1.28 seconds
Started Nov 01 02:43:21 PM PDT 23
Finished Nov 01 02:43:24 PM PDT 23
Peak memory 206644 kb
Host smart-743c474c-54a3-4493-b7bf-2b097c65f68e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20778024641113625254077145716233901499663778536362218546611583930234934197177
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_outstanding.20778024641113625254077145716233901499663778536362218546611583930234934197177
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.111223898021820755815063678047562611010092098294042138476924206167178528651725
Short name T169
Test name
Test status
Simulation time 204078009 ps
CPU time 3.75 seconds
Started Nov 01 02:43:25 PM PDT 23
Finished Nov 01 02:43:31 PM PDT 23
Peak memory 214756 kb
Host smart-99d76a34-4eb3-45c6-9066-8fce90db5fbf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111223898021820755815063678047562611010092098294042138476924206167178528651725 -assert nopostproc +
UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.edn_tl_errors.111223898021820755815063678047562611010092098294042138476924206167178528651725
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.29865082284886277319469131756038372604454280158998598232419984386951746536945
Short name T8
Test name
Test status
Simulation time 155537119 ps
CPU time 2.21 seconds
Started Nov 01 02:43:53 PM PDT 23
Finished Nov 01 02:43:56 PM PDT 23
Peak memory 206636 kb
Host smart-a3fec9fe-590d-4706-ad95-bbcdf4e377d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29865082284886277319469131756038372604454280158998598232419984386951746536945 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.29865082284886277319469131756038372604454280158998598232419984386951746536945
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.53990534432107081646540783609019509797504921799461443746915411272974286751895
Short name T5
Test name
Test status
Simulation time 51163789 ps
CPU time 1.34 seconds
Started Nov 01 02:43:23 PM PDT 23
Finished Nov 01 02:43:26 PM PDT 23
Peak memory 214820 kb
Host smart-4b05e322-7521-4a11-836d-e31eae379749
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5399053443210708164654078360901950979750492
1799461443746915411272974286751895 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.5399053443210708164654078360
9019509797504921799461443746915411272974286751895
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.95876865000337837163100247390894366861924706959795243156473808434227364491714
Short name T135
Test name
Test status
Simulation time 23247569 ps
CPU time 0.83 seconds
Started Nov 01 02:43:30 PM PDT 23
Finished Nov 01 02:43:32 PM PDT 23
Peak memory 206500 kb
Host smart-f7e1979d-a1f0-456c-909b-9fec92e83046
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95876865000337837163100247390894366861924706959795243156473808434227364491714 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.95876865000337837163100247390894366861924706959795243156473808434227364491714
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.96832033736734004206525006852010918699578107672534114662386282645039628216870
Short name T204
Test name
Test status
Simulation time 25518366 ps
CPU time 0.85 seconds
Started Nov 01 02:43:22 PM PDT 23
Finished Nov 01 02:43:25 PM PDT 23
Peak memory 206512 kb
Host smart-325c2959-f07d-4501-813f-e6f78b5021d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96832033736734004206525006852010918699578107672534114662386282645039628216870 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 7.edn_intr_test.96832033736734004206525006852010918699578107672534114662386282645039628216870
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.101761226677225997317470251722963071655062281980866700208880907741954677262264
Short name T68
Test name
Test status
Simulation time 61976116 ps
CPU time 1.28 seconds
Started Nov 01 02:43:28 PM PDT 23
Finished Nov 01 02:43:31 PM PDT 23
Peak memory 206620 kb
Host smart-7016d854-3eb1-45cb-aa10-292a05711ca9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101761226677225997317470251722963071655062281980866700208880907741954677262264
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_outstanding.101761226677225997317470251722963071655062281980866700208880907741954677262264
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.90775240462333975038057726486990749547412465731672504055674222053174590922008
Short name T209
Test name
Test status
Simulation time 204078009 ps
CPU time 3.66 seconds
Started Nov 01 02:43:54 PM PDT 23
Finished Nov 01 02:43:58 PM PDT 23
Peak memory 214712 kb
Host smart-20d860ac-9ed8-4d5f-a634-cf16a76ff097
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90775240462333975038057726486990749547412465731672504055674222053174590922008 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 7.edn_tl_errors.90775240462333975038057726486990749547412465731672504055674222053174590922008
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.7659050639760893847263064839828480259454672398570633009720826551138471261976
Short name T4
Test name
Test status
Simulation time 155537119 ps
CPU time 2.27 seconds
Started Nov 01 02:43:23 PM PDT 23
Finished Nov 01 02:43:27 PM PDT 23
Peak memory 206732 kb
Host smart-915a97f2-d896-44a3-be35-dc4edffb6c4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7659050639760893847263064839828480259454672398570633009720826551138471261976 -assert no
postproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.7659050639760893847263064839828480259454672398570633009720826551138471261976
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.43054258813615897223771537189814713902618750562884982410835342264651139308467
Short name T116
Test name
Test status
Simulation time 51163789 ps
CPU time 1.28 seconds
Started Nov 01 02:43:23 PM PDT 23
Finished Nov 01 02:43:26 PM PDT 23
Peak memory 214824 kb
Host smart-21748a33-bd7c-4cd4-8930-e4b07146ec96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4305425881361589722377153718981471390261875
0562884982410835342264651139308467 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.4305425881361589722377153718
9814713902618750562884982410835342264651139308467
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.105836612201925344012756608267606117039435399393667311777227710826044486841545
Short name T207
Test name
Test status
Simulation time 23247569 ps
CPU time 0.89 seconds
Started Nov 01 02:43:28 PM PDT 23
Finished Nov 01 02:43:30 PM PDT 23
Peak memory 206568 kb
Host smart-021542c5-c651-48b3-bcee-8832d3721096
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105836612201925344012756608267606117039435399393667311777227710826044486841545 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.105836612201925344012756608267606117039435399393667311777227710826044486841545
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.30051732855876592780727028144582309252044305092104812499660530476221998791159
Short name T152
Test name
Test status
Simulation time 25518366 ps
CPU time 0.84 seconds
Started Nov 01 02:43:25 PM PDT 23
Finished Nov 01 02:43:28 PM PDT 23
Peak memory 206404 kb
Host smart-d76d08fd-3ced-466a-974b-96190735dd27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30051732855876592780727028144582309252044305092104812499660530476221998791159 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 8.edn_intr_test.30051732855876592780727028144582309252044305092104812499660530476221998791159
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.6719118989918058308799068938803565119151232662986685059876817215913112111364
Short name T74
Test name
Test status
Simulation time 61976116 ps
CPU time 1.28 seconds
Started Nov 01 02:43:23 PM PDT 23
Finished Nov 01 02:43:26 PM PDT 23
Peak memory 206488 kb
Host smart-ea945b66-eb39-4261-9c7d-9eed40594f54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6719118989918058308799068938803565119151232662986685059876817215913112111364 -
assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_outstanding.6719118989918058308799068938803565119151232662986685059876817215913112111364
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.6723256328594908529128465727932366487483804431254625829484121259714194417705
Short name T67
Test name
Test status
Simulation time 204078009 ps
CPU time 3.67 seconds
Started Nov 01 02:43:20 PM PDT 23
Finished Nov 01 02:43:25 PM PDT 23
Peak memory 214732 kb
Host smart-22bc1905-6241-4bfa-b27f-c01d506ee9da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6723256328594908529128465727932366487483804431254625829484121259714194417705 -assert nopostproc +UV
M_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.edn_tl_errors.6723256328594908529128465727932366487483804431254625829484121259714194417705
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.36668794363477178223228459947813115635286045544183294972762117777034505775184
Short name T154
Test name
Test status
Simulation time 155537119 ps
CPU time 2.19 seconds
Started Nov 01 02:43:20 PM PDT 23
Finished Nov 01 02:43:24 PM PDT 23
Peak memory 206624 kb
Host smart-6851a299-f17f-4fe7-8fdd-eec7eff766af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36668794363477178223228459947813115635286045544183294972762117777034505775184 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.36668794363477178223228459947813115635286045544183294972762117777034505775184
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.82641162380850087585369250663550305681678829905630440323819849391302196031358
Short name T160
Test name
Test status
Simulation time 51163789 ps
CPU time 1.29 seconds
Started Nov 01 02:43:29 PM PDT 23
Finished Nov 01 02:43:32 PM PDT 23
Peak memory 214808 kb
Host smart-2fa8efe6-4ec0-49dc-be95-8895c2630e7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8264116238085008758536925066355030568167882
9905630440323819849391302196031358 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.8264116238085008758536925066
3550305681678829905630440323819849391302196031358
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.77180026194649777818557761860718686226519160919932978309348359270466822251707
Short name T132
Test name
Test status
Simulation time 23247569 ps
CPU time 0.84 seconds
Started Nov 01 02:43:47 PM PDT 23
Finished Nov 01 02:43:48 PM PDT 23
Peak memory 206492 kb
Host smart-20369834-ba33-4035-bc67-a04bd6154db0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77180026194649777818557761860718686226519160919932978309348359270466822251707 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.77180026194649777818557761860718686226519160919932978309348359270466822251707
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.75919637511461010133349251002520117173577556460918650274602355067908703595918
Short name T127
Test name
Test status
Simulation time 25518366 ps
CPU time 0.84 seconds
Started Nov 01 02:43:24 PM PDT 23
Finished Nov 01 02:43:27 PM PDT 23
Peak memory 206492 kb
Host smart-00a81932-8e4d-4e61-9ae3-1ced7386af17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75919637511461010133349251002520117173577556460918650274602355067908703595918 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.edn_intr_test.75919637511461010133349251002520117173577556460918650274602355067908703595918
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.20875274037572570269252012651098280747539723828603578954532777750700334642889
Short name T150
Test name
Test status
Simulation time 61976116 ps
CPU time 1.29 seconds
Started Nov 01 02:43:23 PM PDT 23
Finished Nov 01 02:43:26 PM PDT 23
Peak memory 206612 kb
Host smart-3dac5a48-fbba-4cc1-bac2-4d3a5f22ad79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20875274037572570269252012651098280747539723828603578954532777750700334642889
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_outstanding.20875274037572570269252012651098280747539723828603578954532777750700334642889
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.39807263632289546695557930432294886198140223552113873845858547783558432321678
Short name T234
Test name
Test status
Simulation time 204078009 ps
CPU time 3.58 seconds
Started Nov 01 02:43:52 PM PDT 23
Finished Nov 01 02:43:57 PM PDT 23
Peak memory 214772 kb
Host smart-2db4d5b0-d239-4ffe-9f8e-0616c461c47b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39807263632289546695557930432294886198140223552113873845858547783558432321678 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.edn_tl_errors.39807263632289546695557930432294886198140223552113873845858547783558432321678
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.57711704545208452825968616601882529006288353235552149619162447814166232928230
Short name T125
Test name
Test status
Simulation time 155537119 ps
CPU time 2.17 seconds
Started Nov 01 02:44:00 PM PDT 23
Finished Nov 01 02:44:05 PM PDT 23
Peak memory 206656 kb
Host smart-f015a971-b6d9-40a9-8860-c6f2ca64aa16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57711704545208452825968616601882529006288353235552149619162447814166232928230 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.57711704545208452825968616601882529006288353235552149619162447814166232928230
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.67717584624329966211540494278514672890010006068531628128443306226516466238114
Short name T699
Test name
Test status
Simulation time 18259183 ps
CPU time 0.96 seconds
Started Nov 01 02:25:28 PM PDT 23
Finished Nov 01 02:25:30 PM PDT 23
Peak memory 205632 kb
Host smart-b8127985-b08e-4dec-b1fe-ecb8e243b5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67717584624329966211540494278514672890010006068531628128443306226516466238114 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.edn_alert.67717584624329966211540494278514672890010006068531628128443306226516466238114
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.92720063166081192481364246085983604085517766445533634620872847895999275634894
Short name T879
Test name
Test status
Simulation time 28184990 ps
CPU time 0.87 seconds
Started Nov 01 02:25:29 PM PDT 23
Finished Nov 01 02:25:31 PM PDT 23
Peak memory 205456 kb
Host smart-75c5f859-3652-4638-a8e6-9e7b10590146
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92720063166081192481364246085983604085517766445533634620872847895999275634894 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.edn_alert_test.92720063166081192481364246085983604085517766445533634620872847895999275634894
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.105788515316939463957783125337194031475895266610619965670302988595024232299695
Short name T960
Test name
Test status
Simulation time 12219183 ps
CPU time 0.91 seconds
Started Nov 01 02:25:26 PM PDT 23
Finished Nov 01 02:25:29 PM PDT 23
Peak memory 214908 kb
Host smart-5a88323f-e970-41ab-beca-57d94392217a
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105788515316939463957783125337194031475895266610619965670302988595024232299695 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 0.edn_disable.105788515316939463957783125337194031475895266610619965670302988595024232299695
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.103357528404954106789751240185215322301282456721033008627633039132397833566962
Short name T690
Test name
Test status
Simulation time 17319183 ps
CPU time 0.96 seconds
Started Nov 01 02:25:29 PM PDT 23
Finished Nov 01 02:25:32 PM PDT 23
Peak memory 214844 kb
Host smart-c9455fe5-32c2-4c36-aff0-de1b050cde3e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103357528404954106789751240185215322301282456721033008627633039132397833566962 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable_auto_req_mode.1033575284049541067897512401852153223012824567210330086276
33039132397833566962
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.30890023475905825470343623225524834281707351860071518745055156564361269654441
Short name T722
Test name
Test status
Simulation time 24963823 ps
CPU time 1.15 seconds
Started Nov 01 02:25:26 PM PDT 23
Finished Nov 01 02:25:29 PM PDT 23
Peak memory 230424 kb
Host smart-686a4589-fb59-40ba-ab21-db3c8a5bc2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30890023475905825470343623225524834281707351860071518745055156564361269654441 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
edn_err.30890023475905825470343623225524834281707351860071518745055156564361269654441
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.7940412819343766917298263297448468385082905469886420551609683694485223595754
Short name T39
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 01 02:25:27 PM PDT 23
Finished Nov 01 02:25:30 PM PDT 23
Peak memory 205736 kb
Host smart-8deb6462-7db3-42e7-92e0-6bd2ef07cb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7940412819343766917298263297448468385082905469886420551609683694485223595754 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.edn_genbits.7940412819343766917298263297448468385082905469886420551609683694485223595754
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.63026433884918591091606940546135651029717858806929010870307109232704929481077
Short name T27
Test name
Test status
Simulation time 18439183 ps
CPU time 1.16 seconds
Started Nov 01 02:25:30 PM PDT 23
Finished Nov 01 02:25:34 PM PDT 23
Peak memory 222304 kb
Host smart-66975902-f2b3-4a35-8829-b7ec68bfaae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63026433884918591091606940546135651029717858806929010870307109232704929481077 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.edn_intr.63026433884918591091606940546135651029717858806929010870307109232704929481077
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.100062468691639362084333135458417535371055378228511870649683707690029669087960
Short name T748
Test name
Test status
Simulation time 11759183 ps
CPU time 0.9 seconds
Started Nov 01 02:25:50 PM PDT 23
Finished Nov 01 02:25:58 PM PDT 23
Peak memory 205332 kb
Host smart-4f965b91-1967-47ae-be30-7346262f23d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100062468691639362084333135458417535371055378228511870649683707690029669087960 -assert nopostproc +UVM_TESTNAME=edn_smok
e_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.edn_regwen.100062468691639362084333135458417535371055378228511870649683707690029669087960
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.65900436001064054501226886337844297658644795509368183417557933489407389943537
Short name T31
Test name
Test status
Simulation time 717215632 ps
CPU time 5.96 seconds
Started Nov 01 02:25:29 PM PDT 23
Finished Nov 01 02:25:37 PM PDT 23
Peak memory 234028 kb
Host smart-4be14841-ce58-49cb-9685-5f80bdcefd5b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65900436001064054501226886337844297658644795509368183417557933489407389943537 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.edn_sec_cm.65900436001064054501226886337844297658644795509368183417557933489407389943537
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.91403648923179715824634836625049838761747862535256739217305587758027785730789
Short name T54
Test name
Test status
Simulation time 13059183 ps
CPU time 0.94 seconds
Started Nov 01 02:25:24 PM PDT 23
Finished Nov 01 02:25:28 PM PDT 23
Peak memory 205416 kb
Host smart-b6e113b9-08af-4d04-8005-c8c0908ed401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91403648923179715824634836625049838761747862535256739217305587758027785730789 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.edn_smoke.91403648923179715824634836625049838761747862535256739217305587758027785730789
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.19821885991727718311602199007650283656816113187544234241998612776708523938974
Short name T701
Test name
Test status
Simulation time 154489183 ps
CPU time 4.09 seconds
Started Nov 01 02:25:24 PM PDT 23
Finished Nov 01 02:25:31 PM PDT 23
Peak memory 206424 kb
Host smart-9ffe68b7-edec-4487-9802-b81a291e72e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19821885991727718311602199007650283656816113187544234241998612776708523938974 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.19821885991727718311602199007650283656816113187544234241998612776708523938974
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.49359274147249796536701575054566769745568943109800998734502752209619621106221
Short name T44
Test name
Test status
Simulation time 41708099183 ps
CPU time 1100.59 seconds
Started Nov 01 02:25:39 PM PDT 23
Finished Nov 01 02:44:00 PM PDT 23
Peak memory 215864 kb
Host smart-c5433723-98dd-419a-bef4-4505d76fc2b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493592741472497965367015750
54566769745568943109800998734502752209619621106221 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.493592741472
49796536701575054566769745568943109800998734502752209619621106221
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.92470211550405274056126485402602210654386203458853006238705137934713202790480
Short name T686
Test name
Test status
Simulation time 18259183 ps
CPU time 1 seconds
Started Nov 01 02:25:41 PM PDT 23
Finished Nov 01 02:25:44 PM PDT 23
Peak memory 205552 kb
Host smart-d193fd73-1086-415e-92e4-734f836dcd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92470211550405274056126485402602210654386203458853006238705137934713202790480 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.edn_alert.92470211550405274056126485402602210654386203458853006238705137934713202790480
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.62818911400013492151602271152874450207847209905056868476712206748922759116621
Short name T979
Test name
Test status
Simulation time 28184990 ps
CPU time 0.89 seconds
Started Nov 01 02:25:43 PM PDT 23
Finished Nov 01 02:25:45 PM PDT 23
Peak memory 205456 kb
Host smart-a005a698-774b-491c-8944-6985d68f8673
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62818911400013492151602271152874450207847209905056868476712206748922759116621 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.edn_alert_test.62818911400013492151602271152874450207847209905056868476712206748922759116621
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.115785199104052555637232652702712576051903159322941341936702383393163300767674
Short name T930
Test name
Test status
Simulation time 12219183 ps
CPU time 0.89 seconds
Started Nov 01 02:25:40 PM PDT 23
Finished Nov 01 02:25:43 PM PDT 23
Peak memory 214912 kb
Host smart-212f6da3-b343-4786-bf37-e9385fde464d
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115785199104052555637232652702712576051903159322941341936702383393163300767674 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 1.edn_disable.115785199104052555637232652702712576051903159322941341936702383393163300767674
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.103012890969882242329530813207474276993638279912598814310869009681732672009517
Short name T819
Test name
Test status
Simulation time 17319183 ps
CPU time 0.93 seconds
Started Nov 01 02:25:44 PM PDT 23
Finished Nov 01 02:25:47 PM PDT 23
Peak memory 214884 kb
Host smart-e912277d-b470-458f-80b4-9b02379aa581
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103012890969882242329530813207474276993638279912598814310869009681732672009517 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable_auto_req_mode.1030128909698822423295308132074742769936382799125988143108
69009681732672009517
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.21989932778048637012952922983412477553251101416946806607589822817529058003455
Short name T609
Test name
Test status
Simulation time 24963823 ps
CPU time 1.16 seconds
Started Nov 01 02:25:28 PM PDT 23
Finished Nov 01 02:25:31 PM PDT 23
Peak memory 230524 kb
Host smart-da320530-cba3-43fe-b4ce-7b4b73c1fcce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21989932778048637012952922983412477553251101416946806607589822817529058003455 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
edn_err.21989932778048637012952922983412477553251101416946806607589822817529058003455
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.42119807304409094326091632676670171234414378570333646562505789552679000877758
Short name T641
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:25:44 PM PDT 23
Finished Nov 01 02:25:46 PM PDT 23
Peak memory 205896 kb
Host smart-aea94e96-c775-473a-a9f6-bec89a3e9f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42119807304409094326091632676670171234414378570333646562505789552679000877758 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.edn_genbits.42119807304409094326091632676670171234414378570333646562505789552679000877758
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.88593206695793947131554778857027998608900023206167816024914762619447642016604
Short name T708
Test name
Test status
Simulation time 18439183 ps
CPU time 1.15 seconds
Started Nov 01 02:25:45 PM PDT 23
Finished Nov 01 02:25:48 PM PDT 23
Peak memory 222124 kb
Host smart-d738e0ea-2f2b-42d2-bcb2-902888f94857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88593206695793947131554778857027998608900023206167816024914762619447642016604 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.edn_intr.88593206695793947131554778857027998608900023206167816024914762619447642016604
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.67175917519263783602029719402823045715400875585753871889649608693100874683513
Short name T94
Test name
Test status
Simulation time 11759183 ps
CPU time 0.89 seconds
Started Nov 01 02:25:30 PM PDT 23
Finished Nov 01 02:25:33 PM PDT 23
Peak memory 205420 kb
Host smart-73e5e0a4-2b5e-43a5-bd4e-474d03ee4a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67175917519263783602029719402823045715400875585753871889649608693100874683513 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.edn_regwen.67175917519263783602029719402823045715400875585753871889649608693100874683513
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.107232142829027529716417749428211189073251621578339548118597648157274983179618
Short name T46
Test name
Test status
Simulation time 717215632 ps
CPU time 5.67 seconds
Started Nov 01 02:25:45 PM PDT 23
Finished Nov 01 02:25:53 PM PDT 23
Peak memory 233916 kb
Host smart-c3c6b1d6-683e-4e34-b0be-a976acbef294
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107232142829027529716417749428211189073251621578339548118597648157274983179618 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.edn_sec_cm.107232142829027529716417749428211189073251621578339548118597648157274983179618
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.49600493042901205537864324388689081359172446222907683478482564929329228886184
Short name T976
Test name
Test status
Simulation time 13059183 ps
CPU time 0.88 seconds
Started Nov 01 02:25:31 PM PDT 23
Finished Nov 01 02:25:34 PM PDT 23
Peak memory 205400 kb
Host smart-f8897d62-1163-4127-9e8e-f1e519820a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49600493042901205537864324388689081359172446222907683478482564929329228886184 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.edn_smoke.49600493042901205537864324388689081359172446222907683478482564929329228886184
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.102160932637536879983381293608669663319395098931479249483525912529369586046526
Short name T886
Test name
Test status
Simulation time 154489183 ps
CPU time 3.96 seconds
Started Nov 01 02:25:35 PM PDT 23
Finished Nov 01 02:25:40 PM PDT 23
Peak memory 206424 kb
Host smart-a74830fa-eddb-48ad-9e7c-99d6a27e2c60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102160932637536879983381293608669663319395098931479249483525912529369586046526 -assert nopo
stproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.102160932637536879983381293608669663319395098931479249483525912529369586046526
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.2740463061704795081174747340015034233848542567507504381193991025693492119206
Short name T818
Test name
Test status
Simulation time 41708099183 ps
CPU time 1037.29 seconds
Started Nov 01 02:25:28 PM PDT 23
Finished Nov 01 02:42:47 PM PDT 23
Peak memory 215920 kb
Host smart-992057da-b8b9-4302-bdec-ee4bf89f1053
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274046306170479508117474734
0015034233848542567507504381193991025693492119206 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.2740463061704
795081174747340015034233848542567507504381193991025693492119206
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.58982306483450721830648462957800005796645174034307043924367781371074688915262
Short name T823
Test name
Test status
Simulation time 18259183 ps
CPU time 1 seconds
Started Nov 01 02:26:41 PM PDT 23
Finished Nov 01 02:26:47 PM PDT 23
Peak memory 205528 kb
Host smart-98361c1c-c049-4af1-9616-c627c6a0c896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58982306483450721830648462957800005796645174034307043924367781371074688915262 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.edn_alert.58982306483450721830648462957800005796645174034307043924367781371074688915262
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.99810936681338500510074234266244932729891794794422085800627930490694754832315
Short name T977
Test name
Test status
Simulation time 28184990 ps
CPU time 0.9 seconds
Started Nov 01 02:26:52 PM PDT 23
Finished Nov 01 02:26:57 PM PDT 23
Peak memory 205528 kb
Host smart-1648ae66-0251-43c6-96a5-6540cf7afa44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99810936681338500510074234266244932729891794794422085800627930490694754832315 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.edn_alert_test.99810936681338500510074234266244932729891794794422085800627930490694754832315
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.63260522221024877885279092581800738335150393066999129411488119969920304055933
Short name T521
Test name
Test status
Simulation time 12219183 ps
CPU time 0.88 seconds
Started Nov 01 02:26:51 PM PDT 23
Finished Nov 01 02:26:55 PM PDT 23
Peak memory 214916 kb
Host smart-0e8a9d8b-52be-4ddb-959b-6b0d40d7e7bd
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63260522221024877885279092581800738335150393066999129411488119969920304055933 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.edn_disable.63260522221024877885279092581800738335150393066999129411488119969920304055933
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.83250432637309554419104216729587595099970945515387892234703778016560356622968
Short name T628
Test name
Test status
Simulation time 17319183 ps
CPU time 0.95 seconds
Started Nov 01 02:27:01 PM PDT 23
Finished Nov 01 02:27:16 PM PDT 23
Peak memory 214848 kb
Host smart-3a36e807-e2cc-4d4e-b6ec-33ddea4319e0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83250432637309554419104216729587595099970945515387892234703778016560356622968 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable_auto_req_mode.8325043263730955441910421672958759509997094551538789223470
3778016560356622968
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.18017122117311054414806166452064042421421413594783523131278696092735151596758
Short name T342
Test name
Test status
Simulation time 24963823 ps
CPU time 1.17 seconds
Started Nov 01 02:26:55 PM PDT 23
Finished Nov 01 02:27:04 PM PDT 23
Peak memory 230488 kb
Host smart-411a504a-0289-44f7-a6ff-f6a87ae5ee9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18017122117311054414806166452064042421421413594783523131278696092735151596758 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.edn_err.18017122117311054414806166452064042421421413594783523131278696092735151596758
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.112058002541423032614183085876490552461312731660862408723853339568595178898310
Short name T916
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:26:52 PM PDT 23
Finished Nov 01 02:26:57 PM PDT 23
Peak memory 205864 kb
Host smart-b406ee92-da3c-440b-99a7-8a83da065af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112058002541423032614183085876490552461312731660862408723853339568595178898310 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 10.edn_genbits.112058002541423032614183085876490552461312731660862408723853339568595178898310
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.83163164242493136175872391458787706083278695085698295575143975571167322277328
Short name T36
Test name
Test status
Simulation time 18439183 ps
CPU time 1.13 seconds
Started Nov 01 02:26:56 PM PDT 23
Finished Nov 01 02:27:06 PM PDT 23
Peak memory 222284 kb
Host smart-e7679005-b0a0-4916-8b82-c0e50b77e817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83163164242493136175872391458787706083278695085698295575143975571167322277328 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.edn_intr.83163164242493136175872391458787706083278695085698295575143975571167322277328
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.6688282338754636302560001866042924683397675797494649181767921174288876284125
Short name T522
Test name
Test status
Simulation time 13059183 ps
CPU time 0.88 seconds
Started Nov 01 02:26:49 PM PDT 23
Finished Nov 01 02:26:53 PM PDT 23
Peak memory 205408 kb
Host smart-5e3d4682-951b-4e4a-bd80-b3c905989c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6688282338754636302560001866042924683397675797494649181767921174288876284125 -assert nopostproc +UVM_TESTNAME=edn_smoke_
test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.edn_smoke.6688282338754636302560001866042924683397675797494649181767921174288876284125
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.34998714917236968790857478336822980795730192212004279691573985585407585268024
Short name T764
Test name
Test status
Simulation time 154489183 ps
CPU time 3.99 seconds
Started Nov 01 02:26:51 PM PDT 23
Finished Nov 01 02:26:58 PM PDT 23
Peak memory 206332 kb
Host smart-f7e8ad3b-d44a-4b0a-b4f3-e2d5ca41e531
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34998714917236968790857478336822980795730192212004279691573985585407585268024 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.34998714917236968790857478336822980795730192212004279691573985585407585268024
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.6245167483497519569238748376024477755568451997473926273688055475846686812616
Short name T238
Test name
Test status
Simulation time 41708099183 ps
CPU time 1105.04 seconds
Started Nov 01 02:26:38 PM PDT 23
Finished Nov 01 02:45:06 PM PDT 23
Peak memory 215928 kb
Host smart-15e31d15-4aae-47f8-9f5e-dd0ff071f4bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624516748349751956923874837
6024477755568451997473926273688055475846686812616 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.624516748349
7519569238748376024477755568451997473926273688055475846686812616
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.43071622269924847793286912130040929499530078309646670826161488616614930882580
Short name T931
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 01 02:27:04 PM PDT 23
Finished Nov 01 02:27:19 PM PDT 23
Peak memory 205844 kb
Host smart-5b4cbd92-de0d-460e-8cac-c03c3a38bab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43071622269924847793286912130040929499530078309646670826161488616614930882580 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 100.edn_genbits.43071622269924847793286912130040929499530078309646670826161488616614930882580
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.96148466342106512223522431682044678210308968850237862692382657478125546489850
Short name T936
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:27:02 PM PDT 23
Finished Nov 01 02:27:17 PM PDT 23
Peak memory 205896 kb
Host smart-46eaa594-5a8b-4736-8814-20a7034c5b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96148466342106512223522431682044678210308968850237862692382657478125546489850 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 101.edn_genbits.96148466342106512223522431682044678210308968850237862692382657478125546489850
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.60677832292792380274220628609450640792338930298015093764112289054506758099811
Short name T422
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Nov 01 02:27:27 PM PDT 23
Finished Nov 01 02:27:42 PM PDT 23
Peak memory 205748 kb
Host smart-4af60d37-a22a-40e1-85e5-54e6fc0f3148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60677832292792380274220628609450640792338930298015093764112289054506758099811 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 102.edn_genbits.60677832292792380274220628609450640792338930298015093764112289054506758099811
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.16342843855923697598010892295862892848415356285097962469875645289419568323207
Short name T443
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 01 02:27:00 PM PDT 23
Finished Nov 01 02:27:15 PM PDT 23
Peak memory 205920 kb
Host smart-3f8f3ac5-0de6-4a3c-ac01-ce1497c9aeb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16342843855923697598010892295862892848415356285097962469875645289419568323207 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 103.edn_genbits.16342843855923697598010892295862892848415356285097962469875645289419568323207
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.86850451555794644367563597992356365525573140302843199180809996057489260391725
Short name T267
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:27:15 PM PDT 23
Finished Nov 01 02:27:31 PM PDT 23
Peak memory 205852 kb
Host smart-94757144-1e5c-4e73-be6e-51b04a15030d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86850451555794644367563597992356365525573140302843199180809996057489260391725 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 104.edn_genbits.86850451555794644367563597992356365525573140302843199180809996057489260391725
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.26816381765644901745096156602118898331286525248546846966349218848660924822585
Short name T962
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 01 02:27:09 PM PDT 23
Finished Nov 01 02:27:26 PM PDT 23
Peak memory 205896 kb
Host smart-ea00822c-bd62-4f5f-9d81-b5aca76247c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26816381765644901745096156602118898331286525248546846966349218848660924822585 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 105.edn_genbits.26816381765644901745096156602118898331286525248546846966349218848660924822585
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.84360848365555370199413817176230917396106388336338007908725121641150463686396
Short name T814
Test name
Test status
Simulation time 17999183 ps
CPU time 1.15 seconds
Started Nov 01 02:27:02 PM PDT 23
Finished Nov 01 02:27:17 PM PDT 23
Peak memory 205896 kb
Host smart-591cad04-1a68-4803-93ee-af8b32f9925d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84360848365555370199413817176230917396106388336338007908725121641150463686396 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 106.edn_genbits.84360848365555370199413817176230917396106388336338007908725121641150463686396
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.88095106058936921400001113883869339754944963466570864075658228673375773458927
Short name T66
Test name
Test status
Simulation time 17999183 ps
CPU time 1.15 seconds
Started Nov 01 02:27:15 PM PDT 23
Finished Nov 01 02:27:30 PM PDT 23
Peak memory 205924 kb
Host smart-42daa110-18ba-4377-a37e-d21dd95e330d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88095106058936921400001113883869339754944963466570864075658228673375773458927 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 107.edn_genbits.88095106058936921400001113883869339754944963466570864075658228673375773458927
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.49800369648521779735016089988323227827291171431564755911481600075288456345959
Short name T605
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 01 02:27:15 PM PDT 23
Finished Nov 01 02:27:30 PM PDT 23
Peak memory 205852 kb
Host smart-19c37186-0446-4451-9c21-c09e58e0044e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49800369648521779735016089988323227827291171431564755911481600075288456345959 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 108.edn_genbits.49800369648521779735016089988323227827291171431564755911481600075288456345959
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.35293446245232954393690381774406729932208803280286833838891449755254808757921
Short name T508
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 01 02:27:46 PM PDT 23
Finished Nov 01 02:27:54 PM PDT 23
Peak memory 205860 kb
Host smart-937353cf-9edb-4930-b29e-1b8c78aa0942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35293446245232954393690381774406729932208803280286833838891449755254808757921 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 109.edn_genbits.35293446245232954393690381774406729932208803280286833838891449755254808757921
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.56884455962580170745782242105881920112591381843480341063287709291691835787237
Short name T852
Test name
Test status
Simulation time 18259183 ps
CPU time 0.97 seconds
Started Nov 01 02:26:56 PM PDT 23
Finished Nov 01 02:27:07 PM PDT 23
Peak memory 205512 kb
Host smart-ed63a977-4d8a-4d65-ac69-e6299a43ad15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56884455962580170745782242105881920112591381843480341063287709291691835787237 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.edn_alert.56884455962580170745782242105881920112591381843480341063287709291691835787237
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.112187487766572065025089693482695866122513838290217771469991276210566473260532
Short name T956
Test name
Test status
Simulation time 28184990 ps
CPU time 0.88 seconds
Started Nov 01 02:27:21 PM PDT 23
Finished Nov 01 02:27:35 PM PDT 23
Peak memory 205484 kb
Host smart-16e9298d-e5ca-43d1-bb68-d57e416cc574
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112187487766572065025089693482695866122513838290217771469991276210566473260532 -assert nopostp
roc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 11.edn_alert_test.112187487766572065025089693482695866122513838290217771469991276210566473260532
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.49025720475895124278075817779820946703256303575000337708855309289051574220173
Short name T759
Test name
Test status
Simulation time 12219183 ps
CPU time 0.87 seconds
Started Nov 01 02:27:21 PM PDT 23
Finished Nov 01 02:27:36 PM PDT 23
Peak memory 214872 kb
Host smart-f8dd8ae7-5e52-4631-8dd5-6b7f6df82e46
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49025720475895124278075817779820946703256303575000337708855309289051574220173 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.edn_disable.49025720475895124278075817779820946703256303575000337708855309289051574220173
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.40994720295861535670787957831146517445048145969719661097737687059782773106751
Short name T973
Test name
Test status
Simulation time 17319183 ps
CPU time 0.92 seconds
Started Nov 01 02:26:59 PM PDT 23
Finished Nov 01 02:27:12 PM PDT 23
Peak memory 214812 kb
Host smart-991b4f03-56d8-481a-ae98-f1aad6285807
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40994720295861535670787957831146517445048145969719661097737687059782773106751 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable_auto_req_mode.4099472029586153567078795783114651744504814596971966109773
7687059782773106751
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.99506681660868727904609898109839382084884793400459489693581470107678236294966
Short name T850
Test name
Test status
Simulation time 24963823 ps
CPU time 1.14 seconds
Started Nov 01 02:27:14 PM PDT 23
Finished Nov 01 02:27:30 PM PDT 23
Peak memory 230448 kb
Host smart-ada8b12d-5976-4fe1-8e07-0e2c37f81981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99506681660868727904609898109839382084884793400459489693581470107678236294966 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.edn_err.99506681660868727904609898109839382084884793400459489693581470107678236294966
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.3940548841021268640758123147416517160066516340437663448837905102892227198832
Short name T902
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Nov 01 02:26:58 PM PDT 23
Finished Nov 01 02:27:10 PM PDT 23
Peak memory 205884 kb
Host smart-253fc826-4aaa-48a4-ae55-b404a6e527be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940548841021268640758123147416517160066516340437663448837905102892227198832 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.edn_genbits.3940548841021268640758123147416517160066516340437663448837905102892227198832
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.57560317978699034693430190194603940929449500109411415583580784489600303327187
Short name T271
Test name
Test status
Simulation time 18439183 ps
CPU time 1.15 seconds
Started Nov 01 02:26:56 PM PDT 23
Finished Nov 01 02:27:05 PM PDT 23
Peak memory 222136 kb
Host smart-766bfc33-41c6-4577-9b48-6605086a4d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57560317978699034693430190194603940929449500109411415583580784489600303327187 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.edn_intr.57560317978699034693430190194603940929449500109411415583580784489600303327187
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.110668097524446870549388390191881816713539884834574434750382179348326480617220
Short name T684
Test name
Test status
Simulation time 13059183 ps
CPU time 0.88 seconds
Started Nov 01 02:26:50 PM PDT 23
Finished Nov 01 02:26:53 PM PDT 23
Peak memory 205384 kb
Host smart-8e22d656-e0cc-4a72-87f4-6239fc8053ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110668097524446870549388390191881816713539884834574434750382179348326480617220 -assert nopostproc +UVM_TESTNAME=edn_smok
e_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.edn_smoke.110668097524446870549388390191881816713539884834574434750382179348326480617220
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.13940372011414974280926764634551593174767114254381791266687051811448215695109
Short name T461
Test name
Test status
Simulation time 154489183 ps
CPU time 3.93 seconds
Started Nov 01 02:27:02 PM PDT 23
Finished Nov 01 02:27:20 PM PDT 23
Peak memory 206388 kb
Host smart-b0af8d2c-f716-4f99-86c1-4e86936bbc13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13940372011414974280926764634551593174767114254381791266687051811448215695109 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.13940372011414974280926764634551593174767114254381791266687051811448215695109
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.23148113086791364839207769158691538326846770630480721976247698877206470498425
Short name T846
Test name
Test status
Simulation time 41708099183 ps
CPU time 1047.35 seconds
Started Nov 01 02:26:52 PM PDT 23
Finished Nov 01 02:44:23 PM PDT 23
Peak memory 215796 kb
Host smart-7cd395ce-2fa2-4a48-ae69-9d050fab1888
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231481130867913648392077691
58691538326846770630480721976247698877206470498425 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.23148113086
791364839207769158691538326846770630480721976247698877206470498425
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.19365752469658204182375031655579809623712867699831469033013743675172035879858
Short name T804
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 01 02:27:15 PM PDT 23
Finished Nov 01 02:27:30 PM PDT 23
Peak memory 205816 kb
Host smart-b77d9890-8074-4636-b776-1abc65ae025a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19365752469658204182375031655579809623712867699831469033013743675172035879858 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 110.edn_genbits.19365752469658204182375031655579809623712867699831469033013743675172035879858
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.55456861874115949973886275338600206062398537897536625865453442382128985253824
Short name T307
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 01 02:27:41 PM PDT 23
Finished Nov 01 02:27:51 PM PDT 23
Peak memory 205856 kb
Host smart-83c03208-26ec-4f4b-9b2a-0b05e067ffce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55456861874115949973886275338600206062398537897536625865453442382128985253824 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 111.edn_genbits.55456861874115949973886275338600206062398537897536625865453442382128985253824
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.372909549688418041853900271042450775233087570081486936094997619494631401547
Short name T808
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 01 02:27:14 PM PDT 23
Finished Nov 01 02:27:30 PM PDT 23
Peak memory 205824 kb
Host smart-bf0759de-d45a-48a8-82d7-046168ae6fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372909549688418041853900271042450775233087570081486936094997619494631401547 -assert nopostproc +UVM_TESTNAME=edn_genbits
_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 112.edn_genbits.372909549688418041853900271042450775233087570081486936094997619494631401547
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.92694531843525428803195109610594555959518691889555314072867068687095485084398
Short name T509
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 01 02:27:17 PM PDT 23
Finished Nov 01 02:27:31 PM PDT 23
Peak memory 205816 kb
Host smart-ea6fc4c8-fcdc-44de-a210-f41343762a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92694531843525428803195109610594555959518691889555314072867068687095485084398 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 113.edn_genbits.92694531843525428803195109610594555959518691889555314072867068687095485084398
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.114073503180519622116869990525545280715314930969619649833937675637368836302520
Short name T689
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 01 02:27:26 PM PDT 23
Finished Nov 01 02:27:41 PM PDT 23
Peak memory 205692 kb
Host smart-b2162c38-67f0-420e-9c09-47f1f4dd9035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114073503180519622116869990525545280715314930969619649833937675637368836302520 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 114.edn_genbits.114073503180519622116869990525545280715314930969619649833937675637368836302520
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.97923875988744194860979666528181962035321779233479007642167897407992828665711
Short name T336
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 01 02:27:10 PM PDT 23
Finished Nov 01 02:27:26 PM PDT 23
Peak memory 205892 kb
Host smart-18a790dc-673c-403e-9c2f-edfbdeaf564a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97923875988744194860979666528181962035321779233479007642167897407992828665711 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 115.edn_genbits.97923875988744194860979666528181962035321779233479007642167897407992828665711
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.71751942633614388316041505320578018607945599565700485936625512651373341892946
Short name T493
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 01 02:27:15 PM PDT 23
Finished Nov 01 02:27:31 PM PDT 23
Peak memory 205860 kb
Host smart-549f5ad3-0724-4363-a6e7-3410bc256daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71751942633614388316041505320578018607945599565700485936625512651373341892946 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 116.edn_genbits.71751942633614388316041505320578018607945599565700485936625512651373341892946
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.364953675590895920970973907806635891608859853340681662627745876636413936041
Short name T488
Test name
Test status
Simulation time 17999183 ps
CPU time 1.15 seconds
Started Nov 01 02:27:26 PM PDT 23
Finished Nov 01 02:27:42 PM PDT 23
Peak memory 205896 kb
Host smart-733d05b6-0007-47f0-8dd4-e9fd105f73e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364953675590895920970973907806635891608859853340681662627745876636413936041 -assert nopostproc +UVM_TESTNAME=edn_genbits
_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 117.edn_genbits.364953675590895920970973907806635891608859853340681662627745876636413936041
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.44272283339352337006142802609589546764428053689931394970344750024579686186058
Short name T584
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 01 02:27:11 PM PDT 23
Finished Nov 01 02:27:27 PM PDT 23
Peak memory 205856 kb
Host smart-09ca31e4-e776-4614-b5e7-4f76ce55a041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44272283339352337006142802609589546764428053689931394970344750024579686186058 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 118.edn_genbits.44272283339352337006142802609589546764428053689931394970344750024579686186058
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.83971633563196869719860325607305648598998896451139882288943503418563241265967
Short name T794
Test name
Test status
Simulation time 17999183 ps
CPU time 1.05 seconds
Started Nov 01 02:27:54 PM PDT 23
Finished Nov 01 02:27:59 PM PDT 23
Peak memory 204984 kb
Host smart-064b20e1-6cf1-4101-b213-2dae099223b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83971633563196869719860325607305648598998896451139882288943503418563241265967 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 119.edn_genbits.83971633563196869719860325607305648598998896451139882288943503418563241265967
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.46234950376052322116897974106540841092002851779403182237675631871964679787863
Short name T702
Test name
Test status
Simulation time 18259183 ps
CPU time 1 seconds
Started Nov 01 02:26:21 PM PDT 23
Finished Nov 01 02:26:25 PM PDT 23
Peak memory 205492 kb
Host smart-dd27f6e7-1f55-48cb-8f51-3de537c42e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46234950376052322116897974106540841092002851779403182237675631871964679787863 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.edn_alert.46234950376052322116897974106540841092002851779403182237675631871964679787863
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.19585236055778259691210991319168721554101208016613043217921475740978962503173
Short name T807
Test name
Test status
Simulation time 28184990 ps
CPU time 0.89 seconds
Started Nov 01 02:26:02 PM PDT 23
Finished Nov 01 02:26:08 PM PDT 23
Peak memory 205572 kb
Host smart-74c8c63a-9007-4e21-99f9-4c9e1313e0e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19585236055778259691210991319168721554101208016613043217921475740978962503173 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.edn_alert_test.19585236055778259691210991319168721554101208016613043217921475740978962503173
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.79830694671704652767420851270700722872532659647622113577753431789240845560381
Short name T296
Test name
Test status
Simulation time 17319183 ps
CPU time 0.9 seconds
Started Nov 01 02:26:38 PM PDT 23
Finished Nov 01 02:26:42 PM PDT 23
Peak memory 214956 kb
Host smart-7d4fe312-3b14-43c1-ae2d-bd6251685512
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79830694671704652767420851270700722872532659647622113577753431789240845560381 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable_auto_req_mode.7983069467170465276742085127070072287253265964762211357775
3431789240845560381
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.101758496551893347136841474675537833094990002897597100044577250303379728343618
Short name T913
Test name
Test status
Simulation time 24963823 ps
CPU time 1.16 seconds
Started Nov 01 02:26:42 PM PDT 23
Finished Nov 01 02:26:48 PM PDT 23
Peak memory 230524 kb
Host smart-5d58a728-e5c4-41b6-a5af-98dad37fbd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101758496551893347136841474675537833094990002897597100044577250303379728343618 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.edn_err.101758496551893347136841474675537833094990002897597100044577250303379728343618
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.74641651993128873054053157088303803798039838415390638336795759834454969652336
Short name T903
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 01 02:26:59 PM PDT 23
Finished Nov 01 02:27:12 PM PDT 23
Peak memory 205844 kb
Host smart-87960516-6bb0-4d84-b59b-73e4a0474575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74641651993128873054053157088303803798039838415390638336795759834454969652336 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.edn_genbits.74641651993128873054053157088303803798039838415390638336795759834454969652336
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.81806521093138940660965310709426408863119593446829410632882224493691405571486
Short name T740
Test name
Test status
Simulation time 18439183 ps
CPU time 1.15 seconds
Started Nov 01 02:26:36 PM PDT 23
Finished Nov 01 02:26:38 PM PDT 23
Peak memory 222232 kb
Host smart-94db1561-cf68-4ad0-bd9a-2c111227cdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81806521093138940660965310709426408863119593446829410632882224493691405571486 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.edn_intr.81806521093138940660965310709426408863119593446829410632882224493691405571486
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.97840231880999703808291562421092407799724128024650853990099378829202867318406
Short name T388
Test name
Test status
Simulation time 13059183 ps
CPU time 0.89 seconds
Started Nov 01 02:27:02 PM PDT 23
Finished Nov 01 02:27:17 PM PDT 23
Peak memory 205368 kb
Host smart-509b97a8-4738-4330-a06d-4f9986614b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97840231880999703808291562421092407799724128024650853990099378829202867318406 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.edn_smoke.97840231880999703808291562421092407799724128024650853990099378829202867318406
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.35487322572601318821837362443284442654822824752276009685165688219637343158539
Short name T734
Test name
Test status
Simulation time 154489183 ps
CPU time 3.9 seconds
Started Nov 01 02:26:55 PM PDT 23
Finished Nov 01 02:27:06 PM PDT 23
Peak memory 206440 kb
Host smart-f5c61f07-bd98-41c2-91ab-f4947966c131
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35487322572601318821837362443284442654822824752276009685165688219637343158539 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.35487322572601318821837362443284442654822824752276009685165688219637343158539
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.74228751188820653514846570550488803609558915148484469285433960579600010440787
Short name T372
Test name
Test status
Simulation time 41708099183 ps
CPU time 1102.42 seconds
Started Nov 01 02:26:07 PM PDT 23
Finished Nov 01 02:44:35 PM PDT 23
Peak memory 215796 kb
Host smart-eba82351-3985-40a5-88ec-9ec49a336dcb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742287511888206535148465705
50488803609558915148484469285433960579600010440787 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.74228751188
820653514846570550488803609558915148484469285433960579600010440787
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.76207153264878786245533013980852975834121176747318819999282993173563387817612
Short name T248
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 01 02:27:25 PM PDT 23
Finished Nov 01 02:27:40 PM PDT 23
Peak memory 205880 kb
Host smart-0cd3804f-2659-4a4b-a709-b19ddcee26e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76207153264878786245533013980852975834121176747318819999282993173563387817612 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 120.edn_genbits.76207153264878786245533013980852975834121176747318819999282993173563387817612
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.4068671804409826202290290178303362241222612370961553585380140776159552494384
Short name T394
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 01 02:27:12 PM PDT 23
Finished Nov 01 02:27:29 PM PDT 23
Peak memory 205868 kb
Host smart-f4ecb737-fab2-435f-a343-6315160d97d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068671804409826202290290178303362241222612370961553585380140776159552494384 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 121.edn_genbits.4068671804409826202290290178303362241222612370961553585380140776159552494384
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.67785536555454343207598350803333554222008051185605418933531549794512872077373
Short name T887
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 01 02:28:10 PM PDT 23
Finished Nov 01 02:28:12 PM PDT 23
Peak memory 205716 kb
Host smart-708a0ec3-9a9f-4a50-892e-8fc914a3c339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67785536555454343207598350803333554222008051185605418933531549794512872077373 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 122.edn_genbits.67785536555454343207598350803333554222008051185605418933531549794512872077373
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.98127290920946369068127184196203814167938411132575040571744046025745642056924
Short name T595
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 01 02:27:54 PM PDT 23
Finished Nov 01 02:27:59 PM PDT 23
Peak memory 204280 kb
Host smart-33441ee1-3b5a-498a-b4dc-f215003d050e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98127290920946369068127184196203814167938411132575040571744046025745642056924 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 123.edn_genbits.98127290920946369068127184196203814167938411132575040571744046025745642056924
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.98010586024140896847677926004623124951380346643140763708069084742804823575392
Short name T244
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 01 02:27:19 PM PDT 23
Finished Nov 01 02:27:34 PM PDT 23
Peak memory 205860 kb
Host smart-0fc14d57-a76c-4dbc-9df8-0b64c4f32476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98010586024140896847677926004623124951380346643140763708069084742804823575392 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 124.edn_genbits.98010586024140896847677926004623124951380346643140763708069084742804823575392
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.52276879090968263928085816877378091120935799079553009848772016760853398078730
Short name T728
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:28:10 PM PDT 23
Finished Nov 01 02:28:12 PM PDT 23
Peak memory 205716 kb
Host smart-14958810-5929-4ab0-b599-ab77b7767caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52276879090968263928085816877378091120935799079553009848772016760853398078730 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 125.edn_genbits.52276879090968263928085816877378091120935799079553009848772016760853398078730
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.50521697566046144884578418519655732222360189655426158598015784211809544233523
Short name T313
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 01 02:27:25 PM PDT 23
Finished Nov 01 02:27:39 PM PDT 23
Peak memory 205880 kb
Host smart-c5bfc79a-44ea-4855-a591-8b8dc45b36a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50521697566046144884578418519655732222360189655426158598015784211809544233523 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 126.edn_genbits.50521697566046144884578418519655732222360189655426158598015784211809544233523
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.99237929937263689166547324466029199447377854485913750793089179845668078849963
Short name T541
Test name
Test status
Simulation time 17999183 ps
CPU time 1.18 seconds
Started Nov 01 02:27:29 PM PDT 23
Finished Nov 01 02:27:44 PM PDT 23
Peak memory 205912 kb
Host smart-912b57c7-1d43-46da-9b20-60ce83511256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99237929937263689166547324466029199447377854485913750793089179845668078849963 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 127.edn_genbits.99237929937263689166547324466029199447377854485913750793089179845668078849963
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.102688288347911924808415659234980090781753685987578065005045476173397701979099
Short name T478
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:27:23 PM PDT 23
Finished Nov 01 02:27:37 PM PDT 23
Peak memory 205924 kb
Host smart-b2cb6b6f-1de9-4c3e-9174-214a4b30fb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102688288347911924808415659234980090781753685987578065005045476173397701979099 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 128.edn_genbits.102688288347911924808415659234980090781753685987578065005045476173397701979099
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.102528291591963984064298127716608995951917005891556902659933400699821389317613
Short name T829
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 01 02:27:30 PM PDT 23
Finished Nov 01 02:27:45 PM PDT 23
Peak memory 205764 kb
Host smart-e7e3344f-3d5a-4384-9b19-527c52ef215b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102528291591963984064298127716608995951917005891556902659933400699821389317613 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 129.edn_genbits.102528291591963984064298127716608995951917005891556902659933400699821389317613
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert_test.6565443100310185618951711804970086151834784336770527366674092580565377883156
Short name T680
Test name
Test status
Simulation time 28184990 ps
CPU time 0.9 seconds
Started Nov 01 02:26:41 PM PDT 23
Finished Nov 01 02:26:46 PM PDT 23
Peak memory 205232 kb
Host smart-489ecab5-e334-4d51-bde1-666d49a79c22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6565443100310185618951711804970086151834784336770527366674092580565377883156 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.edn_alert_test.6565443100310185618951711804970086151834784336770527366674092580565377883156
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.26675830307441350032728945087245019009692604563228622898695946669915649583644
Short name T600
Test name
Test status
Simulation time 12219183 ps
CPU time 0.94 seconds
Started Nov 01 02:26:35 PM PDT 23
Finished Nov 01 02:26:38 PM PDT 23
Peak memory 214916 kb
Host smart-afe3c960-4729-4ac1-9968-e092febc014c
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26675830307441350032728945087245019009692604563228622898695946669915649583644 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.edn_disable.26675830307441350032728945087245019009692604563228622898695946669915649583644
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.9198591559786991808642703502517333623323582463105956590899793497579067772815
Short name T334
Test name
Test status
Simulation time 17319183 ps
CPU time 0.94 seconds
Started Nov 01 02:26:34 PM PDT 23
Finished Nov 01 02:26:36 PM PDT 23
Peak memory 214844 kb
Host smart-45c7bf1d-7fd5-46d3-851f-4cc29d554c38
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9198591559786991808642703502517333623323582463105956590899793497579067772815 -assert nopostproc
+UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable_auto_req_mode.91985915597869918086427035025173336233235824631059565908997
93497579067772815
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.82081852306126434194890468631538986377932635188116778881844570634318817770123
Short name T851
Test name
Test status
Simulation time 24963823 ps
CPU time 1.17 seconds
Started Nov 01 02:26:36 PM PDT 23
Finished Nov 01 02:26:38 PM PDT 23
Peak memory 230504 kb
Host smart-66886643-fcff-4405-80d7-cb9848363726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82081852306126434194890468631538986377932635188116778881844570634318817770123 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.edn_err.82081852306126434194890468631538986377932635188116778881844570634318817770123
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.18869037947463231725276545494793383210280914385768054013800683690783520836433
Short name T524
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 01 02:26:39 PM PDT 23
Finished Nov 01 02:26:43 PM PDT 23
Peak memory 205908 kb
Host smart-6075ef5c-9acf-4475-89e1-6364cc9fa580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18869037947463231725276545494793383210280914385768054013800683690783520836433 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.edn_genbits.18869037947463231725276545494793383210280914385768054013800683690783520836433
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.7108747768904666117686582462251356990606579123713881196470671209138527613715
Short name T797
Test name
Test status
Simulation time 18439183 ps
CPU time 1.14 seconds
Started Nov 01 02:26:36 PM PDT 23
Finished Nov 01 02:26:39 PM PDT 23
Peak memory 222240 kb
Host smart-964a1af9-6f71-43b7-bbfb-0509e35c174e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7108747768904666117686582462251356990606579123713881196470671209138527613715 -assert nopostproc +UVM_TESTNAME=edn_intr_t
est +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.edn_intr.7108747768904666117686582462251356990606579123713881196470671209138527613715
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.67843056343393638937271359312219790327560002533151048944486229116816623008318
Short name T258
Test name
Test status
Simulation time 13059183 ps
CPU time 0.88 seconds
Started Nov 01 02:26:04 PM PDT 23
Finished Nov 01 02:26:08 PM PDT 23
Peak memory 205428 kb
Host smart-adc72563-f32e-4386-9609-d207cee12534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67843056343393638937271359312219790327560002533151048944486229116816623008318 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.edn_smoke.67843056343393638937271359312219790327560002533151048944486229116816623008318
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.81714498311432092371390304544630879205699525134075413586606383034701265974927
Short name T552
Test name
Test status
Simulation time 154489183 ps
CPU time 4.07 seconds
Started Nov 01 02:26:22 PM PDT 23
Finished Nov 01 02:26:28 PM PDT 23
Peak memory 206324 kb
Host smart-32983f76-6618-497b-b900-9017721d4134
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81714498311432092371390304544630879205699525134075413586606383034701265974927 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.81714498311432092371390304544630879205699525134075413586606383034701265974927
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.10612511423680318664802594314321292671442496101771358215351330562337057448462
Short name T589
Test name
Test status
Simulation time 41708099183 ps
CPU time 1120.7 seconds
Started Nov 01 02:26:08 PM PDT 23
Finished Nov 01 02:44:53 PM PDT 23
Peak memory 215884 kb
Host smart-9a36d98d-107f-448a-8646-772a117aee96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106125114236803186648025943
14321292671442496101771358215351330562337057448462 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.10612511423
680318664802594314321292671442496101771358215351330562337057448462
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.13453194233104376135855646890990112051512155250899207201973628813308924425388
Short name T831
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 01 02:27:19 PM PDT 23
Finished Nov 01 02:27:35 PM PDT 23
Peak memory 205888 kb
Host smart-e5136c83-e203-4840-9e3a-ee5006eecf16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13453194233104376135855646890990112051512155250899207201973628813308924425388 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 130.edn_genbits.13453194233104376135855646890990112051512155250899207201973628813308924425388
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.85374104360847311436994030089994059529068280755292482928869489614722531683679
Short name T289
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:27:19 PM PDT 23
Finished Nov 01 02:27:35 PM PDT 23
Peak memory 205688 kb
Host smart-78a2c74c-3ee7-43c9-aac5-00fed145f90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85374104360847311436994030089994059529068280755292482928869489614722531683679 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 131.edn_genbits.85374104360847311436994030089994059529068280755292482928869489614722531683679
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.101963301711364762550245596309912369112733121895646350983240396087854466664808
Short name T321
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:27:24 PM PDT 23
Finished Nov 01 02:27:38 PM PDT 23
Peak memory 205828 kb
Host smart-b44378e0-39ad-4793-8cd6-3134ec209dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101963301711364762550245596309912369112733121895646350983240396087854466664808 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 132.edn_genbits.101963301711364762550245596309912369112733121895646350983240396087854466664808
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.30269599501020935976234223967979441192508202341051220178499530816535984323631
Short name T405
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:27:35 PM PDT 23
Finished Nov 01 02:27:47 PM PDT 23
Peak memory 205824 kb
Host smart-e0d1eacc-2160-4767-a64a-371a6771811e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30269599501020935976234223967979441192508202341051220178499530816535984323631 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 133.edn_genbits.30269599501020935976234223967979441192508202341051220178499530816535984323631
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.89125041342915505726726267355491534798813570659583459875960046190031441628596
Short name T484
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 01 02:27:24 PM PDT 23
Finished Nov 01 02:27:38 PM PDT 23
Peak memory 205872 kb
Host smart-8be91cb3-6409-4073-8fb0-dfbab30834f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89125041342915505726726267355491534798813570659583459875960046190031441628596 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 134.edn_genbits.89125041342915505726726267355491534798813570659583459875960046190031441628596
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.30501361748208030088102576199005967939415552225056108918914012386423089973806
Short name T262
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 01 02:27:03 PM PDT 23
Finished Nov 01 02:27:19 PM PDT 23
Peak memory 205808 kb
Host smart-b8c689d3-6a18-4ac1-b717-885fb2adc667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30501361748208030088102576199005967939415552225056108918914012386423089973806 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 135.edn_genbits.30501361748208030088102576199005967939415552225056108918914012386423089973806
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.57159762021910765790309881337833254798274267480700090577497071863341679050282
Short name T309
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:27:27 PM PDT 23
Finished Nov 01 02:27:42 PM PDT 23
Peak memory 205900 kb
Host smart-0aec2e55-ef39-45ad-afb6-22752bcfc708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57159762021910765790309881337833254798274267480700090577497071863341679050282 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 136.edn_genbits.57159762021910765790309881337833254798274267480700090577497071863341679050282
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.78085270967898564193596378671081464316192703261916019947526137264174468813625
Short name T579
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:27:08 PM PDT 23
Finished Nov 01 02:27:25 PM PDT 23
Peak memory 205812 kb
Host smart-4b052d76-7403-4bef-acec-966f27ea0a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78085270967898564193596378671081464316192703261916019947526137264174468813625 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 137.edn_genbits.78085270967898564193596378671081464316192703261916019947526137264174468813625
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.68251864168093349078603696993118026538043095009464094776307417304482363658261
Short name T588
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 01 02:26:52 PM PDT 23
Finished Nov 01 02:26:58 PM PDT 23
Peak memory 205788 kb
Host smart-3285ca4c-5a90-430b-b2b3-6b95c41caf58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68251864168093349078603696993118026538043095009464094776307417304482363658261 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 138.edn_genbits.68251864168093349078603696993118026538043095009464094776307417304482363658261
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.91260599444621295353239382137897242355643214666036299168832027903297256633699
Short name T626
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 01 02:27:33 PM PDT 23
Finished Nov 01 02:27:46 PM PDT 23
Peak memory 205824 kb
Host smart-ce61f657-25d0-4a89-89a3-13fa8bdbff10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91260599444621295353239382137897242355643214666036299168832027903297256633699 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 139.edn_genbits.91260599444621295353239382137897242355643214666036299168832027903297256633699
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.74680233265624256132095767335326124820457888972688137805289719287833678198330
Short name T801
Test name
Test status
Simulation time 18259183 ps
CPU time 1.01 seconds
Started Nov 01 02:26:42 PM PDT 23
Finished Nov 01 02:26:47 PM PDT 23
Peak memory 205608 kb
Host smart-68f34709-b26e-45e8-a0e2-e2cebeddcd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74680233265624256132095767335326124820457888972688137805289719287833678198330 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.edn_alert.74680233265624256132095767335326124820457888972688137805289719287833678198330
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.59486519979622843368473032415142458932755709552334980599751503892739101792405
Short name T393
Test name
Test status
Simulation time 28184990 ps
CPU time 0.91 seconds
Started Nov 01 02:26:07 PM PDT 23
Finished Nov 01 02:26:13 PM PDT 23
Peak memory 205556 kb
Host smart-eb398c55-4d27-4800-bceb-eb501362d734
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59486519979622843368473032415142458932755709552334980599751503892739101792405 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.edn_alert_test.59486519979622843368473032415142458932755709552334980599751503892739101792405
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.2860903522957632484311734771177357770920658103456656320541466894774878123961
Short name T547
Test name
Test status
Simulation time 12219183 ps
CPU time 0.94 seconds
Started Nov 01 02:26:38 PM PDT 23
Finished Nov 01 02:26:42 PM PDT 23
Peak memory 214936 kb
Host smart-128c77a3-5953-48a7-a21f-368a400145cc
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860903522957632484311734771177357770920658103456656320541466894774878123961 -assert nopostproc
+UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.edn_disable.2860903522957632484311734771177357770920658103456656320541466894774878123961
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.64321989324726553089055624940783178847059635847272971241088923771508583343851
Short name T875
Test name
Test status
Simulation time 17319183 ps
CPU time 0.94 seconds
Started Nov 01 02:26:41 PM PDT 23
Finished Nov 01 02:26:46 PM PDT 23
Peak memory 214708 kb
Host smart-dd2a507a-927a-43cd-b664-4714b75b2116
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64321989324726553089055624940783178847059635847272971241088923771508583343851 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable_auto_req_mode.6432198932472655308905562494078317884705963584727297124108
8923771508583343851
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.99304393855059322678954326804086153631659739641438797611650193655421170232393
Short name T873
Test name
Test status
Simulation time 24963823 ps
CPU time 1.17 seconds
Started Nov 01 02:26:45 PM PDT 23
Finished Nov 01 02:26:50 PM PDT 23
Peak memory 230516 kb
Host smart-2b8f0ddc-7afe-4a5b-82e6-a445ec846624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99304393855059322678954326804086153631659739641438797611650193655421170232393 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.edn_err.99304393855059322678954326804086153631659739641438797611650193655421170232393
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.42615382407594775508194841258960564574191359574825840587889647277599085314635
Short name T470
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 01 02:26:08 PM PDT 23
Finished Nov 01 02:26:13 PM PDT 23
Peak memory 205780 kb
Host smart-96e1599c-05ba-440c-a7f3-d17825a9727c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42615382407594775508194841258960564574191359574825840587889647277599085314635 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.edn_genbits.42615382407594775508194841258960564574191359574825840587889647277599085314635
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.10398390888796314588689162246177763888406214207388160764223375726606656627345
Short name T280
Test name
Test status
Simulation time 18439183 ps
CPU time 1.13 seconds
Started Nov 01 02:26:36 PM PDT 23
Finished Nov 01 02:26:38 PM PDT 23
Peak memory 222232 kb
Host smart-1efa82fe-1564-42c4-8afc-5c6ae513f9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10398390888796314588689162246177763888406214207388160764223375726606656627345 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.edn_intr.10398390888796314588689162246177763888406214207388160764223375726606656627345
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.70975050997103018940490389136566180525035191628186870381186801567449967112545
Short name T346
Test name
Test status
Simulation time 13059183 ps
CPU time 0.9 seconds
Started Nov 01 02:26:01 PM PDT 23
Finished Nov 01 02:26:08 PM PDT 23
Peak memory 205264 kb
Host smart-8fb672a9-f391-4424-be55-c427826c1c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70975050997103018940490389136566180525035191628186870381186801567449967112545 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.edn_smoke.70975050997103018940490389136566180525035191628186870381186801567449967112545
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.18598238888039624873116130815830440381729346196135807058117720679908115087318
Short name T529
Test name
Test status
Simulation time 154489183 ps
CPU time 4 seconds
Started Nov 01 02:26:09 PM PDT 23
Finished Nov 01 02:26:17 PM PDT 23
Peak memory 206444 kb
Host smart-2d46ce8f-378a-429f-8250-8781176aaac2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18598238888039624873116130815830440381729346196135807058117720679908115087318 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.18598238888039624873116130815830440381729346196135807058117720679908115087318
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.23719072515225207121659493951993381656725313438666817957866410374241407417958
Short name T648
Test name
Test status
Simulation time 41708099183 ps
CPU time 1111.43 seconds
Started Nov 01 02:26:03 PM PDT 23
Finished Nov 01 02:44:38 PM PDT 23
Peak memory 215944 kb
Host smart-b451b490-b89f-4f7b-a150-e91a31a3d872
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237190725152252071216594939
51993381656725313438666817957866410374241407417958 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.23719072515
225207121659493951993381656725313438666817957866410374241407417958
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.845517080180392498429471419591092092861339132748592889712965742077574183187
Short name T789
Test name
Test status
Simulation time 17999183 ps
CPU time 1.15 seconds
Started Nov 01 02:27:00 PM PDT 23
Finished Nov 01 02:27:15 PM PDT 23
Peak memory 205904 kb
Host smart-b66910e7-f51d-41fc-8cab-54fabc910c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845517080180392498429471419591092092861339132748592889712965742077574183187 -assert nopostproc +UVM_TESTNAME=edn_genbits
_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 140.edn_genbits.845517080180392498429471419591092092861339132748592889712965742077574183187
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.29110586803760334348023316826429540495903563844339795947542716837459810834762
Short name T315
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 01 02:27:00 PM PDT 23
Finished Nov 01 02:27:15 PM PDT 23
Peak memory 205884 kb
Host smart-4f77e203-774c-467a-88a0-473c2d03789e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29110586803760334348023316826429540495903563844339795947542716837459810834762 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 141.edn_genbits.29110586803760334348023316826429540495903563844339795947542716837459810834762
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.25132845817395345680009822423983936766860811940905769024659605661495878712953
Short name T905
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:26:55 PM PDT 23
Finished Nov 01 02:27:02 PM PDT 23
Peak memory 205796 kb
Host smart-48fd4476-27c8-4253-b709-14a7e7508bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25132845817395345680009822423983936766860811940905769024659605661495878712953 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 142.edn_genbits.25132845817395345680009822423983936766860811940905769024659605661495878712953
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.8232691761704699840246567152343292422565821552024762869223833683414455223555
Short name T460
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 01 02:27:15 PM PDT 23
Finished Nov 01 02:27:30 PM PDT 23
Peak memory 205880 kb
Host smart-900374c3-37da-4680-856f-14f61191596e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8232691761704699840246567152343292422565821552024762869223833683414455223555 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 143.edn_genbits.8232691761704699840246567152343292422565821552024762869223833683414455223555
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.114995292966781633572577952990112392339735291667892111065181023873238237602486
Short name T897
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:26:58 PM PDT 23
Finished Nov 01 02:27:10 PM PDT 23
Peak memory 205812 kb
Host smart-4fc55fc1-dec0-4a55-b4b5-3f1c8ae951eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114995292966781633572577952990112392339735291667892111065181023873238237602486 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 144.edn_genbits.114995292966781633572577952990112392339735291667892111065181023873238237602486
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.102432450430261301287926730785662618843935976220328664060948064504930722342721
Short name T351
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:26:56 PM PDT 23
Finished Nov 01 02:27:06 PM PDT 23
Peak memory 205852 kb
Host smart-45d6738b-f57b-4f88-93cd-f56719fc2fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102432450430261301287926730785662618843935976220328664060948064504930722342721 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 145.edn_genbits.102432450430261301287926730785662618843935976220328664060948064504930722342721
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.66475262863525597723623911163239175508857169575650762639210365558312724947856
Short name T427
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:26:59 PM PDT 23
Finished Nov 01 02:27:12 PM PDT 23
Peak memory 205900 kb
Host smart-8e345d50-b694-4f43-871e-1d59bec23269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66475262863525597723623911163239175508857169575650762639210365558312724947856 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 146.edn_genbits.66475262863525597723623911163239175508857169575650762639210365558312724947856
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.15752165518571052740201191890237262698208916236845204690656723043585770283904
Short name T834
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:27:06 PM PDT 23
Finished Nov 01 02:27:22 PM PDT 23
Peak memory 205908 kb
Host smart-60827751-5296-431a-8da1-c63e21bd395b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15752165518571052740201191890237262698208916236845204690656723043585770283904 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 147.edn_genbits.15752165518571052740201191890237262698208916236845204690656723043585770283904
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.19671320156869097202461782223915706632434969015376978867179675644854077783481
Short name T760
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 01 02:27:04 PM PDT 23
Finished Nov 01 02:27:19 PM PDT 23
Peak memory 205908 kb
Host smart-2ce98286-2534-4e69-a2cc-8153083031e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19671320156869097202461782223915706632434969015376978867179675644854077783481 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 148.edn_genbits.19671320156869097202461782223915706632434969015376978867179675644854077783481
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.41483369123747490307354739479566894209785232873475436556868717684877905434164
Short name T878
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 01 02:27:07 PM PDT 23
Finished Nov 01 02:27:23 PM PDT 23
Peak memory 205932 kb
Host smart-3c764757-4945-4d5f-a824-470e68d6ec96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41483369123747490307354739479566894209785232873475436556868717684877905434164 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 149.edn_genbits.41483369123747490307354739479566894209785232873475436556868717684877905434164
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.107985991768259931799127889526253621096279749854557632149928387257331052088307
Short name T817
Test name
Test status
Simulation time 18259183 ps
CPU time 1.05 seconds
Started Nov 01 02:26:51 PM PDT 23
Finished Nov 01 02:26:54 PM PDT 23
Peak memory 205644 kb
Host smart-df86d727-ba5d-4fa6-a1b6-b6aec9ed2d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107985991768259931799127889526253621096279749854557632149928387257331052088307 -assert nopostproc +UVM_TESTNAME=edn_aler
t_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.edn_alert.107985991768259931799127889526253621096279749854557632149928387257331052088307
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.86684485031443776157482852299221216438029122908819059618818568073078298117119
Short name T364
Test name
Test status
Simulation time 28184990 ps
CPU time 0.88 seconds
Started Nov 01 02:26:49 PM PDT 23
Finished Nov 01 02:26:52 PM PDT 23
Peak memory 205484 kb
Host smart-46e30847-99aa-478a-bf66-9804fff4f66c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86684485031443776157482852299221216438029122908819059618818568073078298117119 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.edn_alert_test.86684485031443776157482852299221216438029122908819059618818568073078298117119
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.45852694372959449069932215803048697559326275140329376035843136269557563612994
Short name T63
Test name
Test status
Simulation time 12219183 ps
CPU time 0.88 seconds
Started Nov 01 02:26:55 PM PDT 23
Finished Nov 01 02:27:11 PM PDT 23
Peak memory 214912 kb
Host smart-582d3598-d636-4219-9c2b-fdd86a7a8cbc
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45852694372959449069932215803048697559326275140329376035843136269557563612994 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.edn_disable.45852694372959449069932215803048697559326275140329376035843136269557563612994
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.73498127461839847653769141270241012890076335888728156002447836052949476560022
Short name T371
Test name
Test status
Simulation time 17319183 ps
CPU time 0.95 seconds
Started Nov 01 02:26:41 PM PDT 23
Finished Nov 01 02:26:47 PM PDT 23
Peak memory 214916 kb
Host smart-7d07c2c1-4438-4518-8c59-c11d87696324
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73498127461839847653769141270241012890076335888728156002447836052949476560022 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable_auto_req_mode.7349812746183984765376914127024101289007633588872815600244
7836052949476560022
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.53409462643317839285075039535608764023599206880567218374542848067367880869286
Short name T473
Test name
Test status
Simulation time 24963823 ps
CPU time 1.13 seconds
Started Nov 01 02:26:41 PM PDT 23
Finished Nov 01 02:26:47 PM PDT 23
Peak memory 230416 kb
Host smart-85f57961-0397-469c-867d-46ba2532c666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53409462643317839285075039535608764023599206880567218374542848067367880869286 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.edn_err.53409462643317839285075039535608764023599206880567218374542848067367880869286
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.98622677125339691363467019261014382748415529583624493213029409683638248181552
Short name T331
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:26:58 PM PDT 23
Finished Nov 01 02:27:11 PM PDT 23
Peak memory 205904 kb
Host smart-64860eff-7308-4760-8118-a539d020ab4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98622677125339691363467019261014382748415529583624493213029409683638248181552 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.edn_genbits.98622677125339691363467019261014382748415529583624493213029409683638248181552
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.44654348550892074673134450782275169481275566738061038613368243930238297650915
Short name T665
Test name
Test status
Simulation time 18439183 ps
CPU time 1.12 seconds
Started Nov 01 02:26:49 PM PDT 23
Finished Nov 01 02:26:53 PM PDT 23
Peak memory 222252 kb
Host smart-81f71813-f1ff-48ad-a2ee-1227c75b53e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44654348550892074673134450782275169481275566738061038613368243930238297650915 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.edn_intr.44654348550892074673134450782275169481275566738061038613368243930238297650915
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.95476691190799487828712306465676683416868129513619364791606010444799203078359
Short name T673
Test name
Test status
Simulation time 13059183 ps
CPU time 0.89 seconds
Started Nov 01 02:26:12 PM PDT 23
Finished Nov 01 02:26:15 PM PDT 23
Peak memory 205320 kb
Host smart-07599a5b-5a0d-4b34-b6c1-4c3e19d36367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95476691190799487828712306465676683416868129513619364791606010444799203078359 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.edn_smoke.95476691190799487828712306465676683416868129513619364791606010444799203078359
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.69689431555652825690351120557484153435567619350696705510015337134340225963481
Short name T710
Test name
Test status
Simulation time 154489183 ps
CPU time 3.87 seconds
Started Nov 01 02:26:08 PM PDT 23
Finished Nov 01 02:26:16 PM PDT 23
Peak memory 206228 kb
Host smart-a05ee60a-5910-42ce-b7f2-09619247f804
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69689431555652825690351120557484153435567619350696705510015337134340225963481 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.69689431555652825690351120557484153435567619350696705510015337134340225963481
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.36090925734426994968217144687320529909165465694721252842744123876039232384980
Short name T705
Test name
Test status
Simulation time 41708099183 ps
CPU time 1092.93 seconds
Started Nov 01 02:26:57 PM PDT 23
Finished Nov 01 02:45:20 PM PDT 23
Peak memory 215856 kb
Host smart-6d73bb1d-77ee-4691-9109-e90a3cd1016a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360909257344269949682171446
87320529909165465694721252842744123876039232384980 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.36090925734
426994968217144687320529909165465694721252842744123876039232384980
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.14142286740532515607187558863759624170532896571738939459085616168090557706778
Short name T787
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 01 02:27:05 PM PDT 23
Finished Nov 01 02:27:21 PM PDT 23
Peak memory 205908 kb
Host smart-cc003369-78bb-49b6-b2ba-83943a1a9042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14142286740532515607187558863759624170532896571738939459085616168090557706778 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 150.edn_genbits.14142286740532515607187558863759624170532896571738939459085616168090557706778
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.68839908180363497234921087545589900349177257887447719638374613588232204223313
Short name T278
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:27:12 PM PDT 23
Finished Nov 01 02:27:28 PM PDT 23
Peak memory 205892 kb
Host smart-1b3e13fe-f267-41ce-b48c-5dc7cab243b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68839908180363497234921087545589900349177257887447719638374613588232204223313 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 151.edn_genbits.68839908180363497234921087545589900349177257887447719638374613588232204223313
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.5807369750923678924148068753901256981701688909651211949064094962990448077698
Short name T91
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:27:03 PM PDT 23
Finished Nov 01 02:27:18 PM PDT 23
Peak memory 205896 kb
Host smart-4524866b-0dc4-411c-a4be-127cbd394194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5807369750923678924148068753901256981701688909651211949064094962990448077698 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 152.edn_genbits.5807369750923678924148068753901256981701688909651211949064094962990448077698
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.37985493297575002389319907520204229480617322981459275891302395859276770686266
Short name T266
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 01 02:27:05 PM PDT 23
Finished Nov 01 02:27:21 PM PDT 23
Peak memory 205920 kb
Host smart-343fa6d2-86b2-4235-9fa4-46031ab45440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37985493297575002389319907520204229480617322981459275891302395859276770686266 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 153.edn_genbits.37985493297575002389319907520204229480617322981459275891302395859276770686266
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.39535040850217953420697773317090167586643084600401276216790958775012521252502
Short name T288
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 01 02:27:02 PM PDT 23
Finished Nov 01 02:27:17 PM PDT 23
Peak memory 205896 kb
Host smart-bb0b16eb-82ca-44ec-b467-f6979c5fb5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39535040850217953420697773317090167586643084600401276216790958775012521252502 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 154.edn_genbits.39535040850217953420697773317090167586643084600401276216790958775012521252502
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.115138803446470482553079236338063608866746036296391918205683495659594454445690
Short name T703
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 01 02:27:08 PM PDT 23
Finished Nov 01 02:27:25 PM PDT 23
Peak memory 205844 kb
Host smart-f4ce8911-b4cc-4ac9-8322-acca482822ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115138803446470482553079236338063608866746036296391918205683495659594454445690 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 155.edn_genbits.115138803446470482553079236338063608866746036296391918205683495659594454445690
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.15835194949261679604985063105627789682979799563735431658708076800438612874543
Short name T614
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 01 02:27:03 PM PDT 23
Finished Nov 01 02:27:18 PM PDT 23
Peak memory 205896 kb
Host smart-897ab601-cb4c-46aa-9e63-095244d9bf8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15835194949261679604985063105627789682979799563735431658708076800438612874543 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 156.edn_genbits.15835194949261679604985063105627789682979799563735431658708076800438612874543
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.79484202076366172105867300613215468128040956550912552928704631402607852333678
Short name T245
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:27:11 PM PDT 23
Finished Nov 01 02:27:28 PM PDT 23
Peak memory 205908 kb
Host smart-bb857906-a251-4fca-acfa-e0ae7434ccb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79484202076366172105867300613215468128040956550912552928704631402607852333678 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 157.edn_genbits.79484202076366172105867300613215468128040956550912552928704631402607852333678
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.17963693736476240734085945115661072162520176802523076497535671284591029364243
Short name T955
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 01 02:27:10 PM PDT 23
Finished Nov 01 02:27:26 PM PDT 23
Peak memory 205852 kb
Host smart-e24376a7-328c-4d45-9b18-75fc3948b3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17963693736476240734085945115661072162520176802523076497535671284591029364243 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 158.edn_genbits.17963693736476240734085945115661072162520176802523076497535671284591029364243
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.59543595972271198041835025300092729127519315620899958411687537221702376922735
Short name T772
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 01 02:26:56 PM PDT 23
Finished Nov 01 02:27:05 PM PDT 23
Peak memory 205900 kb
Host smart-a22f0e76-29c5-424a-b151-255f5a669980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59543595972271198041835025300092729127519315620899958411687537221702376922735 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 159.edn_genbits.59543595972271198041835025300092729127519315620899958411687537221702376922735
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.11919405293579799052165720459536744307922762667442660995277417220858305059013
Short name T279
Test name
Test status
Simulation time 18259183 ps
CPU time 1.03 seconds
Started Nov 01 02:26:51 PM PDT 23
Finished Nov 01 02:26:54 PM PDT 23
Peak memory 205516 kb
Host smart-a608da01-1cb4-4010-929c-0d1f6746d038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11919405293579799052165720459536744307922762667442660995277417220858305059013 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.edn_alert.11919405293579799052165720459536744307922762667442660995277417220858305059013
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.100516333816950937019618882451470631412174350947243328159490486655044087787371
Short name T860
Test name
Test status
Simulation time 28184990 ps
CPU time 0.92 seconds
Started Nov 01 02:27:13 PM PDT 23
Finished Nov 01 02:27:30 PM PDT 23
Peak memory 205484 kb
Host smart-273df8fe-edcd-434b-9705-74c9dbd4a41d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100516333816950937019618882451470631412174350947243328159490486655044087787371 -assert nopostp
roc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 16.edn_alert_test.100516333816950937019618882451470631412174350947243328159490486655044087787371
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.14448412953034340794483025019884875104782575482381917015716969845832205084961
Short name T723
Test name
Test status
Simulation time 12219183 ps
CPU time 0.86 seconds
Started Nov 01 02:26:56 PM PDT 23
Finished Nov 01 02:27:05 PM PDT 23
Peak memory 215032 kb
Host smart-e3a41a41-9088-47f0-a73a-bbc088687823
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14448412953034340794483025019884875104782575482381917015716969845832205084961 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.edn_disable.14448412953034340794483025019884875104782575482381917015716969845832205084961
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.96642301943439560959448526505786475215249596719016399803115850671354044916532
Short name T900
Test name
Test status
Simulation time 17319183 ps
CPU time 0.91 seconds
Started Nov 01 02:26:57 PM PDT 23
Finished Nov 01 02:27:08 PM PDT 23
Peak memory 214932 kb
Host smart-0edf511c-8ba1-4c67-b979-7e4f13b486f6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96642301943439560959448526505786475215249596719016399803115850671354044916532 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable_auto_req_mode.9664230194343956095944852650578647521524959671901639980311
5850671354044916532
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.81502077522437697442592476366800474352379002943531311936893897480933751800347
Short name T368
Test name
Test status
Simulation time 24963823 ps
CPU time 1.16 seconds
Started Nov 01 02:26:56 PM PDT 23
Finished Nov 01 02:27:06 PM PDT 23
Peak memory 229716 kb
Host smart-facee62e-5b2b-43cc-b283-ba3c9161b428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81502077522437697442592476366800474352379002943531311936893897480933751800347 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.edn_err.81502077522437697442592476366800474352379002943531311936893897480933751800347
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.94988559761483869312180595747202793425599034094381207963907009995761650861793
Short name T457
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:26:51 PM PDT 23
Finished Nov 01 02:26:56 PM PDT 23
Peak memory 205768 kb
Host smart-daf8b854-20c5-478d-bc03-09ce219b2827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94988559761483869312180595747202793425599034094381207963907009995761650861793 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.edn_genbits.94988559761483869312180595747202793425599034094381207963907009995761650861793
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.47876804620367210599833747297102305742523690787786151081869230769408413577501
Short name T311
Test name
Test status
Simulation time 18439183 ps
CPU time 1.08 seconds
Started Nov 01 02:26:58 PM PDT 23
Finished Nov 01 02:27:09 PM PDT 23
Peak memory 222312 kb
Host smart-42b861ac-2cfc-40ba-9efa-521d9f59afe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47876804620367210599833747297102305742523690787786151081869230769408413577501 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.edn_intr.47876804620367210599833747297102305742523690787786151081869230769408413577501
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.113230047931450901674721253144076524382602769456032111789268568851083159299438
Short name T463
Test name
Test status
Simulation time 13059183 ps
CPU time 0.9 seconds
Started Nov 01 02:26:42 PM PDT 23
Finished Nov 01 02:26:48 PM PDT 23
Peak memory 205316 kb
Host smart-cecd8c4a-86a3-44c8-910c-f1b093e14ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113230047931450901674721253144076524382602769456032111789268568851083159299438 -assert nopostproc +UVM_TESTNAME=edn_smok
e_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.edn_smoke.113230047931450901674721253144076524382602769456032111789268568851083159299438
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.109286037470309976951509055371097389619778262174782355233424858684283204362172
Short name T503
Test name
Test status
Simulation time 154489183 ps
CPU time 4.04 seconds
Started Nov 01 02:26:56 PM PDT 23
Finished Nov 01 02:27:09 PM PDT 23
Peak memory 206304 kb
Host smart-939bc024-cc0e-4ab5-b7f1-156147bc31ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109286037470309976951509055371097389619778262174782355233424858684283204362172 -assert nopo
stproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.109286037470309976951509055371097389619778262174782355233424858684283204362172
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/160.edn_genbits.855031624212130502170946835308275870068370678546102159497193197415195208614
Short name T548
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 01 02:27:17 PM PDT 23
Finished Nov 01 02:27:32 PM PDT 23
Peak memory 205876 kb
Host smart-6bd8d6d1-e867-4a92-bc74-566b97de2f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855031624212130502170946835308275870068370678546102159497193197415195208614 -assert nopostproc +UVM_TESTNAME=edn_genbits
_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 160.edn_genbits.855031624212130502170946835308275870068370678546102159497193197415195208614
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.37587064959946101134079243710123910428986086186010410907276116990589403831327
Short name T237
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:27:14 PM PDT 23
Finished Nov 01 02:27:30 PM PDT 23
Peak memory 205892 kb
Host smart-7afb4e09-6256-4c67-8345-7fc98e10df0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37587064959946101134079243710123910428986086186010410907276116990589403831327 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 161.edn_genbits.37587064959946101134079243710123910428986086186010410907276116990589403831327
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.49724609219184274792389548215427798217256883045144323996693423207105557866621
Short name T477
Test name
Test status
Simulation time 17999183 ps
CPU time 1.05 seconds
Started Nov 01 02:27:41 PM PDT 23
Finished Nov 01 02:27:51 PM PDT 23
Peak memory 205856 kb
Host smart-325a6bb9-8d6f-4cf1-9600-9e178e639ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49724609219184274792389548215427798217256883045144323996693423207105557866621 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 162.edn_genbits.49724609219184274792389548215427798217256883045144323996693423207105557866621
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.64095170837823419127261326470812996803348210647524099242392871726189690532024
Short name T317
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 01 02:27:05 PM PDT 23
Finished Nov 01 02:27:21 PM PDT 23
Peak memory 205824 kb
Host smart-b72a7783-07db-4237-80ee-6a2fef4114b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64095170837823419127261326470812996803348210647524099242392871726189690532024 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 163.edn_genbits.64095170837823419127261326470812996803348210647524099242392871726189690532024
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.43046225342055830893414642697762564296072188183302699663212961474398696201856
Short name T504
Test name
Test status
Simulation time 17999183 ps
CPU time 1.06 seconds
Started Nov 01 02:27:11 PM PDT 23
Finished Nov 01 02:27:27 PM PDT 23
Peak memory 205728 kb
Host smart-8095b42b-8e22-496a-b1c0-20013facdf5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43046225342055830893414642697762564296072188183302699663212961474398696201856 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 164.edn_genbits.43046225342055830893414642697762564296072188183302699663212961474398696201856
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.32477204966888393550280848067662275704349386497400133226075006408653634710809
Short name T433
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 01 02:27:23 PM PDT 23
Finished Nov 01 02:27:38 PM PDT 23
Peak memory 205860 kb
Host smart-8ae077db-7100-4c4a-b8e7-84867a9491e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32477204966888393550280848067662275704349386497400133226075006408653634710809 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 165.edn_genbits.32477204966888393550280848067662275704349386497400133226075006408653634710809
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.78499459540704873033723699988665999428280241465209266171673285993967398764809
Short name T696
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:27:26 PM PDT 23
Finished Nov 01 02:27:41 PM PDT 23
Peak memory 205816 kb
Host smart-87398341-932a-491a-a07a-eace01d66b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78499459540704873033723699988665999428280241465209266171673285993967398764809 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 166.edn_genbits.78499459540704873033723699988665999428280241465209266171673285993967398764809
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.10653465268164858878771908168417073703832148353803478713129168721738841011291
Short name T551
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:27:29 PM PDT 23
Finished Nov 01 02:27:44 PM PDT 23
Peak memory 205784 kb
Host smart-07089128-bdf5-437f-a408-da622bf37fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10653465268164858878771908168417073703832148353803478713129168721738841011291 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 167.edn_genbits.10653465268164858878771908168417073703832148353803478713129168721738841011291
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.1288721576371631652804708689523226943911835576003522450062086859161494670259
Short name T570
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 01 02:27:29 PM PDT 23
Finished Nov 01 02:27:44 PM PDT 23
Peak memory 205772 kb
Host smart-a2473c08-8f3f-43f6-8c95-865e5f19bae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288721576371631652804708689523226943911835576003522450062086859161494670259 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 168.edn_genbits.1288721576371631652804708689523226943911835576003522450062086859161494670259
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.94777260333821816721878734388231900062483482106530242844319474020346136717998
Short name T725
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 01 02:27:03 PM PDT 23
Finished Nov 01 02:27:19 PM PDT 23
Peak memory 205824 kb
Host smart-77508830-1d5a-4cf5-8115-546964caabf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94777260333821816721878734388231900062483482106530242844319474020346136717998 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 169.edn_genbits.94777260333821816721878734388231900062483482106530242844319474020346136717998
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.68272354415859218535571298608946545232763594045208555406645583567051948011560
Short name T796
Test name
Test status
Simulation time 18259183 ps
CPU time 0.97 seconds
Started Nov 01 02:26:59 PM PDT 23
Finished Nov 01 02:27:12 PM PDT 23
Peak memory 205636 kb
Host smart-910ea0fc-f9bc-4191-a58f-df3f15ea6294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68272354415859218535571298608946545232763594045208555406645583567051948011560 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.edn_alert.68272354415859218535571298608946545232763594045208555406645583567051948011560
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.3437914330948981268557321576488574388631180584531640516232207501431599365450
Short name T885
Test name
Test status
Simulation time 28184990 ps
CPU time 0.89 seconds
Started Nov 01 02:26:32 PM PDT 23
Finished Nov 01 02:26:33 PM PDT 23
Peak memory 205524 kb
Host smart-bcb7cc79-e6e4-431b-8ddc-1d0372b86f15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437914330948981268557321576488574388631180584531640516232207501431599365450 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.edn_alert_test.3437914330948981268557321576488574388631180584531640516232207501431599365450
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.214822261496656143785754160744328634315262319878941003969116287181749228468
Short name T64
Test name
Test status
Simulation time 12219183 ps
CPU time 0.86 seconds
Started Nov 01 02:27:21 PM PDT 23
Finished Nov 01 02:27:35 PM PDT 23
Peak memory 214868 kb
Host smart-e068534d-5b2d-415b-9df1-776e575ec038
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214822261496656143785754160744328634315262319878941003969116287181749228468 -assert nopostproc
+UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 17.edn_disable.214822261496656143785754160744328634315262319878941003969116287181749228468
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.88777842824565034513025032680168072924485041253266715466721901592993634414699
Short name T432
Test name
Test status
Simulation time 17319183 ps
CPU time 0.94 seconds
Started Nov 01 02:27:02 PM PDT 23
Finished Nov 01 02:27:17 PM PDT 23
Peak memory 214884 kb
Host smart-32f7208f-cb3f-41bf-a2ae-7a058cd95892
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88777842824565034513025032680168072924485041253266715466721901592993634414699 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable_auto_req_mode.8877784282456503451302503268016807292448504125326671546672
1901592993634414699
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.58749708673755733936407516876787632952223421784794124145954780686117196234866
Short name T538
Test name
Test status
Simulation time 24963823 ps
CPU time 1.18 seconds
Started Nov 01 02:27:15 PM PDT 23
Finished Nov 01 02:27:31 PM PDT 23
Peak memory 230568 kb
Host smart-ca8d3a35-caca-4049-8387-edaf9534e426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58749708673755733936407516876787632952223421784794124145954780686117196234866 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.edn_err.58749708673755733936407516876787632952223421784794124145954780686117196234866
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.81595658011659278609245253021422542663866353532094313909562952679111753541491
Short name T927
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:26:59 PM PDT 23
Finished Nov 01 02:27:11 PM PDT 23
Peak memory 205832 kb
Host smart-f5a5248c-70eb-4edc-b358-719a6c63438a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81595658011659278609245253021422542663866353532094313909562952679111753541491 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.edn_genbits.81595658011659278609245253021422542663866353532094313909562952679111753541491
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.5777705222639713353165165990882659220560502312735910892542066714494927452698
Short name T601
Test name
Test status
Simulation time 18439183 ps
CPU time 1.12 seconds
Started Nov 01 02:26:58 PM PDT 23
Finished Nov 01 02:27:10 PM PDT 23
Peak memory 221940 kb
Host smart-3922fb76-2164-469a-88f4-64fbb6cc4473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5777705222639713353165165990882659220560502312735910892542066714494927452698 -assert nopostproc +UVM_TESTNAME=edn_intr_t
est +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.edn_intr.5777705222639713353165165990882659220560502312735910892542066714494927452698
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.104909612118098215625425969171837936378284805440242449943040246201296312110686
Short name T257
Test name
Test status
Simulation time 13059183 ps
CPU time 0.89 seconds
Started Nov 01 02:27:05 PM PDT 23
Finished Nov 01 02:27:22 PM PDT 23
Peak memory 205360 kb
Host smart-634874f6-e449-44f0-9d4a-29d2264e0f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104909612118098215625425969171837936378284805440242449943040246201296312110686 -assert nopostproc +UVM_TESTNAME=edn_smok
e_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.edn_smoke.104909612118098215625425969171837936378284805440242449943040246201296312110686
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.87620479782462344113920549446060101707160464943200174698848965375070372976457
Short name T857
Test name
Test status
Simulation time 154489183 ps
CPU time 3.94 seconds
Started Nov 01 02:26:54 PM PDT 23
Finished Nov 01 02:27:04 PM PDT 23
Peak memory 206440 kb
Host smart-0f1ac2e2-d386-4573-be37-bfdd0349b2f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87620479782462344113920549446060101707160464943200174698848965375070372976457 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.87620479782462344113920549446060101707160464943200174698848965375070372976457
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.115637712051816726370441528135720710716040537351288945585268775795292635752459
Short name T895
Test name
Test status
Simulation time 41708099183 ps
CPU time 1076.14 seconds
Started Nov 01 02:27:03 PM PDT 23
Finished Nov 01 02:45:14 PM PDT 23
Peak memory 215860 kb
Host smart-f3aae6c7-f4e2-4b95-a2e8-c73a8683d0b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115637712051816726370441528
135720710716040537351288945585268775795292635752459 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.1156377120
51816726370441528135720710716040537351288945585268775795292635752459
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.93717874370690750098274376390889117840732420942005387284316213457522775435065
Short name T464
Test name
Test status
Simulation time 17999183 ps
CPU time 1.02 seconds
Started Nov 01 02:27:25 PM PDT 23
Finished Nov 01 02:27:39 PM PDT 23
Peak memory 205676 kb
Host smart-3b8a01e9-1c97-45ad-9b57-b5001d05b628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93717874370690750098274376390889117840732420942005387284316213457522775435065 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 170.edn_genbits.93717874370690750098274376390889117840732420942005387284316213457522775435065
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.97681018615010813349156295350235903777288770535481934910088738451338210404700
Short name T746
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:27:20 PM PDT 23
Finished Nov 01 02:27:35 PM PDT 23
Peak memory 205864 kb
Host smart-d5d8e5e0-5f71-495d-a953-2c7eb339ae50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97681018615010813349156295350235903777288770535481934910088738451338210404700 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 171.edn_genbits.97681018615010813349156295350235903777288770535481934910088738451338210404700
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.53878682439099754226205176771777423715628507638993617738809761102727652285089
Short name T243
Test name
Test status
Simulation time 17999183 ps
CPU time 1.16 seconds
Started Nov 01 02:27:28 PM PDT 23
Finished Nov 01 02:27:43 PM PDT 23
Peak memory 205880 kb
Host smart-0a333602-3434-4e82-9095-cd6a26aeb0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53878682439099754226205176771777423715628507638993617738809761102727652285089 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 172.edn_genbits.53878682439099754226205176771777423715628507638993617738809761102727652285089
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.46655183410694462636675225598185443134868463460646095236213319819046033445564
Short name T456
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 01 02:27:29 PM PDT 23
Finished Nov 01 02:27:43 PM PDT 23
Peak memory 205880 kb
Host smart-247d0c79-87eb-4d0f-b5d4-d928f42159d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46655183410694462636675225598185443134868463460646095236213319819046033445564 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 173.edn_genbits.46655183410694462636675225598185443134868463460646095236213319819046033445564
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.35832100119754386860861355211943569593383288292064610677784857172353052922350
Short name T951
Test name
Test status
Simulation time 17999183 ps
CPU time 1.04 seconds
Started Nov 01 02:27:24 PM PDT 23
Finished Nov 01 02:27:38 PM PDT 23
Peak memory 205672 kb
Host smart-a6a01b42-76b4-404d-8932-502e1ea62b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35832100119754386860861355211943569593383288292064610677784857172353052922350 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 174.edn_genbits.35832100119754386860861355211943569593383288292064610677784857172353052922350
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.110881438970184253443129396629034440241402837583794145610957753806946376836358
Short name T332
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Nov 01 02:27:25 PM PDT 23
Finished Nov 01 02:27:39 PM PDT 23
Peak memory 205908 kb
Host smart-0bf08300-87ca-4954-a50f-20f8807e7c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110881438970184253443129396629034440241402837583794145610957753806946376836358 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 175.edn_genbits.110881438970184253443129396629034440241402837583794145610957753806946376836358
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.115706407979191443193523739280826388131473991461145894593572887814677597163643
Short name T435
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:27:18 PM PDT 23
Finished Nov 01 02:27:33 PM PDT 23
Peak memory 205884 kb
Host smart-63bf1f0e-2e59-4782-87e2-28649f5337de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115706407979191443193523739280826388131473991461145894593572887814677597163643 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 176.edn_genbits.115706407979191443193523739280826388131473991461145894593572887814677597163643
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.21024576112958199829648851887927703932658237523908079742927008169709835288847
Short name T251
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:27:25 PM PDT 23
Finished Nov 01 02:27:40 PM PDT 23
Peak memory 205980 kb
Host smart-1d068677-52e5-482d-8a26-48365d77c9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21024576112958199829648851887927703932658237523908079742927008169709835288847 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 177.edn_genbits.21024576112958199829648851887927703932658237523908079742927008169709835288847
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.36629014066099071134449097723032015833916735324133979939657398472637142744732
Short name T766
Test name
Test status
Simulation time 17999183 ps
CPU time 1.15 seconds
Started Nov 01 02:27:23 PM PDT 23
Finished Nov 01 02:27:38 PM PDT 23
Peak memory 205768 kb
Host smart-6062d8f8-7691-41cc-84dd-56d3dee94766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36629014066099071134449097723032015833916735324133979939657398472637142744732 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 178.edn_genbits.36629014066099071134449097723032015833916735324133979939657398472637142744732
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.10919375743714818157391247872343666037675100096612728074815011506663452121724
Short name T912
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Nov 01 02:27:20 PM PDT 23
Finished Nov 01 02:27:35 PM PDT 23
Peak memory 205824 kb
Host smart-1b60e87d-5ae7-4cd0-a810-a4961740604c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10919375743714818157391247872343666037675100096612728074815011506663452121724 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 179.edn_genbits.10919375743714818157391247872343666037675100096612728074815011506663452121724
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.41986739718524648772700802276782702727184582130814833284607663385823414041799
Short name T338
Test name
Test status
Simulation time 18259183 ps
CPU time 0.98 seconds
Started Nov 01 02:27:19 PM PDT 23
Finished Nov 01 02:27:34 PM PDT 23
Peak memory 205580 kb
Host smart-cc4bde90-b4ec-4e21-896c-18b8a6abd8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41986739718524648772700802276782702727184582130814833284607663385823414041799 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.edn_alert.41986739718524648772700802276782702727184582130814833284607663385823414041799
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.18381300638264993352531231030784294594024394846733502134358986772879026673222
Short name T866
Test name
Test status
Simulation time 28184990 ps
CPU time 0.89 seconds
Started Nov 01 02:26:38 PM PDT 23
Finished Nov 01 02:26:40 PM PDT 23
Peak memory 205540 kb
Host smart-47e2ab9e-3f5a-45b7-ab20-329dcc868e98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18381300638264993352531231030784294594024394846733502134358986772879026673222 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.edn_alert_test.18381300638264993352531231030784294594024394846733502134358986772879026673222
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.61893743223983019077818312392192624156981708772160561019256373802874061903636
Short name T553
Test name
Test status
Simulation time 12219183 ps
CPU time 0.89 seconds
Started Nov 01 02:26:07 PM PDT 23
Finished Nov 01 02:26:13 PM PDT 23
Peak memory 214912 kb
Host smart-e5b731e5-18ee-4a53-be60-2885a2f201bb
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61893743223983019077818312392192624156981708772160561019256373802874061903636 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.edn_disable.61893743223983019077818312392192624156981708772160561019256373802874061903636
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.52412327592364917144593274459900519961064362465161391911925088595723740828666
Short name T661
Test name
Test status
Simulation time 17319183 ps
CPU time 0.91 seconds
Started Nov 01 02:26:01 PM PDT 23
Finished Nov 01 02:26:08 PM PDT 23
Peak memory 214724 kb
Host smart-d6c25afa-1acf-40e5-8050-e6a9c07c1d81
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52412327592364917144593274459900519961064362465161391911925088595723740828666 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable_auto_req_mode.5241232759236491714459327445990051996106436246516139191192
5088595723740828666
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_genbits.54247320035490750227425649889210435630091343591808949168365624711915212002667
Short name T458
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 01 02:27:04 PM PDT 23
Finished Nov 01 02:27:19 PM PDT 23
Peak memory 205908 kb
Host smart-4339567a-2611-4ad4-86a4-5252a49a40cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54247320035490750227425649889210435630091343591808949168365624711915212002667 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.edn_genbits.54247320035490750227425649889210435630091343591808949168365624711915212002667
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.62912532532405173106828466027823604823921355676857510877437637709893701296003
Short name T719
Test name
Test status
Simulation time 18439183 ps
CPU time 1.12 seconds
Started Nov 01 02:27:24 PM PDT 23
Finished Nov 01 02:27:42 PM PDT 23
Peak memory 222196 kb
Host smart-0df693fd-9831-47f0-bc10-00161f5ec38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62912532532405173106828466027823604823921355676857510877437637709893701296003 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.edn_intr.62912532532405173106828466027823604823921355676857510877437637709893701296003
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.31572339387839731506017659729247239666307894137230754153165119027073580958848
Short name T391
Test name
Test status
Simulation time 13059183 ps
CPU time 0.85 seconds
Started Nov 01 02:26:59 PM PDT 23
Finished Nov 01 02:27:11 PM PDT 23
Peak memory 205280 kb
Host smart-f47381ae-1a06-4331-b798-9431d10f8d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31572339387839731506017659729247239666307894137230754153165119027073580958848 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.edn_smoke.31572339387839731506017659729247239666307894137230754153165119027073580958848
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.42129488052058404237554319384799242151558050558240807932823342097679219970443
Short name T774
Test name
Test status
Simulation time 154489183 ps
CPU time 3.87 seconds
Started Nov 01 02:27:19 PM PDT 23
Finished Nov 01 02:27:37 PM PDT 23
Peak memory 206372 kb
Host smart-1543f78f-3526-4292-8fd0-cf3ddce5a975
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42129488052058404237554319384799242151558050558240807932823342097679219970443 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.42129488052058404237554319384799242151558050558240807932823342097679219970443
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.112267551909639323557334603908702762332855087643313156837557331726160027531299
Short name T780
Test name
Test status
Simulation time 41708099183 ps
CPU time 1094.33 seconds
Started Nov 01 02:27:10 PM PDT 23
Finished Nov 01 02:45:40 PM PDT 23
Peak memory 215908 kb
Host smart-b8cafe53-fe12-4498-b287-06fd7e28c635
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112267551909639323557334603
908702762332855087643313156837557331726160027531299 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.1122675519
09639323557334603908702762332855087643313156837557331726160027531299
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.54231316269092369862059617528161708831377112599863812867253811552920364820890
Short name T729
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 01 02:27:27 PM PDT 23
Finished Nov 01 02:27:42 PM PDT 23
Peak memory 205880 kb
Host smart-4521974f-f706-4a68-a90c-707d4b591795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54231316269092369862059617528161708831377112599863812867253811552920364820890 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 180.edn_genbits.54231316269092369862059617528161708831377112599863812867253811552920364820890
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.8198605033601130048862625286888889449057019448482737417243873972168213905212
Short name T240
Test name
Test status
Simulation time 17999183 ps
CPU time 1.15 seconds
Started Nov 01 02:27:24 PM PDT 23
Finished Nov 01 02:27:39 PM PDT 23
Peak memory 205880 kb
Host smart-270858f6-4439-4f3b-96fc-2eb3a7defc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8198605033601130048862625286888889449057019448482737417243873972168213905212 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 181.edn_genbits.8198605033601130048862625286888889449057019448482737417243873972168213905212
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.14177900069473223183246519928603736047658543711796313286648638927961949222438
Short name T646
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:27:10 PM PDT 23
Finished Nov 01 02:27:26 PM PDT 23
Peak memory 205840 kb
Host smart-afa1ce4d-4024-435a-b063-948805004cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14177900069473223183246519928603736047658543711796313286648638927961949222438 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 182.edn_genbits.14177900069473223183246519928603736047658543711796313286648638927961949222438
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.93028451780478988078805098125372223231316238794421259241549566425746265322661
Short name T423
Test name
Test status
Simulation time 17999183 ps
CPU time 1.19 seconds
Started Nov 01 02:27:27 PM PDT 23
Finished Nov 01 02:27:43 PM PDT 23
Peak memory 205880 kb
Host smart-6b15ed7f-f00a-41a7-a642-60dced9b2a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93028451780478988078805098125372223231316238794421259241549566425746265322661 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 183.edn_genbits.93028451780478988078805098125372223231316238794421259241549566425746265322661
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.103228821914754164305924498026475961788218254712652876831006893889687473758961
Short name T510
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 01 02:27:10 PM PDT 23
Finished Nov 01 02:27:26 PM PDT 23
Peak memory 205888 kb
Host smart-fb592f1c-e5fb-44c2-b0d0-9503303e06b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103228821914754164305924498026475961788218254712652876831006893889687473758961 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 184.edn_genbits.103228821914754164305924498026475961788218254712652876831006893889687473758961
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.107636915757429411234093314592781574412789750936965265689570456041509116004129
Short name T585
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 01 02:27:23 PM PDT 23
Finished Nov 01 02:27:38 PM PDT 23
Peak memory 205796 kb
Host smart-79a0c26e-a436-4c08-b6f7-2f4723fb15cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107636915757429411234093314592781574412789750936965265689570456041509116004129 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 185.edn_genbits.107636915757429411234093314592781574412789750936965265689570456041509116004129
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.88834083595122104550507258132090702616775962664103817017152394190351216880806
Short name T688
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:27:27 PM PDT 23
Finished Nov 01 02:27:42 PM PDT 23
Peak memory 205808 kb
Host smart-2b0f9117-4441-4ad8-b42f-bd4a4e2fad22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88834083595122104550507258132090702616775962664103817017152394190351216880806 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 186.edn_genbits.88834083595122104550507258132090702616775962664103817017152394190351216880806
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.94089042417564095698756398098437592171809800292467183885684653108486637644028
Short name T730
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 01 02:27:18 PM PDT 23
Finished Nov 01 02:27:33 PM PDT 23
Peak memory 205792 kb
Host smart-7cfa2f61-416f-4097-82b4-2068d3017eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94089042417564095698756398098437592171809800292467183885684653108486637644028 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 187.edn_genbits.94089042417564095698756398098437592171809800292467183885684653108486637644028
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.26562078056285333527184396336022855577252600205482880533447496076095277361825
Short name T653
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 01 02:27:17 PM PDT 23
Finished Nov 01 02:27:31 PM PDT 23
Peak memory 205792 kb
Host smart-5f5b7441-c14b-4733-b79e-eeb2319f9929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26562078056285333527184396336022855577252600205482880533447496076095277361825 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 188.edn_genbits.26562078056285333527184396336022855577252600205482880533447496076095277361825
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.104000040973961330609931067554147647757700758895211340423677772836629653958605
Short name T556
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Nov 01 02:27:23 PM PDT 23
Finished Nov 01 02:27:42 PM PDT 23
Peak memory 205796 kb
Host smart-bb052ceb-d145-487e-96db-1ba651e6ac5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104000040973961330609931067554147647757700758895211340423677772836629653958605 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 189.edn_genbits.104000040973961330609931067554147647757700758895211340423677772836629653958605
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.63713293613026783221760260490612051335646364044187341214459112455281289281037
Short name T472
Test name
Test status
Simulation time 18259183 ps
CPU time 1.02 seconds
Started Nov 01 02:26:38 PM PDT 23
Finished Nov 01 02:26:41 PM PDT 23
Peak memory 205636 kb
Host smart-767dd342-704a-4a41-9b28-9f63a496f53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63713293613026783221760260490612051335646364044187341214459112455281289281037 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.edn_alert.63713293613026783221760260490612051335646364044187341214459112455281289281037
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.41374917206576623362872152858705039825019646920594523184203082918430847604540
Short name T445
Test name
Test status
Simulation time 28184990 ps
CPU time 0.86 seconds
Started Nov 01 02:26:05 PM PDT 23
Finished Nov 01 02:26:09 PM PDT 23
Peak memory 205524 kb
Host smart-9d298082-2f5e-4281-801d-a707c5034ba2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41374917206576623362872152858705039825019646920594523184203082918430847604540 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.edn_alert_test.41374917206576623362872152858705039825019646920594523184203082918430847604540
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.39947176576395238194068257922829123280813639235809839275257637277817579274743
Short name T848
Test name
Test status
Simulation time 12219183 ps
CPU time 0.88 seconds
Started Nov 01 02:26:37 PM PDT 23
Finished Nov 01 02:26:39 PM PDT 23
Peak memory 214928 kb
Host smart-d93c05f8-0b22-4bb5-896d-9a4fa00af94f
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39947176576395238194068257922829123280813639235809839275257637277817579274743 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.edn_disable.39947176576395238194068257922829123280813639235809839275257637277817579274743
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.71920597396954157845557569481069524716717864623000856111353015262723798222978
Short name T418
Test name
Test status
Simulation time 17319183 ps
CPU time 0.92 seconds
Started Nov 01 02:26:37 PM PDT 23
Finished Nov 01 02:26:39 PM PDT 23
Peak memory 214816 kb
Host smart-5605d615-5283-4158-a369-0d370007ed90
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71920597396954157845557569481069524716717864623000856111353015262723798222978 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable_auto_req_mode.7192059739695415784555756948106952471671786462300085611135
3015262723798222978
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.78479947858187153431602787752498734298224089739974156105779213956186583127152
Short name T549
Test name
Test status
Simulation time 24963823 ps
CPU time 1.22 seconds
Started Nov 01 02:26:07 PM PDT 23
Finished Nov 01 02:26:12 PM PDT 23
Peak memory 230500 kb
Host smart-79c04192-d8e8-44b4-8aac-39dc25efdc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78479947858187153431602787752498734298224089739974156105779213956186583127152 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.edn_err.78479947858187153431602787752498734298224089739974156105779213956186583127152
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.71682919698970833799035926049753900666082375749479037189083382261648745328074
Short name T805
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Nov 01 02:26:37 PM PDT 23
Finished Nov 01 02:26:39 PM PDT 23
Peak memory 205912 kb
Host smart-74f257c6-99ae-4f7f-ac46-7e4d25ebfef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71682919698970833799035926049753900666082375749479037189083382261648745328074 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.edn_genbits.71682919698970833799035926049753900666082375749479037189083382261648745328074
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.38388067370814289855981926193179787267931845229598324646527885354074617663545
Short name T554
Test name
Test status
Simulation time 18439183 ps
CPU time 1.13 seconds
Started Nov 01 02:26:06 PM PDT 23
Finished Nov 01 02:26:12 PM PDT 23
Peak memory 222348 kb
Host smart-d5e55946-7fb1-4867-a550-b3e0a9acf713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38388067370814289855981926193179787267931845229598324646527885354074617663545 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.edn_intr.38388067370814289855981926193179787267931845229598324646527885354074617663545
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.79129579094423716869834363253944337574400588974169966030808833733292619987543
Short name T915
Test name
Test status
Simulation time 13059183 ps
CPU time 0.89 seconds
Started Nov 01 02:26:06 PM PDT 23
Finished Nov 01 02:26:11 PM PDT 23
Peak memory 205388 kb
Host smart-1dbae29b-6320-4d0c-b6ad-cbac35606d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79129579094423716869834363253944337574400588974169966030808833733292619987543 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.edn_smoke.79129579094423716869834363253944337574400588974169966030808833733292619987543
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.110145033219881266927612943346608772388968312113914323301047669989658230310944
Short name T654
Test name
Test status
Simulation time 154489183 ps
CPU time 4.08 seconds
Started Nov 01 02:26:03 PM PDT 23
Finished Nov 01 02:26:11 PM PDT 23
Peak memory 206444 kb
Host smart-b55f4cdd-7a1c-4cea-8269-95fcf8d85647
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110145033219881266927612943346608772388968312113914323301047669989658230310944 -assert nopo
stproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.110145033219881266927612943346608772388968312113914323301047669989658230310944
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.3278254350978753822791724019122196534850905637197496588649113667975731794948
Short name T830
Test name
Test status
Simulation time 41708099183 ps
CPU time 1094.48 seconds
Started Nov 01 02:26:05 PM PDT 23
Finished Nov 01 02:44:22 PM PDT 23
Peak memory 215924 kb
Host smart-4b72504b-0032-45a6-a3af-3bd9e5d99ea3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327825435097875382279172401
9122196534850905637197496588649113667975731794948 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.327825435097
8753822791724019122196534850905637197496588649113667975731794948
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.101889368805722353904288613513608627225231894586312020471021272692319246369046
Short name T749
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 01 02:27:26 PM PDT 23
Finished Nov 01 02:27:40 PM PDT 23
Peak memory 205876 kb
Host smart-45aa6416-9970-40fb-bcf0-625a5d8d7398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101889368805722353904288613513608627225231894586312020471021272692319246369046 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 190.edn_genbits.101889368805722353904288613513608627225231894586312020471021272692319246369046
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.58223794700867963148759405609934295156870184457170015646559965180530855229634
Short name T505
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:27:38 PM PDT 23
Finished Nov 01 02:27:49 PM PDT 23
Peak memory 205892 kb
Host smart-ba770267-5e0f-418b-aeda-9b88ad13f145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58223794700867963148759405609934295156870184457170015646559965180530855229634 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 191.edn_genbits.58223794700867963148759405609934295156870184457170015646559965180530855229634
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.75022549914174932753322135953505332777259978304884963860304860347482212873974
Short name T379
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:27:19 PM PDT 23
Finished Nov 01 02:27:34 PM PDT 23
Peak memory 205880 kb
Host smart-d9aa9f5a-d10f-4c5a-b33a-068a6e674fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75022549914174932753322135953505332777259978304884963860304860347482212873974 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 192.edn_genbits.75022549914174932753322135953505332777259978304884963860304860347482212873974
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.103235551252351374650924299066824021870806660884042180758070157201876705907226
Short name T517
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:27:09 PM PDT 23
Finished Nov 01 02:27:26 PM PDT 23
Peak memory 205804 kb
Host smart-c3f6a1b6-c902-4ea2-a1e8-7e331b3fb977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103235551252351374650924299066824021870806660884042180758070157201876705907226 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 193.edn_genbits.103235551252351374650924299066824021870806660884042180758070157201876705907226
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.31318606471980846844507451097979418032955380210071325627630760475128576029128
Short name T50
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Nov 01 02:27:14 PM PDT 23
Finished Nov 01 02:27:30 PM PDT 23
Peak memory 205892 kb
Host smart-479d4e02-319d-438a-b023-318d32304e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31318606471980846844507451097979418032955380210071325627630760475128576029128 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 194.edn_genbits.31318606471980846844507451097979418032955380210071325627630760475128576029128
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.43749803027829883382110202760948976990202824434345490966211661938910121424308
Short name T769
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:27:46 PM PDT 23
Finished Nov 01 02:27:54 PM PDT 23
Peak memory 205816 kb
Host smart-a3f212a8-dc72-4cf9-8408-ce6ec90e2849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43749803027829883382110202760948976990202824434345490966211661938910121424308 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 195.edn_genbits.43749803027829883382110202760948976990202824434345490966211661938910121424308
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.105839394305372830601877475354698716820379990977875595497952621616109547998328
Short name T720
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:27:07 PM PDT 23
Finished Nov 01 02:27:23 PM PDT 23
Peak memory 205916 kb
Host smart-3790abea-1a03-4072-b536-5aaefe404ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105839394305372830601877475354698716820379990977875595497952621616109547998328 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 196.edn_genbits.105839394305372830601877475354698716820379990977875595497952621616109547998328
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.69547926877831067687496029480250545551545521295260614347539837764146323645660
Short name T782
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:27:27 PM PDT 23
Finished Nov 01 02:27:43 PM PDT 23
Peak memory 205880 kb
Host smart-b127576e-a5db-4f8f-823a-772ddd7966be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69547926877831067687496029480250545551545521295260614347539837764146323645660 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 197.edn_genbits.69547926877831067687496029480250545551545521295260614347539837764146323645660
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.77775679662052737868711994607780321370352440457315306617852182357941749646151
Short name T474
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:27:21 PM PDT 23
Finished Nov 01 02:27:36 PM PDT 23
Peak memory 205792 kb
Host smart-c2f24522-2e14-4064-8afd-5b2a6a551b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77775679662052737868711994607780321370352440457315306617852182357941749646151 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 198.edn_genbits.77775679662052737868711994607780321370352440457315306617852182357941749646151
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.60436773528192094094236091968806115723197042236388569203686838538916044372385
Short name T358
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 01 02:27:18 PM PDT 23
Finished Nov 01 02:27:34 PM PDT 23
Peak memory 205880 kb
Host smart-03514c5e-66e2-4d6d-8432-0090c3f98f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60436773528192094094236091968806115723197042236388569203686838538916044372385 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 199.edn_genbits.60436773528192094094236091968806115723197042236388569203686838538916044372385
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.87550598259100770465962080010974177763285747572773826461530895890089054461601
Short name T335
Test name
Test status
Simulation time 18259183 ps
CPU time 1.02 seconds
Started Nov 01 02:25:48 PM PDT 23
Finished Nov 01 02:25:58 PM PDT 23
Peak memory 205640 kb
Host smart-51d533ea-71f2-49c0-bbd4-57649f1420eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87550598259100770465962080010974177763285747572773826461530895890089054461601 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.edn_alert.87550598259100770465962080010974177763285747572773826461530895890089054461601
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.37444632147582109709029384917156160717718913509760351249321113603506828520316
Short name T841
Test name
Test status
Simulation time 28184990 ps
CPU time 0.86 seconds
Started Nov 01 02:25:49 PM PDT 23
Finished Nov 01 02:25:58 PM PDT 23
Peak memory 205520 kb
Host smart-f37a5ca9-d685-49b7-aad5-09f864d4a573
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37444632147582109709029384917156160717718913509760351249321113603506828520316 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.edn_alert_test.37444632147582109709029384917156160717718913509760351249321113603506828520316
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.60201444379639924137253310219969826788263708774139339324906288088240231555632
Short name T18
Test name
Test status
Simulation time 12219183 ps
CPU time 0.89 seconds
Started Nov 01 02:25:48 PM PDT 23
Finished Nov 01 02:25:58 PM PDT 23
Peak memory 214940 kb
Host smart-8aad1881-1c3a-42ec-987a-83e2c444047d
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60201444379639924137253310219969826788263708774139339324906288088240231555632 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.edn_disable.60201444379639924137253310219969826788263708774139339324906288088240231555632
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.32508400976804477649887564852005380278487749784433162258555057330635671662184
Short name T23
Test name
Test status
Simulation time 17319183 ps
CPU time 0.94 seconds
Started Nov 01 02:25:46 PM PDT 23
Finished Nov 01 02:25:48 PM PDT 23
Peak memory 214912 kb
Host smart-078229f4-cc55-4479-9ea5-fc10ab199a63
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32508400976804477649887564852005380278487749784433162258555057330635671662184 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable_auto_req_mode.32508400976804477649887564852005380278487749784433162258555
057330635671662184
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.98685405926092317659875323017737504948248172377853988917779898790805494539415
Short name T966
Test name
Test status
Simulation time 24963823 ps
CPU time 1.13 seconds
Started Nov 01 02:25:50 PM PDT 23
Finished Nov 01 02:25:58 PM PDT 23
Peak memory 230500 kb
Host smart-f01481fd-1405-49a1-9c16-762c8fd93119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98685405926092317659875323017737504948248172377853988917779898790805494539415 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
edn_err.98685405926092317659875323017737504948248172377853988917779898790805494539415
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.85260760511083634758009735429269209204925580921772812671521469110250341630782
Short name T942
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:25:45 PM PDT 23
Finished Nov 01 02:25:48 PM PDT 23
Peak memory 205776 kb
Host smart-9ef54d74-a41a-4a9c-a24a-7cbfa48913d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85260760511083634758009735429269209204925580921772812671521469110250341630782 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.edn_genbits.85260760511083634758009735429269209204925580921772812671521469110250341630782
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.7118651097912652063369589362095583238649404377204092519049718427386844305311
Short name T361
Test name
Test status
Simulation time 18439183 ps
CPU time 1.1 seconds
Started Nov 01 02:25:51 PM PDT 23
Finished Nov 01 02:25:58 PM PDT 23
Peak memory 222368 kb
Host smart-4155b5e0-8fb5-4cd4-bdff-59da855bf1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7118651097912652063369589362095583238649404377204092519049718427386844305311 -assert nopostproc +UVM_TESTNAME=edn_intr_t
est +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.edn_intr.7118651097912652063369589362095583238649404377204092519049718427386844305311
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.84078601937113466175487147059596165073886040626529818633932026430046849720649
Short name T95
Test name
Test status
Simulation time 11759183 ps
CPU time 0.87 seconds
Started Nov 01 02:25:48 PM PDT 23
Finished Nov 01 02:25:58 PM PDT 23
Peak memory 205328 kb
Host smart-1752e5bc-87b3-4afc-9c07-8f2b2ac18169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84078601937113466175487147059596165073886040626529818633932026430046849720649 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.edn_regwen.84078601937113466175487147059596165073886040626529818633932026430046849720649
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.33469853543819872458139030803694883646118892872505108695518966694708742587922
Short name T47
Test name
Test status
Simulation time 717215632 ps
CPU time 6 seconds
Started Nov 01 02:25:49 PM PDT 23
Finished Nov 01 02:26:03 PM PDT 23
Peak memory 234100 kb
Host smart-f8d53904-0363-4076-9f78-b45d64af4882
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33469853543819872458139030803694883646118892872505108695518966694708742587922 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.edn_sec_cm.33469853543819872458139030803694883646118892872505108695518966694708742587922
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.61259534538974765554768832631652787056592401236386419600091083922974379282184
Short name T395
Test name
Test status
Simulation time 13059183 ps
CPU time 0.88 seconds
Started Nov 01 02:25:39 PM PDT 23
Finished Nov 01 02:25:41 PM PDT 23
Peak memory 205428 kb
Host smart-282e4490-39fc-49fd-9213-93410154b964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61259534538974765554768832631652787056592401236386419600091083922974379282184 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.edn_smoke.61259534538974765554768832631652787056592401236386419600091083922974379282184
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.93027824947170487327881839466998815267128643908107936550537186497919835145419
Short name T250
Test name
Test status
Simulation time 41708099183 ps
CPU time 1088.3 seconds
Started Nov 01 02:25:39 PM PDT 23
Finished Nov 01 02:43:48 PM PDT 23
Peak memory 215872 kb
Host smart-6f880a06-9cdc-4894-ace2-0457c388f297
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930278249471704873278818394
66998815267128643908107936550537186497919835145419 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.930278249471
70487327881839466998815267128643908107936550537186497919835145419
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.83363734218785340277795807134068167031219745830304506606754261135998613432620
Short name T11
Test name
Test status
Simulation time 18259183 ps
CPU time 1.01 seconds
Started Nov 01 02:26:39 PM PDT 23
Finished Nov 01 02:26:44 PM PDT 23
Peak memory 205620 kb
Host smart-dde43b3a-1d40-4281-a4b4-2e69cccc8355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83363734218785340277795807134068167031219745830304506606754261135998613432620 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 20.edn_alert.83363734218785340277795807134068167031219745830304506606754261135998613432620
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.99667560109149237622983862025620778006703251003152861251566180896722025409236
Short name T352
Test name
Test status
Simulation time 28184990 ps
CPU time 0.88 seconds
Started Nov 01 02:26:34 PM PDT 23
Finished Nov 01 02:26:36 PM PDT 23
Peak memory 205516 kb
Host smart-6281f8e0-f293-4be4-bb65-77275a26545b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99667560109149237622983862025620778006703251003152861251566180896722025409236 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.edn_alert_test.99667560109149237622983862025620778006703251003152861251566180896722025409236
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.102355824462676189770394613675886397078818820836712651418414191818772264411945
Short name T28
Test name
Test status
Simulation time 12219183 ps
CPU time 0.87 seconds
Started Nov 01 02:26:32 PM PDT 23
Finished Nov 01 02:26:34 PM PDT 23
Peak memory 214888 kb
Host smart-06b9ff18-2845-474b-b7e1-ee3b79e6833b
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102355824462676189770394613675886397078818820836712651418414191818772264411945 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 20.edn_disable.102355824462676189770394613675886397078818820836712651418414191818772264411945
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.14265811705299516141252933153681246753090782742687439601794558035690500834447
Short name T642
Test name
Test status
Simulation time 17319183 ps
CPU time 0.92 seconds
Started Nov 01 02:26:52 PM PDT 23
Finished Nov 01 02:26:57 PM PDT 23
Peak memory 214936 kb
Host smart-ed1006bf-1e56-470b-9bb4-bd9e03cc3407
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14265811705299516141252933153681246753090782742687439601794558035690500834447 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable_auto_req_mode.1426581170529951614125293315368124675309078274268743960179
4558035690500834447
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.928874515134203764323430649868793024217695793401866733374706819517829920435
Short name T811
Test name
Test status
Simulation time 24963823 ps
CPU time 1.11 seconds
Started Nov 01 02:26:40 PM PDT 23
Finished Nov 01 02:26:47 PM PDT 23
Peak memory 230472 kb
Host smart-d1b1f06a-03cf-48b6-b9eb-15fc6474926c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928874515134203764323430649868793024217695793401866733374706819517829920435 -assert nopostproc +UVM_TESTNAME=edn_err_tes
t +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.e
dn_err.928874515134203764323430649868793024217695793401866733374706819517829920435
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.19765869172793803428616758332229626005294973764363931357718244903296460515041
Short name T442
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:26:11 PM PDT 23
Finished Nov 01 02:26:15 PM PDT 23
Peak memory 205788 kb
Host smart-7095b1df-3151-48b1-9c3b-feef0ecdaa87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19765869172793803428616758332229626005294973764363931357718244903296460515041 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.edn_genbits.19765869172793803428616758332229626005294973764363931357718244903296460515041
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.34043169576264908411761744685785587460643570597473624314080569806943763416502
Short name T471
Test name
Test status
Simulation time 18439183 ps
CPU time 1.14 seconds
Started Nov 01 02:26:08 PM PDT 23
Finished Nov 01 02:26:13 PM PDT 23
Peak memory 222252 kb
Host smart-3f3cea05-4327-4bc7-93ff-89134ba65810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34043169576264908411761744685785587460643570597473624314080569806943763416502 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.edn_intr.34043169576264908411761744685785587460643570597473624314080569806943763416502
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.7942255255178016983089095796716660386963290350517603972639839475728905757273
Short name T683
Test name
Test status
Simulation time 13059183 ps
CPU time 0.86 seconds
Started Nov 01 02:26:08 PM PDT 23
Finished Nov 01 02:26:13 PM PDT 23
Peak memory 205416 kb
Host smart-83a9afba-540a-43c1-80fb-e053382ac1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7942255255178016983089095796716660386963290350517603972639839475728905757273 -assert nopostproc +UVM_TESTNAME=edn_smoke_
test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.edn_smoke.7942255255178016983089095796716660386963290350517603972639839475728905757273
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.52783967613568882168091623160140224404213981469292927368340114224942372297129
Short name T922
Test name
Test status
Simulation time 154489183 ps
CPU time 3.85 seconds
Started Nov 01 02:26:07 PM PDT 23
Finished Nov 01 02:26:16 PM PDT 23
Peak memory 206440 kb
Host smart-416be0b2-dcf7-44f0-b71d-4ce676d0555a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52783967613568882168091623160140224404213981469292927368340114224942372297129 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.52783967613568882168091623160140224404213981469292927368340114224942372297129
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.33199991014420900393058476566206546378397238454944246845966604362153261867368
Short name T744
Test name
Test status
Simulation time 41708099183 ps
CPU time 1094.48 seconds
Started Nov 01 02:26:11 PM PDT 23
Finished Nov 01 02:44:28 PM PDT 23
Peak memory 215804 kb
Host smart-abbd643d-34ac-4457-a9b8-2a066ea6c1e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331999910144209003930584765
66206546378397238454944246845966604362153261867368 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.33199991014
420900393058476566206546378397238454944246845966604362153261867368
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.110296964989069193950433401758487068061606484590469712786105930001945658416433
Short name T798
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:27:24 PM PDT 23
Finished Nov 01 02:27:39 PM PDT 23
Peak memory 205876 kb
Host smart-e6140b02-2ce3-4d70-b714-e54350afc3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110296964989069193950433401758487068061606484590469712786105930001945658416433 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 200.edn_genbits.110296964989069193950433401758487068061606484590469712786105930001945658416433
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.8212329613208890608134790971851451406746895925107782540168009690717906430938
Short name T968
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 01 02:27:13 PM PDT 23
Finished Nov 01 02:27:30 PM PDT 23
Peak memory 205880 kb
Host smart-5340625b-def0-44dc-8a06-df0859b8af95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8212329613208890608134790971851451406746895925107782540168009690717906430938 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 201.edn_genbits.8212329613208890608134790971851451406746895925107782540168009690717906430938
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.39420120726081196738328012853985267673447509925381222220561509801054098527182
Short name T871
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:27:55 PM PDT 23
Finished Nov 01 02:27:59 PM PDT 23
Peak memory 205864 kb
Host smart-dd3364fa-c01a-482f-a797-123aad82c3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39420120726081196738328012853985267673447509925381222220561509801054098527182 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 202.edn_genbits.39420120726081196738328012853985267673447509925381222220561509801054098527182
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.63489267140083040866091982360839249287323200598688713993782424390632623235250
Short name T48
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 01 02:27:55 PM PDT 23
Finished Nov 01 02:28:00 PM PDT 23
Peak memory 205796 kb
Host smart-3014e9ee-82ff-4902-b455-922188c60e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63489267140083040866091982360839249287323200598688713993782424390632623235250 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 203.edn_genbits.63489267140083040866091982360839249287323200598688713993782424390632623235250
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.89515275360597434687570958662040128587932210681021693785404373536995910223829
Short name T455
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:27:52 PM PDT 23
Finished Nov 01 02:27:56 PM PDT 23
Peak memory 205912 kb
Host smart-b41aedd8-5b7f-4af7-b613-32ee9c16c82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89515275360597434687570958662040128587932210681021693785404373536995910223829 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 204.edn_genbits.89515275360597434687570958662040128587932210681021693785404373536995910223829
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.98076509990446550699073557798088266758441268908998403524779050697953894976846
Short name T809
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 01 02:27:50 PM PDT 23
Finished Nov 01 02:27:55 PM PDT 23
Peak memory 205880 kb
Host smart-34d25e4e-30fb-41d8-b3d6-3fa2ba158c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98076509990446550699073557798088266758441268908998403524779050697953894976846 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 205.edn_genbits.98076509990446550699073557798088266758441268908998403524779050697953894976846
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.100557359061491127109708655348160413850115570180880254404698479428974679526670
Short name T490
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 01 02:27:53 PM PDT 23
Finished Nov 01 02:27:58 PM PDT 23
Peak memory 205924 kb
Host smart-dc9d10f7-8d4c-42a2-80c4-0e3245f1aa57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100557359061491127109708655348160413850115570180880254404698479428974679526670 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 207.edn_genbits.100557359061491127109708655348160413850115570180880254404698479428974679526670
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.38113239036353808742024769864147537919450474769167456681002820826383585103727
Short name T386
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 01 02:27:55 PM PDT 23
Finished Nov 01 02:28:00 PM PDT 23
Peak memory 205824 kb
Host smart-82abc472-ea18-41ba-adad-895cc93bf8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38113239036353808742024769864147537919450474769167456681002820826383585103727 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 208.edn_genbits.38113239036353808742024769864147537919450474769167456681002820826383585103727
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.57968664740234904951465390923409493866919155364319649764476647475983448382905
Short name T468
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:27:50 PM PDT 23
Finished Nov 01 02:27:55 PM PDT 23
Peak memory 205804 kb
Host smart-0d6a20fa-00a1-4571-a054-3fdc0c3ab942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57968664740234904951465390923409493866919155364319649764476647475983448382905 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 209.edn_genbits.57968664740234904951465390923409493866919155364319649764476647475983448382905
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.27702660933258017664167009403452520443405754280615268013522244370527063282386
Short name T906
Test name
Test status
Simulation time 18259183 ps
CPU time 1 seconds
Started Nov 01 02:26:49 PM PDT 23
Finished Nov 01 02:26:52 PM PDT 23
Peak memory 205640 kb
Host smart-29d6954b-d9e7-452e-bb68-b3b06df5f774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27702660933258017664167009403452520443405754280615268013522244370527063282386 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 21.edn_alert.27702660933258017664167009403452520443405754280615268013522244370527063282386
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.57165059605681410588152921570602991923030556128571440363197619017507106906797
Short name T753
Test name
Test status
Simulation time 28184990 ps
CPU time 0.85 seconds
Started Nov 01 02:26:54 PM PDT 23
Finished Nov 01 02:27:01 PM PDT 23
Peak memory 205408 kb
Host smart-2315ecd8-e4df-4448-b758-09aa42073c30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57165059605681410588152921570602991923030556128571440363197619017507106906797 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.edn_alert_test.57165059605681410588152921570602991923030556128571440363197619017507106906797
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.7731647402840557045690417694131622742641595533435949664954657127931271798452
Short name T750
Test name
Test status
Simulation time 12219183 ps
CPU time 0.87 seconds
Started Nov 01 02:26:41 PM PDT 23
Finished Nov 01 02:26:47 PM PDT 23
Peak memory 214828 kb
Host smart-11b22ffc-624b-42ca-9d2f-87839cb711e0
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7731647402840557045690417694131622742641595533435949664954657127931271798452 -assert nopostproc
+UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.edn_disable.7731647402840557045690417694131622742641595533435949664954657127931271798452
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.65645304302290401317230851604578015613043641219544917273409992855355107341055
Short name T294
Test name
Test status
Simulation time 17319183 ps
CPU time 0.91 seconds
Started Nov 01 02:26:51 PM PDT 23
Finished Nov 01 02:26:54 PM PDT 23
Peak memory 214956 kb
Host smart-4a524eeb-f951-4879-827e-f7a473b80599
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65645304302290401317230851604578015613043641219544917273409992855355107341055 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable_auto_req_mode.6564530430229040131723085160457801561304364121954491727340
9992855355107341055
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.95353607247031633698132067434471778266733144573786908274535608900117023585596
Short name T776
Test name
Test status
Simulation time 24963823 ps
CPU time 1.14 seconds
Started Nov 01 02:26:47 PM PDT 23
Finished Nov 01 02:26:51 PM PDT 23
Peak memory 230496 kb
Host smart-5c43be0b-6411-476e-9295-6aeda853e0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95353607247031633698132067434471778266733144573786908274535608900117023585596 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.edn_err.95353607247031633698132067434471778266733144573786908274535608900117023585596
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.29649557685116913978623374103811015121174006934883729543083051080263590786556
Short name T326
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:26:50 PM PDT 23
Finished Nov 01 02:26:53 PM PDT 23
Peak memory 205856 kb
Host smart-3a768556-155b-4705-a032-a15483d39fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29649557685116913978623374103811015121174006934883729543083051080263590786556 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.edn_genbits.29649557685116913978623374103811015121174006934883729543083051080263590786556
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.28302496017272731234880426431263340091030227629149864633832181035039940845234
Short name T430
Test name
Test status
Simulation time 18439183 ps
CPU time 1.19 seconds
Started Nov 01 02:26:44 PM PDT 23
Finished Nov 01 02:26:50 PM PDT 23
Peak memory 222296 kb
Host smart-e6eb5891-bd2e-4847-9459-1b9aac659120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28302496017272731234880426431263340091030227629149864633832181035039940845234 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.edn_intr.28302496017272731234880426431263340091030227629149864633832181035039940845234
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.46222058654669503686087613242555677259203397701006500641174667611299234538296
Short name T429
Test name
Test status
Simulation time 13059183 ps
CPU time 0.86 seconds
Started Nov 01 02:26:39 PM PDT 23
Finished Nov 01 02:26:43 PM PDT 23
Peak memory 205308 kb
Host smart-ae0f507d-7bb7-4a77-b0d5-c8ba0a6ab536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46222058654669503686087613242555677259203397701006500641174667611299234538296 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 21.edn_smoke.46222058654669503686087613242555677259203397701006500641174667611299234538296
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.13527849990192183993826307094260111167475200129093509418915555185856556207332
Short name T964
Test name
Test status
Simulation time 154489183 ps
CPU time 4.09 seconds
Started Nov 01 02:26:50 PM PDT 23
Finished Nov 01 02:26:57 PM PDT 23
Peak memory 206408 kb
Host smart-a5a67dc8-e065-46af-b647-bff3ce7de140
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13527849990192183993826307094260111167475200129093509418915555185856556207332 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.13527849990192183993826307094260111167475200129093509418915555185856556207332
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.77925299649129681643242076254719801336191723010177652621032656306154838996594
Short name T384
Test name
Test status
Simulation time 41708099183 ps
CPU time 1085.96 seconds
Started Nov 01 02:26:56 PM PDT 23
Finished Nov 01 02:45:17 PM PDT 23
Peak memory 215872 kb
Host smart-131c8fc5-a359-44c4-83ba-a88e8dee9be9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779252996491296816432420762
54719801336191723010177652621032656306154838996594 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.77925299649
129681643242076254719801336191723010177652621032656306154838996594
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.12774158249324229457367398295410319287893316985191752700313630096059305610944
Short name T492
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:27:49 PM PDT 23
Finished Nov 01 02:27:55 PM PDT 23
Peak memory 205844 kb
Host smart-c9293ff9-1ca2-4348-8b5f-7eed3ba90799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12774158249324229457367398295410319287893316985191752700313630096059305610944 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 210.edn_genbits.12774158249324229457367398295410319287893316985191752700313630096059305610944
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.110906604635799696902131505934717204579752178438480769137383233643453468944649
Short name T909
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 01 02:27:53 PM PDT 23
Finished Nov 01 02:27:58 PM PDT 23
Peak memory 205924 kb
Host smart-2b52ae6b-0659-4eaa-b343-6144d987f0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110906604635799696902131505934717204579752178438480769137383233643453468944649 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 211.edn_genbits.110906604635799696902131505934717204579752178438480769137383233643453468944649
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.56566196575509645727578652356896296213045568104120787233907021858139323898544
Short name T305
Test name
Test status
Simulation time 17999183 ps
CPU time 1.04 seconds
Started Nov 01 02:27:52 PM PDT 23
Finished Nov 01 02:27:56 PM PDT 23
Peak memory 205704 kb
Host smart-167cf5b0-0114-47ca-901c-31f44e82968b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56566196575509645727578652356896296213045568104120787233907021858139323898544 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 212.edn_genbits.56566196575509645727578652356896296213045568104120787233907021858139323898544
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.9375004524198387916609790134455044988187994449247309833453291455473220000986
Short name T513
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:27:59 PM PDT 23
Finished Nov 01 02:28:05 PM PDT 23
Peak memory 205892 kb
Host smart-3f1e8c87-2d69-4278-bfe7-305322d5d5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9375004524198387916609790134455044988187994449247309833453291455473220000986 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 213.edn_genbits.9375004524198387916609790134455044988187994449247309833453291455473220000986
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.61076746683866914551847889203218934868122604550046205179248539164039167948175
Short name T773
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 01 02:27:49 PM PDT 23
Finished Nov 01 02:27:54 PM PDT 23
Peak memory 205916 kb
Host smart-62ff19a4-b181-4c4d-a563-608ea2c42d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61076746683866914551847889203218934868122604550046205179248539164039167948175 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 214.edn_genbits.61076746683866914551847889203218934868122604550046205179248539164039167948175
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.6738106534891813145536712392302896934365362905650145758279582717805340303210
Short name T533
Test name
Test status
Simulation time 17999183 ps
CPU time 1.15 seconds
Started Nov 01 02:27:52 PM PDT 23
Finished Nov 01 02:27:57 PM PDT 23
Peak memory 205900 kb
Host smart-d4024cbd-c11a-4414-8b03-ebae7f376bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6738106534891813145536712392302896934365362905650145758279582717805340303210 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 215.edn_genbits.6738106534891813145536712392302896934365362905650145758279582717805340303210
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.78379404489215298280732966473194700408664943027437528583778385046184798285440
Short name T476
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:28:01 PM PDT 23
Finished Nov 01 02:28:06 PM PDT 23
Peak memory 205900 kb
Host smart-52e16bbb-80ce-4ae5-8be0-6a781c02e7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78379404489215298280732966473194700408664943027437528583778385046184798285440 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 216.edn_genbits.78379404489215298280732966473194700408664943027437528583778385046184798285440
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.42241178482903102724510011162984027566151734618608847499263537930995823427200
Short name T898
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:27:56 PM PDT 23
Finished Nov 01 02:28:02 PM PDT 23
Peak memory 205768 kb
Host smart-6c37361b-6e6a-48a3-80cd-39bde37f3083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42241178482903102724510011162984027566151734618608847499263537930995823427200 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 217.edn_genbits.42241178482903102724510011162984027566151734618608847499263537930995823427200
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.49813908086810275263535273775446408571920022894227038178421862820125183947189
Short name T771
Test name
Test status
Simulation time 17999183 ps
CPU time 1.17 seconds
Started Nov 01 02:27:54 PM PDT 23
Finished Nov 01 02:27:59 PM PDT 23
Peak memory 205888 kb
Host smart-55e25d23-ebb7-4987-8897-10b861d365e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49813908086810275263535273775446408571920022894227038178421862820125183947189 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 218.edn_genbits.49813908086810275263535273775446408571920022894227038178421862820125183947189
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.5700361196505475898677221166966884315854623911478494770653570052906573634854
Short name T528
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 01 02:27:56 PM PDT 23
Finished Nov 01 02:28:02 PM PDT 23
Peak memory 205872 kb
Host smart-270de0e3-6600-48a1-bd7e-b98e1759b409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5700361196505475898677221166966884315854623911478494770653570052906573634854 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 219.edn_genbits.5700361196505475898677221166966884315854623911478494770653570052906573634854
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.110990781572525474383047529210697042987393215262942748658973802857046999852994
Short name T745
Test name
Test status
Simulation time 18259183 ps
CPU time 0.98 seconds
Started Nov 01 02:26:57 PM PDT 23
Finished Nov 01 02:27:09 PM PDT 23
Peak memory 205620 kb
Host smart-cc1cf595-984f-4147-8f0f-15b028a9f3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110990781572525474383047529210697042987393215262942748658973802857046999852994 -assert nopostproc +UVM_TESTNAME=edn_aler
t_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 22.edn_alert.110990781572525474383047529210697042987393215262942748658973802857046999852994
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.23252028144469263556500503672957339485499051081348028338964806170310451184317
Short name T532
Test name
Test status
Simulation time 28184990 ps
CPU time 0.88 seconds
Started Nov 01 02:27:06 PM PDT 23
Finished Nov 01 02:27:21 PM PDT 23
Peak memory 205576 kb
Host smart-b9f1d2ce-70c6-4695-ba65-8c64243bb356
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23252028144469263556500503672957339485499051081348028338964806170310451184317 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.edn_alert_test.23252028144469263556500503672957339485499051081348028338964806170310451184317
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.111739172875371240001943014080987761730199381710989332272407165811239101514054
Short name T833
Test name
Test status
Simulation time 12219183 ps
CPU time 0.89 seconds
Started Nov 01 02:26:56 PM PDT 23
Finished Nov 01 02:27:05 PM PDT 23
Peak memory 214872 kb
Host smart-6c4316d4-5bc6-4aff-a58b-10d64be5bdcb
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111739172875371240001943014080987761730199381710989332272407165811239101514054 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 22.edn_disable.111739172875371240001943014080987761730199381710989332272407165811239101514054
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.69904832095786305071346227018484470971740120461581830887707516341264398922421
Short name T810
Test name
Test status
Simulation time 17319183 ps
CPU time 0.93 seconds
Started Nov 01 02:27:04 PM PDT 23
Finished Nov 01 02:27:20 PM PDT 23
Peak memory 214980 kb
Host smart-571a6e21-d33b-4ae0-a364-ae28b34c4b72
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69904832095786305071346227018484470971740120461581830887707516341264398922421 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable_auto_req_mode.6990483209578630507134622701848447097174012046158183088770
7516341264398922421
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.6076237577302011829121412876554002946704031674654337149699039164307466086427
Short name T975
Test name
Test status
Simulation time 24963823 ps
CPU time 1.16 seconds
Started Nov 01 02:26:58 PM PDT 23
Finished Nov 01 02:27:10 PM PDT 23
Peak memory 230440 kb
Host smart-f716f40d-5541-4095-a005-1e27b8c59c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6076237577302011829121412876554002946704031674654337149699039164307466086427 -assert nopostproc +UVM_TESTNAME=edn_err_te
st +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
edn_err.6076237577302011829121412876554002946704031674654337149699039164307466086427
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.21139034188152773354285983799011675859547909463978919804568111522659885188299
Short name T540
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:26:57 PM PDT 23
Finished Nov 01 02:27:09 PM PDT 23
Peak memory 205840 kb
Host smart-513c13d6-1947-4c01-b057-9f3abc88faec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21139034188152773354285983799011675859547909463978919804568111522659885188299 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.edn_genbits.21139034188152773354285983799011675859547909463978919804568111522659885188299
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.33059325400886015741171818580341623506703397410388549608453794342017232753533
Short name T707
Test name
Test status
Simulation time 18439183 ps
CPU time 1.11 seconds
Started Nov 01 02:26:53 PM PDT 23
Finished Nov 01 02:26:59 PM PDT 23
Peak memory 222316 kb
Host smart-eda21518-900c-4dbd-8c6d-d6f152c5ad72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33059325400886015741171818580341623506703397410388549608453794342017232753533 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.edn_intr.33059325400886015741171818580341623506703397410388549608453794342017232753533
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.45643922706920311329326780246297824524504471937797156021676482031145596266270
Short name T316
Test name
Test status
Simulation time 13059183 ps
CPU time 0.9 seconds
Started Nov 01 02:26:52 PM PDT 23
Finished Nov 01 02:26:58 PM PDT 23
Peak memory 205292 kb
Host smart-1ea46142-c825-494b-8ab3-799b42dd4b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45643922706920311329326780246297824524504471937797156021676482031145596266270 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 22.edn_smoke.45643922706920311329326780246297824524504471937797156021676482031145596266270
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.60819565181474021121050300833025677137958666391854860090710191030676279531604
Short name T507
Test name
Test status
Simulation time 154489183 ps
CPU time 4.25 seconds
Started Nov 01 02:26:50 PM PDT 23
Finished Nov 01 02:26:57 PM PDT 23
Peak memory 206400 kb
Host smart-c5f476f9-f7f3-4f40-871f-c8d6ca7edb20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60819565181474021121050300833025677137958666391854860090710191030676279531604 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.60819565181474021121050300833025677137958666391854860090710191030676279531604
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.4256789513544379469231949292567726804190550686371478562697953912780196369870
Short name T602
Test name
Test status
Simulation time 41708099183 ps
CPU time 1066.1 seconds
Started Nov 01 02:26:54 PM PDT 23
Finished Nov 01 02:44:46 PM PDT 23
Peak memory 215804 kb
Host smart-90a971a8-4008-4697-af37-3beef16824e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425678951354437946923194929
2567726804190550686371478562697953912780196369870 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.425678951354
4379469231949292567726804190550686371478562697953912780196369870
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.62232268459011900638645866213596665716852672474553345568025717216957377322609
Short name T655
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:27:54 PM PDT 23
Finished Nov 01 02:27:58 PM PDT 23
Peak memory 205904 kb
Host smart-244c1b47-6ba2-4554-bd11-4542c517684a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62232268459011900638645866213596665716852672474553345568025717216957377322609 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 220.edn_genbits.62232268459011900638645866213596665716852672474553345568025717216957377322609
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.28071873711828500254957388238303105727795768334110192211506113245975164075652
Short name T260
Test name
Test status
Simulation time 17999183 ps
CPU time 1.15 seconds
Started Nov 01 02:27:56 PM PDT 23
Finished Nov 01 02:28:01 PM PDT 23
Peak memory 205872 kb
Host smart-e4a69328-408b-4c49-b44f-a3053d17fb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28071873711828500254957388238303105727795768334110192211506113245975164075652 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 221.edn_genbits.28071873711828500254957388238303105727795768334110192211506113245975164075652
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.81571291347593051035680845761562450899568579408532177085342600680719369484442
Short name T616
Test name
Test status
Simulation time 17999183 ps
CPU time 1.17 seconds
Started Nov 01 02:27:54 PM PDT 23
Finished Nov 01 02:27:59 PM PDT 23
Peak memory 205904 kb
Host smart-dacc6b86-f3f2-4241-924e-bad4bafc3c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81571291347593051035680845761562450899568579408532177085342600680719369484442 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 222.edn_genbits.81571291347593051035680845761562450899568579408532177085342600680719369484442
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.54879155316364254607924337720588490237154449405011523766664362870805693150050
Short name T247
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 01 02:27:57 PM PDT 23
Finished Nov 01 02:28:03 PM PDT 23
Peak memory 205880 kb
Host smart-1a11df65-4e2e-4fce-8cfd-17e438df1ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54879155316364254607924337720588490237154449405011523766664362870805693150050 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 223.edn_genbits.54879155316364254607924337720588490237154449405011523766664362870805693150050
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.112241292569535869928643919356245928503772738687193168571626571082169149125493
Short name T870
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:27:56 PM PDT 23
Finished Nov 01 02:28:01 PM PDT 23
Peak memory 205884 kb
Host smart-e962e079-ebc4-45ed-85c0-61b4af62c236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112241292569535869928643919356245928503772738687193168571626571082169149125493 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 224.edn_genbits.112241292569535869928643919356245928503772738687193168571626571082169149125493
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.115171262457258291469483227896874371162239017150608831715372915423782313009842
Short name T932
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 01 02:27:58 PM PDT 23
Finished Nov 01 02:28:04 PM PDT 23
Peak memory 205864 kb
Host smart-7d6999b2-baee-483a-92fc-2834afcf8883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115171262457258291469483227896874371162239017150608831715372915423782313009842 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 225.edn_genbits.115171262457258291469483227896874371162239017150608831715372915423782313009842
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.42575914791324930517919085262392884585435663738415694800059864044505979998691
Short name T466
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:27:55 PM PDT 23
Finished Nov 01 02:28:00 PM PDT 23
Peak memory 205892 kb
Host smart-7abcb0e6-4242-4c0f-9882-b97db43f89ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42575914791324930517919085262392884585435663738415694800059864044505979998691 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 226.edn_genbits.42575914791324930517919085262392884585435663738415694800059864044505979998691
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.94140038357169954602530857408362478863890121270317507325863036342282087491234
Short name T14
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:27:55 PM PDT 23
Finished Nov 01 02:28:00 PM PDT 23
Peak memory 205892 kb
Host smart-41ee638e-31a2-4ba0-a0b1-e9ac65f00ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94140038357169954602530857408362478863890121270317507325863036342282087491234 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 227.edn_genbits.94140038357169954602530857408362478863890121270317507325863036342282087491234
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.86552624582095196128480056962603241204881002508381419285488673603403919444239
Short name T618
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:27:53 PM PDT 23
Finished Nov 01 02:27:58 PM PDT 23
Peak memory 205904 kb
Host smart-0d4be8f4-7b1e-406b-bf1d-d14bf0100da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86552624582095196128480056962603241204881002508381419285488673603403919444239 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 228.edn_genbits.86552624582095196128480056962603241204881002508381419285488673603403919444239
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.39049447718559638475109803755674919841100584291668764532383346108794320048812
Short name T917
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 01 02:27:59 PM PDT 23
Finished Nov 01 02:28:05 PM PDT 23
Peak memory 205904 kb
Host smart-9c591334-529a-481c-a65c-7cd11e328804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39049447718559638475109803755674919841100584291668764532383346108794320048812 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 229.edn_genbits.39049447718559638475109803755674919841100584291668764532383346108794320048812
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.39799845556497059593914339258324805178819345029036358299934971165870060740507
Short name T550
Test name
Test status
Simulation time 18259183 ps
CPU time 1.03 seconds
Started Nov 01 02:26:20 PM PDT 23
Finished Nov 01 02:26:25 PM PDT 23
Peak memory 205584 kb
Host smart-8b199e36-b1c7-44cc-bf36-d7bdb9a8fc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39799845556497059593914339258324805178819345029036358299934971165870060740507 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 23.edn_alert.39799845556497059593914339258324805178819345029036358299934971165870060740507
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_disable.24487211741697480307357171889645531580416468611947864026392737567213148751843
Short name T382
Test name
Test status
Simulation time 12219183 ps
CPU time 0.92 seconds
Started Nov 01 02:26:03 PM PDT 23
Finished Nov 01 02:26:08 PM PDT 23
Peak memory 214936 kb
Host smart-918a0d62-bc4f-4a72-8af7-5786a0964f29
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24487211741697480307357171889645531580416468611947864026392737567213148751843 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.edn_disable.24487211741697480307357171889645531580416468611947864026392737567213148751843
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.112680953728462884037344599035048518438782910787451626314181592916884540828777
Short name T856
Test name
Test status
Simulation time 17319183 ps
CPU time 0.95 seconds
Started Nov 01 02:26:02 PM PDT 23
Finished Nov 01 02:26:08 PM PDT 23
Peak memory 214952 kb
Host smart-98618b4d-7857-4a47-a525-a8107b62f044
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112680953728462884037344599035048518438782910787451626314181592916884540828777 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable_auto_req_mode.112680953728462884037344599035048518438782910787451626314
181592916884540828777
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.52454627997389505744852065776197588809511285990238627322391916149727119521715
Short name T496
Test name
Test status
Simulation time 24963823 ps
CPU time 1.13 seconds
Started Nov 01 02:26:37 PM PDT 23
Finished Nov 01 02:26:40 PM PDT 23
Peak memory 230408 kb
Host smart-81ce9c50-5f37-4715-9e85-d439a8936b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52454627997389505744852065776197588809511285990238627322391916149727119521715 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.edn_err.52454627997389505744852065776197588809511285990238627322391916149727119521715
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.79843929743043318203647007205173292480953881601472659488648384662466416757336
Short name T327
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:27:08 PM PDT 23
Finished Nov 01 02:27:24 PM PDT 23
Peak memory 205840 kb
Host smart-b698f89f-8ff8-454b-b219-ed33040400fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79843929743043318203647007205173292480953881601472659488648384662466416757336 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.edn_genbits.79843929743043318203647007205173292480953881601472659488648384662466416757336
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.108764934020185469831288439428271336231382186832588600185106581142050361255282
Short name T49
Test name
Test status
Simulation time 18439183 ps
CPU time 1.11 seconds
Started Nov 01 02:26:59 PM PDT 23
Finished Nov 01 02:27:12 PM PDT 23
Peak memory 222304 kb
Host smart-d0803546-241b-412d-9abf-dc3f60fbb1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108764934020185469831288439428271336231382186832588600185106581142050361255282 -assert nopostproc +UVM_TESTNAME=edn_intr
_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.edn_intr.108764934020185469831288439428271336231382186832588600185106581142050361255282
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.54970083957378318579147469681531065268579642790200129667522968281121407395290
Short name T428
Test name
Test status
Simulation time 13059183 ps
CPU time 0.88 seconds
Started Nov 01 02:27:01 PM PDT 23
Finished Nov 01 02:27:17 PM PDT 23
Peak memory 205328 kb
Host smart-1e326fc5-3d48-4726-842c-6ba2f4cec3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54970083957378318579147469681531065268579642790200129667522968281121407395290 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 23.edn_smoke.54970083957378318579147469681531065268579642790200129667522968281121407395290
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.199866620926516585197301436667485489053687985769626440580660587765008445250
Short name T712
Test name
Test status
Simulation time 154489183 ps
CPU time 4.05 seconds
Started Nov 01 02:27:15 PM PDT 23
Finished Nov 01 02:27:34 PM PDT 23
Peak memory 206420 kb
Host smart-d1f3eee5-1063-4c1d-b255-f6fcee8f6a51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199866620926516585197301436667485489053687985769626440580660587765008445250 -assert nopostp
roc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.199866620926516585197301436667485489053687985769626440580660587765008445250
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.93714800585535504672512591860127501361219722053575616616654115254138331830536
Short name T693
Test name
Test status
Simulation time 41708099183 ps
CPU time 1117.34 seconds
Started Nov 01 02:27:08 PM PDT 23
Finished Nov 01 02:46:01 PM PDT 23
Peak memory 215860 kb
Host smart-b685e90b-03d0-4237-9464-f3c2feebf8da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937148005855355046725125918
60127501361219722053575616616654115254138331830536 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.93714800585
535504672512591860127501361219722053575616616654115254138331830536
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.58085261831662932356153250551982468160072202526409009434776337757613482756170
Short name T259
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 01 02:28:00 PM PDT 23
Finished Nov 01 02:28:06 PM PDT 23
Peak memory 205900 kb
Host smart-a3440ccb-2237-43d7-9a15-3f5fcf0869a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58085261831662932356153250551982468160072202526409009434776337757613482756170 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 230.edn_genbits.58085261831662932356153250551982468160072202526409009434776337757613482756170
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.82936022158806138471264368333516063492202769932206217253354322524261721037098
Short name T822
Test name
Test status
Simulation time 17999183 ps
CPU time 1.04 seconds
Started Nov 01 02:27:56 PM PDT 23
Finished Nov 01 02:28:01 PM PDT 23
Peak memory 205888 kb
Host smart-add12a66-3c9f-44f6-9ea0-028c4691658e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82936022158806138471264368333516063492202769932206217253354322524261721037098 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 231.edn_genbits.82936022158806138471264368333516063492202769932206217253354322524261721037098
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.61518299323949771699578773815879138623770730205024314574598008125263550273519
Short name T506
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 01 02:27:59 PM PDT 23
Finished Nov 01 02:28:05 PM PDT 23
Peak memory 205872 kb
Host smart-2890a967-1a21-4a59-b45c-c18dbb4ea3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61518299323949771699578773815879138623770730205024314574598008125263550273519 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 232.edn_genbits.61518299323949771699578773815879138623770730205024314574598008125263550273519
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.110813427686068479865273932082424066815938134839799185467022788693375775895938
Short name T632
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:27:56 PM PDT 23
Finished Nov 01 02:28:01 PM PDT 23
Peak memory 205908 kb
Host smart-64f367b4-d340-4b6a-8615-9f52cb68bb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110813427686068479865273932082424066815938134839799185467022788693375775895938 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 233.edn_genbits.110813427686068479865273932082424066815938134839799185467022788693375775895938
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.108787535233678565544891479531597729512370280626968847951925196598032867951834
Short name T718
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 01 02:27:59 PM PDT 23
Finished Nov 01 02:28:05 PM PDT 23
Peak memory 205908 kb
Host smart-d34ab41c-aa50-4102-81af-eb4d65ff7e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108787535233678565544891479531597729512370280626968847951925196598032867951834 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 234.edn_genbits.108787535233678565544891479531597729512370280626968847951925196598032867951834
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.39225872485503403524451739583370135442478723163194482422709540295921817587632
Short name T802
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:27:56 PM PDT 23
Finished Nov 01 02:28:02 PM PDT 23
Peak memory 205900 kb
Host smart-3cfb6567-35ff-4ef1-8a0b-802b09397524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39225872485503403524451739583370135442478723163194482422709540295921817587632 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 235.edn_genbits.39225872485503403524451739583370135442478723163194482422709540295921817587632
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.79427094596802737043478439511187046403277414481234401298960611649620186640642
Short name T883
Test name
Test status
Simulation time 17999183 ps
CPU time 1.18 seconds
Started Nov 01 02:27:59 PM PDT 23
Finished Nov 01 02:28:05 PM PDT 23
Peak memory 205800 kb
Host smart-91bfb0bc-1bc6-40b8-8a0d-b61ac4f5590e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79427094596802737043478439511187046403277414481234401298960611649620186640642 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 236.edn_genbits.79427094596802737043478439511187046403277414481234401298960611649620186640642
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.98658700266053425071705223547412536825855674115331232818020194050551517178909
Short name T491
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:28:03 PM PDT 23
Finished Nov 01 02:28:07 PM PDT 23
Peak memory 205780 kb
Host smart-2cf21373-3c9d-4d83-8e55-16f10d06a947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98658700266053425071705223547412536825855674115331232818020194050551517178909 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 237.edn_genbits.98658700266053425071705223547412536825855674115331232818020194050551517178909
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.56539304461585694210861584461389511930478734239048606352203498008169889168529
Short name T812
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 01 02:27:55 PM PDT 23
Finished Nov 01 02:27:59 PM PDT 23
Peak memory 205788 kb
Host smart-4b708216-98b7-4fda-b443-87fa9b1dac57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56539304461585694210861584461389511930478734239048606352203498008169889168529 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 238.edn_genbits.56539304461585694210861584461389511930478734239048606352203498008169889168529
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.91560535720858468581425393259237173176652295429461229829089771154727009337995
Short name T286
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 01 02:28:00 PM PDT 23
Finished Nov 01 02:28:06 PM PDT 23
Peak memory 205860 kb
Host smart-502e572e-a938-489f-887b-4279b07eb3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91560535720858468581425393259237173176652295429461229829089771154727009337995 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 239.edn_genbits.91560535720858468581425393259237173176652295429461229829089771154727009337995
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.61859258846912477141209436291993249752461309552008442744953452056022536870504
Short name T827
Test name
Test status
Simulation time 18259183 ps
CPU time 0.97 seconds
Started Nov 01 02:26:41 PM PDT 23
Finished Nov 01 02:26:46 PM PDT 23
Peak memory 205468 kb
Host smart-5ffd4488-470b-4ca3-ba89-68fbe43eb263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61859258846912477141209436291993249752461309552008442744953452056022536870504 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 24.edn_alert.61859258846912477141209436291993249752461309552008442744953452056022536870504
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.2509782655614316099395658905314055921156577963538976026249155632154002257122
Short name T611
Test name
Test status
Simulation time 28184990 ps
CPU time 0.87 seconds
Started Nov 01 02:26:40 PM PDT 23
Finished Nov 01 02:26:46 PM PDT 23
Peak memory 205516 kb
Host smart-0be9008a-b5af-48d2-a437-474c41dcdb92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509782655614316099395658905314055921156577963538976026249155632154002257122 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.edn_alert_test.2509782655614316099395658905314055921156577963538976026249155632154002257122
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.30922393470604743218336977525019277527803658315525435096428252208687068666522
Short name T839
Test name
Test status
Simulation time 12219183 ps
CPU time 0.88 seconds
Started Nov 01 02:26:41 PM PDT 23
Finished Nov 01 02:26:46 PM PDT 23
Peak memory 214768 kb
Host smart-5c29aae1-a941-438e-8db5-5b86c5c069b3
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30922393470604743218336977525019277527803658315525435096428252208687068666522 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.edn_disable.30922393470604743218336977525019277527803658315525435096428252208687068666522
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.97975843350327299377113028565020145402960027132379648583275027977981630477475
Short name T489
Test name
Test status
Simulation time 17319183 ps
CPU time 0.92 seconds
Started Nov 01 02:26:41 PM PDT 23
Finished Nov 01 02:26:46 PM PDT 23
Peak memory 214792 kb
Host smart-9a60dc46-817e-4631-8ccd-ceaeca4d7bbd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97975843350327299377113028565020145402960027132379648583275027977981630477475 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable_auto_req_mode.9797584335032729937711302856502014540296002713237964858327
5027977981630477475
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.54348047040096453297235652598790790509494409342368811070394898100530597675789
Short name T704
Test name
Test status
Simulation time 24963823 ps
CPU time 1.14 seconds
Started Nov 01 02:26:40 PM PDT 23
Finished Nov 01 02:26:45 PM PDT 23
Peak memory 230456 kb
Host smart-1e347f95-cbd3-4af4-adf9-cdbc8814e4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54348047040096453297235652598790790509494409342368811070394898100530597675789 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.edn_err.54348047040096453297235652598790790509494409342368811070394898100530597675789
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.5942466030401310223894557483417668159844580722392728637518448423048143370586
Short name T561
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 01 02:26:08 PM PDT 23
Finished Nov 01 02:26:13 PM PDT 23
Peak memory 205900 kb
Host smart-977e06d7-38a8-47b3-bc09-4ce97677c6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5942466030401310223894557483417668159844580722392728637518448423048143370586 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.edn_genbits.5942466030401310223894557483417668159844580722392728637518448423048143370586
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.679090540724727977082979192839297559311435130111880098841400592702905813411
Short name T567
Test name
Test status
Simulation time 18439183 ps
CPU time 1.12 seconds
Started Nov 01 02:26:33 PM PDT 23
Finished Nov 01 02:26:35 PM PDT 23
Peak memory 222160 kb
Host smart-093559d8-34b7-475a-8c85-7c934dd0b975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679090540724727977082979192839297559311435130111880098841400592702905813411 -assert nopostproc +UVM_TESTNAME=edn_intr_te
st +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.edn_intr.679090540724727977082979192839297559311435130111880098841400592702905813411
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.24702184927793118805415066510773164423657214256411925867074338475501362611071
Short name T343
Test name
Test status
Simulation time 13059183 ps
CPU time 0.9 seconds
Started Nov 01 02:26:06 PM PDT 23
Finished Nov 01 02:26:12 PM PDT 23
Peak memory 205440 kb
Host smart-7fc39f14-cb41-4a3e-8b60-dbe1bafbdd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24702184927793118805415066510773164423657214256411925867074338475501362611071 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 24.edn_smoke.24702184927793118805415066510773164423657214256411925867074338475501362611071
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.56167501696724207799832727133096705964958065135920194394852569103901948046694
Short name T630
Test name
Test status
Simulation time 154489183 ps
CPU time 4.05 seconds
Started Nov 01 02:26:03 PM PDT 23
Finished Nov 01 02:26:11 PM PDT 23
Peak memory 206456 kb
Host smart-57e20b9c-8e81-4bd2-bb45-d3d8d51615b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56167501696724207799832727133096705964958065135920194394852569103901948046694 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.56167501696724207799832727133096705964958065135920194394852569103901948046694
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.110512890412030600905395920698733765689001584426997065025149346918113584605986
Short name T330
Test name
Test status
Simulation time 41708099183 ps
CPU time 1102.11 seconds
Started Nov 01 02:26:36 PM PDT 23
Finished Nov 01 02:45:00 PM PDT 23
Peak memory 215768 kb
Host smart-fd5ce04d-95e3-482a-83e7-58a2ae7b16f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110512890412030600905395920
698733765689001584426997065025149346918113584605986 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1105128904
12030600905395920698733765689001584426997065025149346918113584605986
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.48789304759455564172568218421608347695494880129755837343941363646447916764332
Short name T864
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:28:09 PM PDT 23
Finished Nov 01 02:28:11 PM PDT 23
Peak memory 205912 kb
Host smart-0b12b113-fc02-4296-aef1-c64ce79744bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48789304759455564172568218421608347695494880129755837343941363646447916764332 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 240.edn_genbits.48789304759455564172568218421608347695494880129755837343941363646447916764332
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.81564461899325174183727057367831561625705920675129842303620793236633185616829
Short name T239
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 01 02:28:11 PM PDT 23
Finished Nov 01 02:28:13 PM PDT 23
Peak memory 205892 kb
Host smart-554aec55-ee29-46e0-ba5a-667ae549238f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81564461899325174183727057367831561625705920675129842303620793236633185616829 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 241.edn_genbits.81564461899325174183727057367831561625705920675129842303620793236633185616829
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.105948887569011725695050157585981115601404852059882227699277017026171988205272
Short name T933
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 01 02:28:02 PM PDT 23
Finished Nov 01 02:28:07 PM PDT 23
Peak memory 205844 kb
Host smart-9d1ed694-ee8c-446b-852c-53e46ac7d0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105948887569011725695050157585981115601404852059882227699277017026171988205272 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 242.edn_genbits.105948887569011725695050157585981115601404852059882227699277017026171988205272
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.96408338670556269202610809501930391265053114574514378757216393969917964349451
Short name T369
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 01 02:28:22 PM PDT 23
Finished Nov 01 02:28:24 PM PDT 23
Peak memory 205768 kb
Host smart-454ac5a6-a535-422f-8050-0432680cf8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96408338670556269202610809501930391265053114574514378757216393969917964349451 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 243.edn_genbits.96408338670556269202610809501930391265053114574514378757216393969917964349451
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.100746030539203455716084958642211211826154197806017433883635995744005310403476
Short name T438
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:28:02 PM PDT 23
Finished Nov 01 02:28:07 PM PDT 23
Peak memory 205852 kb
Host smart-5e438c77-6822-4d9b-80fe-dfbc3df12aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100746030539203455716084958642211211826154197806017433883635995744005310403476 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 244.edn_genbits.100746030539203455716084958642211211826154197806017433883635995744005310403476
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.67468642321601482957660055292233790126998551112223062514637075014261425610995
Short name T872
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:28:02 PM PDT 23
Finished Nov 01 02:28:07 PM PDT 23
Peak memory 205900 kb
Host smart-76d97b07-bf59-4190-b0a2-cdd5ca4e10ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67468642321601482957660055292233790126998551112223062514637075014261425610995 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 245.edn_genbits.67468642321601482957660055292233790126998551112223062514637075014261425610995
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.85481847917750599580475244009675528414497391877468751248489832865548518989653
Short name T55
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Nov 01 02:28:38 PM PDT 23
Finished Nov 01 02:28:44 PM PDT 23
Peak memory 205908 kb
Host smart-4753d2f3-476b-4bc1-be39-7e32be1dba84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85481847917750599580475244009675528414497391877468751248489832865548518989653 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 246.edn_genbits.85481847917750599580475244009675528414497391877468751248489832865548518989653
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.101607243432394346711383822449146744716937901982202390736866813032368844058681
Short name T706
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 01 02:28:27 PM PDT 23
Finished Nov 01 02:28:31 PM PDT 23
Peak memory 205772 kb
Host smart-0e799cfa-9e51-4c60-b79b-618dec86ffc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101607243432394346711383822449146744716937901982202390736866813032368844058681 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 247.edn_genbits.101607243432394346711383822449146744716937901982202390736866813032368844058681
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.111205827812052851621018720535268138791645839311013950371205973670793975716781
Short name T825
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 01 02:28:14 PM PDT 23
Finished Nov 01 02:28:16 PM PDT 23
Peak memory 205916 kb
Host smart-77678289-300d-4d9a-9985-f54159c65881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111205827812052851621018720535268138791645839311013950371205973670793975716781 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 248.edn_genbits.111205827812052851621018720535268138791645839311013950371205973670793975716781
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.63877727612051003709106161896357141662535402514818345023361189120531915103705
Short name T555
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:28:11 PM PDT 23
Finished Nov 01 02:28:13 PM PDT 23
Peak memory 205892 kb
Host smart-d7600703-46d0-4c1d-8746-a3bf8af4acea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63877727612051003709106161896357141662535402514818345023361189120531915103705 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 249.edn_genbits.63877727612051003709106161896357141662535402514818345023361189120531915103705
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.98903737546333491452118372288602853010259224796563791059662157254473167564085
Short name T277
Test name
Test status
Simulation time 18259183 ps
CPU time 1.05 seconds
Started Nov 01 02:26:40 PM PDT 23
Finished Nov 01 02:26:47 PM PDT 23
Peak memory 205468 kb
Host smart-9b77589d-4cf1-4a06-84ba-13bf6890677a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98903737546333491452118372288602853010259224796563791059662157254473167564085 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 25.edn_alert.98903737546333491452118372288602853010259224796563791059662157254473167564085
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.40426758053307625531342832790702540937747001060186012698176284094146665599638
Short name T821
Test name
Test status
Simulation time 28184990 ps
CPU time 0.86 seconds
Started Nov 01 02:26:40 PM PDT 23
Finished Nov 01 02:26:45 PM PDT 23
Peak memory 205440 kb
Host smart-71088364-c6b1-4117-80d0-b0cfff426ee9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40426758053307625531342832790702540937747001060186012698176284094146665599638 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.edn_alert_test.40426758053307625531342832790702540937747001060186012698176284094146665599638
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.104652152905166690435577103891363147569397172362123584362093522433394684831545
Short name T824
Test name
Test status
Simulation time 12219183 ps
CPU time 0.89 seconds
Started Nov 01 02:26:34 PM PDT 23
Finished Nov 01 02:26:35 PM PDT 23
Peak memory 214836 kb
Host smart-d2d8acde-63e2-41e1-b2b1-bd3175563cab
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104652152905166690435577103891363147569397172362123584362093522433394684831545 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 25.edn_disable.104652152905166690435577103891363147569397172362123584362093522433394684831545
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.21405176574946725109192435365408360004237230525665216275275405521573569888719
Short name T813
Test name
Test status
Simulation time 17319183 ps
CPU time 0.95 seconds
Started Nov 01 02:26:32 PM PDT 23
Finished Nov 01 02:26:34 PM PDT 23
Peak memory 214956 kb
Host smart-31517b43-714d-42e1-8ff4-5b7d666d593f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21405176574946725109192435365408360004237230525665216275275405521573569888719 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable_auto_req_mode.2140517657494672510919243536540836000423723052566521627527
5405521573569888719
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.48683035876607012041207835885937673355492402162410448303524228431615553959578
Short name T727
Test name
Test status
Simulation time 24963823 ps
CPU time 1.17 seconds
Started Nov 01 02:26:38 PM PDT 23
Finished Nov 01 02:26:43 PM PDT 23
Peak memory 230524 kb
Host smart-3aba0f30-183e-43ad-b43c-f5dac1434187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48683035876607012041207835885937673355492402162410448303524228431615553959578 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.edn_err.48683035876607012041207835885937673355492402162410448303524228431615553959578
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.109279690585408639338498383060382288418075862189860727969710206445338261795186
Short name T583
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 01 02:26:40 PM PDT 23
Finished Nov 01 02:26:46 PM PDT 23
Peak memory 205144 kb
Host smart-7dd66ab7-1bf4-4c36-8d62-23e157c65d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109279690585408639338498383060382288418075862189860727969710206445338261795186 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 25.edn_genbits.109279690585408639338498383060382288418075862189860727969710206445338261795186
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.93416867002598197060686443865358878587554292060458816711507343720779866959357
Short name T421
Test name
Test status
Simulation time 18439183 ps
CPU time 1.13 seconds
Started Nov 01 02:26:33 PM PDT 23
Finished Nov 01 02:26:35 PM PDT 23
Peak memory 222364 kb
Host smart-07efa3a3-c9bf-41d1-96de-c45322f10083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93416867002598197060686443865358878587554292060458816711507343720779866959357 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.edn_intr.93416867002598197060686443865358878587554292060458816711507343720779866959357
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.75417632482756697006580210984333723894672440164505813175620798796980438684302
Short name T255
Test name
Test status
Simulation time 13059183 ps
CPU time 0.89 seconds
Started Nov 01 02:26:35 PM PDT 23
Finished Nov 01 02:26:38 PM PDT 23
Peak memory 205372 kb
Host smart-33193dd1-37bd-4505-b321-f8f589c5621f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75417632482756697006580210984333723894672440164505813175620798796980438684302 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 25.edn_smoke.75417632482756697006580210984333723894672440164505813175620798796980438684302
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.35799506953282589590849751882395418439749284397904818972455844467700587201680
Short name T606
Test name
Test status
Simulation time 154489183 ps
CPU time 4 seconds
Started Nov 01 02:26:31 PM PDT 23
Finished Nov 01 02:26:36 PM PDT 23
Peak memory 206444 kb
Host smart-6c4898aa-5130-4466-ba8d-57b38f695d68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35799506953282589590849751882395418439749284397904818972455844467700587201680 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.35799506953282589590849751882395418439749284397904818972455844467700587201680
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.12239259958872063614618990091608882797654856440899334483230083433263029577658
Short name T832
Test name
Test status
Simulation time 41708099183 ps
CPU time 1076.87 seconds
Started Nov 01 02:26:39 PM PDT 23
Finished Nov 01 02:44:40 PM PDT 23
Peak memory 215912 kb
Host smart-27a74756-fad0-4ccf-a69f-994f66eb5a08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122392599588720636146189900
91608882797654856440899334483230083433263029577658 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.12239259958
872063614618990091608882797654856440899334483230083433263029577658
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.5023636329423349929028273818112564078612858129654267205277892423810344300248
Short name T849
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 01 02:27:58 PM PDT 23
Finished Nov 01 02:28:04 PM PDT 23
Peak memory 205836 kb
Host smart-3b9b9869-e6df-4f67-82ed-f72e0ce22837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5023636329423349929028273818112564078612858129654267205277892423810344300248 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 250.edn_genbits.5023636329423349929028273818112564078612858129654267205277892423810344300248
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.35047840992724106988033366143859956857918046755356901105948243110923356495081
Short name T17
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 01 02:28:12 PM PDT 23
Finished Nov 01 02:28:14 PM PDT 23
Peak memory 205888 kb
Host smart-2deae1f1-6c40-4de3-b6f5-0f88fb75929c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35047840992724106988033366143859956857918046755356901105948243110923356495081 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 251.edn_genbits.35047840992724106988033366143859956857918046755356901105948243110923356495081
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.59366934091449417492660535108998553959400525056155392935154362243499455702067
Short name T594
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 01 02:28:37 PM PDT 23
Finished Nov 01 02:28:44 PM PDT 23
Peak memory 205912 kb
Host smart-5d6a36c8-ba44-407b-883a-660b50735679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59366934091449417492660535108998553959400525056155392935154362243499455702067 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 252.edn_genbits.59366934091449417492660535108998553959400525056155392935154362243499455702067
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.46506629330186687574556962382169070534919182886162850741375688076773820651122
Short name T544
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:28:55 PM PDT 23
Finished Nov 01 02:28:57 PM PDT 23
Peak memory 205796 kb
Host smart-99e2d554-0094-4571-b3d5-68bf26b4a437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46506629330186687574556962382169070534919182886162850741375688076773820651122 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 253.edn_genbits.46506629330186687574556962382169070534919182886162850741375688076773820651122
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.77885676703851080846717999628080405159984181155369963733592516654343296846520
Short name T454
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Nov 01 02:28:37 PM PDT 23
Finished Nov 01 02:28:44 PM PDT 23
Peak memory 205880 kb
Host smart-c98cdb8e-59e0-484c-ae9d-cc18b8dc04f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77885676703851080846717999628080405159984181155369963733592516654343296846520 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 254.edn_genbits.77885676703851080846717999628080405159984181155369963733592516654343296846520
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.30692398330437486086018617833498880543250516320369235583965516932140593023625
Short name T51
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:28:39 PM PDT 23
Finished Nov 01 02:28:45 PM PDT 23
Peak memory 205876 kb
Host smart-ae194e9c-3241-41c1-bcee-bef746ede9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30692398330437486086018617833498880543250516320369235583965516932140593023625 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 255.edn_genbits.30692398330437486086018617833498880543250516320369235583965516932140593023625
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.35643059421251711869173703897540183834515390750185753491093049196507261982132
Short name T325
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:27:55 PM PDT 23
Finished Nov 01 02:28:00 PM PDT 23
Peak memory 205808 kb
Host smart-5210fae1-3303-408b-9113-1d635902b8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35643059421251711869173703897540183834515390750185753491093049196507261982132 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 256.edn_genbits.35643059421251711869173703897540183834515390750185753491093049196507261982132
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.10118718869278859404103095194256331291847862768908414242506147754215170603436
Short name T663
Test name
Test status
Simulation time 17999183 ps
CPU time 1.15 seconds
Started Nov 01 02:28:02 PM PDT 23
Finished Nov 01 02:28:07 PM PDT 23
Peak memory 205904 kb
Host smart-a3c969c6-fcee-4e14-9428-2835e29507a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10118718869278859404103095194256331291847862768908414242506147754215170603436 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 257.edn_genbits.10118718869278859404103095194256331291847862768908414242506147754215170603436
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.79948235651175182816850050547723455335403883218498629697931198381840663174580
Short name T625
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 01 02:27:56 PM PDT 23
Finished Nov 01 02:28:01 PM PDT 23
Peak memory 205880 kb
Host smart-ed2da60d-cbfc-452a-9e6b-90b4f6225e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79948235651175182816850050547723455335403883218498629697931198381840663174580 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 258.edn_genbits.79948235651175182816850050547723455335403883218498629697931198381840663174580
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.17792581989650990484791581017312024582450015222794776579162190211809180661504
Short name T530
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:27:52 PM PDT 23
Finished Nov 01 02:27:57 PM PDT 23
Peak memory 205780 kb
Host smart-496b71a8-8a52-4b44-87f4-4deac8373c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17792581989650990484791581017312024582450015222794776579162190211809180661504 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 259.edn_genbits.17792581989650990484791581017312024582450015222794776579162190211809180661504
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.33596152955041839917055150324066646420537449155900257943097501703810101853976
Short name T350
Test name
Test status
Simulation time 18259183 ps
CPU time 1.01 seconds
Started Nov 01 02:26:31 PM PDT 23
Finished Nov 01 02:26:33 PM PDT 23
Peak memory 205616 kb
Host smart-0e256621-6799-4f0a-8470-4077af8fef4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33596152955041839917055150324066646420537449155900257943097501703810101853976 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 26.edn_alert.33596152955041839917055150324066646420537449155900257943097501703810101853976
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.6945056794814908930772659319326769594468470310527496688117632686624244831231
Short name T639
Test name
Test status
Simulation time 28184990 ps
CPU time 0.9 seconds
Started Nov 01 02:26:48 PM PDT 23
Finished Nov 01 02:26:51 PM PDT 23
Peak memory 205524 kb
Host smart-1df00f66-5855-4adb-8b5c-33c34043661d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6945056794814908930772659319326769594468470310527496688117632686624244831231 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.edn_alert_test.6945056794814908930772659319326769594468470310527496688117632686624244831231
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.106985531098047031253775327473315282634343699502587769992495111503360731682726
Short name T742
Test name
Test status
Simulation time 12219183 ps
CPU time 0.89 seconds
Started Nov 01 02:26:39 PM PDT 23
Finished Nov 01 02:26:44 PM PDT 23
Peak memory 214948 kb
Host smart-c6073a72-7768-4252-aadd-460b1511867f
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106985531098047031253775327473315282634343699502587769992495111503360731682726 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 26.edn_disable.106985531098047031253775327473315282634343699502587769992495111503360731682726
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.96651301741202605790691257525863783516260166306456715445876954861658751602280
Short name T619
Test name
Test status
Simulation time 17319183 ps
CPU time 0.91 seconds
Started Nov 01 02:26:39 PM PDT 23
Finished Nov 01 02:26:44 PM PDT 23
Peak memory 214844 kb
Host smart-1cabede7-1d6a-485a-8aa5-bf9035a54a37
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96651301741202605790691257525863783516260166306456715445876954861658751602280 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable_auto_req_mode.9665130174120260579069125752586378351626016630645671544587
6954861658751602280
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.84994941007449488094472561064594939034277375368833125019849537575337831256568
Short name T623
Test name
Test status
Simulation time 24963823 ps
CPU time 1.13 seconds
Started Nov 01 02:26:40 PM PDT 23
Finished Nov 01 02:26:46 PM PDT 23
Peak memory 230464 kb
Host smart-f796b74e-cc86-4d0b-a75e-3b2560dbeb7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84994941007449488094472561064594939034277375368833125019849537575337831256568 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.edn_err.84994941007449488094472561064594939034277375368833125019849537575337831256568
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.50272153791968801790811931934811339674395688761192827430387045899282401588746
Short name T721
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 01 02:26:32 PM PDT 23
Finished Nov 01 02:26:34 PM PDT 23
Peak memory 205848 kb
Host smart-7a7f0729-1893-4d62-8b79-cd8325de930c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50272153791968801790811931934811339674395688761192827430387045899282401588746 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.edn_genbits.50272153791968801790811931934811339674395688761192827430387045899282401588746
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.94151790665541994161658292150951760446400364996564318178945860901690930941453
Short name T33
Test name
Test status
Simulation time 18439183 ps
CPU time 1.11 seconds
Started Nov 01 02:26:50 PM PDT 23
Finished Nov 01 02:26:53 PM PDT 23
Peak memory 222316 kb
Host smart-8016aed7-3486-48d6-b9ba-cdd1a3fa1000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94151790665541994161658292150951760446400364996564318178945860901690930941453 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.edn_intr.94151790665541994161658292150951760446400364996564318178945860901690930941453
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.4690382557164106078399042794344989366034000394533098661127549338000376376220
Short name T469
Test name
Test status
Simulation time 13059183 ps
CPU time 0.92 seconds
Started Nov 01 02:26:30 PM PDT 23
Finished Nov 01 02:26:32 PM PDT 23
Peak memory 205388 kb
Host smart-e4b31a5a-e1e9-4375-9a36-95743edf298d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4690382557164106078399042794344989366034000394533098661127549338000376376220 -assert nopostproc +UVM_TESTNAME=edn_smoke_
test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.edn_smoke.4690382557164106078399042794344989366034000394533098661127549338000376376220
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.5514954251361955455907090748941571123852952454246970949020880256561282187058
Short name T945
Test name
Test status
Simulation time 154489183 ps
CPU time 4.1 seconds
Started Nov 01 02:26:30 PM PDT 23
Finished Nov 01 02:26:35 PM PDT 23
Peak memory 206448 kb
Host smart-cc0f7097-2aa2-4f35-8b2f-728540059252
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5514954251361955455907090748941571123852952454246970949020880256561282187058 -assert nopost
proc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.5514954251361955455907090748941571123852952454246970949020880256561282187058
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.35625535212597877913532624176440893132788032910044560794688136297589072636413
Short name T1
Test name
Test status
Simulation time 41708099183 ps
CPU time 1077.7 seconds
Started Nov 01 02:26:40 PM PDT 23
Finished Nov 01 02:44:42 PM PDT 23
Peak memory 215904 kb
Host smart-959b1d12-3d0f-4fa4-b1e8-1fb498b9cb4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356255352125978779135326241
76440893132788032910044560794688136297589072636413 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.35625535212
597877913532624176440893132788032910044560794688136297589072636413
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.106840173012481802153107431835221134144528848957362833263873775981127285768060
Short name T462
Test name
Test status
Simulation time 17999183 ps
CPU time 1.16 seconds
Started Nov 01 02:27:53 PM PDT 23
Finished Nov 01 02:27:57 PM PDT 23
Peak memory 205776 kb
Host smart-d3a2a288-2722-47a4-aea2-f441f9d7a6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106840173012481802153107431835221134144528848957362833263873775981127285768060 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 260.edn_genbits.106840173012481802153107431835221134144528848957362833263873775981127285768060
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.114743516250837817312704004542785067473110260562945658749727141443375313969111
Short name T389
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 01 02:28:01 PM PDT 23
Finished Nov 01 02:28:06 PM PDT 23
Peak memory 205896 kb
Host smart-d67280f5-502f-4bad-be1c-df9f79c3cb9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114743516250837817312704004542785067473110260562945658749727141443375313969111 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 261.edn_genbits.114743516250837817312704004542785067473110260562945658749727141443375313969111
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.104298686032117349277307385847231612865020175520045019620556435942582539809694
Short name T320
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:27:56 PM PDT 23
Finished Nov 01 02:28:01 PM PDT 23
Peak memory 205868 kb
Host smart-54d4fc3a-0a56-451e-a39b-2f11fe3066db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104298686032117349277307385847231612865020175520045019620556435942582539809694 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 262.edn_genbits.104298686032117349277307385847231612865020175520045019620556435942582539809694
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.23425721563031117426935407002269655932264944594980560219118300250019465515706
Short name T756
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Nov 01 02:27:54 PM PDT 23
Finished Nov 01 02:27:59 PM PDT 23
Peak memory 205900 kb
Host smart-b5ebcab1-6e82-4eec-ae21-aeafe83bbeff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23425721563031117426935407002269655932264944594980560219118300250019465515706 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 263.edn_genbits.23425721563031117426935407002269655932264944594980560219118300250019465515706
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.46351190493088497239606802251667860331590975262683592457204801517434378281612
Short name T304
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:27:55 PM PDT 23
Finished Nov 01 02:28:00 PM PDT 23
Peak memory 205768 kb
Host smart-e3a0ae1b-ea0a-4e2d-b814-b2da14c17def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46351190493088497239606802251667860331590975262683592457204801517434378281612 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 264.edn_genbits.46351190493088497239606802251667860331590975262683592457204801517434378281612
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.67249104433323078763300064640723727037467803377223040738998253649838738437346
Short name T714
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 01 02:27:54 PM PDT 23
Finished Nov 01 02:27:59 PM PDT 23
Peak memory 205788 kb
Host smart-8621884a-9da9-495a-8fd5-2c4970dd3f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67249104433323078763300064640723727037467803377223040738998253649838738437346 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 265.edn_genbits.67249104433323078763300064640723727037467803377223040738998253649838738437346
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.89979001938688523426850932519757007501399557394940978517340949432321410154492
Short name T465
Test name
Test status
Simulation time 17999183 ps
CPU time 1.15 seconds
Started Nov 01 02:27:56 PM PDT 23
Finished Nov 01 02:28:01 PM PDT 23
Peak memory 205808 kb
Host smart-f3db793f-c118-4f0d-ae91-4e467938bdb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89979001938688523426850932519757007501399557394940978517340949432321410154492 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 266.edn_genbits.89979001938688523426850932519757007501399557394940978517340949432321410154492
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.94340224587090010383788193955929247530977271755737399594660258868513024109731
Short name T56
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 01 02:27:58 PM PDT 23
Finished Nov 01 02:28:04 PM PDT 23
Peak memory 205880 kb
Host smart-407adc48-a998-4eef-b15d-8249b0d2cf0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94340224587090010383788193955929247530977271755737399594660258868513024109731 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 267.edn_genbits.94340224587090010383788193955929247530977271755737399594660258868513024109731
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.70641377544570800039092132462984170085764884811779008217574954649293255450146
Short name T269
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 01 02:27:54 PM PDT 23
Finished Nov 01 02:27:59 PM PDT 23
Peak memory 205900 kb
Host smart-e55a7656-ad01-435f-b2e2-d47f0595bb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70641377544570800039092132462984170085764884811779008217574954649293255450146 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 268.edn_genbits.70641377544570800039092132462984170085764884811779008217574954649293255450146
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.42298623856331286788913886013187951720030251839973618672655066401970689172086
Short name T861
Test name
Test status
Simulation time 17999183 ps
CPU time 1.18 seconds
Started Nov 01 02:27:57 PM PDT 23
Finished Nov 01 02:28:03 PM PDT 23
Peak memory 205888 kb
Host smart-d294305f-d9fa-4161-8507-5265018a4c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42298623856331286788913886013187951720030251839973618672655066401970689172086 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 269.edn_genbits.42298623856331286788913886013187951720030251839973618672655066401970689172086
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.87046738560835922179312164443103328953287878151481107199318418548215838855284
Short name T254
Test name
Test status
Simulation time 18259183 ps
CPU time 0.99 seconds
Started Nov 01 02:26:29 PM PDT 23
Finished Nov 01 02:26:31 PM PDT 23
Peak memory 205576 kb
Host smart-70e94aee-43f3-4162-9ddc-6688df99c837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87046738560835922179312164443103328953287878151481107199318418548215838855284 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 27.edn_alert.87046738560835922179312164443103328953287878151481107199318418548215838855284
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.8602499291962642164566674226930092352086272970483014145640070626457248160701
Short name T615
Test name
Test status
Simulation time 28184990 ps
CPU time 0.92 seconds
Started Nov 01 02:26:40 PM PDT 23
Finished Nov 01 02:26:46 PM PDT 23
Peak memory 204908 kb
Host smart-e9e7018f-88f9-4e82-9788-d4863b399eb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8602499291962642164566674226930092352086272970483014145640070626457248160701 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.edn_alert_test.8602499291962642164566674226930092352086272970483014145640070626457248160701
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.48472152494116524513056705613154483273527375271849308477108333080990908279378
Short name T61
Test name
Test status
Simulation time 12219183 ps
CPU time 0.86 seconds
Started Nov 01 02:27:02 PM PDT 23
Finished Nov 01 02:27:17 PM PDT 23
Peak memory 214796 kb
Host smart-9cd3347f-8227-4b11-a312-3e08df8a1bfd
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48472152494116524513056705613154483273527375271849308477108333080990908279378 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.edn_disable.48472152494116524513056705613154483273527375271849308477108333080990908279378
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.56177826308134975607488796098979496280905528624866190991067189052148241233375
Short name T359
Test name
Test status
Simulation time 17319183 ps
CPU time 0.94 seconds
Started Nov 01 02:26:54 PM PDT 23
Finished Nov 01 02:27:01 PM PDT 23
Peak memory 214944 kb
Host smart-9926b609-f0e4-4101-8a77-98a667363b69
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56177826308134975607488796098979496280905528624866190991067189052148241233375 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable_auto_req_mode.5617782630813497560748879609897949628090552862486619099106
7189052148241233375
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.78471614779117271774009009789202791855462942588265974275778053147061978112068
Short name T640
Test name
Test status
Simulation time 24963823 ps
CPU time 1.14 seconds
Started Nov 01 02:26:36 PM PDT 23
Finished Nov 01 02:26:38 PM PDT 23
Peak memory 230392 kb
Host smart-841375ff-f470-4970-8ff8-576caf509534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78471614779117271774009009789202791855462942588265974275778053147061978112068 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.edn_err.78471614779117271774009009789202791855462942588265974275778053147061978112068
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.21679774523812696607907365186939930017166394273099484578906442106707576252131
Short name T459
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:26:30 PM PDT 23
Finished Nov 01 02:26:32 PM PDT 23
Peak memory 205872 kb
Host smart-1f7ebce3-9dbd-4318-b3b5-80e0de9caea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21679774523812696607907365186939930017166394273099484578906442106707576252131 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.edn_genbits.21679774523812696607907365186939930017166394273099484578906442106707576252131
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.40731112556575873377358946074914683950539094179910827305368072127554913286517
Short name T353
Test name
Test status
Simulation time 18439183 ps
CPU time 1.14 seconds
Started Nov 01 02:26:31 PM PDT 23
Finished Nov 01 02:26:33 PM PDT 23
Peak memory 222316 kb
Host smart-394225da-34b4-4717-b27d-b41904169702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40731112556575873377358946074914683950539094179910827305368072127554913286517 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.edn_intr.40731112556575873377358946074914683950539094179910827305368072127554913286517
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.85502005430855493228812006358597028189651418575075914911353102538739479060358
Short name T682
Test name
Test status
Simulation time 13059183 ps
CPU time 0.9 seconds
Started Nov 01 02:26:32 PM PDT 23
Finished Nov 01 02:26:34 PM PDT 23
Peak memory 205424 kb
Host smart-dff8d964-4bf6-408d-9d38-ce6e54751206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85502005430855493228812006358597028189651418575075914911353102538739479060358 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 27.edn_smoke.85502005430855493228812006358597028189651418575075914911353102538739479060358
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.31146812094898126831191617299050988716148804184501208357497935658110028881814
Short name T15
Test name
Test status
Simulation time 154489183 ps
CPU time 3.92 seconds
Started Nov 01 02:26:34 PM PDT 23
Finished Nov 01 02:26:40 PM PDT 23
Peak memory 206456 kb
Host smart-b05342df-751b-4773-b58c-955248ef904d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31146812094898126831191617299050988716148804184501208357497935658110028881814 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.31146812094898126831191617299050988716148804184501208357497935658110028881814
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.33816200837729859368922480093876140956639537175007974741334306538582170128965
Short name T837
Test name
Test status
Simulation time 41708099183 ps
CPU time 1125.45 seconds
Started Nov 01 02:26:52 PM PDT 23
Finished Nov 01 02:45:43 PM PDT 23
Peak memory 215920 kb
Host smart-14106595-8a1e-413d-b3c1-bb4988994df0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338162008377298593689224800
93876140956639537175007974741334306538582170128965 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.33816200837
729859368922480093876140956639537175007974741334306538582170128965
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.108570003987784829598235061794537787268635037247673916261689637195915223451441
Short name T249
Test name
Test status
Simulation time 17999183 ps
CPU time 1.06 seconds
Started Nov 01 02:27:56 PM PDT 23
Finished Nov 01 02:28:02 PM PDT 23
Peak memory 205876 kb
Host smart-7d9eca92-58b1-42a4-9a6e-52faf46e0eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108570003987784829598235061794537787268635037247673916261689637195915223451441 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 270.edn_genbits.108570003987784829598235061794537787268635037247673916261689637195915223451441
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.95052304472081305117409916146124928143337929135869820393352860808241031672660
Short name T738
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 01 02:27:56 PM PDT 23
Finished Nov 01 02:28:01 PM PDT 23
Peak memory 205920 kb
Host smart-7bc1e655-cc81-403f-916f-53aa9ff55529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95052304472081305117409916146124928143337929135869820393352860808241031672660 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 271.edn_genbits.95052304472081305117409916146124928143337929135869820393352860808241031672660
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.51832395431385418918121096000217381461928195108892860490644888973842670004990
Short name T894
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Nov 01 02:27:53 PM PDT 23
Finished Nov 01 02:27:57 PM PDT 23
Peak memory 205892 kb
Host smart-eb703af2-606b-4397-9137-eef45e5cf08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51832395431385418918121096000217381461928195108892860490644888973842670004990 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 272.edn_genbits.51832395431385418918121096000217381461928195108892860490644888973842670004990
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.68009080837532523680205048587524569627943662836295869744509761938422862537047
Short name T620
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 01 02:27:57 PM PDT 23
Finished Nov 01 02:28:02 PM PDT 23
Peak memory 205896 kb
Host smart-fe8a9dff-f773-4bd8-b3ba-e02723ec42e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68009080837532523680205048587524569627943662836295869744509761938422862537047 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 273.edn_genbits.68009080837532523680205048587524569627943662836295869744509761938422862537047
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.76730202963736464360818741642020348215709464946919922082730100587611869794208
Short name T481
Test name
Test status
Simulation time 17999183 ps
CPU time 1.17 seconds
Started Nov 01 02:28:00 PM PDT 23
Finished Nov 01 02:28:06 PM PDT 23
Peak memory 205888 kb
Host smart-77eaece5-54b1-42dd-969f-53fbff1dc194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76730202963736464360818741642020348215709464946919922082730100587611869794208 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 274.edn_genbits.76730202963736464360818741642020348215709464946919922082730100587611869794208
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.76888833359682198488766503282492686024113468370201372027734150765295318192088
Short name T58
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:27:56 PM PDT 23
Finished Nov 01 02:28:02 PM PDT 23
Peak memory 205888 kb
Host smart-7e069b99-044a-46df-9234-e5ff6e01eb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76888833359682198488766503282492686024113468370201372027734150765295318192088 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 275.edn_genbits.76888833359682198488766503282492686024113468370201372027734150765295318192088
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.20985428221259374433943863793138918163861591109353603169243104347223162442216
Short name T672
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Nov 01 02:27:58 PM PDT 23
Finished Nov 01 02:28:04 PM PDT 23
Peak memory 205912 kb
Host smart-d8641ea6-c579-4e5f-a4b1-7768ceb7b04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20985428221259374433943863793138918163861591109353603169243104347223162442216 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 276.edn_genbits.20985428221259374433943863793138918163861591109353603169243104347223162442216
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.31879170407453807772921761302979506115185958609763318683885162271438885332159
Short name T411
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 01 02:27:59 PM PDT 23
Finished Nov 01 02:28:05 PM PDT 23
Peak memory 205856 kb
Host smart-d9c061c6-5ef0-4b4e-b4bd-7172883b9ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31879170407453807772921761302979506115185958609763318683885162271438885332159 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 277.edn_genbits.31879170407453807772921761302979506115185958609763318683885162271438885332159
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.26714977796683362298675639132706918434655738049798868244430905420698834310815
Short name T366
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:28:00 PM PDT 23
Finished Nov 01 02:28:06 PM PDT 23
Peak memory 205856 kb
Host smart-521a2a81-2f69-4c47-ae15-758297e38453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26714977796683362298675639132706918434655738049798868244430905420698834310815 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 278.edn_genbits.26714977796683362298675639132706918434655738049798868244430905420698834310815
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.113417204760591087564440789062634321524682820597362936048606439491957911063457
Short name T911
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 01 02:28:03 PM PDT 23
Finished Nov 01 02:28:07 PM PDT 23
Peak memory 205836 kb
Host smart-40e7f074-4e38-4060-b46d-f560aa92018e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113417204760591087564440789062634321524682820597362936048606439491957911063457 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 279.edn_genbits.113417204760591087564440789062634321524682820597362936048606439491957911063457
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.7640137912553239623345362917483753693781749322161105753188267584586231119814
Short name T644
Test name
Test status
Simulation time 18259183 ps
CPU time 0.98 seconds
Started Nov 01 02:26:53 PM PDT 23
Finished Nov 01 02:26:59 PM PDT 23
Peak memory 205624 kb
Host smart-4f7ecaf4-740e-43e8-952a-0b90da0190a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7640137912553239623345362917483753693781749322161105753188267584586231119814 -assert nopostproc +UVM_TESTNAME=edn_alert_
test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.edn_alert.7640137912553239623345362917483753693781749322161105753188267584586231119814
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.48792829080688866470548273712513045589459851323418434929027187623463809287161
Short name T318
Test name
Test status
Simulation time 28184990 ps
CPU time 0.91 seconds
Started Nov 01 02:26:56 PM PDT 23
Finished Nov 01 02:27:04 PM PDT 23
Peak memory 205516 kb
Host smart-26efa1ff-0ed0-482b-a436-9d0a2dda7764
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48792829080688866470548273712513045589459851323418434929027187623463809287161 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.edn_alert_test.48792829080688866470548273712513045589459851323418434929027187623463809287161
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.9459026214944595709330434492546826765399527913520322057429855054937643002819
Short name T612
Test name
Test status
Simulation time 12219183 ps
CPU time 0.86 seconds
Started Nov 01 02:27:04 PM PDT 23
Finished Nov 01 02:27:20 PM PDT 23
Peak memory 214884 kb
Host smart-1a927b1e-e542-43e5-862b-5770d31dfc91
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9459026214944595709330434492546826765399527913520322057429855054937643002819 -assert nopostproc
+UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.edn_disable.9459026214944595709330434492546826765399527913520322057429855054937643002819
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.40587315195532328441990023196771803106156158405810051940003302125602757035405
Short name T333
Test name
Test status
Simulation time 17319183 ps
CPU time 0.94 seconds
Started Nov 01 02:26:54 PM PDT 23
Finished Nov 01 02:27:01 PM PDT 23
Peak memory 214932 kb
Host smart-8d1d2fcf-7f18-4209-8a82-681ade078650
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40587315195532328441990023196771803106156158405810051940003302125602757035405 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable_auto_req_mode.4058731519553232844199002319677180310615615840581005194000
3302125602757035405
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.10637048290134825130576060292911223046906348809447709943697514767818079949634
Short name T622
Test name
Test status
Simulation time 24963823 ps
CPU time 1.17 seconds
Started Nov 01 02:26:57 PM PDT 23
Finished Nov 01 02:27:09 PM PDT 23
Peak memory 230476 kb
Host smart-cffd758d-69a1-4260-b7ef-882f892015ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10637048290134825130576060292911223046906348809447709943697514767818079949634 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.edn_err.10637048290134825130576060292911223046906348809447709943697514767818079949634
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.91651403527866551163128679293496119206142373170037150419234697749318908565982
Short name T485
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:26:45 PM PDT 23
Finished Nov 01 02:26:50 PM PDT 23
Peak memory 205900 kb
Host smart-495a8682-0788-4954-b7d4-44f280671773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91651403527866551163128679293496119206142373170037150419234697749318908565982 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.edn_genbits.91651403527866551163128679293496119206142373170037150419234697749318908565982
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.108276703200130888968309405946248236675497495764019271161709137539083220092225
Short name T285
Test name
Test status
Simulation time 18439183 ps
CPU time 1.13 seconds
Started Nov 01 02:27:02 PM PDT 23
Finished Nov 01 02:27:18 PM PDT 23
Peak memory 222308 kb
Host smart-8cca23db-32d4-4fd8-b87b-04a0c4acde85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108276703200130888968309405946248236675497495764019271161709137539083220092225 -assert nopostproc +UVM_TESTNAME=edn_intr
_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.edn_intr.108276703200130888968309405946248236675497495764019271161709137539083220092225
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.78844820250119828198639298842634418575607449192860957580602864954415476589596
Short name T946
Test name
Test status
Simulation time 13059183 ps
CPU time 0.87 seconds
Started Nov 01 02:26:38 PM PDT 23
Finished Nov 01 02:26:43 PM PDT 23
Peak memory 205328 kb
Host smart-ca6dea6d-c1cd-414a-b07a-26e2e9139862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78844820250119828198639298842634418575607449192860957580602864954415476589596 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 28.edn_smoke.78844820250119828198639298842634418575607449192860957580602864954415476589596
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.7996926464034241803806835099506467875038326939104705088312048011756740563292
Short name T904
Test name
Test status
Simulation time 154489183 ps
CPU time 3.98 seconds
Started Nov 01 02:26:50 PM PDT 23
Finished Nov 01 02:26:56 PM PDT 23
Peak memory 206460 kb
Host smart-3e96b026-4e39-4c1d-a8a8-7314b6b335c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7996926464034241803806835099506467875038326939104705088312048011756740563292 -assert nopost
proc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.7996926464034241803806835099506467875038326939104705088312048011756740563292
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.42308746855335156301308145616939821361613073439738669998499780154282126090509
Short name T737
Test name
Test status
Simulation time 41708099183 ps
CPU time 1119.37 seconds
Started Nov 01 02:27:03 PM PDT 23
Finished Nov 01 02:45:57 PM PDT 23
Peak memory 215920 kb
Host smart-b038b686-588f-40a8-a2c6-e8e9942cbf04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423087468553351563013081456
16939821361613073439738669998499780154282126090509 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.42308746855
335156301308145616939821361613073439738669998499780154282126090509
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.83654648322393922527158061432217768196121856423940019087894120162491567246214
Short name T978
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:27:57 PM PDT 23
Finished Nov 01 02:28:02 PM PDT 23
Peak memory 205800 kb
Host smart-f0b87c58-04e4-4ea0-88fb-b508537f81b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83654648322393922527158061432217768196121856423940019087894120162491567246214 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 280.edn_genbits.83654648322393922527158061432217768196121856423940019087894120162491567246214
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.50242672257959420509285686428175961996556039533125759111129479117234735994093
Short name T41
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 01 02:28:03 PM PDT 23
Finished Nov 01 02:28:07 PM PDT 23
Peak memory 205840 kb
Host smart-6e7dc8e0-797f-492b-99fd-7f00751cc65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50242672257959420509285686428175961996556039533125759111129479117234735994093 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 281.edn_genbits.50242672257959420509285686428175961996556039533125759111129479117234735994093
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.14507348344312646271420745583650623057251877701239797348314936625774354509510
Short name T367
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 01 02:28:00 PM PDT 23
Finished Nov 01 02:28:05 PM PDT 23
Peak memory 205860 kb
Host smart-264115b5-76a2-4c25-97ba-4d56b6bf23d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14507348344312646271420745583650623057251877701239797348314936625774354509510 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 282.edn_genbits.14507348344312646271420745583650623057251877701239797348314936625774354509510
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.52102552993907243076609455098919136802005451984632732314366639312132023721964
Short name T276
Test name
Test status
Simulation time 17999183 ps
CPU time 1.15 seconds
Started Nov 01 02:28:22 PM PDT 23
Finished Nov 01 02:28:24 PM PDT 23
Peak memory 205864 kb
Host smart-52854349-7335-44b0-870b-89d1e3c3a829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52102552993907243076609455098919136802005451984632732314366639312132023721964 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 283.edn_genbits.52102552993907243076609455098919136802005451984632732314366639312132023721964
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.88915613465810580969196225390319111104188480123948641253484362709891025276559
Short name T502
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 01 02:28:22 PM PDT 23
Finished Nov 01 02:28:24 PM PDT 23
Peak memory 205864 kb
Host smart-ac7420bd-b902-443e-94f1-8b3fcc9a60a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88915613465810580969196225390319111104188480123948641253484362709891025276559 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 284.edn_genbits.88915613465810580969196225390319111104188480123948641253484362709891025276559
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.85550055261013790581180842584791596907037312465390883988410380342438588094761
Short name T52
Test name
Test status
Simulation time 17999183 ps
CPU time 1.03 seconds
Started Nov 01 02:27:54 PM PDT 23
Finished Nov 01 02:27:59 PM PDT 23
Peak memory 205704 kb
Host smart-97b4afd6-305c-4058-9776-1310c150824a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85550055261013790581180842584791596907037312465390883988410380342438588094761 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 285.edn_genbits.85550055261013790581180842584791596907037312465390883988410380342438588094761
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.55868215707101493247562750803481385690528800262579815768807825033775741384330
Short name T306
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 01 02:28:21 PM PDT 23
Finished Nov 01 02:28:23 PM PDT 23
Peak memory 205904 kb
Host smart-37e0c805-0358-46d9-80a6-9f13da5997b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55868215707101493247562750803481385690528800262579815768807825033775741384330 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 286.edn_genbits.55868215707101493247562750803481385690528800262579815768807825033775741384330
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.72606988179508179322609882267742236181215919720145600861988363470814366909843
Short name T842
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 01 02:28:12 PM PDT 23
Finished Nov 01 02:28:14 PM PDT 23
Peak memory 205888 kb
Host smart-f37777bf-4491-45b9-81d5-79fc0e1b8e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72606988179508179322609882267742236181215919720145600861988363470814366909843 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 287.edn_genbits.72606988179508179322609882267742236181215919720145600861988363470814366909843
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.24503234666017207076128492366626255475545409533766215496923145152990236964108
Short name T409
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:28:44 PM PDT 23
Finished Nov 01 02:28:48 PM PDT 23
Peak memory 205864 kb
Host smart-d32af3a2-59a2-4952-9338-7e8813b4486d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24503234666017207076128492366626255475545409533766215496923145152990236964108 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 288.edn_genbits.24503234666017207076128492366626255475545409533766215496923145152990236964108
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.59754185344216000240656629509419403355906549671870929967013077604087205310194
Short name T410
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:28:00 PM PDT 23
Finished Nov 01 02:28:06 PM PDT 23
Peak memory 205928 kb
Host smart-01e0386a-60d5-4143-8848-cae5c867f7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59754185344216000240656629509419403355906549671870929967013077604087205310194 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 289.edn_genbits.59754185344216000240656629509419403355906549671870929967013077604087205310194
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.30532722982298790372598753148311916790020853958742309631081623908824875708277
Short name T261
Test name
Test status
Simulation time 18259183 ps
CPU time 1 seconds
Started Nov 01 02:27:14 PM PDT 23
Finished Nov 01 02:27:30 PM PDT 23
Peak memory 205572 kb
Host smart-5bd811e7-920a-4f6e-9a34-32d014f3b689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30532722982298790372598753148311916790020853958742309631081623908824875708277 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 29.edn_alert.30532722982298790372598753148311916790020853958742309631081623908824875708277
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.10305238467088923097568771700030408060674196208413152753858349460144469758278
Short name T633
Test name
Test status
Simulation time 28184990 ps
CPU time 0.87 seconds
Started Nov 01 02:27:01 PM PDT 23
Finished Nov 01 02:27:15 PM PDT 23
Peak memory 205544 kb
Host smart-ae04224f-be2a-4ab2-a1cd-513b0b4e9257
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10305238467088923097568771700030408060674196208413152753858349460144469758278 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.edn_alert_test.10305238467088923097568771700030408060674196208413152753858349460144469758278
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.105563070505280295825786316500396924571585635899864772854544347122345928088712
Short name T938
Test name
Test status
Simulation time 12219183 ps
CPU time 0.89 seconds
Started Nov 01 02:27:04 PM PDT 23
Finished Nov 01 02:27:19 PM PDT 23
Peak memory 214948 kb
Host smart-5e95b465-d4d9-4f5b-a143-0bb95b190e26
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105563070505280295825786316500396924571585635899864772854544347122345928088712 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 29.edn_disable.105563070505280295825786316500396924571585635899864772854544347122345928088712
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.16636395020448292318560505407864839237619327084895459161334490151049321578041
Short name T761
Test name
Test status
Simulation time 17319183 ps
CPU time 0.92 seconds
Started Nov 01 02:27:21 PM PDT 23
Finished Nov 01 02:27:36 PM PDT 23
Peak memory 214884 kb
Host smart-d3aad83d-73c2-43c5-91e5-62d876e74295
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16636395020448292318560505407864839237619327084895459161334490151049321578041 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable_auto_req_mode.1663639502044829231856050540786483923761932708489545916133
4490151049321578041
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.41175571889706414459492372599470731329119749909343523696668267765502115961097
Short name T925
Test name
Test status
Simulation time 24963823 ps
CPU time 1.12 seconds
Started Nov 01 02:27:16 PM PDT 23
Finished Nov 01 02:27:31 PM PDT 23
Peak memory 230392 kb
Host smart-f13f9681-d952-4028-b7f9-cb1344c500b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41175571889706414459492372599470731329119749909343523696668267765502115961097 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.edn_err.41175571889706414459492372599470731329119749909343523696668267765502115961097
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.62957938964839445927953332814469599172169715989087054228310411539667151801601
Short name T666
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 01 02:27:12 PM PDT 23
Finished Nov 01 02:27:28 PM PDT 23
Peak memory 205932 kb
Host smart-ab0d3772-64de-45ff-88ff-00205275b8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62957938964839445927953332814469599172169715989087054228310411539667151801601 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.edn_genbits.62957938964839445927953332814469599172169715989087054228310411539667151801601
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_smoke.73757337590010824363086850320762675273971173446936690885486275659322831139714
Short name T676
Test name
Test status
Simulation time 13059183 ps
CPU time 0.87 seconds
Started Nov 01 02:26:57 PM PDT 23
Finished Nov 01 02:27:08 PM PDT 23
Peak memory 205392 kb
Host smart-fdc7b7f2-825d-4417-84ac-37d534f0a3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73757337590010824363086850320762675273971173446936690885486275659322831139714 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 29.edn_smoke.73757337590010824363086850320762675273971173446936690885486275659322831139714
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.91830451287639818011068555656410130615919682762384344314995037417762281748687
Short name T576
Test name
Test status
Simulation time 154489183 ps
CPU time 3.88 seconds
Started Nov 01 02:27:03 PM PDT 23
Finished Nov 01 02:27:21 PM PDT 23
Peak memory 206328 kb
Host smart-4234c6e0-0766-4a35-ada1-7f06efd085a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91830451287639818011068555656410130615919682762384344314995037417762281748687 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.91830451287639818011068555656410130615919682762384344314995037417762281748687
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.16062446855679961773282281459106796961950594198830464961213130254522294264160
Short name T795
Test name
Test status
Simulation time 41708099183 ps
CPU time 1070.93 seconds
Started Nov 01 02:26:57 PM PDT 23
Finished Nov 01 02:44:59 PM PDT 23
Peak memory 216008 kb
Host smart-b10d2bf0-1706-455a-ab93-810c98c22729
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160624468556799617732822814
59106796961950594198830464961213130254522294264160 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.16062446855
679961773282281459106796961950594198830464961213130254522294264160
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.1455862434754444819990621295128648640143902260562352670663625632887267691855
Short name T452
Test name
Test status
Simulation time 17999183 ps
CPU time 1.21 seconds
Started Nov 01 02:28:09 PM PDT 23
Finished Nov 01 02:28:11 PM PDT 23
Peak memory 205856 kb
Host smart-1cd6c72d-2210-469d-95a9-e5b0c8a535f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455862434754444819990621295128648640143902260562352670663625632887267691855 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 290.edn_genbits.1455862434754444819990621295128648640143902260562352670663625632887267691855
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.7691995732623987426514464736544939204927792344614644526576151280744831236878
Short name T390
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 01 02:28:25 PM PDT 23
Finished Nov 01 02:28:29 PM PDT 23
Peak memory 205800 kb
Host smart-78acdd9b-a9a2-440d-8251-1c748e53dbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7691995732623987426514464736544939204927792344614644526576151280744831236878 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 291.edn_genbits.7691995732623987426514464736544939204927792344614644526576151280744831236878
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.109481612707892226159730163119364422665864895184645316849213499514809952960688
Short name T571
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 01 02:28:26 PM PDT 23
Finished Nov 01 02:28:30 PM PDT 23
Peak memory 205908 kb
Host smart-b4cc2175-8d99-4031-a09f-4f538d8db777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109481612707892226159730163119364422665864895184645316849213499514809952960688 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 292.edn_genbits.109481612707892226159730163119364422665864895184645316849213499514809952960688
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.35362739895161259977419709840106585881112115592199522440450961073256622574616
Short name T310
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 01 02:28:05 PM PDT 23
Finished Nov 01 02:28:08 PM PDT 23
Peak memory 205840 kb
Host smart-0944d647-c717-49c2-be22-3336024d171a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35362739895161259977419709840106585881112115592199522440450961073256622574616 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 293.edn_genbits.35362739895161259977419709840106585881112115592199522440450961073256622574616
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.94457336349682453725449897466421306686196780544934080463273964983161583396242
Short name T297
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 01 02:28:43 PM PDT 23
Finished Nov 01 02:28:47 PM PDT 23
Peak memory 205808 kb
Host smart-b526ad1e-d0d0-47fa-9992-c9a184a6fa3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94457336349682453725449897466421306686196780544934080463273964983161583396242 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 294.edn_genbits.94457336349682453725449897466421306686196780544934080463273964983161583396242
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.28354820845349198957647590044150506097535111300803807256405998606009911625603
Short name T889
Test name
Test status
Simulation time 17999183 ps
CPU time 1.2 seconds
Started Nov 01 02:28:18 PM PDT 23
Finished Nov 01 02:28:20 PM PDT 23
Peak memory 205892 kb
Host smart-1e0810d9-56dd-4f41-8918-6500e7882a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28354820845349198957647590044150506097535111300803807256405998606009911625603 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 295.edn_genbits.28354820845349198957647590044150506097535111300803807256405998606009911625603
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.88388148773212067918786324408639987169985988235130212601529435642880697013326
Short name T253
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:28:34 PM PDT 23
Finished Nov 01 02:28:40 PM PDT 23
Peak memory 205888 kb
Host smart-3237a95a-8d90-434c-81f3-19efe66f4d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88388148773212067918786324408639987169985988235130212601529435642880697013326 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 296.edn_genbits.88388148773212067918786324408639987169985988235130212601529435642880697013326
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.76035221250828257928025072930220480245872339178921692932307298747469964763392
Short name T629
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Nov 01 02:28:56 PM PDT 23
Finished Nov 01 02:28:57 PM PDT 23
Peak memory 205796 kb
Host smart-775f81f0-054b-4d69-b12b-502271e34a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76035221250828257928025072930220480245872339178921692932307298747469964763392 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 297.edn_genbits.76035221250828257928025072930220480245872339178921692932307298747469964763392
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.55921461034970765695726821390391900167626860894678644563091982285544990119459
Short name T838
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:28:45 PM PDT 23
Finished Nov 01 02:28:50 PM PDT 23
Peak memory 205860 kb
Host smart-79a719f2-2d38-4217-b1d9-b199ff0ce9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55921461034970765695726821390391900167626860894678644563091982285544990119459 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 298.edn_genbits.55921461034970765695726821390391900167626860894678644563091982285544990119459
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.18810110356034988271378375654114018506012443407125778504525834918185753400326
Short name T319
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 01 02:29:02 PM PDT 23
Finished Nov 01 02:29:04 PM PDT 23
Peak memory 205856 kb
Host smart-96f524ee-3bd3-4cf1-8a39-5302ab704091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18810110356034988271378375654114018506012443407125778504525834918185753400326 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 299.edn_genbits.18810110356034988271378375654114018506012443407125778504525834918185753400326
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.77812371728562609954263967583350430288385087341702330641205212131281073380592
Short name T487
Test name
Test status
Simulation time 18259183 ps
CPU time 1.03 seconds
Started Nov 01 02:26:38 PM PDT 23
Finished Nov 01 02:26:42 PM PDT 23
Peak memory 205628 kb
Host smart-1c87b54a-872b-4263-baa3-2b1af148b588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77812371728562609954263967583350430288385087341702330641205212131281073380592 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.edn_alert.77812371728562609954263967583350430288385087341702330641205212131281073380592
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.105851593586657216451533300965120458537299073809418625157910780633371205370034
Short name T867
Test name
Test status
Simulation time 28184990 ps
CPU time 0.87 seconds
Started Nov 01 02:25:52 PM PDT 23
Finished Nov 01 02:25:58 PM PDT 23
Peak memory 205516 kb
Host smart-9f4fd9c6-6841-496f-9538-84afaf259bdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105851593586657216451533300965120458537299073809418625157910780633371205370034 -assert nopostp
roc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 3.edn_alert_test.105851593586657216451533300965120458537299073809418625157910780633371205370034
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.4821994397815598797735321208829008627889992541884775647736882018067966026177
Short name T354
Test name
Test status
Simulation time 12219183 ps
CPU time 0.87 seconds
Started Nov 01 02:25:47 PM PDT 23
Finished Nov 01 02:25:56 PM PDT 23
Peak memory 214796 kb
Host smart-1c195882-3e59-439b-a903-41bd9d63ad16
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4821994397815598797735321208829008627889992541884775647736882018067966026177 -assert nopostproc
+UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.edn_disable.4821994397815598797735321208829008627889992541884775647736882018067966026177
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.102638387145764421615894680501356626976205085750719425015579816768427084063494
Short name T537
Test name
Test status
Simulation time 17319183 ps
CPU time 0.92 seconds
Started Nov 01 02:26:23 PM PDT 23
Finished Nov 01 02:26:27 PM PDT 23
Peak memory 214916 kb
Host smart-7ba990bf-b48e-4267-a778-ccb904419482
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102638387145764421615894680501356626976205085750719425015579816768427084063494 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable_auto_req_mode.1026383871457644216158946805013566269762050857507194250155
79816768427084063494
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.84655487006088666452796367820404077084415210275309030313224348354770508282908
Short name T518
Test name
Test status
Simulation time 24963823 ps
CPU time 1.16 seconds
Started Nov 01 02:26:09 PM PDT 23
Finished Nov 01 02:26:14 PM PDT 23
Peak memory 230492 kb
Host smart-43fff9f1-739d-456e-a72e-253a2a8426ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84655487006088666452796367820404077084415210275309030313224348354770508282908 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
edn_err.84655487006088666452796367820404077084415210275309030313224348354770508282908
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.97615857100159832036869218391024987827361700684105633075984159258119111307731
Short name T365
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Nov 01 02:26:02 PM PDT 23
Finished Nov 01 02:26:08 PM PDT 23
Peak memory 205892 kb
Host smart-10689306-0a65-41bc-96f7-cfa732c57c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97615857100159832036869218391024987827361700684105633075984159258119111307731 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.edn_genbits.97615857100159832036869218391024987827361700684105633075984159258119111307731
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.104843838895131359071740748420110754905760949991317991397980512479699272568211
Short name T284
Test name
Test status
Simulation time 18439183 ps
CPU time 1.14 seconds
Started Nov 01 02:25:52 PM PDT 23
Finished Nov 01 02:25:58 PM PDT 23
Peak memory 222360 kb
Host smart-13d4f0ac-259b-4444-823c-90a161e6fa87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104843838895131359071740748420110754905760949991317991397980512479699272568211 -assert nopostproc +UVM_TESTNAME=edn_intr
_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.edn_intr.104843838895131359071740748420110754905760949991317991397980512479699272568211
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.63049477260640066234848272102862558543531254063339464767101040771892597304329
Short name T935
Test name
Test status
Simulation time 11759183 ps
CPU time 0.87 seconds
Started Nov 01 02:25:49 PM PDT 23
Finished Nov 01 02:25:58 PM PDT 23
Peak memory 205388 kb
Host smart-50be0737-232e-454f-bb1b-5190ed2cf634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63049477260640066234848272102862558543531254063339464767101040771892597304329 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.edn_regwen.63049477260640066234848272102862558543531254063339464767101040771892597304329
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_smoke.3173353731785100665759040820749411926070941387565389845220893190079268670755
Short name T624
Test name
Test status
Simulation time 13059183 ps
CPU time 0.94 seconds
Started Nov 01 02:25:45 PM PDT 23
Finished Nov 01 02:25:48 PM PDT 23
Peak memory 205252 kb
Host smart-7827dea6-6cce-400a-8f10-f6e7b64a0963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173353731785100665759040820749411926070941387565389845220893190079268670755 -assert nopostproc +UVM_TESTNAME=edn_smoke_
test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.edn_smoke.3173353731785100665759040820749411926070941387565389845220893190079268670755
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.859654099496410303934870126403106201276308564675530315043742739059452656973
Short name T534
Test name
Test status
Simulation time 154489183 ps
CPU time 4.02 seconds
Started Nov 01 02:25:51 PM PDT 23
Finished Nov 01 02:26:01 PM PDT 23
Peak memory 206420 kb
Host smart-5a404f69-fb6d-45b9-9a21-78340242d6ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859654099496410303934870126403106201276308564675530315043742739059452656973 -assert nopostp
roc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.859654099496410303934870126403106201276308564675530315043742739059452656973
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.58704969418731724128302055022552518018048467039291980770210862418391407519974
Short name T241
Test name
Test status
Simulation time 41708099183 ps
CPU time 1099.84 seconds
Started Nov 01 02:25:51 PM PDT 23
Finished Nov 01 02:44:17 PM PDT 23
Peak memory 215912 kb
Host smart-d1053b40-b4eb-491b-b7ed-08e50e749fa4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587049694187317241283020550
22552518018048467039291980770210862418391407519974 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.587049694187
31724128302055022552518018048467039291980770210862418391407519974
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.101083026525538421098636696574070582377633934258419328960176358612322372649606
Short name T43
Test name
Test status
Simulation time 18259183 ps
CPU time 1.06 seconds
Started Nov 01 02:27:07 PM PDT 23
Finished Nov 01 02:27:24 PM PDT 23
Peak memory 205628 kb
Host smart-602ec30c-04cb-49c5-ac84-9b95dac49607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101083026525538421098636696574070582377633934258419328960176358612322372649606 -assert nopostproc +UVM_TESTNAME=edn_aler
t_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 30.edn_alert.101083026525538421098636696574070582377633934258419328960176358612322372649606
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.80349420902648669182192229295725402618117228570223435143209872921012939264083
Short name T593
Test name
Test status
Simulation time 28184990 ps
CPU time 0.86 seconds
Started Nov 01 02:27:15 PM PDT 23
Finished Nov 01 02:27:30 PM PDT 23
Peak memory 205492 kb
Host smart-599df51c-43a2-4494-b3cd-eda9ba9fc7ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80349420902648669182192229295725402618117228570223435143209872921012939264083 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.edn_alert_test.80349420902648669182192229295725402618117228570223435143209872921012939264083
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.14848002805173992852692221652119681096369049543975242998340704542287512743220
Short name T29
Test name
Test status
Simulation time 12219183 ps
CPU time 0.88 seconds
Started Nov 01 02:27:04 PM PDT 23
Finished Nov 01 02:27:19 PM PDT 23
Peak memory 214972 kb
Host smart-8b81182c-8a0a-4bb2-a3cd-67b6816c7838
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14848002805173992852692221652119681096369049543975242998340704542287512743220 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.edn_disable.14848002805173992852692221652119681096369049543975242998340704542287512743220
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.13625179969717260427593710017245028088104096482498120985911813681063798446500
Short name T845
Test name
Test status
Simulation time 17319183 ps
CPU time 0.92 seconds
Started Nov 01 02:27:03 PM PDT 23
Finished Nov 01 02:27:19 PM PDT 23
Peak memory 215060 kb
Host smart-59365a55-cfb4-48bc-bb0b-03f41c32f57f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13625179969717260427593710017245028088104096482498120985911813681063798446500 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable_auto_req_mode.1362517996971726042759371001724502808810409648249812098591
1813681063798446500
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.42587453407421413460219534847174581035202437232837037507913621055620257696476
Short name T416
Test name
Test status
Simulation time 24963823 ps
CPU time 1.09 seconds
Started Nov 01 02:27:09 PM PDT 23
Finished Nov 01 02:27:26 PM PDT 23
Peak memory 230448 kb
Host smart-802f8e05-5120-45d2-a9c9-5ceb2d179f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42587453407421413460219534847174581035202437232837037507913621055620257696476 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.edn_err.42587453407421413460219534847174581035202437232837037507913621055620257696476
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.80035683865885765847296889299371478845468745979698945374530219741551637965232
Short name T437
Test name
Test status
Simulation time 17999183 ps
CPU time 1.18 seconds
Started Nov 01 02:27:13 PM PDT 23
Finished Nov 01 02:27:29 PM PDT 23
Peak memory 205908 kb
Host smart-8a26b05b-d040-4359-9295-03a0c86ac957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80035683865885765847296889299371478845468745979698945374530219741551637965232 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.edn_genbits.80035683865885765847296889299371478845468745979698945374530219741551637965232
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.21738991655246865100127476334768899435067266323969861080102727903974777251546
Short name T290
Test name
Test status
Simulation time 18439183 ps
CPU time 1.11 seconds
Started Nov 01 02:27:14 PM PDT 23
Finished Nov 01 02:27:31 PM PDT 23
Peak memory 222264 kb
Host smart-ab1ed0ca-ba36-4b07-9169-a654695a89d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21738991655246865100127476334768899435067266323969861080102727903974777251546 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.edn_intr.21738991655246865100127476334768899435067266323969861080102727903974777251546
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.57308135626096693616035646515218439048363327424117732271314690607733051435456
Short name T937
Test name
Test status
Simulation time 13059183 ps
CPU time 0.89 seconds
Started Nov 01 02:27:09 PM PDT 23
Finished Nov 01 02:27:26 PM PDT 23
Peak memory 205424 kb
Host smart-5a6ccc16-b11e-4b06-b0a0-80a48079d939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57308135626096693616035646515218439048363327424117732271314690607733051435456 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 30.edn_smoke.57308135626096693616035646515218439048363327424117732271314690607733051435456
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.87367290788625171426132479139705365148859518382828387389523841837620761128241
Short name T406
Test name
Test status
Simulation time 154489183 ps
CPU time 3.94 seconds
Started Nov 01 02:27:28 PM PDT 23
Finished Nov 01 02:27:46 PM PDT 23
Peak memory 206276 kb
Host smart-0a8190bc-9b2a-4014-af3f-4bdbab9949e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87367290788625171426132479139705365148859518382828387389523841837620761128241 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.87367290788625171426132479139705365148859518382828387389523841837620761128241
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.31637128207690658419834863943088150504965393296236950577592625329277770711941
Short name T828
Test name
Test status
Simulation time 41708099183 ps
CPU time 1031.77 seconds
Started Nov 01 02:27:14 PM PDT 23
Finished Nov 01 02:44:41 PM PDT 23
Peak memory 215868 kb
Host smart-a9a11219-1098-4519-9d2e-fac0758c4f20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316371282076906584198348639
43088150504965393296236950577592625329277770711941 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.31637128207
690658419834863943088150504965393296236950577592625329277770711941
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.87743540335778846640722512417045104817615430253103544435603063893277228714221
Short name T765
Test name
Test status
Simulation time 18259183 ps
CPU time 0.99 seconds
Started Nov 01 02:26:53 PM PDT 23
Finished Nov 01 02:27:00 PM PDT 23
Peak memory 205592 kb
Host smart-d5073839-c7de-4273-b0a1-224935cebaa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87743540335778846640722512417045104817615430253103544435603063893277228714221 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 31.edn_alert.87743540335778846640722512417045104817615430253103544435603063893277228714221
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.7633902877992296562926656286461276295510684756282544925090316355734980530640
Short name T302
Test name
Test status
Simulation time 28184990 ps
CPU time 0.89 seconds
Started Nov 01 02:26:52 PM PDT 23
Finished Nov 01 02:26:58 PM PDT 23
Peak memory 205564 kb
Host smart-1c617679-2c00-40fc-bb5f-10947eadf4d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7633902877992296562926656286461276295510684756282544925090316355734980530640 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.edn_alert_test.7633902877992296562926656286461276295510684756282544925090316355734980530640
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.68257424563707097555434374139708778428949910816426868169962305634412827655937
Short name T60
Test name
Test status
Simulation time 12219183 ps
CPU time 0.86 seconds
Started Nov 01 02:26:40 PM PDT 23
Finished Nov 01 02:26:45 PM PDT 23
Peak memory 214888 kb
Host smart-5fd154ae-20c7-4c10-b4f9-7f25fff26897
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68257424563707097555434374139708778428949910816426868169962305634412827655937 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.edn_disable.68257424563707097555434374139708778428949910816426868169962305634412827655937
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.14258325429309772144492024275680536104410354342324710460522620294081167207149
Short name T919
Test name
Test status
Simulation time 17319183 ps
CPU time 0.94 seconds
Started Nov 01 02:26:38 PM PDT 23
Finished Nov 01 02:26:41 PM PDT 23
Peak memory 214944 kb
Host smart-acf7c2e7-f517-4646-b0c0-d41e2ba6dfae
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14258325429309772144492024275680536104410354342324710460522620294081167207149 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable_auto_req_mode.1425832542930977214449202427568053610441035434232471046052
2620294081167207149
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.93000218953468136850176454684452584812472443932745894415169738241200766328133
Short name T950
Test name
Test status
Simulation time 24963823 ps
CPU time 1.22 seconds
Started Nov 01 02:26:39 PM PDT 23
Finished Nov 01 02:26:44 PM PDT 23
Peak memory 230404 kb
Host smart-3063d3f3-704e-4390-8537-dc54a70edc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93000218953468136850176454684452584812472443932745894415169738241200766328133 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.edn_err.93000218953468136850176454684452584812472443932745894415169738241200766328133
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.81247099059453693999760199424841857729310134583368947051593917089514795093144
Short name T739
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:27:15 PM PDT 23
Finished Nov 01 02:27:31 PM PDT 23
Peak memory 205800 kb
Host smart-21fbb8ff-9cf2-464a-a64f-0e002206df89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81247099059453693999760199424841857729310134583368947051593917089514795093144 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.edn_genbits.81247099059453693999760199424841857729310134583368947051593917089514795093144
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.59506573898075817204689168898723780345902429003567350324095385407618792988553
Short name T292
Test name
Test status
Simulation time 18439183 ps
CPU time 1.15 seconds
Started Nov 01 02:27:22 PM PDT 23
Finished Nov 01 02:27:42 PM PDT 23
Peak memory 222212 kb
Host smart-5f904f24-7567-44e5-8db5-ace07ff93729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59506573898075817204689168898723780345902429003567350324095385407618792988553 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.edn_intr.59506573898075817204689168898723780345902429003567350324095385407618792988553
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.29664284252019697136193743775279264764646575146749651218132304445051125384328
Short name T907
Test name
Test status
Simulation time 13059183 ps
CPU time 0.9 seconds
Started Nov 01 02:27:09 PM PDT 23
Finished Nov 01 02:27:26 PM PDT 23
Peak memory 205528 kb
Host smart-442e3aaa-940e-4745-be53-825c39e302d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29664284252019697136193743775279264764646575146749651218132304445051125384328 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 31.edn_smoke.29664284252019697136193743775279264764646575146749651218132304445051125384328
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.74258414927773053490919825930514816322229370840724174270869247287730197071846
Short name T417
Test name
Test status
Simulation time 154489183 ps
CPU time 4.07 seconds
Started Nov 01 02:27:15 PM PDT 23
Finished Nov 01 02:27:34 PM PDT 23
Peak memory 206328 kb
Host smart-b97ac071-a66b-49dd-8a7d-e5eea82a2369
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74258414927773053490919825930514816322229370840724174270869247287730197071846 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.74258414927773053490919825930514816322229370840724174270869247287730197071846
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.32738229216457104515261340373078490703451722669719352651555382158899791964711
Short name T242
Test name
Test status
Simulation time 41708099183 ps
CPU time 1073.75 seconds
Started Nov 01 02:27:25 PM PDT 23
Finished Nov 01 02:45:33 PM PDT 23
Peak memory 215816 kb
Host smart-77d4ac6a-d410-4c82-a034-495508fe9940
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327382292164571045152613403
73078490703451722669719352651555382158899791964711 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.32738229216
457104515261340373078490703451722669719352651555382158899791964711
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.8948043484077889150368813607549667990987420117413096650995989343082444411978
Short name T869
Test name
Test status
Simulation time 18259183 ps
CPU time 1.04 seconds
Started Nov 01 02:26:52 PM PDT 23
Finished Nov 01 02:26:58 PM PDT 23
Peak memory 205544 kb
Host smart-cfa68922-c28f-4576-95f6-ac18b01a3a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8948043484077889150368813607549667990987420117413096650995989343082444411978 -assert nopostproc +UVM_TESTNAME=edn_alert_
test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.edn_alert.8948043484077889150368813607549667990987420117413096650995989343082444411978
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.12610819309415062077310332319763279713414150920651330947644298569653106691998
Short name T939
Test name
Test status
Simulation time 28184990 ps
CPU time 0.9 seconds
Started Nov 01 02:26:49 PM PDT 23
Finished Nov 01 02:26:52 PM PDT 23
Peak memory 205588 kb
Host smart-d7c90269-d2c6-4de4-9ac0-56a8c6d68709
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12610819309415062077310332319763279713414150920651330947644298569653106691998 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.edn_alert_test.12610819309415062077310332319763279713414150920651330947644298569653106691998
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.12914803041702383608878904457770837711769606450610597344199830052603782159828
Short name T940
Test name
Test status
Simulation time 12219183 ps
CPU time 0.87 seconds
Started Nov 01 02:26:42 PM PDT 23
Finished Nov 01 02:26:47 PM PDT 23
Peak memory 214860 kb
Host smart-685f8ee6-8648-465a-b6cb-79e5cc91a2a7
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12914803041702383608878904457770837711769606450610597344199830052603782159828 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.edn_disable.12914803041702383608878904457770837711769606450610597344199830052603782159828
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.28628595403010415805058297451204231070632810082973545133459002400229257109509
Short name T424
Test name
Test status
Simulation time 17319183 ps
CPU time 0.95 seconds
Started Nov 01 02:26:50 PM PDT 23
Finished Nov 01 02:26:53 PM PDT 23
Peak memory 214928 kb
Host smart-33308345-e432-4091-9532-09ac561196f3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28628595403010415805058297451204231070632810082973545133459002400229257109509 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable_auto_req_mode.2862859540301041580505829745120423107063281008297354513345
9002400229257109509
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.113850612200385744632906605431889743483622563648679002845526466960578691181961
Short name T854
Test name
Test status
Simulation time 24963823 ps
CPU time 1.11 seconds
Started Nov 01 02:26:52 PM PDT 23
Finished Nov 01 02:26:58 PM PDT 23
Peak memory 230460 kb
Host smart-15157895-51ab-403f-878c-88a0a8be13e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113850612200385744632906605431889743483622563648679002845526466960578691181961 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.edn_err.113850612200385744632906605431889743483622563648679002845526466960578691181961
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.94873125628588403072550874049218771548196238578780407650238497057513599857355
Short name T954
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:26:44 PM PDT 23
Finished Nov 01 02:26:50 PM PDT 23
Peak memory 205880 kb
Host smart-50457a78-c67a-40d7-a05e-5b7c61010b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94873125628588403072550874049218771548196238578780407650238497057513599857355 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.edn_genbits.94873125628588403072550874049218771548196238578780407650238497057513599857355
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.47492129762523026158143172795023622954546156565013604814448480923173450264464
Short name T952
Test name
Test status
Simulation time 18439183 ps
CPU time 1.16 seconds
Started Nov 01 02:26:40 PM PDT 23
Finished Nov 01 02:26:46 PM PDT 23
Peak memory 222220 kb
Host smart-13e33c08-a028-4e5c-b2d6-51decf8267d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47492129762523026158143172795023622954546156565013604814448480923173450264464 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.edn_intr.47492129762523026158143172795023622954546156565013604814448480923173450264464
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.58446472590697262589972857453000949757721208011192784737116301966178096067667
Short name T965
Test name
Test status
Simulation time 13059183 ps
CPU time 0.87 seconds
Started Nov 01 02:26:51 PM PDT 23
Finished Nov 01 02:26:55 PM PDT 23
Peak memory 205396 kb
Host smart-c6022b5c-c917-48bc-a369-8a060bfaf655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58446472590697262589972857453000949757721208011192784737116301966178096067667 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 32.edn_smoke.58446472590697262589972857453000949757721208011192784737116301966178096067667
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.114484994847182592354763142541079209653145713753647595390007752822071634829032
Short name T419
Test name
Test status
Simulation time 154489183 ps
CPU time 3.86 seconds
Started Nov 01 02:26:48 PM PDT 23
Finished Nov 01 02:26:54 PM PDT 23
Peak memory 206232 kb
Host smart-0f637608-9a5c-461d-b149-e3cfb2e1c9d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114484994847182592354763142541079209653145713753647595390007752822071634829032 -assert nopo
stproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.114484994847182592354763142541079209653145713753647595390007752822071634829032
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.20390500722742746905387781235601104198152141989227511488908702963094169980878
Short name T698
Test name
Test status
Simulation time 41708099183 ps
CPU time 1090.16 seconds
Started Nov 01 02:26:39 PM PDT 23
Finished Nov 01 02:44:53 PM PDT 23
Peak memory 215888 kb
Host smart-8f626d77-a3ee-493b-ab25-d110969fa919
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203905007227427469053877812
35601104198152141989227511488908702963094169980878 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.20390500722
742746905387781235601104198152141989227511488908702963094169980878
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.35690109306127883218791134822324603443090593981487373577809344109189064142812
Short name T621
Test name
Test status
Simulation time 18259183 ps
CPU time 0.98 seconds
Started Nov 01 02:26:58 PM PDT 23
Finished Nov 01 02:27:09 PM PDT 23
Peak memory 205620 kb
Host smart-598c55f4-106f-4376-af9b-1baaa3d75a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35690109306127883218791134822324603443090593981487373577809344109189064142812 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 33.edn_alert.35690109306127883218791134822324603443090593981487373577809344109189064142812
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.115111666351769577142399259646758761551046026159169063874299123626186278931625
Short name T559
Test name
Test status
Simulation time 28184990 ps
CPU time 0.91 seconds
Started Nov 01 02:27:10 PM PDT 23
Finished Nov 01 02:27:26 PM PDT 23
Peak memory 205448 kb
Host smart-b45c6e36-5464-4903-bf0e-2a654ce5e787
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115111666351769577142399259646758761551046026159169063874299123626186278931625 -assert nopostp
roc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 33.edn_alert_test.115111666351769577142399259646758761551046026159169063874299123626186278931625
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.95511700684337070837819085821989598510769919493768544555592872093167420247552
Short name T440
Test name
Test status
Simulation time 12219183 ps
CPU time 0.86 seconds
Started Nov 01 02:26:59 PM PDT 23
Finished Nov 01 02:27:12 PM PDT 23
Peak memory 214880 kb
Host smart-a221251b-4a8d-460c-a826-dbbf9e69f9e4
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95511700684337070837819085821989598510769919493768544555592872093167420247552 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.edn_disable.95511700684337070837819085821989598510769919493768544555592872093167420247552
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.27427515579304163344143525374530270711078121065825605127688799039762615381996
Short name T572
Test name
Test status
Simulation time 17319183 ps
CPU time 0.92 seconds
Started Nov 01 02:27:07 PM PDT 23
Finished Nov 01 02:27:23 PM PDT 23
Peak memory 214804 kb
Host smart-0db1065b-79b0-4b5f-8d2f-15147ffa7d7b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27427515579304163344143525374530270711078121065825605127688799039762615381996 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable_auto_req_mode.2742751557930416334414352537453027071107812106582560512768
8799039762615381996
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.54730940390994787771234167296132322163302812571971139481504168129548787742607
Short name T89
Test name
Test status
Simulation time 24963823 ps
CPU time 1.15 seconds
Started Nov 01 02:26:56 PM PDT 23
Finished Nov 01 02:27:05 PM PDT 23
Peak memory 230616 kb
Host smart-ec7e7b82-8cc0-474b-9296-5c353f5afe55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54730940390994787771234167296132322163302812571971139481504168129548787742607 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.edn_err.54730940390994787771234167296132322163302812571971139481504168129548787742607
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.66387692944368583658862484436907937042689960461422111003245929168993715198102
Short name T57
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 01 02:26:56 PM PDT 23
Finished Nov 01 02:27:05 PM PDT 23
Peak memory 205980 kb
Host smart-ebaeaa42-9ba1-4ace-bc51-0a9526844252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66387692944368583658862484436907937042689960461422111003245929168993715198102 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.edn_genbits.66387692944368583658862484436907937042689960461422111003245929168993715198102
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.3049524427562866058198413692249282097740050174314060005611911321581326261512
Short name T659
Test name
Test status
Simulation time 18439183 ps
CPU time 1.13 seconds
Started Nov 01 02:27:01 PM PDT 23
Finished Nov 01 02:27:16 PM PDT 23
Peak memory 222316 kb
Host smart-dcd11e08-f723-40f6-9fa8-5c2b1f234b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049524427562866058198413692249282097740050174314060005611911321581326261512 -assert nopostproc +UVM_TESTNAME=edn_intr_t
est +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.edn_intr.3049524427562866058198413692249282097740050174314060005611911321581326261512
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.80254512184807911535281698198589844232980374621731695556858924725580490459553
Short name T38
Test name
Test status
Simulation time 13059183 ps
CPU time 0.92 seconds
Started Nov 01 02:26:53 PM PDT 23
Finished Nov 01 02:27:00 PM PDT 23
Peak memory 205428 kb
Host smart-9470401e-fdb1-491a-95a7-0cfb6239d9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80254512184807911535281698198589844232980374621731695556858924725580490459553 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 33.edn_smoke.80254512184807911535281698198589844232980374621731695556858924725580490459553
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.29597569346034238675488890877788228562095024042682749229771854829122437341950
Short name T868
Test name
Test status
Simulation time 154489183 ps
CPU time 3.99 seconds
Started Nov 01 02:26:51 PM PDT 23
Finished Nov 01 02:26:58 PM PDT 23
Peak memory 206456 kb
Host smart-4cc3ebea-9bbf-4ae3-b630-acbd4c7f12ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29597569346034238675488890877788228562095024042682749229771854829122437341950 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.29597569346034238675488890877788228562095024042682749229771854829122437341950
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.112629808671266335579889810276016872117057874759302592076907962566423918321513
Short name T591
Test name
Test status
Simulation time 41708099183 ps
CPU time 1064.53 seconds
Started Nov 01 02:26:56 PM PDT 23
Finished Nov 01 02:44:49 PM PDT 23
Peak memory 215848 kb
Host smart-2e1d524c-4158-4c15-8af9-a087f2028dbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112629808671266335579889810
276016872117057874759302592076907962566423918321513 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.1126298086
71266335579889810276016872117057874759302592076907962566423918321513
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.82376762615626473459439525087080897232599604852881357590701331348860872785748
Short name T636
Test name
Test status
Simulation time 18259183 ps
CPU time 0.98 seconds
Started Nov 01 02:27:34 PM PDT 23
Finished Nov 01 02:27:47 PM PDT 23
Peak memory 205636 kb
Host smart-b9421431-129c-4a22-8901-a480af066cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82376762615626473459439525087080897232599604852881357590701331348860872785748 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 34.edn_alert.82376762615626473459439525087080897232599604852881357590701331348860872785748
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.113728144961095136092148411999634137537993220923902512570794450380580293877247
Short name T300
Test name
Test status
Simulation time 28184990 ps
CPU time 0.87 seconds
Started Nov 01 02:27:07 PM PDT 23
Finished Nov 01 02:27:23 PM PDT 23
Peak memory 205528 kb
Host smart-389d5452-513c-41bd-a086-1741a2167716
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113728144961095136092148411999634137537993220923902512570794450380580293877247 -assert nopostp
roc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 34.edn_alert_test.113728144961095136092148411999634137537993220923902512570794450380580293877247
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.44966029279265283452763785360793081306230421935263220750998792818663587867909
Short name T420
Test name
Test status
Simulation time 12219183 ps
CPU time 0.88 seconds
Started Nov 01 02:27:27 PM PDT 23
Finished Nov 01 02:27:42 PM PDT 23
Peak memory 214772 kb
Host smart-d86882d1-7f28-4352-9906-2c63fb37c846
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44966029279265283452763785360793081306230421935263220750998792818663587867909 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.edn_disable.44966029279265283452763785360793081306230421935263220750998792818663587867909
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_err.67804704344077076290982731463161798626122733854305828138937643667588348851735
Short name T426
Test name
Test status
Simulation time 24963823 ps
CPU time 1.12 seconds
Started Nov 01 02:27:14 PM PDT 23
Finished Nov 01 02:27:30 PM PDT 23
Peak memory 230392 kb
Host smart-78d6bfd5-f883-4b6c-9853-7e92cb6fd83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67804704344077076290982731463161798626122733854305828138937643667588348851735 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.edn_err.67804704344077076290982731463161798626122733854305828138937643667588348851735
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.75597086360752316232479345251436828670012982668739547604178735841905516181445
Short name T337
Test name
Test status
Simulation time 17999183 ps
CPU time 1.06 seconds
Started Nov 01 02:27:08 PM PDT 23
Finished Nov 01 02:27:24 PM PDT 23
Peak memory 205764 kb
Host smart-9aa392f9-550d-4795-aecc-8584111acdfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75597086360752316232479345251436828670012982668739547604178735841905516181445 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.edn_genbits.75597086360752316232479345251436828670012982668739547604178735841905516181445
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.59864123858828059008250924173405331718586304755572568685392908456725869973664
Short name T779
Test name
Test status
Simulation time 18439183 ps
CPU time 1.16 seconds
Started Nov 01 02:27:13 PM PDT 23
Finished Nov 01 02:27:30 PM PDT 23
Peak memory 222324 kb
Host smart-ae480e8c-9c08-4296-bf35-53bec07bd8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59864123858828059008250924173405331718586304755572568685392908456725869973664 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.edn_intr.59864123858828059008250924173405331718586304755572568685392908456725869973664
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.38479617859489543021626970057920435087964765336101338402677855137625612794518
Short name T575
Test name
Test status
Simulation time 13059183 ps
CPU time 0.87 seconds
Started Nov 01 02:27:24 PM PDT 23
Finished Nov 01 02:27:38 PM PDT 23
Peak memory 205404 kb
Host smart-ff4da386-2223-4ff1-98ce-35920f699c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38479617859489543021626970057920435087964765336101338402677855137625612794518 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 34.edn_smoke.38479617859489543021626970057920435087964765336101338402677855137625612794518
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.29094973903094824674238234256644454668085912092755289079906922087733222242093
Short name T526
Test name
Test status
Simulation time 154489183 ps
CPU time 4.04 seconds
Started Nov 01 02:27:17 PM PDT 23
Finished Nov 01 02:27:35 PM PDT 23
Peak memory 206420 kb
Host smart-e2053f4c-0fce-4a34-ad81-6847039cba6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29094973903094824674238234256644454668085912092755289079906922087733222242093 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.29094973903094824674238234256644454668085912092755289079906922087733222242093
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.37809762153100322811111274233908279060236034688163844381373407277834686384402
Short name T402
Test name
Test status
Simulation time 41708099183 ps
CPU time 1076.26 seconds
Started Nov 01 02:27:00 PM PDT 23
Finished Nov 01 02:45:08 PM PDT 23
Peak memory 215912 kb
Host smart-c3b1e273-4017-4d1f-b6a3-e3124bac56d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378097621531003228111112742
33908279060236034688163844381373407277834686384402 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.37809762153
100322811111274233908279060236034688163844381373407277834686384402
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.7603829110585358291533031955957130795363225747753066142421096622814267470209
Short name T726
Test name
Test status
Simulation time 18259183 ps
CPU time 0.99 seconds
Started Nov 01 02:27:11 PM PDT 23
Finished Nov 01 02:27:27 PM PDT 23
Peak memory 205544 kb
Host smart-4276240f-b813-4de0-babc-c1e14ce0b895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7603829110585358291533031955957130795363225747753066142421096622814267470209 -assert nopostproc +UVM_TESTNAME=edn_alert_
test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.edn_alert.7603829110585358291533031955957130795363225747753066142421096622814267470209
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.99846097327417418523362316954600951509123868507018663586466241230033534734161
Short name T910
Test name
Test status
Simulation time 28184990 ps
CPU time 0.87 seconds
Started Nov 01 02:27:18 PM PDT 23
Finished Nov 01 02:27:33 PM PDT 23
Peak memory 205368 kb
Host smart-96def304-292e-448c-bb36-d27032d7f90e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99846097327417418523362316954600951509123868507018663586466241230033534734161 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.edn_alert_test.99846097327417418523362316954600951509123868507018663586466241230033534734161
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.61250552214996298242924856044757519911140169074310699155119225882860324920916
Short name T711
Test name
Test status
Simulation time 12219183 ps
CPU time 0.88 seconds
Started Nov 01 02:27:21 PM PDT 23
Finished Nov 01 02:27:36 PM PDT 23
Peak memory 214836 kb
Host smart-374b71ee-b9e7-404f-9826-e37ac6ca9367
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61250552214996298242924856044757519911140169074310699155119225882860324920916 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.edn_disable.61250552214996298242924856044757519911140169074310699155119225882860324920916
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.10761305052363969036110611837304725289263842218074863217753707319444349577900
Short name T380
Test name
Test status
Simulation time 17319183 ps
CPU time 0.93 seconds
Started Nov 01 02:27:21 PM PDT 23
Finished Nov 01 02:27:36 PM PDT 23
Peak memory 214900 kb
Host smart-25926245-0def-4efb-9ba7-07a5b52b1a64
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10761305052363969036110611837304725289263842218074863217753707319444349577900 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable_auto_req_mode.1076130505236396903611061183730472528926384221807486321775
3707319444349577900
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.10765422228281042660930158644119569051382253937911982925776816104218605260999
Short name T700
Test name
Test status
Simulation time 24963823 ps
CPU time 1.14 seconds
Started Nov 01 02:27:14 PM PDT 23
Finished Nov 01 02:27:30 PM PDT 23
Peak memory 230424 kb
Host smart-f4d14161-9ebd-4bc2-8e60-344a3ae20624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10765422228281042660930158644119569051382253937911982925776816104218605260999 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.edn_err.10765422228281042660930158644119569051382253937911982925776816104218605260999
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.63306376937154495007413483584244758267620151209281084929851237780660468055819
Short name T514
Test name
Test status
Simulation time 17999183 ps
CPU time 1.06 seconds
Started Nov 01 02:27:09 PM PDT 23
Finished Nov 01 02:27:26 PM PDT 23
Peak memory 205852 kb
Host smart-c5588949-542d-408d-b9a2-1d1b564ed4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63306376937154495007413483584244758267620151209281084929851237780660468055819 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.edn_genbits.63306376937154495007413483584244758267620151209281084929851237780660468055819
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.87837794903647165485794183273556688996138748154224697496060765022520879721265
Short name T974
Test name
Test status
Simulation time 18439183 ps
CPU time 1.15 seconds
Started Nov 01 02:27:12 PM PDT 23
Finished Nov 01 02:27:29 PM PDT 23
Peak memory 222376 kb
Host smart-9baa5ded-dbad-4e50-91ff-43875b43b631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87837794903647165485794183273556688996138748154224697496060765022520879721265 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.edn_intr.87837794903647165485794183273556688996138748154224697496060765022520879721265
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.95794104131550713711524862307025952464044088425098916341641648923341949620944
Short name T273
Test name
Test status
Simulation time 13059183 ps
CPU time 0.86 seconds
Started Nov 01 02:27:39 PM PDT 23
Finished Nov 01 02:27:50 PM PDT 23
Peak memory 205376 kb
Host smart-b30b45ce-4e04-40db-9808-8e2e6ea80ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95794104131550713711524862307025952464044088425098916341641648923341949620944 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 35.edn_smoke.95794104131550713711524862307025952464044088425098916341641648923341949620944
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.92733485936144598691758182518739790654814250244379690180466010485301449481652
Short name T383
Test name
Test status
Simulation time 154489183 ps
CPU time 3.93 seconds
Started Nov 01 02:27:34 PM PDT 23
Finished Nov 01 02:27:50 PM PDT 23
Peak memory 206420 kb
Host smart-ef6ee6f2-8517-444f-b932-71946f0948c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92733485936144598691758182518739790654814250244379690180466010485301449481652 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.92733485936144598691758182518739790654814250244379690180466010485301449481652
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.69189419776074696640802656484877468294038693937979086014407014028294256661217
Short name T450
Test name
Test status
Simulation time 41708099183 ps
CPU time 1045.3 seconds
Started Nov 01 02:27:11 PM PDT 23
Finished Nov 01 02:44:51 PM PDT 23
Peak memory 215872 kb
Host smart-e3c2c904-0640-43e0-8a80-7e7e7605b747
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691894197760746966408026564
84877468294038693937979086014407014028294256661217 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.69189419776
074696640802656484877468294038693937979086014407014028294256661217
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.83246060344809741220834573644202307758367041407068143021321453495227749140025
Short name T788
Test name
Test status
Simulation time 18259183 ps
CPU time 0.99 seconds
Started Nov 01 02:27:24 PM PDT 23
Finished Nov 01 02:27:39 PM PDT 23
Peak memory 205628 kb
Host smart-9fa33b6d-1005-489b-ba83-bb2e69967edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83246060344809741220834573644202307758367041407068143021321453495227749140025 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 36.edn_alert.83246060344809741220834573644202307758367041407068143021321453495227749140025
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.32500623787308169473205242544862863841403508639874389909922383637172684398421
Short name T949
Test name
Test status
Simulation time 28184990 ps
CPU time 0.88 seconds
Started Nov 01 02:26:38 PM PDT 23
Finished Nov 01 02:26:40 PM PDT 23
Peak memory 205444 kb
Host smart-4cbdc001-04cb-45e4-bbda-90455038d9f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32500623787308169473205242544862863841403508639874389909922383637172684398421 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.edn_alert_test.32500623787308169473205242544862863841403508639874389909922383637172684398421
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.94080226721194155055268463539871790436153773836611231117612923994373844766716
Short name T574
Test name
Test status
Simulation time 12219183 ps
CPU time 0.87 seconds
Started Nov 01 02:26:37 PM PDT 23
Finished Nov 01 02:26:40 PM PDT 23
Peak memory 214832 kb
Host smart-765a6ecb-4e51-44b1-8c87-753658e073a3
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94080226721194155055268463539871790436153773836611231117612923994373844766716 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.edn_disable.94080226721194155055268463539871790436153773836611231117612923994373844766716
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.57136139121033572508565093851927531010338254545629950262075087803870611023814
Short name T637
Test name
Test status
Simulation time 17319183 ps
CPU time 0.89 seconds
Started Nov 01 02:26:50 PM PDT 23
Finished Nov 01 02:26:53 PM PDT 23
Peak memory 214844 kb
Host smart-f116f50e-b559-4b30-b866-2a3418b51835
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57136139121033572508565093851927531010338254545629950262075087803870611023814 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable_auto_req_mode.5713613912103357250856509385192753101033825454562995026207
5087803870611023814
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.71577015808788375408050227927202814782378989048681985657412348354300229000638
Short name T656
Test name
Test status
Simulation time 24963823 ps
CPU time 1.15 seconds
Started Nov 01 02:27:12 PM PDT 23
Finished Nov 01 02:27:29 PM PDT 23
Peak memory 230528 kb
Host smart-15d79b14-eb09-4b14-a5d6-d18458390442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71577015808788375408050227927202814782378989048681985657412348354300229000638 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.edn_err.71577015808788375408050227927202814782378989048681985657412348354300229000638
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.107081218118125120209070104070953178504699565720717423656453836347241382540904
Short name T877
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 01 02:27:01 PM PDT 23
Finished Nov 01 02:27:16 PM PDT 23
Peak memory 206116 kb
Host smart-f607cf8b-3057-4b55-b320-23c41544c1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107081218118125120209070104070953178504699565720717423656453836347241382540904 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 36.edn_genbits.107081218118125120209070104070953178504699565720717423656453836347241382540904
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.72628258485947381492943198967454045873732733289561485992607723884106803476516
Short name T678
Test name
Test status
Simulation time 18439183 ps
CPU time 1.17 seconds
Started Nov 01 02:26:53 PM PDT 23
Finished Nov 01 02:27:00 PM PDT 23
Peak memory 222276 kb
Host smart-e8b10e08-b432-4de0-b6de-eb69a8f9d16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72628258485947381492943198967454045873732733289561485992607723884106803476516 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.edn_intr.72628258485947381492943198967454045873732733289561485992607723884106803476516
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.1629324544245114203669614222353518413898829687006887741169867482081103023352
Short name T357
Test name
Test status
Simulation time 13059183 ps
CPU time 0.95 seconds
Started Nov 01 02:26:54 PM PDT 23
Finished Nov 01 02:27:01 PM PDT 23
Peak memory 205204 kb
Host smart-2505fdcc-f612-40cd-a6b6-c1bccaa80988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629324544245114203669614222353518413898829687006887741169867482081103023352 -assert nopostproc +UVM_TESTNAME=edn_smoke_
test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.edn_smoke.1629324544245114203669614222353518413898829687006887741169867482081103023352
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.47360900729052643858765797714329260004254880933186685170241923065160898730936
Short name T85
Test name
Test status
Simulation time 154489183 ps
CPU time 3.83 seconds
Started Nov 01 02:27:20 PM PDT 23
Finished Nov 01 02:27:38 PM PDT 23
Peak memory 206380 kb
Host smart-c719ce28-fb9d-4590-b0cc-107d83f7a0b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47360900729052643858765797714329260004254880933186685170241923065160898730936 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.47360900729052643858765797714329260004254880933186685170241923065160898730936
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.66384198299487429038847227533140400078555518024161366908321570596136777900583
Short name T536
Test name
Test status
Simulation time 41708099183 ps
CPU time 1082.56 seconds
Started Nov 01 02:27:00 PM PDT 23
Finished Nov 01 02:45:15 PM PDT 23
Peak memory 216132 kb
Host smart-e10aaf0d-fb0c-4a25-9d3f-0b9beffc9668
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663841982994874290388472275
33140400078555518024161366908321570596136777900583 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.66384198299
487429038847227533140400078555518024161366908321570596136777900583
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.112070133966146246103509255183110588976086381161846323543690651575468076796832
Short name T613
Test name
Test status
Simulation time 18259183 ps
CPU time 0.99 seconds
Started Nov 01 02:26:38 PM PDT 23
Finished Nov 01 02:26:40 PM PDT 23
Peak memory 205624 kb
Host smart-7f166164-dc55-491a-8d97-994211667c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112070133966146246103509255183110588976086381161846323543690651575468076796832 -assert nopostproc +UVM_TESTNAME=edn_aler
t_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 37.edn_alert.112070133966146246103509255183110588976086381161846323543690651575468076796832
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.57673936687621870079295095011006346104632656010799338914311327672200302317586
Short name T448
Test name
Test status
Simulation time 28184990 ps
CPU time 0.87 seconds
Started Nov 01 02:26:59 PM PDT 23
Finished Nov 01 02:27:12 PM PDT 23
Peak memory 205548 kb
Host smart-d41e14af-a35b-41f1-af18-9761462f7c97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57673936687621870079295095011006346104632656010799338914311327672200302317586 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.edn_alert_test.57673936687621870079295095011006346104632656010799338914311327672200302317586
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.66645411952566843428668719076285465130418253668175416662708628066627986323618
Short name T890
Test name
Test status
Simulation time 12219183 ps
CPU time 0.89 seconds
Started Nov 01 02:26:54 PM PDT 23
Finished Nov 01 02:27:01 PM PDT 23
Peak memory 214916 kb
Host smart-601ec8f4-c28f-45dd-b496-5ea4b61778c8
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66645411952566843428668719076285465130418253668175416662708628066627986323618 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.edn_disable.66645411952566843428668719076285465130418253668175416662708628066627986323618
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.112523172686753735267499322544947882904648230961152808843901587945837045872478
Short name T677
Test name
Test status
Simulation time 17319183 ps
CPU time 0.94 seconds
Started Nov 01 02:26:38 PM PDT 23
Finished Nov 01 02:26:40 PM PDT 23
Peak memory 214924 kb
Host smart-dbba6504-b8d6-426a-9c78-3974b447885b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112523172686753735267499322544947882904648230961152808843901587945837045872478 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable_auto_req_mode.112523172686753735267499322544947882904648230961152808843
901587945837045872478
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.26680790331967112805599996285922936515677218815582393097536747882993757968601
Short name T447
Test name
Test status
Simulation time 24963823 ps
CPU time 1.15 seconds
Started Nov 01 02:26:41 PM PDT 23
Finished Nov 01 02:26:47 PM PDT 23
Peak memory 230472 kb
Host smart-fc72b5f1-4007-4e31-b20c-99b30b7223cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26680790331967112805599996285922936515677218815582393097536747882993757968601 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.edn_err.26680790331967112805599996285922936515677218815582393097536747882993757968601
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.69058956442122178329756751551674092084071649932320042560544592384098260227022
Short name T287
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:26:54 PM PDT 23
Finished Nov 01 02:27:01 PM PDT 23
Peak memory 205788 kb
Host smart-ecda5201-653d-4b5e-bca6-5267b2500619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69058956442122178329756751551674092084071649932320042560544592384098260227022 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.edn_genbits.69058956442122178329756751551674092084071649932320042560544592384098260227022
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.61176554015591301163112808044035479062794749510243406566072606977777150669856
Short name T741
Test name
Test status
Simulation time 18439183 ps
CPU time 1.2 seconds
Started Nov 01 02:26:44 PM PDT 23
Finished Nov 01 02:26:50 PM PDT 23
Peak memory 222296 kb
Host smart-b68d7f37-2ff9-4e5d-b066-363c80cd34cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61176554015591301163112808044035479062794749510243406566072606977777150669856 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.edn_intr.61176554015591301163112808044035479062794749510243406566072606977777150669856
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.115162370288247333661316762540299897675510884860413982932728159081632157576223
Short name T627
Test name
Test status
Simulation time 13059183 ps
CPU time 0.92 seconds
Started Nov 01 02:26:49 PM PDT 23
Finished Nov 01 02:26:53 PM PDT 23
Peak memory 205404 kb
Host smart-c6c96ef3-5f00-4753-81c3-b9146a8090ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115162370288247333661316762540299897675510884860413982932728159081632157576223 -assert nopostproc +UVM_TESTNAME=edn_smok
e_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 37.edn_smoke.115162370288247333661316762540299897675510884860413982932728159081632157576223
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.31604483845843171482063761193652322292241251998414286454039425886404167528301
Short name T451
Test name
Test status
Simulation time 154489183 ps
CPU time 4.04 seconds
Started Nov 01 02:26:37 PM PDT 23
Finished Nov 01 02:26:42 PM PDT 23
Peak memory 206400 kb
Host smart-a248217f-6502-49ea-b444-b3d25c59e5b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31604483845843171482063761193652322292241251998414286454039425886404167528301 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.31604483845843171482063761193652322292241251998414286454039425886404167528301
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.96989403867042161408707306955707469042356069534405632399694631888847455660539
Short name T596
Test name
Test status
Simulation time 41708099183 ps
CPU time 1073.08 seconds
Started Nov 01 02:26:48 PM PDT 23
Finished Nov 01 02:44:44 PM PDT 23
Peak memory 215860 kb
Host smart-0cb49ad6-3cfe-44c8-9a02-ac6542bdc4d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969894038670421614087073069
55707469042356069534405632399694631888847455660539 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.96989403867
042161408707306955707469042356069534405632399694631888847455660539
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.52579613332578790308579178100488794768001858701760431657407356923691733288063
Short name T963
Test name
Test status
Simulation time 18259183 ps
CPU time 1.04 seconds
Started Nov 01 02:27:09 PM PDT 23
Finished Nov 01 02:27:26 PM PDT 23
Peak memory 205508 kb
Host smart-4977528a-abe9-4ac6-9d77-68cac91ebb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52579613332578790308579178100488794768001858701760431657407356923691733288063 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 38.edn_alert.52579613332578790308579178100488794768001858701760431657407356923691733288063
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.71080356017304815316462130258798839754014432169463972173398873982390515929995
Short name T657
Test name
Test status
Simulation time 28184990 ps
CPU time 0.86 seconds
Started Nov 01 02:26:59 PM PDT 23
Finished Nov 01 02:27:11 PM PDT 23
Peak memory 205448 kb
Host smart-d922fa5e-ef60-4bf9-aa88-b1b74c84f3b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71080356017304815316462130258798839754014432169463972173398873982390515929995 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.edn_alert_test.71080356017304815316462130258798839754014432169463972173398873982390515929995
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.14699355679360318471346447360243423413332058442382137809445510514501488952671
Short name T65
Test name
Test status
Simulation time 12219183 ps
CPU time 0.9 seconds
Started Nov 01 02:27:01 PM PDT 23
Finished Nov 01 02:27:16 PM PDT 23
Peak memory 214896 kb
Host smart-be715797-13ad-401d-bccd-6a0c4d2501a4
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14699355679360318471346447360243423413332058442382137809445510514501488952671 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.edn_disable.14699355679360318471346447360243423413332058442382137809445510514501488952671
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.108724320950430673309005415482156275025428748105996142443639279205970246062069
Short name T763
Test name
Test status
Simulation time 17319183 ps
CPU time 0.94 seconds
Started Nov 01 02:26:59 PM PDT 23
Finished Nov 01 02:27:12 PM PDT 23
Peak memory 214912 kb
Host smart-25fca208-e927-48f9-9f6c-7a27f02841d0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108724320950430673309005415482156275025428748105996142443639279205970246062069 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable_auto_req_mode.108724320950430673309005415482156275025428748105996142443
639279205970246062069
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.82236369987720903377973488029899035790241042961849120742875513551464147925045
Short name T370
Test name
Test status
Simulation time 24963823 ps
CPU time 1.17 seconds
Started Nov 01 02:27:08 PM PDT 23
Finished Nov 01 02:27:25 PM PDT 23
Peak memory 230376 kb
Host smart-8f58e52b-2417-4132-875b-049c37e07f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82236369987720903377973488029899035790241042961849120742875513551464147925045 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.edn_err.82236369987720903377973488029899035790241042961849120742875513551464147925045
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.61689611457722841529454389753506843701883766637156644636501280117532935817769
Short name T256
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:26:53 PM PDT 23
Finished Nov 01 02:27:01 PM PDT 23
Peak memory 205776 kb
Host smart-dcc40bba-70c9-4674-b80f-372eb8f6f94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61689611457722841529454389753506843701883766637156644636501280117532935817769 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.edn_genbits.61689611457722841529454389753506843701883766637156644636501280117532935817769
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.15537953816886102850849967207670970169603320548689033713354208845958615523292
Short name T835
Test name
Test status
Simulation time 18439183 ps
CPU time 1.14 seconds
Started Nov 01 02:26:51 PM PDT 23
Finished Nov 01 02:26:55 PM PDT 23
Peak memory 222200 kb
Host smart-229d8cd7-3292-411b-a4dd-34c518b71831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15537953816886102850849967207670970169603320548689033713354208845958615523292 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.edn_intr.15537953816886102850849967207670970169603320548689033713354208845958615523292
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.91454510638650490663692777602670021158742294559434432903094423116187828853682
Short name T747
Test name
Test status
Simulation time 13059183 ps
CPU time 0.88 seconds
Started Nov 01 02:26:51 PM PDT 23
Finished Nov 01 02:26:55 PM PDT 23
Peak memory 205292 kb
Host smart-a27b67fa-4458-4d79-ab0a-a08da16ca2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91454510638650490663692777602670021158742294559434432903094423116187828853682 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 38.edn_smoke.91454510638650490663692777602670021158742294559434432903094423116187828853682
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.97130421466357042058905618748886295616859184499017501069830266494340065068274
Short name T475
Test name
Test status
Simulation time 154489183 ps
CPU time 3.97 seconds
Started Nov 01 02:26:49 PM PDT 23
Finished Nov 01 02:26:55 PM PDT 23
Peak memory 206324 kb
Host smart-dd357b46-8673-4c97-9d33-741b5e0a27fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97130421466357042058905618748886295616859184499017501069830266494340065068274 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.97130421466357042058905618748886295616859184499017501069830266494340065068274
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.44130487488443282654053242053535955637502839581227024716417581565023256872557
Short name T498
Test name
Test status
Simulation time 41708099183 ps
CPU time 1089.86 seconds
Started Nov 01 02:26:57 PM PDT 23
Finished Nov 01 02:45:18 PM PDT 23
Peak memory 215896 kb
Host smart-f6207618-c782-4d61-8b35-4bf045719c9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441304874884432826540532420
53535955637502839581227024716417581565023256872557 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.44130487488
443282654053242053535955637502839581227024716417581565023256872557
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.65798194097982770114435182938535604676234138442755934978694862924502921146032
Short name T434
Test name
Test status
Simulation time 18259183 ps
CPU time 1 seconds
Started Nov 01 02:27:10 PM PDT 23
Finished Nov 01 02:27:26 PM PDT 23
Peak memory 205620 kb
Host smart-6878a437-52d8-49e4-b1ab-2736b2cb8570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65798194097982770114435182938535604676234138442755934978694862924502921146032 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 39.edn_alert.65798194097982770114435182938535604676234138442755934978694862924502921146032
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.86450071349531577536949082517880616856441910274830872825728503168436979614077
Short name T270
Test name
Test status
Simulation time 28184990 ps
CPU time 0.94 seconds
Started Nov 01 02:26:56 PM PDT 23
Finished Nov 01 02:27:07 PM PDT 23
Peak memory 205640 kb
Host smart-b4c2304f-41c1-44a1-9cd5-598900a608c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86450071349531577536949082517880616856441910274830872825728503168436979614077 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.edn_alert_test.86450071349531577536949082517880616856441910274830872825728503168436979614077
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.74182118958033220345592376509754448433455886262623088529878888096864079918297
Short name T617
Test name
Test status
Simulation time 12219183 ps
CPU time 0.88 seconds
Started Nov 01 02:27:09 PM PDT 23
Finished Nov 01 02:27:25 PM PDT 23
Peak memory 214956 kb
Host smart-39177323-791b-4783-a921-d0ff906384bb
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74182118958033220345592376509754448433455886262623088529878888096864079918297 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.edn_disable.74182118958033220345592376509754448433455886262623088529878888096864079918297
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.111028768625969941300999035475579061395480251567507120272775744539523821058814
Short name T512
Test name
Test status
Simulation time 17319183 ps
CPU time 0.94 seconds
Started Nov 01 02:27:00 PM PDT 23
Finished Nov 01 02:27:13 PM PDT 23
Peak memory 214972 kb
Host smart-dda238fd-8bc3-4187-888c-9f8f3725b3a4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111028768625969941300999035475579061395480251567507120272775744539523821058814 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable_auto_req_mode.111028768625969941300999035475579061395480251567507120272
775744539523821058814
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.58964656051732505818429277226538558975790523358607690516818110341678790994588
Short name T497
Test name
Test status
Simulation time 24963823 ps
CPU time 1.12 seconds
Started Nov 01 02:27:06 PM PDT 23
Finished Nov 01 02:27:22 PM PDT 23
Peak memory 230472 kb
Host smart-1c487624-9c56-4bb9-9424-c1826138a46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58964656051732505818429277226538558975790523358607690516818110341678790994588 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.edn_err.58964656051732505818429277226538558975790523358607690516818110341678790994588
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.6302861710397739580812719151425584421507238235804674989352570640095980229667
Short name T37
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:26:59 PM PDT 23
Finished Nov 01 02:27:12 PM PDT 23
Peak memory 205772 kb
Host smart-b4298215-d1c1-477f-804c-43348a246da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6302861710397739580812719151425584421507238235804674989352570640095980229667 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.edn_genbits.6302861710397739580812719151425584421507238235804674989352570640095980229667
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.40713621074124261704873539667520111692244797614263553948686368773410354789263
Short name T580
Test name
Test status
Simulation time 18439183 ps
CPU time 1.12 seconds
Started Nov 01 02:27:01 PM PDT 23
Finished Nov 01 02:27:16 PM PDT 23
Peak memory 222344 kb
Host smart-d434ce89-3ee7-4d2b-a095-46d7e906037c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40713621074124261704873539667520111692244797614263553948686368773410354789263 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.edn_intr.40713621074124261704873539667520111692244797614263553948686368773410354789263
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.19903284536930574748072407493357119819183918891638509605554936665440376583864
Short name T381
Test name
Test status
Simulation time 13059183 ps
CPU time 0.87 seconds
Started Nov 01 02:27:01 PM PDT 23
Finished Nov 01 02:27:17 PM PDT 23
Peak memory 205416 kb
Host smart-222fa0a8-f3bc-4293-81e3-e2e10865bf21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19903284536930574748072407493357119819183918891638509605554936665440376583864 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 39.edn_smoke.19903284536930574748072407493357119819183918891638509605554936665440376583864
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.75908654958518042145607675090790651626582524595614720892591329157170930107674
Short name T439
Test name
Test status
Simulation time 154489183 ps
CPU time 3.94 seconds
Started Nov 01 02:26:57 PM PDT 23
Finished Nov 01 02:27:12 PM PDT 23
Peak memory 206420 kb
Host smart-4c7e30b5-57bf-4de1-9bf8-575010dd0a7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75908654958518042145607675090790651626582524595614720892591329157170930107674 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.75908654958518042145607675090790651626582524595614720892591329157170930107674
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.89205873384181872768877319875814153135936016332292491373418443497434845464560
Short name T778
Test name
Test status
Simulation time 41708099183 ps
CPU time 1085.73 seconds
Started Nov 01 02:27:09 PM PDT 23
Finished Nov 01 02:45:30 PM PDT 23
Peak memory 215856 kb
Host smart-1f986224-41a5-4c30-accc-26ba16364d86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892058733841818727688773198
75814153135936016332292491373418443497434845464560 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.89205873384
181872768877319875814153135936016332292491373418443497434845464560
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.2167578264524574834485739086194013766875367935111510754071645319563253651566
Short name T715
Test name
Test status
Simulation time 18259183 ps
CPU time 1.04 seconds
Started Nov 01 02:26:22 PM PDT 23
Finished Nov 01 02:26:26 PM PDT 23
Peak memory 205596 kb
Host smart-23d3050c-a5ad-448d-8b59-89dd9389d345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167578264524574834485739086194013766875367935111510754071645319563253651566 -assert nopostproc +UVM_TESTNAME=edn_alert_
test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.edn_alert.2167578264524574834485739086194013766875367935111510754071645319563253651566
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.3435263847533493039894025169086324111609510415768540093284690963417924181960
Short name T13
Test name
Test status
Simulation time 28184990 ps
CPU time 0.88 seconds
Started Nov 01 02:26:45 PM PDT 23
Finished Nov 01 02:26:50 PM PDT 23
Peak memory 205548 kb
Host smart-15cf12f8-6bcb-4aba-850f-11035ca3fa93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435263847533493039894025169086324111609510415768540093284690963417924181960 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.edn_alert_test.3435263847533493039894025169086324111609510415768540093284690963417924181960
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.26199125070746308501892350895197039036317648405082111505496311870051390470261
Short name T399
Test name
Test status
Simulation time 12219183 ps
CPU time 0.91 seconds
Started Nov 01 02:26:03 PM PDT 23
Finished Nov 01 02:26:08 PM PDT 23
Peak memory 214932 kb
Host smart-00ee63f5-f45f-40bf-a68d-6b78ea562c1b
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26199125070746308501892350895197039036317648405082111505496311870051390470261 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.edn_disable.26199125070746308501892350895197039036317648405082111505496311870051390470261
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.80581746005518018142221703973724281255243491607702052274929923588608602086270
Short name T918
Test name
Test status
Simulation time 17319183 ps
CPU time 0.94 seconds
Started Nov 01 02:26:44 PM PDT 23
Finished Nov 01 02:26:50 PM PDT 23
Peak memory 214940 kb
Host smart-5c291b48-dfb4-4ad9-9663-8a3c4c81f61f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80581746005518018142221703973724281255243491607702052274929923588608602086270 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable_auto_req_mode.80581746005518018142221703973724281255243491607702052274929
923588608602086270
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.4392175868894296449026004390165797264590380396244263018273680574257517036959
Short name T415
Test name
Test status
Simulation time 24963823 ps
CPU time 1.21 seconds
Started Nov 01 02:26:08 PM PDT 23
Finished Nov 01 02:26:14 PM PDT 23
Peak memory 230472 kb
Host smart-5c104b8d-6def-43ae-bcf8-e8e09feb4ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4392175868894296449026004390165797264590380396244263018273680574257517036959 -assert nopostproc +UVM_TESTNAME=edn_err_te
st +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.e
dn_err.4392175868894296449026004390165797264590380396244263018273680574257517036959
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.42863916297197501984755333052740622613947346114173627636579537862810832657568
Short name T691
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:25:54 PM PDT 23
Finished Nov 01 02:26:02 PM PDT 23
Peak memory 205872 kb
Host smart-4f75f54a-eb48-4ed0-b6dc-c16d0bbed5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42863916297197501984755333052740622613947346114173627636579537862810832657568 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.edn_genbits.42863916297197501984755333052740622613947346114173627636579537862810832657568
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.89595967017147317825082610668960346123990372258394915022284728732395279627925
Short name T941
Test name
Test status
Simulation time 18439183 ps
CPU time 1.16 seconds
Started Nov 01 02:26:38 PM PDT 23
Finished Nov 01 02:26:43 PM PDT 23
Peak memory 222364 kb
Host smart-a2e65beb-93cd-4727-b056-df7ec2c3798e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89595967017147317825082610668960346123990372258394915022284728732395279627925 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.edn_intr.89595967017147317825082610668960346123990372258394915022284728732395279627925
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.82684077400232602209703100442023034280195882826022299182010380246934107777404
Short name T651
Test name
Test status
Simulation time 11759183 ps
CPU time 0.84 seconds
Started Nov 01 02:26:07 PM PDT 23
Finished Nov 01 02:26:13 PM PDT 23
Peak memory 205344 kb
Host smart-fdcdb956-014d-4d85-ae6b-b8eba741d319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82684077400232602209703100442023034280195882826022299182010380246934107777404 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.edn_regwen.82684077400232602209703100442023034280195882826022299182010380246934107777404
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.62535412089801143589862268396868250789664746793901855736889315727368509111802
Short name T32
Test name
Test status
Simulation time 717215632 ps
CPU time 5.85 seconds
Started Nov 01 02:26:09 PM PDT 23
Finished Nov 01 02:26:18 PM PDT 23
Peak memory 234076 kb
Host smart-b406b28b-9aeb-47a2-b4f8-83692764ebf7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62535412089801143589862268396868250789664746793901855736889315727368509111802 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.edn_sec_cm.62535412089801143589862268396868250789664746793901855736889315727368509111802
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.113851066551568326713463256387221380017127174698077246168000461267860047956427
Short name T436
Test name
Test status
Simulation time 13059183 ps
CPU time 0.94 seconds
Started Nov 01 02:26:04 PM PDT 23
Finished Nov 01 02:26:08 PM PDT 23
Peak memory 205352 kb
Host smart-38821d76-842d-4514-b363-139418dc30a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113851066551568326713463256387221380017127174698077246168000461267860047956427 -assert nopostproc +UVM_TESTNAME=edn_smok
e_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.edn_smoke.113851066551568326713463256387221380017127174698077246168000461267860047956427
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.93329590593637332493071279375452059913989086012390106638382698320383277782810
Short name T607
Test name
Test status
Simulation time 154489183 ps
CPU time 3.99 seconds
Started Nov 01 02:26:39 PM PDT 23
Finished Nov 01 02:26:47 PM PDT 23
Peak memory 206416 kb
Host smart-813cc39d-fa76-481e-9ca6-488dcd47b289
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93329590593637332493071279375452059913989086012390106638382698320383277782810 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.93329590593637332493071279375452059913989086012390106638382698320383277782810
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.84689210809013101354157937195488187481259853482990227313985639603687619112788
Short name T751
Test name
Test status
Simulation time 41708099183 ps
CPU time 1124.93 seconds
Started Nov 01 02:26:08 PM PDT 23
Finished Nov 01 02:44:57 PM PDT 23
Peak memory 215876 kb
Host smart-0e2c683f-d6cc-49de-8f31-9da3e8afcdc0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846892108090131013541579371
95488187481259853482990227313985639603687619112788 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.846892108090
13101354157937195488187481259853482990227313985639603687619112788
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.47585877916905861543074845205338663895820358023726451910185248211964771461889
Short name T647
Test name
Test status
Simulation time 18259183 ps
CPU time 1.03 seconds
Started Nov 01 02:26:57 PM PDT 23
Finished Nov 01 02:27:09 PM PDT 23
Peak memory 205556 kb
Host smart-aaec07ed-732f-4611-8dfc-9512e8e66bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47585877916905861543074845205338663895820358023726451910185248211964771461889 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 40.edn_alert.47585877916905861543074845205338663895820358023726451910185248211964771461889
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.86670388003362533987393701867290805637681381416358408069998234078113159828071
Short name T586
Test name
Test status
Simulation time 28184990 ps
CPU time 0.86 seconds
Started Nov 01 02:27:02 PM PDT 23
Finished Nov 01 02:27:17 PM PDT 23
Peak memory 205544 kb
Host smart-b7d75820-b562-4bdb-a3f9-f58a7c068fb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86670388003362533987393701867290805637681381416358408069998234078113159828071 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.edn_alert_test.86670388003362533987393701867290805637681381416358408069998234078113159828071
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.86104884051956449144331168922461366077415383983581221394523055942824034880977
Short name T958
Test name
Test status
Simulation time 12219183 ps
CPU time 0.91 seconds
Started Nov 01 02:27:03 PM PDT 23
Finished Nov 01 02:27:18 PM PDT 23
Peak memory 214836 kb
Host smart-bc832854-42f1-4238-9b1e-45bd746acb06
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86104884051956449144331168922461366077415383983581221394523055942824034880977 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.edn_disable.86104884051956449144331168922461366077415383983581221394523055942824034880977
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.27564524280213326408885773488397754216694514157911577961977159712051675848617
Short name T587
Test name
Test status
Simulation time 17319183 ps
CPU time 0.92 seconds
Started Nov 01 02:26:57 PM PDT 23
Finished Nov 01 02:27:08 PM PDT 23
Peak memory 214944 kb
Host smart-135c11dc-ca81-4d75-a8f5-cf7755b43c8f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27564524280213326408885773488397754216694514157911577961977159712051675848617 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable_auto_req_mode.2756452428021332640888577348839775421669451415791157796197
7159712051675848617
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.36928543673774328795315663609319837774353705242675456986286427915032649234906
Short name T853
Test name
Test status
Simulation time 24963823 ps
CPU time 1.15 seconds
Started Nov 01 02:26:55 PM PDT 23
Finished Nov 01 02:27:04 PM PDT 23
Peak memory 230420 kb
Host smart-c8159b37-f01e-4277-8843-774b709e0f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36928543673774328795315663609319837774353705242675456986286427915032649234906 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.edn_err.36928543673774328795315663609319837774353705242675456986286427915032649234906
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.1362555881216092166283455212483716565426682552593666072466653203710898297510
Short name T385
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:27:06 PM PDT 23
Finished Nov 01 02:27:22 PM PDT 23
Peak memory 205916 kb
Host smart-c1fb901f-6ca3-4d54-980b-6330851eeeef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362555881216092166283455212483716565426682552593666072466653203710898297510 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.edn_genbits.1362555881216092166283455212483716565426682552593666072466653203710898297510
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.14583621606834982992852398618054906907788002824630533883037096606817477320581
Short name T920
Test name
Test status
Simulation time 18439183 ps
CPU time 1.12 seconds
Started Nov 01 02:27:02 PM PDT 23
Finished Nov 01 02:27:17 PM PDT 23
Peak memory 222296 kb
Host smart-dd578c36-9407-41a0-8489-07b23f4fbc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14583621606834982992852398618054906907788002824630533883037096606817477320581 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.edn_intr.14583621606834982992852398618054906907788002824630533883037096606817477320581
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.46966294800952184899502183657794211733589801560975049883795270548651467846458
Short name T944
Test name
Test status
Simulation time 13059183 ps
CPU time 0.86 seconds
Started Nov 01 02:27:09 PM PDT 23
Finished Nov 01 02:27:26 PM PDT 23
Peak memory 205404 kb
Host smart-f00b6f6e-4171-4c14-b9ee-c706b261a2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46966294800952184899502183657794211733589801560975049883795270548651467846458 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 40.edn_smoke.46966294800952184899502183657794211733589801560975049883795270548651467846458
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.49121304436722921614352722418523451343265680199904310184763884799682407959004
Short name T671
Test name
Test status
Simulation time 154489183 ps
CPU time 4.15 seconds
Started Nov 01 02:26:57 PM PDT 23
Finished Nov 01 02:27:12 PM PDT 23
Peak memory 206224 kb
Host smart-d2357b0d-da57-4a65-b25e-ad07d911556f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49121304436722921614352722418523451343265680199904310184763884799682407959004 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.49121304436722921614352722418523451343265680199904310184763884799682407959004
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.47796121585121968155513776418657155948549415568941993064228454395113226448683
Short name T754
Test name
Test status
Simulation time 41708099183 ps
CPU time 1101.82 seconds
Started Nov 01 02:26:54 PM PDT 23
Finished Nov 01 02:45:22 PM PDT 23
Peak memory 215884 kb
Host smart-57077bfc-1930-4d66-94a2-e99ee6b2a4fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477961215851219681555137764
18657155948549415568941993064228454395113226448683 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.47796121585
121968155513776418657155948549415568941993064228454395113226448683
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.58443770862200958013614986048632466343369462213710639166461139879082125578932
Short name T670
Test name
Test status
Simulation time 18259183 ps
CPU time 0.97 seconds
Started Nov 01 02:26:56 PM PDT 23
Finished Nov 01 02:27:05 PM PDT 23
Peak memory 205556 kb
Host smart-38006b99-ba92-4358-8231-a482db8d1d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58443770862200958013614986048632466343369462213710639166461139879082125578932 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 41.edn_alert.58443770862200958013614986048632466343369462213710639166461139879082125578932
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.3694655134427762910274932823650647463459804878906528216500065198476734531292
Short name T449
Test name
Test status
Simulation time 28184990 ps
CPU time 0.89 seconds
Started Nov 01 02:27:04 PM PDT 23
Finished Nov 01 02:27:20 PM PDT 23
Peak memory 205548 kb
Host smart-b6638af3-d925-4801-a74a-be6281f10524
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694655134427762910274932823650647463459804878906528216500065198476734531292 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.edn_alert_test.3694655134427762910274932823650647463459804878906528216500065198476734531292
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.32378754263460585116459494580140892617763850363682820425177095766296839997398
Short name T874
Test name
Test status
Simulation time 12219183 ps
CPU time 0.9 seconds
Started Nov 01 02:27:00 PM PDT 23
Finished Nov 01 02:27:13 PM PDT 23
Peak memory 214932 kb
Host smart-7336c6cd-f316-4874-9500-6770149ac820
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32378754263460585116459494580140892617763850363682820425177095766296839997398 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.edn_disable.32378754263460585116459494580140892617763850363682820425177095766296839997398
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.83478584016457471528214566504981590812261541991836010671222391879870128596714
Short name T667
Test name
Test status
Simulation time 17319183 ps
CPU time 0.93 seconds
Started Nov 01 02:27:00 PM PDT 23
Finished Nov 01 02:27:13 PM PDT 23
Peak memory 214944 kb
Host smart-2c2daa11-9a9b-485e-8c35-84b9c5c42cb7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83478584016457471528214566504981590812261541991836010671222391879870128596714 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable_auto_req_mode.8347858401645747152821456650498159081226154199183601067122
2391879870128596714
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.115670797334716599889070258567736447771931287454089072570011226874829259746567
Short name T557
Test name
Test status
Simulation time 24963823 ps
CPU time 1.13 seconds
Started Nov 01 02:27:07 PM PDT 23
Finished Nov 01 02:27:23 PM PDT 23
Peak memory 230448 kb
Host smart-23c2b0c0-4460-4bae-8341-cbddd0e1e20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115670797334716599889070258567736447771931287454089072570011226874829259746567 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.edn_err.115670797334716599889070258567736447771931287454089072570011226874829259746567
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.56765291544429432850323502218098680999872595485426893600438512951223267214646
Short name T340
Test name
Test status
Simulation time 17999183 ps
CPU time 1.05 seconds
Started Nov 01 02:27:05 PM PDT 23
Finished Nov 01 02:27:21 PM PDT 23
Peak memory 205904 kb
Host smart-52321e13-1225-4412-9d18-43761f1acae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56765291544429432850323502218098680999872595485426893600438512951223267214646 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.edn_genbits.56765291544429432850323502218098680999872595485426893600438512951223267214646
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.107406514643281874904286773956231569890313283999712413023509560342716448297237
Short name T758
Test name
Test status
Simulation time 18439183 ps
CPU time 1.12 seconds
Started Nov 01 02:26:56 PM PDT 23
Finished Nov 01 02:27:06 PM PDT 23
Peak memory 222448 kb
Host smart-813f1f9c-7188-42cb-8efc-e0ab50a9c85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107406514643281874904286773956231569890313283999712413023509560342716448297237 -assert nopostproc +UVM_TESTNAME=edn_intr
_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.edn_intr.107406514643281874904286773956231569890313283999712413023509560342716448297237
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.108102813752699377924569665902681277627438527052211914269569860286260348653662
Short name T344
Test name
Test status
Simulation time 13059183 ps
CPU time 0.88 seconds
Started Nov 01 02:27:01 PM PDT 23
Finished Nov 01 02:27:16 PM PDT 23
Peak memory 205348 kb
Host smart-9b6d1636-b043-425d-93fa-a39f64d0c053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108102813752699377924569665902681277627438527052211914269569860286260348653662 -assert nopostproc +UVM_TESTNAME=edn_smok
e_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 41.edn_smoke.108102813752699377924569665902681277627438527052211914269569860286260348653662
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.13145194104404439217892398411557877838163275572768200788592834450398213492758
Short name T967
Test name
Test status
Simulation time 154489183 ps
CPU time 4.13 seconds
Started Nov 01 02:26:55 PM PDT 23
Finished Nov 01 02:27:07 PM PDT 23
Peak memory 206316 kb
Host smart-75749fa4-a766-4077-8dbb-a2bf35366742
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13145194104404439217892398411557877838163275572768200788592834450398213492758 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.13145194104404439217892398411557877838163275572768200788592834450398213492758
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.53948634442236273175804374333233892271836531921509414210806160604617817199439
Short name T784
Test name
Test status
Simulation time 41708099183 ps
CPU time 1095.06 seconds
Started Nov 01 02:27:04 PM PDT 23
Finished Nov 01 02:45:34 PM PDT 23
Peak memory 215920 kb
Host smart-c212f2d5-3715-480b-91c2-5a1f380482bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539486344422362731758043743
33233892271836531921509414210806160604617817199439 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.53948634442
236273175804374333233892271836531921509414210806160604617817199439
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.13769838163879488478630463398916842947057907865025592409738281694650563002222
Short name T716
Test name
Test status
Simulation time 18259183 ps
CPU time 1.03 seconds
Started Nov 01 02:26:57 PM PDT 23
Finished Nov 01 02:27:08 PM PDT 23
Peak memory 205364 kb
Host smart-ba58d90f-1841-436c-a3da-f60f7503ddff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13769838163879488478630463398916842947057907865025592409738281694650563002222 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 42.edn_alert.13769838163879488478630463398916842947057907865025592409738281694650563002222
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.83727719578690675020343511492738355679852970877604913209192636271940334089701
Short name T581
Test name
Test status
Simulation time 28184990 ps
CPU time 0.87 seconds
Started Nov 01 02:27:09 PM PDT 23
Finished Nov 01 02:27:25 PM PDT 23
Peak memory 205444 kb
Host smart-429702bb-1253-4c00-9192-771ee42be331
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83727719578690675020343511492738355679852970877604913209192636271940334089701 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.edn_alert_test.83727719578690675020343511492738355679852970877604913209192636271940334089701
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.82027011282143453637895202699295111312810197435540201961490951780061016513015
Short name T791
Test name
Test status
Simulation time 12219183 ps
CPU time 0.89 seconds
Started Nov 01 03:00:52 PM PDT 23
Finished Nov 01 03:00:54 PM PDT 23
Peak memory 214936 kb
Host smart-971eb0e0-424e-4184-8b25-a285e4753327
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82027011282143453637895202699295111312810197435540201961490951780061016513015 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.edn_disable.82027011282143453637895202699295111312810197435540201961490951780061016513015
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.35530915234907307783611674934187534424828309074395466793762548312089548808110
Short name T674
Test name
Test status
Simulation time 17319183 ps
CPU time 0.92 seconds
Started Nov 01 02:27:01 PM PDT 23
Finished Nov 01 02:27:16 PM PDT 23
Peak memory 214944 kb
Host smart-8b79fb98-5f7a-4860-8100-956d0a18686e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35530915234907307783611674934187534424828309074395466793762548312089548808110 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable_auto_req_mode.3553091523490730778361167493418753442482830907439546679376
2548312089548808110
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.83171781505155442976111122017329165313058255089950979927607746219376820467854
Short name T328
Test name
Test status
Simulation time 24963823 ps
CPU time 1.16 seconds
Started Nov 01 02:26:57 PM PDT 23
Finished Nov 01 02:27:09 PM PDT 23
Peak memory 230484 kb
Host smart-b92ab0ca-138d-41a0-b908-0363742ea231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83171781505155442976111122017329165313058255089950979927607746219376820467854 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.edn_err.83171781505155442976111122017329165313058255089950979927607746219376820467854
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.18282135466948066800142742573930866322841434286969056479458782425154442336800
Short name T800
Test name
Test status
Simulation time 17999183 ps
CPU time 1.16 seconds
Started Nov 01 02:26:57 PM PDT 23
Finished Nov 01 02:27:09 PM PDT 23
Peak memory 205840 kb
Host smart-b700e1d9-1c44-4aff-800b-2494dac5b71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18282135466948066800142742573930866322841434286969056479458782425154442336800 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.edn_genbits.18282135466948066800142742573930866322841434286969056479458782425154442336800
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.28182969798594347719032605660675195618190965647480931392876617691985175252834
Short name T446
Test name
Test status
Simulation time 18439183 ps
CPU time 1.19 seconds
Started Nov 01 02:27:05 PM PDT 23
Finished Nov 01 02:27:22 PM PDT 23
Peak memory 222368 kb
Host smart-9aabbeb8-dd5f-49ea-8c65-c9ebdafe7732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28182969798594347719032605660675195618190965647480931392876617691985175252834 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.edn_intr.28182969798594347719032605660675195618190965647480931392876617691985175252834
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.54579647984336229574281109604883165316684381619792085146393290827238222075913
Short name T349
Test name
Test status
Simulation time 13059183 ps
CPU time 0.87 seconds
Started Nov 01 02:27:08 PM PDT 23
Finished Nov 01 02:27:24 PM PDT 23
Peak memory 205364 kb
Host smart-38d90dc8-490d-4327-a31a-7931c618d436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54579647984336229574281109604883165316684381619792085146393290827238222075913 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 42.edn_smoke.54579647984336229574281109604883165316684381619792085146393290827238222075913
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.102207256797268574603006300182560783871168034650539687756147835165386164445197
Short name T862
Test name
Test status
Simulation time 154489183 ps
CPU time 3.92 seconds
Started Nov 01 02:27:04 PM PDT 23
Finished Nov 01 02:27:23 PM PDT 23
Peak memory 206436 kb
Host smart-78382bd7-67e2-4113-8678-bf91ab5d7242
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102207256797268574603006300182560783871168034650539687756147835165386164445197 -assert nopo
stproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.102207256797268574603006300182560783871168034650539687756147835165386164445197
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.93651921968928662802186059815756579555068589466331804350668048955387498136524
Short name T324
Test name
Test status
Simulation time 41708099183 ps
CPU time 1092.46 seconds
Started Nov 01 02:39:05 PM PDT 23
Finished Nov 01 02:57:21 PM PDT 23
Peak memory 215816 kb
Host smart-86fcc629-2316-4d9c-b664-6ea9d21e74d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936519219689286628021860598
15756579555068589466331804350668048955387498136524 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.93651921968
928662802186059815756579555068589466331804350668048955387498136524
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.26036127902160746520331942422166152716970512834971044939838051297141312010792
Short name T645
Test name
Test status
Simulation time 18259183 ps
CPU time 0.96 seconds
Started Nov 01 02:27:00 PM PDT 23
Finished Nov 01 02:27:13 PM PDT 23
Peak memory 205620 kb
Host smart-a55e90ce-73a6-47b3-9acb-a3d27caff23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26036127902160746520331942422166152716970512834971044939838051297141312010792 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 43.edn_alert.26036127902160746520331942422166152716970512834971044939838051297141312010792
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.30748534701791578263776902286167415142858376858129905123937104494930600231532
Short name T582
Test name
Test status
Simulation time 28184990 ps
CPU time 0.86 seconds
Started Nov 01 02:27:05 PM PDT 23
Finished Nov 01 02:27:21 PM PDT 23
Peak memory 205540 kb
Host smart-39187def-9ca2-4caa-b804-9594caafd30d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30748534701791578263776902286167415142858376858129905123937104494930600231532 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.edn_alert_test.30748534701791578263776902286167415142858376858129905123937104494930600231532
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.28348524202483422985510127173176272864323164539569294501099478340402923395965
Short name T717
Test name
Test status
Simulation time 12219183 ps
CPU time 0.89 seconds
Started Nov 01 02:26:59 PM PDT 23
Finished Nov 01 02:27:12 PM PDT 23
Peak memory 214880 kb
Host smart-8876536d-dbac-4d7a-b415-7cbb5c8d5138
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28348524202483422985510127173176272864323164539569294501099478340402923395965 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.edn_disable.28348524202483422985510127173176272864323164539569294501099478340402923395965
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.21264254629293015781838563133788172002929899643369619338433066559770170635674
Short name T520
Test name
Test status
Simulation time 17319183 ps
CPU time 0.94 seconds
Started Nov 01 02:26:56 PM PDT 23
Finished Nov 01 02:27:06 PM PDT 23
Peak memory 214112 kb
Host smart-26ba6152-2e2a-4a34-97c2-a15f1f6bedc8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21264254629293015781838563133788172002929899643369619338433066559770170635674 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable_auto_req_mode.2126425462929301578183856313378817200292989964336961933843
3066559770170635674
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.48029609169595047229866112658482440656854216044227005012174058490167573858235
Short name T480
Test name
Test status
Simulation time 24963823 ps
CPU time 1.15 seconds
Started Nov 01 02:26:56 PM PDT 23
Finished Nov 01 02:27:07 PM PDT 23
Peak memory 230640 kb
Host smart-6acc0466-3bf3-4864-aaee-5932aff42c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48029609169595047229866112658482440656854216044227005012174058490167573858235 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.edn_err.48029609169595047229866112658482440656854216044227005012174058490167573858235
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.40941458721894310666349756724141660885707090081718946144771540638881350172599
Short name T948
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 01 02:27:04 PM PDT 23
Finished Nov 01 02:27:20 PM PDT 23
Peak memory 205908 kb
Host smart-beaa195f-1540-499a-a4e0-e89fcd5995b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40941458721894310666349756724141660885707090081718946144771540638881350172599 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.edn_genbits.40941458721894310666349756724141660885707090081718946144771540638881350172599
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.11348204766865982515957904451649017147532439906462319178946456191107869450729
Short name T519
Test name
Test status
Simulation time 18439183 ps
CPU time 1.17 seconds
Started Nov 01 02:26:54 PM PDT 23
Finished Nov 01 02:27:01 PM PDT 23
Peak memory 222320 kb
Host smart-57d012a0-45f9-4704-a60f-b6ca0dcfdf0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11348204766865982515957904451649017147532439906462319178946456191107869450729 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.edn_intr.11348204766865982515957904451649017147532439906462319178946456191107869450729
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.10024453259316418791392906704941102246709421845086599330973037861564148452883
Short name T603
Test name
Test status
Simulation time 13059183 ps
CPU time 0.85 seconds
Started Nov 01 02:26:55 PM PDT 23
Finished Nov 01 02:27:03 PM PDT 23
Peak memory 205344 kb
Host smart-a501b9cb-1440-44b2-ab43-ef8e7fc35a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10024453259316418791392906704941102246709421845086599330973037861564148452883 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 43.edn_smoke.10024453259316418791392906704941102246709421845086599330973037861564148452883
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.104546656625064320861783789353878461056405786479568088587504194588423269216886
Short name T375
Test name
Test status
Simulation time 154489183 ps
CPU time 4.38 seconds
Started Nov 01 02:26:58 PM PDT 23
Finished Nov 01 02:27:13 PM PDT 23
Peak memory 206428 kb
Host smart-cd7f4c10-5f67-4147-a41b-66fa867823a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104546656625064320861783789353878461056405786479568088587504194588423269216886 -assert nopo
stproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.104546656625064320861783789353878461056405786479568088587504194588423269216886
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.90663328786825345521728892319233023163569436312686948054232143824082328250826
Short name T252
Test name
Test status
Simulation time 41708099183 ps
CPU time 1106.65 seconds
Started Nov 01 02:26:59 PM PDT 23
Finished Nov 01 02:45:38 PM PDT 23
Peak memory 215920 kb
Host smart-edb2ad8b-3f95-484b-9075-f98aa7d9f5d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906633287868253455217288923
19233023163569436312686948054232143824082328250826 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.90663328786
825345521728892319233023163569436312686948054232143824082328250826
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.80710051870125760505873551929812487493383606685575329388407218592559709601159
Short name T709
Test name
Test status
Simulation time 18259183 ps
CPU time 1.01 seconds
Started Nov 01 02:27:08 PM PDT 23
Finished Nov 01 02:27:24 PM PDT 23
Peak memory 205492 kb
Host smart-7423c9e0-3dff-499d-a8cd-401d062e8869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80710051870125760505873551929812487493383606685575329388407218592559709601159 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 44.edn_alert.80710051870125760505873551929812487493383606685575329388407218592559709601159
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.92266671734502746021719826956378869544724247213774074084241723649602251804770
Short name T12
Test name
Test status
Simulation time 28184990 ps
CPU time 0.9 seconds
Started Nov 01 02:27:00 PM PDT 23
Finished Nov 01 02:27:14 PM PDT 23
Peak memory 205552 kb
Host smart-1df17167-c3f8-4a1d-b449-ee6e528f1502
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92266671734502746021719826956378869544724247213774074084241723649602251804770 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.edn_alert_test.92266671734502746021719826956378869544724247213774074084241723649602251804770
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.56122519111699677191885025902694378032667153313116938637843042937765831814582
Short name T972
Test name
Test status
Simulation time 12219183 ps
CPU time 0.84 seconds
Started Nov 01 02:27:06 PM PDT 23
Finished Nov 01 02:27:21 PM PDT 23
Peak memory 214928 kb
Host smart-9769b4f3-401e-4401-bc8a-7369ad6d3e51
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56122519111699677191885025902694378032667153313116938637843042937765831814582 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.edn_disable.56122519111699677191885025902694378032667153313116938637843042937765831814582
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.113032499423136748649064386941729426516053705756511560301037453455887765443648
Short name T355
Test name
Test status
Simulation time 17319183 ps
CPU time 0.96 seconds
Started Nov 01 02:27:04 PM PDT 23
Finished Nov 01 02:27:20 PM PDT 23
Peak memory 214976 kb
Host smart-9e4abc86-ec96-4611-9e27-28ea725de5dd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113032499423136748649064386941729426516053705756511560301037453455887765443648 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable_auto_req_mode.113032499423136748649064386941729426516053705756511560301
037453455887765443648
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.20477057154902053083916474021974394493980397671926676501246309195360345471323
Short name T815
Test name
Test status
Simulation time 24963823 ps
CPU time 1.12 seconds
Started Nov 01 02:27:10 PM PDT 23
Finished Nov 01 02:27:26 PM PDT 23
Peak memory 230488 kb
Host smart-cae43081-aacb-4fc0-b09d-51601b0403b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20477057154902053083916474021974394493980397671926676501246309195360345471323 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.edn_err.20477057154902053083916474021974394493980397671926676501246309195360345471323
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.109825038594106767319316760455536116157828350166618422594824024997598571363185
Short name T953
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:26:56 PM PDT 23
Finished Nov 01 02:27:05 PM PDT 23
Peak memory 206016 kb
Host smart-5291be38-895c-400e-914c-fd67ed9aec18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109825038594106767319316760455536116157828350166618422594824024997598571363185 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 44.edn_genbits.109825038594106767319316760455536116157828350166618422594824024997598571363185
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.40298008218924222005406947119131764733060429016430144840556001319745363682712
Short name T523
Test name
Test status
Simulation time 18439183 ps
CPU time 1.17 seconds
Started Nov 01 02:26:55 PM PDT 23
Finished Nov 01 02:27:03 PM PDT 23
Peak memory 222220 kb
Host smart-291afad0-7958-47a6-aa17-23bbf20d0b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40298008218924222005406947119131764733060429016430144840556001319745363682712 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.edn_intr.40298008218924222005406947119131764733060429016430144840556001319745363682712
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.2021501134257176916459536975334557045444513623849674451782770433693337157670
Short name T934
Test name
Test status
Simulation time 13059183 ps
CPU time 0.87 seconds
Started Nov 01 02:26:59 PM PDT 23
Finished Nov 01 02:27:11 PM PDT 23
Peak memory 205348 kb
Host smart-55888e4e-93ee-4333-88a9-de2bbbd35ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021501134257176916459536975334557045444513623849674451782770433693337157670 -assert nopostproc +UVM_TESTNAME=edn_smoke_
test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.edn_smoke.2021501134257176916459536975334557045444513623849674451782770433693337157670
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.96840580708681667702019609353104748905206094269369404732794785692251539690370
Short name T820
Test name
Test status
Simulation time 154489183 ps
CPU time 3.96 seconds
Started Nov 01 02:27:24 PM PDT 23
Finished Nov 01 02:27:41 PM PDT 23
Peak memory 206360 kb
Host smart-493329af-8463-4b61-a095-8f792d096455
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96840580708681667702019609353104748905206094269369404732794785692251539690370 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.96840580708681667702019609353104748905206094269369404732794785692251539690370
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.52550609985539898835132392590533194928172172372523081497678337050948430663507
Short name T806
Test name
Test status
Simulation time 41708099183 ps
CPU time 1084.62 seconds
Started Nov 01 02:26:53 PM PDT 23
Finished Nov 01 02:45:04 PM PDT 23
Peak memory 215884 kb
Host smart-65de7a94-550e-4eb1-afcd-f5470245a60f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525506099855398988351323925
90533194928172172372523081497678337050948430663507 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.52550609985
539898835132392590533194928172172372523081497678337050948430663507
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.153579667398732040380567417930024691901390165100827105608114028709203105378
Short name T263
Test name
Test status
Simulation time 18259183 ps
CPU time 0.99 seconds
Started Nov 01 02:27:08 PM PDT 23
Finished Nov 01 02:27:24 PM PDT 23
Peak memory 205616 kb
Host smart-3a23fe1f-e88c-4287-aa7d-7d0e242ebcff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153579667398732040380567417930024691901390165100827105608114028709203105378 -assert nopostproc +UVM_TESTNAME=edn_alert_t
est +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.edn_alert.153579667398732040380567417930024691901390165100827105608114028709203105378
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.110928303532310998642923021087180540651180684295588414402441822484094435288664
Short name T467
Test name
Test status
Simulation time 28184990 ps
CPU time 0.88 seconds
Started Nov 01 02:27:22 PM PDT 23
Finished Nov 01 02:27:37 PM PDT 23
Peak memory 205492 kb
Host smart-12d6eaf7-ac72-44e1-9f99-b3685e4075dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110928303532310998642923021087180540651180684295588414402441822484094435288664 -assert nopostp
roc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 45.edn_alert_test.110928303532310998642923021087180540651180684295588414402441822484094435288664
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.93716535737494929317956938734711536809235733263025440865800768759412779317100
Short name T412
Test name
Test status
Simulation time 12219183 ps
CPU time 0.87 seconds
Started Nov 01 02:27:04 PM PDT 23
Finished Nov 01 02:27:19 PM PDT 23
Peak memory 215044 kb
Host smart-4bf0aef0-adbc-43e4-85de-8dd34247e2c3
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93716535737494929317956938734711536809235733263025440865800768759412779317100 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.edn_disable.93716535737494929317956938734711536809235733263025440865800768759412779317100
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.51555387568918015015984047363410096646397964458145538251910526926181347829983
Short name T752
Test name
Test status
Simulation time 17319183 ps
CPU time 0.94 seconds
Started Nov 01 02:27:27 PM PDT 23
Finished Nov 01 02:27:42 PM PDT 23
Peak memory 214988 kb
Host smart-a76e3fc6-a71e-4f9c-87ca-4f16e6e021ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51555387568918015015984047363410096646397964458145538251910526926181347829983 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable_auto_req_mode.5155538756891801501598404736341009664639796445814553825191
0526926181347829983
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.70671821116989782737417851005073532668886151673420607088849808557371150958805
Short name T308
Test name
Test status
Simulation time 24963823 ps
CPU time 1.12 seconds
Started Nov 01 02:27:21 PM PDT 23
Finished Nov 01 02:27:36 PM PDT 23
Peak memory 230500 kb
Host smart-e0188114-9304-4a1c-87b8-0fbb6343016c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70671821116989782737417851005073532668886151673420607088849808557371150958805 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.edn_err.70671821116989782737417851005073532668886151673420607088849808557371150958805
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.14473859946158156929289612527536135205665148084035737827671153966088183172443
Short name T924
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 01 02:26:59 PM PDT 23
Finished Nov 01 02:27:11 PM PDT 23
Peak memory 205908 kb
Host smart-33c58c58-c008-4247-ba1f-0d51921e3f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14473859946158156929289612527536135205665148084035737827671153966088183172443 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.edn_genbits.14473859946158156929289612527536135205665148084035737827671153966088183172443
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.98340782308480903639313174450814867097009577128110371286005153152683300168743
Short name T25
Test name
Test status
Simulation time 18439183 ps
CPU time 1.11 seconds
Started Nov 01 02:27:12 PM PDT 23
Finished Nov 01 02:27:29 PM PDT 23
Peak memory 222180 kb
Host smart-f83bfba7-1cdc-46ad-adfd-bbd40b2ff362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98340782308480903639313174450814867097009577128110371286005153152683300168743 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.edn_intr.98340782308480903639313174450814867097009577128110371286005153152683300168743
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.72029258602812203432437399450421449010059297445252354626088795543001255365767
Short name T264
Test name
Test status
Simulation time 13059183 ps
CPU time 0.9 seconds
Started Nov 01 02:27:27 PM PDT 23
Finished Nov 01 02:27:42 PM PDT 23
Peak memory 205156 kb
Host smart-a6d39919-64dc-4f64-8a2f-fadfdf896921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72029258602812203432437399450421449010059297445252354626088795543001255365767 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 45.edn_smoke.72029258602812203432437399450421449010059297445252354626088795543001255365767
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.9246482116513887788346294308640446890315749307371979037553463804952831085626
Short name T692
Test name
Test status
Simulation time 154489183 ps
CPU time 3.78 seconds
Started Nov 01 02:27:40 PM PDT 23
Finished Nov 01 02:27:53 PM PDT 23
Peak memory 206400 kb
Host smart-38aac9a8-bc1a-4990-8bf4-8e4b348cc2f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9246482116513887788346294308640446890315749307371979037553463804952831085626 -assert nopost
proc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.9246482116513887788346294308640446890315749307371979037553463804952831085626
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.104605027600499447943383934381936297686943066832689859318959859920504835988698
Short name T844
Test name
Test status
Simulation time 41708099183 ps
CPU time 1081.34 seconds
Started Nov 01 02:27:01 PM PDT 23
Finished Nov 01 02:45:16 PM PDT 23
Peak memory 215944 kb
Host smart-e8dc5cd8-aed2-42b4-968c-9ef6dd904602
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104605027600499447943383934
381936297686943066832689859318959859920504835988698 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.1046050276
00499447943383934381936297686943066832689859318959859920504835988698
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.115437644619266636315371866924686323463229324416350773093656406603309770040095
Short name T322
Test name
Test status
Simulation time 18259183 ps
CPU time 0.98 seconds
Started Nov 01 02:27:24 PM PDT 23
Finished Nov 01 02:27:39 PM PDT 23
Peak memory 205580 kb
Host smart-f81723d0-e1f3-431f-b82d-04ede19469cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115437644619266636315371866924686323463229324416350773093656406603309770040095 -assert nopostproc +UVM_TESTNAME=edn_aler
t_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 46.edn_alert.115437644619266636315371866924686323463229324416350773093656406603309770040095
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.4669677538909678303284883371602776015803522775439132117312113779347146050149
Short name T638
Test name
Test status
Simulation time 28184990 ps
CPU time 0.87 seconds
Started Nov 01 02:27:21 PM PDT 23
Finished Nov 01 02:27:35 PM PDT 23
Peak memory 205552 kb
Host smart-02c7ba4a-dcf8-47ca-a736-26917cf9e60c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4669677538909678303284883371602776015803522775439132117312113779347146050149 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.edn_alert_test.4669677538909678303284883371602776015803522775439132117312113779347146050149
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.107230659210406319163296766049178416103580724567160315411137596662068758544910
Short name T444
Test name
Test status
Simulation time 12219183 ps
CPU time 0.93 seconds
Started Nov 01 02:26:59 PM PDT 23
Finished Nov 01 02:27:11 PM PDT 23
Peak memory 214976 kb
Host smart-7f70a74f-7f0f-4727-98ea-2e85bf7fa8b5
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107230659210406319163296766049178416103580724567160315411137596662068758544910 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 46.edn_disable.107230659210406319163296766049178416103580724567160315411137596662068758544910
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.45087558471797668125648821111739048441485396677123102314524426724930542085793
Short name T293
Test name
Test status
Simulation time 17319183 ps
CPU time 0.9 seconds
Started Nov 01 02:27:25 PM PDT 23
Finished Nov 01 02:27:39 PM PDT 23
Peak memory 214740 kb
Host smart-e64a9aca-7873-4e4f-82e5-23fba5458510
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45087558471797668125648821111739048441485396677123102314524426724930542085793 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable_auto_req_mode.4508755847179766812564882111173904844148539667712310231452
4426724930542085793
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.93108708038145329555850377486855507654137363275149707691823140528501419772957
Short name T387
Test name
Test status
Simulation time 24963823 ps
CPU time 1.12 seconds
Started Nov 01 02:27:00 PM PDT 23
Finished Nov 01 02:27:13 PM PDT 23
Peak memory 230780 kb
Host smart-1c1c3e18-3611-4720-9dbd-938e55fbf6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93108708038145329555850377486855507654137363275149707691823140528501419772957 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.edn_err.93108708038145329555850377486855507654137363275149707691823140528501419772957
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.70703933485159355598486005951078228815234719070371612777280237484624079221067
Short name T323
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:27:14 PM PDT 23
Finished Nov 01 02:27:30 PM PDT 23
Peak memory 205852 kb
Host smart-ba202c18-fbfd-4652-ac4d-69baaa8018ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70703933485159355598486005951078228815234719070371612777280237484624079221067 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.edn_genbits.70703933485159355598486005951078228815234719070371612777280237484624079221067
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.34906320374270365631388383833672167019943355309222103428166235776112891233206
Short name T268
Test name
Test status
Simulation time 18439183 ps
CPU time 1.1 seconds
Started Nov 01 02:27:11 PM PDT 23
Finished Nov 01 02:27:27 PM PDT 23
Peak memory 222224 kb
Host smart-0a481f73-43e3-477b-8adf-5a898bca85ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34906320374270365631388383833672167019943355309222103428166235776112891233206 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.edn_intr.34906320374270365631388383833672167019943355309222103428166235776112891233206
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.87853134188161799449184382701121956833525407452263595118717094784570822564795
Short name T840
Test name
Test status
Simulation time 13059183 ps
CPU time 0.87 seconds
Started Nov 01 02:27:02 PM PDT 23
Finished Nov 01 02:27:17 PM PDT 23
Peak memory 205456 kb
Host smart-563906c1-6f2b-4791-9196-936a034bd35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87853134188161799449184382701121956833525407452263595118717094784570822564795 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 46.edn_smoke.87853134188161799449184382701121956833525407452263595118717094784570822564795
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.95779565038689529004508249829028076470555184684813986000367087073226323830930
Short name T272
Test name
Test status
Simulation time 154489183 ps
CPU time 4.03 seconds
Started Nov 01 02:27:38 PM PDT 23
Finished Nov 01 02:27:53 PM PDT 23
Peak memory 206328 kb
Host smart-51133876-f04b-42e3-906a-2b7b9494b7b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95779565038689529004508249829028076470555184684813986000367087073226323830930 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.95779565038689529004508249829028076470555184684813986000367087073226323830930
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.9522048907465526669458669463225666871965236242725317997967279398760697107647
Short name T400
Test name
Test status
Simulation time 41708099183 ps
CPU time 1063.85 seconds
Started Nov 01 02:27:19 PM PDT 23
Finished Nov 01 02:45:17 PM PDT 23
Peak memory 215756 kb
Host smart-0b44a2bc-d8c2-4cf7-9853-8e2159ac315e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952204890746552666945866946
3225666871965236242725317997967279398760697107647 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.952204890746
5526669458669463225666871965236242725317997967279398760697107647
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.7412665659435246932597527047203107370332430869163245155073840677954613870339
Short name T882
Test name
Test status
Simulation time 18259183 ps
CPU time 0.97 seconds
Started Nov 01 02:27:56 PM PDT 23
Finished Nov 01 02:28:01 PM PDT 23
Peak memory 205116 kb
Host smart-8c5a68fd-042e-41a2-abf0-907fbefd0475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7412665659435246932597527047203107370332430869163245155073840677954613870339 -assert nopostproc +UVM_TESTNAME=edn_alert_
test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.edn_alert.7412665659435246932597527047203107370332430869163245155073840677954613870339
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.83284768223890813924946756582258083852886185784659077944852246490804017189812
Short name T45
Test name
Test status
Simulation time 28184990 ps
CPU time 0.87 seconds
Started Nov 01 02:27:24 PM PDT 23
Finished Nov 01 02:27:38 PM PDT 23
Peak memory 205484 kb
Host smart-bb218b1c-1d0b-43e1-b127-021f187df52e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83284768223890813924946756582258083852886185784659077944852246490804017189812 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.edn_alert_test.83284768223890813924946756582258083852886185784659077944852246490804017189812
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.50214286244485093857384349870261634925757872231944316507884749479619723291863
Short name T891
Test name
Test status
Simulation time 12219183 ps
CPU time 0.87 seconds
Started Nov 01 02:27:57 PM PDT 23
Finished Nov 01 02:28:03 PM PDT 23
Peak memory 214444 kb
Host smart-8804f23d-b131-4228-825a-0cf7b414f10f
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50214286244485093857384349870261634925757872231944316507884749479619723291863 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.edn_disable.50214286244485093857384349870261634925757872231944316507884749479619723291863
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.1496715826999622183069034894648753372885240278135034237356982202568815827828
Short name T908
Test name
Test status
Simulation time 17319183 ps
CPU time 0.96 seconds
Started Nov 01 02:27:14 PM PDT 23
Finished Nov 01 02:27:30 PM PDT 23
Peak memory 214952 kb
Host smart-afd36162-ba51-4148-868e-7107c44a36c9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496715826999622183069034894648753372885240278135034237356982202568815827828 -assert nopostproc
+UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable_auto_req_mode.14967158269996221830690348946487533728852402781350342373569
82202568815827828
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.42657451542590105200020526112428481813734965779000962819846252490684569486341
Short name T785
Test name
Test status
Simulation time 24963823 ps
CPU time 1.15 seconds
Started Nov 01 02:27:23 PM PDT 23
Finished Nov 01 02:27:37 PM PDT 23
Peak memory 230516 kb
Host smart-c784b423-b40f-4cf9-98fe-eac3b4859c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42657451542590105200020526112428481813734965779000962819846252490684569486341 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.edn_err.42657451542590105200020526112428481813734965779000962819846252490684569486341
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.10533636950626018321539108458198499508372461507734388750234603650511707422385
Short name T403
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 01 02:27:11 PM PDT 23
Finished Nov 01 02:27:27 PM PDT 23
Peak memory 205852 kb
Host smart-ea0638c1-7b37-4f90-be04-dde7a7c56fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10533636950626018321539108458198499508372461507734388750234603650511707422385 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.edn_genbits.10533636950626018321539108458198499508372461507734388750234603650511707422385
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.43167908516032462454017840044167115515780817830283683035006433597104644236700
Short name T783
Test name
Test status
Simulation time 18439183 ps
CPU time 1.11 seconds
Started Nov 01 02:27:32 PM PDT 23
Finished Nov 01 02:27:46 PM PDT 23
Peak memory 222192 kb
Host smart-2b8ce1a0-12db-4ebf-b66b-4310f17d9947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43167908516032462454017840044167115515780817830283683035006433597104644236700 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.edn_intr.43167908516032462454017840044167115515780817830283683035006433597104644236700
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.73980933277494667187845624782098026469577600267177548119534105897337153723482
Short name T392
Test name
Test status
Simulation time 13059183 ps
CPU time 0.87 seconds
Started Nov 01 02:27:24 PM PDT 23
Finished Nov 01 02:27:39 PM PDT 23
Peak memory 205316 kb
Host smart-c64edaa5-ffd8-4412-80e1-424bf65dc664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73980933277494667187845624782098026469577600267177548119534105897337153723482 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 47.edn_smoke.73980933277494667187845624782098026469577600267177548119534105897337153723482
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.41863276188086956586131671346197316665204798997723427889258393671717247194814
Short name T643
Test name
Test status
Simulation time 154489183 ps
CPU time 3.77 seconds
Started Nov 01 02:27:57 PM PDT 23
Finished Nov 01 02:28:06 PM PDT 23
Peak memory 205956 kb
Host smart-b7fe1f53-414b-4469-8eb5-72a7ef0155cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41863276188086956586131671346197316665204798997723427889258393671717247194814 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.41863276188086956586131671346197316665204798997723427889258393671717247194814
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.79317065845334879129759333052104124792627729283738705599563275328705127823795
Short name T246
Test name
Test status
Simulation time 41708099183 ps
CPU time 1093.62 seconds
Started Nov 01 02:27:11 PM PDT 23
Finished Nov 01 02:45:40 PM PDT 23
Peak memory 215892 kb
Host smart-3ba1647a-cdf6-4554-89bd-820ea976524d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793170658453348791297593330
52104124792627729283738705599563275328705127823795 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.79317065845
334879129759333052104124792627729283738705599563275328705127823795
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.109315313238770095659148839750988811449871717997940700906765089979488423674487
Short name T377
Test name
Test status
Simulation time 18259183 ps
CPU time 1.05 seconds
Started Nov 01 02:27:17 PM PDT 23
Finished Nov 01 02:27:32 PM PDT 23
Peak memory 205636 kb
Host smart-2f58bf33-8f08-4b56-91bb-f5fca9b14fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109315313238770095659148839750988811449871717997940700906765089979488423674487 -assert nopostproc +UVM_TESTNAME=edn_aler
t_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 48.edn_alert.109315313238770095659148839750988811449871717997940700906765089979488423674487
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.43654955165603007497945172230544992511186689931188209037248706118178437310657
Short name T631
Test name
Test status
Simulation time 28184990 ps
CPU time 0.89 seconds
Started Nov 01 02:26:56 PM PDT 23
Finished Nov 01 02:27:06 PM PDT 23
Peak memory 205436 kb
Host smart-9423aae0-2c10-4dd1-9a09-6126afe251e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43654955165603007497945172230544992511186689931188209037248706118178437310657 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.edn_alert_test.43654955165603007497945172230544992511186689931188209037248706118178437310657
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.76542120210436672889821046740427061641167721541629760853251817015461414866724
Short name T408
Test name
Test status
Simulation time 12219183 ps
CPU time 0.9 seconds
Started Nov 01 02:27:05 PM PDT 23
Finished Nov 01 02:27:21 PM PDT 23
Peak memory 214872 kb
Host smart-c8ea65a7-7823-4628-8724-87923d7dc5ec
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76542120210436672889821046740427061641167721541629760853251817015461414866724 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.edn_disable.76542120210436672889821046740427061641167721541629760853251817015461414866724
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.41552614191758689392155905681808516666246651438191758672180842390010409218666
Short name T24
Test name
Test status
Simulation time 17319183 ps
CPU time 0.95 seconds
Started Nov 01 02:26:52 PM PDT 23
Finished Nov 01 02:26:57 PM PDT 23
Peak memory 214936 kb
Host smart-235f0a0f-d80f-4879-bb30-c55a84e09d1b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41552614191758689392155905681808516666246651438191758672180842390010409218666 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable_auto_req_mode.4155261419175868939215590568180851666624665143819175867218
0842390010409218666
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.64708073754692750868922897718005185913284180260776330545114743088893365883139
Short name T961
Test name
Test status
Simulation time 24963823 ps
CPU time 1.2 seconds
Started Nov 01 02:27:18 PM PDT 23
Finished Nov 01 02:27:34 PM PDT 23
Peak memory 230484 kb
Host smart-61a28baf-a1fa-44d3-864c-cb4e83295792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64708073754692750868922897718005185913284180260776330545114743088893365883139 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.edn_err.64708073754692750868922897718005185913284180260776330545114743088893365883139
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.1012537542759190124096139559741737292034020691284700806780686538478217822505
Short name T516
Test name
Test status
Simulation time 17999183 ps
CPU time 1.06 seconds
Started Nov 01 02:27:14 PM PDT 23
Finished Nov 01 02:27:30 PM PDT 23
Peak memory 205876 kb
Host smart-b720b951-4bf1-46b8-86e7-db1051449a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012537542759190124096139559741737292034020691284700806780686538478217822505 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.edn_genbits.1012537542759190124096139559741737292034020691284700806780686538478217822505
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.89577959190911931314867009307637846374977767754981140640604427999169822941758
Short name T604
Test name
Test status
Simulation time 18439183 ps
CPU time 1.22 seconds
Started Nov 01 02:27:29 PM PDT 23
Finished Nov 01 02:27:44 PM PDT 23
Peak memory 222344 kb
Host smart-104ed5d9-21c5-4f83-bdc3-23fd595e2126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89577959190911931314867009307637846374977767754981140640604427999169822941758 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.edn_intr.89577959190911931314867009307637846374977767754981140640604427999169822941758
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.106551503353443562646957374216167464625558688073185999202023106449609254294253
Short name T755
Test name
Test status
Simulation time 13059183 ps
CPU time 0.92 seconds
Started Nov 01 02:27:29 PM PDT 23
Finished Nov 01 02:27:43 PM PDT 23
Peak memory 205376 kb
Host smart-cdfad36b-8b4f-432f-8e30-550fcdc3c543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106551503353443562646957374216167464625558688073185999202023106449609254294253 -assert nopostproc +UVM_TESTNAME=edn_smok
e_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 48.edn_smoke.106551503353443562646957374216167464625558688073185999202023106449609254294253
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.28980866823512805289976976632449385985101630759685212484999729673492354785924
Short name T969
Test name
Test status
Simulation time 154489183 ps
CPU time 4.18 seconds
Started Nov 01 02:27:21 PM PDT 23
Finished Nov 01 02:27:39 PM PDT 23
Peak memory 206448 kb
Host smart-31293357-fa54-4f36-b424-ff0d46a8d712
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28980866823512805289976976632449385985101630759685212484999729673492354785924 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.28980866823512805289976976632449385985101630759685212484999729673492354785924
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.105428165380089197614167495909300551413640943189681103553090099739421695688323
Short name T565
Test name
Test status
Simulation time 41708099183 ps
CPU time 1052.68 seconds
Started Nov 01 02:27:25 PM PDT 23
Finished Nov 01 02:45:12 PM PDT 23
Peak memory 215876 kb
Host smart-70caaa1b-c9bc-404f-9513-05aa8514b38c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105428165380089197614167495
909300551413640943189681103553090099739421695688323 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.1054281653
80089197614167495909300551413640943189681103553090099739421695688323
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.25291649028487876393528234092287112500519465929068388953310734175039099325412
Short name T731
Test name
Test status
Simulation time 18259183 ps
CPU time 1 seconds
Started Nov 01 02:27:05 PM PDT 23
Finished Nov 01 02:27:21 PM PDT 23
Peak memory 205636 kb
Host smart-8363e797-f9eb-4fef-a1be-34e6f13adfda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25291649028487876393528234092287112500519465929068388953310734175039099325412 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 49.edn_alert.25291649028487876393528234092287112500519465929068388953310734175039099325412
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.53924379899428320102230247605793767304979855222689124635521650873463479259192
Short name T855
Test name
Test status
Simulation time 28184990 ps
CPU time 0.86 seconds
Started Nov 01 02:27:20 PM PDT 23
Finished Nov 01 02:27:35 PM PDT 23
Peak memory 205480 kb
Host smart-269e74bd-012b-4935-b742-3477093fc4be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53924379899428320102230247605793767304979855222689124635521650873463479259192 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.edn_alert_test.53924379899428320102230247605793767304979855222689124635521650873463479259192
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.27790544459450157784393874899906143310851322021450004016664138153196655188140
Short name T414
Test name
Test status
Simulation time 12219183 ps
CPU time 0.87 seconds
Started Nov 01 02:26:58 PM PDT 23
Finished Nov 01 02:27:10 PM PDT 23
Peak memory 214500 kb
Host smart-2fd76586-9cc2-44f0-8200-b1d685c78188
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27790544459450157784393874899906143310851322021450004016664138153196655188140 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.edn_disable.27790544459450157784393874899906143310851322021450004016664138153196655188140
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.27499030378295652272627893929475374647370486683257983836482441672623575419703
Short name T339
Test name
Test status
Simulation time 17319183 ps
CPU time 0.92 seconds
Started Nov 01 02:27:00 PM PDT 23
Finished Nov 01 02:27:14 PM PDT 23
Peak memory 214948 kb
Host smart-72851199-f279-45ff-87e1-c8e0c823e6fe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27499030378295652272627893929475374647370486683257983836482441672623575419703 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable_auto_req_mode.2749903037829565227262789392947537464737048668325798383648
2441672623575419703
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.2337053120519639125055453061860893183401794134697013975591451821487350047258
Short name T314
Test name
Test status
Simulation time 24963823 ps
CPU time 1.12 seconds
Started Nov 01 02:27:07 PM PDT 23
Finished Nov 01 02:27:23 PM PDT 23
Peak memory 230492 kb
Host smart-fa622c94-8751-4f2f-a8e5-6b4a1f15ade8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337053120519639125055453061860893183401794134697013975591451821487350047258 -assert nopostproc +UVM_TESTNAME=edn_err_te
st +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
edn_err.2337053120519639125055453061860893183401794134697013975591451821487350047258
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.40154442958379180883558283151915919539028620034312113036655874308103599048548
Short name T803
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:26:51 PM PDT 23
Finished Nov 01 02:26:55 PM PDT 23
Peak memory 205840 kb
Host smart-b3054e30-2a11-4fc0-be29-6a02dca1bbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40154442958379180883558283151915919539028620034312113036655874308103599048548 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.edn_genbits.40154442958379180883558283151915919539028620034312113036655874308103599048548
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.89811849978106553564973354886438683189413944187727973787407957783576189692026
Short name T923
Test name
Test status
Simulation time 18439183 ps
CPU time 1.15 seconds
Started Nov 01 02:26:55 PM PDT 23
Finished Nov 01 02:27:05 PM PDT 23
Peak memory 222320 kb
Host smart-7a9b6160-cd31-4508-9387-3b768987f030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89811849978106553564973354886438683189413944187727973787407957783576189692026 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.edn_intr.89811849978106553564973354886438683189413944187727973787407957783576189692026
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.69060036610382062046644448406971796426953351650809151754103425567299888230578
Short name T669
Test name
Test status
Simulation time 13059183 ps
CPU time 0.91 seconds
Started Nov 01 02:26:51 PM PDT 23
Finished Nov 01 02:26:54 PM PDT 23
Peak memory 205436 kb
Host smart-ffd30af1-35fc-476a-870d-c465b90ca097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69060036610382062046644448406971796426953351650809151754103425567299888230578 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 49.edn_smoke.69060036610382062046644448406971796426953351650809151754103425567299888230578
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.72759866844116038997134920797723916790514952655330387287051575610214928993922
Short name T281
Test name
Test status
Simulation time 154489183 ps
CPU time 4.1 seconds
Started Nov 01 02:26:56 PM PDT 23
Finished Nov 01 02:27:10 PM PDT 23
Peak memory 206536 kb
Host smart-69a31d8c-01bf-4720-b113-2943a89551c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72759866844116038997134920797723916790514952655330387287051575610214928993922 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.72759866844116038997134920797723916790514952655330387287051575610214928993922
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.60705161356199598740301338170783193511505897575693552658344706388699339272399
Short name T356
Test name
Test status
Simulation time 41708099183 ps
CPU time 1081.12 seconds
Started Nov 01 02:26:55 PM PDT 23
Finished Nov 01 02:45:04 PM PDT 23
Peak memory 216032 kb
Host smart-76888d3a-251e-470b-a4db-d864593d141a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607051613561995987403013381
70783193511505897575693552658344706388699339272399 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.60705161356
199598740301338170783193511505897575693552658344706388699339272399
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.96740253276857160725483241283284736664065392710466724029320547156240154874135
Short name T768
Test name
Test status
Simulation time 18259183 ps
CPU time 0.98 seconds
Started Nov 01 02:26:39 PM PDT 23
Finished Nov 01 02:26:44 PM PDT 23
Peak memory 205524 kb
Host smart-d12b8c18-881c-4dd2-b497-be9edac7af8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96740253276857160725483241283284736664065392710466724029320547156240154874135 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.edn_alert.96740253276857160725483241283284736664065392710466724029320547156240154874135
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.86206822451486141243514116447939103408922010185929766988587215787810763754747
Short name T347
Test name
Test status
Simulation time 28184990 ps
CPU time 0.93 seconds
Started Nov 01 02:26:37 PM PDT 23
Finished Nov 01 02:26:40 PM PDT 23
Peak memory 205500 kb
Host smart-adc226b5-36db-4543-8f85-4da70aa9b7a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86206822451486141243514116447939103408922010185929766988587215787810763754747 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.edn_alert_test.86206822451486141243514116447939103408922010185929766988587215787810763754747
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.115610685171010844515425946095409108699109261447582617077405636644869842230040
Short name T374
Test name
Test status
Simulation time 12219183 ps
CPU time 0.91 seconds
Started Nov 01 02:26:41 PM PDT 23
Finished Nov 01 02:26:46 PM PDT 23
Peak memory 214864 kb
Host smart-ef76386d-9339-4534-b3d0-d65dd4c55ef0
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115610685171010844515425946095409108699109261447582617077405636644869842230040 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 5.edn_disable.115610685171010844515425946095409108699109261447582617077405636644869842230040
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.67340813459363620085370770494977732682669764375760586811334249758232839812534
Short name T664
Test name
Test status
Simulation time 17319183 ps
CPU time 0.92 seconds
Started Nov 01 02:26:41 PM PDT 23
Finished Nov 01 02:26:46 PM PDT 23
Peak memory 214840 kb
Host smart-5213829b-5579-44c8-a503-9ccfe5f033d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67340813459363620085370770494977732682669764375760586811334249758232839812534 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable_auto_req_mode.67340813459363620085370770494977732682669764375760586811334
249758232839812534
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.11102957185715852039102025871476269479542034394680721952728896700195708096174
Short name T298
Test name
Test status
Simulation time 24963823 ps
CPU time 1.15 seconds
Started Nov 01 02:26:41 PM PDT 23
Finished Nov 01 02:26:47 PM PDT 23
Peak memory 230356 kb
Host smart-bb127826-13ae-4ffe-8f5c-9c37575bc3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11102957185715852039102025871476269479542034394680721952728896700195708096174 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
edn_err.11102957185715852039102025871476269479542034394680721952728896700195708096174
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.73175101393858996168607542873799693286777380838974088671218678003515973820288
Short name T914
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 01 02:26:30 PM PDT 23
Finished Nov 01 02:26:33 PM PDT 23
Peak memory 205936 kb
Host smart-8abf2f4d-02a0-4946-904b-793602ca56b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73175101393858996168607542873799693286777380838974088671218678003515973820288 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.edn_genbits.73175101393858996168607542873799693286777380838974088671218678003515973820288
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.32840032517903330225365726019615203621550631443378239607561208307191608088414
Short name T483
Test name
Test status
Simulation time 18439183 ps
CPU time 1.14 seconds
Started Nov 01 02:26:52 PM PDT 23
Finished Nov 01 02:26:58 PM PDT 23
Peak memory 222312 kb
Host smart-77555406-1486-43b1-80a0-330d09b92ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32840032517903330225365726019615203621550631443378239607561208307191608088414 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.edn_intr.32840032517903330225365726019615203621550631443378239607561208307191608088414
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.105941665015059416750315817260602802620953260045563315104137190415007814660046
Short name T650
Test name
Test status
Simulation time 11759183 ps
CPU time 0.85 seconds
Started Nov 01 02:25:55 PM PDT 23
Finished Nov 01 02:26:06 PM PDT 23
Peak memory 205360 kb
Host smart-122677ee-9041-4225-b904-2b0fa098587d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105941665015059416750315817260602802620953260045563315104137190415007814660046 -assert nopostproc +UVM_TESTNAME=edn_smok
e_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 5.edn_regwen.105941665015059416750315817260602802620953260045563315104137190415007814660046
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.10695388146327691662459874410511842306342022752467384910848655212140527873767
Short name T881
Test name
Test status
Simulation time 13059183 ps
CPU time 0.91 seconds
Started Nov 01 02:26:09 PM PDT 23
Finished Nov 01 02:26:14 PM PDT 23
Peak memory 205440 kb
Host smart-977d369b-7ab8-48cf-8df2-4973497764de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10695388146327691662459874410511842306342022752467384910848655212140527873767 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.edn_smoke.10695388146327691662459874410511842306342022752467384910848655212140527873767
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.49456109361423058509093658393426006566228659416895859537990268572117907227817
Short name T573
Test name
Test status
Simulation time 154489183 ps
CPU time 4.02 seconds
Started Nov 01 02:26:35 PM PDT 23
Finished Nov 01 02:26:41 PM PDT 23
Peak memory 206328 kb
Host smart-50c98cdb-c7d3-4e45-9f78-b8670be1b4fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49456109361423058509093658393426006566228659416895859537990268572117907227817 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.49456109361423058509093658393426006566228659416895859537990268572117907227817
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.57669555072270624483961288496246465865571267240334150013870894466862429771
Short name T970
Test name
Test status
Simulation time 41708099183 ps
CPU time 1061.53 seconds
Started Nov 01 02:27:04 PM PDT 23
Finished Nov 01 02:45:01 PM PDT 23
Peak memory 215920 kb
Host smart-600fca3d-733a-48d5-bb6c-99c2811436b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576695550722706244839612884
96246465865571267240334150013870894466862429771 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.576695550722706
24483961288496246465865571267240334150013870894466862429771
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.94693646664491119961660331250969635582420805072063364909328143310933333953113
Short name T87
Test name
Test status
Simulation time 24963823 ps
CPU time 1.12 seconds
Started Nov 01 02:26:59 PM PDT 23
Finished Nov 01 02:27:12 PM PDT 23
Peak memory 230544 kb
Host smart-8229d6b1-a387-4156-8c72-cab747d8921e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94693646664491119961660331250969635582420805072063364909328143310933333953113 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50
.edn_err.94693646664491119961660331250969635582420805072063364909328143310933333953113
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.75150263013416970250094135094991248156883473701889146806816850426252156922434
Short name T928
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 01 02:27:22 PM PDT 23
Finished Nov 01 02:27:37 PM PDT 23
Peak memory 205864 kb
Host smart-92ccd439-c520-444c-b9c0-fcd5d5920f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75150263013416970250094135094991248156883473701889146806816850426252156922434 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 50.edn_genbits.75150263013416970250094135094991248156883473701889146806816850426252156922434
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.49195464887480719000340386135332418016248083611930017435777471496127923789889
Short name T943
Test name
Test status
Simulation time 24963823 ps
CPU time 1.16 seconds
Started Nov 01 02:27:00 PM PDT 23
Finished Nov 01 02:27:14 PM PDT 23
Peak memory 230544 kb
Host smart-9fefa3b9-7311-4a0c-91f7-6be411e0a326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49195464887480719000340386135332418016248083611930017435777471496127923789889 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51
.edn_err.49195464887480719000340386135332418016248083611930017435777471496127923789889
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.5557969586691116196340183028612531355279943898756640596855348416115043769768
Short name T303
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Nov 01 02:27:14 PM PDT 23
Finished Nov 01 02:27:30 PM PDT 23
Peak memory 205860 kb
Host smart-78a8c079-d348-44bf-ab82-7b1501429742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5557969586691116196340183028612531355279943898756640596855348416115043769768 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 51.edn_genbits.5557969586691116196340183028612531355279943898756640596855348416115043769768
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.66386027713670842047356045284749322267980834981823274622717781993683532027081
Short name T495
Test name
Test status
Simulation time 24963823 ps
CPU time 1.14 seconds
Started Nov 01 02:27:21 PM PDT 23
Finished Nov 01 02:27:36 PM PDT 23
Peak memory 230464 kb
Host smart-f31baa27-4329-4c46-9226-6f6ac5367475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66386027713670842047356045284749322267980834981823274622717781993683532027081 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52
.edn_err.66386027713670842047356045284749322267980834981823274622717781993683532027081
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.100775272706978419238966102796554040753439497183558679739435352282227505421239
Short name T847
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 01 02:27:16 PM PDT 23
Finished Nov 01 02:27:31 PM PDT 23
Peak memory 205856 kb
Host smart-8dc497d3-b23e-4437-91bf-9d884b9dcb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100775272706978419238966102796554040753439497183558679739435352282227505421239 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 52.edn_genbits.100775272706978419238966102796554040753439497183558679739435352282227505421239
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.79304280848644482261191353808590432638971883088587047800785932025574096924885
Short name T545
Test name
Test status
Simulation time 24963823 ps
CPU time 1.13 seconds
Started Nov 01 02:27:06 PM PDT 23
Finished Nov 01 02:27:22 PM PDT 23
Peak memory 230532 kb
Host smart-9ec9353b-868a-4888-8652-084e4ce47f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79304280848644482261191353808590432638971883088587047800785932025574096924885 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53
.edn_err.79304280848644482261191353808590432638971883088587047800785932025574096924885
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.56492921359158024253574513565191485361977380518047291563274746239677684990724
Short name T494
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:27:13 PM PDT 23
Finished Nov 01 02:27:29 PM PDT 23
Peak memory 205856 kb
Host smart-195d6730-0f31-458d-822b-c2114628aaf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56492921359158024253574513565191485361977380518047291563274746239677684990724 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 53.edn_genbits.56492921359158024253574513565191485361977380518047291563274746239677684990724
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.98932587223836073516362142712951911748232232883910358627276539913339688359543
Short name T959
Test name
Test status
Simulation time 24963823 ps
CPU time 1.14 seconds
Started Nov 01 02:26:57 PM PDT 23
Finished Nov 01 02:27:09 PM PDT 23
Peak memory 230528 kb
Host smart-b5364fd6-668e-4f9f-8c7e-768093b8de7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98932587223836073516362142712951911748232232883910358627276539913339688359543 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54
.edn_err.98932587223836073516362142712951911748232232883910358627276539913339688359543
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.54333702650949138019784186244731601998987220994280382226839242693798333585757
Short name T899
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 01 02:27:12 PM PDT 23
Finished Nov 01 02:27:29 PM PDT 23
Peak memory 205896 kb
Host smart-5b6927b7-ac48-4580-8b2a-9ae937fe59c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54333702650949138019784186244731601998987220994280382226839242693798333585757 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 54.edn_genbits.54333702650949138019784186244731601998987220994280382226839242693798333585757
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.42773157048474816094000971831701628550855334751826290415935587022426692123325
Short name T53
Test name
Test status
Simulation time 24963823 ps
CPU time 1.12 seconds
Started Nov 01 02:27:10 PM PDT 23
Finished Nov 01 02:27:26 PM PDT 23
Peak memory 230496 kb
Host smart-7cc7cecc-b09d-4ad1-a62d-3a5740b63d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42773157048474816094000971831701628550855334751826290415935587022426692123325 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55
.edn_err.42773157048474816094000971831701628550855334751826290415935587022426692123325
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.15279695318411852191701133798525760852326560860422904695783730681430747400507
Short name T566
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 01 02:27:04 PM PDT 23
Finished Nov 01 02:27:20 PM PDT 23
Peak memory 205924 kb
Host smart-ce479ac7-e34d-48de-9942-5199f31589e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15279695318411852191701133798525760852326560860422904695783730681430747400507 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 55.edn_genbits.15279695318411852191701133798525760852326560860422904695783730681430747400507
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.11758125066764204309132493822780942777832708421854905786509401407791028562694
Short name T295
Test name
Test status
Simulation time 24963823 ps
CPU time 1.16 seconds
Started Nov 01 02:27:05 PM PDT 23
Finished Nov 01 02:27:21 PM PDT 23
Peak memory 230632 kb
Host smart-5bf6ddc3-c31d-455d-92a5-e68ebfeb88d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11758125066764204309132493822780942777832708421854905786509401407791028562694 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56
.edn_err.11758125066764204309132493822780942777832708421854905786509401407791028562694
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.19704346115243055613677462028205936772380000350601817807277392046239577735104
Short name T345
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 01 02:27:25 PM PDT 23
Finished Nov 01 02:27:39 PM PDT 23
Peak memory 205856 kb
Host smart-d021b419-f2bd-431a-8615-031e862bbd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19704346115243055613677462028205936772380000350601817807277392046239577735104 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 56.edn_genbits.19704346115243055613677462028205936772380000350601817807277392046239577735104
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.21077975883369994362875821904136887949206953611198333790464886410292171772136
Short name T425
Test name
Test status
Simulation time 24963823 ps
CPU time 1.11 seconds
Started Nov 01 02:27:09 PM PDT 23
Finished Nov 01 02:27:26 PM PDT 23
Peak memory 230408 kb
Host smart-e9c355f2-48f9-4d4c-a083-92b065263c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21077975883369994362875821904136887949206953611198333790464886410292171772136 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57
.edn_err.21077975883369994362875821904136887949206953611198333790464886410292171772136
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.72551092092230375733174552505631310477677184400796033043148003438940889573265
Short name T662
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 01 02:27:29 PM PDT 23
Finished Nov 01 02:27:44 PM PDT 23
Peak memory 205824 kb
Host smart-fa00d365-4b12-4eab-9bca-9887a550dcc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72551092092230375733174552505631310477677184400796033043148003438940889573265 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 57.edn_genbits.72551092092230375733174552505631310477677184400796033043148003438940889573265
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.19229166026975882238206755068080953038554067610171227719282162477973447508597
Short name T21
Test name
Test status
Simulation time 24963823 ps
CPU time 1.16 seconds
Started Nov 01 02:27:16 PM PDT 23
Finished Nov 01 02:27:31 PM PDT 23
Peak memory 230408 kb
Host smart-db1b6dd8-dd84-446c-8c40-e4484bc7aa1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19229166026975882238206755068080953038554067610171227719282162477973447508597 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58
.edn_err.19229166026975882238206755068080953038554067610171227719282162477973447508597
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.68385041886979913385900551037753566499590844113449730951694307830810008060296
Short name T697
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 01 02:27:13 PM PDT 23
Finished Nov 01 02:27:29 PM PDT 23
Peak memory 205728 kb
Host smart-2c6b4aca-5828-4e0e-8609-f8b53bd5ae8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68385041886979913385900551037753566499590844113449730951694307830810008060296 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 58.edn_genbits.68385041886979913385900551037753566499590844113449730951694307830810008060296
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.28844344661900839489794874282280404683428150428829716318532838207553918520563
Short name T590
Test name
Test status
Simulation time 24963823 ps
CPU time 1.15 seconds
Started Nov 01 02:27:14 PM PDT 23
Finished Nov 01 02:27:30 PM PDT 23
Peak memory 230424 kb
Host smart-eb448efb-38bf-4a32-8922-1e9d0dcb0474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28844344661900839489794874282280404683428150428829716318532838207553918520563 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59
.edn_err.28844344661900839489794874282280404683428150428829716318532838207553918520563
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.67166166321160631932273774025676481412216510273032605804856515185756744648055
Short name T577
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 01 02:27:46 PM PDT 23
Finished Nov 01 02:27:54 PM PDT 23
Peak memory 205860 kb
Host smart-8f73d60e-0ee3-43e0-8b90-602dcc1f59ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67166166321160631932273774025676481412216510273032605804856515185756744648055 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 59.edn_genbits.67166166321160631932273774025676481412216510273032605804856515185756744648055
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.103198655333131719995832138437530015244945635043519169427054403985577075815971
Short name T598
Test name
Test status
Simulation time 18259183 ps
CPU time 1.03 seconds
Started Nov 01 02:26:51 PM PDT 23
Finished Nov 01 02:26:55 PM PDT 23
Peak memory 205596 kb
Host smart-28994e51-5985-478a-9e28-c850ed8491e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103198655333131719995832138437530015244945635043519169427054403985577075815971 -assert nopostproc +UVM_TESTNAME=edn_aler
t_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.edn_alert.103198655333131719995832138437530015244945635043519169427054403985577075815971
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.51729300801722320094867387139972677586095420873548512893758998525562616231245
Short name T578
Test name
Test status
Simulation time 28184990 ps
CPU time 0.88 seconds
Started Nov 01 02:26:44 PM PDT 23
Finished Nov 01 02:26:50 PM PDT 23
Peak memory 205508 kb
Host smart-9d60388c-d39b-4d7f-8f34-cfc93135c048
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51729300801722320094867387139972677586095420873548512893758998525562616231245 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.edn_alert_test.51729300801722320094867387139972677586095420873548512893758998525562616231245
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.37574209991521143041959509935750009864893632655505930035233994522296464071280
Short name T569
Test name
Test status
Simulation time 12219183 ps
CPU time 0.88 seconds
Started Nov 01 02:26:44 PM PDT 23
Finished Nov 01 02:26:50 PM PDT 23
Peak memory 214880 kb
Host smart-fdc6f9c4-a158-4054-b22a-baae6d87abf1
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37574209991521143041959509935750009864893632655505930035233994522296464071280 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.edn_disable.37574209991521143041959509935750009864893632655505930035233994522296464071280
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.41061682036460333788243480186949161305466628123927872640239534448950137783905
Short name T531
Test name
Test status
Simulation time 17319183 ps
CPU time 0.92 seconds
Started Nov 01 02:26:56 PM PDT 23
Finished Nov 01 02:27:07 PM PDT 23
Peak memory 214944 kb
Host smart-09cf376b-19cf-4592-9390-0893d52911d4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41061682036460333788243480186949161305466628123927872640239534448950137783905 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable_auto_req_mode.41061682036460333788243480186949161305466628123927872640239
534448950137783905
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.43531846903989776852329954704673984771920525433015730545046099675353712624988
Short name T597
Test name
Test status
Simulation time 24963823 ps
CPU time 1.15 seconds
Started Nov 01 02:26:51 PM PDT 23
Finished Nov 01 02:26:55 PM PDT 23
Peak memory 230488 kb
Host smart-31321f68-ef3d-41ef-83ee-e533fca705a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43531846903989776852329954704673984771920525433015730545046099675353712624988 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
edn_err.43531846903989776852329954704673984771920525433015730545046099675353712624988
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.50356774340798284758638957359501328067937995380444749457469932706547185381933
Short name T929
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:26:49 PM PDT 23
Finished Nov 01 02:26:53 PM PDT 23
Peak memory 205904 kb
Host smart-1d750045-e530-4f7c-9756-e94684e50c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50356774340798284758638957359501328067937995380444749457469932706547185381933 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.edn_genbits.50356774340798284758638957359501328067937995380444749457469932706547185381933
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.113184873907234269148272902322665602044696722531019535351319797873434032706766
Short name T681
Test name
Test status
Simulation time 18439183 ps
CPU time 1.13 seconds
Started Nov 01 02:26:40 PM PDT 23
Finished Nov 01 02:26:45 PM PDT 23
Peak memory 222352 kb
Host smart-c40eb74a-c8be-4118-b83c-47a21c710481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113184873907234269148272902322665602044696722531019535351319797873434032706766 -assert nopostproc +UVM_TESTNAME=edn_intr
_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.edn_intr.113184873907234269148272902322665602044696722531019535351319797873434032706766
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.102306234225695574041397240952959808132571417145054984029861664682950035035838
Short name T694
Test name
Test status
Simulation time 11759183 ps
CPU time 0.83 seconds
Started Nov 01 02:26:54 PM PDT 23
Finished Nov 01 02:27:01 PM PDT 23
Peak memory 205256 kb
Host smart-b3607601-d44d-49ea-af58-bac503a4468c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102306234225695574041397240952959808132571417145054984029861664682950035035838 -assert nopostproc +UVM_TESTNAME=edn_smok
e_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 6.edn_regwen.102306234225695574041397240952959808132571417145054984029861664682950035035838
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.95691920139922506884799342179680163244650639420585009700256836934759906992615
Short name T732
Test name
Test status
Simulation time 13059183 ps
CPU time 0.88 seconds
Started Nov 01 02:26:44 PM PDT 23
Finished Nov 01 02:26:50 PM PDT 23
Peak memory 205372 kb
Host smart-3e1f8783-ec3a-437c-bdc4-a29157dea639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95691920139922506884799342179680163244650639420585009700256836934759906992615 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.edn_smoke.95691920139922506884799342179680163244650639420585009700256836934759906992615
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.2682329111551857863116795535195720496186854048166424077602578797570369344485
Short name T97
Test name
Test status
Simulation time 154489183 ps
CPU time 4.04 seconds
Started Nov 01 02:26:52 PM PDT 23
Finished Nov 01 02:27:00 PM PDT 23
Peak memory 206444 kb
Host smart-638af8fc-8e64-4040-baa2-1c9e752a198b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682329111551857863116795535195720496186854048166424077602578797570369344485 -assert nopost
proc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.2682329111551857863116795535195720496186854048166424077602578797570369344485
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.11863397896650457722085137086544439853684898646957706075159357648743028435275
Short name T781
Test name
Test status
Simulation time 41708099183 ps
CPU time 1098.36 seconds
Started Nov 01 02:26:39 PM PDT 23
Finished Nov 01 02:45:02 PM PDT 23
Peak memory 215896 kb
Host smart-ff81c345-4c2c-4baf-a143-a7a737638209
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118633978966504577220851370
86544439853684898646957706075159357648743028435275 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.118633978966
50457722085137086544439853684898646957706075159357648743028435275
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.78803454101835653714157928930006195645407358885059743358969042603224054849371
Short name T724
Test name
Test status
Simulation time 24963823 ps
CPU time 1.19 seconds
Started Nov 01 02:27:16 PM PDT 23
Finished Nov 01 02:27:31 PM PDT 23
Peak memory 230344 kb
Host smart-aec1c101-dac6-4994-8d56-bbd918d0f5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78803454101835653714157928930006195645407358885059743358969042603224054849371 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60
.edn_err.78803454101835653714157928930006195645407358885059743358969042603224054849371
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.24693744157788920174159730191378847931810022623216771797028015183309877140853
Short name T790
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:27:18 PM PDT 23
Finished Nov 01 02:27:33 PM PDT 23
Peak memory 205792 kb
Host smart-6956d930-1470-46d7-aeae-d48281f9fc70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24693744157788920174159730191378847931810022623216771797028015183309877140853 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 60.edn_genbits.24693744157788920174159730191378847931810022623216771797028015183309877140853
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.20985225722319586465303414047031606857759097073188527760431006984548628578072
Short name T479
Test name
Test status
Simulation time 24963823 ps
CPU time 1.11 seconds
Started Nov 01 02:28:10 PM PDT 23
Finished Nov 01 02:28:12 PM PDT 23
Peak memory 230312 kb
Host smart-01b807b3-47a6-404b-9f68-7644a7160966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20985225722319586465303414047031606857759097073188527760431006984548628578072 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61
.edn_err.20985225722319586465303414047031606857759097073188527760431006984548628578072
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.93043009981186574482523089510699415303726854062693202215303112603592066568584
Short name T564
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 01 02:27:26 PM PDT 23
Finished Nov 01 02:27:40 PM PDT 23
Peak memory 205448 kb
Host smart-aaa938df-01a5-4688-a987-d8cc906efa15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93043009981186574482523089510699415303726854062693202215303112603592066568584 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 61.edn_genbits.93043009981186574482523089510699415303726854062693202215303112603592066568584
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.45760151504513944165616469742588595597985131898283542994248571733870815002133
Short name T859
Test name
Test status
Simulation time 24963823 ps
CPU time 1.13 seconds
Started Nov 01 02:27:07 PM PDT 23
Finished Nov 01 02:27:27 PM PDT 23
Peak memory 230528 kb
Host smart-a38f8987-676d-4aaa-93d5-fc990b4f9c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45760151504513944165616469742588595597985131898283542994248571733870815002133 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62
.edn_err.45760151504513944165616469742588595597985131898283542994248571733870815002133
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.53066692057185363817002162459614550138468387330879521027491738628320553363224
Short name T398
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:27:23 PM PDT 23
Finished Nov 01 02:27:42 PM PDT 23
Peak memory 205792 kb
Host smart-b2d7ff62-fdcc-466a-8e3c-92d02b688251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53066692057185363817002162459614550138468387330879521027491738628320553363224 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 62.edn_genbits.53066692057185363817002162459614550138468387330879521027491738628320553363224
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.24214652702553151903066064059231627011595540827317022257833523549120726350763
Short name T275
Test name
Test status
Simulation time 24963823 ps
CPU time 1.17 seconds
Started Nov 01 02:27:13 PM PDT 23
Finished Nov 01 02:27:29 PM PDT 23
Peak memory 230528 kb
Host smart-c903e12f-6af8-4fb2-9d51-b4e968d2ec59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24214652702553151903066064059231627011595540827317022257833523549120726350763 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63
.edn_err.24214652702553151903066064059231627011595540827317022257833523549120726350763
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.18183864743032898358816704957405499216671150438642314496808101219530740762516
Short name T453
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:27:20 PM PDT 23
Finished Nov 01 02:27:35 PM PDT 23
Peak memory 205904 kb
Host smart-e9112b7d-f30d-43f7-8bc7-80f887c9d9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18183864743032898358816704957405499216671150438642314496808101219530740762516 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 63.edn_genbits.18183864743032898358816704957405499216671150438642314496808101219530740762516
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.50058770188812635361963969383889673229368817913274512979903245470840595487361
Short name T20
Test name
Test status
Simulation time 24963823 ps
CPU time 1.11 seconds
Started Nov 01 02:27:58 PM PDT 23
Finished Nov 01 02:28:04 PM PDT 23
Peak memory 230024 kb
Host smart-f277c327-a297-4a65-99e4-d9e28419fca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50058770188812635361963969383889673229368817913274512979903245470840595487361 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64
.edn_err.50058770188812635361963969383889673229368817913274512979903245470840595487361
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.69663978196537188921552598987754043049566381221829015837343537761397366318950
Short name T660
Test name
Test status
Simulation time 17999183 ps
CPU time 1.16 seconds
Started Nov 01 02:27:28 PM PDT 23
Finished Nov 01 02:27:43 PM PDT 23
Peak memory 205840 kb
Host smart-a573bb69-be09-4132-a426-826deff1e57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69663978196537188921552598987754043049566381221829015837343537761397366318950 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 64.edn_genbits.69663978196537188921552598987754043049566381221829015837343537761397366318950
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.39611828761823357934131613544804489631555056822999415508909412638846086764214
Short name T599
Test name
Test status
Simulation time 24963823 ps
CPU time 1.12 seconds
Started Nov 01 02:27:07 PM PDT 23
Finished Nov 01 02:27:23 PM PDT 23
Peak memory 230500 kb
Host smart-f6a6afbe-a20e-4f22-bb8e-84fe29b599d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39611828761823357934131613544804489631555056822999415508909412638846086764214 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65
.edn_err.39611828761823357934131613544804489631555056822999415508909412638846086764214
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.93651493740371521638849638417157630250260935946511128262575804223207818117267
Short name T695
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 01 02:27:10 PM PDT 23
Finished Nov 01 02:27:26 PM PDT 23
Peak memory 205880 kb
Host smart-2cadd9c9-1383-4b75-adb4-5c13def957f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93651493740371521638849638417157630250260935946511128262575804223207818117267 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 65.edn_genbits.93651493740371521638849638417157630250260935946511128262575804223207818117267
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.57697561237725585339777167909143781654558383420400187279179755245356872743236
Short name T291
Test name
Test status
Simulation time 24963823 ps
CPU time 1.16 seconds
Started Nov 01 02:27:54 PM PDT 23
Finished Nov 01 02:27:59 PM PDT 23
Peak memory 228696 kb
Host smart-8a0a4ad3-15a4-4669-afd5-1af0a741b226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57697561237725585339777167909143781654558383420400187279179755245356872743236 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66
.edn_err.57697561237725585339777167909143781654558383420400187279179755245356872743236
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.109106068323869429001673952943401781066550436715746733960685061556879065290722
Short name T539
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:27:35 PM PDT 23
Finished Nov 01 02:27:47 PM PDT 23
Peak memory 205908 kb
Host smart-11de46e4-050c-4f70-a4b4-b95d79fe8ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109106068323869429001673952943401781066550436715746733960685061556879065290722 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 66.edn_genbits.109106068323869429001673952943401781066550436715746733960685061556879065290722
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.50475190660604125451194153231742345189545564204307883262497480356603106424718
Short name T19
Test name
Test status
Simulation time 24963823 ps
CPU time 1.14 seconds
Started Nov 01 02:27:22 PM PDT 23
Finished Nov 01 02:27:36 PM PDT 23
Peak memory 230548 kb
Host smart-84ab13ca-850a-45ab-a494-604089c29e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50475190660604125451194153231742345189545564204307883262497480356603106424718 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67
.edn_err.50475190660604125451194153231742345189545564204307883262497480356603106424718
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.10968920584412814949992003937286888142226107203271568322473177802995996616026
Short name T525
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 01 02:27:34 PM PDT 23
Finished Nov 01 02:27:47 PM PDT 23
Peak memory 205840 kb
Host smart-69a55186-0f79-4ff3-ba59-fb677f4ac44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10968920584412814949992003937286888142226107203271568322473177802995996616026 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 67.edn_genbits.10968920584412814949992003937286888142226107203271568322473177802995996616026
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.12063460349545215115120788990398573835064366958130302622612756285091233119513
Short name T799
Test name
Test status
Simulation time 24963823 ps
CPU time 1.2 seconds
Started Nov 01 02:26:53 PM PDT 23
Finished Nov 01 02:26:59 PM PDT 23
Peak memory 230476 kb
Host smart-f029c863-16b4-4209-ad66-04190e3031a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12063460349545215115120788990398573835064366958130302622612756285091233119513 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68
.edn_err.12063460349545215115120788990398573835064366958130302622612756285091233119513
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.109943489581057341117054247702450802298524170135463090237053570814166822222957
Short name T312
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 01 02:27:30 PM PDT 23
Finished Nov 01 02:27:45 PM PDT 23
Peak memory 205800 kb
Host smart-082a7eb9-234d-45e7-9267-46f6985e53a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109943489581057341117054247702450802298524170135463090237053570814166822222957 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 68.edn_genbits.109943489581057341117054247702450802298524170135463090237053570814166822222957
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.46021506887924143624232657559069516731542463610272976438069119314643506870079
Short name T501
Test name
Test status
Simulation time 24963823 ps
CPU time 1.14 seconds
Started Nov 01 02:27:00 PM PDT 23
Finished Nov 01 02:27:13 PM PDT 23
Peak memory 230536 kb
Host smart-ad81028b-6d49-4113-b9b5-c994d61989b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46021506887924143624232657559069516731542463610272976438069119314643506870079 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69
.edn_err.46021506887924143624232657559069516731542463610272976438069119314643506870079
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.66560289355729695779674127560742218966597547529425784555041957206846691945287
Short name T792
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:26:56 PM PDT 23
Finished Nov 01 02:27:06 PM PDT 23
Peak memory 205992 kb
Host smart-c7e30b5d-f851-494f-8808-2d16c420a217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66560289355729695779674127560742218966597547529425784555041957206846691945287 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 69.edn_genbits.66560289355729695779674127560742218966597547529425784555041957206846691945287
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.67885406846758170283355852340489463931068416744361928058484131659714626677284
Short name T299
Test name
Test status
Simulation time 18259183 ps
CPU time 0.97 seconds
Started Nov 01 02:26:01 PM PDT 23
Finished Nov 01 02:26:08 PM PDT 23
Peak memory 205536 kb
Host smart-af2328dc-3b34-4a6e-a89c-1dc38ad26714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67885406846758170283355852340489463931068416744361928058484131659714626677284 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.edn_alert.67885406846758170283355852340489463931068416744361928058484131659714626677284
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.35333126174872388963853359275197809606431844726331656204118190779378482496928
Short name T274
Test name
Test status
Simulation time 28184990 ps
CPU time 0.87 seconds
Started Nov 01 02:25:52 PM PDT 23
Finished Nov 01 02:25:58 PM PDT 23
Peak memory 205516 kb
Host smart-969363df-67bb-405c-9b80-53bec0557037
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35333126174872388963853359275197809606431844726331656204118190779378482496928 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.edn_alert_test.35333126174872388963853359275197809606431844726331656204118190779378482496928
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.13873510607048373793776569422051005059430197851689007061447643290774580631108
Short name T592
Test name
Test status
Simulation time 12219183 ps
CPU time 0.86 seconds
Started Nov 01 02:25:53 PM PDT 23
Finished Nov 01 02:25:59 PM PDT 23
Peak memory 214944 kb
Host smart-b70c292f-bd9c-4e1e-9429-417f2c88c567
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13873510607048373793776569422051005059430197851689007061447643290774580631108 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.edn_disable.13873510607048373793776569422051005059430197851689007061447643290774580631108
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.78169797045592047605798364729325400313325497420246061623006041933588337756764
Short name T786
Test name
Test status
Simulation time 17319183 ps
CPU time 0.93 seconds
Started Nov 01 02:26:50 PM PDT 23
Finished Nov 01 02:26:53 PM PDT 23
Peak memory 214928 kb
Host smart-cb6d9722-ec9f-4126-a50c-0d781e9c6294
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78169797045592047605798364729325400313325497420246061623006041933588337756764 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable_auto_req_mode.78169797045592047605798364729325400313325497420246061623006
041933588337756764
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.44816004468850099686984313959410682204067404093562124895856573317431423125634
Short name T675
Test name
Test status
Simulation time 24963823 ps
CPU time 1.14 seconds
Started Nov 01 02:25:52 PM PDT 23
Finished Nov 01 02:25:58 PM PDT 23
Peak memory 230500 kb
Host smart-9538bc19-36de-4cb9-bca1-80259d0ed5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44816004468850099686984313959410682204067404093562124895856573317431423125634 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
edn_err.44816004468850099686984313959410682204067404093562124895856573317431423125634
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.81815956809205214482075029565460502938722739776957273503323658348865275994976
Short name T735
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 01 02:26:56 PM PDT 23
Finished Nov 01 02:27:07 PM PDT 23
Peak memory 205832 kb
Host smart-2b0f6b91-2604-4fad-97ab-f11e8bbdec7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81815956809205214482075029565460502938722739776957273503323658348865275994976 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.edn_genbits.81815956809205214482075029565460502938722739776957273503323658348865275994976
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.25184393829427186245925152764001073396888196639352404827810127426513444219594
Short name T500
Test name
Test status
Simulation time 18439183 ps
CPU time 1.1 seconds
Started Nov 01 02:26:52 PM PDT 23
Finished Nov 01 02:26:58 PM PDT 23
Peak memory 222344 kb
Host smart-59613965-a63b-42a5-b596-e01f5b462bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25184393829427186245925152764001073396888196639352404827810127426513444219594 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.edn_intr.25184393829427186245925152764001073396888196639352404827810127426513444219594
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.101494878908274745250334671664465858879021944205936687031383801106936346785921
Short name T401
Test name
Test status
Simulation time 11759183 ps
CPU time 0.85 seconds
Started Nov 01 02:27:16 PM PDT 23
Finished Nov 01 02:27:31 PM PDT 23
Peak memory 205276 kb
Host smart-2c15504b-3665-474c-bca2-0af14befd145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101494878908274745250334671664465858879021944205936687031383801106936346785921 -assert nopostproc +UVM_TESTNAME=edn_smok
e_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 7.edn_regwen.101494878908274745250334671664465858879021944205936687031383801106936346785921
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.11548393898355521940952601558353252297436324045092980647690072189787573521919
Short name T762
Test name
Test status
Simulation time 13059183 ps
CPU time 0.9 seconds
Started Nov 01 02:26:51 PM PDT 23
Finished Nov 01 02:26:54 PM PDT 23
Peak memory 205392 kb
Host smart-774289a8-9aaa-4896-8094-5ae41fec068c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11548393898355521940952601558353252297436324045092980647690072189787573521919 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.edn_smoke.11548393898355521940952601558353252297436324045092980647690072189787573521919
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.51693013808067786041916309997774518419578285680333606085642930097494063896439
Short name T971
Test name
Test status
Simulation time 154489183 ps
CPU time 3.89 seconds
Started Nov 01 02:27:02 PM PDT 23
Finished Nov 01 02:27:20 PM PDT 23
Peak memory 206332 kb
Host smart-55c080f0-add0-452c-a403-14f44647cd3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51693013808067786041916309997774518419578285680333606085642930097494063896439 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.51693013808067786041916309997774518419578285680333606085642930097494063896439
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.100208030351975636964362071582636876034621322547065677346182374154158527802977
Short name T543
Test name
Test status
Simulation time 41708099183 ps
CPU time 1104.53 seconds
Started Nov 01 02:26:20 PM PDT 23
Finished Nov 01 02:44:48 PM PDT 23
Peak memory 215896 kb
Host smart-5334205f-78ca-4729-81d1-a454dd9e13ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100208030351975636964362071
582636876034621322547065677346182374154158527802977 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.10020803035
1975636964362071582636876034621322547065677346182374154158527802977
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.67581457344197168030813124704496979541601653442071988375527442820389926813105
Short name T562
Test name
Test status
Simulation time 24963823 ps
CPU time 1.16 seconds
Started Nov 01 02:27:02 PM PDT 23
Finished Nov 01 02:27:18 PM PDT 23
Peak memory 230444 kb
Host smart-f4c66a38-cb4e-48e3-b63c-ca56cf860d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67581457344197168030813124704496979541601653442071988375527442820389926813105 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70
.edn_err.67581457344197168030813124704496979541601653442071988375527442820389926813105
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.96656933732122610928281376187809127603527622228155165399226500115253005908911
Short name T301
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:27:05 PM PDT 23
Finished Nov 01 02:27:21 PM PDT 23
Peak memory 205908 kb
Host smart-0ba66798-2416-4b06-b6cf-bfd9c687f5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96656933732122610928281376187809127603527622228155165399226500115253005908911 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 70.edn_genbits.96656933732122610928281376187809127603527622228155165399226500115253005908911
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.433633122588846892568903500075227785218108137643621910934163099716588711983
Short name T515
Test name
Test status
Simulation time 24963823 ps
CPU time 1.17 seconds
Started Nov 01 02:27:24 PM PDT 23
Finished Nov 01 02:27:38 PM PDT 23
Peak memory 230496 kb
Host smart-be7aaf7a-fc53-4b98-ad11-caa7937512c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433633122588846892568903500075227785218108137643621910934163099716588711983 -assert nopostproc +UVM_TESTNAME=edn_err_tes
t +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.e
dn_err.433633122588846892568903500075227785218108137643621910934163099716588711983
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.97366441135546250985123334611590218987605650825743490454505950363921019910902
Short name T560
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 01 02:27:07 PM PDT 23
Finished Nov 01 02:27:23 PM PDT 23
Peak memory 205904 kb
Host smart-fcb5221a-f16e-457a-8746-0793a5da47c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97366441135546250985123334611590218987605650825743490454505950363921019910902 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 71.edn_genbits.97366441135546250985123334611590218987605650825743490454505950363921019910902
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.41409257766373644432842042885289726089240184305975827742060082269633254279833
Short name T608
Test name
Test status
Simulation time 24963823 ps
CPU time 1.12 seconds
Started Nov 01 02:27:10 PM PDT 23
Finished Nov 01 02:27:31 PM PDT 23
Peak memory 230496 kb
Host smart-ab6cdc22-8426-4e61-a226-ac2c39af6e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41409257766373644432842042885289726089240184305975827742060082269633254279833 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72
.edn_err.41409257766373644432842042885289726089240184305975827742060082269633254279833
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.70545019785016592664907263479234692497566365745738701632156526483995735827553
Short name T558
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 01 02:26:56 PM PDT 23
Finished Nov 01 02:27:05 PM PDT 23
Peak memory 205716 kb
Host smart-6c5f495e-b06b-4a4e-bcf9-99b7154e26c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70545019785016592664907263479234692497566365745738701632156526483995735827553 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 72.edn_genbits.70545019785016592664907263479234692497566365745738701632156526483995735827553
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.68246883439333002855143649878372826133284903187243603808562543026632060194016
Short name T362
Test name
Test status
Simulation time 24963823 ps
CPU time 1.18 seconds
Started Nov 01 02:27:11 PM PDT 23
Finished Nov 01 02:27:27 PM PDT 23
Peak memory 230524 kb
Host smart-8548cba0-044c-4914-8986-b6f5345814c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68246883439333002855143649878372826133284903187243603808562543026632060194016 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73
.edn_err.68246883439333002855143649878372826133284903187243603808562543026632060194016
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.112313696970892783579718558816185157742099359815747609196807075003367262446056
Short name T283
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 01 02:27:15 PM PDT 23
Finished Nov 01 02:27:30 PM PDT 23
Peak memory 205852 kb
Host smart-509cf078-92e6-4d4f-bd6b-52abe97455cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112313696970892783579718558816185157742099359815747609196807075003367262446056 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 73.edn_genbits.112313696970892783579718558816185157742099359815747609196807075003367262446056
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.42980697146392885085010015324651659262432904613250060763651912429564240368078
Short name T441
Test name
Test status
Simulation time 24963823 ps
CPU time 1.14 seconds
Started Nov 01 02:27:14 PM PDT 23
Finished Nov 01 02:27:30 PM PDT 23
Peak memory 230392 kb
Host smart-d9aaf38d-95f8-4c95-bf8b-22e381186e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42980697146392885085010015324651659262432904613250060763651912429564240368078 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74
.edn_err.42980697146392885085010015324651659262432904613250060763651912429564240368078
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.106065803039564664558863356515607162492322965618090681020022146083419375088808
Short name T610
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 01 02:26:59 PM PDT 23
Finished Nov 01 02:27:12 PM PDT 23
Peak memory 205832 kb
Host smart-153a6430-1afe-4459-a117-09f86730e2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106065803039564664558863356515607162492322965618090681020022146083419375088808 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 74.edn_genbits.106065803039564664558863356515607162492322965618090681020022146083419375088808
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.66713067085150276032880481554281048197628881459791670018936682218216022579261
Short name T892
Test name
Test status
Simulation time 24963823 ps
CPU time 1.15 seconds
Started Nov 01 02:27:17 PM PDT 23
Finished Nov 01 02:27:32 PM PDT 23
Peak memory 230488 kb
Host smart-50ad70a3-4b2d-4dd4-9789-c47c1fa44259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66713067085150276032880481554281048197628881459791670018936682218216022579261 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75
.edn_err.66713067085150276032880481554281048197628881459791670018936682218216022579261
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.106776098005443345161323864661268526353267430408944911554186445122749575333404
Short name T733
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 01 02:27:04 PM PDT 23
Finished Nov 01 02:27:19 PM PDT 23
Peak memory 205908 kb
Host smart-35753f05-9ef0-48b0-8bba-63369fe849a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106776098005443345161323864661268526353267430408944911554186445122749575333404 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 75.edn_genbits.106776098005443345161323864661268526353267430408944911554186445122749575333404
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.70184455304128682693677227926292669815573316431873722298065950908151243064594
Short name T679
Test name
Test status
Simulation time 24963823 ps
CPU time 1.12 seconds
Started Nov 01 02:27:03 PM PDT 23
Finished Nov 01 02:27:18 PM PDT 23
Peak memory 230500 kb
Host smart-0045a24a-8a0f-44e5-8f52-c3359e1e8c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70184455304128682693677227926292669815573316431873722298065950908151243064594 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76
.edn_err.70184455304128682693677227926292669815573316431873722298065950908151243064594
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.49367771827753704773610607232139582507945284567244213496564132393634055298541
Short name T404
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:27:01 PM PDT 23
Finished Nov 01 02:27:17 PM PDT 23
Peak memory 205888 kb
Host smart-15513c1d-c3c0-4f3f-a72a-340b571f76e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49367771827753704773610607232139582507945284567244213496564132393634055298541 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 76.edn_genbits.49367771827753704773610607232139582507945284567244213496564132393634055298541
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.11220940910751987413538453865483986109573525523929382185027796322200554793488
Short name T90
Test name
Test status
Simulation time 24963823 ps
CPU time 1.13 seconds
Started Nov 01 02:27:04 PM PDT 23
Finished Nov 01 02:27:19 PM PDT 23
Peak memory 230532 kb
Host smart-e914855e-d5fd-498d-be00-3a6ef07d5ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11220940910751987413538453865483986109573525523929382185027796322200554793488 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77
.edn_err.11220940910751987413538453865483986109573525523929382185027796322200554793488
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.12592648950751677015176521465960231827263856415015803151539634616728334380089
Short name T775
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 01 02:27:05 PM PDT 23
Finished Nov 01 02:27:22 PM PDT 23
Peak memory 205908 kb
Host smart-0de71f8c-8b9c-4aab-acfd-d68fdd053ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12592648950751677015176521465960231827263856415015803151539634616728334380089 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 77.edn_genbits.12592648950751677015176521465960231827263856415015803151539634616728334380089
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.104152581179369044579559049567653435489485649928136794277062318263392946254241
Short name T858
Test name
Test status
Simulation time 24963823 ps
CPU time 1.16 seconds
Started Nov 01 02:27:08 PM PDT 23
Finished Nov 01 02:27:25 PM PDT 23
Peak memory 230632 kb
Host smart-386dcaf2-001d-43a4-8f1f-77715c195397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104152581179369044579559049567653435489485649928136794277062318263392946254241 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
8.edn_err.104152581179369044579559049567653435489485649928136794277062318263392946254241
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.3121033610052410272045458390788334882760900035315620162609368286588872987722
Short name T265
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:26:56 PM PDT 23
Finished Nov 01 02:27:06 PM PDT 23
Peak memory 206024 kb
Host smart-610d781d-44bc-426e-a41f-eb99ec07845b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121033610052410272045458390788334882760900035315620162609368286588872987722 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 78.edn_genbits.3121033610052410272045458390788334882760900035315620162609368286588872987722
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.67791650753115805843599360567573763939958750919725650440081195384302293893174
Short name T713
Test name
Test status
Simulation time 24963823 ps
CPU time 1.15 seconds
Started Nov 01 02:27:15 PM PDT 23
Finished Nov 01 02:27:31 PM PDT 23
Peak memory 230484 kb
Host smart-9b6fa1e7-29fe-4a2c-b5b7-1ee50b00d7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67791650753115805843599360567573763939958750919725650440081195384302293893174 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79
.edn_err.67791650753115805843599360567573763939958750919725650440081195384302293893174
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.69972186432175984235286405559071888823762226136988791754775655971160370882747
Short name T876
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 01 02:27:09 PM PDT 23
Finished Nov 01 02:27:26 PM PDT 23
Peak memory 205996 kb
Host smart-c0d25024-62ba-434b-85db-487680d0d74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69972186432175984235286405559071888823762226136988791754775655971160370882747 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 79.edn_genbits.69972186432175984235286405559071888823762226136988791754775655971160370882747
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.19289682457984368783918433866699629787447519410724780317571392862346447533183
Short name T884
Test name
Test status
Simulation time 18259183 ps
CPU time 1.01 seconds
Started Nov 01 02:25:53 PM PDT 23
Finished Nov 01 02:26:01 PM PDT 23
Peak memory 205636 kb
Host smart-f40749d0-b6ae-40ba-9963-54989ed33136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19289682457984368783918433866699629787447519410724780317571392862346447533183 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.edn_alert.19289682457984368783918433866699629787447519410724780317571392862346447533183
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.94069708849508966625260948555146370780890758832700231896589931681971931923678
Short name T957
Test name
Test status
Simulation time 28184990 ps
CPU time 0.92 seconds
Started Nov 01 02:26:34 PM PDT 23
Finished Nov 01 02:26:36 PM PDT 23
Peak memory 205528 kb
Host smart-429bb286-2148-450a-b6bb-f8314a163b83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94069708849508966625260948555146370780890758832700231896589931681971931923678 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.edn_alert_test.94069708849508966625260948555146370780890758832700231896589931681971931923678
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.13279145880488507061164982150672690686502707741889608399032735135710530185791
Short name T62
Test name
Test status
Simulation time 12219183 ps
CPU time 0.9 seconds
Started Nov 01 02:26:06 PM PDT 23
Finished Nov 01 02:26:12 PM PDT 23
Peak memory 214928 kb
Host smart-42f8dee7-3720-46d4-aa8b-1bd3b50afb3a
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13279145880488507061164982150672690686502707741889608399032735135710530185791 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.edn_disable.13279145880488507061164982150672690686502707741889608399032735135710530185791
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.37638868522823795067110770480672073580251189719162005358133739310248789764347
Short name T880
Test name
Test status
Simulation time 17319183 ps
CPU time 0.93 seconds
Started Nov 01 02:26:03 PM PDT 23
Finished Nov 01 02:26:08 PM PDT 23
Peak memory 214940 kb
Host smart-11a71c9d-4682-4b7f-9423-8a7b1be67840
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37638868522823795067110770480672073580251189719162005358133739310248789764347 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable_auto_req_mode.37638868522823795067110770480672073580251189719162005358133
739310248789764347
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.80803781439217015376850037490354371903952567800873347239637580850566511859971
Short name T947
Test name
Test status
Simulation time 24963823 ps
CPU time 1.18 seconds
Started Nov 01 02:26:04 PM PDT 23
Finished Nov 01 02:26:08 PM PDT 23
Peak memory 230452 kb
Host smart-99e7c566-982a-4214-a51e-44b3e6f8921d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80803781439217015376850037490354371903952567800873347239637580850566511859971 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
edn_err.80803781439217015376850037490354371903952567800873347239637580850566511859971
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.109086130369089630901049396895583093231561907354547802618756258087989745938600
Short name T770
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 01 02:25:51 PM PDT 23
Finished Nov 01 02:25:58 PM PDT 23
Peak memory 205840 kb
Host smart-bcc8a4f9-96e5-4797-88ba-6b7c59e55f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109086130369089630901049396895583093231561907354547802618756258087989745938600 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 8.edn_genbits.109086130369089630901049396895583093231561907354547802618756258087989745938600
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.19682551014034156216883238407561977079624619919824904998292835271442262925578
Short name T546
Test name
Test status
Simulation time 18439183 ps
CPU time 1.14 seconds
Started Nov 01 02:26:07 PM PDT 23
Finished Nov 01 02:26:13 PM PDT 23
Peak memory 222288 kb
Host smart-e55f309e-4340-4b35-8b08-5724f4f00983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19682551014034156216883238407561977079624619919824904998292835271442262925578 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.edn_intr.19682551014034156216883238407561977079624619919824904998292835271442262925578
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.93276703315387219590455207048496393728702846054756903369373362527960838061554
Short name T767
Test name
Test status
Simulation time 11759183 ps
CPU time 0.89 seconds
Started Nov 01 02:26:36 PM PDT 23
Finished Nov 01 02:26:38 PM PDT 23
Peak memory 205328 kb
Host smart-b9a5fc8d-d039-462b-aa89-d7f53c5c8c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93276703315387219590455207048496393728702846054756903369373362527960838061554 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.edn_regwen.93276703315387219590455207048496393728702846054756903369373362527960838061554
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.76936357303051221386982460522143556488898860407274584929123505664506828655464
Short name T96
Test name
Test status
Simulation time 13059183 ps
CPU time 0.89 seconds
Started Nov 01 02:26:39 PM PDT 23
Finished Nov 01 02:26:43 PM PDT 23
Peak memory 205408 kb
Host smart-719ceed3-bb44-440c-9833-62ae2b997b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76936357303051221386982460522143556488898860407274584929123505664506828655464 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.edn_smoke.76936357303051221386982460522143556488898860407274584929123505664506828655464
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.88625115390763189239679619373168981485474268812281842612805531580793910758796
Short name T743
Test name
Test status
Simulation time 154489183 ps
CPU time 3.95 seconds
Started Nov 01 02:26:36 PM PDT 23
Finished Nov 01 02:26:41 PM PDT 23
Peak memory 206412 kb
Host smart-081ecc01-fe1d-4be4-aab8-05d2e6afff91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88625115390763189239679619373168981485474268812281842612805531580793910758796 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.88625115390763189239679619373168981485474268812281842612805531580793910758796
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.30288729829634542198603467648108281074663045391073448896856828568500511904295
Short name T901
Test name
Test status
Simulation time 41708099183 ps
CPU time 1101.43 seconds
Started Nov 01 02:26:37 PM PDT 23
Finished Nov 01 02:44:59 PM PDT 23
Peak memory 215904 kb
Host smart-8bf3c910-059d-4dbd-963f-5e8d5d9c5ee1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302887298296345421986034676
48108281074663045391073448896856828568500511904295 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.302887298296
34542198603467648108281074663045391073448896856828568500511904295
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.107371304343960376069550309023670174754509112433548340419261761190899985697936
Short name T396
Test name
Test status
Simulation time 24963823 ps
CPU time 1.16 seconds
Started Nov 01 02:27:15 PM PDT 23
Finished Nov 01 02:27:31 PM PDT 23
Peak memory 230496 kb
Host smart-8ac6bd4e-d1e6-4ca7-80af-0a1d5f52356e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107371304343960376069550309023670174754509112433548340419261761190899985697936 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
0.edn_err.107371304343960376069550309023670174754509112433548340419261761190899985697936
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.46269068777817125270420548025605769254800753873838372147904556226647763327839
Short name T542
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 01 02:27:09 PM PDT 23
Finished Nov 01 02:27:26 PM PDT 23
Peak memory 205852 kb
Host smart-5c400c49-2629-4424-b916-17d9ecb838d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46269068777817125270420548025605769254800753873838372147904556226647763327839 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 80.edn_genbits.46269068777817125270420548025605769254800753873838372147904556226647763327839
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.61016732341481577507550876367851477639374813049037111876398506119005509024816
Short name T658
Test name
Test status
Simulation time 24963823 ps
CPU time 1.14 seconds
Started Nov 01 02:27:11 PM PDT 23
Finished Nov 01 02:27:27 PM PDT 23
Peak memory 230452 kb
Host smart-d9d45ce6-ecda-4f9c-9ce9-609187fd089a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61016732341481577507550876367851477639374813049037111876398506119005509024816 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81
.edn_err.61016732341481577507550876367851477639374813049037111876398506119005509024816
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.66970393204514875394558923054549331607931361315700100020733341376884652895328
Short name T563
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:27:13 PM PDT 23
Finished Nov 01 02:27:29 PM PDT 23
Peak memory 205800 kb
Host smart-0344ce45-f1b4-4331-ab4d-71ff8d434f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66970393204514875394558923054549331607931361315700100020733341376884652895328 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 81.edn_genbits.66970393204514875394558923054549331607931361315700100020733341376884652895328
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.81474994807473168165700722815155482702416814417626980070809877447450158891934
Short name T921
Test name
Test status
Simulation time 24963823 ps
CPU time 1.12 seconds
Started Nov 01 02:27:15 PM PDT 23
Finished Nov 01 02:27:30 PM PDT 23
Peak memory 230396 kb
Host smart-6665ccde-fd6f-4ca0-b071-7a3543a8c0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81474994807473168165700722815155482702416814417626980070809877447450158891934 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82
.edn_err.81474994807473168165700722815155482702416814417626980070809877447450158891934
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.94674747601431962808574317048684333100223934203522921772147577002218624611436
Short name T687
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 01 02:27:11 PM PDT 23
Finished Nov 01 02:27:27 PM PDT 23
Peak memory 205728 kb
Host smart-e79b7d33-d187-44b0-8685-5e9ae007656a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94674747601431962808574317048684333100223934203522921772147577002218624611436 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 82.edn_genbits.94674747601431962808574317048684333100223934203522921772147577002218624611436
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.18794254080240302590842507296363666892460932356173504133028506318795632178659
Short name T348
Test name
Test status
Simulation time 24963823 ps
CPU time 1.11 seconds
Started Nov 01 02:27:12 PM PDT 23
Finished Nov 01 02:27:28 PM PDT 23
Peak memory 230500 kb
Host smart-36faa217-8d17-4d58-880e-90c120a8b3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18794254080240302590842507296363666892460932356173504133028506318795632178659 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83
.edn_err.18794254080240302590842507296363666892460932356173504133028506318795632178659
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.91253970084941136061025682470974927913489264529890454186018538994722763124152
Short name T568
Test name
Test status
Simulation time 17999183 ps
CPU time 1.05 seconds
Started Nov 01 02:27:12 PM PDT 23
Finished Nov 01 02:27:28 PM PDT 23
Peak memory 205728 kb
Host smart-5bb9b118-f84d-4574-9345-48f1fe017ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91253970084941136061025682470974927913489264529890454186018538994722763124152 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 83.edn_genbits.91253970084941136061025682470974927913489264529890454186018538994722763124152
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.33546606642802237778632832612974481254845709910698616285027348775943294192587
Short name T363
Test name
Test status
Simulation time 24963823 ps
CPU time 1.14 seconds
Started Nov 01 02:27:18 PM PDT 23
Finished Nov 01 02:27:33 PM PDT 23
Peak memory 230424 kb
Host smart-17f71b7e-f8f0-402a-aa1f-f62f3c39fc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33546606642802237778632832612974481254845709910698616285027348775943294192587 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84
.edn_err.33546606642802237778632832612974481254845709910698616285027348775943294192587
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.71415369150856378693039979128017715116100118133694447087287555592184318818682
Short name T816
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 01 02:27:04 PM PDT 23
Finished Nov 01 02:27:21 PM PDT 23
Peak memory 205892 kb
Host smart-977c95f0-b64f-49a4-bff0-af6f4aa16314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71415369150856378693039979128017715116100118133694447087287555592184318818682 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 84.edn_genbits.71415369150856378693039979128017715116100118133694447087287555592184318818682
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.5534479152922361909831897158840293305357385534309283417815095447475862730061
Short name T88
Test name
Test status
Simulation time 24963823 ps
CPU time 1.12 seconds
Started Nov 01 02:27:15 PM PDT 23
Finished Nov 01 02:27:30 PM PDT 23
Peak memory 230468 kb
Host smart-ac03f6a3-c913-4b8b-9522-8f74479e10a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5534479152922361909831897158840293305357385534309283417815095447475862730061 -assert nopostproc +UVM_TESTNAME=edn_err_te
st +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.
edn_err.5534479152922361909831897158840293305357385534309283417815095447475862730061
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.7865836963315865278086950974370562449046497483855608474048052069609674942280
Short name T793
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 01 02:27:26 PM PDT 23
Finished Nov 01 02:27:40 PM PDT 23
Peak memory 205472 kb
Host smart-e9d324ab-54bf-4a03-a36c-25621f3a786d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7865836963315865278086950974370562449046497483855608474048052069609674942280 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 85.edn_genbits.7865836963315865278086950974370562449046497483855608474048052069609674942280
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.45464500321045066521179872464795064500023287431875863829588945931032825985564
Short name T865
Test name
Test status
Simulation time 24963823 ps
CPU time 1.13 seconds
Started Nov 01 02:27:17 PM PDT 23
Finished Nov 01 02:27:32 PM PDT 23
Peak memory 230412 kb
Host smart-1c27a2c8-f9eb-44eb-b72d-331c780f701f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45464500321045066521179872464795064500023287431875863829588945931032825985564 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86
.edn_err.45464500321045066521179872464795064500023287431875863829588945931032825985564
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.4345120616850152070587495804484251541219506379733336108431623423363568912903
Short name T378
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 01 02:27:25 PM PDT 23
Finished Nov 01 02:27:39 PM PDT 23
Peak memory 205696 kb
Host smart-2576641b-4c22-4f7e-9094-5610a5cdb6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4345120616850152070587495804484251541219506379733336108431623423363568912903 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 86.edn_genbits.4345120616850152070587495804484251541219506379733336108431623423363568912903
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.87688129528856642582511228637423349858096165256064591067308753406450713495693
Short name T668
Test name
Test status
Simulation time 24963823 ps
CPU time 1.16 seconds
Started Nov 01 02:27:24 PM PDT 23
Finished Nov 01 02:27:38 PM PDT 23
Peak memory 230512 kb
Host smart-041d53be-0cad-4017-9df5-d3e17fa4c3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87688129528856642582511228637423349858096165256064591067308753406450713495693 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87
.edn_err.87688129528856642582511228637423349858096165256064591067308753406450713495693
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.58062797057639612574255578047834500784112734295012897044772968683217311873289
Short name T407
Test name
Test status
Simulation time 17999183 ps
CPU time 1.06 seconds
Started Nov 01 02:27:25 PM PDT 23
Finished Nov 01 02:27:39 PM PDT 23
Peak memory 205676 kb
Host smart-64e4d470-1c4c-478a-80c8-3850f5b93da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58062797057639612574255578047834500784112734295012897044772968683217311873289 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 87.edn_genbits.58062797057639612574255578047834500784112734295012897044772968683217311873289
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.69546196977254541942410293326077629923831271301184762385540749314664702060216
Short name T535
Test name
Test status
Simulation time 24963823 ps
CPU time 1.19 seconds
Started Nov 01 02:27:09 PM PDT 23
Finished Nov 01 02:27:26 PM PDT 23
Peak memory 230460 kb
Host smart-a0c52d11-a3d6-4267-a392-9265cad8b937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69546196977254541942410293326077629923831271301184762385540749314664702060216 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88
.edn_err.69546196977254541942410293326077629923831271301184762385540749314664702060216
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.21472648086197213667146823994223367960414109863157110133161221287968695591529
Short name T86
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 01 02:27:32 PM PDT 23
Finished Nov 01 02:27:46 PM PDT 23
Peak memory 205880 kb
Host smart-4afac3a1-615c-4a99-8a4e-5ff68d36b6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21472648086197213667146823994223367960414109863157110133161221287968695591529 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 88.edn_genbits.21472648086197213667146823994223367960414109863157110133161221287968695591529
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.8487882871080120813041223137073106239870968923973056915805983344568446828479
Short name T843
Test name
Test status
Simulation time 24963823 ps
CPU time 1.17 seconds
Started Nov 01 02:27:13 PM PDT 23
Finished Nov 01 02:27:30 PM PDT 23
Peak memory 230432 kb
Host smart-887f367d-1061-4228-97fe-6de8b168dd3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8487882871080120813041223137073106239870968923973056915805983344568446828479 -assert nopostproc +UVM_TESTNAME=edn_err_te
st +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.
edn_err.8487882871080120813041223137073106239870968923973056915805983344568446828479
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.90409120589884821541198167592338176571163602170791765337996815447524309350243
Short name T40
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Nov 01 02:27:54 PM PDT 23
Finished Nov 01 02:27:59 PM PDT 23
Peak memory 204136 kb
Host smart-9e9c8291-c89a-436e-9331-b18fb6887be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90409120589884821541198167592338176571163602170791765337996815447524309350243 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 89.edn_genbits.90409120589884821541198167592338176571163602170791765337996815447524309350243
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.97811626968104137959130338658918102321048178554365778608755962233228313405351
Short name T360
Test name
Test status
Simulation time 18259183 ps
CPU time 0.98 seconds
Started Nov 01 02:26:40 PM PDT 23
Finished Nov 01 02:26:45 PM PDT 23
Peak memory 205592 kb
Host smart-48a72499-5756-4453-93d8-d7e921136a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97811626968104137959130338658918102321048178554365778608755962233228313405351 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.edn_alert.97811626968104137959130338658918102321048178554365778608755962233228313405351
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.69298428045660065975146543641125251228902948925869606297471550932238706093219
Short name T926
Test name
Test status
Simulation time 28184990 ps
CPU time 0.87 seconds
Started Nov 01 02:26:40 PM PDT 23
Finished Nov 01 02:26:45 PM PDT 23
Peak memory 205512 kb
Host smart-989bdd86-bf10-402c-9613-56395076d79c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69298428045660065975146543641125251228902948925869606297471550932238706093219 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.edn_alert_test.69298428045660065975146543641125251228902948925869606297471550932238706093219
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.59227311159309747790194960037024438307647706041584204221228094281853272855949
Short name T736
Test name
Test status
Simulation time 12219183 ps
CPU time 0.9 seconds
Started Nov 01 02:26:38 PM PDT 23
Finished Nov 01 02:26:41 PM PDT 23
Peak memory 214832 kb
Host smart-495443b7-2bfc-48f4-9600-0ac5c94a4f6c
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59227311159309747790194960037024438307647706041584204221228094281853272855949 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.edn_disable.59227311159309747790194960037024438307647706041584204221228094281853272855949
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.87277547704375002427115411980881005740400793669622050038169706242371694374
Short name T826
Test name
Test status
Simulation time 17319183 ps
CPU time 0.94 seconds
Started Nov 01 02:26:52 PM PDT 23
Finished Nov 01 02:26:58 PM PDT 23
Peak memory 214920 kb
Host smart-76795f36-5a61-4fdd-89fe-65a054d0bc14
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87277547704375002427115411980881005740400793669622050038169706242371694374 -assert nopostproc +
UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable_auto_req_mode.87277547704375002427115411980881005740400793669622050038169706242371694374
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.49647079332532680811487687589123393952067270008385132148938718367611532041126
Short name T413
Test name
Test status
Simulation time 24963823 ps
CPU time 1.16 seconds
Started Nov 01 02:26:44 PM PDT 23
Finished Nov 01 02:26:50 PM PDT 23
Peak memory 230492 kb
Host smart-b5707216-8e95-4a6b-b7b6-77f969007c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49647079332532680811487687589123393952067270008385132148938718367611532041126 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
edn_err.49647079332532680811487687589123393952067270008385132148938718367611532041126
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.8645641887451517109912926063554850180713026042290442752915949932658910806462
Short name T527
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:26:38 PM PDT 23
Finished Nov 01 02:26:43 PM PDT 23
Peak memory 205928 kb
Host smart-8d183b51-887c-4b99-8062-b033000fc5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8645641887451517109912926063554850180713026042290442752915949932658910806462 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.edn_genbits.8645641887451517109912926063554850180713026042290442752915949932658910806462
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.57718405807981669242525191194253168401216796848576710410815074790334743353313
Short name T634
Test name
Test status
Simulation time 18439183 ps
CPU time 1.13 seconds
Started Nov 01 02:26:37 PM PDT 23
Finished Nov 01 02:26:40 PM PDT 23
Peak memory 222304 kb
Host smart-f5c285f1-d201-4eaa-bf6e-9caf5b9303d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57718405807981669242525191194253168401216796848576710410815074790334743353313 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.edn_intr.57718405807981669242525191194253168401216796848576710410815074790334743353313
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_smoke.39257241680857159885614991970875461554261009270492545281776234010885288157630
Short name T93
Test name
Test status
Simulation time 13059183 ps
CPU time 0.86 seconds
Started Nov 01 02:26:37 PM PDT 23
Finished Nov 01 02:26:39 PM PDT 23
Peak memory 205376 kb
Host smart-fa5cb7b1-d66a-4ecc-9bbd-a9431ef1247d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39257241680857159885614991970875461554261009270492545281776234010885288157630 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.edn_smoke.39257241680857159885614991970875461554261009270492545281776234010885288157630
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.110438399868889099424564788654183201975884491719597786744035462791430158221066
Short name T397
Test name
Test status
Simulation time 154489183 ps
CPU time 4.04 seconds
Started Nov 01 02:26:10 PM PDT 23
Finished Nov 01 02:26:17 PM PDT 23
Peak memory 206432 kb
Host smart-1bc202de-de66-41c9-b198-dab040a7dca6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110438399868889099424564788654183201975884491719597786744035462791430158221066 -assert nopo
stproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.110438399868889099424564788654183201975884491719597786744035462791430158221066
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.90078426263352955215372105828090332721330675523603111943431686264443417703939
Short name T685
Test name
Test status
Simulation time 41708099183 ps
CPU time 1063.63 seconds
Started Nov 01 02:26:38 PM PDT 23
Finished Nov 01 02:44:24 PM PDT 23
Peak memory 215900 kb
Host smart-def84b96-d8e8-4a95-8e9e-bb5d066de613
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900784262633529552153721058
28090332721330675523603111943431686264443417703939 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.900784262633
52955215372105828090332721330675523603111943431686264443417703939
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.15848085070739751712672787438895468219237185567283873541351450693403813671475
Short name T34
Test name
Test status
Simulation time 24963823 ps
CPU time 1.15 seconds
Started Nov 01 02:27:24 PM PDT 23
Finished Nov 01 02:27:39 PM PDT 23
Peak memory 230472 kb
Host smart-c64cb39f-a1c5-43fe-9190-ece8d435bed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15848085070739751712672787438895468219237185567283873541351450693403813671475 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90
.edn_err.15848085070739751712672787438895468219237185567283873541351450693403813671475
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.51251152240511228567775957162915441375128138262955143334115378564437109731608
Short name T863
Test name
Test status
Simulation time 17999183 ps
CPU time 1.15 seconds
Started Nov 01 02:27:24 PM PDT 23
Finished Nov 01 02:27:39 PM PDT 23
Peak memory 205776 kb
Host smart-a2e560c7-6853-4207-8b49-d1ea2f9199d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51251152240511228567775957162915441375128138262955143334115378564437109731608 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 90.edn_genbits.51251152240511228567775957162915441375128138262955143334115378564437109731608
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.64694172444006095132295997024002463147840992510090560912858261733416125314988
Short name T836
Test name
Test status
Simulation time 24963823 ps
CPU time 1.16 seconds
Started Nov 01 02:27:21 PM PDT 23
Finished Nov 01 02:27:36 PM PDT 23
Peak memory 230440 kb
Host smart-12af6110-c558-4134-914a-4712719c9ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64694172444006095132295997024002463147840992510090560912858261733416125314988 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91
.edn_err.64694172444006095132295997024002463147840992510090560912858261733416125314988
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.92937580822876117978533686125007209681838260846894682190557531002513697286662
Short name T486
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 01 02:27:26 PM PDT 23
Finished Nov 01 02:27:41 PM PDT 23
Peak memory 205768 kb
Host smart-c6daaba2-cb51-43e1-92b9-df4bf3b64902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92937580822876117978533686125007209681838260846894682190557531002513697286662 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 91.edn_genbits.92937580822876117978533686125007209681838260846894682190557531002513697286662
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.115722786457492214615431755316356515179432186124973913411844141294449692434887
Short name T482
Test name
Test status
Simulation time 24963823 ps
CPU time 1.14 seconds
Started Nov 01 02:27:20 PM PDT 23
Finished Nov 01 02:27:35 PM PDT 23
Peak memory 230588 kb
Host smart-9f62c0a5-122e-44a0-a551-16f54ef0f5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115722786457492214615431755316356515179432186124973913411844141294449692434887 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
2.edn_err.115722786457492214615431755316356515179432186124973913411844141294449692434887
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.67042061539578032333704757471462236037727273721988148461970099820172252664367
Short name T499
Test name
Test status
Simulation time 17999183 ps
CPU time 1.19 seconds
Started Nov 01 02:27:34 PM PDT 23
Finished Nov 01 02:27:47 PM PDT 23
Peak memory 205840 kb
Host smart-b043c9fc-2146-4b54-ae2f-366f1360b399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67042061539578032333704757471462236037727273721988148461970099820172252664367 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 92.edn_genbits.67042061539578032333704757471462236037727273721988148461970099820172252664367
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.108066542691333316497927097629466109096011272574830747524773013236971813749504
Short name T649
Test name
Test status
Simulation time 24963823 ps
CPU time 1.12 seconds
Started Nov 01 02:27:05 PM PDT 23
Finished Nov 01 02:27:21 PM PDT 23
Peak memory 230516 kb
Host smart-7a2ba5f3-0224-41ad-8d91-c66f5611989f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108066542691333316497927097629466109096011272574830747524773013236971813749504 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
3.edn_err.108066542691333316497927097629466109096011272574830747524773013236971813749504
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.13595614652049290589290996944281429245294316186740277919368246818463864063100
Short name T896
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 01 02:27:20 PM PDT 23
Finished Nov 01 02:27:35 PM PDT 23
Peak memory 205888 kb
Host smart-3473b221-e133-4dd5-ba57-452681a42873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13595614652049290589290996944281429245294316186740277919368246818463864063100 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 93.edn_genbits.13595614652049290589290996944281429245294316186740277919368246818463864063100
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.84298539149737287260499979229725438276212376257645816593627731250665229492153
Short name T980
Test name
Test status
Simulation time 24963823 ps
CPU time 1.16 seconds
Started Nov 01 02:27:02 PM PDT 23
Finished Nov 01 02:27:17 PM PDT 23
Peak memory 230568 kb
Host smart-2a5e838f-78a3-4625-a8c0-39bde541f32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84298539149737287260499979229725438276212376257645816593627731250665229492153 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94
.edn_err.84298539149737287260499979229725438276212376257645816593627731250665229492153
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.85713951869358113281655035366629494010169883066043093629716178985095844874240
Short name T757
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 01 02:27:19 PM PDT 23
Finished Nov 01 02:27:35 PM PDT 23
Peak memory 205808 kb
Host smart-087983e8-e1f4-474d-a080-332a7dd1b2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85713951869358113281655035366629494010169883066043093629716178985095844874240 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 94.edn_genbits.85713951869358113281655035366629494010169883066043093629716178985095844874240
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.106604097045890101133897918010126647863894430647389182112288018221850581594956
Short name T635
Test name
Test status
Simulation time 24963823 ps
CPU time 1.1 seconds
Started Nov 01 02:26:52 PM PDT 23
Finished Nov 01 02:26:58 PM PDT 23
Peak memory 230388 kb
Host smart-301f450d-cc0f-4ff0-9755-f93693f2c145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106604097045890101133897918010126647863894430647389182112288018221850581594956 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
5.edn_err.106604097045890101133897918010126647863894430647389182112288018221850581594956
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.19017861997837641814333398113237144608758988730621182634498330616973582530820
Short name T777
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:26:57 PM PDT 23
Finished Nov 01 02:27:09 PM PDT 23
Peak memory 205992 kb
Host smart-33c0c46e-ada0-4403-b383-54aeceb24504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19017861997837641814333398113237144608758988730621182634498330616973582530820 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 95.edn_genbits.19017861997837641814333398113237144608758988730621182634498330616973582530820
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.98197478981542376029987057599215499736433190208124776543251493707123970388300
Short name T341
Test name
Test status
Simulation time 24963823 ps
CPU time 1.14 seconds
Started Nov 01 02:27:17 PM PDT 23
Finished Nov 01 02:27:32 PM PDT 23
Peak memory 230444 kb
Host smart-ced07c41-626d-4484-a3a5-c0fc8702a6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98197478981542376029987057599215499736433190208124776543251493707123970388300 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96
.edn_err.98197478981542376029987057599215499736433190208124776543251493707123970388300
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.60748487007708703139806089174181235381416527089691502074908012117076550559933
Short name T652
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 01 02:26:57 PM PDT 23
Finished Nov 01 02:27:08 PM PDT 23
Peak memory 205900 kb
Host smart-fce6cff2-285d-4d67-84f5-83b7732d0b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60748487007708703139806089174181235381416527089691502074908012117076550559933 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 96.edn_genbits.60748487007708703139806089174181235381416527089691502074908012117076550559933
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.23199797102680656524519803456298867811958403950654663318746717793326959369760
Short name T329
Test name
Test status
Simulation time 24963823 ps
CPU time 1.16 seconds
Started Nov 01 02:27:10 PM PDT 23
Finished Nov 01 02:27:26 PM PDT 23
Peak memory 230516 kb
Host smart-855c349b-3782-4662-9d01-d56e31164e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23199797102680656524519803456298867811958403950654663318746717793326959369760 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97
.edn_err.23199797102680656524519803456298867811958403950654663318746717793326959369760
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.107890318935467445311501069839200105494568996918459903034207084767772537754864
Short name T431
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 01 02:27:04 PM PDT 23
Finished Nov 01 02:27:20 PM PDT 23
Peak memory 205908 kb
Host smart-b290bf9c-0c17-458f-be1e-2535cb0ab016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107890318935467445311501069839200105494568996918459903034207084767772537754864 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 97.edn_genbits.107890318935467445311501069839200105494568996918459903034207084767772537754864
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.30345946414667468819708914525266190898616387980709658337483076874619490844220
Short name T888
Test name
Test status
Simulation time 24963823 ps
CPU time 1.12 seconds
Started Nov 01 02:27:00 PM PDT 23
Finished Nov 01 02:27:13 PM PDT 23
Peak memory 230516 kb
Host smart-d351657e-e0d4-4d61-b388-922d5a438073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30345946414667468819708914525266190898616387980709658337483076874619490844220 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98
.edn_err.30345946414667468819708914525266190898616387980709658337483076874619490844220
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.22831491053701686687479289517783952453657992944982321401346866101571248574489
Short name T511
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 01 02:26:53 PM PDT 23
Finished Nov 01 02:27:01 PM PDT 23
Peak memory 205872 kb
Host smart-63bedcf5-ce84-4349-b7b3-6a470d3f5feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22831491053701686687479289517783952453657992944982321401346866101571248574489 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 98.edn_genbits.22831491053701686687479289517783952453657992944982321401346866101571248574489
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.22838592071139080200276694546665722872387889875092225688066129353372017892977
Short name T373
Test name
Test status
Simulation time 24963823 ps
CPU time 1.16 seconds
Started Nov 01 02:27:14 PM PDT 23
Finished Nov 01 02:27:31 PM PDT 23
Peak memory 230556 kb
Host smart-8e439144-3564-449d-95e4-c526c5d449d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22838592071139080200276694546665722872387889875092225688066129353372017892977 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99
.edn_err.22838592071139080200276694546665722872387889875092225688066129353372017892977
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.94812329571765201841403244289536333335112226405097860407370000034108485149282
Short name T893
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 01 02:27:04 PM PDT 23
Finished Nov 01 02:27:20 PM PDT 23
Peak memory 205916 kb
Host smart-306393ae-9fd0-4109-8022-638e7594523e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94812329571765201841403244289536333335112226405097860407370000034108485149282 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 99.edn_genbits.94812329571765201841403244289536333335112226405097860407370000034108485149282
Directory /workspace/99.edn_genbits/latest
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