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 LINE       702
 SUB-EXPRESSION 
 Number  Term
      1  (cmd_fifo_rst_fo[3] || main_sm_done_pulse) ? '0 : (capt_gencmd_fifo_cnt ? sfifo_gencmd_depth : (capt_rescmd_fifo_cnt ? sfifo_rescmd_depth : ((send_gencmd || boot_send_gencmd || send_rescmd) ? ((cmd_fifo_cnt_q - 1)) : cmd_fifo_cnt_q))))

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T17,T25

 LINE       702
 SUB-EXPRESSION (cmd_fifo_rst_fo[3] || main_sm_done_pulse)
                 ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T17,T25
1	0	Covered	T41,T42,T43

 LINE       702
 SUB-EXPRESSION 
 Number  Term
      1  capt_gencmd_fifo_cnt ? sfifo_gencmd_depth : (capt_rescmd_fifo_cnt ? sfifo_rescmd_depth : ((send_gencmd || boot_send_gencmd || send_rescmd) ? ((cmd_fifo_cnt_q - 1)) : cmd_fifo_cnt_q)))

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T17,T25,T21

 LINE       702
 SUB-EXPRESSION (capt_rescmd_fifo_cnt ? sfifo_rescmd_depth : ((send_gencmd || boot_send_gencmd || send_rescmd) ? ((cmd_fifo_cnt_q - 1)) : cmd_fifo_cnt_q))
                 ----------1---------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T21,T22,T23

 LINE       702
 SUB-EXPRESSION ((send_gencmd || boot_send_gencmd || send_rescmd) ? ((cmd_fifo_cnt_q - 1)) : cmd_fifo_cnt_q)
                 ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T17,T25,T21

 LINE       702
 SUB-EXPRESSION (send_gencmd || boot_send_gencmd || send_rescmd)
                 -----1-----    --------2-------    -----3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T16,T17,T18
0	0	1	Covered	T21,T22,T23
0	1	0	Covered	T17,T25,T26
1	0	0	Covered	T21,T22,T23

 LINE       710
 EXPRESSION (cmd_fifo_cnt_q == 4'(1))
            ------------1------------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T17,T25,T21

 LINE       756
 EXPRESSION (((!packer_ep_rvalid[0])) && edn_i[0].edn_req)
             ------------1-----------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T25
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T17,T18

 LINE       756
 EXPRESSION (((!packer_ep_rvalid[1])) && edn_i[1].edn_req)
             ------------1-----------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T17,T25,T21
1	0	Covered	T16,T17,T18
1	1	Covered	T17,T25,T21

 LINE       756
 EXPRESSION (((!packer_ep_rvalid[2])) && edn_i[2].edn_req)
             ------------1-----------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T17,T25,T26
1	0	Covered	T16,T17,T18
1	1	Covered	T17,T25,T26

 LINE       756
 EXPRESSION (((!packer_ep_rvalid[3])) && edn_i[3].edn_req)
             ------------1-----------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T17,T25,T26
1	0	Covered	T16,T17,T18
1	1	Covered	T17,T25,T26

 LINE       756
 EXPRESSION (((!packer_ep_rvalid[4])) && edn_i[4].edn_req)
             ------------1-----------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T17,T25,T26
1	0	Covered	T16,T17,T18
1	1	Covered	T17,T25,T26

 LINE       756
 EXPRESSION (((!packer_ep_rvalid[5])) && edn_i[5].edn_req)
             ------------1-----------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T17,T25,T26
1	0	Covered	T16,T17,T18
1	1	Covered	T17,T25,T26

 LINE       756
 EXPRESSION (((!packer_ep_rvalid[6])) && edn_i[6].edn_req)
             ------------1-----------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T27,T28,T29
1	0	Covered	T16,T17,T18
1	1	Covered	T27,T28,T29

 LINE       787
 EXPRESSION (((!edn_enable_fo[CsrngFipsEn])) ? 1'b0 : ((packer_cs_push && packer_cs_wready) ? csrng_cmd_i.genbits_fips : csrng_fips_q))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T17,T18

 LINE       787
 SUB-EXPRESSION ((packer_cs_push && packer_cs_wready) ? csrng_cmd_i.genbits_fips : csrng_fips_q)
                 ------------------1-----------------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T17,T25

 LINE       787
 SUB-EXPRESSION (packer_cs_push && packer_cs_wready)
                 -------1------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T25
1	1	Covered	T16,T17,T25

 LINE       802
 EXPRESSION (packer_cs_rvalid && packer_cs_rready)
             --------1-------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T21,T24,T13
1	1	Covered	T16,T17,T25

 LINE       804
 EXPRESSION (cs_rdata_capt_vld ? packer_cs_rdata[63:0] : cs_rdata_capt_q)
             --------1--------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T17,T25

 LINE       806
 EXPRESSION (((!edn_enable_fo[CsrngDataVld])) ? 1'b0 : (cs_rdata_capt_vld ? 1'b1 : cs_rdata_capt_vld_q))
             ----------------1---------------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T17,T18

 LINE       806
 SUB-EXPRESSION (cs_rdata_capt_vld ? 1'b1 : cs_rdata_capt_vld_q)
                 --------1--------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T17,T25

 LINE       812
 EXPRESSION (cs_rdata_capt_vld && cs_rdata_capt_vld_q && (cs_rdata_capt_q == packer_cs_rdata[63:0]))
             --------1--------    ---------2---------    ---------------------3--------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T17,T25
1	0	1	Not Covered
1	1	0	Covered	T17,T25,T26
1	1	1	Covered	T41,T42,T43

 LINE       812
 SUB-EXPRESSION (cs_rdata_capt_q == packer_cs_rdata[63:0])
                ---------------------1--------------------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T17,T18

 LINE       855
 EXPRESSION (packer_arb_valid && packer_ep_wready[0] && packer_arb_gnt[0])
             --------1-------    ---------2---------    --------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T16,T17,T18
1	1	1	Covered	T16,T17,T25

 LINE       855
 EXPRESSION (packer_arb_valid && packer_ep_wready[1] && packer_arb_gnt[1])
             --------1-------    ---------2---------    --------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T16,T17,T18
1	1	1	Covered	T17,T25,T21

 LINE       855
 EXPRESSION (packer_arb_valid && packer_ep_wready[2] && packer_arb_gnt[2])
             --------1-------    ---------2---------    --------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T16,T17,T18
1	1	1	Covered	T17,T25,T26

 LINE       855
 EXPRESSION (packer_arb_valid && packer_ep_wready[3] && packer_arb_gnt[3])
             --------1-------    ---------2---------    --------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T16,T17,T18
1	1	1	Covered	T17,T25,T26

 LINE       855
 EXPRESSION (packer_arb_valid && packer_ep_wready[4] && packer_arb_gnt[4])
             --------1-------    ---------2---------    --------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T16,T17,T18
1	1	1	Covered	T17,T25,T26

 LINE       855
 EXPRESSION (packer_arb_valid && packer_ep_wready[5] && packer_arb_gnt[5])
             --------1-------    ---------2---------    --------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T16,T17,T18
1	1	1	Covered	T17,T25,T26

 LINE       855
 EXPRESSION (packer_arb_valid && packer_ep_wready[6] && packer_arb_gnt[6])
             --------1-------    ---------2---------    --------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T16,T17,T18
1	1	1	Covered	T27,T28,T29

 LINE       859
 EXPRESSION (packer_ep_clr[0] ? 1'b0 : ((packer_ep_push[0] && packer_ep_wready[0]) ? csrng_fips_q : edn_fips_q[0]))
             --------1-------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T17,T18

 LINE       859
 SUB-EXPRESSION ((packer_ep_push[0] && packer_ep_wready[0]) ? csrng_fips_q : edn_fips_q[0])
                 ---------------------1--------------------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T17,T25

 LINE       859
 SUB-EXPRESSION (packer_ep_push[0] && packer_ep_wready[0])
                 --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Not Covered
1	1	Covered	T16,T17,T25

 LINE       859
 EXPRESSION (packer_ep_clr[1] ? 1'b0 : ((packer_ep_push[1] && packer_ep_wready[1]) ? csrng_fips_q : edn_fips_q[1]))
             --------1-------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T17,T18

 LINE       859
 SUB-EXPRESSION ((packer_ep_push[1] && packer_ep_wready[1]) ? csrng_fips_q : edn_fips_q[1])
                 ---------------------1--------------------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T17,T25,T21

 LINE       859
 SUB-EXPRESSION (packer_ep_push[1] && packer_ep_wready[1])
                 --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Not Covered
1	1	Covered	T17,T25,T21

 LINE       859
 EXPRESSION (packer_ep_clr[2] ? 1'b0 : ((packer_ep_push[2] && packer_ep_wready[2]) ? csrng_fips_q : edn_fips_q[2]))
             --------1-------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T17,T18

 LINE       859
 SUB-EXPRESSION ((packer_ep_push[2] && packer_ep_wready[2]) ? csrng_fips_q : edn_fips_q[2])
                 ---------------------1--------------------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T17,T25,T26

 LINE       859
 SUB-EXPRESSION (packer_ep_push[2] && packer_ep_wready[2])
                 --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Not Covered
1	1	Covered	T17,T25,T26

 LINE       859
 EXPRESSION (packer_ep_clr[3] ? 1'b0 : ((packer_ep_push[3] && packer_ep_wready[3]) ? csrng_fips_q : edn_fips_q[3]))
             --------1-------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T17,T18

 LINE       859
 SUB-EXPRESSION ((packer_ep_push[3] && packer_ep_wready[3]) ? csrng_fips_q : edn_fips_q[3])
                 ---------------------1--------------------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T17,T25,T26

 LINE       859
 SUB-EXPRESSION (packer_ep_push[3] && packer_ep_wready[3])
                 --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Not Covered
1	1	Covered	T17,T25,T26

 LINE       859
 EXPRESSION (packer_ep_clr[4] ? 1'b0 : ((packer_ep_push[4] && packer_ep_wready[4]) ? csrng_fips_q : edn_fips_q[4]))
             --------1-------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T17,T18

 LINE       859
 SUB-EXPRESSION ((packer_ep_push[4] && packer_ep_wready[4]) ? csrng_fips_q : edn_fips_q[4])
                 ---------------------1--------------------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T17,T25,T26

 LINE       859
 SUB-EXPRESSION (packer_ep_push[4] && packer_ep_wready[4])
                 --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Not Covered
1	1	Covered	T17,T25,T26

 LINE       859
 EXPRESSION (packer_ep_clr[5] ? 1'b0 : ((packer_ep_push[5] && packer_ep_wready[5]) ? csrng_fips_q : edn_fips_q[5]))
             --------1-------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T17,T18

 LINE       859
 SUB-EXPRESSION ((packer_ep_push[5] && packer_ep_wready[5]) ? csrng_fips_q : edn_fips_q[5])
                 ---------------------1--------------------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T17,T25,T26

 LINE       859
 SUB-EXPRESSION (packer_ep_push[5] && packer_ep_wready[5])
                 --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Not Covered
1	1	Covered	T17,T25,T26

 LINE       859
 EXPRESSION (packer_ep_clr[6] ? 1'b0 : ((packer_ep_push[6] && packer_ep_wready[6]) ? csrng_fips_q : edn_fips_q[6]))
             --------1-------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T17,T18

 LINE       859
 SUB-EXPRESSION ((packer_ep_push[6] && packer_ep_wready[6]) ? csrng_fips_q : edn_fips_q[6])
                 ---------------------1--------------------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T27,T28,T29

 LINE       859
 SUB-EXPRESSION (packer_ep_push[6] && packer_ep_wready[6])
                 --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Not Covered
1	1	Covered	T27,T28,T29

 LINE       892
 EXPRESSION (((|err_code_test_bit[19:3])) || ((|err_code_test_bit[27:22])))
             --------------1-------------    --------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T1,T44,T45
1	0	Covered	T20,T1,T34