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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.04 98.64 87.64 94.78 59.21 96.47 96.83 82.73


Total test records in report: 980
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T752 /workspace/coverage/default/46.edn_genbits.38929291319722584406790079925222459205650224911857521989774019455574393492590 Nov 22 01:35:39 PM PST 23 Nov 22 01:35:43 PM PST 23 17999183 ps
T753 /workspace/coverage/default/0.edn_regwen.110229878687029962721712572837430445846876318653050081627397597154375399229317 Nov 22 01:31:32 PM PST 23 Nov 22 01:31:34 PM PST 23 11759183 ps
T754 /workspace/coverage/default/1.edn_genbits.102784106868475630960574097864637493193756639982725405908814917609208644668304 Nov 22 01:31:32 PM PST 23 Nov 22 01:31:34 PM PST 23 17999183 ps
T755 /workspace/coverage/default/23.edn_alert_test.90658945886108583709380488086120775955415444855384421268238303454475694481199 Nov 22 01:34:19 PM PST 23 Nov 22 01:34:21 PM PST 23 28184990 ps
T756 /workspace/coverage/default/9.edn_regwen.102717307839554012227224479596935692147872246776516672455193386994373036060274 Nov 22 01:33:22 PM PST 23 Nov 22 01:33:24 PM PST 23 11759183 ps
T757 /workspace/coverage/default/6.edn_alert.77011406055820133582541938602926689345936386386901056779714910531811308108701 Nov 22 01:31:50 PM PST 23 Nov 22 01:31:53 PM PST 23 18259183 ps
T758 /workspace/coverage/default/46.edn_stress_all.113241611628120547719055393213264979522508098464612587559962521277843616788049 Nov 22 01:35:41 PM PST 23 Nov 22 01:35:47 PM PST 23 154489183 ps
T759 /workspace/coverage/default/38.edn_stress_all.111779748123054190093155295460600107613119980557344778613509646083711117077382 Nov 22 01:35:05 PM PST 23 Nov 22 01:35:15 PM PST 23 154489183 ps
T760 /workspace/coverage/default/29.edn_smoke.44769531456563704898070517675988409113094043598336056411092030767730805341398 Nov 22 01:34:40 PM PST 23 Nov 22 01:34:42 PM PST 23 13059183 ps
T761 /workspace/coverage/default/63.edn_genbits.54029811871600793200275494955021421715574796568880601427171825712591640212336 Nov 22 01:35:37 PM PST 23 Nov 22 01:35:42 PM PST 23 17999183 ps
T762 /workspace/coverage/default/104.edn_genbits.70689992399950379029566356834227053109488850550686816445464029049483913108009 Nov 22 01:36:34 PM PST 23 Nov 22 01:36:36 PM PST 23 17999183 ps
T763 /workspace/coverage/default/26.edn_intr.59474162013218678273492388647101261920207037513791239939465240720684893425607 Nov 22 01:34:41 PM PST 23 Nov 22 01:34:43 PM PST 23 18439183 ps
T764 /workspace/coverage/default/237.edn_genbits.34289498822883616893249786451839820086394652585308911823552060441911536710289 Nov 22 01:36:56 PM PST 23 Nov 22 01:37:02 PM PST 23 17999183 ps
T765 /workspace/coverage/default/15.edn_stress_all.102989514399860981756463374619626893775573824592109591351439317792934608122866 Nov 22 01:33:42 PM PST 23 Nov 22 01:33:48 PM PST 23 154489183 ps
T766 /workspace/coverage/default/245.edn_genbits.1003414969212616087669113818966604717889741948566749717456233144262435660644 Nov 22 01:36:54 PM PST 23 Nov 22 01:37:01 PM PST 23 17999183 ps
T767 /workspace/coverage/default/293.edn_genbits.84047911643953275033797539839810173796216497114207494489645471379580783579671 Nov 22 01:36:53 PM PST 23 Nov 22 01:36:58 PM PST 23 17999183 ps
T768 /workspace/coverage/default/278.edn_genbits.85133183728484981416215985637908991807582922686917430947005298802815704188399 Nov 22 01:36:30 PM PST 23 Nov 22 01:36:32 PM PST 23 17999183 ps
T769 /workspace/coverage/default/44.edn_genbits.115726096546151738202395786284421787405074730717724409941499210070146783349049 Nov 22 01:35:30 PM PST 23 Nov 22 01:35:32 PM PST 23 17999183 ps
T770 /workspace/coverage/default/8.edn_genbits.33240364851703693917858247615129618247423348513786125003247178946023845859926 Nov 22 01:33:24 PM PST 23 Nov 22 01:33:27 PM PST 23 17999183 ps
T771 /workspace/coverage/default/48.edn_smoke.13431236693700687742218868087969576941208136685752807619782126509757197310675 Nov 22 01:35:43 PM PST 23 Nov 22 01:35:47 PM PST 23 13059183 ps
T772 /workspace/coverage/default/159.edn_genbits.53516496271523014934112608783965731182268154481235963328146852572734898366655 Nov 22 01:36:50 PM PST 23 Nov 22 01:36:54 PM PST 23 17999183 ps
T773 /workspace/coverage/default/79.edn_genbits.103003200711820523092183139345402710016888364782059028464337433905661828746910 Nov 22 01:36:00 PM PST 23 Nov 22 01:36:03 PM PST 23 17999183 ps
T774 /workspace/coverage/default/294.edn_genbits.46365741155853271186207497095347445196652729232364770334371583544384891223770 Nov 22 01:36:52 PM PST 23 Nov 22 01:36:57 PM PST 23 17999183 ps
T775 /workspace/coverage/default/18.edn_err.101128949605686051576382343141257856093464864832774863040649287923368915494339 Nov 22 01:34:15 PM PST 23 Nov 22 01:34:17 PM PST 23 24963823 ps
T776 /workspace/coverage/default/122.edn_genbits.46250689442489430868580187930541256748847790795838571908996657011135225449130 Nov 22 01:36:48 PM PST 23 Nov 22 01:36:51 PM PST 23 17999183 ps
T777 /workspace/coverage/default/31.edn_stress_all_with_rand_reset.110512926889860713095148043354197937728005199936735658717533328197629120450741 Nov 22 01:34:40 PM PST 23 Nov 22 01:52:01 PM PST 23 41708099183 ps
T778 /workspace/coverage/default/81.edn_err.4429189201584291508618020334491592162504260045528793788526376294216888657180 Nov 22 01:35:57 PM PST 23 Nov 22 01:35:59 PM PST 23 24963823 ps
T779 /workspace/coverage/default/11.edn_disable_auto_req_mode.76788624241530096211281479409838186168801376686975602318415387676182014536204 Nov 22 01:33:28 PM PST 23 Nov 22 01:33:29 PM PST 23 14969183 ps
T780 /workspace/coverage/default/22.edn_alert.81022832793568231841244635659288681621653879943519730688193750329886561020781 Nov 22 01:34:25 PM PST 23 Nov 22 01:34:27 PM PST 23 18259183 ps
T781 /workspace/coverage/default/12.edn_smoke.108306039207576709080602645614347565980476211616589483926452392748982899010696 Nov 22 01:33:27 PM PST 23 Nov 22 01:33:29 PM PST 23 13059183 ps
T782 /workspace/coverage/default/144.edn_genbits.68355957132531247101749735792067357992790212429742062174943212873113550284209 Nov 22 01:36:44 PM PST 23 Nov 22 01:36:46 PM PST 23 17999183 ps
T783 /workspace/coverage/default/288.edn_genbits.23616237727363754108720324293518655916330346457504857983756691638067197024407 Nov 22 01:36:48 PM PST 23 Nov 22 01:36:50 PM PST 23 17999183 ps
T784 /workspace/coverage/default/11.edn_disable.41686747272754494537231054280672466239095969638818418812114672764323386383829 Nov 22 01:33:28 PM PST 23 Nov 22 01:33:30 PM PST 23 12219183 ps
T785 /workspace/coverage/default/27.edn_stress_all_with_rand_reset.79186433639992078611115757760222912831617990785573847577131942263120404638211 Nov 22 01:34:27 PM PST 23 Nov 22 01:52:46 PM PST 23 41708099183 ps
T786 /workspace/coverage/default/45.edn_genbits.51030715189730138394088254578378346284152777295482649950702878528614383813515 Nov 22 01:35:38 PM PST 23 Nov 22 01:35:42 PM PST 23 17999183 ps
T787 /workspace/coverage/default/20.edn_alert_test.29765001390894482635568885686969669463433879670640488991286094280418593592999 Nov 22 01:34:09 PM PST 23 Nov 22 01:34:11 PM PST 23 28184990 ps
T788 /workspace/coverage/default/19.edn_intr.66313709578450150531940265008026828763282820901066528335282115158791016271037 Nov 22 01:34:12 PM PST 23 Nov 22 01:34:14 PM PST 23 18439183 ps
T789 /workspace/coverage/default/25.edn_stress_all_with_rand_reset.55317911149025877452840269232050911147543159798594366273705831713829962815674 Nov 22 01:34:15 PM PST 23 Nov 22 01:51:47 PM PST 23 41708099183 ps
T790 /workspace/coverage/default/76.edn_err.91149215552841070387839798293642779891959325960404605150922769760308857418806 Nov 22 01:35:59 PM PST 23 Nov 22 01:36:00 PM PST 23 24963823 ps
T791 /workspace/coverage/default/95.edn_err.75815071860015695016090435885819204671587848805209787853651757975105553161776 Nov 22 01:35:54 PM PST 23 Nov 22 01:35:56 PM PST 23 24963823 ps
T792 /workspace/coverage/default/24.edn_stress_all.2858319495573724568152152705865873444570850457714078119613370270659414173602 Nov 22 01:34:29 PM PST 23 Nov 22 01:34:34 PM PST 23 154489183 ps
T793 /workspace/coverage/default/107.edn_genbits.110905468232010348799501124593782843843763106080290399962448425405018378509876 Nov 22 01:36:36 PM PST 23 Nov 22 01:36:40 PM PST 23 17999183 ps
T794 /workspace/coverage/default/13.edn_disable.29459657505096534391996722679664065672529125623270808976683702636876520998519 Nov 22 01:33:32 PM PST 23 Nov 22 01:33:34 PM PST 23 12219183 ps
T795 /workspace/coverage/default/23.edn_smoke.91531834629163802396751969641145943803742472195074865680352250055349071324790 Nov 22 01:34:14 PM PST 23 Nov 22 01:34:16 PM PST 23 13059183 ps
T796 /workspace/coverage/default/34.edn_alert.38363116779267598167809834707924723420734520458109968264496989678879836787558 Nov 22 01:35:10 PM PST 23 Nov 22 01:35:15 PM PST 23 18259183 ps
T797 /workspace/coverage/default/21.edn_stress_all_with_rand_reset.62007007299933434967733019007859870835639698174981596745194793203778841003216 Nov 22 01:34:15 PM PST 23 Nov 22 01:52:19 PM PST 23 41708099183 ps
T798 /workspace/coverage/default/19.edn_err.106339110698940419344987891177797829329294041850872240737274267418203348364598 Nov 22 01:34:14 PM PST 23 Nov 22 01:34:17 PM PST 23 24963823 ps
T799 /workspace/coverage/default/1.edn_alert.60878558548954165093950567108809719741456357763826654324489133567308688574724 Nov 22 01:31:32 PM PST 23 Nov 22 01:31:34 PM PST 23 18259183 ps
T800 /workspace/coverage/default/72.edn_err.64856333165947331096724758983067576008359498601970090730287807759491066803696 Nov 22 01:35:55 PM PST 23 Nov 22 01:35:57 PM PST 23 24963823 ps
T801 /workspace/coverage/default/7.edn_smoke.27975617610651623158603160459785256911102857843546381989777041321821909520389 Nov 22 01:31:50 PM PST 23 Nov 22 01:31:53 PM PST 23 13059183 ps
T802 /workspace/coverage/default/74.edn_err.84402747400066013596011380205462954394976251422716786390648216305260255655161 Nov 22 01:35:55 PM PST 23 Nov 22 01:35:57 PM PST 23 24963823 ps
T803 /workspace/coverage/default/82.edn_genbits.59791093169700093863887829494974068918789364666784619180616668712662167656285 Nov 22 01:35:59 PM PST 23 Nov 22 01:36:01 PM PST 23 17999183 ps
T804 /workspace/coverage/default/6.edn_genbits.26078823939068724556777437770303433753937197584280962931779555896107945734946 Nov 22 01:31:51 PM PST 23 Nov 22 01:31:53 PM PST 23 17999183 ps
T805 /workspace/coverage/default/208.edn_genbits.50773652125500301533411394933227669184775487958918746222099482615776173643249 Nov 22 01:36:35 PM PST 23 Nov 22 01:36:37 PM PST 23 17999183 ps
T806 /workspace/coverage/default/37.edn_err.3104291270283597389900200733005624650217314103482580944581602654751545362350 Nov 22 01:35:06 PM PST 23 Nov 22 01:35:13 PM PST 23 24963823 ps
T807 /workspace/coverage/default/49.edn_alert_test.42704731194755504332748328973936680305027749515272935366514917955475748660825 Nov 22 01:35:35 PM PST 23 Nov 22 01:35:40 PM PST 23 28184990 ps
T808 /workspace/coverage/default/9.edn_alert_test.38487142566414802575611753203755492335502916514227433955023554310517160824292 Nov 22 01:33:23 PM PST 23 Nov 22 01:33:26 PM PST 23 28184990 ps
T809 /workspace/coverage/default/6.edn_stress_all.33388003104667395954672107653453826634447324018446167301207228523216407651590 Nov 22 01:31:50 PM PST 23 Nov 22 01:31:56 PM PST 23 154489183 ps
T810 /workspace/coverage/default/2.edn_smoke.30806522326951515271921331755217720249285531645015085938097863934564743025817 Nov 22 01:31:36 PM PST 23 Nov 22 01:31:39 PM PST 23 13059183 ps
T811 /workspace/coverage/default/7.edn_regwen.87129164853802754449430536240447398447087960823692681606867919681147523663850 Nov 22 01:31:49 PM PST 23 Nov 22 01:31:50 PM PST 23 11759183 ps
T812 /workspace/coverage/default/1.edn_stress_all.44174218391849309577405885728088567885875893460700302512118478012853434616692 Nov 22 01:31:34 PM PST 23 Nov 22 01:31:40 PM PST 23 154489183 ps
T813 /workspace/coverage/default/49.edn_intr.8361422492265318201969345430079678327944869738610472638309394766634799495070 Nov 22 01:35:33 PM PST 23 Nov 22 01:35:35 PM PST 23 18439183 ps
T814 /workspace/coverage/default/8.edn_stress_all.111967081411547785530112927886032701601653445710737318579347524181771327407266 Nov 22 01:33:23 PM PST 23 Nov 22 01:33:28 PM PST 23 154489183 ps
T815 /workspace/coverage/default/57.edn_genbits.33667210993009666252580795544396169098376920538525386497937857809715914638698 Nov 22 01:35:37 PM PST 23 Nov 22 01:35:42 PM PST 23 17999183 ps
T816 /workspace/coverage/default/32.edn_disable.76346047728489300863865054560644067807152564427191661390965756789690272768848 Nov 22 01:35:03 PM PST 23 Nov 22 01:35:06 PM PST 23 12219183 ps
T817 /workspace/coverage/default/5.edn_disable_auto_req_mode.43111428475674967317870261066385191289089611727205153564109406972754386720157 Nov 22 01:31:50 PM PST 23 Nov 22 01:31:51 PM PST 23 14969183 ps
T818 /workspace/coverage/default/40.edn_alert.36732810734062089794312492258793790840896085566683403282522218489880933055272 Nov 22 01:35:32 PM PST 23 Nov 22 01:35:35 PM PST 23 18259183 ps
T819 /workspace/coverage/default/19.edn_smoke.13415891280284886161045053572127399620139524448065185986561691952504246353649 Nov 22 01:34:02 PM PST 23 Nov 22 01:34:04 PM PST 23 13059183 ps
T820 /workspace/coverage/default/265.edn_genbits.106243450596409072027446407672979683522203722085310298765126694856469131513967 Nov 22 01:36:27 PM PST 23 Nov 22 01:36:29 PM PST 23 17999183 ps
T821 /workspace/coverage/default/253.edn_genbits.105520614345911288395068781570350341635476793849334909171967393557180853108135 Nov 22 01:36:56 PM PST 23 Nov 22 01:37:02 PM PST 23 17999183 ps
T822 /workspace/coverage/default/43.edn_stress_all.20482491467970533541911170301460361604771839091225058722072534722417707131118 Nov 22 01:35:38 PM PST 23 Nov 22 01:35:45 PM PST 23 154489183 ps
T823 /workspace/coverage/default/47.edn_err.91921685909306575586327186408702537381423678283778378137883553076270683284431 Nov 22 01:35:42 PM PST 23 Nov 22 01:35:47 PM PST 23 24963823 ps
T824 /workspace/coverage/default/10.edn_intr.66484615588113687623302323356403304741407200695815041824917583677265556587648 Nov 22 01:33:25 PM PST 23 Nov 22 01:33:27 PM PST 23 18439183 ps
T825 /workspace/coverage/default/55.edn_err.79994849111806330169666641358476184935672631516175330488751325390854989748784 Nov 22 01:35:36 PM PST 23 Nov 22 01:35:40 PM PST 23 24963823 ps
T53 /workspace/coverage/default/4.edn_sec_cm.452534870505987734255485276389023047113984806195430024161714946567858082012 Nov 22 01:31:51 PM PST 23 Nov 22 01:31:58 PM PST 23 717215632 ps
T826 /workspace/coverage/default/166.edn_genbits.51392927110904078738089342083388685520540912495676224429328540302332121222564 Nov 22 01:36:50 PM PST 23 Nov 22 01:36:55 PM PST 23 17999183 ps
T827 /workspace/coverage/default/204.edn_genbits.11946601096163645067872607338251492039831108109144825407194969691214830204640 Nov 22 01:36:27 PM PST 23 Nov 22 01:36:28 PM PST 23 17999183 ps
T828 /workspace/coverage/default/200.edn_genbits.77815729411910013845364634021779104016451969292166125804306999947775712562350 Nov 22 01:36:46 PM PST 23 Nov 22 01:36:48 PM PST 23 17999183 ps
T829 /workspace/coverage/default/42.edn_stress_all_with_rand_reset.77960748339270554205984896970971564768232683054575134308803403509331304114715 Nov 22 01:35:31 PM PST 23 Nov 22 01:52:34 PM PST 23 41708099183 ps
T830 /workspace/coverage/default/12.edn_stress_all_with_rand_reset.9195204031996649751555789152785092039989796532695873914441638249906870029203 Nov 22 01:33:29 PM PST 23 Nov 22 01:51:50 PM PST 23 41708099183 ps
T831 /workspace/coverage/default/164.edn_genbits.93126516940449658938140239212192960229885433192866789297904771051367241206462 Nov 22 01:36:53 PM PST 23 Nov 22 01:36:58 PM PST 23 17999183 ps
T832 /workspace/coverage/default/38.edn_disable.112678367875033079245596678256120661007984914259562364311690115030235746252678 Nov 22 01:35:20 PM PST 23 Nov 22 01:35:21 PM PST 23 12219183 ps
T833 /workspace/coverage/default/231.edn_genbits.79543776391735559620234738390012408237542690931297851255574309763890336623238 Nov 22 01:36:50 PM PST 23 Nov 22 01:36:54 PM PST 23 17999183 ps
T834 /workspace/coverage/default/5.edn_alert.99752996312341457656244707655919371060913475471066253912685467285842658975722 Nov 22 01:31:49 PM PST 23 Nov 22 01:31:51 PM PST 23 18259183 ps
T835 /workspace/coverage/default/42.edn_genbits.84623648306599967130683147634682444920013308353603625107557443940708417973306 Nov 22 01:35:30 PM PST 23 Nov 22 01:35:33 PM PST 23 17999183 ps
T836 /workspace/coverage/default/27.edn_err.30249517821938581813937021321830176428220913779979790954999468592176442124915 Nov 22 01:34:28 PM PST 23 Nov 22 01:34:30 PM PST 23 24963823 ps
T837 /workspace/coverage/default/254.edn_genbits.84775018521286929267025050605276364541327789596339361240770168609790677584574 Nov 22 01:36:49 PM PST 23 Nov 22 01:36:53 PM PST 23 17999183 ps
T838 /workspace/coverage/default/67.edn_err.105957095774596673512275167474018154852419754607084279346467286258348663786570 Nov 22 01:35:43 PM PST 23 Nov 22 01:35:47 PM PST 23 24963823 ps
T839 /workspace/coverage/default/273.edn_genbits.70542343528162174701475199657867179617488310276490265748823363529828295380919 Nov 22 01:36:37 PM PST 23 Nov 22 01:36:41 PM PST 23 17999183 ps
T840 /workspace/coverage/default/244.edn_genbits.108709429870144183981139616924655541494555376153362699222747457526969253374348 Nov 22 01:36:52 PM PST 23 Nov 22 01:36:58 PM PST 23 17999183 ps
T841 /workspace/coverage/default/40.edn_alert_test.35963784521413493551589474419375319996610194644033891386215929301264458783374 Nov 22 01:35:31 PM PST 23 Nov 22 01:35:34 PM PST 23 28184990 ps
T842 /workspace/coverage/default/292.edn_genbits.643771501554027615566538975029058940413700604816040511924275658984802585657 Nov 22 01:36:47 PM PST 23 Nov 22 01:36:50 PM PST 23 17999183 ps
T843 /workspace/coverage/default/110.edn_genbits.106587606260442384547156952129730885937773029244792927425588633732970299741591 Nov 22 01:36:45 PM PST 23 Nov 22 01:36:48 PM PST 23 17999183 ps
T844 /workspace/coverage/default/12.edn_disable.22733988815629700026758110463141813757478590121433295816172042522890853674862 Nov 22 01:33:28 PM PST 23 Nov 22 01:33:29 PM PST 23 12219183 ps
T845 /workspace/coverage/default/182.edn_genbits.32547137226199250626301069116823664258721767309122900845050364784474656659171 Nov 22 01:36:35 PM PST 23 Nov 22 01:36:37 PM PST 23 17999183 ps
T846 /workspace/coverage/default/13.edn_genbits.25281130128238916675417786202706487892545702380881714745214138162679182503556 Nov 22 01:33:37 PM PST 23 Nov 22 01:33:41 PM PST 23 17999183 ps
T847 /workspace/coverage/default/45.edn_stress_all_with_rand_reset.3920508421134776853605644030349625402506554713205063681025938504108404866980 Nov 22 01:35:41 PM PST 23 Nov 22 01:53:31 PM PST 23 41708099183 ps
T848 /workspace/coverage/default/9.edn_stress_all_with_rand_reset.94405507372297456533940348336737946901281658756433691499529152752713955770168 Nov 22 01:33:24 PM PST 23 Nov 22 01:51:34 PM PST 23 41708099183 ps
T849 /workspace/coverage/default/48.edn_disable.98847260750247593415036035909032862431646864251275093213002326661164598578619 Nov 22 01:35:40 PM PST 23 Nov 22 01:35:43 PM PST 23 12219183 ps
T850 /workspace/coverage/default/224.edn_genbits.53370402844401302815251283033350662407182357632286787045064605311033530931292 Nov 22 01:36:48 PM PST 23 Nov 22 01:36:51 PM PST 23 17999183 ps
T851 /workspace/coverage/default/89.edn_genbits.93828153634805626521990610351077106588275658136386472740261604094998958375340 Nov 22 01:36:07 PM PST 23 Nov 22 01:36:09 PM PST 23 17999183 ps
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T952 /workspace/coverage/default/214.edn_genbits.27231421162458153378228738042494938455158828993854301998375074064682520739129 Nov 22 01:36:35 PM PST 23 Nov 22 01:36:38 PM PST 23 17999183 ps
T953 /workspace/coverage/default/152.edn_genbits.104092673765317908238412222412041651178218516116096150061726979264230298808621 Nov 22 01:36:49 PM PST 23 Nov 22 01:36:52 PM PST 23 17999183 ps
T954 /workspace/coverage/default/127.edn_genbits.17054037404320974845233538166443667842022172027963689775502151528572683609337 Nov 22 01:36:53 PM PST 23 Nov 22 01:36:59 PM PST 23 17999183 ps
T955 /workspace/coverage/default/35.edn_genbits.3801187031405990592808318494433234139778166874450295698046004546885126139560 Nov 22 01:35:07 PM PST 23 Nov 22 01:35:15 PM PST 23 17999183 ps
T956 /workspace/coverage/default/25.edn_alert.3586284348919425293884540300180637779270169460584610868281821337104681326553 Nov 22 01:34:40 PM PST 23 Nov 22 01:34:42 PM PST 23 18259183 ps
T957 /workspace/coverage/default/113.edn_genbits.112027339958401918170708278333233355882488689189059280010638494429558030129254 Nov 22 01:36:35 PM PST 23 Nov 22 01:36:37 PM PST 23 17999183 ps
T958 /workspace/coverage/default/35.edn_alert_test.68058101657540465025682886065850973256929992466951424266772761868667279322508 Nov 22 01:35:07 PM PST 23 Nov 22 01:35:15 PM PST 23 28184990 ps
T959 /workspace/coverage/default/92.edn_err.53942568742175634188453725771601544063309734291777851476870259677523445878361 Nov 22 01:36:51 PM PST 23 Nov 22 01:36:55 PM PST 23 24963823 ps
T960 /workspace/coverage/default/14.edn_disable.108892883215630091931462999273031818875064734059554390553233174513155437714938 Nov 22 01:33:42 PM PST 23 Nov 22 01:33:45 PM PST 23 12219183 ps
T961 /workspace/coverage/default/260.edn_genbits.7797342319282538441560369590088374420314363496297438407042515164173126538779 Nov 22 01:36:43 PM PST 23 Nov 22 01:36:45 PM PST 23 17999183 ps
T962 /workspace/coverage/default/33.edn_stress_all_with_rand_reset.7703704364851810820391524522163406052317228591417967140066448523299229796290 Nov 22 01:35:03 PM PST 23 Nov 22 01:53:15 PM PST 23 41708099183 ps
T963 /workspace/coverage/default/73.edn_err.29467108669734025473306844017904905379538391285559802802867015045660146435396 Nov 22 01:36:01 PM PST 23 Nov 22 01:36:03 PM PST 23 24963823 ps
T964 /workspace/coverage/default/64.edn_err.64560599614797451309184413235929022440160988088604829463668757391767621282256 Nov 22 01:35:39 PM PST 23 Nov 22 01:35:43 PM PST 23 24963823 ps
T965 /workspace/coverage/default/154.edn_genbits.32564010691903384375184171967348711424152734245328533286168520062164635533841 Nov 22 01:36:34 PM PST 23 Nov 22 01:36:36 PM PST 23 17999183 ps
T966 /workspace/coverage/default/14.edn_intr.16712942817012008182338349406971818076877584752835505840701035628732232250932 Nov 22 01:33:34 PM PST 23 Nov 22 01:33:41 PM PST 23 18439183 ps
T967 /workspace/coverage/default/11.edn_genbits.112313527127010762499307669439982269292764134386187481862975183374635282260765 Nov 22 01:33:26 PM PST 23 Nov 22 01:33:28 PM PST 23 17999183 ps
T968 /workspace/coverage/default/36.edn_genbits.94442084291588420524584853452839297502841052531046468927946068170415079863850 Nov 22 01:35:05 PM PST 23 Nov 22 01:35:11 PM PST 23 17999183 ps
T969 /workspace/coverage/default/75.edn_err.49369302868654677151108009953105698409581662798899046746590114257416608062289 Nov 22 01:36:01 PM PST 23 Nov 22 01:36:03 PM PST 23 24963823 ps
T970 /workspace/coverage/default/146.edn_genbits.99408624308053854464489088456533988544283635745852965896924212732909298955854 Nov 22 01:36:36 PM PST 23 Nov 22 01:36:39 PM PST 23 17999183 ps
T971 /workspace/coverage/default/223.edn_genbits.47664247770344239631706887126887442163113670183431155790113744967505478709057 Nov 22 01:36:47 PM PST 23 Nov 22 01:36:50 PM PST 23 17999183 ps
T972 /workspace/coverage/default/3.edn_alert.31937946793702161971741466456375089307794653943640197408082613287364463129197 Nov 22 01:31:34 PM PST 23 Nov 22 01:31:37 PM PST 23 18259183 ps
T973 /workspace/coverage/default/211.edn_genbits.69511472987921842745053830231051985291977098631491903492016414132857956133914 Nov 22 01:36:36 PM PST 23 Nov 22 01:36:39 PM PST 23 17999183 ps
T974 /workspace/coverage/default/181.edn_genbits.55930879171403198657176920512712625872848474329869187632071773648742293985151 Nov 22 01:36:54 PM PST 23 Nov 22 01:37:01 PM PST 23 17999183 ps
T975 /workspace/coverage/default/23.edn_stress_all_with_rand_reset.31267620858682693300383849576054693134069518586295220897123741370321721827832 Nov 22 01:34:13 PM PST 23 Nov 22 01:51:42 PM PST 23 41708099183 ps
T976 /workspace/coverage/default/0.edn_disable_auto_req_mode.32721173828917728919173923863303046669117519986101810839676428053002690699403 Nov 22 01:31:33 PM PST 23 Nov 22 01:31:36 PM PST 23 14969183 ps
T977 /workspace/coverage/default/49.edn_err.27845600128736613516115190025125241177775218602716367268319218073565728620517 Nov 22 01:35:34 PM PST 23 Nov 22 01:35:38 PM PST 23 24963823 ps
T978 /workspace/coverage/default/19.edn_alert.56755918349429999827807373970265136463172635751719722217866285542543647366068 Nov 22 01:34:11 PM PST 23 Nov 22 01:34:13 PM PST 23 18259183 ps
T979 /workspace/coverage/default/165.edn_genbits.39921498436412253946387957531025081517862930963808995297042578637740570166094 Nov 22 01:36:49 PM PST 23 Nov 22 01:36:52 PM PST 23 17999183 ps
T980 /workspace/coverage/default/4.edn_disable_auto_req_mode.47813985691515553996518021574213804745063630705507955112228969594217903331085 Nov 22 01:31:51 PM PST 23 Nov 22 01:31:53 PM PST 23 14969183 ps

Test location /workspace/coverage/default/160.edn_genbits.48475606933601143857329721502106907693963859985618411295842911234328831097891
Short name T25
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:36:50 PM PST 23
Finished Nov 22 01:36:55 PM PST 23
Peak memory 205804 kb
Host smart-c15cbdff-3c66-485e-b9bd-e2ebb62109fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48475606933601143857329721502106907693963859985618411295842911234328831097891 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 160.edn_genbits.48475606933601143857329721502106907693963859985618411295842911234328831097891
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.64035267142174327382922929461544108571527342925425524092418211454815034989612
Short name T1
Test name
Test status
Simulation time 41708099183 ps
CPU time 1098.12 seconds
Started Nov 22 01:34:29 PM PST 23
Finished Nov 22 01:52:48 PM PST 23
Peak memory 215880 kb
Host smart-bac646db-5973-4dff-8072-e89f2427d55d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640352671421743273829229294
61544108571527342925425524092418211454815034989612 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.64035267142
174327382922929461544108571527342925425524092418211454815034989612
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.97144212416500152037148034217916818272624584804422667872736524774159723170958
Short name T21
Test name
Test status
Simulation time 14969183 ps
CPU time 0.9 seconds
Started Nov 22 01:33:41 PM PST 23
Finished Nov 22 01:33:42 PM PST 23
Peak memory 214868 kb
Host smart-04722325-3bb4-4633-9148-105a90e81d62
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97144212416500152037148034217916818272624584804422667872736524774159723170958 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable_auto_req_mode.9714421241650015203714803421791681827262458480442266787273
6524774159723170958
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_sec_cm.113972168137116426293511646776879350035725230257432219414120913430805593700469
Short name T30
Test name
Test status
Simulation time 717215632 ps
CPU time 5.64 seconds
Started Nov 22 01:31:34 PM PST 23
Finished Nov 22 01:31:42 PM PST 23
Peak memory 233960 kb
Host smart-77bad2f7-f97a-4efa-922a-a733cec04791
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113972168137116426293511646776879350035725230257432219414120913430805593700469 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.edn_sec_cm.113972168137116426293511646776879350035725230257432219414120913430805593700469
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/20.edn_err.79734849059989309960846579304925792451589131942408580763920581845975426992734
Short name T18
Test name
Test status
Simulation time 24963823 ps
CPU time 1.19 seconds
Started Nov 22 01:34:10 PM PST 23
Finished Nov 22 01:34:13 PM PST 23
Peak memory 230448 kb
Host smart-cfc6aa86-72b5-4489-927c-f94ec017510c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79734849059989309960846579304925792451589131942408580763920581845975426992734 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.edn_err.79734849059989309960846579304925792451589131942408580763920581845975426992734
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/0.edn_disable.30723490786052654643385115833436786893337454268809375243098443418482046145854
Short name T71
Test name
Test status
Simulation time 12219183 ps
CPU time 0.81 seconds
Started Nov 22 01:31:31 PM PST 23
Finished Nov 22 01:31:33 PM PST 23
Peak memory 214732 kb
Host smart-7b836fce-197b-466c-90f5-60e2b9be5ffb
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30723490786052654643385115833436786893337454268809375243098443418482046145854 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.edn_disable.30723490786052654643385115833436786893337454268809375243098443418482046145854
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.10198453046069809550396873898979538534356389240297066906709379760184011774988
Short name T10
Test name
Test status
Simulation time 155537119 ps
CPU time 2.15 seconds
Started Nov 22 01:18:35 PM PST 23
Finished Nov 22 01:18:39 PM PST 23
Peak memory 206528 kb
Host smart-d8ed67e5-d82a-45c4-99d7-96e2fafadd6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10198453046069809550396873898979538534356389240297066906709379760184011774988 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.10198453046069809550396873898979538534356389240297066906709379760184011774988
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.217989164378655402697904336416857279445512268882213136894684488542788305050
Short name T312
Test name
Test status
Simulation time 18259183 ps
CPU time 0.99 seconds
Started Nov 22 01:31:32 PM PST 23
Finished Nov 22 01:31:34 PM PST 23
Peak memory 205548 kb
Host smart-a755a1f7-b9ff-49db-a4a5-5bbf2c401ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217989164378655402697904336416857279445512268882213136894684488542788305050 -assert nopostproc +UVM_TESTNAME=edn_alert_t
est +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.edn_alert.217989164378655402697904336416857279445512268882213136894684488542788305050
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_regwen.110229878687029962721712572837430445846876318653050081627397597154375399229317
Short name T753
Test name
Test status
Simulation time 11759183 ps
CPU time 0.85 seconds
Started Nov 22 01:31:32 PM PST 23
Finished Nov 22 01:31:34 PM PST 23
Peak memory 205328 kb
Host smart-de2d7dc0-0db9-44b0-81f8-56b3d988e6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110229878687029962721712572837430445846876318653050081627397597154375399229317 -assert nopostproc +UVM_TESTNAME=edn_smok
e_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.edn_regwen.110229878687029962721712572837430445846876318653050081627397597154375399229317
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_intr.88001280447427872140756386168114551185523238105440367427589610712836469177247
Short name T283
Test name
Test status
Simulation time 18439183 ps
CPU time 1.11 seconds
Started Nov 22 01:31:33 PM PST 23
Finished Nov 22 01:31:35 PM PST 23
Peak memory 222232 kb
Host smart-7359047b-5210-4208-aefb-d6d4e88994cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88001280447427872140756386168114551185523238105440367427589610712836469177247 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.edn_intr.88001280447427872140756386168114551185523238105440367427589610712836469177247
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/11.edn_alert_test.35273163500956167673727304671181904067419163404623486456035635687953508064108
Short name T269
Test name
Test status
Simulation time 28184990 ps
CPU time 0.88 seconds
Started Nov 22 01:33:31 PM PST 23
Finished Nov 22 01:33:33 PM PST 23
Peak memory 205444 kb
Host smart-cce3eb97-1965-4720-8c30-9f5d5f14174a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35273163500956167673727304671181904067419163404623486456035635687953508064108 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.edn_alert_test.35273163500956167673727304671181904067419163404623486456035635687953508064108
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.10886634476806248504936498010578226012205668627852224577352398168394356400495
Short name T89
Test name
Test status
Simulation time 61976116 ps
CPU time 1.34 seconds
Started Nov 22 01:19:02 PM PST 23
Finished Nov 22 01:19:05 PM PST 23
Peak memory 206560 kb
Host smart-5611e193-16e6-4796-9421-6cb0987d5fb5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10886634476806248504936498010578226012205668627852224577352398168394356400495
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_outstanding.10886634476806248504936498010578226012205668627852224577352398168394356400495
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/default/11.edn_stress_all.80854401467467291329183376378370576213073920464165845168702099109449001439772
Short name T302
Test name
Test status
Simulation time 154489183 ps
CPU time 4 seconds
Started Nov 22 01:33:28 PM PST 23
Finished Nov 22 01:33:32 PM PST 23
Peak memory 206364 kb
Host smart-8f68237a-70e5-4bc3-91f5-37416bd037bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80854401467467291329183376378370576213073920464165845168702099109449001439772 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.80854401467467291329183376378370576213073920464165845168702099109449001439772
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_smoke.55500602270746476187520372128939996260321353678207068940759661282590407375514
Short name T251
Test name
Test status
Simulation time 13059183 ps
CPU time 0.91 seconds
Started Nov 22 01:33:42 PM PST 23
Finished Nov 22 01:33:45 PM PST 23
Peak memory 205384 kb
Host smart-e343cc3e-0a9e-4d1b-90bb-616951fe8e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55500602270746476187520372128939996260321353678207068940759661282590407375514 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.edn_smoke.55500602270746476187520372128939996260321353678207068940759661282590407375514
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.13953840833184909922303761091917825044018541056223457083390410410444345214401
Short name T188
Test name
Test status
Simulation time 59184494 ps
CPU time 1.35 seconds
Started Nov 22 01:18:32 PM PST 23
Finished Nov 22 01:18:36 PM PST 23
Peak memory 206284 kb
Host smart-b9a04abb-b4a8-4fdb-abe0-01be3d87ac6f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13953840833184909922303761091917825044018541056223457083390410410444345214401 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.13953840833184909922303761091917825044018541056223457083390410410444345214401
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.66517009156969533574114102951221530774077449021834554398917441979318446976141
Short name T176
Test name
Test status
Simulation time 351971476 ps
CPU time 5.32 seconds
Started Nov 22 01:18:15 PM PST 23
Finished Nov 22 01:18:25 PM PST 23
Peak memory 206508 kb
Host smart-bc99ecfa-d2d7-4c54-8977-0591a2a7e7f3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66517009156969533574114102951221530774077449021834554398917441979318446976141 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.66517009156969533574114102951221530774077449021834554398917441979318446976141
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.75818698043921376945559773169977834632314755342198737338956840878162969267843
Short name T125
Test name
Test status
Simulation time 26726680 ps
CPU time 0.89 seconds
Started Nov 22 01:18:13 PM PST 23
Finished Nov 22 01:18:18 PM PST 23
Peak memory 206536 kb
Host smart-b1a4b349-9912-4ca1-a7a6-9988dec18404
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75818698043921376945559773169977834632314755342198737338956840878162969267843 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.75818698043921376945559773169977834632314755342198737338956840878162969267843
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.63726575184387145009222840384982491577611530489882974020283286082998365705662
Short name T216
Test name
Test status
Simulation time 51163789 ps
CPU time 1.33 seconds
Started Nov 22 01:18:32 PM PST 23
Finished Nov 22 01:18:35 PM PST 23
Peak memory 214764 kb
Host smart-7298a4b7-c3da-4867-b732-bddfdd29103f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6372657518438714500922284038498249157761153
0489882974020283286082998365705662 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.6372657518438714500922284038
4982491577611530489882974020283286082998365705662
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.32487162471454476280309744394973450370431811902956995230285244761186771662861
Short name T126
Test name
Test status
Simulation time 23247569 ps
CPU time 0.82 seconds
Started Nov 22 01:19:12 PM PST 23
Finished Nov 22 01:19:15 PM PST 23
Peak memory 206308 kb
Host smart-bfbff3f0-e0bb-4529-ac9f-70dd5d016fd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32487162471454476280309744394973450370431811902956995230285244761186771662861 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.32487162471454476280309744394973450370431811902956995230285244761186771662861
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.20133460310078522833673891231121390621898502509821748332805409364895816284353
Short name T144
Test name
Test status
Simulation time 25518366 ps
CPU time 0.83 seconds
Started Nov 22 01:18:15 PM PST 23
Finished Nov 22 01:18:21 PM PST 23
Peak memory 206424 kb
Host smart-768b298b-5333-4534-89fc-4547d4a56b7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20133460310078522833673891231121390621898502509821748332805409364895816284353 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 0.edn_intr_test.20133460310078522833673891231121390621898502509821748332805409364895816284353
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.24600421219965501609498274412986128328859500410798385019081764175187292818170
Short name T172
Test name
Test status
Simulation time 61976116 ps
CPU time 1.31 seconds
Started Nov 22 01:19:02 PM PST 23
Finished Nov 22 01:19:05 PM PST 23
Peak memory 206388 kb
Host smart-1d0590db-658b-413c-aa3f-7db3d599ac61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24600421219965501609498274412986128328859500410798385019081764175187292818170
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_outstanding.24600421219965501609498274412986128328859500410798385019081764175187292818170
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.42966394828878600238328385531584443887564359476095463883799254950600059049003
Short name T191
Test name
Test status
Simulation time 204078009 ps
CPU time 3.47 seconds
Started Nov 22 01:18:56 PM PST 23
Finished Nov 22 01:19:02 PM PST 23
Peak memory 214196 kb
Host smart-c673c9b0-f405-4f60-893c-5a88f544a3b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42966394828878600238328385531584443887564359476095463883799254950600059049003 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 0.edn_tl_errors.42966394828878600238328385531584443887564359476095463883799254950600059049003
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.18094769384798187724949927496740653354434019679964112988091281093759405319049
Short name T130
Test name
Test status
Simulation time 155537119 ps
CPU time 2.15 seconds
Started Nov 22 01:18:58 PM PST 23
Finished Nov 22 01:19:03 PM PST 23
Peak memory 206204 kb
Host smart-a72d3eea-0380-46a1-b121-73dad583c4bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18094769384798187724949927496740653354434019679964112988091281093759405319049 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.18094769384798187724949927496740653354434019679964112988091281093759405319049
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.23837335083602557010092173742967694938613637146072089654865536904102932605750
Short name T181
Test name
Test status
Simulation time 59184494 ps
CPU time 1.36 seconds
Started Nov 22 01:19:03 PM PST 23
Finished Nov 22 01:19:07 PM PST 23
Peak memory 206340 kb
Host smart-070d9b2d-ca14-41dc-b296-d4c3f5eff8aa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23837335083602557010092173742967694938613637146072089654865536904102932605750 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.23837335083602557010092173742967694938613637146072089654865536904102932605750
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.42307030702487726755364585539444568634831553677466219807626248052123664006059
Short name T101
Test name
Test status
Simulation time 351971476 ps
CPU time 5.15 seconds
Started Nov 22 01:18:33 PM PST 23
Finished Nov 22 01:18:40 PM PST 23
Peak memory 206520 kb
Host smart-be8bd15e-7e26-46c3-8478-e8b2e125632b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42307030702487726755364585539444568634831553677466219807626248052123664006059 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.42307030702487726755364585539444568634831553677466219807626248052123664006059
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.17721479581799303054756431036826973896262638707848863225955741237252205931601
Short name T167
Test name
Test status
Simulation time 26726680 ps
CPU time 0.89 seconds
Started Nov 22 01:18:34 PM PST 23
Finished Nov 22 01:18:37 PM PST 23
Peak memory 206460 kb
Host smart-10afd764-d275-4923-8a4d-bc27d16d3169
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17721479581799303054756431036826973896262638707848863225955741237252205931601 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.17721479581799303054756431036826973896262638707848863225955741237252205931601
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.29463809327006330500538593113055561090297498479952930248063181995683762840502
Short name T168
Test name
Test status
Simulation time 51163789 ps
CPU time 1.32 seconds
Started Nov 22 01:18:38 PM PST 23
Finished Nov 22 01:18:42 PM PST 23
Peak memory 214744 kb
Host smart-04fb8b32-7aac-4a11-a92c-99b50d8bc82a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946380932700633050053859311305556109029749
8479952930248063181995683762840502 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.2946380932700633050053859311
3055561090297498479952930248063181995683762840502
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.82091480362035424271561841174042582601859551668831001603249434578850193929404
Short name T228
Test name
Test status
Simulation time 23247569 ps
CPU time 0.83 seconds
Started Nov 22 01:18:32 PM PST 23
Finished Nov 22 01:18:35 PM PST 23
Peak memory 206512 kb
Host smart-296ee6a6-80f9-4da3-b0e9-716ece5a1ba9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82091480362035424271561841174042582601859551668831001603249434578850193929404 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.82091480362035424271561841174042582601859551668831001603249434578850193929404
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.13730817987789101810058154797245690657241256925830446104073447235151271901024
Short name T159
Test name
Test status
Simulation time 25518366 ps
CPU time 0.85 seconds
Started Nov 22 01:18:43 PM PST 23
Finished Nov 22 01:18:45 PM PST 23
Peak memory 206352 kb
Host smart-5ba06567-12a9-4408-b1b6-cfc97a858748
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13730817987789101810058154797245690657241256925830446104073447235151271901024 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 1.edn_intr_test.13730817987789101810058154797245690657241256925830446104073447235151271901024
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.6757469183396235832249315770363832984166284619181730933730353002984079044971
Short name T2
Test name
Test status
Simulation time 204078009 ps
CPU time 3.71 seconds
Started Nov 22 01:18:11 PM PST 23
Finished Nov 22 01:18:20 PM PST 23
Peak memory 214584 kb
Host smart-a44dd304-a028-45bf-9736-0400731c01e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6757469183396235832249315770363832984166284619181730933730353002984079044971 -assert nopostproc +UV
M_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.edn_tl_errors.6757469183396235832249315770363832984166284619181730933730353002984079044971
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.13113553843162634720067742155407211806423976954715400648859690451902990564314
Short name T227
Test name
Test status
Simulation time 51163789 ps
CPU time 1.3 seconds
Started Nov 22 01:18:39 PM PST 23
Finished Nov 22 01:18:42 PM PST 23
Peak memory 214720 kb
Host smart-695280bb-522c-47ae-8fa2-6e9495dcdf67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311355384316263472006774215540721180642397
6954715400648859690451902990564314 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.131135538431626347200677421
55407211806423976954715400648859690451902990564314
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.67352490663211045275496270037538166880515032507846943347064271914835762921208
Short name T124
Test name
Test status
Simulation time 23247569 ps
CPU time 0.86 seconds
Started Nov 22 01:18:35 PM PST 23
Finished Nov 22 01:18:39 PM PST 23
Peak memory 206372 kb
Host smart-fa7a76b4-e049-4182-9cb5-863e3d559b7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67352490663211045275496270037538166880515032507846943347064271914835762921208 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.67352490663211045275496270037538166880515032507846943347064271914835762921208
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.11142879014425344384076784358833547780241052578214206234784804194407178759762
Short name T84
Test name
Test status
Simulation time 25518366 ps
CPU time 0.85 seconds
Started Nov 22 01:19:03 PM PST 23
Finished Nov 22 01:19:06 PM PST 23
Peak memory 206272 kb
Host smart-9f9cdc6e-8b28-4d39-b427-fca52cd9e916
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11142879014425344384076784358833547780241052578214206234784804194407178759762 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 10.edn_intr_test.11142879014425344384076784358833547780241052578214206234784804194407178759762
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.22644056916129451986196439446591396830062508460718493243532175621092968051059
Short name T91
Test name
Test status
Simulation time 61976116 ps
CPU time 1.28 seconds
Started Nov 22 01:18:50 PM PST 23
Finished Nov 22 01:18:52 PM PST 23
Peak memory 206596 kb
Host smart-dae0dfc8-9721-4f00-b364-7da0de99f8a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22644056916129451986196439446591396830062508460718493243532175621092968051059
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_outstanding.22644056916129451986196439446591396830062508460718493243532175621092968051059
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.57768811202571053055405423696781588268692052787207382700391024744314061012623
Short name T222
Test name
Test status
Simulation time 204078009 ps
CPU time 3.75 seconds
Started Nov 22 01:19:02 PM PST 23
Finished Nov 22 01:19:06 PM PST 23
Peak memory 214732 kb
Host smart-df147eda-1a89-454e-85ff-a47ce48e9126
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57768811202571053055405423696781588268692052787207382700391024744314061012623 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 10.edn_tl_errors.57768811202571053055405423696781588268692052787207382700391024744314061012623
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.65696509977415937503068225407201710002845094546964259429274889920276165801061
Short name T121
Test name
Test status
Simulation time 155537119 ps
CPU time 2.19 seconds
Started Nov 22 01:18:56 PM PST 23
Finished Nov 22 01:19:00 PM PST 23
Peak memory 206572 kb
Host smart-8d3f990e-69a9-49c7-a63d-4300c1acfea0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65696509977415937503068225407201710002845094546964259429274889920276165801061 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.65696509977415937503068225407201710002845094546964259429274889920276165801061
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.31683307659035998249903505394862420060255915198765773328824640556883800680522
Short name T146
Test name
Test status
Simulation time 51163789 ps
CPU time 1.33 seconds
Started Nov 22 01:18:54 PM PST 23
Finished Nov 22 01:18:57 PM PST 23
Peak memory 214720 kb
Host smart-3770333e-2d70-49b4-aacb-5096489fd7e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168330765903599824990350539486242006025591
5198765773328824640556883800680522 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.316833076590359982499035053
94862420060255915198765773328824640556883800680522
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.50429676102602204805973596466434135415606486763439242521232213142434304901014
Short name T108
Test name
Test status
Simulation time 23247569 ps
CPU time 0.93 seconds
Started Nov 22 01:19:03 PM PST 23
Finished Nov 22 01:19:06 PM PST 23
Peak memory 206416 kb
Host smart-9b90bbb4-eea8-432d-8a8a-5ce9678843f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50429676102602204805973596466434135415606486763439242521232213142434304901014 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.50429676102602204805973596466434135415606486763439242521232213142434304901014
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.98541070494844951935355897364033938407856665320447573905425573825690229645231
Short name T157
Test name
Test status
Simulation time 25518366 ps
CPU time 0.83 seconds
Started Nov 22 01:18:36 PM PST 23
Finished Nov 22 01:18:40 PM PST 23
Peak memory 206392 kb
Host smart-f4d9f9a0-9483-43ae-9892-4eb310ea4e48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98541070494844951935355897364033938407856665320447573905425573825690229645231 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 11.edn_intr_test.98541070494844951935355897364033938407856665320447573905425573825690229645231
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.61900724238791070444058486402696030439632749509799209665802288692339164083881
Short name T49
Test name
Test status
Simulation time 61976116 ps
CPU time 1.29 seconds
Started Nov 22 01:18:37 PM PST 23
Finished Nov 22 01:18:42 PM PST 23
Peak memory 206580 kb
Host smart-dbdb2fb0-ecf8-43c6-86af-9ceb13033f57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61900724238791070444058486402696030439632749509799209665802288692339164083881
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_outstanding.61900724238791070444058486402696030439632749509799209665802288692339164083881
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.114687997283445432966662657767192231535330117819027137375564765611696087972871
Short name T8
Test name
Test status
Simulation time 204078009 ps
CPU time 3.49 seconds
Started Nov 22 01:19:05 PM PST 23
Finished Nov 22 01:19:13 PM PST 23
Peak memory 214716 kb
Host smart-d11956e4-613e-4883-8914-492cbff137ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114687997283445432966662657767192231535330117819027137375564765611696087972871 -assert nopostproc +
UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.edn_tl_errors.114687997283445432966662657767192231535330117819027137375564765611696087972871
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.92951768324363545149541449433868008841387444495022807868724259953833975883088
Short name T123
Test name
Test status
Simulation time 155537119 ps
CPU time 2.25 seconds
Started Nov 22 01:18:47 PM PST 23
Finished Nov 22 01:18:51 PM PST 23
Peak memory 206576 kb
Host smart-9d994039-58fc-4598-a5e4-db38bd8804e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92951768324363545149541449433868008841387444495022807868724259953833975883088 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.92951768324363545149541449433868008841387444495022807868724259953833975883088
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.52152793010878941071089825182186011153036555184848406917811243031634583090859
Short name T5
Test name
Test status
Simulation time 51163789 ps
CPU time 1.34 seconds
Started Nov 22 01:19:03 PM PST 23
Finished Nov 22 01:19:06 PM PST 23
Peak memory 214752 kb
Host smart-7dc75df0-0e0c-4df7-8cce-c9e2eb2024f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5215279301087894107108982518218601115303655
5184848406917811243031634583090859 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.521527930108789410710898251
82186011153036555184848406917811243031634583090859
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.67686142768629631530523921202560596918016891553527151963179269135086530846331
Short name T185
Test name
Test status
Simulation time 23247569 ps
CPU time 0.83 seconds
Started Nov 22 01:18:53 PM PST 23
Finished Nov 22 01:18:55 PM PST 23
Peak memory 206532 kb
Host smart-51bbf3a9-13be-4121-ae29-1975ce6c8782
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67686142768629631530523921202560596918016891553527151963179269135086530846331 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.67686142768629631530523921202560596918016891553527151963179269135086530846331
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.69189952449682286451996054816318974435835015752781485692136918863360342782134
Short name T232
Test name
Test status
Simulation time 25518366 ps
CPU time 0.86 seconds
Started Nov 22 01:19:01 PM PST 23
Finished Nov 22 01:19:03 PM PST 23
Peak memory 206308 kb
Host smart-afaaf0b4-ee79-4684-a72c-b31116e658b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69189952449682286451996054816318974435835015752781485692136918863360342782134 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 12.edn_intr_test.69189952449682286451996054816318974435835015752781485692136918863360342782134
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.28151954420421135926877833718828115698592873471331457200445287898385168530842
Short name T230
Test name
Test status
Simulation time 61976116 ps
CPU time 1.27 seconds
Started Nov 22 01:19:03 PM PST 23
Finished Nov 22 01:19:08 PM PST 23
Peak memory 206480 kb
Host smart-db92f487-b08e-405f-9618-3cbf43ea5631
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28151954420421135926877833718828115698592873471331457200445287898385168530842
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_outstanding.28151954420421135926877833718828115698592873471331457200445287898385168530842
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.68818286606749778773663756646375610152317576236872357854554975756449237236395
Short name T3
Test name
Test status
Simulation time 204078009 ps
CPU time 3.66 seconds
Started Nov 22 01:18:50 PM PST 23
Finished Nov 22 01:18:56 PM PST 23
Peak memory 214756 kb
Host smart-81214f28-8aea-4f4b-b985-7188e0b95ecc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68818286606749778773663756646375610152317576236872357854554975756449237236395 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 12.edn_tl_errors.68818286606749778773663756646375610152317576236872357854554975756449237236395
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.41873269859822030302211788713489153990414988228055749023888105400661406439694
Short name T180
Test name
Test status
Simulation time 155537119 ps
CPU time 2.26 seconds
Started Nov 22 01:19:05 PM PST 23
Finished Nov 22 01:19:11 PM PST 23
Peak memory 206596 kb
Host smart-6677cc55-82c8-4587-a744-ea4a0cbba318
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41873269859822030302211788713489153990414988228055749023888105400661406439694 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.41873269859822030302211788713489153990414988228055749023888105400661406439694
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.40889601211930528472232802595759944710607101271313069258463313224861856615385
Short name T6
Test name
Test status
Simulation time 51163789 ps
CPU time 1.25 seconds
Started Nov 22 01:19:08 PM PST 23
Finished Nov 22 01:19:13 PM PST 23
Peak memory 214772 kb
Host smart-d7c1a9db-678b-47d2-95fc-ae9543c56160
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088960121193052847223280259575994471060710
1271313069258463313224861856615385 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.408896012119305284722328025
95759944710607101271313069258463313224861856615385
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.57400276179380473937492119156847465164714519594974613051921183898165821122395
Short name T109
Test name
Test status
Simulation time 23247569 ps
CPU time 0.84 seconds
Started Nov 22 01:18:52 PM PST 23
Finished Nov 22 01:18:54 PM PST 23
Peak memory 206488 kb
Host smart-4297d535-cf24-4a82-b02b-49b3cb47b9dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57400276179380473937492119156847465164714519594974613051921183898165821122395 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.57400276179380473937492119156847465164714519594974613051921183898165821122395
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.74355592324066968672728573556993595234035099600254165853497208418664842110300
Short name T158
Test name
Test status
Simulation time 25518366 ps
CPU time 0.87 seconds
Started Nov 22 01:18:53 PM PST 23
Finished Nov 22 01:18:55 PM PST 23
Peak memory 206320 kb
Host smart-3f385cfe-8af2-4467-9791-fcb6784b728a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74355592324066968672728573556993595234035099600254165853497208418664842110300 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 13.edn_intr_test.74355592324066968672728573556993595234035099600254165853497208418664842110300
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.66953959084853240111446578757323035008176405332256329873495795118993936951034
Short name T88
Test name
Test status
Simulation time 61976116 ps
CPU time 1.28 seconds
Started Nov 22 01:18:53 PM PST 23
Finished Nov 22 01:18:55 PM PST 23
Peak memory 206512 kb
Host smart-cc10f0f8-7a29-438d-9343-233a910abedb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66953959084853240111446578757323035008176405332256329873495795118993936951034
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_outstanding.66953959084853240111446578757323035008176405332256329873495795118993936951034
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.98050289491362843752265279756718080789321001137986792813071491471732607900872
Short name T142
Test name
Test status
Simulation time 204078009 ps
CPU time 3.63 seconds
Started Nov 22 01:18:52 PM PST 23
Finished Nov 22 01:18:57 PM PST 23
Peak memory 214684 kb
Host smart-693729ed-c1f9-4d52-b2fe-68f575045b43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98050289491362843752265279756718080789321001137986792813071491471732607900872 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 13.edn_tl_errors.98050289491362843752265279756718080789321001137986792813071491471732607900872
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.47256632080275469251997638774773725504465220105645338662145542507552539797115
Short name T106
Test name
Test status
Simulation time 155537119 ps
CPU time 2.21 seconds
Started Nov 22 01:18:53 PM PST 23
Finished Nov 22 01:18:56 PM PST 23
Peak memory 206564 kb
Host smart-011953f0-cc15-472f-84f9-c536ab231e66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47256632080275469251997638774773725504465220105645338662145542507552539797115 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.47256632080275469251997638774773725504465220105645338662145542507552539797115
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.91193953508910535413142704033358710084614697524292093950052719890768218032706
Short name T114
Test name
Test status
Simulation time 51163789 ps
CPU time 1.24 seconds
Started Nov 22 01:18:58 PM PST 23
Finished Nov 22 01:19:02 PM PST 23
Peak memory 214760 kb
Host smart-afda0863-b1a5-4af0-bd81-10580eff9211
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9119395350891053541314270403335871008461469
7524292093950052719890768218032706 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.911939535089105354131427040
33358710084614697524292093950052719890768218032706
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.90382440953073378676628893714575593750462244594146997129884224086041399100738
Short name T129
Test name
Test status
Simulation time 23247569 ps
CPU time 0.85 seconds
Started Nov 22 01:18:51 PM PST 23
Finished Nov 22 01:18:54 PM PST 23
Peak memory 206400 kb
Host smart-077073e9-9cc5-4377-89ad-53b57f499a49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90382440953073378676628893714575593750462244594146997129884224086041399100738 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.90382440953073378676628893714575593750462244594146997129884224086041399100738
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.111819632118377663023692552985709223370254777856931709186890169150331701090047
Short name T199
Test name
Test status
Simulation time 25518366 ps
CPU time 0.85 seconds
Started Nov 22 01:18:52 PM PST 23
Finished Nov 22 01:18:54 PM PST 23
Peak memory 206268 kb
Host smart-924a53bc-8970-4b9a-965c-05901d41b6ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111819632118377663023692552985709223370254777856931709186890169150331701090047 -assert nopostproc +
UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.edn_intr_test.111819632118377663023692552985709223370254777856931709186890169150331701090047
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.28221967928078956856224429799714258458749436535913335474259620156335715103026
Short name T81
Test name
Test status
Simulation time 61976116 ps
CPU time 1.31 seconds
Started Nov 22 01:19:01 PM PST 23
Finished Nov 22 01:19:04 PM PST 23
Peak memory 206568 kb
Host smart-4546fd22-2481-43be-97b8-fce632266e98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28221967928078956856224429799714258458749436535913335474259620156335715103026
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_outstanding.28221967928078956856224429799714258458749436535913335474259620156335715103026
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.51882083469827950370386484599414230997501242613293905475023915110878824906419
Short name T203
Test name
Test status
Simulation time 204078009 ps
CPU time 3.84 seconds
Started Nov 22 01:19:05 PM PST 23
Finished Nov 22 01:19:13 PM PST 23
Peak memory 214708 kb
Host smart-22287cbd-b084-4758-88b4-472c8aefa32b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51882083469827950370386484599414230997501242613293905475023915110878824906419 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 14.edn_tl_errors.51882083469827950370386484599414230997501242613293905475023915110878824906419
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.77519494290000492589492451953693807933784283401573606232508070053504086293763
Short name T205
Test name
Test status
Simulation time 155537119 ps
CPU time 2.12 seconds
Started Nov 22 01:18:53 PM PST 23
Finished Nov 22 01:18:57 PM PST 23
Peak memory 206344 kb
Host smart-c0f0d4be-6bec-4df4-9e80-14babe272619
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77519494290000492589492451953693807933784283401573606232508070053504086293763 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.77519494290000492589492451953693807933784283401573606232508070053504086293763
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.108789345319644422281829360601574265313132550673110652661249044872595509255338
Short name T148
Test name
Test status
Simulation time 51163789 ps
CPU time 1.25 seconds
Started Nov 22 01:19:06 PM PST 23
Finished Nov 22 01:19:12 PM PST 23
Peak memory 214660 kb
Host smart-e5c9ead5-c5fa-4989-874a-ee70d65d6603
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087893453196444222818293606015742653131325
50673110652661249044872595509255338 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.10878934531964442228182936
0601574265313132550673110652661249044872595509255338
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.88682239835040312773874375160108700021732070881643223765333472481984686265459
Short name T187
Test name
Test status
Simulation time 23247569 ps
CPU time 0.86 seconds
Started Nov 22 01:19:08 PM PST 23
Finished Nov 22 01:19:13 PM PST 23
Peak memory 206424 kb
Host smart-6d172eb8-b661-430f-ab7d-b6e5a3119ef3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88682239835040312773874375160108700021732070881643223765333472481984686265459 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.88682239835040312773874375160108700021732070881643223765333472481984686265459
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.36879223240265411706676225229424601790551650370261144569111388734300016262982
Short name T128
Test name
Test status
Simulation time 25518366 ps
CPU time 0.86 seconds
Started Nov 22 01:19:04 PM PST 23
Finished Nov 22 01:19:09 PM PST 23
Peak memory 206408 kb
Host smart-b350fa30-bfdc-448a-bd58-fbf56f249d43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36879223240265411706676225229424601790551650370261144569111388734300016262982 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 15.edn_intr_test.36879223240265411706676225229424601790551650370261144569111388734300016262982
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.9458272992308443190576413280415891674295457737370202995532449563821283695759
Short name T209
Test name
Test status
Simulation time 61976116 ps
CPU time 1.33 seconds
Started Nov 22 01:19:07 PM PST 23
Finished Nov 22 01:19:12 PM PST 23
Peak memory 206572 kb
Host smart-0c241006-b1ed-4a07-aa60-55972085cc8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9458272992308443190576413280415891674295457737370202995532449563821283695759 -
assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_outstanding.9458272992308443190576413280415891674295457737370202995532449563821283695759
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.34992605182081099570649613243904863953397688868944826895590498128165253953030
Short name T170
Test name
Test status
Simulation time 204078009 ps
CPU time 3.62 seconds
Started Nov 22 01:19:05 PM PST 23
Finished Nov 22 01:19:13 PM PST 23
Peak memory 214720 kb
Host smart-f023bda1-c548-4282-b138-e244f30ca9dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34992605182081099570649613243904863953397688868944826895590498128165253953030 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 15.edn_tl_errors.34992605182081099570649613243904863953397688868944826895590498128165253953030
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.14241105628870885228746909501781982980142651310772832659459831327447153785079
Short name T136
Test name
Test status
Simulation time 155537119 ps
CPU time 2.54 seconds
Started Nov 22 01:19:03 PM PST 23
Finished Nov 22 01:19:07 PM PST 23
Peak memory 206576 kb
Host smart-8b9503ea-4e96-4f9f-9102-16774dc7343d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14241105628870885228746909501781982980142651310772832659459831327447153785079 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.14241105628870885228746909501781982980142651310772832659459831327447153785079
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.11162523162896942797371605961153922466102981094570221003024872350560856999808
Short name T175
Test name
Test status
Simulation time 51163789 ps
CPU time 1.25 seconds
Started Nov 22 01:19:23 PM PST 23
Finished Nov 22 01:19:25 PM PST 23
Peak memory 214800 kb
Host smart-0b3f17aa-7205-47c9-83d3-adbf86794872
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116252316289694279737160596115392246610298
1094570221003024872350560856999808 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.111625231628969427973716059
61153922466102981094570221003024872350560856999808
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.104336857386838514629255555511049623927491872652556393547190952570475871913219
Short name T137
Test name
Test status
Simulation time 23247569 ps
CPU time 0.82 seconds
Started Nov 22 01:19:15 PM PST 23
Finished Nov 22 01:19:18 PM PST 23
Peak memory 206512 kb
Host smart-e97712d0-5dfd-41ce-af2d-59926a397d0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104336857386838514629255555511049623927491872652556393547190952570475871913219 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.104336857386838514629255555511049623927491872652556393547190952570475871913219
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.76811966869220348426395838831231096246479436463668590169486581334276094870457
Short name T234
Test name
Test status
Simulation time 25518366 ps
CPU time 0.87 seconds
Started Nov 22 01:19:04 PM PST 23
Finished Nov 22 01:19:08 PM PST 23
Peak memory 206360 kb
Host smart-9ba8d32b-9dd2-469e-8fa5-76a36ff24d34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76811966869220348426395838831231096246479436463668590169486581334276094870457 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 16.edn_intr_test.76811966869220348426395838831231096246479436463668590169486581334276094870457
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.38398850836609042436689008707709027351900649569443056438782693811736756958992
Short name T90
Test name
Test status
Simulation time 61976116 ps
CPU time 1.3 seconds
Started Nov 22 01:19:27 PM PST 23
Finished Nov 22 01:19:29 PM PST 23
Peak memory 206520 kb
Host smart-ea5f88df-964b-46d2-8241-4764c7c53574
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38398850836609042436689008707709027351900649569443056438782693811736756958992
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_outstanding.38398850836609042436689008707709027351900649569443056438782693811736756958992
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.79048643707699062168450017633476225179130733975216683030566721964150510002099
Short name T105
Test name
Test status
Simulation time 204078009 ps
CPU time 3.44 seconds
Started Nov 22 01:19:09 PM PST 23
Finished Nov 22 01:19:16 PM PST 23
Peak memory 214572 kb
Host smart-a8e93048-272f-4802-9033-47613b2fc2d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79048643707699062168450017633476225179130733975216683030566721964150510002099 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 16.edn_tl_errors.79048643707699062168450017633476225179130733975216683030566721964150510002099
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.93359234499476322151824059817093513741464099817171721887931442901172595637379
Short name T145
Test name
Test status
Simulation time 155537119 ps
CPU time 2.21 seconds
Started Nov 22 01:19:04 PM PST 23
Finished Nov 22 01:19:10 PM PST 23
Peak memory 206528 kb
Host smart-2e8350c1-288e-476e-93bc-490cd5c56aa2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93359234499476322151824059817093513741464099817171721887931442901172595637379 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.93359234499476322151824059817093513741464099817171721887931442901172595637379
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.81643301373221579792971001240504893478634572792657331523631047975693709982897
Short name T156
Test name
Test status
Simulation time 51163789 ps
CPU time 1.27 seconds
Started Nov 22 01:19:26 PM PST 23
Finished Nov 22 01:19:29 PM PST 23
Peak memory 214776 kb
Host smart-32c658f6-414d-4044-aa03-01b796b4ff22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8164330137322157979297100124050489347863457
2792657331523631047975693709982897 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.816433013732215797929710012
40504893478634572792657331523631047975693709982897
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.81359076155018834287048435721582835025597922818697656822482016169078104439794
Short name T50
Test name
Test status
Simulation time 23247569 ps
CPU time 0.83 seconds
Started Nov 22 01:19:29 PM PST 23
Finished Nov 22 01:19:33 PM PST 23
Peak memory 206480 kb
Host smart-df342988-b2d0-4ce2-820c-cedb8f1bbc31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81359076155018834287048435721582835025597922818697656822482016169078104439794 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.81359076155018834287048435721582835025597922818697656822482016169078104439794
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.92426506439726226687478414699010440989698330755222543127664647321364052852931
Short name T116
Test name
Test status
Simulation time 25518366 ps
CPU time 0.87 seconds
Started Nov 22 01:19:06 PM PST 23
Finished Nov 22 01:19:11 PM PST 23
Peak memory 206380 kb
Host smart-3413e3ec-0773-4253-aebe-4815295f77f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92426506439726226687478414699010440989698330755222543127664647321364052852931 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 17.edn_intr_test.92426506439726226687478414699010440989698330755222543127664647321364052852931
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.10581379160767486390487732601023947738051401551533346684542985921987373761454
Short name T233
Test name
Test status
Simulation time 61976116 ps
CPU time 1.24 seconds
Started Nov 22 01:19:25 PM PST 23
Finished Nov 22 01:19:27 PM PST 23
Peak memory 206596 kb
Host smart-34820d8a-3349-4303-8f03-74f45e15485c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10581379160767486390487732601023947738051401551533346684542985921987373761454
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_outstanding.10581379160767486390487732601023947738051401551533346684542985921987373761454
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.25419237235472104394755661550733741796203196535259402877270792852823368906371
Short name T135
Test name
Test status
Simulation time 204078009 ps
CPU time 3.57 seconds
Started Nov 22 01:19:14 PM PST 23
Finished Nov 22 01:19:19 PM PST 23
Peak memory 214724 kb
Host smart-bbf5bbbc-6517-46fe-95ad-9bcff0b036af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25419237235472104394755661550733741796203196535259402877270792852823368906371 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 17.edn_tl_errors.25419237235472104394755661550733741796203196535259402877270792852823368906371
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.4796821067639699377037490158238227715784684047977991703665882245269527504209
Short name T225
Test name
Test status
Simulation time 155537119 ps
CPU time 2.13 seconds
Started Nov 22 01:19:26 PM PST 23
Finished Nov 22 01:19:30 PM PST 23
Peak memory 206584 kb
Host smart-86429ee4-89fd-4e7f-be7a-16ca7ae965cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4796821067639699377037490158238227715784684047977991703665882245269527504209 -assert no
postproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.4796821067639699377037490158238227715784684047977991703665882245269527504209
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.51880004803025482422654100047701973847128183817138576438025549332989772141276
Short name T151
Test name
Test status
Simulation time 51163789 ps
CPU time 1.29 seconds
Started Nov 22 01:19:36 PM PST 23
Finished Nov 22 01:19:43 PM PST 23
Peak memory 214752 kb
Host smart-5fa0e227-f784-43f2-a25d-0d7341d1d58c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5188000480302548242265410004770197384712818
3817138576438025549332989772141276 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.518800048030254824226541000
47701973847128183817138576438025549332989772141276
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.110166578512079439145505664174623650409774006091225629319577576228174062837700
Short name T231
Test name
Test status
Simulation time 23247569 ps
CPU time 0.83 seconds
Started Nov 22 01:19:29 PM PST 23
Finished Nov 22 01:19:32 PM PST 23
Peak memory 206344 kb
Host smart-7d52186e-e690-417c-b5a9-5e18a7810f33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110166578512079439145505664174623650409774006091225629319577576228174062837700 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.110166578512079439145505664174623650409774006091225629319577576228174062837700
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.91108972539465867433858023765710618598218018452541877104721389470391618818829
Short name T235
Test name
Test status
Simulation time 25518366 ps
CPU time 0.82 seconds
Started Nov 22 01:19:39 PM PST 23
Finished Nov 22 01:19:46 PM PST 23
Peak memory 206412 kb
Host smart-7ad41926-1dda-4d8f-8ef1-2409bff4bd16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91108972539465867433858023765710618598218018452541877104721389470391618818829 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 18.edn_intr_test.91108972539465867433858023765710618598218018452541877104721389470391618818829
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.63358555577215168263499184491391117542394445557043225236066362236464923032065
Short name T15
Test name
Test status
Simulation time 61976116 ps
CPU time 1.31 seconds
Started Nov 22 01:19:08 PM PST 23
Finished Nov 22 01:19:13 PM PST 23
Peak memory 206512 kb
Host smart-0e372b5c-065e-471c-8b6e-ffde834beeb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63358555577215168263499184491391117542394445557043225236066362236464923032065
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_outstanding.63358555577215168263499184491391117542394445557043225236066362236464923032065
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.50110479836709664785685275118728720357571951777804410890023135321363099983370
Short name T104
Test name
Test status
Simulation time 204078009 ps
CPU time 3.74 seconds
Started Nov 22 01:19:07 PM PST 23
Finished Nov 22 01:19:15 PM PST 23
Peak memory 214572 kb
Host smart-c52af50c-dcaa-4c84-9932-4731e3927fed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50110479836709664785685275118728720357571951777804410890023135321363099983370 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 18.edn_tl_errors.50110479836709664785685275118728720357571951777804410890023135321363099983370
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.4208607627268715531848914852293253194936859785277292400819251230995734445886
Short name T4
Test name
Test status
Simulation time 155537119 ps
CPU time 2.19 seconds
Started Nov 22 01:19:28 PM PST 23
Finished Nov 22 01:19:33 PM PST 23
Peak memory 206560 kb
Host smart-e67e9e56-9539-45d6-bc68-c3bf3a3f4734
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208607627268715531848914852293253194936859785277292400819251230995734445886 -assert no
postproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.4208607627268715531848914852293253194936859785277292400819251230995734445886
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.52987293010270265420231099930043910442556683539167343284749420056623614324678
Short name T208
Test name
Test status
Simulation time 51163789 ps
CPU time 1.19 seconds
Started Nov 22 01:19:35 PM PST 23
Finished Nov 22 01:19:42 PM PST 23
Peak memory 214616 kb
Host smart-7d95b14c-c439-4064-b4ce-aeb5035e6532
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5298729301027026542023109993004391044255668
3539167343284749420056623614324678 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.529872930102702654202310999
30043910442556683539167343284749420056623614324678
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.83664071808700412251885341489530375827920223290043270960002463065488596503401
Short name T86
Test name
Test status
Simulation time 23247569 ps
CPU time 0.83 seconds
Started Nov 22 01:19:33 PM PST 23
Finished Nov 22 01:19:38 PM PST 23
Peak memory 206452 kb
Host smart-1e17b231-dbde-46cc-a82d-800ba5274264
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83664071808700412251885341489530375827920223290043270960002463065488596503401 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.83664071808700412251885341489530375827920223290043270960002463065488596503401
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.46510729380011771090115082641970547799480743216793871960619271019025484071951
Short name T224
Test name
Test status
Simulation time 25518366 ps
CPU time 0.82 seconds
Started Nov 22 01:19:37 PM PST 23
Finished Nov 22 01:19:44 PM PST 23
Peak memory 206268 kb
Host smart-8081e511-6a68-4c2e-acc1-883822fdff51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46510729380011771090115082641970547799480743216793871960619271019025484071951 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 19.edn_intr_test.46510729380011771090115082641970547799480743216793871960619271019025484071951
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.35705848329988413194391306067345558755764240464504528603562334509697361196701
Short name T198
Test name
Test status
Simulation time 61976116 ps
CPU time 1.33 seconds
Started Nov 22 01:19:35 PM PST 23
Finished Nov 22 01:19:42 PM PST 23
Peak memory 206548 kb
Host smart-84bc263b-0719-4337-8423-a63e2f403591
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35705848329988413194391306067345558755764240464504528603562334509697361196701
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_outstanding.35705848329988413194391306067345558755764240464504528603562334509697361196701
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.40709794514304265762801913880938229802090984685113612172133452830991601899178
Short name T166
Test name
Test status
Simulation time 204078009 ps
CPU time 3.69 seconds
Started Nov 22 01:19:28 PM PST 23
Finished Nov 22 01:19:35 PM PST 23
Peak memory 214752 kb
Host smart-2e8e6179-6335-42ac-b1f4-f11f7a3c2cf9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40709794514304265762801913880938229802090984685113612172133452830991601899178 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 19.edn_tl_errors.40709794514304265762801913880938229802090984685113612172133452830991601899178
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.83497820808023502781202524264423227543952653459094282776992897450579100432158
Short name T80
Test name
Test status
Simulation time 155537119 ps
CPU time 2.32 seconds
Started Nov 22 01:19:33 PM PST 23
Finished Nov 22 01:19:39 PM PST 23
Peak memory 206536 kb
Host smart-896424b1-4bf1-4e15-bf88-ebfdc167c64f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83497820808023502781202524264423227543952653459094282776992897450579100432158 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.83497820808023502781202524264423227543952653459094282776992897450579100432158
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.73630312342736069318382284860942283525375499365334402832707167491253465637246
Short name T206
Test name
Test status
Simulation time 59184494 ps
CPU time 1.38 seconds
Started Nov 22 01:18:43 PM PST 23
Finished Nov 22 01:18:46 PM PST 23
Peak memory 206340 kb
Host smart-f5467fee-feff-494e-b6cb-a2adeaf1f542
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73630312342736069318382284860942283525375499365334402832707167491253465637246 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.73630312342736069318382284860942283525375499365334402832707167491253465637246
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.18670086576637354017950164443622377270493725882899218061918241050422111855810
Short name T219
Test name
Test status
Simulation time 351971476 ps
CPU time 5.33 seconds
Started Nov 22 01:19:04 PM PST 23
Finished Nov 22 01:19:13 PM PST 23
Peak memory 206484 kb
Host smart-dba89209-972a-4d3f-992a-107f803c9d50
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18670086576637354017950164443622377270493725882899218061918241050422111855810 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.18670086576637354017950164443622377270493725882899218061918241050422111855810
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.11177628055633276125492163481329002162967733755219421698515576113633328534197
Short name T189
Test name
Test status
Simulation time 26726680 ps
CPU time 0.85 seconds
Started Nov 22 01:18:40 PM PST 23
Finished Nov 22 01:18:42 PM PST 23
Peak memory 206368 kb
Host smart-39d702e3-1590-43b2-992c-f67315814e73
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11177628055633276125492163481329002162967733755219421698515576113633328534197 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.11177628055633276125492163481329002162967733755219421698515576113633328534197
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.102183965317776283679657901161225332541204814548910009795241678359520181060562
Short name T112
Test name
Test status
Simulation time 51163789 ps
CPU time 1.26 seconds
Started Nov 22 01:18:32 PM PST 23
Finished Nov 22 01:18:35 PM PST 23
Peak memory 214804 kb
Host smart-e87387fe-9d72-4681-95b8-a2c20c98b51b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021839653177762836796579011612253325412048
14548910009795241678359520181060562 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.102183965317776283679657901
161225332541204814548910009795241678359520181060562
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.93103007787246722151958549637490073096405984498270954972864694688958007948141
Short name T162
Test name
Test status
Simulation time 23247569 ps
CPU time 0.88 seconds
Started Nov 22 01:18:42 PM PST 23
Finished Nov 22 01:18:45 PM PST 23
Peak memory 206448 kb
Host smart-66b2209d-6f02-4342-9750-2d83032781ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93103007787246722151958549637490073096405984498270954972864694688958007948141 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.93103007787246722151958549637490073096405984498270954972864694688958007948141
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.100061245552028510745736815757349985529865155456289541017099514013098494144989
Short name T122
Test name
Test status
Simulation time 25518366 ps
CPU time 0.85 seconds
Started Nov 22 01:18:42 PM PST 23
Finished Nov 22 01:18:45 PM PST 23
Peak memory 206248 kb
Host smart-4a0fd6e1-ec0a-4f8f-bce4-328a85c425bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100061245552028510745736815757349985529865155456289541017099514013098494144989 -assert nopostproc +
UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.edn_intr_test.100061245552028510745736815757349985529865155456289541017099514013098494144989
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.113730660421595833438405656985920640581217117892222730840790913667994695398678
Short name T83
Test name
Test status
Simulation time 61976116 ps
CPU time 1.32 seconds
Started Nov 22 01:19:12 PM PST 23
Finished Nov 22 01:19:15 PM PST 23
Peak memory 206572 kb
Host smart-1bdb65e2-587e-450e-b5c0-d7cf7e25ccb0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113730660421595833438405656985920640581217117892222730840790913667994695398678
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_outstanding.113730660421595833438405656985920640581217117892222730840790913667994695398678
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.48288760229335931350822819910542812601555369988651571739311298840622763477787
Short name T161
Test name
Test status
Simulation time 204078009 ps
CPU time 3.73 seconds
Started Nov 22 01:18:36 PM PST 23
Finished Nov 22 01:18:42 PM PST 23
Peak memory 214752 kb
Host smart-72174590-b73d-4737-ace3-8b8c4cd87e73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48288760229335931350822819910542812601555369988651571739311298840622763477787 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 2.edn_tl_errors.48288760229335931350822819910542812601555369988651571739311298840622763477787
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.66468573975899011391645539738701237285145457536411276767160181235615925760581
Short name T183
Test name
Test status
Simulation time 155537119 ps
CPU time 2.29 seconds
Started Nov 22 01:18:35 PM PST 23
Finished Nov 22 01:18:39 PM PST 23
Peak memory 206520 kb
Host smart-23f5ac42-456c-41e6-9b01-2aef51f2b5fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66468573975899011391645539738701237285145457536411276767160181235615925760581 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.66468573975899011391645539738701237285145457536411276767160181235615925760581
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.69668523313286966318635131918032000307683910062914157601611713494463321435274
Short name T178
Test name
Test status
Simulation time 25518366 ps
CPU time 0.86 seconds
Started Nov 22 01:19:35 PM PST 23
Finished Nov 22 01:19:42 PM PST 23
Peak memory 206328 kb
Host smart-6bada69d-93dd-4c5c-a1ba-be1216f0a457
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69668523313286966318635131918032000307683910062914157601611713494463321435274 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 20.edn_intr_test.69668523313286966318635131918032000307683910062914157601611713494463321435274
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.50509327633386325338522769875602446278337404435208557173170344132939041076152
Short name T192
Test name
Test status
Simulation time 25518366 ps
CPU time 0.81 seconds
Started Nov 22 01:19:37 PM PST 23
Finished Nov 22 01:19:44 PM PST 23
Peak memory 206272 kb
Host smart-caf6bad9-d21e-4da0-bad3-d77908af7257
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50509327633386325338522769875602446278337404435208557173170344132939041076152 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 21.edn_intr_test.50509327633386325338522769875602446278337404435208557173170344132939041076152
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.53694926208519598635124007197344692455018676509992200754221818450400018392371
Short name T51
Test name
Test status
Simulation time 25518366 ps
CPU time 0.84 seconds
Started Nov 22 01:19:42 PM PST 23
Finished Nov 22 01:19:49 PM PST 23
Peak memory 206336 kb
Host smart-b35c7cc0-c5e0-47ad-ae62-0f01f8ad4d47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53694926208519598635124007197344692455018676509992200754221818450400018392371 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 22.edn_intr_test.53694926208519598635124007197344692455018676509992200754221818450400018392371
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.1717427290275042492369824494223543434457260378674820400273300596830963375275
Short name T110
Test name
Test status
Simulation time 25518366 ps
CPU time 0.82 seconds
Started Nov 22 01:19:40 PM PST 23
Finished Nov 22 01:19:47 PM PST 23
Peak memory 206336 kb
Host smart-95b8634e-6767-4c2b-abac-bdf38f53aeb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717427290275042492369824494223543434457260378674820400273300596830963375275 -assert nopostproc +UV
M_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 23.edn_intr_test.1717427290275042492369824494223543434457260378674820400273300596830963375275
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.35360609186285130555993086130606957782774486729880313384218609382281515331437
Short name T163
Test name
Test status
Simulation time 25518366 ps
CPU time 0.83 seconds
Started Nov 22 01:19:37 PM PST 23
Finished Nov 22 01:19:43 PM PST 23
Peak memory 206268 kb
Host smart-c929df6f-7a39-4b79-a4b3-7f0761e2091a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35360609186285130555993086130606957782774486729880313384218609382281515331437 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 24.edn_intr_test.35360609186285130555993086130606957782774486729880313384218609382281515331437
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.114754067961957959373142570314386094924232182360766755520610561123166804187256
Short name T226
Test name
Test status
Simulation time 25518366 ps
CPU time 0.84 seconds
Started Nov 22 01:19:43 PM PST 23
Finished Nov 22 01:19:50 PM PST 23
Peak memory 206368 kb
Host smart-a044d41b-461e-4a2f-a1fd-dbd32274ef6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114754067961957959373142570314386094924232182360766755520610561123166804187256 -assert nopostproc +
UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 25.edn_intr_test.114754067961957959373142570314386094924232182360766755520610561123166804187256
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.82514734054100709480396531265025719152167184127526598018320876231776551381659
Short name T143
Test name
Test status
Simulation time 25518366 ps
CPU time 0.84 seconds
Started Nov 22 01:19:46 PM PST 23
Finished Nov 22 01:19:52 PM PST 23
Peak memory 206344 kb
Host smart-4add0bce-585b-4d23-91c9-0be4a14570bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82514734054100709480396531265025719152167184127526598018320876231776551381659 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 26.edn_intr_test.82514734054100709480396531265025719152167184127526598018320876231776551381659
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.70575464053026256757364851819931108040206302940362212604396105713602634347023
Short name T190
Test name
Test status
Simulation time 25518366 ps
CPU time 0.9 seconds
Started Nov 22 01:19:46 PM PST 23
Finished Nov 22 01:19:52 PM PST 23
Peak memory 206340 kb
Host smart-8f70e059-2085-485d-9665-52391e74a668
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70575464053026256757364851819931108040206302940362212604396105713602634347023 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 27.edn_intr_test.70575464053026256757364851819931108040206302940362212604396105713602634347023
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.7442136747190346094290563931945366188562888722588845334641160690059891849060
Short name T195
Test name
Test status
Simulation time 25518366 ps
CPU time 0.86 seconds
Started Nov 22 01:19:36 PM PST 23
Finished Nov 22 01:19:43 PM PST 23
Peak memory 206220 kb
Host smart-b72722c2-ba33-40d7-a025-a25594b594d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7442136747190346094290563931945366188562888722588845334641160690059891849060 -assert nopostproc +UV
M_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 28.edn_intr_test.7442136747190346094290563931945366188562888722588845334641160690059891849060
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.39499112605769823763625917087611964435720095124964624815650772597043907130161
Short name T220
Test name
Test status
Simulation time 25518366 ps
CPU time 0.85 seconds
Started Nov 22 01:19:52 PM PST 23
Finished Nov 22 01:19:57 PM PST 23
Peak memory 206328 kb
Host smart-afe4881e-90f4-463a-81aa-3e1726c2ae48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39499112605769823763625917087611964435720095124964624815650772597043907130161 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 29.edn_intr_test.39499112605769823763625917087611964435720095124964624815650772597043907130161
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.103547891924247245395228278590365901312697203738177818757418725976121341284747
Short name T196
Test name
Test status
Simulation time 59184494 ps
CPU time 1.34 seconds
Started Nov 22 01:19:02 PM PST 23
Finished Nov 22 01:19:05 PM PST 23
Peak memory 206556 kb
Host smart-eaf7ecdc-35b1-4b42-888d-23a18b47a4b7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103547891924247245395228278590365901312697203738177818757418725976121341284747 -assert nop
ostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.103547891924247245395228278590365901312697203738177818757418725976121341284747
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.73281030057299302092004735745914692946574866132844328682489310806738217117913
Short name T179
Test name
Test status
Simulation time 351971476 ps
CPU time 4.92 seconds
Started Nov 22 01:18:31 PM PST 23
Finished Nov 22 01:18:37 PM PST 23
Peak memory 206424 kb
Host smart-0f0d36a3-a0e9-4ed0-8138-3a3063932835
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73281030057299302092004735745914692946574866132844328682489310806738217117913 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.73281030057299302092004735745914692946574866132844328682489310806738217117913
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.6897711114398081376189177556305611449845120430615522974817283116453737942675
Short name T218
Test name
Test status
Simulation time 26726680 ps
CPU time 0.85 seconds
Started Nov 22 01:18:34 PM PST 23
Finished Nov 22 01:18:37 PM PST 23
Peak memory 206400 kb
Host smart-7218dc31-48e9-44a0-b86b-b9dca071e7d5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6897711114398081376189177556305611449845120430615522974817283116453737942675 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.6897711114398081376189177556305611449845120430615522974817283116453737942675
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.42599195271479004557982544153870780831553599657589983232818496202398670030339
Short name T131
Test name
Test status
Simulation time 51163789 ps
CPU time 1.26 seconds
Started Nov 22 01:18:31 PM PST 23
Finished Nov 22 01:18:34 PM PST 23
Peak memory 214672 kb
Host smart-660fe524-5dc0-43ba-b01a-42c2dd257a5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259919527147900455798254415387078083155359
9657589983232818496202398670030339 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.4259919527147900455798254415
3870780831553599657589983232818496202398670030339
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.2715789011819007922203458820145691536673857277310109197254400722694182887573
Short name T184
Test name
Test status
Simulation time 23247569 ps
CPU time 0.82 seconds
Started Nov 22 01:18:34 PM PST 23
Finished Nov 22 01:18:37 PM PST 23
Peak memory 206540 kb
Host smart-8cd439cd-4689-43d8-a511-114a9f334b0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715789011819007922203458820145691536673857277310109197254400722694182887573 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.2715789011819007922203458820145691536673857277310109197254400722694182887573
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.51147863562846254200574962480419044998836132099671741600221546645433383891204
Short name T173
Test name
Test status
Simulation time 25518366 ps
CPU time 0.83 seconds
Started Nov 22 01:18:50 PM PST 23
Finished Nov 22 01:18:52 PM PST 23
Peak memory 206312 kb
Host smart-2db64a10-46a9-48f1-a433-a3f22ffa8f5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51147863562846254200574962480419044998836132099671741600221546645433383891204 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 3.edn_intr_test.51147863562846254200574962480419044998836132099671741600221546645433383891204
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.25308489854286636950796842604412667802745774239059774071452948244050306856347
Short name T197
Test name
Test status
Simulation time 61976116 ps
CPU time 1.33 seconds
Started Nov 22 01:18:33 PM PST 23
Finished Nov 22 01:18:36 PM PST 23
Peak memory 206572 kb
Host smart-e148a989-75f6-4772-95bb-878f69530ec5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25308489854286636950796842604412667802745774239059774071452948244050306856347
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_outstanding.25308489854286636950796842604412667802745774239059774071452948244050306856347
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.31906173216932890174995985671739325757171071844734033313113050863109601426071
Short name T7
Test name
Test status
Simulation time 204078009 ps
CPU time 3.72 seconds
Started Nov 22 01:19:03 PM PST 23
Finished Nov 22 01:19:08 PM PST 23
Peak memory 214592 kb
Host smart-88ee6da8-9cd7-4b2d-8af4-44a1f2d920f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31906173216932890174995985671739325757171071844734033313113050863109601426071 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 3.edn_tl_errors.31906173216932890174995985671739325757171071844734033313113050863109601426071
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.70616460601859478427237135022356909241390605298399294293281840370954315279992
Short name T133
Test name
Test status
Simulation time 155537119 ps
CPU time 2.28 seconds
Started Nov 22 01:18:37 PM PST 23
Finished Nov 22 01:18:42 PM PST 23
Peak memory 206560 kb
Host smart-08eec88d-2c90-4baf-a2ba-060a4d3050c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70616460601859478427237135022356909241390605298399294293281840370954315279992 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.70616460601859478427237135022356909241390605298399294293281840370954315279992
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.35275654459083476049398628174750673168446749459387036346141183488723251542611
Short name T132
Test name
Test status
Simulation time 25518366 ps
CPU time 0.87 seconds
Started Nov 22 01:18:54 PM PST 23
Finished Nov 22 01:18:57 PM PST 23
Peak memory 206152 kb
Host smart-82ec1707-7550-4ed6-b7f1-7999da01446b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35275654459083476049398628174750673168446749459387036346141183488723251542611 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 30.edn_intr_test.35275654459083476049398628174750673168446749459387036346141183488723251542611
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.52390220812999947935911724577742176710097673972583737866532142980078872991616
Short name T152
Test name
Test status
Simulation time 25518366 ps
CPU time 0.91 seconds
Started Nov 22 01:18:52 PM PST 23
Finished Nov 22 01:18:54 PM PST 23
Peak memory 206292 kb
Host smart-226c5005-c421-4807-a152-6a762944240d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52390220812999947935911724577742176710097673972583737866532142980078872991616 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 31.edn_intr_test.52390220812999947935911724577742176710097673972583737866532142980078872991616
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.15388601665394373795447479791819739298580719851768613713679930902047965904820
Short name T115
Test name
Test status
Simulation time 25518366 ps
CPU time 0.87 seconds
Started Nov 22 01:19:01 PM PST 23
Finished Nov 22 01:19:03 PM PST 23
Peak memory 206404 kb
Host smart-b009f23c-cedf-452f-af3c-4b5794b43605
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15388601665394373795447479791819739298580719851768613713679930902047965904820 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 32.edn_intr_test.15388601665394373795447479791819739298580719851768613713679930902047965904820
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.71475572644536285658702481035663694726355315368376502650965981772118795470470
Short name T119
Test name
Test status
Simulation time 25518366 ps
CPU time 0.85 seconds
Started Nov 22 01:18:54 PM PST 23
Finished Nov 22 01:18:57 PM PST 23
Peak memory 206320 kb
Host smart-83124d32-81e2-41ae-8d22-08d57bd29908
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71475572644536285658702481035663694726355315368376502650965981772118795470470 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 33.edn_intr_test.71475572644536285658702481035663694726355315368376502650965981772118795470470
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.26377784939681214538629794474291627599178746506711494039412823351075677971112
Short name T186
Test name
Test status
Simulation time 25518366 ps
CPU time 0.85 seconds
Started Nov 22 01:19:53 PM PST 23
Finished Nov 22 01:19:59 PM PST 23
Peak memory 206384 kb
Host smart-f06f7749-a4ee-4889-a329-873bd104de70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26377784939681214538629794474291627599178746506711494039412823351075677971112 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 34.edn_intr_test.26377784939681214538629794474291627599178746506711494039412823351075677971112
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.63165103246349241417733403141082540391724362297892196199822059199409074315313
Short name T113
Test name
Test status
Simulation time 25518366 ps
CPU time 0.87 seconds
Started Nov 22 01:19:05 PM PST 23
Finished Nov 22 01:19:10 PM PST 23
Peak memory 206384 kb
Host smart-43d69bf5-3c21-4b00-b1e9-93c7d169bf30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63165103246349241417733403141082540391724362297892196199822059199409074315313 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 35.edn_intr_test.63165103246349241417733403141082540391724362297892196199822059199409074315313
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.24682466337648912770510623485663288384763432503416163419347833282918804141077
Short name T200
Test name
Test status
Simulation time 25518366 ps
CPU time 0.81 seconds
Started Nov 22 01:18:53 PM PST 23
Finished Nov 22 01:18:56 PM PST 23
Peak memory 206152 kb
Host smart-2830ebd3-6833-499e-a048-de00082407f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24682466337648912770510623485663288384763432503416163419347833282918804141077 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 36.edn_intr_test.24682466337648912770510623485663288384763432503416163419347833282918804141077
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.52460972373230592989208131088937213775352569388132502424964280223616172309877
Short name T217
Test name
Test status
Simulation time 25518366 ps
CPU time 0.85 seconds
Started Nov 22 01:19:03 PM PST 23
Finished Nov 22 01:19:06 PM PST 23
Peak memory 206336 kb
Host smart-3c4a4f08-819e-48f3-954f-1d704e28213c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52460972373230592989208131088937213775352569388132502424964280223616172309877 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 37.edn_intr_test.52460972373230592989208131088937213775352569388132502424964280223616172309877
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.38719103605114179140647359103897088118998915047700365564211579143924286680806
Short name T221
Test name
Test status
Simulation time 25518366 ps
CPU time 0.88 seconds
Started Nov 22 01:19:02 PM PST 23
Finished Nov 22 01:19:04 PM PST 23
Peak memory 206384 kb
Host smart-f56f2d7d-40c1-40e0-aec6-7e4658ed2cf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38719103605114179140647359103897088118998915047700365564211579143924286680806 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 38.edn_intr_test.38719103605114179140647359103897088118998915047700365564211579143924286680806
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.4867960475867230610265443415787861927394489761023153633771567590380895574943
Short name T169
Test name
Test status
Simulation time 25518366 ps
CPU time 0.88 seconds
Started Nov 22 01:19:09 PM PST 23
Finished Nov 22 01:19:13 PM PST 23
Peak memory 206248 kb
Host smart-a433054b-6f15-4238-93e0-4bb99879386c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4867960475867230610265443415787861927394489761023153633771567590380895574943 -assert nopostproc +UV
M_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 39.edn_intr_test.4867960475867230610265443415787861927394489761023153633771567590380895574943
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.95240746562907303272971232353231500336201391246685828866087044885153043907992
Short name T99
Test name
Test status
Simulation time 59184494 ps
CPU time 1.36 seconds
Started Nov 22 01:18:36 PM PST 23
Finished Nov 22 01:18:40 PM PST 23
Peak memory 206504 kb
Host smart-a5d63535-bf56-4aa6-a4de-2049fd130e13
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95240746562907303272971232353231500336201391246685828866087044885153043907992 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.95240746562907303272971232353231500336201391246685828866087044885153043907992
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.42319317534309603153276666794719948989034480961467906427150362079840283983581
Short name T100
Test name
Test status
Simulation time 351971476 ps
CPU time 5.01 seconds
Started Nov 22 01:18:41 PM PST 23
Finished Nov 22 01:18:48 PM PST 23
Peak memory 206456 kb
Host smart-46351f8c-ac25-412f-8b03-03fe1b996564
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42319317534309603153276666794719948989034480961467906427150362079840283983581 -assert nopo
stproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.42319317534309603153276666794719948989034480961467906427150362079840283983581
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.100737184563374666265445147539979780389156954496982218421224704857549642635724
Short name T223
Test name
Test status
Simulation time 26726680 ps
CPU time 0.93 seconds
Started Nov 22 01:18:32 PM PST 23
Finished Nov 22 01:18:35 PM PST 23
Peak memory 206540 kb
Host smart-cee7bd3e-c29b-4168-808d-60362f4b495d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100737184563374666265445147539979780389156954496982218421224704857549642635724 -assert nop
ostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.100737184563374666265445147539979780389156954496982218421224704857549642635724
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.54408834660692723030653289440826466072541102968487635834186391549717848220807
Short name T193
Test name
Test status
Simulation time 51163789 ps
CPU time 1.28 seconds
Started Nov 22 01:18:43 PM PST 23
Finished Nov 22 01:18:46 PM PST 23
Peak memory 214792 kb
Host smart-15d03563-4c0f-41bf-b79d-5e6ecd6ab677
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5440883466069272303065328944082646607254110
2968487635834186391549717848220807 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.5440883466069272303065328944
0826466072541102968487635834186391549717848220807
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.65007117354539428538625637429647636714285205221215349697030237003439841120588
Short name T154
Test name
Test status
Simulation time 23247569 ps
CPU time 0.87 seconds
Started Nov 22 01:19:04 PM PST 23
Finished Nov 22 01:19:08 PM PST 23
Peak memory 206484 kb
Host smart-4ee28a76-9d09-4e37-a750-9d16fa2a91a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65007117354539428538625637429647636714285205221215349697030237003439841120588 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.65007117354539428538625637429647636714285205221215349697030237003439841120588
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.42814631046360771699453939952775624869100293057814106712059772458362408203192
Short name T139
Test name
Test status
Simulation time 25518366 ps
CPU time 0.87 seconds
Started Nov 22 01:19:03 PM PST 23
Finished Nov 22 01:19:07 PM PST 23
Peak memory 206260 kb
Host smart-efd3e72b-9c5e-4b3e-8024-2d8e84d088a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42814631046360771699453939952775624869100293057814106712059772458362408203192 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 4.edn_intr_test.42814631046360771699453939952775624869100293057814106712059772458362408203192
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.56342490816708211830901694856354008098291931871104430095133351152172849288792
Short name T87
Test name
Test status
Simulation time 61976116 ps
CPU time 1.31 seconds
Started Nov 22 01:18:32 PM PST 23
Finished Nov 22 01:18:36 PM PST 23
Peak memory 206496 kb
Host smart-e48fd4d6-d97c-4225-a106-16deb48a99db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56342490816708211830901694856354008098291931871104430095133351152172849288792
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_outstanding.56342490816708211830901694856354008098291931871104430095133351152172849288792
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.85250493924029739618951240624105051801396909678444857263055997309434843819468
Short name T79
Test name
Test status
Simulation time 204078009 ps
CPU time 3.9 seconds
Started Nov 22 01:18:34 PM PST 23
Finished Nov 22 01:18:40 PM PST 23
Peak memory 214728 kb
Host smart-5bf74fe2-254d-45ab-ac49-44cc038a70f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85250493924029739618951240624105051801396909678444857263055997309434843819468 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 4.edn_tl_errors.85250493924029739618951240624105051801396909678444857263055997309434843819468
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.28297960997412602799456387575433579510418693182753221389923124787333847593353
Short name T9
Test name
Test status
Simulation time 155537119 ps
CPU time 2.29 seconds
Started Nov 22 01:18:32 PM PST 23
Finished Nov 22 01:18:36 PM PST 23
Peak memory 206584 kb
Host smart-a415cee1-b891-47e9-907b-ffedf1a01c70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28297960997412602799456387575433579510418693182753221389923124787333847593353 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.28297960997412602799456387575433579510418693182753221389923124787333847593353
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.18867737832748840586074076514485318940852790284388304716636384069584141356729
Short name T194
Test name
Test status
Simulation time 25518366 ps
CPU time 0.82 seconds
Started Nov 22 01:18:53 PM PST 23
Finished Nov 22 01:18:55 PM PST 23
Peak memory 206412 kb
Host smart-aa1d0cd0-5a3f-4b6c-9d95-95ed313c3262
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18867737832748840586074076514485318940852790284388304716636384069584141356729 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 40.edn_intr_test.18867737832748840586074076514485318940852790284388304716636384069584141356729
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.43110819366749313751483833887298881926140338094984450946076925688829961276120
Short name T207
Test name
Test status
Simulation time 25518366 ps
CPU time 0.83 seconds
Started Nov 22 01:19:04 PM PST 23
Finished Nov 22 01:19:08 PM PST 23
Peak memory 206384 kb
Host smart-59580a4a-a7bb-48ca-a27d-305c0244682d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43110819366749313751483833887298881926140338094984450946076925688829961276120 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 41.edn_intr_test.43110819366749313751483833887298881926140338094984450946076925688829961276120
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.79364796220525152142868408128225629743830439075744799371213071197876130404465
Short name T204
Test name
Test status
Simulation time 25518366 ps
CPU time 0.86 seconds
Started Nov 22 01:19:04 PM PST 23
Finished Nov 22 01:19:09 PM PST 23
Peak memory 206384 kb
Host smart-7c175968-b6fb-44f5-9938-785a85ddc6d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79364796220525152142868408128225629743830439075744799371213071197876130404465 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 42.edn_intr_test.79364796220525152142868408128225629743830439075744799371213071197876130404465
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.29086043163486769547281524035706149985374693623808173445244468354368631868264
Short name T140
Test name
Test status
Simulation time 25518366 ps
CPU time 0.84 seconds
Started Nov 22 01:19:08 PM PST 23
Finished Nov 22 01:19:12 PM PST 23
Peak memory 206300 kb
Host smart-1ca54fa2-6049-4966-97ba-d9a15149b418
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29086043163486769547281524035706149985374693623808173445244468354368631868264 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 43.edn_intr_test.29086043163486769547281524035706149985374693623808173445244468354368631868264
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.64948903560747890038478796751622246034168783180792686869316123644866158108635
Short name T201
Test name
Test status
Simulation time 25518366 ps
CPU time 0.85 seconds
Started Nov 22 01:19:05 PM PST 23
Finished Nov 22 01:19:10 PM PST 23
Peak memory 206252 kb
Host smart-b2b7b08f-3e4e-4a23-ac1b-34734d3a82fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64948903560747890038478796751622246034168783180792686869316123644866158108635 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 44.edn_intr_test.64948903560747890038478796751622246034168783180792686869316123644866158108635
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.22827619315832909031866162654440620384247829059964918832824057522793210556138
Short name T138
Test name
Test status
Simulation time 25518366 ps
CPU time 0.81 seconds
Started Nov 22 01:19:02 PM PST 23
Finished Nov 22 01:19:05 PM PST 23
Peak memory 206316 kb
Host smart-c2d8b74e-50ee-491b-8d00-a23c02f957cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22827619315832909031866162654440620384247829059964918832824057522793210556138 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 45.edn_intr_test.22827619315832909031866162654440620384247829059964918832824057522793210556138
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.48795594919465006201780955448159212944382805467945622785008656546021590955466
Short name T120
Test name
Test status
Simulation time 25518366 ps
CPU time 0.88 seconds
Started Nov 22 01:19:07 PM PST 23
Finished Nov 22 01:19:11 PM PST 23
Peak memory 206400 kb
Host smart-c26191e5-0b19-4b34-9de6-5c1a944721c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48795594919465006201780955448159212944382805467945622785008656546021590955466 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 46.edn_intr_test.48795594919465006201780955448159212944382805467945622785008656546021590955466
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.59798276812973954174132849670307186083276314316025836382119787116221198374569
Short name T85
Test name
Test status
Simulation time 25518366 ps
CPU time 0.83 seconds
Started Nov 22 01:19:24 PM PST 23
Finished Nov 22 01:19:26 PM PST 23
Peak memory 206380 kb
Host smart-6b7faf5b-b9ea-4142-8028-46f3e9e96eba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59798276812973954174132849670307186083276314316025836382119787116221198374569 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 47.edn_intr_test.59798276812973954174132849670307186083276314316025836382119787116221198374569
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.68190387020929152951775802582135531803300098472936345277236538271837976770326
Short name T102
Test name
Test status
Simulation time 25518366 ps
CPU time 0.84 seconds
Started Nov 22 01:19:08 PM PST 23
Finished Nov 22 01:19:12 PM PST 23
Peak memory 206272 kb
Host smart-0efedaef-f33b-4d84-b4d6-d4884c4b9cfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68190387020929152951775802582135531803300098472936345277236538271837976770326 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 48.edn_intr_test.68190387020929152951775802582135531803300098472936345277236538271837976770326
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.95032034897430099626112770921394489110609399048241491952326064977113025587451
Short name T14
Test name
Test status
Simulation time 25518366 ps
CPU time 0.86 seconds
Started Nov 22 01:19:03 PM PST 23
Finished Nov 22 01:19:08 PM PST 23
Peak memory 206364 kb
Host smart-199b5066-9b70-4aa3-92a1-4958dc87a7d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95032034897430099626112770921394489110609399048241491952326064977113025587451 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 49.edn_intr_test.95032034897430099626112770921394489110609399048241491952326064977113025587451
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.83137881457919588670990784608591500171601225616923968073509574989647343154149
Short name T214
Test name
Test status
Simulation time 51163789 ps
CPU time 1.3 seconds
Started Nov 22 01:18:33 PM PST 23
Finished Nov 22 01:18:37 PM PST 23
Peak memory 214780 kb
Host smart-16f50031-6cdf-4adf-b352-f110487ab2d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8313788145791958867099078460859150017160122
5616923968073509574989647343154149 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.8313788145791958867099078460
8591500171601225616923968073509574989647343154149
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.10761065922792850012328926176258358854360330881859312677971985353819608215259
Short name T117
Test name
Test status
Simulation time 23247569 ps
CPU time 0.89 seconds
Started Nov 22 01:18:38 PM PST 23
Finished Nov 22 01:18:42 PM PST 23
Peak memory 206476 kb
Host smart-1a9fd035-657f-4227-9464-a5a6ba36e5bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10761065922792850012328926176258358854360330881859312677971985353819608215259 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.10761065922792850012328926176258358854360330881859312677971985353819608215259
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.21440048553285636114205282409160805277831601967499891385066159267004311457582
Short name T149
Test name
Test status
Simulation time 25518366 ps
CPU time 0.84 seconds
Started Nov 22 01:18:53 PM PST 23
Finished Nov 22 01:18:54 PM PST 23
Peak memory 206356 kb
Host smart-8c891534-e8b9-45c9-b127-0d5b27755940
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21440048553285636114205282409160805277831601967499891385066159267004311457582 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.edn_intr_test.21440048553285636114205282409160805277831601967499891385066159267004311457582
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.101366305762520424732054406610783445761441076409879852107534098092652067434501
Short name T153
Test name
Test status
Simulation time 61976116 ps
CPU time 1.37 seconds
Started Nov 22 01:19:03 PM PST 23
Finished Nov 22 01:19:08 PM PST 23
Peak memory 206564 kb
Host smart-5c3921c3-63df-43a2-9f70-be96c1a5f0d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101366305762520424732054406610783445761441076409879852107534098092652067434501
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_outstanding.101366305762520424732054406610783445761441076409879852107534098092652067434501
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.24189734985814310618299636603920611959927679470407646915954140775684995870975
Short name T165
Test name
Test status
Simulation time 204078009 ps
CPU time 3.61 seconds
Started Nov 22 01:18:32 PM PST 23
Finished Nov 22 01:18:37 PM PST 23
Peak memory 214712 kb
Host smart-3f6a0869-ac89-4379-b46f-50dc17cfe976
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24189734985814310618299636603920611959927679470407646915954140775684995870975 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.edn_tl_errors.24189734985814310618299636603920611959927679470407646915954140775684995870975
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.55738869331062028091966944699052845719371290154344624049727026046101129263971
Short name T118
Test name
Test status
Simulation time 155537119 ps
CPU time 2.29 seconds
Started Nov 22 01:18:36 PM PST 23
Finished Nov 22 01:18:40 PM PST 23
Peak memory 206588 kb
Host smart-d81d91b0-4154-4179-b2f6-a303ef51db24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55738869331062028091966944699052845719371290154344624049727026046101129263971 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.55738869331062028091966944699052845719371290154344624049727026046101129263971
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.6543443995306821392718722637836041662402008228276077200579403772316325314266
Short name T103
Test name
Test status
Simulation time 51163789 ps
CPU time 1.25 seconds
Started Nov 22 01:18:46 PM PST 23
Finished Nov 22 01:18:49 PM PST 23
Peak memory 214756 kb
Host smart-d5b62919-ec23-4414-9649-009201f7f95d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6543443995306821392718722637836041662402008
228276077200579403772316325314266 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.65434439953068213927187226378
36041662402008228276077200579403772316325314266
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.115078441623358286940149432233333427268102195230580499474962713773820173423036
Short name T150
Test name
Test status
Simulation time 23247569 ps
CPU time 0.85 seconds
Started Nov 22 01:18:45 PM PST 23
Finished Nov 22 01:18:49 PM PST 23
Peak memory 206452 kb
Host smart-090e4edb-b708-423c-a823-41e1c6b3a90d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115078441623358286940149432233333427268102195230580499474962713773820173423036 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.115078441623358286940149432233333427268102195230580499474962713773820173423036
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.12907604819565676867293263751712916646466386509954770448861996932585334733118
Short name T141
Test name
Test status
Simulation time 25518366 ps
CPU time 0.83 seconds
Started Nov 22 01:18:35 PM PST 23
Finished Nov 22 01:18:38 PM PST 23
Peak memory 206428 kb
Host smart-ec5cada5-75b1-4fa4-acee-382ece215b27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12907604819565676867293263751712916646466386509954770448861996932585334733118 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 6.edn_intr_test.12907604819565676867293263751712916646466386509954770448861996932585334733118
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.156749046656931116990085810969928434806898297131282702405079814726470900663
Short name T229
Test name
Test status
Simulation time 61976116 ps
CPU time 1.3 seconds
Started Nov 22 01:18:36 PM PST 23
Finished Nov 22 01:18:40 PM PST 23
Peak memory 206548 kb
Host smart-39fe4fa4-09af-42a9-9df5-e3f71b980c0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156749046656931116990085810969928434806898297131282702405079814726470900663 -a
ssert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_outstanding.156749046656931116990085810969928434806898297131282702405079814726470900663
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.98614593555079265020749854539970329298764892243526929148828784610003316726427
Short name T210
Test name
Test status
Simulation time 204078009 ps
CPU time 3.8 seconds
Started Nov 22 01:18:50 PM PST 23
Finished Nov 22 01:18:56 PM PST 23
Peak memory 214732 kb
Host smart-a6a57ec6-bfb3-4824-8ff3-95afacd76d9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98614593555079265020749854539970329298764892243526929148828784610003316726427 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 6.edn_tl_errors.98614593555079265020749854539970329298764892243526929148828784610003316726427
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.70127080470305835236260988126295997864172314218122119870560068263141897261388
Short name T174
Test name
Test status
Simulation time 155537119 ps
CPU time 2.3 seconds
Started Nov 22 01:18:54 PM PST 23
Finished Nov 22 01:18:58 PM PST 23
Peak memory 206508 kb
Host smart-fa5c8028-033a-4f3a-a360-24343d9d7039
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70127080470305835236260988126295997864172314218122119870560068263141897261388 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.70127080470305835236260988126295997864172314218122119870560068263141897261388
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.5435603551348354131545301118753230923816124335003344888457371280227277404167
Short name T171
Test name
Test status
Simulation time 51163789 ps
CPU time 1.31 seconds
Started Nov 22 01:18:43 PM PST 23
Finished Nov 22 01:18:46 PM PST 23
Peak memory 214712 kb
Host smart-351dbe7e-cd2c-4009-8dd6-dd309da7193b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5435603551348354131545301118753230923816124
335003344888457371280227277404167 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.54356035513483541315453011187
53230923816124335003344888457371280227277404167
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.80829603419722259320322766206859736402493769261549852188367982656315693249917
Short name T160
Test name
Test status
Simulation time 23247569 ps
CPU time 0.84 seconds
Started Nov 22 01:19:03 PM PST 23
Finished Nov 22 01:19:07 PM PST 23
Peak memory 206532 kb
Host smart-8ebdf4de-a1e3-47d7-9fc3-33198221972c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80829603419722259320322766206859736402493769261549852188367982656315693249917 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.80829603419722259320322766206859736402493769261549852188367982656315693249917
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.74288443411551481652424602314659813960656828143572587868266445593600137271350
Short name T127
Test name
Test status
Simulation time 25518366 ps
CPU time 0.86 seconds
Started Nov 22 01:19:08 PM PST 23
Finished Nov 22 01:19:13 PM PST 23
Peak memory 206400 kb
Host smart-b45b0099-cc9b-41d4-bc49-9e6453e074e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74288443411551481652424602314659813960656828143572587868266445593600137271350 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 7.edn_intr_test.74288443411551481652424602314659813960656828143572587868266445593600137271350
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.35089412110955886886367914197727057747456322889067643174667046327944414317686
Short name T202
Test name
Test status
Simulation time 61976116 ps
CPU time 1.33 seconds
Started Nov 22 01:19:01 PM PST 23
Finished Nov 22 01:19:04 PM PST 23
Peak memory 206492 kb
Host smart-ffca4186-c607-42b0-9d7a-05b68f7b95ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35089412110955886886367914197727057747456322889067643174667046327944414317686
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_outstanding.35089412110955886886367914197727057747456322889067643174667046327944414317686
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.43506248586070179146109890695034484763248982537188593028822911631173626541248
Short name T213
Test name
Test status
Simulation time 204078009 ps
CPU time 3.43 seconds
Started Nov 22 01:18:55 PM PST 23
Finished Nov 22 01:19:00 PM PST 23
Peak memory 214576 kb
Host smart-a996ea05-7274-4088-b865-6be0ada31b67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43506248586070179146109890695034484763248982537188593028822911631173626541248 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 7.edn_tl_errors.43506248586070179146109890695034484763248982537188593028822911631173626541248
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.93425643313386821527639294120813597200555094867993923973872197755752112990846
Short name T182
Test name
Test status
Simulation time 155537119 ps
CPU time 2.24 seconds
Started Nov 22 01:19:05 PM PST 23
Finished Nov 22 01:19:11 PM PST 23
Peak memory 206616 kb
Host smart-2becc72d-28ca-4c93-9825-0709f2cea01d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93425643313386821527639294120813597200555094867993923973872197755752112990846 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.93425643313386821527639294120813597200555094867993923973872197755752112990846
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.43049120344419589390381210918797331619274738418458955297378216498957832244232
Short name T177
Test name
Test status
Simulation time 51163789 ps
CPU time 1.31 seconds
Started Nov 22 01:19:03 PM PST 23
Finished Nov 22 01:19:06 PM PST 23
Peak memory 214644 kb
Host smart-922396dc-d07c-48ad-9f7a-44a577e9f8b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4304912034441958939038121091879733161927473
8418458955297378216498957832244232 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.4304912034441958939038121091
8797331619274738418458955297378216498957832244232
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.9447791199083883403799428460347641623193288015590750175007176724564917811359
Short name T111
Test name
Test status
Simulation time 23247569 ps
CPU time 0.88 seconds
Started Nov 22 01:19:03 PM PST 23
Finished Nov 22 01:19:08 PM PST 23
Peak memory 206500 kb
Host smart-0a99656d-4021-44b0-9a33-e06b35054c78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9447791199083883403799428460347641623193288015590750175007176724564917811359 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.9447791199083883403799428460347641623193288015590750175007176724564917811359
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.60688617846976924977024124669411620939731654738952458188611824907715304815251
Short name T236
Test name
Test status
Simulation time 25518366 ps
CPU time 0.84 seconds
Started Nov 22 01:18:36 PM PST 23
Finished Nov 22 01:18:39 PM PST 23
Peak memory 206376 kb
Host smart-f4c3f897-092b-4080-a465-3cebcab86c12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60688617846976924977024124669411620939731654738952458188611824907715304815251 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 8.edn_intr_test.60688617846976924977024124669411620939731654738952458188611824907715304815251
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.4360587394643532333123682273113845535385392782722202841880688820124469514364
Short name T82
Test name
Test status
Simulation time 61976116 ps
CPU time 1.26 seconds
Started Nov 22 01:18:56 PM PST 23
Finished Nov 22 01:18:59 PM PST 23
Peak memory 206524 kb
Host smart-0bc93d48-49af-44df-9422-84acd068cabb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4360587394643532333123682273113845535385392782722202841880688820124469514364 -
assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_outstanding.4360587394643532333123682273113845535385392782722202841880688820124469514364
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.18490045624287264328001792346830325633822684740270422721031603717572938531834
Short name T164
Test name
Test status
Simulation time 204078009 ps
CPU time 3.93 seconds
Started Nov 22 01:19:04 PM PST 23
Finished Nov 22 01:19:12 PM PST 23
Peak memory 214732 kb
Host smart-72bfe40a-1fdc-4954-be22-a7fc9157ef53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18490045624287264328001792346830325633822684740270422721031603717572938531834 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 8.edn_tl_errors.18490045624287264328001792346830325633822684740270422721031603717572938531834
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.46975745386854853617302881775071984485087777413387579680654566951680108295759
Short name T134
Test name
Test status
Simulation time 155537119 ps
CPU time 2.17 seconds
Started Nov 22 01:18:42 PM PST 23
Finished Nov 22 01:18:46 PM PST 23
Peak memory 206560 kb
Host smart-e8a3d86a-531f-43c0-8ada-96d9f9f4f4e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46975745386854853617302881775071984485087777413387579680654566951680108295759 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.46975745386854853617302881775071984485087777413387579680654566951680108295759
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.31012528335279479189648515674719303888672665956886881880800447148728294025476
Short name T147
Test name
Test status
Simulation time 51163789 ps
CPU time 1.25 seconds
Started Nov 22 01:18:36 PM PST 23
Finished Nov 22 01:18:39 PM PST 23
Peak memory 214620 kb
Host smart-baa08edc-8cca-4e79-97b2-3f35464e5efc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101252833527947918964851567471930388867266
5956886881880800447148728294025476 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.3101252833527947918964851567
4719303888672665956886881880800447148728294025476
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.67715417127114516324536692609670686952757824018961099423806569587978667559767
Short name T212
Test name
Test status
Simulation time 23247569 ps
CPU time 0.85 seconds
Started Nov 22 01:18:52 PM PST 23
Finished Nov 22 01:18:54 PM PST 23
Peak memory 206516 kb
Host smart-c5c0ee45-b247-4a43-9061-a4f74b57fb11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67715417127114516324536692609670686952757824018961099423806569587978667559767 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.67715417127114516324536692609670686952757824018961099423806569587978667559767
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.56856105958313740868760369515972016806696038689200961993490218354928036299762
Short name T155
Test name
Test status
Simulation time 25518366 ps
CPU time 0.86 seconds
Started Nov 22 01:18:44 PM PST 23
Finished Nov 22 01:18:48 PM PST 23
Peak memory 206344 kb
Host smart-b1d72148-c133-40c9-94ad-055e53d9b366
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56856105958313740868760369515972016806696038689200961993490218354928036299762 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.edn_intr_test.56856105958313740868760369515972016806696038689200961993490218354928036299762
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.8626661109003063470283248896123545711900411992463991611151123935519843585453
Short name T211
Test name
Test status
Simulation time 61976116 ps
CPU time 1.26 seconds
Started Nov 22 01:18:36 PM PST 23
Finished Nov 22 01:18:40 PM PST 23
Peak memory 206580 kb
Host smart-e2cbce46-397c-4101-98db-5b1b3f36e2f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8626661109003063470283248896123545711900411992463991611151123935519843585453 -
assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_outstanding.8626661109003063470283248896123545711900411992463991611151123935519843585453
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.94276828335345058387243645310963747092150512299823078166428192057982310148949
Short name T215
Test name
Test status
Simulation time 204078009 ps
CPU time 3.75 seconds
Started Nov 22 01:18:36 PM PST 23
Finished Nov 22 01:18:42 PM PST 23
Peak memory 214700 kb
Host smart-28b218a8-af7b-4c5e-8c97-368e750f530e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94276828335345058387243645310963747092150512299823078166428192057982310148949 -assert nopostproc +U
VM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.edn_tl_errors.94276828335345058387243645310963747092150512299823078166428192057982310148949
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.18247063306823616210332905036862518228478947651674897010137283058506910847473
Short name T107
Test name
Test status
Simulation time 155537119 ps
CPU time 2.28 seconds
Started Nov 22 01:18:51 PM PST 23
Finished Nov 22 01:18:55 PM PST 23
Peak memory 206588 kb
Host smart-7c8b3cb3-6c51-424e-8d99-b3cb50519104
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18247063306823616210332905036862518228478947651674897010137283058506910847473 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.18247063306823616210332905036862518228478947651674897010137283058506910847473
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert_test.97764539940881604797447764258419267383350869889322061676282160115570000083913
Short name T598
Test name
Test status
Simulation time 28184990 ps
CPU time 0.86 seconds
Started Nov 22 01:31:32 PM PST 23
Finished Nov 22 01:31:34 PM PST 23
Peak memory 205436 kb
Host smart-7e5b3c9c-3fb6-46b5-9991-2f71d53ee0bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97764539940881604797447764258419267383350869889322061676282160115570000083913 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.edn_alert_test.97764539940881604797447764258419267383350869889322061676282160115570000083913
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.32721173828917728919173923863303046669117519986101810839676428053002690699403
Short name T976
Test name
Test status
Simulation time 14969183 ps
CPU time 0.92 seconds
Started Nov 22 01:31:33 PM PST 23
Finished Nov 22 01:31:36 PM PST 23
Peak memory 214900 kb
Host smart-1f2ee45a-f266-4401-8121-bffafead0089
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32721173828917728919173923863303046669117519986101810839676428053002690699403 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable_auto_req_mode.32721173828917728919173923863303046669117519986101810839676
428053002690699403
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.111115409510637015110557108294313651970500787337607671136423589486611460618013
Short name T375
Test name
Test status
Simulation time 24963823 ps
CPU time 1.17 seconds
Started Nov 22 01:31:33 PM PST 23
Finished Nov 22 01:31:35 PM PST 23
Peak memory 230460 kb
Host smart-0ce00ed9-4da1-41ec-9874-9e15c45f54aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111115409510637015110557108294313651970500787337607671136423589486611460618013 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.edn_err.111115409510637015110557108294313651970500787337607671136423589486611460618013
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.29976984738156446856275156370212785443512282738772294658468343637870242074996
Short name T441
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:31:39 PM PST 23
Finished Nov 22 01:31:41 PM PST 23
Peak memory 205676 kb
Host smart-10acce4e-d745-4abb-b56c-287e040145af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29976984738156446856275156370212785443512282738772294658468343637870242074996 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.edn_genbits.29976984738156446856275156370212785443512282738772294658468343637870242074996
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.76928608991125822334940441705158457906165172339388627429767803240522665318363
Short name T728
Test name
Test status
Simulation time 18439183 ps
CPU time 1.17 seconds
Started Nov 22 01:31:34 PM PST 23
Finished Nov 22 01:31:37 PM PST 23
Peak memory 222256 kb
Host smart-5a16c83d-600c-4c53-8433-d06b97114f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76928608991125822334940441705158457906165172339388627429767803240522665318363 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.edn_intr.76928608991125822334940441705158457906165172339388627429767803240522665318363
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_sec_cm.87092299677074269253338859719290040821334626804229907581374782988269994598879
Short name T32
Test name
Test status
Simulation time 717215632 ps
CPU time 5.6 seconds
Started Nov 22 01:31:31 PM PST 23
Finished Nov 22 01:31:37 PM PST 23
Peak memory 234012 kb
Host smart-49f83f18-9621-44ef-9228-5f9a5e784151
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87092299677074269253338859719290040821334626804229907581374782988269994598879 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.edn_sec_cm.87092299677074269253338859719290040821334626804229907581374782988269994598879
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.44301161145498193792405352277668438910072970139838456958377612068119692942590
Short name T903
Test name
Test status
Simulation time 13059183 ps
CPU time 0.88 seconds
Started Nov 22 01:31:33 PM PST 23
Finished Nov 22 01:31:35 PM PST 23
Peak memory 205364 kb
Host smart-23f69055-9650-458f-95ce-10e4789a13bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44301161145498193792405352277668438910072970139838456958377612068119692942590 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.edn_smoke.44301161145498193792405352277668438910072970139838456958377612068119692942590
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.25224274508747720355217621597775280846032130730393798785101840492841211835622
Short name T612
Test name
Test status
Simulation time 154489183 ps
CPU time 4.01 seconds
Started Nov 22 01:31:33 PM PST 23
Finished Nov 22 01:31:38 PM PST 23
Peak memory 206404 kb
Host smart-b9b9a5b1-858d-4c39-bd04-a741487334f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25224274508747720355217621597775280846032130730393798785101840492841211835622 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.25224274508747720355217621597775280846032130730393798785101840492841211835622
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.20686182693046068289764969967061713120835491145927104625901200825803512747155
Short name T279
Test name
Test status
Simulation time 41708099183 ps
CPU time 1077.89 seconds
Started Nov 22 01:31:34 PM PST 23
Finished Nov 22 01:49:34 PM PST 23
Peak memory 215712 kb
Host smart-f30597b2-e20b-4586-9c98-1337b919e549
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206861826930460682897649699
67061713120835491145927104625901200825803512747155 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.206861826930
46068289764969967061713120835491145927104625901200825803512747155
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.60878558548954165093950567108809719741456357763826654324489133567308688574724
Short name T799
Test name
Test status
Simulation time 18259183 ps
CPU time 0.97 seconds
Started Nov 22 01:31:32 PM PST 23
Finished Nov 22 01:31:34 PM PST 23
Peak memory 205384 kb
Host smart-1f4a4862-6942-4a2d-8b25-f4fcedb3a8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60878558548954165093950567108809719741456357763826654324489133567308688574724 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.edn_alert.60878558548954165093950567108809719741456357763826654324489133567308688574724
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.29932445208197979806942795866481133444537035625471643052661474451759558911551
Short name T325
Test name
Test status
Simulation time 28184990 ps
CPU time 0.86 seconds
Started Nov 22 01:31:35 PM PST 23
Finished Nov 22 01:31:38 PM PST 23
Peak memory 205416 kb
Host smart-201705bc-4046-444d-b381-ba323a67b9aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29932445208197979806942795866481133444537035625471643052661474451759558911551 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.edn_alert_test.29932445208197979806942795866481133444537035625471643052661474451759558911551
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.46399073084882811667187064721565157177795531885491939156941442699614321195604
Short name T69
Test name
Test status
Simulation time 12219183 ps
CPU time 0.88 seconds
Started Nov 22 01:31:40 PM PST 23
Finished Nov 22 01:31:42 PM PST 23
Peak memory 214880 kb
Host smart-9e8bcc0a-4483-4492-a8b1-513f699dd6c3
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46399073084882811667187064721565157177795531885491939156941442699614321195604 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.edn_disable.46399073084882811667187064721565157177795531885491939156941442699614321195604
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.30207540717988252414933394341561995760088114599113686978398840959259054084877
Short name T733
Test name
Test status
Simulation time 14969183 ps
CPU time 0.89 seconds
Started Nov 22 01:31:35 PM PST 23
Finished Nov 22 01:31:38 PM PST 23
Peak memory 214868 kb
Host smart-e220e38e-f4b7-41c1-97a7-03c34305a0ab
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30207540717988252414933394341561995760088114599113686978398840959259054084877 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable_auto_req_mode.30207540717988252414933394341561995760088114599113686978398
840959259054084877
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.73364838989456895060309986782496496933594046237552526174553492050765677595895
Short name T559
Test name
Test status
Simulation time 24963823 ps
CPU time 1.13 seconds
Started Nov 22 01:31:35 PM PST 23
Finished Nov 22 01:31:38 PM PST 23
Peak memory 230444 kb
Host smart-2152a495-f3dc-4402-b7a5-47e4d56ddc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73364838989456895060309986782496496933594046237552526174553492050765677595895 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
edn_err.73364838989456895060309986782496496933594046237552526174553492050765677595895
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.102784106868475630960574097864637493193756639982725405908814917609208644668304
Short name T754
Test name
Test status
Simulation time 17999183 ps
CPU time 1.16 seconds
Started Nov 22 01:31:32 PM PST 23
Finished Nov 22 01:31:34 PM PST 23
Peak memory 205808 kb
Host smart-ae5a3e9e-85f4-4afb-888e-51030615520d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102784106868475630960574097864637493193756639982725405908814917609208644668304 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.edn_genbits.102784106868475630960574097864637493193756639982725405908814917609208644668304
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_regwen.41812797337015194477662017480418818624578016969832034692426476844402043255853
Short name T96
Test name
Test status
Simulation time 11759183 ps
CPU time 0.84 seconds
Started Nov 22 01:31:34 PM PST 23
Finished Nov 22 01:31:37 PM PST 23
Peak memory 205324 kb
Host smart-8e998a60-f770-4979-861c-81522f02d436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41812797337015194477662017480418818624578016969832034692426476844402043255853 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.edn_regwen.41812797337015194477662017480418818624578016969832034692426476844402043255853
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_smoke.29351519862660584809860819735221757632460037480127357487363572829432662517534
Short name T946
Test name
Test status
Simulation time 13059183 ps
CPU time 0.9 seconds
Started Nov 22 01:31:32 PM PST 23
Finished Nov 22 01:31:34 PM PST 23
Peak memory 205332 kb
Host smart-cb25550d-0c88-4ad9-9ef0-84d70c7a3b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29351519862660584809860819735221757632460037480127357487363572829432662517534 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.edn_smoke.29351519862660584809860819735221757632460037480127357487363572829432662517534
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.44174218391849309577405885728088567885875893460700302512118478012853434616692
Short name T812
Test name
Test status
Simulation time 154489183 ps
CPU time 4.02 seconds
Started Nov 22 01:31:34 PM PST 23
Finished Nov 22 01:31:40 PM PST 23
Peak memory 206428 kb
Host smart-1cf7ed03-7c0d-4223-8ff5-bf2b7ad9c6b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44174218391849309577405885728088567885875893460700302512118478012853434616692 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.44174218391849309577405885728088567885875893460700302512118478012853434616692
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.50461172818350449197255908075214280124712530544585253232369820262192266576884
Short name T242
Test name
Test status
Simulation time 41708099183 ps
CPU time 1075.21 seconds
Started Nov 22 01:31:34 PM PST 23
Finished Nov 22 01:49:32 PM PST 23
Peak memory 215872 kb
Host smart-ee3ea110-0e37-40d7-8961-98aff37b71f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504611728183504491972559080
75214280124712530544585253232369820262192266576884 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.504611728183
50449197255908075214280124712530544585253232369820262192266576884
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.39082910832449044205818137132966175482103383450109502338834617669914273639507
Short name T860
Test name
Test status
Simulation time 18259183 ps
CPU time 0.96 seconds
Started Nov 22 01:33:25 PM PST 23
Finished Nov 22 01:33:27 PM PST 23
Peak memory 205496 kb
Host smart-c2509b0a-ceab-421c-a604-99c51546b26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39082910832449044205818137132966175482103383450109502338834617669914273639507 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.edn_alert.39082910832449044205818137132966175482103383450109502338834617669914273639507
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.7015749326558274612067976139093177250479168706015987654707566900827233237974
Short name T331
Test name
Test status
Simulation time 28184990 ps
CPU time 0.88 seconds
Started Nov 22 01:33:28 PM PST 23
Finished Nov 22 01:33:29 PM PST 23
Peak memory 205492 kb
Host smart-8898ee39-67fb-4538-8110-d9b27d0cae09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7015749326558274612067976139093177250479168706015987654707566900827233237974 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.edn_alert_test.7015749326558274612067976139093177250479168706015987654707566900827233237974
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.80233734544622388212794576922902660766001980056803747194840150725921883863106
Short name T709
Test name
Test status
Simulation time 12219183 ps
CPU time 0.84 seconds
Started Nov 22 01:33:25 PM PST 23
Finished Nov 22 01:33:27 PM PST 23
Peak memory 214772 kb
Host smart-4d598ae7-3b0b-4c9f-a7f3-cf5e2bc8b800
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80233734544622388212794576922902660766001980056803747194840150725921883863106 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.edn_disable.80233734544622388212794576922902660766001980056803747194840150725921883863106
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.39720716712274520088974711500532485508181313293838217154517013679000635004470
Short name T424
Test name
Test status
Simulation time 14969183 ps
CPU time 0.88 seconds
Started Nov 22 01:33:24 PM PST 23
Finished Nov 22 01:33:27 PM PST 23
Peak memory 214764 kb
Host smart-45a68eac-e751-498e-aaab-bb1942d54b58
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39720716712274520088974711500532485508181313293838217154517013679000635004470 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable_auto_req_mode.3972071671227452008897471150053248550818131329383821715451
7013679000635004470
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.16439056835791313572772653218558026136663886596779276015601883653947957070867
Short name T616
Test name
Test status
Simulation time 24963823 ps
CPU time 1.16 seconds
Started Nov 22 01:33:24 PM PST 23
Finished Nov 22 01:33:27 PM PST 23
Peak memory 230520 kb
Host smart-9a920dc1-64ca-4336-82a4-460bceb03f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16439056835791313572772653218558026136663886596779276015601883653947957070867 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.edn_err.16439056835791313572772653218558026136663886596779276015601883653947957070867
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.4678357255851020281933658694413005090865441558137017651281340455118744037155
Short name T590
Test name
Test status
Simulation time 17999183 ps
CPU time 1.06 seconds
Started Nov 22 01:33:23 PM PST 23
Finished Nov 22 01:33:25 PM PST 23
Peak memory 205832 kb
Host smart-203d795b-fb8c-4491-b7a7-189598735b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4678357255851020281933658694413005090865441558137017651281340455118744037155 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.edn_genbits.4678357255851020281933658694413005090865441558137017651281340455118744037155
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.66484615588113687623302323356403304741407200695815041824917583677265556587648
Short name T824
Test name
Test status
Simulation time 18439183 ps
CPU time 1.13 seconds
Started Nov 22 01:33:25 PM PST 23
Finished Nov 22 01:33:27 PM PST 23
Peak memory 222192 kb
Host smart-f57df2f4-d412-4fe4-b700-0110782240bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66484615588113687623302323356403304741407200695815041824917583677265556587648 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.edn_intr.66484615588113687623302323356403304741407200695815041824917583677265556587648
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.62989993768931957487948658086028715415142199283624117208493202872025238495561
Short name T542
Test name
Test status
Simulation time 13059183 ps
CPU time 0.9 seconds
Started Nov 22 01:33:23 PM PST 23
Finished Nov 22 01:33:25 PM PST 23
Peak memory 205360 kb
Host smart-24ec252a-a655-44ca-8d04-2be90dc3d67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62989993768931957487948658086028715415142199283624117208493202872025238495561 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.edn_smoke.62989993768931957487948658086028715415142199283624117208493202872025238495561
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.106701000091453077200913601784429098168180690019097120944330110451875868567328
Short name T596
Test name
Test status
Simulation time 154489183 ps
CPU time 4.01 seconds
Started Nov 22 01:33:24 PM PST 23
Finished Nov 22 01:33:29 PM PST 23
Peak memory 206368 kb
Host smart-1523098b-6bad-4365-a232-415b8695fcd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106701000091453077200913601784429098168180690019097120944330110451875868567328 -assert nopo
stproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.106701000091453077200913601784429098168180690019097120944330110451875868567328
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.35965187635286937011728725870747361418021473522522549980374835891079161572310
Short name T573
Test name
Test status
Simulation time 41708099183 ps
CPU time 1084.88 seconds
Started Nov 22 01:33:24 PM PST 23
Finished Nov 22 01:51:31 PM PST 23
Peak memory 215840 kb
Host smart-4bd9501f-ba43-4f9f-8416-abf13bdf76b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359651876352869370117287258
70747361418021473522522549980374835891079161572310 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.35965187635
286937011728725870747361418021473522522549980374835891079161572310
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.62142406733983554611735414640066988978582499332746778710826910237845932674127
Short name T386
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:36:14 PM PST 23
Finished Nov 22 01:36:15 PM PST 23
Peak memory 205836 kb
Host smart-4eaa90c5-a8c2-47d9-a9a6-b88e349185cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62142406733983554611735414640066988978582499332746778710826910237845932674127 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 100.edn_genbits.62142406733983554611735414640066988978582499332746778710826910237845932674127
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.21889399773103072408185438769041608829196600184599560541847926344642401950480
Short name T336
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 22 01:36:22 PM PST 23
Finished Nov 22 01:36:24 PM PST 23
Peak memory 205752 kb
Host smart-e0c27ed0-5026-4ba9-b1d5-b78c98a20a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21889399773103072408185438769041608829196600184599560541847926344642401950480 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 101.edn_genbits.21889399773103072408185438769041608829196600184599560541847926344642401950480
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.4266112624380914292996968528081165029051190841639403212927537628528073641282
Short name T371
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Nov 22 01:36:18 PM PST 23
Finished Nov 22 01:36:20 PM PST 23
Peak memory 205820 kb
Host smart-da3bc655-c304-4699-90e9-f2b7ae92e971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266112624380914292996968528081165029051190841639403212927537628528073641282 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 102.edn_genbits.4266112624380914292996968528081165029051190841639403212927537628528073641282
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.43529836355840477009497465478320075540780045238624530658643427857726480243522
Short name T677
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:36:25 PM PST 23
Finished Nov 22 01:36:26 PM PST 23
Peak memory 205848 kb
Host smart-3bf5d797-73f5-49d9-a973-697359287ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43529836355840477009497465478320075540780045238624530658643427857726480243522 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 103.edn_genbits.43529836355840477009497465478320075540780045238624530658643427857726480243522
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.70689992399950379029566356834227053109488850550686816445464029049483913108009
Short name T762
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 22 01:36:34 PM PST 23
Finished Nov 22 01:36:36 PM PST 23
Peak memory 205764 kb
Host smart-9929f826-57e1-455a-9841-4e22f581dae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70689992399950379029566356834227053109488850550686816445464029049483913108009 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 104.edn_genbits.70689992399950379029566356834227053109488850550686816445464029049483913108009
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.26314593045301565327582403810565198530984212144027002386082486043909360202624
Short name T396
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:36:36 PM PST 23
Finished Nov 22 01:36:38 PM PST 23
Peak memory 205816 kb
Host smart-ab41efe7-36c6-4764-af1e-fc41b8b0f2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26314593045301565327582403810565198530984212144027002386082486043909360202624 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 105.edn_genbits.26314593045301565327582403810565198530984212144027002386082486043909360202624
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.107182775152112957441531807184532562593662911421780571639914355268543339175290
Short name T607
Test name
Test status
Simulation time 17999183 ps
CPU time 1.16 seconds
Started Nov 22 01:36:28 PM PST 23
Finished Nov 22 01:36:30 PM PST 23
Peak memory 205856 kb
Host smart-669a6e4e-8ee2-42c4-9081-6221c024d5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107182775152112957441531807184532562593662911421780571639914355268543339175290 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 106.edn_genbits.107182775152112957441531807184532562593662911421780571639914355268543339175290
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.110905468232010348799501124593782843843763106080290399962448425405018378509876
Short name T793
Test name
Test status
Simulation time 17999183 ps
CPU time 1.15 seconds
Started Nov 22 01:36:36 PM PST 23
Finished Nov 22 01:36:40 PM PST 23
Peak memory 205844 kb
Host smart-1181de15-f7e9-477f-80f6-63561070ba5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110905468232010348799501124593782843843763106080290399962448425405018378509876 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 107.edn_genbits.110905468232010348799501124593782843843763106080290399962448425405018378509876
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.106326716483240894221098814958250773785957597106540698764657235029528442551822
Short name T575
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 22 01:36:30 PM PST 23
Finished Nov 22 01:36:31 PM PST 23
Peak memory 205724 kb
Host smart-a035bbce-6471-4612-aa2e-02d830553cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106326716483240894221098814958250773785957597106540698764657235029528442551822 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 108.edn_genbits.106326716483240894221098814958250773785957597106540698764657235029528442551822
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.45670421720994957893228422997923592500926105365153218475179922812724557513898
Short name T365
Test name
Test status
Simulation time 17999183 ps
CPU time 1.15 seconds
Started Nov 22 01:36:35 PM PST 23
Finished Nov 22 01:36:38 PM PST 23
Peak memory 205804 kb
Host smart-be2698e2-2a21-4c63-a359-bfb78aebd740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45670421720994957893228422997923592500926105365153218475179922812724557513898 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 109.edn_genbits.45670421720994957893228422997923592500926105365153218475179922812724557513898
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.26269071676926203718789755961331828041347037905082036812248257654800350498849
Short name T296
Test name
Test status
Simulation time 18259183 ps
CPU time 0.97 seconds
Started Nov 22 01:33:29 PM PST 23
Finished Nov 22 01:33:30 PM PST 23
Peak memory 205580 kb
Host smart-30843088-e44d-4ec4-a7ef-95d7f2b62d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26269071676926203718789755961331828041347037905082036812248257654800350498849 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.edn_alert.26269071676926203718789755961331828041347037905082036812248257654800350498849
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_disable.41686747272754494537231054280672466239095969638818418812114672764323386383829
Short name T784
Test name
Test status
Simulation time 12219183 ps
CPU time 0.86 seconds
Started Nov 22 01:33:28 PM PST 23
Finished Nov 22 01:33:30 PM PST 23
Peak memory 214860 kb
Host smart-d8402d7c-0610-410a-ab67-589c4968052b
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41686747272754494537231054280672466239095969638818418812114672764323386383829 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.edn_disable.41686747272754494537231054280672466239095969638818418812114672764323386383829
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.76788624241530096211281479409838186168801376686975602318415387676182014536204
Short name T779
Test name
Test status
Simulation time 14969183 ps
CPU time 0.92 seconds
Started Nov 22 01:33:28 PM PST 23
Finished Nov 22 01:33:29 PM PST 23
Peak memory 214884 kb
Host smart-52c240b8-835c-42ea-b7dc-a6e25df447cc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76788624241530096211281479409838186168801376686975602318415387676182014536204 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable_auto_req_mode.7678862424153009621128147940983818616880137668697560231841
5387676182014536204
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.58787879685225550006574051806803801035595733347914651148315892202495928461600
Short name T292
Test name
Test status
Simulation time 24963823 ps
CPU time 1.13 seconds
Started Nov 22 01:33:31 PM PST 23
Finished Nov 22 01:33:33 PM PST 23
Peak memory 230400 kb
Host smart-179a812c-fb8c-4dd2-b21f-5938b469a3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58787879685225550006574051806803801035595733347914651148315892202495928461600 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.edn_err.58787879685225550006574051806803801035595733347914651148315892202495928461600
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.112313527127010762499307669439982269292764134386187481862975183374635282260765
Short name T967
Test name
Test status
Simulation time 17999183 ps
CPU time 1.06 seconds
Started Nov 22 01:33:26 PM PST 23
Finished Nov 22 01:33:28 PM PST 23
Peak memory 205840 kb
Host smart-e12de4fd-10bf-4c9a-879f-ea2051435c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112313527127010762499307669439982269292764134386187481862975183374635282260765 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 11.edn_genbits.112313527127010762499307669439982269292764134386187481862975183374635282260765
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.66421877406738186311431222083605319794137415614488422940618201477200956677514
Short name T723
Test name
Test status
Simulation time 18439183 ps
CPU time 1.1 seconds
Started Nov 22 01:33:28 PM PST 23
Finished Nov 22 01:33:29 PM PST 23
Peak memory 222256 kb
Host smart-3be87362-852d-4474-b984-55671f7ad5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66421877406738186311431222083605319794137415614488422940618201477200956677514 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.edn_intr.66421877406738186311431222083605319794137415614488422940618201477200956677514
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.81776994028383908149370853053035682977111155235674760478500655156228768875712
Short name T620
Test name
Test status
Simulation time 13059183 ps
CPU time 0.89 seconds
Started Nov 22 01:33:27 PM PST 23
Finished Nov 22 01:33:29 PM PST 23
Peak memory 205332 kb
Host smart-acb0f2f7-7eeb-4da1-b932-baf6dccce357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81776994028383908149370853053035682977111155235674760478500655156228768875712 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.edn_smoke.81776994028383908149370853053035682977111155235674760478500655156228768875712
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.21865406270297787962762660724363392008639922832153920542795799438375395931479
Short name T45
Test name
Test status
Simulation time 41708099183 ps
CPU time 1077.09 seconds
Started Nov 22 01:33:27 PM PST 23
Finished Nov 22 01:51:25 PM PST 23
Peak memory 215860 kb
Host smart-aa79f3ad-6997-4b34-9f53-6067981b2126
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218654062702977879627626607
24363392008639922832153920542795799438375395931479 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.21865406270
297787962762660724363392008639922832153920542795799438375395931479
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.106587606260442384547156952129730885937773029244792927425588633732970299741591
Short name T843
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 22 01:36:45 PM PST 23
Finished Nov 22 01:36:48 PM PST 23
Peak memory 205840 kb
Host smart-ed7d5f12-fcfc-484e-a931-ba24af9017cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106587606260442384547156952129730885937773029244792927425588633732970299741591 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 110.edn_genbits.106587606260442384547156952129730885937773029244792927425588633732970299741591
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.52729389189089774641629717312391993468469459472482229208491937441028231774246
Short name T862
Test name
Test status
Simulation time 17999183 ps
CPU time 1.16 seconds
Started Nov 22 01:36:49 PM PST 23
Finished Nov 22 01:36:53 PM PST 23
Peak memory 205744 kb
Host smart-54772c04-29e5-43d7-8d2b-79272e539d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52729389189089774641629717312391993468469459472482229208491937441028231774246 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 111.edn_genbits.52729389189089774641629717312391993468469459472482229208491937441028231774246
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.22245156557786488521692937755294510780209111600108322222092855274978786110890
Short name T855
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 22 01:36:36 PM PST 23
Finished Nov 22 01:36:39 PM PST 23
Peak memory 205944 kb
Host smart-47b730f1-edfe-4975-8dc6-88575cb20cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22245156557786488521692937755294510780209111600108322222092855274978786110890 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 112.edn_genbits.22245156557786488521692937755294510780209111600108322222092855274978786110890
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.112027339958401918170708278333233355882488689189059280010638494429558030129254
Short name T957
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 22 01:36:35 PM PST 23
Finished Nov 22 01:36:37 PM PST 23
Peak memory 205788 kb
Host smart-6822b2bd-1851-426a-be85-75a26d1a2353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112027339958401918170708278333233355882488689189059280010638494429558030129254 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 113.edn_genbits.112027339958401918170708278333233355882488689189059280010638494429558030129254
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.28542675315119908448360122750629458194314835469610130984888470699286017326255
Short name T480
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:36:34 PM PST 23
Finished Nov 22 01:36:35 PM PST 23
Peak memory 205848 kb
Host smart-e208003e-d610-4f04-b18c-e86c7267928d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28542675315119908448360122750629458194314835469610130984888470699286017326255 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 114.edn_genbits.28542675315119908448360122750629458194314835469610130984888470699286017326255
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.60470180700192242405005864568984241949485119670287546985996924227707859772965
Short name T314
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 22 01:36:48 PM PST 23
Finished Nov 22 01:36:50 PM PST 23
Peak memory 205708 kb
Host smart-a9e27cc9-2be0-4e69-a83b-36d26b5c0d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60470180700192242405005864568984241949485119670287546985996924227707859772965 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 115.edn_genbits.60470180700192242405005864568984241949485119670287546985996924227707859772965
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.63212033148311337304716147338456688460155558552345734040574965185729059831581
Short name T475
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:36:44 PM PST 23
Finished Nov 22 01:36:46 PM PST 23
Peak memory 205820 kb
Host smart-a0ffdd66-de4d-46ca-966e-2185ac4493e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63212033148311337304716147338456688460155558552345734040574965185729059831581 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 116.edn_genbits.63212033148311337304716147338456688460155558552345734040574965185729059831581
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.114693864732537667118010934456509387335649137011523454097933414788493652651015
Short name T561
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 22 01:36:50 PM PST 23
Finished Nov 22 01:36:54 PM PST 23
Peak memory 205944 kb
Host smart-b02057d3-521c-469d-94b4-11613c5f77e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114693864732537667118010934456509387335649137011523454097933414788493652651015 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 117.edn_genbits.114693864732537667118010934456509387335649137011523454097933414788493652651015
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.23608524430994202395488507522600251154154581471311022472824690763730475908171
Short name T466
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 22 01:36:50 PM PST 23
Finished Nov 22 01:36:55 PM PST 23
Peak memory 205804 kb
Host smart-5bea3d38-0330-4e88-8b4a-1c91a99b1c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23608524430994202395488507522600251154154581471311022472824690763730475908171 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 118.edn_genbits.23608524430994202395488507522600251154154581471311022472824690763730475908171
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.105403203311319770338056583518014532960179213316245581325058311414323252483967
Short name T295
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 22 01:36:47 PM PST 23
Finished Nov 22 01:36:50 PM PST 23
Peak memory 205776 kb
Host smart-aacddd59-e240-435e-b82f-0f7fe304e919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105403203311319770338056583518014532960179213316245581325058311414323252483967 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 119.edn_genbits.105403203311319770338056583518014532960179213316245581325058311414323252483967
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.86939369254001410892958683235191330050636642972125306511714067284432959976007
Short name T431
Test name
Test status
Simulation time 18259183 ps
CPU time 1 seconds
Started Nov 22 01:33:29 PM PST 23
Finished Nov 22 01:33:31 PM PST 23
Peak memory 205580 kb
Host smart-1a3cf55d-6a0c-4b9f-9975-b133438b7f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86939369254001410892958683235191330050636642972125306511714067284432959976007 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.edn_alert.86939369254001410892958683235191330050636642972125306511714067284432959976007
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.3809571845854718669186351637818653313964816032532088560589316947772825566201
Short name T291
Test name
Test status
Simulation time 28184990 ps
CPU time 0.85 seconds
Started Nov 22 01:33:28 PM PST 23
Finished Nov 22 01:33:29 PM PST 23
Peak memory 205508 kb
Host smart-da63efd7-2470-4750-bbb1-a1552fbd2407
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809571845854718669186351637818653313964816032532088560589316947772825566201 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.edn_alert_test.3809571845854718669186351637818653313964816032532088560589316947772825566201
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.22733988815629700026758110463141813757478590121433295816172042522890853674862
Short name T844
Test name
Test status
Simulation time 12219183 ps
CPU time 0.88 seconds
Started Nov 22 01:33:28 PM PST 23
Finished Nov 22 01:33:29 PM PST 23
Peak memory 214816 kb
Host smart-fa02f29a-5e88-42bb-8d18-d278470da959
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22733988815629700026758110463141813757478590121433295816172042522890853674862 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.edn_disable.22733988815629700026758110463141813757478590121433295816172042522890853674862
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.44821278924048521082279519327946869480389455555252914365380029769852604377139
Short name T714
Test name
Test status
Simulation time 14969183 ps
CPU time 0.89 seconds
Started Nov 22 01:33:28 PM PST 23
Finished Nov 22 01:33:30 PM PST 23
Peak memory 214840 kb
Host smart-7ad3ae00-6902-4aa9-9b7c-5f7d21128e89
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44821278924048521082279519327946869480389455555252914365380029769852604377139 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable_auto_req_mode.4482127892404852108227951932794686948038945555525291436538
0029769852604377139
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.49814882338367433785598272880066702452303038563107567405946873897477862498785
Short name T260
Test name
Test status
Simulation time 24963823 ps
CPU time 1.15 seconds
Started Nov 22 01:33:28 PM PST 23
Finished Nov 22 01:33:30 PM PST 23
Peak memory 230460 kb
Host smart-908981b7-1c38-406e-a701-52a864168f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49814882338367433785598272880066702452303038563107567405946873897477862498785 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.edn_err.49814882338367433785598272880066702452303038563107567405946873897477862498785
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.7685017803678874163604343150218624944924191648224128264368021826199496239888
Short name T422
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:33:28 PM PST 23
Finished Nov 22 01:33:30 PM PST 23
Peak memory 205720 kb
Host smart-635a7a5c-fa28-4046-9522-b4bd9c109a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7685017803678874163604343150218624944924191648224128264368021826199496239888 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.edn_genbits.7685017803678874163604343150218624944924191648224128264368021826199496239888
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.18712289249032755291884179761532218649292532301889360227027235959234885970040
Short name T494
Test name
Test status
Simulation time 18439183 ps
CPU time 1.1 seconds
Started Nov 22 01:33:26 PM PST 23
Finished Nov 22 01:33:29 PM PST 23
Peak memory 222172 kb
Host smart-b1b1158e-c338-4fa5-9096-3554fe001950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18712289249032755291884179761532218649292532301889360227027235959234885970040 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.edn_intr.18712289249032755291884179761532218649292532301889360227027235959234885970040
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.108306039207576709080602645614347565980476211616589483926452392748982899010696
Short name T781
Test name
Test status
Simulation time 13059183 ps
CPU time 0.87 seconds
Started Nov 22 01:33:27 PM PST 23
Finished Nov 22 01:33:29 PM PST 23
Peak memory 205280 kb
Host smart-357f3210-89a4-4eba-974b-e86c8b929246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108306039207576709080602645614347565980476211616589483926452392748982899010696 -assert nopostproc +UVM_TESTNAME=edn_smok
e_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.edn_smoke.108306039207576709080602645614347565980476211616589483926452392748982899010696
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.7093468431408717455621673062726927804809877094247696438752619443882011859292
Short name T20
Test name
Test status
Simulation time 154489183 ps
CPU time 3.86 seconds
Started Nov 22 01:33:27 PM PST 23
Finished Nov 22 01:33:32 PM PST 23
Peak memory 206272 kb
Host smart-208bd3b5-bcd4-4c8a-8891-3a0d8e2a6669
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7093468431408717455621673062726927804809877094247696438752619443882011859292 -assert nopost
proc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.7093468431408717455621673062726927804809877094247696438752619443882011859292
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.9195204031996649751555789152785092039989796532695873914441638249906870029203
Short name T830
Test name
Test status
Simulation time 41708099183 ps
CPU time 1100.11 seconds
Started Nov 22 01:33:29 PM PST 23
Finished Nov 22 01:51:50 PM PST 23
Peak memory 215832 kb
Host smart-1a2e39b4-ac04-4240-848e-e5822dc92ebb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919520403199664975155578915
2785092039989796532695873914441638249906870029203 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.919520403199
6649751555789152785092039989796532695873914441638249906870029203
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.105832445151345936047523336171721990607393311029687625348943954555282732108718
Short name T930
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:36:50 PM PST 23
Finished Nov 22 01:36:54 PM PST 23
Peak memory 205732 kb
Host smart-4694d289-5077-4742-86e0-8041554a10f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105832445151345936047523336171721990607393311029687625348943954555282732108718 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 120.edn_genbits.105832445151345936047523336171721990607393311029687625348943954555282732108718
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.3249054191131349549000781294547582069894525649753757441201883888743925729629
Short name T330
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 22 01:36:52 PM PST 23
Finished Nov 22 01:36:57 PM PST 23
Peak memory 205920 kb
Host smart-a2b04a7e-9d97-4065-96f2-ce2fd4e51ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249054191131349549000781294547582069894525649753757441201883888743925729629 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 121.edn_genbits.3249054191131349549000781294547582069894525649753757441201883888743925729629
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.46250689442489430868580187930541256748847790795838571908996657011135225449130
Short name T776
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 22 01:36:48 PM PST 23
Finished Nov 22 01:36:51 PM PST 23
Peak memory 205820 kb
Host smart-febc0191-2498-4271-90f1-47903a6bfe8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46250689442489430868580187930541256748847790795838571908996657011135225449130 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 122.edn_genbits.46250689442489430868580187930541256748847790795838571908996657011135225449130
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.112160123600494873387246071239755153990536197040597863870217508139869760067057
Short name T305
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:36:51 PM PST 23
Finished Nov 22 01:36:55 PM PST 23
Peak memory 205892 kb
Host smart-03010dc5-ec88-4e92-852d-3d7036b2b52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112160123600494873387246071239755153990536197040597863870217508139869760067057 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 123.edn_genbits.112160123600494873387246071239755153990536197040597863870217508139869760067057
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.2677886792059629698945898116134351016583969286015130436130360517546992891247
Short name T662
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 22 01:36:52 PM PST 23
Finished Nov 22 01:36:58 PM PST 23
Peak memory 205860 kb
Host smart-545f0d9d-d7b6-4f30-9d74-7a745a6ececb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677886792059629698945898116134351016583969286015130436130360517546992891247 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 124.edn_genbits.2677886792059629698945898116134351016583969286015130436130360517546992891247
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.72813123472322027923035472991809305495383415543364432847975097312057471795631
Short name T665
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:36:52 PM PST 23
Finished Nov 22 01:36:57 PM PST 23
Peak memory 205708 kb
Host smart-84ef22b2-1a8b-455c-b320-a1b58cce8ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72813123472322027923035472991809305495383415543364432847975097312057471795631 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 125.edn_genbits.72813123472322027923035472991809305495383415543364432847975097312057471795631
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.2176637028853941490410282694440556933073045856406166010664609022253890032263
Short name T897
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:36:50 PM PST 23
Finished Nov 22 01:36:55 PM PST 23
Peak memory 205764 kb
Host smart-d65262ac-63dd-4bcc-852a-86f9c260be51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176637028853941490410282694440556933073045856406166010664609022253890032263 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 126.edn_genbits.2176637028853941490410282694440556933073045856406166010664609022253890032263
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.17054037404320974845233538166443667842022172027963689775502151528572683609337
Short name T954
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 22 01:36:53 PM PST 23
Finished Nov 22 01:36:59 PM PST 23
Peak memory 205844 kb
Host smart-0c0b9ff7-cf6d-49eb-8220-dc2a412dcfdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17054037404320974845233538166443667842022172027963689775502151528572683609337 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 127.edn_genbits.17054037404320974845233538166443667842022172027963689775502151528572683609337
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.58812003371156812881707459230164926913716420957950077588977162387669495567960
Short name T892
Test name
Test status
Simulation time 17999183 ps
CPU time 1.03 seconds
Started Nov 22 01:36:49 PM PST 23
Finished Nov 22 01:36:53 PM PST 23
Peak memory 205748 kb
Host smart-0f6ca0c2-f15d-44fa-926d-40edd1dda81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58812003371156812881707459230164926913716420957950077588977162387669495567960 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 128.edn_genbits.58812003371156812881707459230164926913716420957950077588977162387669495567960
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.96717047953299223546353896595667287105138223750794700637317512915739770210046
Short name T416
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Nov 22 01:36:49 PM PST 23
Finished Nov 22 01:36:53 PM PST 23
Peak memory 205660 kb
Host smart-bfd23616-96ac-4d75-8227-7d517d7eb98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96717047953299223546353896595667287105138223750794700637317512915739770210046 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 129.edn_genbits.96717047953299223546353896595667287105138223750794700637317512915739770210046
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.63342959204586141208075312571557638977473981448302544990264653408494867715390
Short name T532
Test name
Test status
Simulation time 18259183 ps
CPU time 0.98 seconds
Started Nov 22 01:33:34 PM PST 23
Finished Nov 22 01:33:40 PM PST 23
Peak memory 205308 kb
Host smart-e6e7a0a5-88f0-4067-8d6a-4fbccbfd68c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63342959204586141208075312571557638977473981448302544990264653408494867715390 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.edn_alert.63342959204586141208075312571557638977473981448302544990264653408494867715390
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.40029836005306367358509034391687498600181914266087809286230906220172393526855
Short name T74
Test name
Test status
Simulation time 28184990 ps
CPU time 0.92 seconds
Started Nov 22 01:33:35 PM PST 23
Finished Nov 22 01:33:40 PM PST 23
Peak memory 205464 kb
Host smart-761d2fcd-f673-402a-a52e-03af0fc9491b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40029836005306367358509034391687498600181914266087809286230906220172393526855 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.edn_alert_test.40029836005306367358509034391687498600181914266087809286230906220172393526855
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.29459657505096534391996722679664065672529125623270808976683702636876520998519
Short name T794
Test name
Test status
Simulation time 12219183 ps
CPU time 0.88 seconds
Started Nov 22 01:33:32 PM PST 23
Finished Nov 22 01:33:34 PM PST 23
Peak memory 214856 kb
Host smart-f016581d-bd80-4247-ae9c-4dca5b8d9454
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29459657505096534391996722679664065672529125623270808976683702636876520998519 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.edn_disable.29459657505096534391996722679664065672529125623270808976683702636876520998519
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.41701384175541779918757699577237558947327652580014103969175777961514090317646
Short name T881
Test name
Test status
Simulation time 14969183 ps
CPU time 0.92 seconds
Started Nov 22 01:33:35 PM PST 23
Finished Nov 22 01:33:40 PM PST 23
Peak memory 214840 kb
Host smart-943c41cc-8bd4-4f4b-9dee-adf228697507
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41701384175541779918757699577237558947327652580014103969175777961514090317646 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable_auto_req_mode.4170138417554177991875769957723755894732765258001410396917
5777961514090317646
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.23262953003163336673284194616473925862225692338544421012238802134299207484244
Short name T392
Test name
Test status
Simulation time 24963823 ps
CPU time 1.13 seconds
Started Nov 22 01:33:34 PM PST 23
Finished Nov 22 01:33:41 PM PST 23
Peak memory 230424 kb
Host smart-0c40d0a0-e4cb-4645-963e-636da7a9a754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23262953003163336673284194616473925862225692338544421012238802134299207484244 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.edn_err.23262953003163336673284194616473925862225692338544421012238802134299207484244
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.25281130128238916675417786202706487892545702380881714745214138162679182503556
Short name T846
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Nov 22 01:33:37 PM PST 23
Finished Nov 22 01:33:41 PM PST 23
Peak memory 205704 kb
Host smart-46dff2b3-f3a0-49d8-9bc2-8ef2f6144106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25281130128238916675417786202706487892545702380881714745214138162679182503556 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.edn_genbits.25281130128238916675417786202706487892545702380881714745214138162679182503556
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.47012599750782225359003462160436490872117233527219796596582802124027495778034
Short name T389
Test name
Test status
Simulation time 18439183 ps
CPU time 1.13 seconds
Started Nov 22 01:33:35 PM PST 23
Finished Nov 22 01:33:41 PM PST 23
Peak memory 221356 kb
Host smart-3f5156d7-a98f-4cf3-afbb-21f96a0d5c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47012599750782225359003462160436490872117233527219796596582802124027495778034 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.edn_intr.47012599750782225359003462160436490872117233527219796596582802124027495778034
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.70908211250980271295739108002745901122570122429245926045612667329879428094628
Short name T605
Test name
Test status
Simulation time 13059183 ps
CPU time 0.9 seconds
Started Nov 22 01:33:28 PM PST 23
Finished Nov 22 01:33:30 PM PST 23
Peak memory 205376 kb
Host smart-62f289d9-017b-48c3-b0f8-149db0d3ea27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70908211250980271295739108002745901122570122429245926045612667329879428094628 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.edn_smoke.70908211250980271295739108002745901122570122429245926045612667329879428094628
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.9652312879896853402617499544607972058534866015457906053083008073740806449723
Short name T326
Test name
Test status
Simulation time 154489183 ps
CPU time 4.01 seconds
Started Nov 22 01:33:30 PM PST 23
Finished Nov 22 01:33:34 PM PST 23
Peak memory 206400 kb
Host smart-568aab99-f437-48f2-bc98-030f1f651605
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9652312879896853402617499544607972058534866015457906053083008073740806449723 -assert nopost
proc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.9652312879896853402617499544607972058534866015457906053083008073740806449723
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.108014760177346591237178223190781301530348908672416055731396923041616959293445
Short name T534
Test name
Test status
Simulation time 41708099183 ps
CPU time 1076.63 seconds
Started Nov 22 01:33:29 PM PST 23
Finished Nov 22 01:51:26 PM PST 23
Peak memory 215876 kb
Host smart-20c9549e-1744-4311-bb44-b63647769972
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108014760177346591237178223
190781301530348908672416055731396923041616959293445 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.1080147601
77346591237178223190781301530348908672416055731396923041616959293445
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.14231004417527710061045499992502807592869993621001228485010010838862362788626
Short name T680
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 22 01:36:51 PM PST 23
Finished Nov 22 01:36:55 PM PST 23
Peak memory 205708 kb
Host smart-ec35f743-3e95-4bb8-ad05-0b93961af7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14231004417527710061045499992502807592869993621001228485010010838862362788626 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 130.edn_genbits.14231004417527710061045499992502807592869993621001228485010010838862362788626
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.101455141047862495627111077293067993820218492713237824904576908761976258212567
Short name T512
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 22 01:36:49 PM PST 23
Finished Nov 22 01:36:53 PM PST 23
Peak memory 205688 kb
Host smart-b509a2e9-3371-4489-938b-4ed6ce5e8693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101455141047862495627111077293067993820218492713237824904576908761976258212567 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 131.edn_genbits.101455141047862495627111077293067993820218492713237824904576908761976258212567
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.85224606156771245682365366023629313950197138954894343334135280793318008593555
Short name T459
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 22 01:36:53 PM PST 23
Finished Nov 22 01:36:59 PM PST 23
Peak memory 205888 kb
Host smart-0b172b2a-a4cc-47d5-b3f6-d6ca99803b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85224606156771245682365366023629313950197138954894343334135280793318008593555 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 132.edn_genbits.85224606156771245682365366023629313950197138954894343334135280793318008593555
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.80452060825990591400419177604074691370088902544503020384201840977122467264168
Short name T625
Test name
Test status
Simulation time 17999183 ps
CPU time 1.06 seconds
Started Nov 22 01:36:51 PM PST 23
Finished Nov 22 01:36:55 PM PST 23
Peak memory 205864 kb
Host smart-dc3c2838-4171-49ee-a3df-82c09f72885a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80452060825990591400419177604074691370088902544503020384201840977122467264168 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 133.edn_genbits.80452060825990591400419177604074691370088902544503020384201840977122467264168
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.112803029434021209162197484522435163205574800345704704791406093400867666971256
Short name T289
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 22 01:36:49 PM PST 23
Finished Nov 22 01:36:52 PM PST 23
Peak memory 205160 kb
Host smart-4027c46a-7fbc-4fbc-981d-582c6d08ec28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112803029434021209162197484522435163205574800345704704791406093400867666971256 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 134.edn_genbits.112803029434021209162197484522435163205574800345704704791406093400867666971256
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.40447146417255172401446435002438019098049237274327929368126894638125200548542
Short name T412
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:36:49 PM PST 23
Finished Nov 22 01:36:53 PM PST 23
Peak memory 205804 kb
Host smart-42ce2f22-a4c0-4144-9f8f-abc44d420aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40447146417255172401446435002438019098049237274327929368126894638125200548542 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 135.edn_genbits.40447146417255172401446435002438019098049237274327929368126894638125200548542
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.54698049752140301064056518219027818550498898318817696563089143885715254637138
Short name T947
Test name
Test status
Simulation time 17999183 ps
CPU time 1.04 seconds
Started Nov 22 01:36:48 PM PST 23
Finished Nov 22 01:36:51 PM PST 23
Peak memory 205784 kb
Host smart-445bceed-50ee-4f81-814e-97ea17ddff2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54698049752140301064056518219027818550498898318817696563089143885715254637138 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 136.edn_genbits.54698049752140301064056518219027818550498898318817696563089143885715254637138
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.98187937940694501770358789082493648489678108660273723987470972953848413586741
Short name T702
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 22 01:36:53 PM PST 23
Finished Nov 22 01:36:59 PM PST 23
Peak memory 205880 kb
Host smart-40bd7c96-9917-4711-969c-f7fa416912ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98187937940694501770358789082493648489678108660273723987470972953848413586741 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 137.edn_genbits.98187937940694501770358789082493648489678108660273723987470972953848413586741
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.2515571175706692791643433798814467147264006976179283536615303352409435196683
Short name T355
Test name
Test status
Simulation time 17999183 ps
CPU time 1.16 seconds
Started Nov 22 01:36:52 PM PST 23
Finished Nov 22 01:36:58 PM PST 23
Peak memory 205844 kb
Host smart-4b421dea-9202-4462-b6f5-beb587f26945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515571175706692791643433798814467147264006976179283536615303352409435196683 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 138.edn_genbits.2515571175706692791643433798814467147264006976179283536615303352409435196683
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.84833946551071975457755772587477586520834608899200681710136970517949670502249
Short name T347
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 22 01:36:53 PM PST 23
Finished Nov 22 01:36:59 PM PST 23
Peak memory 205804 kb
Host smart-1a979d13-63d6-4e3e-9889-bd37c8527ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84833946551071975457755772587477586520834608899200681710136970517949670502249 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 139.edn_genbits.84833946551071975457755772587477586520834608899200681710136970517949670502249
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.69818829500261614599630392549141201652465275351578738854610171819429094662266
Short name T341
Test name
Test status
Simulation time 18259183 ps
CPU time 0.96 seconds
Started Nov 22 01:33:32 PM PST 23
Finished Nov 22 01:33:34 PM PST 23
Peak memory 205564 kb
Host smart-8ab35325-2455-4a1c-89ca-2a923349de12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69818829500261614599630392549141201652465275351578738854610171819429094662266 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.edn_alert.69818829500261614599630392549141201652465275351578738854610171819429094662266
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.73724606725611510934108159644338881772513010577909559408819083023465225007507
Short name T437
Test name
Test status
Simulation time 28184990 ps
CPU time 0.86 seconds
Started Nov 22 01:33:44 PM PST 23
Finished Nov 22 01:33:46 PM PST 23
Peak memory 205468 kb
Host smart-79a66713-3df6-464a-8c74-8675786a7762
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73724606725611510934108159644338881772513010577909559408819083023465225007507 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.edn_alert_test.73724606725611510934108159644338881772513010577909559408819083023465225007507
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.108892883215630091931462999273031818875064734059554390553233174513155437714938
Short name T960
Test name
Test status
Simulation time 12219183 ps
CPU time 0.88 seconds
Started Nov 22 01:33:42 PM PST 23
Finished Nov 22 01:33:45 PM PST 23
Peak memory 214792 kb
Host smart-45320aa9-11d7-496d-b3ca-c8d0d1e8dd58
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108892883215630091931462999273031818875064734059554390553233174513155437714938 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 14.edn_disable.108892883215630091931462999273031818875064734059554390553233174513155437714938
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_err.84344498587158710473924917903275131069603765251233917629654752641989458510821
Short name T93
Test name
Test status
Simulation time 24963823 ps
CPU time 1.12 seconds
Started Nov 22 01:33:41 PM PST 23
Finished Nov 22 01:33:44 PM PST 23
Peak memory 230504 kb
Host smart-fbbd4fc7-c482-4ab8-a87f-dcf8a0394f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84344498587158710473924917903275131069603765251233917629654752641989458510821 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.edn_err.84344498587158710473924917903275131069603765251233917629654752641989458510821
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.75078446358269080081262994076675714231474541880357930314836206509642933579905
Short name T498
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 22 01:33:32 PM PST 23
Finished Nov 22 01:33:34 PM PST 23
Peak memory 205708 kb
Host smart-f70312a0-99c1-4a89-b576-fc19dad4dae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75078446358269080081262994076675714231474541880357930314836206509642933579905 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.edn_genbits.75078446358269080081262994076675714231474541880357930314836206509642933579905
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.16712942817012008182338349406971818076877584752835505840701035628732232250932
Short name T966
Test name
Test status
Simulation time 18439183 ps
CPU time 1.13 seconds
Started Nov 22 01:33:34 PM PST 23
Finished Nov 22 01:33:41 PM PST 23
Peak memory 221988 kb
Host smart-1380a59b-a53c-4bb5-910f-0a268710e8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16712942817012008182338349406971818076877584752835505840701035628732232250932 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.edn_intr.16712942817012008182338349406971818076877584752835505840701035628732232250932
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.70335920797130903214928451935166667159028601068080370900865176182620505621974
Short name T367
Test name
Test status
Simulation time 13059183 ps
CPU time 0.89 seconds
Started Nov 22 01:33:35 PM PST 23
Finished Nov 22 01:33:40 PM PST 23
Peak memory 204416 kb
Host smart-1cb9aacd-598d-4c9f-a82d-d63020a1c49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70335920797130903214928451935166667159028601068080370900865176182620505621974 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.edn_smoke.70335920797130903214928451935166667159028601068080370900865176182620505621974
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.44359730601928886882164034580062249508831735536729575818517694910434581572969
Short name T530
Test name
Test status
Simulation time 154489183 ps
CPU time 4.04 seconds
Started Nov 22 01:33:35 PM PST 23
Finished Nov 22 01:33:44 PM PST 23
Peak memory 206372 kb
Host smart-d907b38b-5b81-45fb-910c-b8ff85c6fb33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44359730601928886882164034580062249508831735536729575818517694910434581572969 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.44359730601928886882164034580062249508831735536729575818517694910434581572969
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.37290786542350614131527289851590189486592487613802974647232124249116013034708
Short name T552
Test name
Test status
Simulation time 41708099183 ps
CPU time 1083.79 seconds
Started Nov 22 01:33:34 PM PST 23
Finished Nov 22 01:51:43 PM PST 23
Peak memory 215824 kb
Host smart-bb57d9c0-9403-47ce-aeef-7dc73c6477d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372907865423506141315272898
51590189486592487613802974647232124249116013034708 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.37290786542
350614131527289851590189486592487613802974647232124249116013034708
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.59865164158920039053784132974863049057070496571095014812320765941274268862968
Short name T63
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:36:49 PM PST 23
Finished Nov 22 01:36:53 PM PST 23
Peak memory 205880 kb
Host smart-a2488f70-d8f8-4209-842a-1d643923655b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59865164158920039053784132974863049057070496571095014812320765941274268862968 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 140.edn_genbits.59865164158920039053784132974863049057070496571095014812320765941274268862968
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.61773257392321267007822353957326996980503759011622296793724521760174902277981
Short name T414
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 22 01:36:35 PM PST 23
Finished Nov 22 01:36:38 PM PST 23
Peak memory 205848 kb
Host smart-273c11a4-7959-4732-ab62-7f1ea739b539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61773257392321267007822353957326996980503759011622296793724521760174902277981 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 141.edn_genbits.61773257392321267007822353957326996980503759011622296793724521760174902277981
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.44558379469413693986012508041285413919845097514303173578465990102323956527800
Short name T696
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:36:27 PM PST 23
Finished Nov 22 01:36:29 PM PST 23
Peak memory 205856 kb
Host smart-c92f6745-eeb3-49de-a408-38be2d0d2c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44558379469413693986012508041285413919845097514303173578465990102323956527800 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 142.edn_genbits.44558379469413693986012508041285413919845097514303173578465990102323956527800
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.97687097498202121694243826344727500218389159783561878648665091639417621884226
Short name T869
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:36:37 PM PST 23
Finished Nov 22 01:36:40 PM PST 23
Peak memory 205868 kb
Host smart-51b00d65-a8d8-47e3-ae25-f5b301ca2682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97687097498202121694243826344727500218389159783561878648665091639417621884226 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 143.edn_genbits.97687097498202121694243826344727500218389159783561878648665091639417621884226
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.68355957132531247101749735792067357992790212429742062174943212873113550284209
Short name T782
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 22 01:36:44 PM PST 23
Finished Nov 22 01:36:46 PM PST 23
Peak memory 205860 kb
Host smart-00992be5-22ab-4818-adcd-c03ced04a602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68355957132531247101749735792067357992790212429742062174943212873113550284209 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 144.edn_genbits.68355957132531247101749735792067357992790212429742062174943212873113550284209
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.38131980946489857448532691621336525631282088339451820679591081644536746534403
Short name T357
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 22 01:36:27 PM PST 23
Finished Nov 22 01:36:29 PM PST 23
Peak memory 205900 kb
Host smart-04cc71ef-cc78-480e-89d2-33759f03a674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38131980946489857448532691621336525631282088339451820679591081644536746534403 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 145.edn_genbits.38131980946489857448532691621336525631282088339451820679591081644536746534403
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.99408624308053854464489088456533988544283635745852965896924212732909298955854
Short name T970
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 22 01:36:36 PM PST 23
Finished Nov 22 01:36:39 PM PST 23
Peak memory 205792 kb
Host smart-0bde4cad-5d8e-4324-a547-9ceebc9ba7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99408624308053854464489088456533988544283635745852965896924212732909298955854 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 146.edn_genbits.99408624308053854464489088456533988544283635745852965896924212732909298955854
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.91436769158878517288328263025584912236074719820184261036428413803868446157445
Short name T12
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:36:27 PM PST 23
Finished Nov 22 01:36:29 PM PST 23
Peak memory 205864 kb
Host smart-9e99613b-bcf7-4ab9-a8fe-fd3a5963bf57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91436769158878517288328263025584912236074719820184261036428413803868446157445 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 147.edn_genbits.91436769158878517288328263025584912236074719820184261036428413803868446157445
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.16969083229534785620459934830773448137094438975035998487637903469657092308414
Short name T438
Test name
Test status
Simulation time 17999183 ps
CPU time 1.16 seconds
Started Nov 22 01:36:33 PM PST 23
Finished Nov 22 01:36:34 PM PST 23
Peak memory 205812 kb
Host smart-ffcdb92f-a956-4bed-beb7-a79d007e8ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16969083229534785620459934830773448137094438975035998487637903469657092308414 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 148.edn_genbits.16969083229534785620459934830773448137094438975035998487637903469657092308414
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.23000514374350337350919657164059508270449063371766795020235262757823117091335
Short name T327
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 22 01:36:36 PM PST 23
Finished Nov 22 01:36:39 PM PST 23
Peak memory 205848 kb
Host smart-18d8007b-6b8a-45c1-a220-bc0cc65798e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23000514374350337350919657164059508270449063371766795020235262757823117091335 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 149.edn_genbits.23000514374350337350919657164059508270449063371766795020235262757823117091335
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.115468088706023425364234849128834336867742414340373587243517928671135620175368
Short name T436
Test name
Test status
Simulation time 18259183 ps
CPU time 0.95 seconds
Started Nov 22 01:33:42 PM PST 23
Finished Nov 22 01:33:45 PM PST 23
Peak memory 205452 kb
Host smart-03c112d3-d9e1-4ad8-a17f-b05ed14f3f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115468088706023425364234849128834336867742414340373587243517928671135620175368 -assert nopostproc +UVM_TESTNAME=edn_aler
t_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.edn_alert.115468088706023425364234849128834336867742414340373587243517928671135620175368
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.47143293834651097013303369518791629286086005407179548351122486774068845062520
Short name T655
Test name
Test status
Simulation time 28184990 ps
CPU time 0.87 seconds
Started Nov 22 01:33:42 PM PST 23
Finished Nov 22 01:33:45 PM PST 23
Peak memory 205532 kb
Host smart-d677a75c-743a-44cf-b34c-519a623f1bf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47143293834651097013303369518791629286086005407179548351122486774068845062520 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.edn_alert_test.47143293834651097013303369518791629286086005407179548351122486774068845062520
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.105704882250155191433373541249715486418115918294806773249918451527276703569943
Short name T539
Test name
Test status
Simulation time 12219183 ps
CPU time 0.9 seconds
Started Nov 22 01:33:42 PM PST 23
Finished Nov 22 01:33:45 PM PST 23
Peak memory 214748 kb
Host smart-49931948-2ec9-4717-b7a7-ef4e350e0cbb
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105704882250155191433373541249715486418115918294806773249918451527276703569943 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 15.edn_disable.105704882250155191433373541249715486418115918294806773249918451527276703569943
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.28093630297637757496222078091728501149644083225867592962339630594934540831881
Short name T608
Test name
Test status
Simulation time 14969183 ps
CPU time 0.92 seconds
Started Nov 22 01:33:45 PM PST 23
Finished Nov 22 01:33:47 PM PST 23
Peak memory 214864 kb
Host smart-f1a912a0-e7cf-405f-a978-8120212523fe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28093630297637757496222078091728501149644083225867592962339630594934540831881 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable_auto_req_mode.2809363029763775749622207809172850114964408322586759296233
9630594934540831881
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.71808155950850846098455245846272859246108696355681263549476391802145385590819
Short name T478
Test name
Test status
Simulation time 24963823 ps
CPU time 1.11 seconds
Started Nov 22 01:33:44 PM PST 23
Finished Nov 22 01:33:46 PM PST 23
Peak memory 230424 kb
Host smart-8e04fc62-53ec-44a8-be95-3086e6ec9c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71808155950850846098455245846272859246108696355681263549476391802145385590819 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.edn_err.71808155950850846098455245846272859246108696355681263549476391802145385590819
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.56380037700271877186293648422206235785222693209933445619361817606881655091189
Short name T572
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:33:41 PM PST 23
Finished Nov 22 01:33:43 PM PST 23
Peak memory 205808 kb
Host smart-9ed1dfe6-f0a5-4130-b9d1-5b07b98e60bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56380037700271877186293648422206235785222693209933445619361817606881655091189 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.edn_genbits.56380037700271877186293648422206235785222693209933445619361817606881655091189
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.69118217350480706031157159255381443493041486479169181616756545290793157127804
Short name T894
Test name
Test status
Simulation time 18439183 ps
CPU time 1.14 seconds
Started Nov 22 01:33:44 PM PST 23
Finished Nov 22 01:33:47 PM PST 23
Peak memory 222228 kb
Host smart-2799f306-3fcb-4174-8290-4bab32eea8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69118217350480706031157159255381443493041486479169181616756545290793157127804 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.edn_intr.69118217350480706031157159255381443493041486479169181616756545290793157127804
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_stress_all.102989514399860981756463374619626893775573824592109591351439317792934608122866
Short name T765
Test name
Test status
Simulation time 154489183 ps
CPU time 3.96 seconds
Started Nov 22 01:33:42 PM PST 23
Finished Nov 22 01:33:48 PM PST 23
Peak memory 206396 kb
Host smart-6c04e4b3-ecf8-48b6-afa8-ee259a13cd18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102989514399860981756463374619626893775573824592109591351439317792934608122866 -assert nopo
stproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.102989514399860981756463374619626893775573824592109591351439317792934608122866
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.31317380600033380495972821185910477118604770583166891206165209002060360160187
Short name T469
Test name
Test status
Simulation time 41708099183 ps
CPU time 1110.98 seconds
Started Nov 22 01:33:46 PM PST 23
Finished Nov 22 01:52:18 PM PST 23
Peak memory 215812 kb
Host smart-b317dc58-98a8-4592-a468-4da88224a01b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313173806000333804959728211
85910477118604770583166891206165209002060360160187 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.31317380600
033380495972821185910477118604770583166891206165209002060360160187
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.57816270240821052103768845310938414877208885152151769161385418540287596726567
Short name T319
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 22 01:36:35 PM PST 23
Finished Nov 22 01:36:38 PM PST 23
Peak memory 205820 kb
Host smart-08248e6f-8e7e-40c4-b60b-b7830e36a579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57816270240821052103768845310938414877208885152151769161385418540287596726567 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 150.edn_genbits.57816270240821052103768845310938414877208885152151769161385418540287596726567
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.26258054107935826121080211509736808844606891585982502218578300433064569900129
Short name T861
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 22 01:36:36 PM PST 23
Finished Nov 22 01:36:39 PM PST 23
Peak memory 205832 kb
Host smart-deacc1b4-e8ed-4b0e-8bcc-2719ef9e8ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26258054107935826121080211509736808844606891585982502218578300433064569900129 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 151.edn_genbits.26258054107935826121080211509736808844606891585982502218578300433064569900129
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.104092673765317908238412222412041651178218516116096150061726979264230298808621
Short name T953
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 22 01:36:49 PM PST 23
Finished Nov 22 01:36:52 PM PST 23
Peak memory 205828 kb
Host smart-43ffb2ee-6199-45ae-9f3b-e7d0bfb091f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104092673765317908238412222412041651178218516116096150061726979264230298808621 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 152.edn_genbits.104092673765317908238412222412041651178218516116096150061726979264230298808621
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.3487753547167750396533265774635179603270003566572846526429318813009903530037
Short name T338
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 22 01:36:52 PM PST 23
Finished Nov 22 01:36:57 PM PST 23
Peak memory 205840 kb
Host smart-63fea6c7-a7f2-4859-8cf0-7f58dbf3a750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487753547167750396533265774635179603270003566572846526429318813009903530037 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 153.edn_genbits.3487753547167750396533265774635179603270003566572846526429318813009903530037
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.32564010691903384375184171967348711424152734245328533286168520062164635533841
Short name T965
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 22 01:36:34 PM PST 23
Finished Nov 22 01:36:36 PM PST 23
Peak memory 205800 kb
Host smart-401cc81f-d53b-497d-8ec0-76fe8070d1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32564010691903384375184171967348711424152734245328533286168520062164635533841 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 154.edn_genbits.32564010691903384375184171967348711424152734245328533286168520062164635533841
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.32300888514725929500191088789268922117494599484618161618891098206314380833517
Short name T624
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 22 01:36:44 PM PST 23
Finished Nov 22 01:36:46 PM PST 23
Peak memory 205848 kb
Host smart-fca37b73-4a99-4e62-a5e5-d5158a68bcbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32300888514725929500191088789268922117494599484618161618891098206314380833517 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 155.edn_genbits.32300888514725929500191088789268922117494599484618161618891098206314380833517
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.79413029943931898456303539386446302384331704588941037989489947343765574805084
Short name T914
Test name
Test status
Simulation time 17999183 ps
CPU time 1.06 seconds
Started Nov 22 01:36:46 PM PST 23
Finished Nov 22 01:36:49 PM PST 23
Peak memory 205780 kb
Host smart-1fc96709-d075-43b6-aa1c-9003b3a0b49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79413029943931898456303539386446302384331704588941037989489947343765574805084 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 156.edn_genbits.79413029943931898456303539386446302384331704588941037989489947343765574805084
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.29718779976391614622713513894824205216624541241851539022382270542806187058085
Short name T750
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 22 01:36:44 PM PST 23
Finished Nov 22 01:36:47 PM PST 23
Peak memory 205880 kb
Host smart-832c712c-cf51-4bec-ba19-23aede635e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29718779976391614622713513894824205216624541241851539022382270542806187058085 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 157.edn_genbits.29718779976391614622713513894824205216624541241851539022382270542806187058085
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.33104533435424120090824952182917561402371660758902361337935528986366831677630
Short name T259
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:36:49 PM PST 23
Finished Nov 22 01:36:52 PM PST 23
Peak memory 205848 kb
Host smart-9bfc59b8-d6ec-498b-a9e2-f1099c8395d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33104533435424120090824952182917561402371660758902361337935528986366831677630 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 158.edn_genbits.33104533435424120090824952182917561402371660758902361337935528986366831677630
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.53516496271523014934112608783965731182268154481235963328146852572734898366655
Short name T772
Test name
Test status
Simulation time 17999183 ps
CPU time 1.16 seconds
Started Nov 22 01:36:50 PM PST 23
Finished Nov 22 01:36:54 PM PST 23
Peak memory 205948 kb
Host smart-1e2b7e70-df76-4d2a-8d6f-b112934b0c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53516496271523014934112608783965731182268154481235963328146852572734898366655 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 159.edn_genbits.53516496271523014934112608783965731182268154481235963328146852572734898366655
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.37434827263425843930408783326765883624786771354517254054327072026644642528084
Short name T293
Test name
Test status
Simulation time 18259183 ps
CPU time 1 seconds
Started Nov 22 01:34:12 PM PST 23
Finished Nov 22 01:34:13 PM PST 23
Peak memory 205524 kb
Host smart-dc4cbc1c-4934-4fbb-b0a9-0d07dd0bee30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37434827263425843930408783326765883624786771354517254054327072026644642528084 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.edn_alert.37434827263425843930408783326765883624786771354517254054327072026644642528084
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.1935079326438269248638824047413545937660976825999245291044439037751090811314
Short name T685
Test name
Test status
Simulation time 28184990 ps
CPU time 0.93 seconds
Started Nov 22 01:34:11 PM PST 23
Finished Nov 22 01:34:13 PM PST 23
Peak memory 205524 kb
Host smart-460dfb8e-f164-4fe5-b260-77080171533c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935079326438269248638824047413545937660976825999245291044439037751090811314 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.edn_alert_test.1935079326438269248638824047413545937660976825999245291044439037751090811314
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.19034925993868467163493849848271932589754187241987864372966072321592500602125
Short name T651
Test name
Test status
Simulation time 12219183 ps
CPU time 0.9 seconds
Started Nov 22 01:33:57 PM PST 23
Finished Nov 22 01:33:59 PM PST 23
Peak memory 214884 kb
Host smart-ea1dc2ad-f518-476f-9a93-64fc2ea185f4
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19034925993868467163493849848271932589754187241987864372966072321592500602125 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.edn_disable.19034925993868467163493849848271932589754187241987864372966072321592500602125
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.33400781586838170527608489478968879322523951413733946150457457712585811998468
Short name T927
Test name
Test status
Simulation time 14969183 ps
CPU time 0.92 seconds
Started Nov 22 01:34:01 PM PST 23
Finished Nov 22 01:34:03 PM PST 23
Peak memory 214868 kb
Host smart-1f3b22fa-cc06-4020-baed-8ef3cb472b2d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33400781586838170527608489478968879322523951413733946150457457712585811998468 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable_auto_req_mode.3340078158683817052760848947896887932252395141373394615045
7457712585811998468
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.50170705237614786562111119323264012215425247063957339962377126513265106758732
Short name T484
Test name
Test status
Simulation time 24963823 ps
CPU time 1.16 seconds
Started Nov 22 01:34:17 PM PST 23
Finished Nov 22 01:34:19 PM PST 23
Peak memory 230348 kb
Host smart-ee509f34-3045-43d1-9c47-3fcb9b314de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50170705237614786562111119323264012215425247063957339962377126513265106758732 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.edn_err.50170705237614786562111119323264012215425247063957339962377126513265106758732
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.888014320587501897788655527076782065686853984089715542609936589362913808860
Short name T284
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 22 01:34:04 PM PST 23
Finished Nov 22 01:34:05 PM PST 23
Peak memory 205732 kb
Host smart-e5279d90-874a-4ab7-b190-59ae1b3615ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888014320587501897788655527076782065686853984089715542609936589362913808860 -assert nopostproc +UVM_TESTNAME=edn_genbits
_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 16.edn_genbits.888014320587501897788655527076782065686853984089715542609936589362913808860
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.46990462400659951152179927361719556232269587578339748450095471954018231335827
Short name T380
Test name
Test status
Simulation time 18439183 ps
CPU time 1.13 seconds
Started Nov 22 01:33:56 PM PST 23
Finished Nov 22 01:33:57 PM PST 23
Peak memory 222164 kb
Host smart-17b39965-b994-4926-9195-d35bf70905d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46990462400659951152179927361719556232269587578339748450095471954018231335827 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.edn_intr.46990462400659951152179927361719556232269587578339748450095471954018231335827
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.95806615915902740157238963253944380851608060173291764816908700108945419251983
Short name T311
Test name
Test status
Simulation time 13059183 ps
CPU time 0.96 seconds
Started Nov 22 01:33:45 PM PST 23
Finished Nov 22 01:33:47 PM PST 23
Peak memory 205356 kb
Host smart-41251ad1-687d-418c-b150-c66ca2184cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95806615915902740157238963253944380851608060173291764816908700108945419251983 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.edn_smoke.95806615915902740157238963253944380851608060173291764816908700108945419251983
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.8692266070480404335441759334291157398712564390169527184378243694930616034816
Short name T859
Test name
Test status
Simulation time 154489183 ps
CPU time 3.92 seconds
Started Nov 22 01:34:01 PM PST 23
Finished Nov 22 01:34:05 PM PST 23
Peak memory 206348 kb
Host smart-00adc546-ffe5-41a7-9c02-ea693dd9ce92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8692266070480404335441759334291157398712564390169527184378243694930616034816 -assert nopost
proc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.8692266070480404335441759334291157398712564390169527184378243694930616034816
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.77794497561097367918669225158399931821555523796342121497854836571469494312936
Short name T656
Test name
Test status
Simulation time 41708099183 ps
CPU time 1107.38 seconds
Started Nov 22 01:34:11 PM PST 23
Finished Nov 22 01:52:39 PM PST 23
Peak memory 215888 kb
Host smart-b7cb66da-13fd-4076-9f78-ee3c0cab85b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777944975610973679186692251
58399931821555523796342121497854836571469494312936 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.77794497561
097367918669225158399931821555523796342121497854836571469494312936
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/161.edn_genbits.32298392413257635817339295683415855823362570648973925159651519448168540679120
Short name T564
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:36:48 PM PST 23
Finished Nov 22 01:36:51 PM PST 23
Peak memory 205848 kb
Host smart-ba3ece7d-66d1-4244-ba7f-6ebcb2de9ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32298392413257635817339295683415855823362570648973925159651519448168540679120 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 161.edn_genbits.32298392413257635817339295683415855823362570648973925159651519448168540679120
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.101144099813158487139803515631301328728964519583962691786671661984402297482389
Short name T876
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 22 01:36:48 PM PST 23
Finished Nov 22 01:36:51 PM PST 23
Peak memory 205832 kb
Host smart-7b0cb242-c7ba-4ec1-9590-c422c0b33eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101144099813158487139803515631301328728964519583962691786671661984402297482389 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 162.edn_genbits.101144099813158487139803515631301328728964519583962691786671661984402297482389
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.73945072446290338109383375914319433489279466146902543715980383689756056142265
Short name T263
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Nov 22 01:36:56 PM PST 23
Finished Nov 22 01:37:02 PM PST 23
Peak memory 205848 kb
Host smart-9e2a283b-f3ae-464e-8b41-84b59c85c125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73945072446290338109383375914319433489279466146902543715980383689756056142265 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 163.edn_genbits.73945072446290338109383375914319433489279466146902543715980383689756056142265
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.93126516940449658938140239212192960229885433192866789297904771051367241206462
Short name T831
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 22 01:36:53 PM PST 23
Finished Nov 22 01:36:58 PM PST 23
Peak memory 205888 kb
Host smart-d1641acb-2a93-42d3-9c22-80765b265877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93126516940449658938140239212192960229885433192866789297904771051367241206462 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 164.edn_genbits.93126516940449658938140239212192960229885433192866789297904771051367241206462
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.39921498436412253946387957531025081517862930963808995297042578637740570166094
Short name T979
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 22 01:36:49 PM PST 23
Finished Nov 22 01:36:52 PM PST 23
Peak memory 205836 kb
Host smart-9766dff8-1f04-4eb7-abfd-03aca556f424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39921498436412253946387957531025081517862930963808995297042578637740570166094 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 165.edn_genbits.39921498436412253946387957531025081517862930963808995297042578637740570166094
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.51392927110904078738089342083388685520540912495676224429328540302332121222564
Short name T826
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:36:50 PM PST 23
Finished Nov 22 01:36:55 PM PST 23
Peak memory 205768 kb
Host smart-f4fc9240-3b83-4d63-90d4-415b4a5a6cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51392927110904078738089342083388685520540912495676224429328540302332121222564 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 166.edn_genbits.51392927110904078738089342083388685520540912495676224429328540302332121222564
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.77564818085906973612924147016021562762000563688856447224802706485351354860526
Short name T426
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:36:52 PM PST 23
Finished Nov 22 01:36:58 PM PST 23
Peak memory 205844 kb
Host smart-b3b4564e-d685-4be0-8233-5eb009b98252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77564818085906973612924147016021562762000563688856447224802706485351354860526 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 167.edn_genbits.77564818085906973612924147016021562762000563688856447224802706485351354860526
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.31376036489241054913716222910144379425240535873590217698051044404079360179718
Short name T350
Test name
Test status
Simulation time 17999183 ps
CPU time 1.06 seconds
Started Nov 22 01:36:50 PM PST 23
Finished Nov 22 01:36:54 PM PST 23
Peak memory 205436 kb
Host smart-927ea1c2-75b3-4218-8194-4193864bd5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31376036489241054913716222910144379425240535873590217698051044404079360179718 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 168.edn_genbits.31376036489241054913716222910144379425240535873590217698051044404079360179718
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.74913311877702353985104917773961807784526883222292106064403604959098565729505
Short name T893
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 22 01:36:51 PM PST 23
Finished Nov 22 01:36:56 PM PST 23
Peak memory 205708 kb
Host smart-47907631-3035-4084-bf4c-bac1d9ba8cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74913311877702353985104917773961807784526883222292106064403604959098565729505 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 169.edn_genbits.74913311877702353985104917773961807784526883222292106064403604959098565729505
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.15795231766677447450014621327452642136764243241195645601981484645769596092516
Short name T902
Test name
Test status
Simulation time 18259183 ps
CPU time 1.05 seconds
Started Nov 22 01:34:12 PM PST 23
Finished Nov 22 01:34:14 PM PST 23
Peak memory 205580 kb
Host smart-a8a1f1fa-171e-4260-bf32-dd7ddb1533ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15795231766677447450014621327452642136764243241195645601981484645769596092516 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.edn_alert.15795231766677447450014621327452642136764243241195645601981484645769596092516
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.77610710390067067653832407565960137895621878074938022558027251765858129369260
Short name T565
Test name
Test status
Simulation time 28184990 ps
CPU time 0.89 seconds
Started Nov 22 01:34:11 PM PST 23
Finished Nov 22 01:34:13 PM PST 23
Peak memory 205512 kb
Host smart-e273d4f6-9394-4b6e-b0a1-567f6169c55d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77610710390067067653832407565960137895621878074938022558027251765858129369260 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.edn_alert_test.77610710390067067653832407565960137895621878074938022558027251765858129369260
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.26483230722875557791572502456597738199252167619497416952511498205293508009186
Short name T394
Test name
Test status
Simulation time 12219183 ps
CPU time 0.89 seconds
Started Nov 22 01:33:57 PM PST 23
Finished Nov 22 01:33:59 PM PST 23
Peak memory 214812 kb
Host smart-d0b2eacc-f701-47ba-b1b9-12b5542e1e62
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26483230722875557791572502456597738199252167619497416952511498205293508009186 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.edn_disable.26483230722875557791572502456597738199252167619497416952511498205293508009186
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.104788285895420633867430581826301554506326337519368047385283538913870427288694
Short name T907
Test name
Test status
Simulation time 14969183 ps
CPU time 0.86 seconds
Started Nov 22 01:34:03 PM PST 23
Finished Nov 22 01:34:05 PM PST 23
Peak memory 214776 kb
Host smart-6b0ebc6d-4d50-4a11-ade5-0ce8a3c29e86
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104788285895420633867430581826301554506326337519368047385283538913870427288694 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable_auto_req_mode.104788285895420633867430581826301554506326337519368047385
283538913870427288694
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.68669954979723754122116126099061878035205095316840127414589883704794083477430
Short name T884
Test name
Test status
Simulation time 24963823 ps
CPU time 1.17 seconds
Started Nov 22 01:34:03 PM PST 23
Finished Nov 22 01:34:05 PM PST 23
Peak memory 230456 kb
Host smart-fff80f2b-bb61-4e22-a04e-63c4a1caa202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68669954979723754122116126099061878035205095316840127414589883704794083477430 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.edn_err.68669954979723754122116126099061878035205095316840127414589883704794083477430
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.57298535335369720840730916940246474943763161780623231965068904389084923482133
Short name T563
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:33:58 PM PST 23
Finished Nov 22 01:34:00 PM PST 23
Peak memory 205764 kb
Host smart-1b2aa443-6f1f-4200-b1a5-3265e62a3d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57298535335369720840730916940246474943763161780623231965068904389084923482133 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.edn_genbits.57298535335369720840730916940246474943763161780623231965068904389084923482133
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.114776031622085279835007318480520661490815279142835201957513505803285711193341
Short name T435
Test name
Test status
Simulation time 18439183 ps
CPU time 1.13 seconds
Started Nov 22 01:33:58 PM PST 23
Finished Nov 22 01:33:59 PM PST 23
Peak memory 222276 kb
Host smart-4a6b71ad-aa10-4869-9eef-8ba3066edd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114776031622085279835007318480520661490815279142835201957513505803285711193341 -assert nopostproc +UVM_TESTNAME=edn_intr
_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.edn_intr.114776031622085279835007318480520661490815279142835201957513505803285711193341
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.54941619811522294362198256291945832986419167706308840253417338868006368015276
Short name T455
Test name
Test status
Simulation time 13059183 ps
CPU time 0.9 seconds
Started Nov 22 01:34:07 PM PST 23
Finished Nov 22 01:34:10 PM PST 23
Peak memory 205356 kb
Host smart-a1c082fa-e98d-470b-b3b9-49a9a0dee02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54941619811522294362198256291945832986419167706308840253417338868006368015276 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.edn_smoke.54941619811522294362198256291945832986419167706308840253417338868006368015276
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.8176622249710195429486734003455563455114114325190886410487380333397987076324
Short name T399
Test name
Test status
Simulation time 154489183 ps
CPU time 3.81 seconds
Started Nov 22 01:34:03 PM PST 23
Finished Nov 22 01:34:08 PM PST 23
Peak memory 206264 kb
Host smart-193fd93a-e12b-49eb-bde0-e02ef307fab3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8176622249710195429486734003455563455114114325190886410487380333397987076324 -assert nopost
proc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.8176622249710195429486734003455563455114114325190886410487380333397987076324
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.80266545191820451250621439650366336192213224555322951363025413360180104835955
Short name T652
Test name
Test status
Simulation time 41708099183 ps
CPU time 1063.99 seconds
Started Nov 22 01:34:14 PM PST 23
Finished Nov 22 01:51:59 PM PST 23
Peak memory 215832 kb
Host smart-348f0298-58cd-4487-ba06-17817172b2b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802665451918204512506214396
50366336192213224555322951363025413360180104835955 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.80266545191
820451250621439650366336192213224555322951363025413360180104835955
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.25021345320626838036076551976195544068790791043836075635498754467839715124629
Short name T536
Test name
Test status
Simulation time 17999183 ps
CPU time 1.05 seconds
Started Nov 22 01:36:49 PM PST 23
Finished Nov 22 01:36:52 PM PST 23
Peak memory 205820 kb
Host smart-455d85fb-d965-4fd8-8646-c1b9686d83e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25021345320626838036076551976195544068790791043836075635498754467839715124629 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 170.edn_genbits.25021345320626838036076551976195544068790791043836075635498754467839715124629
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.9553654614665011266245184944142852510324640535673809592408274291028771089364
Short name T526
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Nov 22 01:36:56 PM PST 23
Finished Nov 22 01:37:02 PM PST 23
Peak memory 205848 kb
Host smart-24c0a225-e1bf-4028-afec-b04ed4217468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9553654614665011266245184944142852510324640535673809592408274291028771089364 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 171.edn_genbits.9553654614665011266245184944142852510324640535673809592408274291028771089364
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.112151833026326066872405833465853105169058914782387046894450106632421905618102
Short name T611
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 22 01:36:51 PM PST 23
Finished Nov 22 01:36:55 PM PST 23
Peak memory 205760 kb
Host smart-1d13b9c1-b191-41c8-bc33-ffba8595b2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112151833026326066872405833465853105169058914782387046894450106632421905618102 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 172.edn_genbits.112151833026326066872405833465853105169058914782387046894450106632421905618102
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.102849562353548546863667524229925544390425289568248111514792888465447134086548
Short name T458
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:36:51 PM PST 23
Finished Nov 22 01:36:56 PM PST 23
Peak memory 205860 kb
Host smart-1c4d147d-b178-4cbe-a727-8a1249cb2610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102849562353548546863667524229925544390425289568248111514792888465447134086548 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 173.edn_genbits.102849562353548546863667524229925544390425289568248111514792888465447134086548
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.31254581879961630891017140404038947209566589383679611386918680760375002012041
Short name T364
Test name
Test status
Simulation time 17999183 ps
CPU time 1.16 seconds
Started Nov 22 01:36:56 PM PST 23
Finished Nov 22 01:37:02 PM PST 23
Peak memory 205652 kb
Host smart-50501fd6-da92-4b57-8035-447dfd091f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31254581879961630891017140404038947209566589383679611386918680760375002012041 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 174.edn_genbits.31254581879961630891017140404038947209566589383679611386918680760375002012041
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.104248832766518164480887943385612714435434969760915700846306711351528846377436
Short name T369
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:36:52 PM PST 23
Finished Nov 22 01:36:57 PM PST 23
Peak memory 205860 kb
Host smart-849f3e83-eb07-43f3-9897-076775f52172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104248832766518164480887943385612714435434969760915700846306711351528846377436 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 175.edn_genbits.104248832766518164480887943385612714435434969760915700846306711351528846377436
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.17342579287120514776276518216023511572077375966379939307934960350518884629694
Short name T576
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 22 01:36:53 PM PST 23
Finished Nov 22 01:36:59 PM PST 23
Peak memory 205804 kb
Host smart-84063fce-cfb7-4f69-99e5-b7d093c40e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17342579287120514776276518216023511572077375966379939307934960350518884629694 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 176.edn_genbits.17342579287120514776276518216023511572077375966379939307934960350518884629694
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.44237309611785505379148016457507437162524407423399423108177912582937650552405
Short name T241
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 22 01:36:53 PM PST 23
Finished Nov 22 01:36:59 PM PST 23
Peak memory 205880 kb
Host smart-3654f284-abd4-48ea-8218-228b00c91a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44237309611785505379148016457507437162524407423399423108177912582937650552405 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 177.edn_genbits.44237309611785505379148016457507437162524407423399423108177912582937650552405
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.93756936516218562737364704186996643012973971345813889578608117855881076760758
Short name T603
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 22 01:36:53 PM PST 23
Finished Nov 22 01:36:59 PM PST 23
Peak memory 205804 kb
Host smart-643534e0-475a-41e1-a713-895f79f137e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93756936516218562737364704186996643012973971345813889578608117855881076760758 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 178.edn_genbits.93756936516218562737364704186996643012973971345813889578608117855881076760758
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.88906096675909451925601267922612308507310207372827922470959553115142550334439
Short name T674
Test name
Test status
Simulation time 17999183 ps
CPU time 1.05 seconds
Started Nov 22 01:36:48 PM PST 23
Finished Nov 22 01:36:50 PM PST 23
Peak memory 205784 kb
Host smart-d87cbf52-b7f5-4580-9118-bb677afe3fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88906096675909451925601267922612308507310207372827922470959553115142550334439 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 179.edn_genbits.88906096675909451925601267922612308507310207372827922470959553115142550334439
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.98961477889954206236186034797315739833097739114467673878363068975481494112434
Short name T944
Test name
Test status
Simulation time 18259183 ps
CPU time 0.97 seconds
Started Nov 22 01:34:02 PM PST 23
Finished Nov 22 01:34:04 PM PST 23
Peak memory 205416 kb
Host smart-972d4fd0-d8cb-40db-aa16-602c42b79ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98961477889954206236186034797315739833097739114467673878363068975481494112434 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.edn_alert.98961477889954206236186034797315739833097739114467673878363068975481494112434
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.11595012532601338736545895315623673752955137631551251588330677735989684208822
Short name T937
Test name
Test status
Simulation time 28184990 ps
CPU time 0.93 seconds
Started Nov 22 01:34:15 PM PST 23
Finished Nov 22 01:34:17 PM PST 23
Peak memory 205408 kb
Host smart-b898ce04-f3d9-4722-9c39-650e511e5291
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11595012532601338736545895315623673752955137631551251588330677735989684208822 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.edn_alert_test.11595012532601338736545895315623673752955137631551251588330677735989684208822
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.101657009540092301614368452591476602326833642820523358013628951304599402163911
Short name T467
Test name
Test status
Simulation time 12219183 ps
CPU time 0.9 seconds
Started Nov 22 01:34:11 PM PST 23
Finished Nov 22 01:34:13 PM PST 23
Peak memory 214756 kb
Host smart-e0812237-6361-4df9-b20e-e4a8ab354bb3
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101657009540092301614368452591476602326833642820523358013628951304599402163911 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 18.edn_disable.101657009540092301614368452591476602326833642820523358013628951304599402163911
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.97637539691430905779239976880404893287663656267308433475715903799197973283102
Short name T725
Test name
Test status
Simulation time 14969183 ps
CPU time 0.9 seconds
Started Nov 22 01:34:12 PM PST 23
Finished Nov 22 01:34:14 PM PST 23
Peak memory 214820 kb
Host smart-591046ce-5228-43cd-9bd1-7c78b3148b4d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97637539691430905779239976880404893287663656267308433475715903799197973283102 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable_auto_req_mode.9763753969143090577923997688040489328766365626730843347571
5903799197973283102
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.101128949605686051576382343141257856093464864832774863040649287923368915494339
Short name T775
Test name
Test status
Simulation time 24963823 ps
CPU time 1.16 seconds
Started Nov 22 01:34:15 PM PST 23
Finished Nov 22 01:34:17 PM PST 23
Peak memory 230440 kb
Host smart-54932208-74c9-4587-bf60-3a76e2563d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101128949605686051576382343141257856093464864832774863040649287923368915494339 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.edn_err.101128949605686051576382343141257856093464864832774863040649287923368915494339
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.100525234424951022868781280911948755495173455903353023229808278173875416409067
Short name T679
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 22 01:34:14 PM PST 23
Finished Nov 22 01:34:17 PM PST 23
Peak memory 205856 kb
Host smart-6f1df5d2-1ba5-4a15-8997-74a2a7be287e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100525234424951022868781280911948755495173455903353023229808278173875416409067 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 18.edn_genbits.100525234424951022868781280911948755495173455903353023229808278173875416409067
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.68002811039745605526739212160884424253100797006447036972385952857844801750897
Short name T376
Test name
Test status
Simulation time 18439183 ps
CPU time 1.16 seconds
Started Nov 22 01:34:15 PM PST 23
Finished Nov 22 01:34:17 PM PST 23
Peak memory 222248 kb
Host smart-522ed8fb-1227-4758-9b6f-5e56f7fe43d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68002811039745605526739212160884424253100797006447036972385952857844801750897 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.edn_intr.68002811039745605526739212160884424253100797006447036972385952857844801750897
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.35754350543267250728880462644365629295896859275614455740137311387618722505174
Short name T643
Test name
Test status
Simulation time 13059183 ps
CPU time 0.94 seconds
Started Nov 22 01:34:03 PM PST 23
Finished Nov 22 01:34:05 PM PST 23
Peak memory 205380 kb
Host smart-a3cad350-958a-4e08-aaab-ee61b0731eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35754350543267250728880462644365629295896859275614455740137311387618722505174 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.edn_smoke.35754350543267250728880462644365629295896859275614455740137311387618722505174
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.93809495790587021776315805709696139547525099843383115999936630938265028472695
Short name T323
Test name
Test status
Simulation time 154489183 ps
CPU time 4.01 seconds
Started Nov 22 01:34:13 PM PST 23
Finished Nov 22 01:34:19 PM PST 23
Peak memory 206308 kb
Host smart-41b54e9f-107c-49c7-9644-09450158d917
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93809495790587021776315805709696139547525099843383115999936630938265028472695 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.93809495790587021776315805709696139547525099843383115999936630938265028472695
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.27849455736920778032505263066972501953640258400697211378456392981773288015369
Short name T420
Test name
Test status
Simulation time 41708099183 ps
CPU time 1107.67 seconds
Started Nov 22 01:34:19 PM PST 23
Finished Nov 22 01:52:47 PM PST 23
Peak memory 215860 kb
Host smart-35863b5d-6300-489c-9765-ed2a5a4a95b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278494557369207780325052630
66972501953640258400697211378456392981773288015369 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.27849455736
920778032505263066972501953640258400697211378456392981773288015369
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.5094192263216724570451248693535464494932990032938121728335327703041494046488
Short name T510
Test name
Test status
Simulation time 17999183 ps
CPU time 1.17 seconds
Started Nov 22 01:36:53 PM PST 23
Finished Nov 22 01:36:59 PM PST 23
Peak memory 205784 kb
Host smart-f02ad142-11d5-45a8-9e5b-b4ff57b7db36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5094192263216724570451248693535464494932990032938121728335327703041494046488 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 180.edn_genbits.5094192263216724570451248693535464494932990032938121728335327703041494046488
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.55930879171403198657176920512712625872848474329869187632071773648742293985151
Short name T974
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:36:54 PM PST 23
Finished Nov 22 01:37:01 PM PST 23
Peak memory 205848 kb
Host smart-3b4242b1-e408-4690-840e-178ea4e869d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55930879171403198657176920512712625872848474329869187632071773648742293985151 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 181.edn_genbits.55930879171403198657176920512712625872848474329869187632071773648742293985151
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.32547137226199250626301069116823664258721767309122900845050364784474656659171
Short name T845
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 22 01:36:35 PM PST 23
Finished Nov 22 01:36:37 PM PST 23
Peak memory 205764 kb
Host smart-5c89b641-80eb-4404-aa12-8267e0561f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32547137226199250626301069116823664258721767309122900845050364784474656659171 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 182.edn_genbits.32547137226199250626301069116823664258721767309122900845050364784474656659171
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.93216627841420641454442776824225172293753866289504373196183148386050908609579
Short name T286
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Nov 22 01:36:35 PM PST 23
Finished Nov 22 01:36:38 PM PST 23
Peak memory 205812 kb
Host smart-725f13b2-79ef-4dd7-88f4-54324c46023a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93216627841420641454442776824225172293753866289504373196183148386050908609579 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 183.edn_genbits.93216627841420641454442776824225172293753866289504373196183148386050908609579
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.55451174216071526628763706214315292045110663079011512625542054186043422765380
Short name T453
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 22 01:36:35 PM PST 23
Finished Nov 22 01:36:38 PM PST 23
Peak memory 205792 kb
Host smart-7f13b039-b0f9-4a41-80fb-0bc768f025d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55451174216071526628763706214315292045110663079011512625542054186043422765380 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 184.edn_genbits.55451174216071526628763706214315292045110663079011512625542054186043422765380
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.85966919573729446971623438532865455882232313520900349060432172781204970021440
Short name T490
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:36:36 PM PST 23
Finished Nov 22 01:36:40 PM PST 23
Peak memory 205944 kb
Host smart-52113169-d909-49ff-9602-b09279eab052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85966919573729446971623438532865455882232313520900349060432172781204970021440 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 185.edn_genbits.85966919573729446971623438532865455882232313520900349060432172781204970021440
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.103341656864403438131474334965750797935331163315040284252397076106992154427418
Short name T255
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 22 01:36:35 PM PST 23
Finished Nov 22 01:36:37 PM PST 23
Peak memory 205804 kb
Host smart-abc9dcc7-b9c5-406d-a5d4-448a61dc6e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103341656864403438131474334965750797935331163315040284252397076106992154427418 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 186.edn_genbits.103341656864403438131474334965750797935331163315040284252397076106992154427418
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.44505442414006008672417538571794677638239610029652368391960245013294241318666
Short name T618
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:36:36 PM PST 23
Finished Nov 22 01:36:39 PM PST 23
Peak memory 205840 kb
Host smart-b027d764-b617-4e04-bce6-b44ac3a99664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44505442414006008672417538571794677638239610029652368391960245013294241318666 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 187.edn_genbits.44505442414006008672417538571794677638239610029652368391960245013294241318666
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.114743305934892234515362141113283300715026308305584017106624542453379720396086
Short name T315
Test name
Test status
Simulation time 17999183 ps
CPU time 1.17 seconds
Started Nov 22 01:36:35 PM PST 23
Finished Nov 22 01:36:37 PM PST 23
Peak memory 205820 kb
Host smart-3d3f1bdb-4f1b-4333-b82d-c48ba401fba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114743305934892234515362141113283300715026308305584017106624542453379720396086 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 188.edn_genbits.114743305934892234515362141113283300715026308305584017106624542453379720396086
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.77453167855915502267966858651225810803463729911229552872053526352013119383063
Short name T514
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:36:35 PM PST 23
Finished Nov 22 01:36:37 PM PST 23
Peak memory 205808 kb
Host smart-f67474af-e81c-4087-8bf7-0b82bb1a85ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77453167855915502267966858651225810803463729911229552872053526352013119383063 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 189.edn_genbits.77453167855915502267966858651225810803463729911229552872053526352013119383063
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.56755918349429999827807373970265136463172635751719722217866285542543647366068
Short name T978
Test name
Test status
Simulation time 18259183 ps
CPU time 0.98 seconds
Started Nov 22 01:34:11 PM PST 23
Finished Nov 22 01:34:13 PM PST 23
Peak memory 205412 kb
Host smart-5b30efd7-3637-4e20-b33d-827ba50befd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56755918349429999827807373970265136463172635751719722217866285542543647366068 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.edn_alert.56755918349429999827807373970265136463172635751719722217866285542543647366068
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.94255780368014661303138036351247949307527305435328854981559604832805195990389
Short name T654
Test name
Test status
Simulation time 28184990 ps
CPU time 0.88 seconds
Started Nov 22 01:34:14 PM PST 23
Finished Nov 22 01:34:16 PM PST 23
Peak memory 205540 kb
Host smart-9b03b623-a726-45e1-92ec-51d367430af2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94255780368014661303138036351247949307527305435328854981559604832805195990389 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.edn_alert_test.94255780368014661303138036351247949307527305435328854981559604832805195990389
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.75223646830807195854245662251869160598962417160513152391453813536775301830315
Short name T584
Test name
Test status
Simulation time 12219183 ps
CPU time 0.85 seconds
Started Nov 22 01:34:18 PM PST 23
Finished Nov 22 01:34:20 PM PST 23
Peak memory 214852 kb
Host smart-18fb4199-d820-4dc0-bd66-0a4482dbf968
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75223646830807195854245662251869160598962417160513152391453813536775301830315 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.edn_disable.75223646830807195854245662251869160598962417160513152391453813536775301830315
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.6117953005295699945114893240435360052452257549292749746148380529796106725267
Short name T299
Test name
Test status
Simulation time 14969183 ps
CPU time 0.93 seconds
Started Nov 22 01:34:16 PM PST 23
Finished Nov 22 01:34:18 PM PST 23
Peak memory 214872 kb
Host smart-ff36f70a-d45f-4e74-ba9d-e612c60f8237
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6117953005295699945114893240435360052452257549292749746148380529796106725267 -assert nopostproc
+UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable_auto_req_mode.61179530052956999451148932404353600524522575492927497461483
80529796106725267
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.106339110698940419344987891177797829329294041850872240737274267418203348364598
Short name T798
Test name
Test status
Simulation time 24963823 ps
CPU time 1.14 seconds
Started Nov 22 01:34:14 PM PST 23
Finished Nov 22 01:34:17 PM PST 23
Peak memory 230440 kb
Host smart-87a126e3-ae2a-400d-a8ca-7d6e63246d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106339110698940419344987891177797829329294041850872240737274267418203348364598 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.edn_err.106339110698940419344987891177797829329294041850872240737274267418203348364598
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.59160499247298717724609334612014642816053070291191202518795507519439698754352
Short name T481
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 22 01:34:01 PM PST 23
Finished Nov 22 01:34:03 PM PST 23
Peak memory 205712 kb
Host smart-780c97a2-7235-40a1-a470-14913ae825d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59160499247298717724609334612014642816053070291191202518795507519439698754352 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.edn_genbits.59160499247298717724609334612014642816053070291191202518795507519439698754352
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.66313709578450150531940265008026828763282820901066528335282115158791016271037
Short name T788
Test name
Test status
Simulation time 18439183 ps
CPU time 1.16 seconds
Started Nov 22 01:34:12 PM PST 23
Finished Nov 22 01:34:14 PM PST 23
Peak memory 222220 kb
Host smart-e786368b-6ffb-46ad-b4c1-895466a50d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66313709578450150531940265008026828763282820901066528335282115158791016271037 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.edn_intr.66313709578450150531940265008026828763282820901066528335282115158791016271037
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.13415891280284886161045053572127399620139524448065185986561691952504246353649
Short name T819
Test name
Test status
Simulation time 13059183 ps
CPU time 0.94 seconds
Started Nov 22 01:34:02 PM PST 23
Finished Nov 22 01:34:04 PM PST 23
Peak memory 205400 kb
Host smart-0fd24ed6-4f79-419a-90a9-8150abafc2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13415891280284886161045053572127399620139524448065185986561691952504246353649 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.edn_smoke.13415891280284886161045053572127399620139524448065185986561691952504246353649
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.70572980206530498076658174546778363497646572410067092730564699191554503881810
Short name T370
Test name
Test status
Simulation time 154489183 ps
CPU time 3.93 seconds
Started Nov 22 01:34:17 PM PST 23
Finished Nov 22 01:34:22 PM PST 23
Peak memory 206328 kb
Host smart-17f28c06-2356-4f04-8a76-5bc5616c734b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70572980206530498076658174546778363497646572410067092730564699191554503881810 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.70572980206530498076658174546778363497646572410067092730564699191554503881810
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.98318815516106703620915398542698504850367542105597869222723752097647908165862
Short name T237
Test name
Test status
Simulation time 41708099183 ps
CPU time 1084.94 seconds
Started Nov 22 01:34:12 PM PST 23
Finished Nov 22 01:52:18 PM PST 23
Peak memory 215968 kb
Host smart-efb61dd6-7807-4224-bd7e-2c675f680a6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983188155161067036209153985
42698504850367542105597869222723752097647908165862 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.98318815516
106703620915398542698504850367542105597869222723752097647908165862
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.46696851971101853377915686957146880395424127652396901448380823985939070247188
Short name T274
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:36:30 PM PST 23
Finished Nov 22 01:36:32 PM PST 23
Peak memory 205856 kb
Host smart-58a4e95e-e8c5-482e-b894-ca0f8d67f3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46696851971101853377915686957146880395424127652396901448380823985939070247188 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 190.edn_genbits.46696851971101853377915686957146880395424127652396901448380823985939070247188
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.45237397001354729137193768059552812039091451528347363268312846056606969624839
Short name T528
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:36:44 PM PST 23
Finished Nov 22 01:36:45 PM PST 23
Peak memory 205840 kb
Host smart-6dbf5f02-962c-492b-a5e9-5c7fefddd454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45237397001354729137193768059552812039091451528347363268312846056606969624839 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 191.edn_genbits.45237397001354729137193768059552812039091451528347363268312846056606969624839
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.86851054627224509403128687306916038740128883131854694175515321301223536484722
Short name T457
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:36:36 PM PST 23
Finished Nov 22 01:36:40 PM PST 23
Peak memory 205868 kb
Host smart-a08c24d7-772e-4950-a9cc-0af173e8edf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86851054627224509403128687306916038740128883131854694175515321301223536484722 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 192.edn_genbits.86851054627224509403128687306916038740128883131854694175515321301223536484722
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.45134539425751049636857354809057067318238046862411875294661488607509241437076
Short name T261
Test name
Test status
Simulation time 17999183 ps
CPU time 1.16 seconds
Started Nov 22 01:36:35 PM PST 23
Finished Nov 22 01:36:37 PM PST 23
Peak memory 205744 kb
Host smart-7c746c39-ee62-4fb0-84f8-7a2718de14f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45134539425751049636857354809057067318238046862411875294661488607509241437076 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 193.edn_genbits.45134539425751049636857354809057067318238046862411875294661488607509241437076
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.16888123431264044186938971320502545612153822870684951257264215411400439875433
Short name T888
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:36:44 PM PST 23
Finished Nov 22 01:36:47 PM PST 23
Peak memory 205812 kb
Host smart-219334ec-b2ca-4dc1-a4ab-609dec7e7c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16888123431264044186938971320502545612153822870684951257264215411400439875433 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 194.edn_genbits.16888123431264044186938971320502545612153822870684951257264215411400439875433
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.34896387964687243086429798936861496507790102446050029918399517220920949854527
Short name T741
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:36:28 PM PST 23
Finished Nov 22 01:36:31 PM PST 23
Peak memory 205836 kb
Host smart-b4e5d3a9-051d-49c4-ad3b-e5f4ec13199c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34896387964687243086429798936861496507790102446050029918399517220920949854527 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 195.edn_genbits.34896387964687243086429798936861496507790102446050029918399517220920949854527
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.37282657869932440379173067252361454902991830844461924439437862029049927643323
Short name T691
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 22 01:36:36 PM PST 23
Finished Nov 22 01:36:38 PM PST 23
Peak memory 205812 kb
Host smart-3e57876b-6fd4-470b-a2fa-78182e01e740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37282657869932440379173067252361454902991830844461924439437862029049927643323 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 196.edn_genbits.37282657869932440379173067252361454902991830844461924439437862029049927643323
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.22864009453706482622421668236653629736693272465243384341719596779287743566145
Short name T509
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 22 01:36:32 PM PST 23
Finished Nov 22 01:36:34 PM PST 23
Peak memory 205856 kb
Host smart-556cf94f-d4e0-410a-ad49-43d7371d6873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22864009453706482622421668236653629736693272465243384341719596779287743566145 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 197.edn_genbits.22864009453706482622421668236653629736693272465243384341719596779287743566145
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.109936844637924054750555037466635084401411581825898128696526903063800360928380
Short name T501
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 22 01:36:36 PM PST 23
Finished Nov 22 01:36:40 PM PST 23
Peak memory 205940 kb
Host smart-2ffa2cd0-4fc5-4892-9afe-6461c89ea3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109936844637924054750555037466635084401411581825898128696526903063800360928380 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 198.edn_genbits.109936844637924054750555037466635084401411581825898128696526903063800360928380
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.96342953863575252860859718732205811066927984343787618895451159895015689731330
Short name T278
Test name
Test status
Simulation time 17999183 ps
CPU time 1.18 seconds
Started Nov 22 01:36:28 PM PST 23
Finished Nov 22 01:36:29 PM PST 23
Peak memory 205832 kb
Host smart-dbbacdb1-1bc2-474a-a5f3-11344e251405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96342953863575252860859718732205811066927984343787618895451159895015689731330 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 199.edn_genbits.96342953863575252860859718732205811066927984343787618895451159895015689731330
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.46878628104766471289457404714049735358168682589409549703556236866244401053830
Short name T874
Test name
Test status
Simulation time 18259183 ps
CPU time 0.97 seconds
Started Nov 22 01:31:35 PM PST 23
Finished Nov 22 01:31:38 PM PST 23
Peak memory 205508 kb
Host smart-ed6b5a48-0a63-46a1-9f1b-95842a9ea1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46878628104766471289457404714049735358168682589409549703556236866244401053830 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.edn_alert.46878628104766471289457404714049735358168682589409549703556236866244401053830
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.46310770926791242669487596371204877030160428190817074072449265866488776241738
Short name T406
Test name
Test status
Simulation time 28184990 ps
CPU time 0.83 seconds
Started Nov 22 01:31:34 PM PST 23
Finished Nov 22 01:31:37 PM PST 23
Peak memory 205344 kb
Host smart-5d584bbd-539d-4e33-b5ea-296fffb0a227
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46310770926791242669487596371204877030160428190817074072449265866488776241738 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.edn_alert_test.46310770926791242669487596371204877030160428190817074072449265866488776241738
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.29277892858256370894788529730052107065480045096749782689327442555662497806469
Short name T349
Test name
Test status
Simulation time 12219183 ps
CPU time 0.87 seconds
Started Nov 22 01:31:36 PM PST 23
Finished Nov 22 01:31:39 PM PST 23
Peak memory 214888 kb
Host smart-3c25cf23-16de-49ee-9ac5-05f38dacc719
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29277892858256370894788529730052107065480045096749782689327442555662497806469 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.edn_disable.29277892858256370894788529730052107065480045096749782689327442555662497806469
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.86861387019162825840044230706559758370303252100594656045331983121428835338377
Short name T553
Test name
Test status
Simulation time 14969183 ps
CPU time 0.93 seconds
Started Nov 22 01:31:36 PM PST 23
Finished Nov 22 01:31:39 PM PST 23
Peak memory 214816 kb
Host smart-6922ef39-c9d7-47b7-81ef-41314d92fd9f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86861387019162825840044230706559758370303252100594656045331983121428835338377 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable_auto_req_mode.86861387019162825840044230706559758370303252100594656045331
983121428835338377
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.18888761127120702474882878959720432576742847015559366436805439851645399629277
Short name T711
Test name
Test status
Simulation time 24963823 ps
CPU time 1.12 seconds
Started Nov 22 01:31:35 PM PST 23
Finished Nov 22 01:31:38 PM PST 23
Peak memory 230344 kb
Host smart-2daa3ea4-27ce-4e84-a5f1-125fd2145b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18888761127120702474882878959720432576742847015559366436805439851645399629277 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
edn_err.18888761127120702474882878959720432576742847015559366436805439851645399629277
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.107609312214946055684923239372138874027479529946835516692565870268467450899013
Short name T460
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:31:36 PM PST 23
Finished Nov 22 01:31:39 PM PST 23
Peak memory 205740 kb
Host smart-83f7b188-3d00-4bb5-8881-71f44dd765b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107609312214946055684923239372138874027479529946835516692565870268467450899013 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.edn_genbits.107609312214946055684923239372138874027479529946835516692565870268467450899013
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.93446826607886852922416462515347098059576090315458918657786094544142717711196
Short name T735
Test name
Test status
Simulation time 18439183 ps
CPU time 1.12 seconds
Started Nov 22 01:31:40 PM PST 23
Finished Nov 22 01:31:42 PM PST 23
Peak memory 222276 kb
Host smart-dc0e6ebe-2bce-48c8-ab9d-fd1b58819782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93446826607886852922416462515347098059576090315458918657786094544142717711196 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.edn_intr.93446826607886852922416462515347098059576090315458918657786094544142717711196
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.88475045172546921047071793787532491400513643718113277924661150947377190731638
Short name T689
Test name
Test status
Simulation time 11759183 ps
CPU time 0.87 seconds
Started Nov 22 01:31:37 PM PST 23
Finished Nov 22 01:31:39 PM PST 23
Peak memory 205340 kb
Host smart-991d9610-865b-4078-b8c1-de90e9d8bf8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88475045172546921047071793787532491400513643718113277924661150947377190731638 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.edn_regwen.88475045172546921047071793787532491400513643718113277924661150947377190731638
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.53319423768271612401247776322381822396250472532307264494574435386617610413031
Short name T31
Test name
Test status
Simulation time 717215632 ps
CPU time 5.8 seconds
Started Nov 22 01:31:37 PM PST 23
Finished Nov 22 01:31:44 PM PST 23
Peak memory 234076 kb
Host smart-2a3d75f2-d31c-4b2e-a4e1-0aa2d8e29118
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53319423768271612401247776322381822396250472532307264494574435386617610413031 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.edn_sec_cm.53319423768271612401247776322381822396250472532307264494574435386617610413031
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.30806522326951515271921331755217720249285531645015085938097863934564743025817
Short name T810
Test name
Test status
Simulation time 13059183 ps
CPU time 0.87 seconds
Started Nov 22 01:31:36 PM PST 23
Finished Nov 22 01:31:39 PM PST 23
Peak memory 205284 kb
Host smart-3774b6bd-5bd4-430c-a759-cc083128c4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30806522326951515271921331755217720249285531645015085938097863934564743025817 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.edn_smoke.30806522326951515271921331755217720249285531645015085938097863934564743025817
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.48426380228383933031269694329155435858847496655469283114358529858513016246336
Short name T264
Test name
Test status
Simulation time 154489183 ps
CPU time 3.91 seconds
Started Nov 22 01:31:36 PM PST 23
Finished Nov 22 01:31:42 PM PST 23
Peak memory 206368 kb
Host smart-4c214dd1-7996-48ff-89d5-c7c2afbbdc96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48426380228383933031269694329155435858847496655469283114358529858513016246336 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.48426380228383933031269694329155435858847496655469283114358529858513016246336
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.98324746438554368317549920841193354729068166071901019240150171439917560293321
Short name T868
Test name
Test status
Simulation time 41708099183 ps
CPU time 1042.78 seconds
Started Nov 22 01:31:38 PM PST 23
Finished Nov 22 01:49:02 PM PST 23
Peak memory 215792 kb
Host smart-e171b34c-fe41-4cef-8592-9648bd4e8fd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983247464385543683175499208
41193354729068166071901019240150171439917560293321 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.983247464385
54368317549920841193354729068166071901019240150171439917560293321
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.70193735360963289608566857854535541054793926395038207493314476711785065397066
Short name T614
Test name
Test status
Simulation time 18259183 ps
CPU time 1.01 seconds
Started Nov 22 01:34:16 PM PST 23
Finished Nov 22 01:34:18 PM PST 23
Peak memory 205564 kb
Host smart-57dc1f27-d851-4ce4-8a8d-133c9d433ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70193735360963289608566857854535541054793926395038207493314476711785065397066 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 20.edn_alert.70193735360963289608566857854535541054793926395038207493314476711785065397066
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.29765001390894482635568885686969669463433879670640488991286094280418593592999
Short name T787
Test name
Test status
Simulation time 28184990 ps
CPU time 0.84 seconds
Started Nov 22 01:34:09 PM PST 23
Finished Nov 22 01:34:11 PM PST 23
Peak memory 205396 kb
Host smart-444e1c72-77e0-41cc-b507-e6cb8c02324a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29765001390894482635568885686969669463433879670640488991286094280418593592999 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.edn_alert_test.29765001390894482635568885686969669463433879670640488991286094280418593592999
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.110229204771636384584931512508044153252692742830139663800794561735563575602572
Short name T852
Test name
Test status
Simulation time 12219183 ps
CPU time 0.84 seconds
Started Nov 22 01:34:14 PM PST 23
Finished Nov 22 01:34:16 PM PST 23
Peak memory 214876 kb
Host smart-f87c3b98-2fd5-4fba-a088-40df00e12135
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110229204771636384584931512508044153252692742830139663800794561735563575602572 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 20.edn_disable.110229204771636384584931512508044153252692742830139663800794561735563575602572
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.53548293855755620216815445970367699148166944308565959604996784222548434500606
Short name T550
Test name
Test status
Simulation time 14969183 ps
CPU time 0.91 seconds
Started Nov 22 01:34:13 PM PST 23
Finished Nov 22 01:34:15 PM PST 23
Peak memory 214828 kb
Host smart-bede8834-237e-4f0d-9f74-46485cb22a73
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53548293855755620216815445970367699148166944308565959604996784222548434500606 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable_auto_req_mode.5354829385575562021681544597036769914816694430856595960499
6784222548434500606
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_genbits.23290628976100053084941055401112878623249696303066852228848883724817882423932
Short name T486
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 22 01:34:11 PM PST 23
Finished Nov 22 01:34:13 PM PST 23
Peak memory 205844 kb
Host smart-e4f48cc9-3d28-4b72-b9e5-17e401790ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23290628976100053084941055401112878623249696303066852228848883724817882423932 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.edn_genbits.23290628976100053084941055401112878623249696303066852228848883724817882423932
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.20908619179468760048306464261459298922460727608973866985831628160785293305919
Short name T631
Test name
Test status
Simulation time 18439183 ps
CPU time 1.11 seconds
Started Nov 22 01:34:13 PM PST 23
Finished Nov 22 01:34:15 PM PST 23
Peak memory 222176 kb
Host smart-bd17dd4d-b373-4b8b-88f1-b08dbf129e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20908619179468760048306464261459298922460727608973866985831628160785293305919 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.edn_intr.20908619179468760048306464261459298922460727608973866985831628160785293305919
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.28111215948285885224260829469314156479546422172443388647235130788989698972811
Short name T661
Test name
Test status
Simulation time 13059183 ps
CPU time 0.88 seconds
Started Nov 22 01:34:18 PM PST 23
Finished Nov 22 01:34:20 PM PST 23
Peak memory 205332 kb
Host smart-29c9dbd6-5c0a-4a0c-8ad9-c1d7e19c9f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28111215948285885224260829469314156479546422172443388647235130788989698972811 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 20.edn_smoke.28111215948285885224260829469314156479546422172443388647235130788989698972811
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.25485165837434461908365818548829218014536048380006243193809999170036535487607
Short name T98
Test name
Test status
Simulation time 154489183 ps
CPU time 3.93 seconds
Started Nov 22 01:34:18 PM PST 23
Finished Nov 22 01:34:23 PM PST 23
Peak memory 206276 kb
Host smart-9502398f-bdf4-437c-90b1-2fa6ab12adf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25485165837434461908365818548829218014536048380006243193809999170036535487607 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.25485165837434461908365818548829218014536048380006243193809999170036535487607
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.89707107144812968360169533081450655611157900603803747023204363460096326202634
Short name T277
Test name
Test status
Simulation time 41708099183 ps
CPU time 1077.8 seconds
Started Nov 22 01:34:16 PM PST 23
Finished Nov 22 01:52:15 PM PST 23
Peak memory 215840 kb
Host smart-0b455180-4dc2-4074-8ad3-3eac4709fae2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897071071448129683601695330
81450655611157900603803747023204363460096326202634 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.89707107144
812968360169533081450655611157900603803747023204363460096326202634
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.77815729411910013845364634021779104016451969292166125804306999947775712562350
Short name T828
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 22 01:36:46 PM PST 23
Finished Nov 22 01:36:48 PM PST 23
Peak memory 205744 kb
Host smart-0ece1109-7006-4bc1-bb6f-ee5507452738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77815729411910013845364634021779104016451969292166125804306999947775712562350 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 200.edn_genbits.77815729411910013845364634021779104016451969292166125804306999947775712562350
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.15527575551300465583792363772645994780380003047940813648013683076198994489450
Short name T343
Test name
Test status
Simulation time 17999183 ps
CPU time 1.21 seconds
Started Nov 22 01:36:36 PM PST 23
Finished Nov 22 01:36:40 PM PST 23
Peak memory 205764 kb
Host smart-89ecf7f3-5bfc-4ce4-bf5d-2cce971a4541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15527575551300465583792363772645994780380003047940813648013683076198994489450 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 201.edn_genbits.15527575551300465583792363772645994780380003047940813648013683076198994489450
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.8222147483033654282640891161201620538414926337998142688217283040039042830860
Short name T522
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 22 01:36:33 PM PST 23
Finished Nov 22 01:36:35 PM PST 23
Peak memory 205852 kb
Host smart-c3d2a7e3-73b1-45ab-9a39-afee87f2dddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8222147483033654282640891161201620538414926337998142688217283040039042830860 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 202.edn_genbits.8222147483033654282640891161201620538414926337998142688217283040039042830860
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.113012976995272309451448995157578615668992621675793598496161803137387922804322
Short name T358
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 22 01:36:48 PM PST 23
Finished Nov 22 01:36:50 PM PST 23
Peak memory 205796 kb
Host smart-46da7f25-2c18-4eab-bab1-778144556ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113012976995272309451448995157578615668992621675793598496161803137387922804322 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 203.edn_genbits.113012976995272309451448995157578615668992621675793598496161803137387922804322
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.11946601096163645067872607338251492039831108109144825407194969691214830204640
Short name T827
Test name
Test status
Simulation time 17999183 ps
CPU time 1.06 seconds
Started Nov 22 01:36:27 PM PST 23
Finished Nov 22 01:36:28 PM PST 23
Peak memory 205824 kb
Host smart-d7c71e3a-d400-4730-b4eb-c007dda19136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11946601096163645067872607338251492039831108109144825407194969691214830204640 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 204.edn_genbits.11946601096163645067872607338251492039831108109144825407194969691214830204640
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.64965773029455713279265876728006606694201278090053756473608958030515918671949
Short name T359
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Nov 22 01:36:46 PM PST 23
Finished Nov 22 01:36:48 PM PST 23
Peak memory 205812 kb
Host smart-1e042fcb-ffb5-4716-890a-bd59aba4fe74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64965773029455713279265876728006606694201278090053756473608958030515918671949 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 205.edn_genbits.64965773029455713279265876728006606694201278090053756473608958030515918671949
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.106703291856161078750673418972814538554222076943425676255022634629918004995139
Short name T889
Test name
Test status
Simulation time 17999183 ps
CPU time 1.17 seconds
Started Nov 22 01:36:27 PM PST 23
Finished Nov 22 01:36:29 PM PST 23
Peak memory 205840 kb
Host smart-4822022b-d85b-4c11-9a8e-38559c6ab397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106703291856161078750673418972814538554222076943425676255022634629918004995139 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 206.edn_genbits.106703291856161078750673418972814538554222076943425676255022634629918004995139
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.35164965076780847210610286553757493939450586292403545840656060854507656092870
Short name T507
Test name
Test status
Simulation time 17999183 ps
CPU time 1.18 seconds
Started Nov 22 01:36:36 PM PST 23
Finished Nov 22 01:36:40 PM PST 23
Peak memory 205840 kb
Host smart-c1846a86-c7ef-4c5e-b019-9a2a6e28c62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35164965076780847210610286553757493939450586292403545840656060854507656092870 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 207.edn_genbits.35164965076780847210610286553757493939450586292403545840656060854507656092870
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.50773652125500301533411394933227669184775487958918746222099482615776173643249
Short name T805
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 22 01:36:35 PM PST 23
Finished Nov 22 01:36:37 PM PST 23
Peak memory 205848 kb
Host smart-ec6eb57d-a2ef-496b-9bef-8c02da51c7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50773652125500301533411394933227669184775487958918746222099482615776173643249 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 208.edn_genbits.50773652125500301533411394933227669184775487958918746222099482615776173643249
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.67922918208464021173288062615360917740436250264558530596710609600547995282878
Short name T40
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 22 01:36:49 PM PST 23
Finished Nov 22 01:36:52 PM PST 23
Peak memory 205792 kb
Host smart-add31953-fcf9-4a9b-be31-02b611d1bc18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67922918208464021173288062615360917740436250264558530596710609600547995282878 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 209.edn_genbits.67922918208464021173288062615360917740436250264558530596710609600547995282878
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.52457662944053083691507884007457206403052308648037719175392837917605168515292
Short name T929
Test name
Test status
Simulation time 18259183 ps
CPU time 1 seconds
Started Nov 22 01:34:15 PM PST 23
Finished Nov 22 01:34:18 PM PST 23
Peak memory 205572 kb
Host smart-36d7a6b5-8173-4d5c-98b9-5af1e7bc72e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52457662944053083691507884007457206403052308648037719175392837917605168515292 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 21.edn_alert.52457662944053083691507884007457206403052308648037719175392837917605168515292
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.8715790111540699144882205617318061076766698498374676960166518761698064013683
Short name T692
Test name
Test status
Simulation time 28184990 ps
CPU time 0.85 seconds
Started Nov 22 01:34:14 PM PST 23
Finished Nov 22 01:34:16 PM PST 23
Peak memory 205520 kb
Host smart-1ac61032-c573-429e-ad76-d0a3f1c03acc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8715790111540699144882205617318061076766698498374676960166518761698064013683 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.edn_alert_test.8715790111540699144882205617318061076766698498374676960166518761698064013683
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.55659937958801224555713975716071173830291499051937755866023571848753303011891
Short name T671
Test name
Test status
Simulation time 12219183 ps
CPU time 0.88 seconds
Started Nov 22 01:34:15 PM PST 23
Finished Nov 22 01:34:17 PM PST 23
Peak memory 214892 kb
Host smart-09afea14-7059-448a-93a3-34df48e86fea
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55659937958801224555713975716071173830291499051937755866023571848753303011891 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.edn_disable.55659937958801224555713975716071173830291499051937755866023571848753303011891
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.97623096574920342357588222751034778902741978540795866107191180489320776698485
Short name T446
Test name
Test status
Simulation time 14969183 ps
CPU time 0.86 seconds
Started Nov 22 01:34:12 PM PST 23
Finished Nov 22 01:34:14 PM PST 23
Peak memory 214824 kb
Host smart-9fc33f06-4907-40cb-b494-adc78a3b6aae
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97623096574920342357588222751034778902741978540795866107191180489320776698485 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable_auto_req_mode.9762309657492034235758822275103477890274197854079586610719
1180489320776698485
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.43512722820541759170692692922121440988435359747700159967754629976080117231728
Short name T742
Test name
Test status
Simulation time 24963823 ps
CPU time 1.17 seconds
Started Nov 22 01:34:14 PM PST 23
Finished Nov 22 01:34:16 PM PST 23
Peak memory 230364 kb
Host smart-3f728fb4-02e9-4808-81ab-25d4afb5fcb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43512722820541759170692692922121440988435359747700159967754629976080117231728 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.edn_err.43512722820541759170692692922121440988435359747700159967754629976080117231728
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.59793000493569834585574193630978579451720232022044465492423259470187295728973
Short name T473
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 22 01:34:14 PM PST 23
Finished Nov 22 01:34:17 PM PST 23
Peak memory 205840 kb
Host smart-37c17533-6243-469e-80bd-d7b703a31387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59793000493569834585574193630978579451720232022044465492423259470187295728973 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.edn_genbits.59793000493569834585574193630978579451720232022044465492423259470187295728973
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.97313775643051656385184017478296662290827225447696398678459649933374849569146
Short name T321
Test name
Test status
Simulation time 18439183 ps
CPU time 1.12 seconds
Started Nov 22 01:34:18 PM PST 23
Finished Nov 22 01:34:20 PM PST 23
Peak memory 222272 kb
Host smart-bf5fc508-9d65-42aa-9d8d-c587803eed46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97313775643051656385184017478296662290827225447696398678459649933374849569146 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.edn_intr.97313775643051656385184017478296662290827225447696398678459649933374849569146
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.104441114547825740427329234953791825540916568668718522485875060365246795428311
Short name T334
Test name
Test status
Simulation time 13059183 ps
CPU time 0.87 seconds
Started Nov 22 01:34:15 PM PST 23
Finished Nov 22 01:34:17 PM PST 23
Peak memory 205328 kb
Host smart-62fcd5d2-8ede-4c7b-9df9-7f58d2d4ffd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104441114547825740427329234953791825540916568668718522485875060365246795428311 -assert nopostproc +UVM_TESTNAME=edn_smok
e_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 21.edn_smoke.104441114547825740427329234953791825540916568668718522485875060365246795428311
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.41657458560301608527178264771603263213110851411884907574687776043956122008298
Short name T443
Test name
Test status
Simulation time 154489183 ps
CPU time 4.16 seconds
Started Nov 22 01:34:14 PM PST 23
Finished Nov 22 01:34:20 PM PST 23
Peak memory 206372 kb
Host smart-7b907670-1763-43f7-add5-9a242d20c541
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41657458560301608527178264771603263213110851411884907574687776043956122008298 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.41657458560301608527178264771603263213110851411884907574687776043956122008298
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.62007007299933434967733019007859870835639698174981596745194793203778841003216
Short name T797
Test name
Test status
Simulation time 41708099183 ps
CPU time 1082.95 seconds
Started Nov 22 01:34:15 PM PST 23
Finished Nov 22 01:52:19 PM PST 23
Peak memory 215880 kb
Host smart-9614b4f9-0bdd-4386-a699-20af881a2f1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620070072999334349677330190
07859870835639698174981596745194793203778841003216 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.62007007299
933434967733019007859870835639698174981596745194793203778841003216
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.31740293527254020602694184868342842912791667494032402774766735778381713279082
Short name T516
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:36:33 PM PST 23
Finished Nov 22 01:36:34 PM PST 23
Peak memory 205744 kb
Host smart-7b023004-3f04-4fb6-8fb3-36ce941d465f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31740293527254020602694184868342842912791667494032402774766735778381713279082 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 210.edn_genbits.31740293527254020602694184868342842912791667494032402774766735778381713279082
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.69511472987921842745053830231051985291977098631491903492016414132857956133914
Short name T973
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 22 01:36:36 PM PST 23
Finished Nov 22 01:36:39 PM PST 23
Peak memory 205840 kb
Host smart-e4c554ab-f57e-4d29-af7d-8c5d5d690903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69511472987921842745053830231051985291977098631491903492016414132857956133914 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 211.edn_genbits.69511472987921842745053830231051985291977098631491903492016414132857956133914
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.55766331778926491062828940297211699668114775677889551940097331743252586988127
Short name T557
Test name
Test status
Simulation time 17999183 ps
CPU time 1.15 seconds
Started Nov 22 01:36:48 PM PST 23
Finished Nov 22 01:36:51 PM PST 23
Peak memory 205792 kb
Host smart-73aef7fc-1333-46fc-baa2-8a31ff770e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55766331778926491062828940297211699668114775677889551940097331743252586988127 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 212.edn_genbits.55766331778926491062828940297211699668114775677889551940097331743252586988127
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.62461294085291289055134850278193125424848349748340066916846736446524416940514
Short name T878
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 22 01:36:36 PM PST 23
Finished Nov 22 01:36:40 PM PST 23
Peak memory 205832 kb
Host smart-5d2a4d31-127b-47b6-9082-4e8754d4d55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62461294085291289055134850278193125424848349748340066916846736446524416940514 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 213.edn_genbits.62461294085291289055134850278193125424848349748340066916846736446524416940514
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.27231421162458153378228738042494938455158828993854301998375074064682520739129
Short name T952
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Nov 22 01:36:35 PM PST 23
Finished Nov 22 01:36:38 PM PST 23
Peak memory 205820 kb
Host smart-7abd9b20-5013-4bdf-8c51-8c1604b3fbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27231421162458153378228738042494938455158828993854301998375074064682520739129 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 214.edn_genbits.27231421162458153378228738042494938455158828993854301998375074064682520739129
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.52674404648171502827636726708429598325202085586969117512812987006445673120408
Short name T411
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 22 01:36:28 PM PST 23
Finished Nov 22 01:36:30 PM PST 23
Peak memory 205880 kb
Host smart-b885cf67-68f1-4e5b-a4a0-cc58eb31a164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52674404648171502827636726708429598325202085586969117512812987006445673120408 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 215.edn_genbits.52674404648171502827636726708429598325202085586969117512812987006445673120408
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.59994406047780671572954295911032413496517596462402974238955257099310168031871
Short name T863
Test name
Test status
Simulation time 17999183 ps
CPU time 1.17 seconds
Started Nov 22 01:36:36 PM PST 23
Finished Nov 22 01:36:40 PM PST 23
Peak memory 205816 kb
Host smart-afd63540-964e-4b84-a4e6-c31767d79eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59994406047780671572954295911032413496517596462402974238955257099310168031871 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 216.edn_genbits.59994406047780671572954295911032413496517596462402974238955257099310168031871
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.90799745890824915747611267580571681601114040720223426410700566826528535089648
Short name T660
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:36:35 PM PST 23
Finished Nov 22 01:36:37 PM PST 23
Peak memory 205824 kb
Host smart-b807afb5-99f9-44df-80cb-7e458714b9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90799745890824915747611267580571681601114040720223426410700566826528535089648 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 217.edn_genbits.90799745890824915747611267580571681601114040720223426410700566826528535089648
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.102485062662929684822545731841582925291173639977493978312366914440671924187027
Short name T433
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:36:52 PM PST 23
Finished Nov 22 01:36:58 PM PST 23
Peak memory 205924 kb
Host smart-96ebf681-ca46-4def-abf5-1d387fee83a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102485062662929684822545731841582925291173639977493978312366914440671924187027 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 218.edn_genbits.102485062662929684822545731841582925291173639977493978312366914440671924187027
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.2316661210695791618287714415911300760254088983520590241576689187585549044728
Short name T492
Test name
Test status
Simulation time 17999183 ps
CPU time 1.16 seconds
Started Nov 22 01:36:46 PM PST 23
Finished Nov 22 01:36:49 PM PST 23
Peak memory 205792 kb
Host smart-541e8acd-0cc7-4959-83d5-1089f7b9d1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316661210695791618287714415911300760254088983520590241576689187585549044728 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 219.edn_genbits.2316661210695791618287714415911300760254088983520590241576689187585549044728
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.81022832793568231841244635659288681621653879943519730688193750329886561020781
Short name T780
Test name
Test status
Simulation time 18259183 ps
CPU time 0.97 seconds
Started Nov 22 01:34:25 PM PST 23
Finished Nov 22 01:34:27 PM PST 23
Peak memory 205492 kb
Host smart-c45af704-a512-49b4-8f43-06f51aef27af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81022832793568231841244635659288681621653879943519730688193750329886561020781 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 22.edn_alert.81022832793568231841244635659288681621653879943519730688193750329886561020781
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.75965941748514645039017999713837820184853904349954010013285527559239066225495
Short name T917
Test name
Test status
Simulation time 28184990 ps
CPU time 0.9 seconds
Started Nov 22 01:34:18 PM PST 23
Finished Nov 22 01:34:20 PM PST 23
Peak memory 205500 kb
Host smart-eb09bcff-0dbf-40cd-8bd1-78da4e7766a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75965941748514645039017999713837820184853904349954010013285527559239066225495 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.edn_alert_test.75965941748514645039017999713837820184853904349954010013285527559239066225495
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.99194814995954416479793404347736310062740421590010172419976439782386865365266
Short name T322
Test name
Test status
Simulation time 12219183 ps
CPU time 0.85 seconds
Started Nov 22 01:34:18 PM PST 23
Finished Nov 22 01:34:20 PM PST 23
Peak memory 214852 kb
Host smart-44656123-de2a-477f-a488-eb6fd618d758
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99194814995954416479793404347736310062740421590010172419976439782386865365266 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.edn_disable.99194814995954416479793404347736310062740421590010172419976439782386865365266
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.94221408837796726251707714219492030329025615063071777072601788945973161962257
Short name T901
Test name
Test status
Simulation time 14969183 ps
CPU time 0.94 seconds
Started Nov 22 01:34:15 PM PST 23
Finished Nov 22 01:34:18 PM PST 23
Peak memory 214816 kb
Host smart-a357796f-8651-4546-82c7-806cd36a969c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94221408837796726251707714219492030329025615063071777072601788945973161962257 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable_auto_req_mode.9422140883779672625170771421949203032902561506307177707260
1788945973161962257
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.98315542110596386087843952388288622829267864257416431789151594967956330204763
Short name T942
Test name
Test status
Simulation time 24963823 ps
CPU time 1.17 seconds
Started Nov 22 01:34:27 PM PST 23
Finished Nov 22 01:34:28 PM PST 23
Peak memory 230520 kb
Host smart-4880d6ea-023d-4fd0-b765-019c6e70037a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98315542110596386087843952388288622829267864257416431789151594967956330204763 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.edn_err.98315542110596386087843952388288622829267864257416431789151594967956330204763
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.92374053296963926692235331489649764151102187481042411976914025864154369009038
Short name T745
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 22 01:34:32 PM PST 23
Finished Nov 22 01:34:34 PM PST 23
Peak memory 205816 kb
Host smart-26719281-b3eb-42e2-ae39-4deb09578056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92374053296963926692235331489649764151102187481042411976914025864154369009038 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.edn_genbits.92374053296963926692235331489649764151102187481042411976914025864154369009038
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.44572428464923685902800195308202333682128607900484608905473901763615413569782
Short name T247
Test name
Test status
Simulation time 18439183 ps
CPU time 1.16 seconds
Started Nov 22 01:34:28 PM PST 23
Finished Nov 22 01:34:30 PM PST 23
Peak memory 222232 kb
Host smart-d01c7afc-d538-4c8b-bf79-00ed707f8d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44572428464923685902800195308202333682128607900484608905473901763615413569782 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.edn_intr.44572428464923685902800195308202333682128607900484608905473901763615413569782
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.30236538130794926496848840094677710205271504120354759920088684919320650803397
Short name T713
Test name
Test status
Simulation time 13059183 ps
CPU time 0.87 seconds
Started Nov 22 01:34:14 PM PST 23
Finished Nov 22 01:34:16 PM PST 23
Peak memory 205324 kb
Host smart-00d3b305-e698-4c40-87c1-00b2ef01d0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30236538130794926496848840094677710205271504120354759920088684919320650803397 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 22.edn_smoke.30236538130794926496848840094677710205271504120354759920088684919320650803397
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.83664474840638605243779712003807858398087210101964126333073313256974380843467
Short name T340
Test name
Test status
Simulation time 154489183 ps
CPU time 3.96 seconds
Started Nov 22 01:34:28 PM PST 23
Finished Nov 22 01:34:33 PM PST 23
Peak memory 206328 kb
Host smart-2f1a1b5a-a481-480e-8bb6-ffc9af3ab74a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83664474840638605243779712003807858398087210101964126333073313256974380843467 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.83664474840638605243779712003807858398087210101964126333073313256974380843467
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.1924260559778382192317533865925149433451903306766842740076866082115681601364
Short name T304
Test name
Test status
Simulation time 41708099183 ps
CPU time 1062.12 seconds
Started Nov 22 01:34:18 PM PST 23
Finished Nov 22 01:52:01 PM PST 23
Peak memory 215772 kb
Host smart-755574db-c415-414f-a4b6-f568f504ccb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192426055977838219231753386
5925149433451903306766842740076866082115681601364 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.192426055977
8382192317533865925149433451903306766842740076866082115681601364
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.59637465250126957916280114741488532637139256747164763467615996525420125226211
Short name T476
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:36:50 PM PST 23
Finished Nov 22 01:36:54 PM PST 23
Peak memory 205848 kb
Host smart-138dd88c-b527-4abf-9477-111e324355a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59637465250126957916280114741488532637139256747164763467615996525420125226211 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 220.edn_genbits.59637465250126957916280114741488532637139256747164763467615996525420125226211
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.58177281596871522023875796577137884101586829815191925347892079684949045162248
Short name T316
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:36:44 PM PST 23
Finished Nov 22 01:36:46 PM PST 23
Peak memory 205844 kb
Host smart-985c61df-8a95-46b2-a80b-f758c7e925b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58177281596871522023875796577137884101586829815191925347892079684949045162248 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 221.edn_genbits.58177281596871522023875796577137884101586829815191925347892079684949045162248
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.66281273224977961515105586593521103077929254154505148715120458081864404288528
Short name T463
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 22 01:36:49 PM PST 23
Finished Nov 22 01:36:52 PM PST 23
Peak memory 205824 kb
Host smart-3b4c837d-0684-4339-8a07-a8f62628c5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66281273224977961515105586593521103077929254154505148715120458081864404288528 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 222.edn_genbits.66281273224977961515105586593521103077929254154505148715120458081864404288528
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.47664247770344239631706887126887442163113670183431155790113744967505478709057
Short name T971
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:36:47 PM PST 23
Finished Nov 22 01:36:50 PM PST 23
Peak memory 205844 kb
Host smart-8a3b5b94-697e-4632-a0e5-129f56a8e004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47664247770344239631706887126887442163113670183431155790113744967505478709057 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 223.edn_genbits.47664247770344239631706887126887442163113670183431155790113744967505478709057
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.53370402844401302815251283033350662407182357632286787045064605311033530931292
Short name T850
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 22 01:36:48 PM PST 23
Finished Nov 22 01:36:51 PM PST 23
Peak memory 205824 kb
Host smart-22ecf6f7-f88c-431f-8923-9e7f510080a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53370402844401302815251283033350662407182357632286787045064605311033530931292 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 224.edn_genbits.53370402844401302815251283033350662407182357632286787045064605311033530931292
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.45021069549562289217367178456797842466341478562918446293123826007705305145380
Short name T653
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 22 01:36:44 PM PST 23
Finished Nov 22 01:36:45 PM PST 23
Peak memory 205856 kb
Host smart-b7f0fdaf-4dfc-43dd-b10c-940f30ffb792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45021069549562289217367178456797842466341478562918446293123826007705305145380 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 225.edn_genbits.45021069549562289217367178456797842466341478562918446293123826007705305145380
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.40084528049707447663307504896926213970794604069868626460326756319492620873138
Short name T577
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 22 01:36:49 PM PST 23
Finished Nov 22 01:36:53 PM PST 23
Peak memory 205816 kb
Host smart-9bbefa44-502f-4dd9-ae6e-1e1688b7abc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40084528049707447663307504896926213970794604069868626460326756319492620873138 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 226.edn_genbits.40084528049707447663307504896926213970794604069868626460326756319492620873138
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.10872996235627515836276290439605643078892520294889560402479051568769753991156
Short name T915
Test name
Test status
Simulation time 17999183 ps
CPU time 1.15 seconds
Started Nov 22 01:36:46 PM PST 23
Finished Nov 22 01:36:49 PM PST 23
Peak memory 205820 kb
Host smart-e4ab3519-f3d8-419c-b45a-e125cfc4110a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10872996235627515836276290439605643078892520294889560402479051568769753991156 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 227.edn_genbits.10872996235627515836276290439605643078892520294889560402479051568769753991156
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.18232684593064387524713736735048790567913719716265962413911365882364804737508
Short name T461
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 22 01:36:49 PM PST 23
Finished Nov 22 01:36:52 PM PST 23
Peak memory 205836 kb
Host smart-ebacb636-e6ab-4afb-9284-f19c2bdca3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18232684593064387524713736735048790567913719716265962413911365882364804737508 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 228.edn_genbits.18232684593064387524713736735048790567913719716265962413911365882364804737508
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.50653193249044187684727190766092121689899619056559193430369291080693003594493
Short name T317
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 22 01:36:53 PM PST 23
Finished Nov 22 01:36:59 PM PST 23
Peak memory 205844 kb
Host smart-20a03107-b6ab-4432-957d-5a0ea2c4a672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50653193249044187684727190766092121689899619056559193430369291080693003594493 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 229.edn_genbits.50653193249044187684727190766092121689899619056559193430369291080693003594493
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.10180410068324067105909404582118581375413262230603941521033616851293445275888
Short name T566
Test name
Test status
Simulation time 18259183 ps
CPU time 0.97 seconds
Started Nov 22 01:34:18 PM PST 23
Finished Nov 22 01:34:21 PM PST 23
Peak memory 205592 kb
Host smart-0d227b2e-08f9-4d10-8e69-2c0e54eb8658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10180410068324067105909404582118581375413262230603941521033616851293445275888 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 23.edn_alert.10180410068324067105909404582118581375413262230603941521033616851293445275888
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.90658945886108583709380488086120775955415444855384421268238303454475694481199
Short name T755
Test name
Test status
Simulation time 28184990 ps
CPU time 0.89 seconds
Started Nov 22 01:34:19 PM PST 23
Finished Nov 22 01:34:21 PM PST 23
Peak memory 205512 kb
Host smart-bc742039-e7b9-4a82-b822-5addd11995bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90658945886108583709380488086120775955415444855384421268238303454475694481199 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.edn_alert_test.90658945886108583709380488086120775955415444855384421268238303454475694481199
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.79580740535646446179388745213101008248824625377574045846419180001544035468315
Short name T672
Test name
Test status
Simulation time 12219183 ps
CPU time 0.88 seconds
Started Nov 22 01:34:15 PM PST 23
Finished Nov 22 01:34:17 PM PST 23
Peak memory 214864 kb
Host smart-5f28716c-1578-4de5-91d2-18bde0d869db
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79580740535646446179388745213101008248824625377574045846419180001544035468315 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.edn_disable.79580740535646446179388745213101008248824625377574045846419180001544035468315
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.92655281293720738191536109180443132459831229937925865124845151098621494961346
Short name T249
Test name
Test status
Simulation time 14969183 ps
CPU time 0.92 seconds
Started Nov 22 01:34:27 PM PST 23
Finished Nov 22 01:34:29 PM PST 23
Peak memory 214888 kb
Host smart-17d9a078-8ccc-4498-88a7-c68438f593b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92655281293720738191536109180443132459831229937925865124845151098621494961346 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable_auto_req_mode.9265528129372073819153610918044313245983122993792586512484
5151098621494961346
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.6021215570633951246897447911014391557485210916192579210813870621988940219139
Short name T397
Test name
Test status
Simulation time 24963823 ps
CPU time 1.15 seconds
Started Nov 22 01:34:39 PM PST 23
Finished Nov 22 01:34:41 PM PST 23
Peak memory 230456 kb
Host smart-cfa67ec3-1c07-435f-a18d-31699d02a441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6021215570633951246897447911014391557485210916192579210813870621988940219139 -assert nopostproc +UVM_TESTNAME=edn_err_te
st +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
edn_err.6021215570633951246897447911014391557485210916192579210813870621988940219139
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.114408126380246657078474090256901283854968045715065592737474464831213217315340
Short name T601
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 22 01:34:14 PM PST 23
Finished Nov 22 01:34:17 PM PST 23
Peak memory 205856 kb
Host smart-859ec8b9-e89d-451c-9cd4-6284773572a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114408126380246657078474090256901283854968045715065592737474464831213217315340 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 23.edn_genbits.114408126380246657078474090256901283854968045715065592737474464831213217315340
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.18475780541545835896728834273073187500893550817909303196310671779415244516852
Short name T470
Test name
Test status
Simulation time 18439183 ps
CPU time 1.17 seconds
Started Nov 22 01:34:15 PM PST 23
Finished Nov 22 01:34:17 PM PST 23
Peak memory 222216 kb
Host smart-34749bfe-33a2-42ed-9c65-f6da6196c1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18475780541545835896728834273073187500893550817909303196310671779415244516852 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.edn_intr.18475780541545835896728834273073187500893550817909303196310671779415244516852
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.91531834629163802396751969641145943803742472195074865680352250055349071324790
Short name T795
Test name
Test status
Simulation time 13059183 ps
CPU time 0.86 seconds
Started Nov 22 01:34:14 PM PST 23
Finished Nov 22 01:34:16 PM PST 23
Peak memory 205364 kb
Host smart-944f6045-ed85-45e7-bd14-f8b310bdbf88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91531834629163802396751969641145943803742472195074865680352250055349071324790 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 23.edn_smoke.91531834629163802396751969641145943803742472195074865680352250055349071324790
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.100180371394537871178472600619431896257067360900024309590813586329289140708792
Short name T239
Test name
Test status
Simulation time 154489183 ps
CPU time 3.83 seconds
Started Nov 22 01:34:17 PM PST 23
Finished Nov 22 01:34:22 PM PST 23
Peak memory 206252 kb
Host smart-264f727f-ed73-4028-85f8-e40493318ec2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100180371394537871178472600619431896257067360900024309590813586329289140708792 -assert nopo
stproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.100180371394537871178472600619431896257067360900024309590813586329289140708792
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.31267620858682693300383849576054693134069518586295220897123741370321721827832
Short name T975
Test name
Test status
Simulation time 41708099183 ps
CPU time 1048.04 seconds
Started Nov 22 01:34:13 PM PST 23
Finished Nov 22 01:51:42 PM PST 23
Peak memory 215828 kb
Host smart-ed2fd02e-3ffa-4b94-8952-141ff2fd9593
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312676208586826933003838495
76054693134069518586295220897123741370321721827832 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.31267620858
682693300383849576054693134069518586295220897123741370321721827832
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.74855422654398640817323222823337447976065660677805502408431889470460868777755
Short name T329
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 22 01:36:50 PM PST 23
Finished Nov 22 01:36:54 PM PST 23
Peak memory 205768 kb
Host smart-9aeebf4c-1a45-435f-b528-9c594e13da32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74855422654398640817323222823337447976065660677805502408431889470460868777755 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 230.edn_genbits.74855422654398640817323222823337447976065660677805502408431889470460868777755
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.79543776391735559620234738390012408237542690931297851255574309763890336623238
Short name T833
Test name
Test status
Simulation time 17999183 ps
CPU time 1.06 seconds
Started Nov 22 01:36:50 PM PST 23
Finished Nov 22 01:36:54 PM PST 23
Peak memory 205748 kb
Host smart-1e4af2d0-514c-4e45-9b23-c0d4cd1b1651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79543776391735559620234738390012408237542690931297851255574309763890336623238 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 231.edn_genbits.79543776391735559620234738390012408237542690931297851255574309763890336623238
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.32237058545351067561043761465745347308317006148438233009640413836770651763573
Short name T726
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 22 01:36:56 PM PST 23
Finished Nov 22 01:37:02 PM PST 23
Peak memory 205876 kb
Host smart-de7ff19d-1ad2-4ce9-8dee-79c49124b3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32237058545351067561043761465745347308317006148438233009640413836770651763573 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 232.edn_genbits.32237058545351067561043761465745347308317006148438233009640413836770651763573
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.94987723817768787399190427803548356026650381496390521838036134532769588232574
Short name T62
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 22 01:36:52 PM PST 23
Finished Nov 22 01:36:58 PM PST 23
Peak memory 205920 kb
Host smart-cc1d7532-4dea-4fae-842b-ac3747672746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94987723817768787399190427803548356026650381496390521838036134532769588232574 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 233.edn_genbits.94987723817768787399190427803548356026650381496390521838036134532769588232574
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.18756714713987660916075984322349767871582824423025817330521638888647538891702
Short name T705
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 22 01:36:53 PM PST 23
Finished Nov 22 01:36:59 PM PST 23
Peak memory 205888 kb
Host smart-78c34ec6-28d0-4720-bd18-4c48c50df92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18756714713987660916075984322349767871582824423025817330521638888647538891702 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 234.edn_genbits.18756714713987660916075984322349767871582824423025817330521638888647538891702
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.76815618521634116006291706725854169920481066313691407412830334779086891944200
Short name T493
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 22 01:36:50 PM PST 23
Finished Nov 22 01:36:54 PM PST 23
Peak memory 205748 kb
Host smart-1479015d-9acf-4ad0-b428-e10483d9a1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76815618521634116006291706725854169920481066313691407412830334779086891944200 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 235.edn_genbits.76815618521634116006291706725854169920481066313691407412830334779086891944200
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.466212511552037524140093571164178476733892038901365048982521038543839329432
Short name T721
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:36:52 PM PST 23
Finished Nov 22 01:36:58 PM PST 23
Peak memory 205728 kb
Host smart-83159058-c606-4960-9ffd-ffa32996ed85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466212511552037524140093571164178476733892038901365048982521038543839329432 -assert nopostproc +UVM_TESTNAME=edn_genbits
_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 236.edn_genbits.466212511552037524140093571164178476733892038901365048982521038543839329432
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.34289498822883616893249786451839820086394652585308911823552060441911536710289
Short name T764
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 22 01:36:56 PM PST 23
Finished Nov 22 01:37:02 PM PST 23
Peak memory 205608 kb
Host smart-0f14ef8f-0b65-43b2-a792-b2ed783152b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34289498822883616893249786451839820086394652585308911823552060441911536710289 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 237.edn_genbits.34289498822883616893249786451839820086394652585308911823552060441911536710289
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.67057487072114450754828088462842356467384663469267789769937356960760522105306
Short name T244
Test name
Test status
Simulation time 17999183 ps
CPU time 1.19 seconds
Started Nov 22 01:36:52 PM PST 23
Finished Nov 22 01:36:58 PM PST 23
Peak memory 205764 kb
Host smart-bfaf8019-2398-45ff-b442-8428a6a97eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67057487072114450754828088462842356467384663469267789769937356960760522105306 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 238.edn_genbits.67057487072114450754828088462842356467384663469267789769937356960760522105306
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.14710136947059148598561991879743555917890264812748395495034132255101927396770
Short name T615
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Nov 22 01:36:52 PM PST 23
Finished Nov 22 01:36:57 PM PST 23
Peak memory 205764 kb
Host smart-9f7b51a7-a00f-4f9c-a107-76b158d056c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14710136947059148598561991879743555917890264812748395495034132255101927396770 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 239.edn_genbits.14710136947059148598561991879743555917890264812748395495034132255101927396770
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.4225910073237425391767325482954639007377169232930371522145431841344299060594
Short name T391
Test name
Test status
Simulation time 18259183 ps
CPU time 1 seconds
Started Nov 22 01:34:14 PM PST 23
Finished Nov 22 01:34:16 PM PST 23
Peak memory 205508 kb
Host smart-3cac3c3d-f969-4611-b343-800220ad253b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225910073237425391767325482954639007377169232930371522145431841344299060594 -assert nopostproc +UVM_TESTNAME=edn_alert_
test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.edn_alert.4225910073237425391767325482954639007377169232930371522145431841344299060594
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.110569354594089210227650570510061271411099699786917344407663213519452423482693
Short name T554
Test name
Test status
Simulation time 28184990 ps
CPU time 0.87 seconds
Started Nov 22 01:34:15 PM PST 23
Finished Nov 22 01:34:17 PM PST 23
Peak memory 205488 kb
Host smart-1b9a8346-4df0-4cff-8eea-9872020e6264
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110569354594089210227650570510061271411099699786917344407663213519452423482693 -assert nopostp
roc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 24.edn_alert_test.110569354594089210227650570510061271411099699786917344407663213519452423482693
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.100335326953798211167767273497035649570791824275919595151671720283534567711852
Short name T886
Test name
Test status
Simulation time 12219183 ps
CPU time 0.97 seconds
Started Nov 22 01:34:18 PM PST 23
Finished Nov 22 01:34:20 PM PST 23
Peak memory 214748 kb
Host smart-bf36a57b-4bf6-4e17-8d3e-fbb6107ed440
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100335326953798211167767273497035649570791824275919595151671720283534567711852 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 24.edn_disable.100335326953798211167767273497035649570791824275919595151671720283534567711852
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.38870973492535807498831551819501183344299736000915874309344976838368429012469
Short name T710
Test name
Test status
Simulation time 14969183 ps
CPU time 0.94 seconds
Started Nov 22 01:34:33 PM PST 23
Finished Nov 22 01:34:34 PM PST 23
Peak memory 214864 kb
Host smart-80f103c1-dcac-4ddf-9738-a95f343bfb3f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38870973492535807498831551819501183344299736000915874309344976838368429012469 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable_auto_req_mode.3887097349253580749883155181950118334429973600091587430934
4976838368429012469
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.3773183687961084561114733682724767356600200123808972245551231304839984922841
Short name T551
Test name
Test status
Simulation time 24963823 ps
CPU time 1.16 seconds
Started Nov 22 01:34:15 PM PST 23
Finished Nov 22 01:34:18 PM PST 23
Peak memory 230448 kb
Host smart-cc0acff6-559e-42cf-b1a2-1b95d9b546d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773183687961084561114733682724767356600200123808972245551231304839984922841 -assert nopostproc +UVM_TESTNAME=edn_err_te
st +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
edn_err.3773183687961084561114733682724767356600200123808972245551231304839984922841
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.15912052756346617481376277302282910352430434770901240591633326304419573557431
Short name T379
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 22 01:34:18 PM PST 23
Finished Nov 22 01:34:20 PM PST 23
Peak memory 205848 kb
Host smart-b946701d-148a-4481-978e-7b201815b3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15912052756346617481376277302282910352430434770901240591633326304419573557431 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.edn_genbits.15912052756346617481376277302282910352430434770901240591633326304419573557431
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.112405978150619991018724753315732260252608763793698233049830411909920716623043
Short name T895
Test name
Test status
Simulation time 18439183 ps
CPU time 1.16 seconds
Started Nov 22 01:34:13 PM PST 23
Finished Nov 22 01:34:15 PM PST 23
Peak memory 222280 kb
Host smart-5056fc4e-db71-4e5c-bf13-12552c1b238f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112405978150619991018724753315732260252608763793698233049830411909920716623043 -assert nopostproc +UVM_TESTNAME=edn_intr
_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.edn_intr.112405978150619991018724753315732260252608763793698233049830411909920716623043
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.110959029739155201781288211385493388657952142333301037593399074134166147620106
Short name T857
Test name
Test status
Simulation time 13059183 ps
CPU time 0.84 seconds
Started Nov 22 01:34:14 PM PST 23
Finished Nov 22 01:34:16 PM PST 23
Peak memory 205300 kb
Host smart-c980634e-dbf9-4b1a-aff7-3004b8ffda75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110959029739155201781288211385493388657952142333301037593399074134166147620106 -assert nopostproc +UVM_TESTNAME=edn_smok
e_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 24.edn_smoke.110959029739155201781288211385493388657952142333301037593399074134166147620106
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.2858319495573724568152152705865873444570850457714078119613370270659414173602
Short name T792
Test name
Test status
Simulation time 154489183 ps
CPU time 4.04 seconds
Started Nov 22 01:34:29 PM PST 23
Finished Nov 22 01:34:34 PM PST 23
Peak memory 206352 kb
Host smart-4e543625-b951-4cda-9a31-b115b575b85c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858319495573724568152152705865873444570850457714078119613370270659414173602 -assert nopost
proc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.2858319495573724568152152705865873444570850457714078119613370270659414173602
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.16183263588490384795763279775353626588786348941242395216559618644456810318758
Short name T743
Test name
Test status
Simulation time 41708099183 ps
CPU time 1111.53 seconds
Started Nov 22 01:34:13 PM PST 23
Finished Nov 22 01:52:46 PM PST 23
Peak memory 215848 kb
Host smart-3ad9f76f-9507-4643-b0e3-c1585edf9633
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161832635884903847957632797
75353626588786348941242395216559618644456810318758 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.16183263588
490384795763279775353626588786348941242395216559618644456810318758
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.97312700396570962590827141994792417327118329943983341891464560716017458053945
Short name T520
Test name
Test status
Simulation time 17999183 ps
CPU time 1.17 seconds
Started Nov 22 01:36:50 PM PST 23
Finished Nov 22 01:36:55 PM PST 23
Peak memory 205804 kb
Host smart-bc208d1e-988d-406f-ab3d-4cd221157569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97312700396570962590827141994792417327118329943983341891464560716017458053945 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 240.edn_genbits.97312700396570962590827141994792417327118329943983341891464560716017458053945
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.76795186047494566238014217812986192485196019196720204603794761019925970336633
Short name T890
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 22 01:36:53 PM PST 23
Finished Nov 22 01:36:59 PM PST 23
Peak memory 205848 kb
Host smart-f60660be-de70-480e-8209-c4685fe50eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76795186047494566238014217812986192485196019196720204603794761019925970336633 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 241.edn_genbits.76795186047494566238014217812986192485196019196720204603794761019925970336633
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.94715185853940091535094646606146900881133680784981055563463255216705421290520
Short name T75
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 22 01:36:53 PM PST 23
Finished Nov 22 01:36:58 PM PST 23
Peak memory 205848 kb
Host smart-0b7a727a-4666-4d15-8399-8070cacdcfa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94715185853940091535094646606146900881133680784981055563463255216705421290520 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 242.edn_genbits.94715185853940091535094646606146900881133680784981055563463255216705421290520
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.69697262888933185785169651830146041757705446736684972627053837459009879432747
Short name T697
Test name
Test status
Simulation time 17999183 ps
CPU time 1.15 seconds
Started Nov 22 01:36:52 PM PST 23
Finished Nov 22 01:36:58 PM PST 23
Peak memory 205848 kb
Host smart-e79955ce-f80d-4c10-8076-575b09f7a538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69697262888933185785169651830146041757705446736684972627053837459009879432747 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 243.edn_genbits.69697262888933185785169651830146041757705446736684972627053837459009879432747
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.108709429870144183981139616924655541494555376153362699222747457526969253374348
Short name T840
Test name
Test status
Simulation time 17999183 ps
CPU time 1.06 seconds
Started Nov 22 01:36:52 PM PST 23
Finished Nov 22 01:36:58 PM PST 23
Peak memory 205840 kb
Host smart-1c0916a9-286c-4c0a-be87-3e6fe6bfe6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108709429870144183981139616924655541494555376153362699222747457526969253374348 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 244.edn_genbits.108709429870144183981139616924655541494555376153362699222747457526969253374348
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.1003414969212616087669113818966604717889741948566749717456233144262435660644
Short name T766
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:36:54 PM PST 23
Finished Nov 22 01:37:01 PM PST 23
Peak memory 205848 kb
Host smart-ae4266c5-03c5-48ec-af45-07e1e4fffab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003414969212616087669113818966604717889741948566749717456233144262435660644 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 245.edn_genbits.1003414969212616087669113818966604717889741948566749717456233144262435660644
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.25350652854863299402608086346418215197258837347522804628710815782296306508169
Short name T719
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:36:54 PM PST 23
Finished Nov 22 01:37:01 PM PST 23
Peak memory 205784 kb
Host smart-18c3397b-199e-4a31-a8cf-e0bf14ddecb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25350652854863299402608086346418215197258837347522804628710815782296306508169 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 246.edn_genbits.25350652854863299402608086346418215197258837347522804628710815782296306508169
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.39671637584792692901114471529668755785798072783990992139348610894135952854867
Short name T934
Test name
Test status
Simulation time 17999183 ps
CPU time 1.05 seconds
Started Nov 22 01:36:54 PM PST 23
Finished Nov 22 01:37:00 PM PST 23
Peak memory 205848 kb
Host smart-fc3f853c-f9ed-4514-98fa-702fc8178fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39671637584792692901114471529668755785798072783990992139348610894135952854867 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 247.edn_genbits.39671637584792692901114471529668755785798072783990992139348610894135952854867
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.55629618333152196429636109939541160223365152373779483039295713099969156394602
Short name T288
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:36:53 PM PST 23
Finished Nov 22 01:37:00 PM PST 23
Peak memory 205804 kb
Host smart-7052452e-6e95-4a2b-8356-cb46a187a9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55629618333152196429636109939541160223365152373779483039295713099969156394602 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 248.edn_genbits.55629618333152196429636109939541160223365152373779483039295713099969156394602
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.97961605499168312494146977500176522326323211522178980663759451738168522614836
Short name T257
Test name
Test status
Simulation time 17999183 ps
CPU time 1.06 seconds
Started Nov 22 01:36:53 PM PST 23
Finished Nov 22 01:36:59 PM PST 23
Peak memory 205784 kb
Host smart-6de4a493-2d3e-465c-9f43-37cb26743620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97961605499168312494146977500176522326323211522178980663759451738168522614836 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 249.edn_genbits.97961605499168312494146977500176522326323211522178980663759451738168522614836
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.3586284348919425293884540300180637779270169460584610868281821337104681326553
Short name T956
Test name
Test status
Simulation time 18259183 ps
CPU time 1.01 seconds
Started Nov 22 01:34:40 PM PST 23
Finished Nov 22 01:34:42 PM PST 23
Peak memory 205544 kb
Host smart-41c2b319-dbdf-4b12-a66e-4301ce6bcb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586284348919425293884540300180637779270169460584610868281821337104681326553 -assert nopostproc +UVM_TESTNAME=edn_alert_
test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.edn_alert.3586284348919425293884540300180637779270169460584610868281821337104681326553
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.113358173799244876334572101493610680614112466127989109106915154223647572554537
Short name T290
Test name
Test status
Simulation time 28184990 ps
CPU time 0.88 seconds
Started Nov 22 01:34:40 PM PST 23
Finished Nov 22 01:34:42 PM PST 23
Peak memory 205532 kb
Host smart-629b66aa-e729-4f49-8a27-418092fc898b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113358173799244876334572101493610680614112466127989109106915154223647572554537 -assert nopostp
roc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 25.edn_alert_test.113358173799244876334572101493610680614112466127989109106915154223647572554537
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.4863387332227339459233315918928360822111443627217348580231067365964576370333
Short name T353
Test name
Test status
Simulation time 12219183 ps
CPU time 0.99 seconds
Started Nov 22 01:34:40 PM PST 23
Finished Nov 22 01:34:43 PM PST 23
Peak memory 214744 kb
Host smart-46b04b7c-9289-4185-93aa-001c85064918
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4863387332227339459233315918928360822111443627217348580231067365964576370333 -assert nopostproc
+UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.edn_disable.4863387332227339459233315918928360822111443627217348580231067365964576370333
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.81926539635839761523076057796909015079890632276213427801724430086626275536941
Short name T303
Test name
Test status
Simulation time 14969183 ps
CPU time 0.94 seconds
Started Nov 22 01:34:40 PM PST 23
Finished Nov 22 01:34:42 PM PST 23
Peak memory 214840 kb
Host smart-1cd9ea94-c114-437f-b9da-5d544f43492e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81926539635839761523076057796909015079890632276213427801724430086626275536941 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable_auto_req_mode.8192653963583976152307605779690901507989063227621342780172
4430086626275536941
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.10939182078614569268690539084421365898593216172245070213988911280251126420729
Short name T562
Test name
Test status
Simulation time 24963823 ps
CPU time 1.2 seconds
Started Nov 22 01:34:40 PM PST 23
Finished Nov 22 01:34:43 PM PST 23
Peak memory 230460 kb
Host smart-bbb386a8-5206-4381-8f64-7aa6755949d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10939182078614569268690539084421365898593216172245070213988911280251126420729 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.edn_err.10939182078614569268690539084421365898593216172245070213988911280251126420729
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.11793111767085914874687291155224465755795897490778934640802515143008621662756
Short name T504
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 22 01:34:15 PM PST 23
Finished Nov 22 01:34:17 PM PST 23
Peak memory 205848 kb
Host smart-86572a93-af3d-4739-bd6b-a5d85ecbf6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11793111767085914874687291155224465755795897490778934640802515143008621662756 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.edn_genbits.11793111767085914874687291155224465755795897490778934640802515143008621662756
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.86218444849853317879176782922667434507957744090649457717363352204998169081068
Short name T76
Test name
Test status
Simulation time 18439183 ps
CPU time 1.11 seconds
Started Nov 22 01:34:16 PM PST 23
Finished Nov 22 01:34:19 PM PST 23
Peak memory 222272 kb
Host smart-62d6f6df-37e3-42d4-a9ed-9a989712641e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86218444849853317879176782922667434507957744090649457717363352204998169081068 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.edn_intr.86218444849853317879176782922667434507957744090649457717363352204998169081068
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.77162796558262167048284966295366944054395049759983179439276393471283781980272
Short name T287
Test name
Test status
Simulation time 13059183 ps
CPU time 0.9 seconds
Started Nov 22 01:34:37 PM PST 23
Finished Nov 22 01:34:38 PM PST 23
Peak memory 205372 kb
Host smart-b5a3e703-f1dc-4c0e-964e-5cb0af9d959e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77162796558262167048284966295366944054395049759983179439276393471283781980272 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 25.edn_smoke.77162796558262167048284966295366944054395049759983179439276393471283781980272
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.31240221291215743395344876111284417384083779001689318495797228502595064685645
Short name T722
Test name
Test status
Simulation time 154489183 ps
CPU time 4.05 seconds
Started Nov 22 01:34:17 PM PST 23
Finished Nov 22 01:34:22 PM PST 23
Peak memory 206304 kb
Host smart-fb276cee-fbed-4754-8d65-1f7859b0869f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31240221291215743395344876111284417384083779001689318495797228502595064685645 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.31240221291215743395344876111284417384083779001689318495797228502595064685645
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.55317911149025877452840269232050911147543159798594366273705831713829962815674
Short name T789
Test name
Test status
Simulation time 41708099183 ps
CPU time 1049.73 seconds
Started Nov 22 01:34:15 PM PST 23
Finished Nov 22 01:51:47 PM PST 23
Peak memory 215872 kb
Host smart-9a94b7e3-1ea0-4d3a-b75c-abf822b02864
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553179111490258774528402692
32050911147543159798594366273705831713829962815674 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.55317911149
025877452840269232050911147543159798594366273705831713829962815674
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.62331343974556159100365065185938482743042204311349876366719433273950181388165
Short name T581
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:36:54 PM PST 23
Finished Nov 22 01:37:01 PM PST 23
Peak memory 205804 kb
Host smart-e6b5bb61-445c-4dcb-b972-fb706a783f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62331343974556159100365065185938482743042204311349876366719433273950181388165 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 250.edn_genbits.62331343974556159100365065185938482743042204311349876366719433273950181388165
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.8021214706321927358967019945239974021096192513117523394701936814462333974970
Short name T271
Test name
Test status
Simulation time 17999183 ps
CPU time 1.06 seconds
Started Nov 22 01:36:53 PM PST 23
Finished Nov 22 01:36:59 PM PST 23
Peak memory 205784 kb
Host smart-28f1d866-014c-4547-a5ab-31759db1d655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8021214706321927358967019945239974021096192513117523394701936814462333974970 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 251.edn_genbits.8021214706321927358967019945239974021096192513117523394701936814462333974970
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.38504641565165819091897904218832779215062565225388668988505406645067020219106
Short name T253
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 22 01:36:55 PM PST 23
Finished Nov 22 01:37:01 PM PST 23
Peak memory 205856 kb
Host smart-2946d680-7174-46a7-bbc4-b3fdddba779c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38504641565165819091897904218832779215062565225388668988505406645067020219106 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 252.edn_genbits.38504641565165819091897904218832779215062565225388668988505406645067020219106
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.105520614345911288395068781570350341635476793849334909171967393557180853108135
Short name T821
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 22 01:36:56 PM PST 23
Finished Nov 22 01:37:02 PM PST 23
Peak memory 205752 kb
Host smart-1712801a-63ba-4428-8888-a8f722263718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105520614345911288395068781570350341635476793849334909171967393557180853108135 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 253.edn_genbits.105520614345911288395068781570350341635476793849334909171967393557180853108135
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.84775018521286929267025050605276364541327789596339361240770168609790677584574
Short name T837
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 22 01:36:49 PM PST 23
Finished Nov 22 01:36:53 PM PST 23
Peak memory 205856 kb
Host smart-eac257a4-6787-423d-ac60-ec30250ed885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84775018521286929267025050605276364541327789596339361240770168609790677584574 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 254.edn_genbits.84775018521286929267025050605276364541327789596339361240770168609790677584574
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.13019559909302151675183928972750282158823479429908937117021687598847605930866
Short name T393
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:36:56 PM PST 23
Finished Nov 22 01:37:02 PM PST 23
Peak memory 205748 kb
Host smart-a9a1923d-c920-4998-b7c4-6d2ba5b38052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13019559909302151675183928972750282158823479429908937117021687598847605930866 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 255.edn_genbits.13019559909302151675183928972750282158823479429908937117021687598847605930866
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.77560601745651857469431503543653208876138863082169593233757978163033715980092
Short name T923
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:36:54 PM PST 23
Finished Nov 22 01:37:01 PM PST 23
Peak memory 205784 kb
Host smart-999c72b1-a29d-4844-ad7f-b58c891e8441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77560601745651857469431503543653208876138863082169593233757978163033715980092 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 256.edn_genbits.77560601745651857469431503543653208876138863082169593233757978163033715980092
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.48323752069728376546842539514522614006586094248892514226663457397334081797945
Short name T404
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:36:48 PM PST 23
Finished Nov 22 01:36:50 PM PST 23
Peak memory 205780 kb
Host smart-62bf1ab4-8d3d-4db0-aa1e-28c3f8fb02f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48323752069728376546842539514522614006586094248892514226663457397334081797945 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 257.edn_genbits.48323752069728376546842539514522614006586094248892514226663457397334081797945
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.49793812455787266269277722726685849892152937431929788322472674561313213966931
Short name T429
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:36:35 PM PST 23
Finished Nov 22 01:36:38 PM PST 23
Peak memory 205812 kb
Host smart-18ebeb1a-560f-4089-a4c2-a44f76c07754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49793812455787266269277722726685849892152937431929788322472674561313213966931 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 258.edn_genbits.49793812455787266269277722726685849892152937431929788322472674561313213966931
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.49919374793536979289225641071729122863507212484034847519245620245581765405656
Short name T706
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 22 01:36:54 PM PST 23
Finished Nov 22 01:37:01 PM PST 23
Peak memory 205856 kb
Host smart-a5e550d1-bc66-40ea-a2dd-4329db5d1942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49919374793536979289225641071729122863507212484034847519245620245581765405656 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 259.edn_genbits.49919374793536979289225641071729122863507212484034847519245620245581765405656
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.65969547395322954982215181861697947209309927648827270228446244835989529761445
Short name T451
Test name
Test status
Simulation time 18259183 ps
CPU time 0.96 seconds
Started Nov 22 01:35:04 PM PST 23
Finished Nov 22 01:35:07 PM PST 23
Peak memory 205488 kb
Host smart-b4dc1584-9b96-4823-ba3a-0e086fdb6e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65969547395322954982215181861697947209309927648827270228446244835989529761445 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 26.edn_alert.65969547395322954982215181861697947209309927648827270228446244835989529761445
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.10513276861875174268440676729965135550739127840885371086422588746249762025652
Short name T442
Test name
Test status
Simulation time 28184990 ps
CPU time 0.89 seconds
Started Nov 22 01:34:52 PM PST 23
Finished Nov 22 01:34:54 PM PST 23
Peak memory 205376 kb
Host smart-bbfe5564-3f28-4597-a98a-fee55def5ba1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10513276861875174268440676729965135550739127840885371086422588746249762025652 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.edn_alert_test.10513276861875174268440676729965135550739127840885371086422588746249762025652
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.82433908875128046882204586112759566826681416244974447347689075684561552649069
Short name T928
Test name
Test status
Simulation time 12219183 ps
CPU time 0.88 seconds
Started Nov 22 01:34:53 PM PST 23
Finished Nov 22 01:34:55 PM PST 23
Peak memory 214880 kb
Host smart-366ad618-ff1a-4980-840d-8560ef58ec05
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82433908875128046882204586112759566826681416244974447347689075684561552649069 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.edn_disable.82433908875128046882204586112759566826681416244974447347689075684561552649069
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.9006062045271672016658568220301676602110955120685135015843406270891873094553
Short name T707
Test name
Test status
Simulation time 14969183 ps
CPU time 0.89 seconds
Started Nov 22 01:34:52 PM PST 23
Finished Nov 22 01:34:54 PM PST 23
Peak memory 214880 kb
Host smart-c06ec6c8-b9d9-4028-8f6e-bdd0f79a7cc6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9006062045271672016658568220301676602110955120685135015843406270891873094553 -assert nopostproc
+UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable_auto_req_mode.90060620452716720166585682203016766021109551206851350158434
06270891873094553
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.93870724351462633960910791388738329888233813674390007726906909990463614524702
Short name T887
Test name
Test status
Simulation time 24963823 ps
CPU time 1.15 seconds
Started Nov 22 01:34:40 PM PST 23
Finished Nov 22 01:34:43 PM PST 23
Peak memory 230424 kb
Host smart-6c79448b-dffc-47d4-bc1a-c388b7bbe207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93870724351462633960910791388738329888233813674390007726906909990463614524702 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.edn_err.93870724351462633960910791388738329888233813674390007726906909990463614524702
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.25609773780464238116599911319045581428397558287371912649758784660836603973895
Short name T495
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:34:33 PM PST 23
Finished Nov 22 01:34:34 PM PST 23
Peak memory 205824 kb
Host smart-92344054-a146-4990-96b5-d55e423e6c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25609773780464238116599911319045581428397558287371912649758784660836603973895 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.edn_genbits.25609773780464238116599911319045581428397558287371912649758784660836603973895
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.59474162013218678273492388647101261920207037513791239939465240720684893425607
Short name T763
Test name
Test status
Simulation time 18439183 ps
CPU time 1.13 seconds
Started Nov 22 01:34:41 PM PST 23
Finished Nov 22 01:34:43 PM PST 23
Peak memory 222228 kb
Host smart-6a47f830-e27b-4db7-830a-a7998fa3aaba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59474162013218678273492388647101261920207037513791239939465240720684893425607 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.edn_intr.59474162013218678273492388647101261920207037513791239939465240720684893425607
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.70877389560897111632999281874859810019938110618524194551691693612336611285765
Short name T306
Test name
Test status
Simulation time 13059183 ps
CPU time 0.95 seconds
Started Nov 22 01:34:41 PM PST 23
Finished Nov 22 01:34:43 PM PST 23
Peak memory 205344 kb
Host smart-9b2b6ecc-e7cc-43e8-9e83-e7018ee9fe12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70877389560897111632999281874859810019938110618524194551691693612336611285765 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 26.edn_smoke.70877389560897111632999281874859810019938110618524194551691693612336611285765
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.33414328176751974271688394352391638831165458929560396252665258535126523295005
Short name T513
Test name
Test status
Simulation time 154489183 ps
CPU time 3.91 seconds
Started Nov 22 01:34:41 PM PST 23
Finished Nov 22 01:34:46 PM PST 23
Peak memory 206372 kb
Host smart-e210f70c-cdd2-4a94-8eab-232dadef89ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33414328176751974271688394352391638831165458929560396252665258535126523295005 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.33414328176751974271688394352391638831165458929560396252665258535126523295005
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.17308657769355875194160960973004198012209021504896267876049683330270252929027
Short name T641
Test name
Test status
Simulation time 41708099183 ps
CPU time 1080.82 seconds
Started Nov 22 01:34:29 PM PST 23
Finished Nov 22 01:52:31 PM PST 23
Peak memory 215840 kb
Host smart-2857dfac-fa7b-4ee6-ab91-dbe13f933e2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173086577693558751941609609
73004198012209021504896267876049683330270252929027 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.17308657769
355875194160960973004198012209021504896267876049683330270252929027
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.7797342319282538441560369590088374420314363496297438407042515164173126538779
Short name T961
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 22 01:36:43 PM PST 23
Finished Nov 22 01:36:45 PM PST 23
Peak memory 205820 kb
Host smart-6f1598b7-034a-44d4-b21f-7105a8eb3726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7797342319282538441560369590088374420314363496297438407042515164173126538779 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 260.edn_genbits.7797342319282538441560369590088374420314363496297438407042515164173126538779
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.26863638471150749192876247767767540287437757473368627547299707673788755195426
Short name T693
Test name
Test status
Simulation time 17999183 ps
CPU time 1.04 seconds
Started Nov 22 01:36:34 PM PST 23
Finished Nov 22 01:36:36 PM PST 23
Peak memory 205764 kb
Host smart-1d1dab7b-0239-4f78-affd-049550c900c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26863638471150749192876247767767540287437757473368627547299707673788755195426 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 261.edn_genbits.26863638471150749192876247767767540287437757473368627547299707673788755195426
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.26169448002149570449639706417478829521933783003637956882937169570855637052783
Short name T17
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:36:37 PM PST 23
Finished Nov 22 01:36:41 PM PST 23
Peak memory 205868 kb
Host smart-af721fe4-fe10-406c-9e52-3e7625426da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26169448002149570449639706417478829521933783003637956882937169570855637052783 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 262.edn_genbits.26169448002149570449639706417478829521933783003637956882937169570855637052783
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.103179706839881129307586661713422217111732133244942353453692929960763137379096
Short name T64
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:36:50 PM PST 23
Finished Nov 22 01:36:54 PM PST 23
Peak memory 205808 kb
Host smart-b88cffa4-56ea-4532-bfb9-8b1e6a40c382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103179706839881129307586661713422217111732133244942353453692929960763137379096 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 263.edn_genbits.103179706839881129307586661713422217111732133244942353453692929960763137379096
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.37456923315847513652595916157407947260011697557356476525137981649619599587618
Short name T462
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:36:36 PM PST 23
Finished Nov 22 01:36:39 PM PST 23
Peak memory 205808 kb
Host smart-5ff6ee22-fb7a-45fa-b965-989bdc82484a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37456923315847513652595916157407947260011697557356476525137981649619599587618 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 264.edn_genbits.37456923315847513652595916157407947260011697557356476525137981649619599587618
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.106243450596409072027446407672979683522203722085310298765126694856469131513967
Short name T820
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:36:27 PM PST 23
Finished Nov 22 01:36:29 PM PST 23
Peak memory 205808 kb
Host smart-2745988b-032a-4ad9-afc8-b64680bca6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106243450596409072027446407672979683522203722085310298765126694856469131513967 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 265.edn_genbits.106243450596409072027446407672979683522203722085310298765126694856469131513967
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.66534395190217717934771130489972434427555406766958157261378363241545739421760
Short name T646
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 22 01:36:35 PM PST 23
Finished Nov 22 01:36:38 PM PST 23
Peak memory 205824 kb
Host smart-6095ad19-7fa5-4811-b115-aaeb520e8176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66534395190217717934771130489972434427555406766958157261378363241545739421760 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 266.edn_genbits.66534395190217717934771130489972434427555406766958157261378363241545739421760
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.19427372103673979418105076895891411211905846593904351011400916889810475428539
Short name T58
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 22 01:36:35 PM PST 23
Finished Nov 22 01:36:38 PM PST 23
Peak memory 205832 kb
Host smart-a1cfea22-c7c6-432b-bec5-7d2c92e0f73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19427372103673979418105076895891411211905846593904351011400916889810475428539 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 267.edn_genbits.19427372103673979418105076895891411211905846593904351011400916889810475428539
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.103561642044963656960544299440661118470180378428243825291657689015717405897609
Short name T701
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:36:30 PM PST 23
Finished Nov 22 01:36:32 PM PST 23
Peak memory 205852 kb
Host smart-45dd0f47-399d-4ea3-b818-2d6548d8590f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103561642044963656960544299440661118470180378428243825291657689015717405897609 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 268.edn_genbits.103561642044963656960544299440661118470180378428243825291657689015717405897609
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.70391331109234089403907079665365153396593557242204522314800643209401840915163
Short name T275
Test name
Test status
Simulation time 17999183 ps
CPU time 1.06 seconds
Started Nov 22 01:36:32 PM PST 23
Finished Nov 22 01:36:33 PM PST 23
Peak memory 205808 kb
Host smart-6a7e2e15-8903-45eb-9d21-a5a3d1c436f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70391331109234089403907079665365153396593557242204522314800643209401840915163 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 269.edn_genbits.70391331109234089403907079665365153396593557242204522314800643209401840915163
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.99660318391818235571877105066239550125721250215042732559869804767704508333747
Short name T496
Test name
Test status
Simulation time 18259183 ps
CPU time 0.96 seconds
Started Nov 22 01:34:29 PM PST 23
Finished Nov 22 01:34:31 PM PST 23
Peak memory 205580 kb
Host smart-e8e8bd4e-2375-4126-9492-a69fb5273d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99660318391818235571877105066239550125721250215042732559869804767704508333747 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 27.edn_alert.99660318391818235571877105066239550125721250215042732559869804767704508333747
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.92495709988463102882213533128410857564794204681537181869668890356045430386656
Short name T633
Test name
Test status
Simulation time 28184990 ps
CPU time 0.91 seconds
Started Nov 22 01:34:40 PM PST 23
Finished Nov 22 01:34:42 PM PST 23
Peak memory 205476 kb
Host smart-eac07e92-5081-4ca8-862d-21649263c3cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92495709988463102882213533128410857564794204681537181869668890356045430386656 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.edn_alert_test.92495709988463102882213533128410857564794204681537181869668890356045430386656
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.85049318731903395356808920203734510076797244225122994639644655296802092247075
Short name T622
Test name
Test status
Simulation time 12219183 ps
CPU time 0.82 seconds
Started Nov 22 01:34:38 PM PST 23
Finished Nov 22 01:34:39 PM PST 23
Peak memory 214800 kb
Host smart-5967513b-589e-489f-81ea-ba2f4b2636a4
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85049318731903395356808920203734510076797244225122994639644655296802092247075 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.edn_disable.85049318731903395356808920203734510076797244225122994639644655296802092247075
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.111567030596940846340625283198849798833669437319023933055271283916241494606913
Short name T267
Test name
Test status
Simulation time 14969183 ps
CPU time 0.87 seconds
Started Nov 22 01:34:28 PM PST 23
Finished Nov 22 01:34:29 PM PST 23
Peak memory 214864 kb
Host smart-2af607b8-d9e1-4739-9e49-dfaeeff46369
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111567030596940846340625283198849798833669437319023933055271283916241494606913 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable_auto_req_mode.111567030596940846340625283198849798833669437319023933055
271283916241494606913
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.30249517821938581813937021321830176428220913779979790954999468592176442124915
Short name T836
Test name
Test status
Simulation time 24963823 ps
CPU time 1.12 seconds
Started Nov 22 01:34:28 PM PST 23
Finished Nov 22 01:34:30 PM PST 23
Peak memory 230448 kb
Host smart-866bc4bb-c2f2-45d6-a9f8-5be4fef9954b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30249517821938581813937021321830176428220913779979790954999468592176442124915 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.edn_err.30249517821938581813937021321830176428220913779979790954999468592176442124915
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.42111707091180900406450657254696324609570846120646903977837156478447691153621
Short name T385
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 22 01:34:54 PM PST 23
Finished Nov 22 01:34:56 PM PST 23
Peak memory 205856 kb
Host smart-33f800b1-f862-404a-aebc-9f70fb5f4d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42111707091180900406450657254696324609570846120646903977837156478447691153621 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.edn_genbits.42111707091180900406450657254696324609570846120646903977837156478447691153621
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.112707104042680117322357187098570394505503110384747631365445848302966938131018
Short name T879
Test name
Test status
Simulation time 18439183 ps
CPU time 1.11 seconds
Started Nov 22 01:34:26 PM PST 23
Finished Nov 22 01:34:28 PM PST 23
Peak memory 222264 kb
Host smart-5b430226-7e49-4303-9be6-2bab34476049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112707104042680117322357187098570394505503110384747631365445848302966938131018 -assert nopostproc +UVM_TESTNAME=edn_intr
_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.edn_intr.112707104042680117322357187098570394505503110384747631365445848302966938131018
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.49545195534373072645083563191222810828984879232493132436332251406912581825572
Short name T97
Test name
Test status
Simulation time 13059183 ps
CPU time 0.89 seconds
Started Nov 22 01:35:03 PM PST 23
Finished Nov 22 01:35:05 PM PST 23
Peak memory 205320 kb
Host smart-3aaa1103-7fca-4f80-a82e-b9a66ca8b4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49545195534373072645083563191222810828984879232493132436332251406912581825572 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 27.edn_smoke.49545195534373072645083563191222810828984879232493132436332251406912581825572
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.28240893765704682418860070465437825414877322005633407192360972321197501294962
Short name T939
Test name
Test status
Simulation time 154489183 ps
CPU time 4.14 seconds
Started Nov 22 01:35:03 PM PST 23
Finished Nov 22 01:35:10 PM PST 23
Peak memory 206228 kb
Host smart-d0bf73cb-7000-4aa6-a235-a83cc801d491
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28240893765704682418860070465437825414877322005633407192360972321197501294962 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.28240893765704682418860070465437825414877322005633407192360972321197501294962
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.79186433639992078611115757760222912831617990785573847577131942263120404638211
Short name T785
Test name
Test status
Simulation time 41708099183 ps
CPU time 1097.31 seconds
Started Nov 22 01:34:27 PM PST 23
Finished Nov 22 01:52:46 PM PST 23
Peak memory 215792 kb
Host smart-eda87ae3-96cd-4c68-bc09-bcfc3d6c169e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791864336399920786111157577
60222912831617990785573847577131942263120404638211 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.79186433639
992078611115757760222912831617990785573847577131942263120404638211
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.105973797608484230660346376747725960017355049523638215713263860214970116499626
Short name T56
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 22 01:36:33 PM PST 23
Finished Nov 22 01:36:34 PM PST 23
Peak memory 205852 kb
Host smart-b4c36aaa-d929-4716-9704-ca2b1997e47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105973797608484230660346376747725960017355049523638215713263860214970116499626 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 270.edn_genbits.105973797608484230660346376747725960017355049523638215713263860214970116499626
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.85344537171502429936488742071180086471627245657141026363523038188202938411430
Short name T606
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:36:36 PM PST 23
Finished Nov 22 01:36:40 PM PST 23
Peak memory 205792 kb
Host smart-82786b28-1e25-40ec-9932-d9043b433ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85344537171502429936488742071180086471627245657141026363523038188202938411430 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 271.edn_genbits.85344537171502429936488742071180086471627245657141026363523038188202938411430
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.61259097534847922446664427837724833989502715109560500226293436437071139114204
Short name T77
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:36:36 PM PST 23
Finished Nov 22 01:36:40 PM PST 23
Peak memory 205764 kb
Host smart-0e9828d1-a2f9-43d8-bf6f-a1c22e8d1b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61259097534847922446664427837724833989502715109560500226293436437071139114204 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 272.edn_genbits.61259097534847922446664427837724833989502715109560500226293436437071139114204
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.70542343528162174701475199657867179617488310276490265748823363529828295380919
Short name T839
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 22 01:36:37 PM PST 23
Finished Nov 22 01:36:41 PM PST 23
Peak memory 205792 kb
Host smart-7f797c57-53ff-4ba6-a10d-8132e170e92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70542343528162174701475199657867179617488310276490265748823363529828295380919 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 273.edn_genbits.70542343528162174701475199657867179617488310276490265748823363529828295380919
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.63151126818643791022701138089126219488531535077433399428085204987900401199014
Short name T591
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 22 01:36:35 PM PST 23
Finished Nov 22 01:36:39 PM PST 23
Peak memory 205764 kb
Host smart-353f8f08-07f3-40b5-a1f5-d06c8c59ede1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63151126818643791022701138089126219488531535077433399428085204987900401199014 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 274.edn_genbits.63151126818643791022701138089126219488531535077433399428085204987900401199014
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.7742308171116830211660430845257345469886926399280036118568361825529981819910
Short name T240
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 22 01:36:35 PM PST 23
Finished Nov 22 01:36:37 PM PST 23
Peak memory 205812 kb
Host smart-3912cbd0-727c-4486-8052-7da80a4cb5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7742308171116830211660430845257345469886926399280036118568361825529981819910 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 275.edn_genbits.7742308171116830211660430845257345469886926399280036118568361825529981819910
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.33642012536524841523990473330972315288948011125839836389501530410724148749807
Short name T362
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 22 01:36:45 PM PST 23
Finished Nov 22 01:36:47 PM PST 23
Peak memory 205816 kb
Host smart-8080307e-c4de-44e5-922a-341190ed2897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33642012536524841523990473330972315288948011125839836389501530410724148749807 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 276.edn_genbits.33642012536524841523990473330972315288948011125839836389501530410724148749807
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.24450187805532651906309144588531392949929824887572853784755658517249728109159
Short name T419
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 22 01:36:33 PM PST 23
Finished Nov 22 01:36:35 PM PST 23
Peak memory 205836 kb
Host smart-dbfed08d-9298-4390-a146-bae366bc5f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24450187805532651906309144588531392949929824887572853784755658517249728109159 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 277.edn_genbits.24450187805532651906309144588531392949929824887572853784755658517249728109159
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.85133183728484981416215985637908991807582922686917430947005298802815704188399
Short name T768
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:36:30 PM PST 23
Finished Nov 22 01:36:32 PM PST 23
Peak memory 205728 kb
Host smart-0aac2934-4e5a-4f1b-bf85-3403287f9a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85133183728484981416215985637908991807582922686917430947005298802815704188399 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 278.edn_genbits.85133183728484981416215985637908991807582922686917430947005298802815704188399
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.1851440682913097598307160720293467537523771384329364754246803398523277277151
Short name T372
Test name
Test status
Simulation time 17999183 ps
CPU time 1.15 seconds
Started Nov 22 01:36:44 PM PST 23
Finished Nov 22 01:36:47 PM PST 23
Peak memory 205832 kb
Host smart-75844df4-d235-4d0f-9225-5300b2fb07f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851440682913097598307160720293467537523771384329364754246803398523277277151 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 279.edn_genbits.1851440682913097598307160720293467537523771384329364754246803398523277277151
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.111527932353563963171007199220997637774456992357299530986755180617252172446292
Short name T402
Test name
Test status
Simulation time 18259183 ps
CPU time 0.98 seconds
Started Nov 22 01:34:42 PM PST 23
Finished Nov 22 01:34:44 PM PST 23
Peak memory 205484 kb
Host smart-6c6bb151-9c16-42b0-b9cc-ca9b53370dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111527932353563963171007199220997637774456992357299530986755180617252172446292 -assert nopostproc +UVM_TESTNAME=edn_aler
t_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.edn_alert.111527932353563963171007199220997637774456992357299530986755180617252172446292
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.62215524054665293969253486878590242447306222746046903807292779988801023454555
Short name T46
Test name
Test status
Simulation time 28184990 ps
CPU time 0.86 seconds
Started Nov 22 01:34:42 PM PST 23
Finished Nov 22 01:34:44 PM PST 23
Peak memory 205404 kb
Host smart-7667c28c-51a2-4019-9599-4135a5a50085
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62215524054665293969253486878590242447306222746046903807292779988801023454555 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.edn_alert_test.62215524054665293969253486878590242447306222746046903807292779988801023454555
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.38544766037440715689457069526215126409540181445868862878928051246286836739039
Short name T65
Test name
Test status
Simulation time 12219183 ps
CPU time 0.91 seconds
Started Nov 22 01:34:39 PM PST 23
Finished Nov 22 01:34:41 PM PST 23
Peak memory 214780 kb
Host smart-5afc7048-b34e-40f2-a421-6cfe24f4f930
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38544766037440715689457069526215126409540181445868862878928051246286836739039 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.edn_disable.38544766037440715689457069526215126409540181445868862878928051246286836739039
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.95515179812068139082154859774979410839291600695498346348854934465511623610253
Short name T272
Test name
Test status
Simulation time 14969183 ps
CPU time 0.96 seconds
Started Nov 22 01:34:39 PM PST 23
Finished Nov 22 01:34:41 PM PST 23
Peak memory 214828 kb
Host smart-eaa86d54-1ca7-4a6f-b78c-4ea90baebb82
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95515179812068139082154859774979410839291600695498346348854934465511623610253 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable_auto_req_mode.9551517981206813908215485977497941083929160069549834634885
4934465511623610253
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.92015728928093171815652609330269687408501116209564397442092908424575400284547
Short name T482
Test name
Test status
Simulation time 24963823 ps
CPU time 1.16 seconds
Started Nov 22 01:34:29 PM PST 23
Finished Nov 22 01:34:31 PM PST 23
Peak memory 230424 kb
Host smart-0a6713af-9c65-4a55-b2c5-e2da540d3e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92015728928093171815652609330269687408501116209564397442092908424575400284547 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.edn_err.92015728928093171815652609330269687408501116209564397442092908424575400284547
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.51465890029526147821913387208308682495802831812306986523330028311688051672858
Short name T555
Test name
Test status
Simulation time 17999183 ps
CPU time 1.17 seconds
Started Nov 22 01:34:40 PM PST 23
Finished Nov 22 01:34:42 PM PST 23
Peak memory 205704 kb
Host smart-fb76d5ad-cdb1-4bbe-b8ed-f11bc86d19f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51465890029526147821913387208308682495802831812306986523330028311688051672858 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.edn_genbits.51465890029526147821913387208308682495802831812306986523330028311688051672858
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.70823146017060005952786939646133429274552687045482673050609466616913718800827
Short name T740
Test name
Test status
Simulation time 18439183 ps
CPU time 1.11 seconds
Started Nov 22 01:34:34 PM PST 23
Finished Nov 22 01:34:36 PM PST 23
Peak memory 222280 kb
Host smart-5352b774-08c4-45dd-bd9c-c80d9a0ee508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70823146017060005952786939646133429274552687045482673050609466616913718800827 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.edn_intr.70823146017060005952786939646133429274552687045482673050609466616913718800827
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.68882482042474236300911892280229842477558510843337807892737790343049431965762
Short name T628
Test name
Test status
Simulation time 13059183 ps
CPU time 0.87 seconds
Started Nov 22 01:34:28 PM PST 23
Finished Nov 22 01:34:30 PM PST 23
Peak memory 205284 kb
Host smart-6ba872eb-bcef-4bab-b39e-d3046dbb6465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68882482042474236300911892280229842477558510843337807892737790343049431965762 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 28.edn_smoke.68882482042474236300911892280229842477558510843337807892737790343049431965762
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.49306199896703110425607684942370372410985969936347177497744544259574759486453
Short name T744
Test name
Test status
Simulation time 154489183 ps
CPU time 3.91 seconds
Started Nov 22 01:34:31 PM PST 23
Finished Nov 22 01:34:36 PM PST 23
Peak memory 206396 kb
Host smart-9654447e-4f01-4fd7-91e9-89a35aa52daa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49306199896703110425607684942370372410985969936347177497744544259574759486453 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.49306199896703110425607684942370372410985969936347177497744544259574759486453
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/280.edn_genbits.82011011266125687491726522082666918494126587134619480229614041405813394545304
Short name T676
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 22 01:36:36 PM PST 23
Finished Nov 22 01:36:40 PM PST 23
Peak memory 205792 kb
Host smart-9720a7a1-89d0-4f80-a510-32dd89e143dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82011011266125687491726522082666918494126587134619480229614041405813394545304 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 280.edn_genbits.82011011266125687491726522082666918494126587134619480229614041405813394545304
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.51107018453241352952351098818732562575546884477221011793747568710073273708547
Short name T866
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:36:50 PM PST 23
Finished Nov 22 01:36:54 PM PST 23
Peak memory 205876 kb
Host smart-aacea1cf-b5d9-4ece-8f90-266b0481b544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51107018453241352952351098818732562575546884477221011793747568710073273708547 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 281.edn_genbits.51107018453241352952351098818732562575546884477221011793747568710073273708547
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.64824763512576544169008917723515577665868426184032655223229877214910479725972
Short name T511
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:36:50 PM PST 23
Finished Nov 22 01:36:54 PM PST 23
Peak memory 205884 kb
Host smart-4beb416f-75c3-48ba-8f02-ad7c1073550b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64824763512576544169008917723515577665868426184032655223229877214910479725972 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 282.edn_genbits.64824763512576544169008917723515577665868426184032655223229877214910479725972
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.33901585363025004296776583530359472158272408765998795454952499772279149522735
Short name T432
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 22 01:36:49 PM PST 23
Finished Nov 22 01:36:52 PM PST 23
Peak memory 205824 kb
Host smart-a2b7dd52-f92d-48ba-95cd-0333d1b05d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33901585363025004296776583530359472158272408765998795454952499772279149522735 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 283.edn_genbits.33901585363025004296776583530359472158272408765998795454952499772279149522735
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.115321850273382932433936798841166933924277869782218670270741737747172008788952
Short name T377
Test name
Test status
Simulation time 17999183 ps
CPU time 1.04 seconds
Started Nov 22 01:36:47 PM PST 23
Finished Nov 22 01:36:49 PM PST 23
Peak memory 205760 kb
Host smart-9778dd2c-e24b-4980-a601-de0cfa6fe03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115321850273382932433936798841166933924277869782218670270741737747172008788952 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 284.edn_genbits.115321850273382932433936798841166933924277869782218670270741737747172008788952
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.49582041412484925139752189493200283147658787805652134724751062838401855678085
Short name T252
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 22 01:36:48 PM PST 23
Finished Nov 22 01:36:50 PM PST 23
Peak memory 205820 kb
Host smart-2b25e6d1-44e1-4406-97a6-f3130571d092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49582041412484925139752189493200283147658787805652134724751062838401855678085 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 285.edn_genbits.49582041412484925139752189493200283147658787805652134724751062838401855678085
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.58298328916753719473557013727428609343586123689185272300151593342943234752233
Short name T678
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:36:46 PM PST 23
Finished Nov 22 01:36:49 PM PST 23
Peak memory 205792 kb
Host smart-dfb05865-afe8-45e0-b743-3767db7c9565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58298328916753719473557013727428609343586123689185272300151593342943234752233 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 286.edn_genbits.58298328916753719473557013727428609343586123689185272300151593342943234752233
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.108462349395456338287964272539739644839958244892471562589335060712976398907418
Short name T751
Test name
Test status
Simulation time 17999183 ps
CPU time 1.06 seconds
Started Nov 22 01:36:47 PM PST 23
Finished Nov 22 01:36:49 PM PST 23
Peak memory 205772 kb
Host smart-1073c69b-b4ea-4960-9fe4-8660cac995aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108462349395456338287964272539739644839958244892471562589335060712976398907418 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 287.edn_genbits.108462349395456338287964272539739644839958244892471562589335060712976398907418
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.23616237727363754108720324293518655916330346457504857983756691638067197024407
Short name T783
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 22 01:36:48 PM PST 23
Finished Nov 22 01:36:50 PM PST 23
Peak memory 205820 kb
Host smart-003d88bd-4c13-4cc9-9dc8-1c44cdb1cc06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23616237727363754108720324293518655916330346457504857983756691638067197024407 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 288.edn_genbits.23616237727363754108720324293518655916330346457504857983756691638067197024407
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.63511594621636551219280252051318838665151567888527833342428722913633471459258
Short name T425
Test name
Test status
Simulation time 17999183 ps
CPU time 1.15 seconds
Started Nov 22 01:36:37 PM PST 23
Finished Nov 22 01:36:41 PM PST 23
Peak memory 205864 kb
Host smart-091c8802-7d72-4031-b8c4-a966068f3cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63511594621636551219280252051318838665151567888527833342428722913633471459258 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 289.edn_genbits.63511594621636551219280252051318838665151567888527833342428722913633471459258
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.95354125551566470467288053120858630185145050729714672839821031302626889994699
Short name T42
Test name
Test status
Simulation time 18259183 ps
CPU time 0.98 seconds
Started Nov 22 01:34:38 PM PST 23
Finished Nov 22 01:34:40 PM PST 23
Peak memory 205448 kb
Host smart-602d8339-e473-4b6f-a6d9-1b412ccd57a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95354125551566470467288053120858630185145050729714672839821031302626889994699 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 29.edn_alert.95354125551566470467288053120858630185145050729714672839821031302626889994699
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.110547196808053595912399416586001845632792984644350389784813789299467023519180
Short name T248
Test name
Test status
Simulation time 28184990 ps
CPU time 0.87 seconds
Started Nov 22 01:34:27 PM PST 23
Finished Nov 22 01:34:29 PM PST 23
Peak memory 205480 kb
Host smart-15a891ee-6f2e-415b-8af8-4f4d2493b572
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110547196808053595912399416586001845632792984644350389784813789299467023519180 -assert nopostp
roc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 29.edn_alert_test.110547196808053595912399416586001845632792984644350389784813789299467023519180
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.29018867569985121494454898151742508267808732733011867409279571605137582006860
Short name T468
Test name
Test status
Simulation time 12219183 ps
CPU time 0.87 seconds
Started Nov 22 01:34:45 PM PST 23
Finished Nov 22 01:34:46 PM PST 23
Peak memory 214820 kb
Host smart-75bcff67-b95b-49e7-865f-25b1b0c715d1
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29018867569985121494454898151742508267808732733011867409279571605137582006860 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.edn_disable.29018867569985121494454898151742508267808732733011867409279571605137582006860
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.100564998428172743995577809193687109827727357247936961218497972294771900279268
Short name T613
Test name
Test status
Simulation time 14969183 ps
CPU time 0.94 seconds
Started Nov 22 01:34:28 PM PST 23
Finished Nov 22 01:34:30 PM PST 23
Peak memory 214784 kb
Host smart-ea7a2c22-a280-4bc7-baca-b1f7262eb917
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100564998428172743995577809193687109827727357247936961218497972294771900279268 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable_auto_req_mode.100564998428172743995577809193687109827727357247936961218
497972294771900279268
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.14592798200927655642734717562638053263469194356971349190965170031191039753954
Short name T659
Test name
Test status
Simulation time 24963823 ps
CPU time 1.16 seconds
Started Nov 22 01:34:39 PM PST 23
Finished Nov 22 01:34:41 PM PST 23
Peak memory 230372 kb
Host smart-3b4db8bb-90c9-4997-9cf8-fb1b322a1169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14592798200927655642734717562638053263469194356971349190965170031191039753954 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.edn_err.14592798200927655642734717562638053263469194356971349190965170031191039753954
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.30895494457298239381486064003727789068094310548234522289679561604587322326019
Short name T479
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 22 01:34:45 PM PST 23
Finished Nov 22 01:34:47 PM PST 23
Peak memory 205780 kb
Host smart-4906f427-c0c7-4e65-ab10-af68ba1b42e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30895494457298239381486064003727789068094310548234522289679561604587322326019 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.edn_genbits.30895494457298239381486064003727789068094310548234522289679561604587322326019
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.71705556957543048868848188100001262496324698173177246116605006897785222963470
Short name T950
Test name
Test status
Simulation time 18439183 ps
CPU time 1.13 seconds
Started Nov 22 01:34:45 PM PST 23
Finished Nov 22 01:34:47 PM PST 23
Peak memory 222204 kb
Host smart-cf9aa88f-94cc-40e8-8ef9-4e71c4b7ec0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71705556957543048868848188100001262496324698173177246116605006897785222963470 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.edn_intr.71705556957543048868848188100001262496324698173177246116605006897785222963470
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.44769531456563704898070517675988409113094043598336056411092030767730805341398
Short name T760
Test name
Test status
Simulation time 13059183 ps
CPU time 0.9 seconds
Started Nov 22 01:34:40 PM PST 23
Finished Nov 22 01:34:42 PM PST 23
Peak memory 205332 kb
Host smart-36a30e5e-b442-4f8f-9eea-8cc879a800bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44769531456563704898070517675988409113094043598336056411092030767730805341398 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 29.edn_smoke.44769531456563704898070517675988409113094043598336056411092030767730805341398
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.70958124060438493843554794940215237986262258891156977539304305503750040066063
Short name T920
Test name
Test status
Simulation time 154489183 ps
CPU time 4.04 seconds
Started Nov 22 01:34:41 PM PST 23
Finished Nov 22 01:34:46 PM PST 23
Peak memory 206372 kb
Host smart-e22ec667-b068-4e09-8daa-959a64dc1d93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70958124060438493843554794940215237986262258891156977539304305503750040066063 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.70958124060438493843554794940215237986262258891156977539304305503750040066063
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.24758817454651704710834421609935678329065133722218587546484376814096060873273
Short name T452
Test name
Test status
Simulation time 41708099183 ps
CPU time 1081.79 seconds
Started Nov 22 01:34:28 PM PST 23
Finished Nov 22 01:52:30 PM PST 23
Peak memory 215832 kb
Host smart-475c4e54-086b-41ff-b439-b72634ba2797
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247588174546517047108344216
09935678329065133722218587546484376814096060873273 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.24758817454
651704710834421609935678329065133722218587546484376814096060873273
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.16095824482527376150160893159698642624317989043018589852341338507935752516063
Short name T540
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 22 01:36:49 PM PST 23
Finished Nov 22 01:36:53 PM PST 23
Peak memory 205728 kb
Host smart-77a1e6da-0193-44bf-ae99-e36c92ae3ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16095824482527376150160893159698642624317989043018589852341338507935752516063 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 290.edn_genbits.16095824482527376150160893159698642624317989043018589852341338507935752516063
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.6120163849930121937599247082148275132130310022180131931211871439509697814950
Short name T537
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 22 01:36:52 PM PST 23
Finished Nov 22 01:36:57 PM PST 23
Peak memory 205860 kb
Host smart-585127a4-f58f-4b51-8737-7c72b284311f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6120163849930121937599247082148275132130310022180131931211871439509697814950 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 291.edn_genbits.6120163849930121937599247082148275132130310022180131931211871439509697814950
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.643771501554027615566538975029058940413700604816040511924275658984802585657
Short name T842
Test name
Test status
Simulation time 17999183 ps
CPU time 1.03 seconds
Started Nov 22 01:36:47 PM PST 23
Finished Nov 22 01:36:50 PM PST 23
Peak memory 205728 kb
Host smart-3d422c88-cdb9-47fb-aa01-0abb66196869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643771501554027615566538975029058940413700604816040511924275658984802585657 -assert nopostproc +UVM_TESTNAME=edn_genbits
_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 292.edn_genbits.643771501554027615566538975029058940413700604816040511924275658984802585657
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.84047911643953275033797539839810173796216497114207494489645471379580783579671
Short name T767
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 22 01:36:53 PM PST 23
Finished Nov 22 01:36:58 PM PST 23
Peak memory 205844 kb
Host smart-c6129db4-535b-433b-a689-4771b2189943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84047911643953275033797539839810173796216497114207494489645471379580783579671 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 293.edn_genbits.84047911643953275033797539839810173796216497114207494489645471379580783579671
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.46365741155853271186207497095347445196652729232364770334371583544384891223770
Short name T774
Test name
Test status
Simulation time 17999183 ps
CPU time 1.22 seconds
Started Nov 22 01:36:52 PM PST 23
Finished Nov 22 01:36:57 PM PST 23
Peak memory 205708 kb
Host smart-215ac4d5-0822-4374-a5e3-aecbe6a27196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46365741155853271186207497095347445196652729232364770334371583544384891223770 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 294.edn_genbits.46365741155853271186207497095347445196652729232364770334371583544384891223770
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.36239129178601723491538222649405857429891037181044106595244065366002533271805
Short name T26
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:36:51 PM PST 23
Finished Nov 22 01:36:55 PM PST 23
Peak memory 205768 kb
Host smart-399237ca-5879-43af-a3f2-0dd6ecbee00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36239129178601723491538222649405857429891037181044106595244065366002533271805 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 295.edn_genbits.36239129178601723491538222649405857429891037181044106595244065366002533271805
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.87262507559246705323396655149083313818728160426989806809086572377620892662439
Short name T683
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 22 01:36:49 PM PST 23
Finished Nov 22 01:36:52 PM PST 23
Peak memory 205252 kb
Host smart-680036f7-f8f0-43e2-9183-83b2447d8923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87262507559246705323396655149083313818728160426989806809086572377620892662439 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 296.edn_genbits.87262507559246705323396655149083313818728160426989806809086572377620892662439
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.37486696653399883780541882175314066416771499804904371825504360373232513665736
Short name T387
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 22 01:36:50 PM PST 23
Finished Nov 22 01:36:54 PM PST 23
Peak memory 205820 kb
Host smart-2eda73a1-2903-4c42-a6b6-085358f072b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37486696653399883780541882175314066416771499804904371825504360373232513665736 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 297.edn_genbits.37486696653399883780541882175314066416771499804904371825504360373232513665736
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.23390707521385476424068884686163550901736024638387891083403954236859062564850
Short name T640
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:36:52 PM PST 23
Finished Nov 22 01:36:58 PM PST 23
Peak memory 205844 kb
Host smart-61ce0a20-d9c5-4b0e-9901-4aecbaca9666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23390707521385476424068884686163550901736024638387891083403954236859062564850 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 298.edn_genbits.23390707521385476424068884686163550901736024638387891083403954236859062564850
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.110800657238460426230132362309499281574874626495618417155458743011542468835103
Short name T873
Test name
Test status
Simulation time 17999183 ps
CPU time 1.19 seconds
Started Nov 22 01:36:51 PM PST 23
Finished Nov 22 01:36:55 PM PST 23
Peak memory 205944 kb
Host smart-9522519c-d612-4f93-b1c7-99be46631ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110800657238460426230132362309499281574874626495618417155458743011542468835103 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 299.edn_genbits.110800657238460426230132362309499281574874626495618417155458743011542468835103
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.31937946793702161971741466456375089307794653943640197408082613287364463129197
Short name T972
Test name
Test status
Simulation time 18259183 ps
CPU time 0.96 seconds
Started Nov 22 01:31:34 PM PST 23
Finished Nov 22 01:31:37 PM PST 23
Peak memory 205600 kb
Host smart-ac71844e-ce14-4dea-b6ee-7e2d4183b51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31937946793702161971741466456375089307794653943640197408082613287364463129197 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.edn_alert.31937946793702161971741466456375089307794653943640197408082613287364463129197
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.56513895266869503293662376616278927717234443140788279778967838346822550967013
Short name T599
Test name
Test status
Simulation time 28184990 ps
CPU time 0.87 seconds
Started Nov 22 01:31:50 PM PST 23
Finished Nov 22 01:31:52 PM PST 23
Peak memory 205472 kb
Host smart-8a410295-7b29-409d-8e69-0248ac3bf58f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56513895266869503293662376616278927717234443140788279778967838346822550967013 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.edn_alert_test.56513895266869503293662376616278927717234443140788279778967838346822550967013
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.100683239972750815934102205002201314341403163593894692925988240398049262456858
Short name T427
Test name
Test status
Simulation time 12219183 ps
CPU time 0.87 seconds
Started Nov 22 01:31:39 PM PST 23
Finished Nov 22 01:31:41 PM PST 23
Peak memory 214820 kb
Host smart-df4a5471-a2ba-464e-b369-674f58580558
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100683239972750815934102205002201314341403163593894692925988240398049262456858 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 3.edn_disable.100683239972750815934102205002201314341403163593894692925988240398049262456858
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.18448247297533218395338352089154586320236269097701462877724480823706546941654
Short name T60
Test name
Test status
Simulation time 14969183 ps
CPU time 0.91 seconds
Started Nov 22 01:31:52 PM PST 23
Finished Nov 22 01:31:54 PM PST 23
Peak memory 214904 kb
Host smart-e67673b4-4bdf-4f30-9032-b895aa2d94fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18448247297533218395338352089154586320236269097701462877724480823706546941654 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable_auto_req_mode.18448247297533218395338352089154586320236269097701462877724
480823706546941654
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.91183658214206741469011672979783816117069106367767521545051684176117832716681
Short name T378
Test name
Test status
Simulation time 24963823 ps
CPU time 1.14 seconds
Started Nov 22 01:31:38 PM PST 23
Finished Nov 22 01:31:40 PM PST 23
Peak memory 230468 kb
Host smart-8e152a6e-1950-4719-81e8-941c4a3976e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91183658214206741469011672979783816117069106367767521545051684176117832716681 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
edn_err.91183658214206741469011672979783816117069106367767521545051684176117832716681
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.60620909015742783569083803072182469487034261999464020940788578080555767020854
Short name T925
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Nov 22 01:31:36 PM PST 23
Finished Nov 22 01:31:39 PM PST 23
Peak memory 205832 kb
Host smart-baa58e91-9bc8-489e-9970-e7d3b12147d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60620909015742783569083803072182469487034261999464020940788578080555767020854 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.edn_genbits.60620909015742783569083803072182469487034261999464020940788578080555767020854
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.60524983298025368672384118927255061374884893856050999412328646111956699130684
Short name T634
Test name
Test status
Simulation time 18439183 ps
CPU time 1.08 seconds
Started Nov 22 01:31:34 PM PST 23
Finished Nov 22 01:31:38 PM PST 23
Peak memory 222140 kb
Host smart-0131bbc7-3ab7-4a16-b6bc-871050f237a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60524983298025368672384118927255061374884893856050999412328646111956699130684 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.edn_intr.60524983298025368672384118927255061374884893856050999412328646111956699130684
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.103672253364493890865903254215201711461574740003883474785743962123783288225281
Short name T910
Test name
Test status
Simulation time 11759183 ps
CPU time 0.86 seconds
Started Nov 22 01:31:35 PM PST 23
Finished Nov 22 01:31:38 PM PST 23
Peak memory 205304 kb
Host smart-0513223d-41bd-4251-9511-1e984cf98996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103672253364493890865903254215201711461574740003883474785743962123783288225281 -assert nopostproc +UVM_TESTNAME=edn_smok
e_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 3.edn_regwen.103672253364493890865903254215201711461574740003883474785743962123783288225281
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.108293498339005096867142183960616463971185308991351008550784039847537352524870
Short name T52
Test name
Test status
Simulation time 717215632 ps
CPU time 5.84 seconds
Started Nov 22 01:31:51 PM PST 23
Finished Nov 22 01:31:58 PM PST 23
Peak memory 234044 kb
Host smart-1a653409-9495-44e3-94b9-e5a217b65834
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108293498339005096867142183960616463971185308991351008550784039847537352524870 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.edn_sec_cm.108293498339005096867142183960616463971185308991351008550784039847537352524870
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.26247564504057213354124020754694210940869326878265124645991459162248985875062
Short name T877
Test name
Test status
Simulation time 13059183 ps
CPU time 0.85 seconds
Started Nov 22 01:31:35 PM PST 23
Finished Nov 22 01:31:38 PM PST 23
Peak memory 205264 kb
Host smart-fd75ac9b-3b45-4875-9a58-7a106bddaf46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26247564504057213354124020754694210940869326878265124645991459162248985875062 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.edn_smoke.26247564504057213354124020754694210940869326878265124645991459162248985875062
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.9196075257078170017497938566819805517241976677095109614959327765867558364504
Short name T570
Test name
Test status
Simulation time 154489183 ps
CPU time 3.91 seconds
Started Nov 22 01:31:38 PM PST 23
Finished Nov 22 01:31:43 PM PST 23
Peak memory 206320 kb
Host smart-ef030419-99b2-4278-89b9-9adc17ffd189
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9196075257078170017497938566819805517241976677095109614959327765867558364504 -assert nopost
proc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.9196075257078170017497938566819805517241976677095109614959327765867558364504
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.24529717816509555722227404282331629458380280324592389748409069382230093521629
Short name T935
Test name
Test status
Simulation time 41708099183 ps
CPU time 1081.17 seconds
Started Nov 22 01:31:36 PM PST 23
Finished Nov 22 01:49:39 PM PST 23
Peak memory 215768 kb
Host smart-ecf3cbea-8cf2-43c9-94bb-6133b9cba927
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245297178165095557222274042
82331629458380280324592389748409069382230093521629 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.245297178165
09555722227404282331629458380280324592389748409069382230093521629
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.27282232305335302468013489282305244568461485459708050249478244865421418403024
Short name T668
Test name
Test status
Simulation time 18259183 ps
CPU time 1.03 seconds
Started Nov 22 01:34:41 PM PST 23
Finished Nov 22 01:34:43 PM PST 23
Peak memory 205592 kb
Host smart-590e8a2a-dd44-49b4-85fd-3803ec48f105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27282232305335302468013489282305244568461485459708050249478244865421418403024 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 30.edn_alert.27282232305335302468013489282305244568461485459708050249478244865421418403024
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.38199507839666224102335951020792503838555474991462887984346710594975624016786
Short name T256
Test name
Test status
Simulation time 28184990 ps
CPU time 0.84 seconds
Started Nov 22 01:34:39 PM PST 23
Finished Nov 22 01:34:40 PM PST 23
Peak memory 205376 kb
Host smart-4cdc71f7-d219-4aea-a084-6dcd941f4115
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38199507839666224102335951020792503838555474991462887984346710594975624016786 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.edn_alert_test.38199507839666224102335951020792503838555474991462887984346710594975624016786
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.67032814499138198037973278510637611529208159137756321268761762639385071462151
Short name T657
Test name
Test status
Simulation time 12219183 ps
CPU time 0.85 seconds
Started Nov 22 01:34:28 PM PST 23
Finished Nov 22 01:34:29 PM PST 23
Peak memory 214908 kb
Host smart-1edde15d-d30f-4e25-9152-f5d72a20e93c
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67032814499138198037973278510637611529208159137756321268761762639385071462151 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.edn_disable.67032814499138198037973278510637611529208159137756321268761762639385071462151
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.12792687789761698027095727221300870850261741836611646473395572936639897694067
Short name T644
Test name
Test status
Simulation time 14969183 ps
CPU time 0.89 seconds
Started Nov 22 01:34:42 PM PST 23
Finished Nov 22 01:34:44 PM PST 23
Peak memory 214788 kb
Host smart-28f705b5-36c8-4cdd-aa28-a976fb4a1db9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12792687789761698027095727221300870850261741836611646473395572936639897694067 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable_auto_req_mode.1279268778976169802709572722130087085026174183661164647339
5572936639897694067
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.43427931556946345198131038363174163174376700068423946108111410728240307179469
Short name T921
Test name
Test status
Simulation time 24963823 ps
CPU time 1.12 seconds
Started Nov 22 01:34:40 PM PST 23
Finished Nov 22 01:34:42 PM PST 23
Peak memory 230352 kb
Host smart-6b16626f-56f9-421b-8bd2-31c948082147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43427931556946345198131038363174163174376700068423946108111410728240307179469 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.edn_err.43427931556946345198131038363174163174376700068423946108111410728240307179469
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.100052056432581057985730450475502006562578746783441233372283658129355366997957
Short name T538
Test name
Test status
Simulation time 17999183 ps
CPU time 1.06 seconds
Started Nov 22 01:34:39 PM PST 23
Finished Nov 22 01:34:41 PM PST 23
Peak memory 205740 kb
Host smart-86ba34e3-1e20-42bb-8f59-08d1a72d1045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100052056432581057985730450475502006562578746783441233372283658129355366997957 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 30.edn_genbits.100052056432581057985730450475502006562578746783441233372283658129355366997957
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.10873949276343988899322880026912901573767335163958532187102625531734523782156
Short name T549
Test name
Test status
Simulation time 18439183 ps
CPU time 1.14 seconds
Started Nov 22 01:34:33 PM PST 23
Finished Nov 22 01:34:35 PM PST 23
Peak memory 222280 kb
Host smart-68166543-7cda-485d-802f-4c69180c0416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10873949276343988899322880026912901573767335163958532187102625531734523782156 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.edn_intr.10873949276343988899322880026912901573767335163958532187102625531734523782156
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.96786634247021632580289598010241610922293832603535595124007472378551677947200
Short name T727
Test name
Test status
Simulation time 13059183 ps
CPU time 0.94 seconds
Started Nov 22 01:34:41 PM PST 23
Finished Nov 22 01:34:43 PM PST 23
Peak memory 205408 kb
Host smart-300c7ec5-61bb-4a65-aecd-59d8bfd37997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96786634247021632580289598010241610922293832603535595124007472378551677947200 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 30.edn_smoke.96786634247021632580289598010241610922293832603535595124007472378551677947200
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.89113074675042601139503884960578005494215478298511902962170136374854721149540
Short name T407
Test name
Test status
Simulation time 154489183 ps
CPU time 4.03 seconds
Started Nov 22 01:34:40 PM PST 23
Finished Nov 22 01:34:45 PM PST 23
Peak memory 206392 kb
Host smart-8f8fbded-129b-45a4-b845-923bb0a9a416
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89113074675042601139503884960578005494215478298511902962170136374854721149540 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.89113074675042601139503884960578005494215478298511902962170136374854721149540
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.41716412130212418388358778818549738540854298999827363920234216669320041032258
Short name T635
Test name
Test status
Simulation time 41708099183 ps
CPU time 1034.69 seconds
Started Nov 22 01:34:38 PM PST 23
Finished Nov 22 01:51:53 PM PST 23
Peak memory 215756 kb
Host smart-8c26ec74-ff54-4367-8b52-8a00b1b96f09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417164121302124183883587788
18549738540854298999827363920234216669320041032258 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.41716412130
212418388358778818549738540854298999827363920234216669320041032258
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.83366498817632065717898664001537249899924557274649042279664749325298093687459
Short name T41
Test name
Test status
Simulation time 18259183 ps
CPU time 1.02 seconds
Started Nov 22 01:35:03 PM PST 23
Finished Nov 22 01:35:05 PM PST 23
Peak memory 205572 kb
Host smart-a2190cc4-cf47-4492-8914-29545f41a564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83366498817632065717898664001537249899924557274649042279664749325298093687459 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 31.edn_alert.83366498817632065717898664001537249899924557274649042279664749325298093687459
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.84688719241730065436189547043422933623510815671981576612629049530135720784209
Short name T858
Test name
Test status
Simulation time 28184990 ps
CPU time 0.88 seconds
Started Nov 22 01:34:52 PM PST 23
Finished Nov 22 01:34:54 PM PST 23
Peak memory 205436 kb
Host smart-b9276d06-2830-47e9-9141-269a276c2777
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84688719241730065436189547043422933623510815671981576612629049530135720784209 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.edn_alert_test.84688719241730065436189547043422933623510815671981576612629049530135720784209
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.44472322855270708938184202155132062148850127169152498376846950863355203310338
Short name T546
Test name
Test status
Simulation time 12219183 ps
CPU time 0.88 seconds
Started Nov 22 01:34:51 PM PST 23
Finished Nov 22 01:34:53 PM PST 23
Peak memory 214860 kb
Host smart-052ff59e-a2f9-4d74-9225-5db9ae77fca4
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44472322855270708938184202155132062148850127169152498376846950863355203310338 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.edn_disable.44472322855270708938184202155132062148850127169152498376846950863355203310338
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.115182637492966133228635509341845291979856968966200194743064660903557095780898
Short name T488
Test name
Test status
Simulation time 14969183 ps
CPU time 0.92 seconds
Started Nov 22 01:35:04 PM PST 23
Finished Nov 22 01:35:07 PM PST 23
Peak memory 214784 kb
Host smart-78d5e47d-7fdb-49b0-9389-3c2bcfc0784f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115182637492966133228635509341845291979856968966200194743064660903557095780898 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable_auto_req_mode.115182637492966133228635509341845291979856968966200194743
064660903557095780898
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.113549904130028356294992778078944922967326520443069779371433042957048768129078
Short name T749
Test name
Test status
Simulation time 24963823 ps
CPU time 1.13 seconds
Started Nov 22 01:34:49 PM PST 23
Finished Nov 22 01:34:51 PM PST 23
Peak memory 230412 kb
Host smart-813b28f6-bd84-4759-9962-d2d9ae883e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113549904130028356294992778078944922967326520443069779371433042957048768129078 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.edn_err.113549904130028356294992778078944922967326520443069779371433042957048768129078
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.16816807065591516820522866820791630798857751283433499128714609799211669821924
Short name T736
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:34:29 PM PST 23
Finished Nov 22 01:34:31 PM PST 23
Peak memory 205856 kb
Host smart-d670b8f3-f0f4-4de9-8b33-10e94ccf2a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16816807065591516820522866820791630798857751283433499128714609799211669821924 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.edn_genbits.16816807065591516820522866820791630798857751283433499128714609799211669821924
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.39101079541592030577271235559038829033253402853031338176919981558939311872786
Short name T374
Test name
Test status
Simulation time 18439183 ps
CPU time 1.12 seconds
Started Nov 22 01:34:51 PM PST 23
Finished Nov 22 01:34:53 PM PST 23
Peak memory 222256 kb
Host smart-2a9f5336-62cb-4ac4-8e88-6726b4534137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39101079541592030577271235559038829033253402853031338176919981558939311872786 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.edn_intr.39101079541592030577271235559038829033253402853031338176919981558939311872786
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.80864036806150975400733447127294567524172308680600127337269749689255769578143
Short name T621
Test name
Test status
Simulation time 13059183 ps
CPU time 0.87 seconds
Started Nov 22 01:34:34 PM PST 23
Finished Nov 22 01:34:36 PM PST 23
Peak memory 205344 kb
Host smart-0b4226ca-8545-497c-874f-4b9936a649cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80864036806150975400733447127294567524172308680600127337269749689255769578143 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 31.edn_smoke.80864036806150975400733447127294567524172308680600127337269749689255769578143
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.16130666722706320527289281529906830471901677118387377014869414617196460541107
Short name T716
Test name
Test status
Simulation time 154489183 ps
CPU time 3.96 seconds
Started Nov 22 01:34:39 PM PST 23
Finished Nov 22 01:34:44 PM PST 23
Peak memory 206332 kb
Host smart-b5933e8a-34fc-4b51-a6c5-4ff9aecf617c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16130666722706320527289281529906830471901677118387377014869414617196460541107 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.16130666722706320527289281529906830471901677118387377014869414617196460541107
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.110512926889860713095148043354197937728005199936735658717533328197629120450741
Short name T777
Test name
Test status
Simulation time 41708099183 ps
CPU time 1040.27 seconds
Started Nov 22 01:34:40 PM PST 23
Finished Nov 22 01:52:01 PM PST 23
Peak memory 215804 kb
Host smart-c557603c-48b2-4aa6-aadf-03778da87298
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110512926889860713095148043
354197937728005199936735658717533328197629120450741 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.1105129268
89860713095148043354197937728005199936735658717533328197629120450741
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.63795241510498380952596316191575278694410637690965387196928573107562031278364
Short name T342
Test name
Test status
Simulation time 18259183 ps
CPU time 1.01 seconds
Started Nov 22 01:34:51 PM PST 23
Finished Nov 22 01:34:53 PM PST 23
Peak memory 205584 kb
Host smart-4f9657c7-17b3-4fc8-81d0-745a1595fe6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63795241510498380952596316191575278694410637690965387196928573107562031278364 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 32.edn_alert.63795241510498380952596316191575278694410637690965387196928573107562031278364
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.69706687052583564835138710679438680083917985099369614201286095890480928818270
Short name T345
Test name
Test status
Simulation time 28184990 ps
CPU time 0.89 seconds
Started Nov 22 01:34:51 PM PST 23
Finished Nov 22 01:34:53 PM PST 23
Peak memory 205536 kb
Host smart-ca860dbb-b016-446e-b83f-6c5d766e7aaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69706687052583564835138710679438680083917985099369614201286095890480928818270 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.edn_alert_test.69706687052583564835138710679438680083917985099369614201286095890480928818270
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.76346047728489300863865054560644067807152564427191661390965756789690272768848
Short name T816
Test name
Test status
Simulation time 12219183 ps
CPU time 0.91 seconds
Started Nov 22 01:35:03 PM PST 23
Finished Nov 22 01:35:06 PM PST 23
Peak memory 214896 kb
Host smart-41b25b4b-5596-442c-a1af-e36bb6385fac
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76346047728489300863865054560644067807152564427191661390965756789690272768848 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.edn_disable.76346047728489300863865054560644067807152564427191661390965756789690272768848
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.15469092982347560018361958907430062694573758032447008116345668615251049474755
Short name T936
Test name
Test status
Simulation time 14969183 ps
CPU time 0.9 seconds
Started Nov 22 01:34:51 PM PST 23
Finished Nov 22 01:34:52 PM PST 23
Peak memory 214828 kb
Host smart-c8f5d79d-a8b6-49fb-8f40-788130c676c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15469092982347560018361958907430062694573758032447008116345668615251049474755 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable_auto_req_mode.1546909298234756001836195890743006269457375803244700811634
5668615251049474755
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.14447303031200377463981442786244292379624992752297031195928743394481476344361
Short name T891
Test name
Test status
Simulation time 24963823 ps
CPU time 1.14 seconds
Started Nov 22 01:35:04 PM PST 23
Finished Nov 22 01:35:07 PM PST 23
Peak memory 230456 kb
Host smart-de267a4e-dff5-4e17-bbf1-d818fec2909f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14447303031200377463981442786244292379624992752297031195928743394481476344361 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.edn_err.14447303031200377463981442786244292379624992752297031195928743394481476344361
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.71903763549288192028615380262654538008650715215854800129950710191373375492055
Short name T880
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 22 01:35:04 PM PST 23
Finished Nov 22 01:35:07 PM PST 23
Peak memory 205856 kb
Host smart-c41bda92-1f60-41f6-9ac3-800573a2075f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71903763549288192028615380262654538008650715215854800129950710191373375492055 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.edn_genbits.71903763549288192028615380262654538008650715215854800129950710191373375492055
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.37049973248706095676246037818189227219774154969290653005419123459942106956123
Short name T448
Test name
Test status
Simulation time 18439183 ps
CPU time 1.15 seconds
Started Nov 22 01:34:54 PM PST 23
Finished Nov 22 01:34:56 PM PST 23
Peak memory 222240 kb
Host smart-182f3acf-ef4a-4f56-b71a-27b41318b65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37049973248706095676246037818189227219774154969290653005419123459942106956123 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.edn_intr.37049973248706095676246037818189227219774154969290653005419123459942106956123
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.115007268989377899695430440517727404158737463265247987870558583732994199277091
Short name T447
Test name
Test status
Simulation time 13059183 ps
CPU time 0.88 seconds
Started Nov 22 01:34:50 PM PST 23
Finished Nov 22 01:34:51 PM PST 23
Peak memory 205216 kb
Host smart-fc513a2c-1092-4bd2-b675-9fd208aad531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115007268989377899695430440517727404158737463265247987870558583732994199277091 -assert nopostproc +UVM_TESTNAME=edn_smok
e_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 32.edn_smoke.115007268989377899695430440517727404158737463265247987870558583732994199277091
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.22558309356916994014433174497182762555904149888509812812067637314619976663546
Short name T853
Test name
Test status
Simulation time 154489183 ps
CPU time 3.85 seconds
Started Nov 22 01:35:03 PM PST 23
Finished Nov 22 01:35:09 PM PST 23
Peak memory 206396 kb
Host smart-519f9429-0a99-4a3c-b562-7a4b16a162ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22558309356916994014433174497182762555904149888509812812067637314619976663546 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.22558309356916994014433174497182762555904149888509812812067637314619976663546
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.21052262991248046901956369815309984289832626990574304876116341012087157844351
Short name T471
Test name
Test status
Simulation time 41708099183 ps
CPU time 1100.51 seconds
Started Nov 22 01:35:04 PM PST 23
Finished Nov 22 01:53:27 PM PST 23
Peak memory 215860 kb
Host smart-6aca88c4-b17a-49f2-abca-997a5038bd1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210522629912480469019563698
15309984289832626990574304876116341012087157844351 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.21052262991
248046901956369815309984289832626990574304876116341012087157844351
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.40998451528685846117361407454351926026396374836589601248511996479104503465589
Short name T335
Test name
Test status
Simulation time 18259183 ps
CPU time 0.98 seconds
Started Nov 22 01:34:50 PM PST 23
Finished Nov 22 01:34:52 PM PST 23
Peak memory 205416 kb
Host smart-28f16cce-6fd7-44bd-8393-71ebf3a0ee49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40998451528685846117361407454351926026396374836589601248511996479104503465589 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 33.edn_alert.40998451528685846117361407454351926026396374836589601248511996479104503465589
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.83754676255865846370971907514104490941014344909153466271261209240055104534772
Short name T47
Test name
Test status
Simulation time 28184990 ps
CPU time 0.88 seconds
Started Nov 22 01:35:07 PM PST 23
Finished Nov 22 01:35:15 PM PST 23
Peak memory 205484 kb
Host smart-258ca75e-670d-41d4-9c21-164a95840719
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83754676255865846370971907514104490941014344909153466271261209240055104534772 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.edn_alert_test.83754676255865846370971907514104490941014344909153466271261209240055104534772
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.86595462305216967197019733068359592976789675354399364349787738316344124803021
Short name T332
Test name
Test status
Simulation time 12219183 ps
CPU time 0.87 seconds
Started Nov 22 01:35:05 PM PST 23
Finished Nov 22 01:35:10 PM PST 23
Peak memory 214792 kb
Host smart-334c2266-8dcd-4707-8f91-3977dee21357
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86595462305216967197019733068359592976789675354399364349787738316344124803021 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.edn_disable.86595462305216967197019733068359592976789675354399364349787738316344124803021
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.90318518499410494630074143173173260382355281597767312063681616697816250544435
Short name T919
Test name
Test status
Simulation time 14969183 ps
CPU time 0.87 seconds
Started Nov 22 01:35:06 PM PST 23
Finished Nov 22 01:35:13 PM PST 23
Peak memory 214804 kb
Host smart-02c9482d-b61e-457e-8a35-a40a2c8006d2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90318518499410494630074143173173260382355281597767312063681616697816250544435 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable_auto_req_mode.9031851849941049463007414317317326038235528159776731206368
1616697816250544435
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.18229687962991724675689778638324203387348259789214718136280765960515964900677
Short name T527
Test name
Test status
Simulation time 24963823 ps
CPU time 1.13 seconds
Started Nov 22 01:35:05 PM PST 23
Finished Nov 22 01:35:13 PM PST 23
Peak memory 230504 kb
Host smart-05860d27-40e4-4e27-9f4b-e27b96565283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18229687962991724675689778638324203387348259789214718136280765960515964900677 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.edn_err.18229687962991724675689778638324203387348259789214718136280765960515964900677
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.67630711094540111234469592523460239711246797830167045370826354990542595984627
Short name T73
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Nov 22 01:35:04 PM PST 23
Finished Nov 22 01:35:07 PM PST 23
Peak memory 205848 kb
Host smart-b025ae94-029a-4e83-a09d-68f0cb9382b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67630711094540111234469592523460239711246797830167045370826354990542595984627 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.edn_genbits.67630711094540111234469592523460239711246797830167045370826354990542595984627
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.621929062812074641376043210375495443999487436760977695230182368980953689333
Short name T941
Test name
Test status
Simulation time 18439183 ps
CPU time 1.12 seconds
Started Nov 22 01:34:50 PM PST 23
Finished Nov 22 01:34:52 PM PST 23
Peak memory 222288 kb
Host smart-b3ebd231-40fb-4192-bbb0-a653592e92cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621929062812074641376043210375495443999487436760977695230182368980953689333 -assert nopostproc +UVM_TESTNAME=edn_intr_te
st +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.edn_intr.621929062812074641376043210375495443999487436760977695230182368980953689333
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.112122734569623345776262260680357935552817568280735762751818503236939937258135
Short name T872
Test name
Test status
Simulation time 13059183 ps
CPU time 0.87 seconds
Started Nov 22 01:34:51 PM PST 23
Finished Nov 22 01:34:53 PM PST 23
Peak memory 205244 kb
Host smart-9445a003-130d-4a33-ad62-219ba7501bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112122734569623345776262260680357935552817568280735762751818503236939937258135 -assert nopostproc +UVM_TESTNAME=edn_smok
e_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.edn_smoke.112122734569623345776262260680357935552817568280735762751818503236939937258135
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.81973293846032584052595431773254570114794949345393847316688415015100621431891
Short name T485
Test name
Test status
Simulation time 154489183 ps
CPU time 4.08 seconds
Started Nov 22 01:34:50 PM PST 23
Finished Nov 22 01:34:55 PM PST 23
Peak memory 206360 kb
Host smart-45c6f4cb-f2f9-49ab-ab81-14cd2d2aa9f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81973293846032584052595431773254570114794949345393847316688415015100621431891 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.81973293846032584052595431773254570114794949345393847316688415015100621431891
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.7703704364851810820391524522163406052317228591417967140066448523299229796290
Short name T962
Test name
Test status
Simulation time 41708099183 ps
CPU time 1089.37 seconds
Started Nov 22 01:35:03 PM PST 23
Finished Nov 22 01:53:15 PM PST 23
Peak memory 215796 kb
Host smart-e7d744db-4e16-4c07-9517-08449ebb75b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770370436485181082039152452
2163406052317228591417967140066448523299229796290 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.770370436485
1810820391524522163406052317228591417967140066448523299229796290
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.38363116779267598167809834707924723420734520458109968264496989678879836787558
Short name T796
Test name
Test status
Simulation time 18259183 ps
CPU time 0.99 seconds
Started Nov 22 01:35:10 PM PST 23
Finished Nov 22 01:35:15 PM PST 23
Peak memory 205492 kb
Host smart-4e57ef11-c0db-4fa3-af95-b8255689db88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38363116779267598167809834707924723420734520458109968264496989678879836787558 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 34.edn_alert.38363116779267598167809834707924723420734520458109968264496989678879836787558
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.110623145414999275300458906968434578600234360426451788314245892291404326492517
Short name T673
Test name
Test status
Simulation time 28184990 ps
CPU time 0.89 seconds
Started Nov 22 01:35:22 PM PST 23
Finished Nov 22 01:35:24 PM PST 23
Peak memory 205404 kb
Host smart-b23f7919-7f7b-4b1d-860a-6b854de2fc8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110623145414999275300458906968434578600234360426451788314245892291404326492517 -assert nopostp
roc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 34.edn_alert_test.110623145414999275300458906968434578600234360426451788314245892291404326492517
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.56381032797051520592639087612720115377835930308474432515570289767965513317653
Short name T682
Test name
Test status
Simulation time 12219183 ps
CPU time 0.85 seconds
Started Nov 22 01:35:10 PM PST 23
Finished Nov 22 01:35:15 PM PST 23
Peak memory 214876 kb
Host smart-cc53eb14-46e2-43e5-8aae-ce926cdfac1d
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56381032797051520592639087612720115377835930308474432515570289767965513317653 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.edn_disable.56381032797051520592639087612720115377835930308474432515570289767965513317653
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.8219607942557352480008342100058247280773914942032726979758564793338885363522
Short name T346
Test name
Test status
Simulation time 14969183 ps
CPU time 0.93 seconds
Started Nov 22 01:35:20 PM PST 23
Finished Nov 22 01:35:22 PM PST 23
Peak memory 214880 kb
Host smart-a3ac0770-3a72-477a-b1ed-f35871860b8d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8219607942557352480008342100058247280773914942032726979758564793338885363522 -assert nopostproc
+UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable_auto_req_mode.82196079425573524800083421000582472807739149420327269797585
64793338885363522
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.31198929897914194034349563567308339660697781260329703836454541672000801737259
Short name T687
Test name
Test status
Simulation time 24963823 ps
CPU time 1.19 seconds
Started Nov 22 01:35:20 PM PST 23
Finished Nov 22 01:35:22 PM PST 23
Peak memory 230404 kb
Host smart-3db7a18a-f089-4795-be6b-7263f1484fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31198929897914194034349563567308339660697781260329703836454541672000801737259 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.edn_err.31198929897914194034349563567308339660697781260329703836454541672000801737259
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.59422709210286357414100611544861583480693759106425209316012449784110750908933
Short name T395
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 22 01:35:09 PM PST 23
Finished Nov 22 01:35:15 PM PST 23
Peak memory 205792 kb
Host smart-5877542d-f9c9-4c34-b636-7db7c3d64f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59422709210286357414100611544861583480693759106425209316012449784110750908933 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.edn_genbits.59422709210286357414100611544861583480693759106425209316012449784110750908933
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.111672240925329021026087164932142845043685249132802819563634323430509310282878
Short name T500
Test name
Test status
Simulation time 18439183 ps
CPU time 1.15 seconds
Started Nov 22 01:35:05 PM PST 23
Finished Nov 22 01:35:12 PM PST 23
Peak memory 222188 kb
Host smart-648430c7-5fb7-4ad3-8e2c-e5254c2e3573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111672240925329021026087164932142845043685249132802819563634323430509310282878 -assert nopostproc +UVM_TESTNAME=edn_intr
_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.edn_intr.111672240925329021026087164932142845043685249132802819563634323430509310282878
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.30291034189857558450047603000052842392362998977672775507635497451532919118215
Short name T333
Test name
Test status
Simulation time 13059183 ps
CPU time 0.93 seconds
Started Nov 22 01:35:07 PM PST 23
Finished Nov 22 01:35:15 PM PST 23
Peak memory 205332 kb
Host smart-2a2f9d7e-a852-464d-8041-1b611c208210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30291034189857558450047603000052842392362998977672775507635497451532919118215 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 34.edn_smoke.30291034189857558450047603000052842392362998977672775507635497451532919118215
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.100834883429392486700026450226160352088638492346372677863504810554101589017897
Short name T729
Test name
Test status
Simulation time 154489183 ps
CPU time 3.98 seconds
Started Nov 22 01:35:09 PM PST 23
Finished Nov 22 01:35:18 PM PST 23
Peak memory 206268 kb
Host smart-2941e55d-935d-4b25-9b6c-2fee09e23b0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100834883429392486700026450226160352088638492346372677863504810554101589017897 -assert nopo
stproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.100834883429392486700026450226160352088638492346372677863504810554101589017897
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.113286081488614882941953131009173233867261379879866302079951593641480767609994
Short name T664
Test name
Test status
Simulation time 41708099183 ps
CPU time 1071.12 seconds
Started Nov 22 01:35:10 PM PST 23
Finished Nov 22 01:53:06 PM PST 23
Peak memory 215784 kb
Host smart-30a994d7-d5e3-401c-8a01-80f11dcc3032
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113286081488614882941953131
009173233867261379879866302079951593641480767609994 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.1132860814
88614882941953131009173233867261379879866302079951593641480767609994
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.87390380816720829256613457672643280942324925701018231736730672602490218171029
Short name T700
Test name
Test status
Simulation time 18259183 ps
CPU time 0.99 seconds
Started Nov 22 01:35:11 PM PST 23
Finished Nov 22 01:35:16 PM PST 23
Peak memory 205448 kb
Host smart-8c5301fd-4169-49fa-b1af-fac0bd836a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87390380816720829256613457672643280942324925701018231736730672602490218171029 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 35.edn_alert.87390380816720829256613457672643280942324925701018231736730672602490218171029
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.68058101657540465025682886065850973256929992466951424266772761868667279322508
Short name T958
Test name
Test status
Simulation time 28184990 ps
CPU time 0.9 seconds
Started Nov 22 01:35:07 PM PST 23
Finished Nov 22 01:35:15 PM PST 23
Peak memory 205520 kb
Host smart-60199272-7ffe-4335-a248-475f833b59e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68058101657540465025682886065850973256929992466951424266772761868667279322508 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.edn_alert_test.68058101657540465025682886065850973256929992466951424266772761868667279322508
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.99959996207156157323580646431436495074101616515309337331555916603586161525108
Short name T588
Test name
Test status
Simulation time 12219183 ps
CPU time 0.89 seconds
Started Nov 22 01:35:08 PM PST 23
Finished Nov 22 01:35:15 PM PST 23
Peak memory 214816 kb
Host smart-a2fe8db2-2218-4719-a113-40f1bd5329a8
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99959996207156157323580646431436495074101616515309337331555916603586161525108 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.edn_disable.99959996207156157323580646431436495074101616515309337331555916603586161525108
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.34245990465628448700508015355983738432170003248533970050448146457295434943864
Short name T409
Test name
Test status
Simulation time 14969183 ps
CPU time 0.91 seconds
Started Nov 22 01:35:08 PM PST 23
Finished Nov 22 01:35:15 PM PST 23
Peak memory 214824 kb
Host smart-87bf38ba-1f9c-4eda-b78b-d31487698138
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34245990465628448700508015355983738432170003248533970050448146457295434943864 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable_auto_req_mode.3424599046562844870050801535598373843217000324853397005044
8146457295434943864
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.56282859106170547241993619366663897191539577611797288929527705996018380266052
Short name T440
Test name
Test status
Simulation time 24963823 ps
CPU time 1.16 seconds
Started Nov 22 01:35:11 PM PST 23
Finished Nov 22 01:35:16 PM PST 23
Peak memory 230332 kb
Host smart-5558b6f4-5e14-4738-80f8-dbae406cd62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56282859106170547241993619366663897191539577611797288929527705996018380266052 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.edn_err.56282859106170547241993619366663897191539577611797288929527705996018380266052
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.3801187031405990592808318494433234139778166874450295698046004546885126139560
Short name T955
Test name
Test status
Simulation time 17999183 ps
CPU time 1.06 seconds
Started Nov 22 01:35:07 PM PST 23
Finished Nov 22 01:35:15 PM PST 23
Peak memory 205848 kb
Host smart-0533c39f-9e91-4e23-b20c-43ebc4ddc51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801187031405990592808318494433234139778166874450295698046004546885126139560 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.edn_genbits.3801187031405990592808318494433234139778166874450295698046004546885126139560
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.43601463268207400047209568887180015234774751666337533346345493888067484193353
Short name T882
Test name
Test status
Simulation time 18439183 ps
CPU time 1.08 seconds
Started Nov 22 01:35:03 PM PST 23
Finished Nov 22 01:35:07 PM PST 23
Peak memory 222264 kb
Host smart-3cafd58f-3c51-482d-b3b6-4daf77172ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43601463268207400047209568887180015234774751666337533346345493888067484193353 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.edn_intr.43601463268207400047209568887180015234774751666337533346345493888067484193353
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.42018263779914550908217479625994618253954007961425329530567238033955590135757
Short name T569
Test name
Test status
Simulation time 13059183 ps
CPU time 0.93 seconds
Started Nov 22 01:35:05 PM PST 23
Finished Nov 22 01:35:12 PM PST 23
Peak memory 205400 kb
Host smart-68a87ed5-efd4-43b8-aa8f-1900df6b4339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42018263779914550908217479625994618253954007961425329530567238033955590135757 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 35.edn_smoke.42018263779914550908217479625994618253954007961425329530567238033955590135757
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.37131769099107821721626158923618527280665714276679423393080091084585522081337
Short name T273
Test name
Test status
Simulation time 154489183 ps
CPU time 3.98 seconds
Started Nov 22 01:35:07 PM PST 23
Finished Nov 22 01:35:18 PM PST 23
Peak memory 206396 kb
Host smart-b4747f7d-a5d1-4b4a-abe9-8c36648f6cb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37131769099107821721626158923618527280665714276679423393080091084585522081337 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.37131769099107821721626158923618527280665714276679423393080091084585522081337
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.22442618951782557029875199219463556066053301951226446119612125024248281013445
Short name T318
Test name
Test status
Simulation time 41708099183 ps
CPU time 1038.07 seconds
Started Nov 22 01:35:05 PM PST 23
Finished Nov 22 01:52:29 PM PST 23
Peak memory 215768 kb
Host smart-154ecfc5-59b1-411d-9c59-999ecc67f8f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224426189517825570298751992
19463556066053301951226446119612125024248281013445 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.22442618951
782557029875199219463556066053301951226446119612125024248281013445
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.95392925824176564282757004400593158364100283266013368714379640208841343253966
Short name T629
Test name
Test status
Simulation time 18259183 ps
CPU time 1.04 seconds
Started Nov 22 01:35:03 PM PST 23
Finished Nov 22 01:35:06 PM PST 23
Peak memory 205536 kb
Host smart-55583bfe-78ef-48eb-b0c3-2d82232495f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95392925824176564282757004400593158364100283266013368714379640208841343253966 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 36.edn_alert.95392925824176564282757004400593158364100283266013368714379640208841343253966
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.39236519150043220054163328725755101526200223044246320972556602436838641071993
Short name T502
Test name
Test status
Simulation time 28184990 ps
CPU time 0.87 seconds
Started Nov 22 01:35:20 PM PST 23
Finished Nov 22 01:35:22 PM PST 23
Peak memory 205620 kb
Host smart-db44bab4-73f9-4a0d-ad98-fe2b9cd5af7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39236519150043220054163328725755101526200223044246320972556602436838641071993 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.edn_alert_test.39236519150043220054163328725755101526200223044246320972556602436838641071993
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.111890047693463871082732026573277527961179344321135162236422772994143061640288
Short name T403
Test name
Test status
Simulation time 12219183 ps
CPU time 0.88 seconds
Started Nov 22 01:35:06 PM PST 23
Finished Nov 22 01:35:14 PM PST 23
Peak memory 214884 kb
Host smart-e1561603-b0f9-418c-a8b1-400c1a4c2f3c
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111890047693463871082732026573277527961179344321135162236422772994143061640288 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 36.edn_disable.111890047693463871082732026573277527961179344321135162236422772994143061640288
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.4313549591241593046404764752239127237647212813140286310765170381318069447089
Short name T262
Test name
Test status
Simulation time 14969183 ps
CPU time 0.91 seconds
Started Nov 22 01:35:10 PM PST 23
Finished Nov 22 01:35:15 PM PST 23
Peak memory 214820 kb
Host smart-412389cc-c6cb-41c5-8a8c-8a87c5899252
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4313549591241593046404764752239127237647212813140286310765170381318069447089 -assert nopostproc
+UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable_auto_req_mode.43135495912415930464047647522391272376472128131402863107651
70381318069447089
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.39082782433358089587806465531220175183165602096663633250848093555400940764449
Short name T592
Test name
Test status
Simulation time 24963823 ps
CPU time 1.13 seconds
Started Nov 22 01:35:08 PM PST 23
Finished Nov 22 01:35:15 PM PST 23
Peak memory 230252 kb
Host smart-2f4d69aa-d926-4e5b-bb45-9961bc5aa61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39082782433358089587806465531220175183165602096663633250848093555400940764449 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.edn_err.39082782433358089587806465531220175183165602096663633250848093555400940764449
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.94442084291588420524584853452839297502841052531046468927946068170415079863850
Short name T968
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Nov 22 01:35:05 PM PST 23
Finished Nov 22 01:35:11 PM PST 23
Peak memory 205836 kb
Host smart-f663bd78-9ad5-49aa-8260-5fa4eaa407eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94442084291588420524584853452839297502841052531046468927946068170415079863850 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.edn_genbits.94442084291588420524584853452839297502841052531046468927946068170415079863850
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.56477610211763617375247280525934136404210719941070599068865894383319766572540
Short name T33
Test name
Test status
Simulation time 18439183 ps
CPU time 1.11 seconds
Started Nov 22 01:35:05 PM PST 23
Finished Nov 22 01:35:12 PM PST 23
Peak memory 222220 kb
Host smart-9b4f1b93-737f-46e9-b3c0-c691ace9175f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56477610211763617375247280525934136404210719941070599068865894383319766572540 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.edn_intr.56477610211763617375247280525934136404210719941070599068865894383319766572540
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.75339371096099311705314660948419080929010514646154454694157960312904595767302
Short name T533
Test name
Test status
Simulation time 13059183 ps
CPU time 0.9 seconds
Started Nov 22 01:35:05 PM PST 23
Finished Nov 22 01:35:12 PM PST 23
Peak memory 205380 kb
Host smart-76694420-4b8e-4e99-9cb0-236fb17e7720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75339371096099311705314660948419080929010514646154454694157960312904595767302 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 36.edn_smoke.75339371096099311705314660948419080929010514646154454694157960312904595767302
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.51497901313419068587579867330663626992571073550774450526900057806051321543810
Short name T487
Test name
Test status
Simulation time 154489183 ps
CPU time 4.13 seconds
Started Nov 22 01:35:08 PM PST 23
Finished Nov 22 01:35:18 PM PST 23
Peak memory 206304 kb
Host smart-4f2ffa47-24da-4cb0-a074-91e579cee6f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51497901313419068587579867330663626992571073550774450526900057806051321543810 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.51497901313419068587579867330663626992571073550774450526900057806051321543810
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.12923032248988443855791408720600364608452710849961797392141939493865404676192
Short name T681
Test name
Test status
Simulation time 41708099183 ps
CPU time 1080.66 seconds
Started Nov 22 01:35:10 PM PST 23
Finished Nov 22 01:53:15 PM PST 23
Peak memory 215848 kb
Host smart-e0e44aa2-6947-43bc-aac7-85772897dd21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129230322489884438557914087
20600364608452710849961797392141939493865404676192 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.12923032248
988443855791408720600364608452710849961797392141939493865404676192
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.48294318504095800512966025151869288346348426910920896460922592702163449330084
Short name T924
Test name
Test status
Simulation time 18259183 ps
CPU time 0.97 seconds
Started Nov 22 01:35:05 PM PST 23
Finished Nov 22 01:35:12 PM PST 23
Peak memory 205532 kb
Host smart-fd009557-affc-4efc-8d44-ebab4d3ef9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48294318504095800512966025151869288346348426910920896460922592702163449330084 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 37.edn_alert.48294318504095800512966025151869288346348426910920896460922592702163449330084
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.2652786837530694950326903273329705330031906079653909426103613041967835437317
Short name T48
Test name
Test status
Simulation time 28184990 ps
CPU time 0.89 seconds
Started Nov 22 01:35:22 PM PST 23
Finished Nov 22 01:35:24 PM PST 23
Peak memory 205440 kb
Host smart-75269df8-b8be-456d-a27e-94aa0b70564c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652786837530694950326903273329705330031906079653909426103613041967835437317 -assert nopostpro
c +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.edn_alert_test.2652786837530694950326903273329705330031906079653909426103613041967835437317
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.4539562555603573934218633285736196562484643052131653145887619940244646032766
Short name T909
Test name
Test status
Simulation time 12219183 ps
CPU time 0.85 seconds
Started Nov 22 01:35:07 PM PST 23
Finished Nov 22 01:35:15 PM PST 23
Peak memory 214888 kb
Host smart-52a35b16-bdfd-4370-a328-d5642c9f3428
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4539562555603573934218633285736196562484643052131653145887619940244646032766 -assert nopostproc
+UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.edn_disable.4539562555603573934218633285736196562484643052131653145887619940244646032766
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.83020604230006961580482384755100283446669530704279440310950531140256323049992
Short name T951
Test name
Test status
Simulation time 14969183 ps
CPU time 0.9 seconds
Started Nov 22 01:35:10 PM PST 23
Finished Nov 22 01:35:15 PM PST 23
Peak memory 214820 kb
Host smart-d1811eee-d97b-4750-9d4f-50c5837f8b2f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83020604230006961580482384755100283446669530704279440310950531140256323049992 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable_auto_req_mode.8302060423000696158048238475510028344666953070427944031095
0531140256323049992
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.3104291270283597389900200733005624650217314103482580944581602654751545362350
Short name T806
Test name
Test status
Simulation time 24963823 ps
CPU time 1.14 seconds
Started Nov 22 01:35:06 PM PST 23
Finished Nov 22 01:35:13 PM PST 23
Peak memory 230464 kb
Host smart-13e2fc32-f38f-4167-9372-e3540abb64fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104291270283597389900200733005624650217314103482580944581602654751545362350 -assert nopostproc +UVM_TESTNAME=edn_err_te
st +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
edn_err.3104291270283597389900200733005624650217314103482580944581602654751545362350
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.79360986555833971954371540063432106480019582325632101499774572572818782661542
Short name T39
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Nov 22 01:35:04 PM PST 23
Finished Nov 22 01:35:07 PM PST 23
Peak memory 205820 kb
Host smart-4da1f45b-02c3-47d9-b647-8592bbf21f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79360986555833971954371540063432106480019582325632101499774572572818782661542 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.edn_genbits.79360986555833971954371540063432106480019582325632101499774572572818782661542
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.86001984298474187344004733419811399025096035525056563279356364678068155170647
Short name T24
Test name
Test status
Simulation time 18439183 ps
CPU time 1.11 seconds
Started Nov 22 01:35:07 PM PST 23
Finished Nov 22 01:35:15 PM PST 23
Peak memory 222268 kb
Host smart-258014b4-5820-4313-99f7-7e83a2cd9ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86001984298474187344004733419811399025096035525056563279356364678068155170647 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.edn_intr.86001984298474187344004733419811399025096035525056563279356364678068155170647
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.9218927597623355951404810067297696067042830986565361845593915380682971817552
Short name T491
Test name
Test status
Simulation time 13059183 ps
CPU time 0.9 seconds
Started Nov 22 01:35:10 PM PST 23
Finished Nov 22 01:35:15 PM PST 23
Peak memory 205300 kb
Host smart-d3aa2d68-d7ef-4bf5-935a-71e91a8b093a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9218927597623355951404810067297696067042830986565361845593915380682971817552 -assert nopostproc +UVM_TESTNAME=edn_smoke_
test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.edn_smoke.9218927597623355951404810067297696067042830986565361845593915380682971817552
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.83864613500730299211408704705652727770168874355579523881190806010812711824834
Short name T418
Test name
Test status
Simulation time 154489183 ps
CPU time 3.88 seconds
Started Nov 22 01:35:08 PM PST 23
Finished Nov 22 01:35:18 PM PST 23
Peak memory 206236 kb
Host smart-912aebc2-6fbb-4312-b4fd-9f5eeb26473a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83864613500730299211408704705652727770168874355579523881190806010812711824834 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.83864613500730299211408704705652727770168874355579523881190806010812711824834
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.84111550423562485720414587666718111824293820737511163984029711223683971011514
Short name T524
Test name
Test status
Simulation time 41708099183 ps
CPU time 1076.71 seconds
Started Nov 22 01:35:07 PM PST 23
Finished Nov 22 01:53:11 PM PST 23
Peak memory 215868 kb
Host smart-bf50bb3c-c610-4d1f-9ea8-3e967f03c246
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841115504235624857204145876
66718111824293820737511163984029711223683971011514 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.84111550423
562485720414587666718111824293820737511163984029711223683971011514
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.65519355690370682452577972456276180166719414668486316429623345556093250725881
Short name T609
Test name
Test status
Simulation time 18259183 ps
CPU time 1 seconds
Started Nov 22 01:35:05 PM PST 23
Finished Nov 22 01:35:12 PM PST 23
Peak memory 205592 kb
Host smart-00d2b203-aa42-4b38-8a7b-81b013c01921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65519355690370682452577972456276180166719414668486316429623345556093250725881 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 38.edn_alert.65519355690370682452577972456276180166719414668486316429623345556093250725881
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.23428831855679828147535410416031200579521089687668343485525406350108585004316
Short name T746
Test name
Test status
Simulation time 28184990 ps
CPU time 0.89 seconds
Started Nov 22 01:35:09 PM PST 23
Finished Nov 22 01:35:15 PM PST 23
Peak memory 205468 kb
Host smart-768d6b6a-cc57-4442-947f-0f94ef6c8e81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23428831855679828147535410416031200579521089687668343485525406350108585004316 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.edn_alert_test.23428831855679828147535410416031200579521089687668343485525406350108585004316
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.112678367875033079245596678256120661007984914259562364311690115030235746252678
Short name T832
Test name
Test status
Simulation time 12219183 ps
CPU time 0.87 seconds
Started Nov 22 01:35:20 PM PST 23
Finished Nov 22 01:35:21 PM PST 23
Peak memory 214836 kb
Host smart-d97a69f9-99ca-4e3d-9e71-c1284f07ddec
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112678367875033079245596678256120661007984914259562364311690115030235746252678 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 38.edn_disable.112678367875033079245596678256120661007984914259562364311690115030235746252678
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.113840028991633140820207097030031997813407132032001078756498045640872061124741
Short name T308
Test name
Test status
Simulation time 14969183 ps
CPU time 0.92 seconds
Started Nov 22 01:35:05 PM PST 23
Finished Nov 22 01:35:07 PM PST 23
Peak memory 214876 kb
Host smart-5cfb5db3-96c0-4002-ba92-cf951b0b023b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113840028991633140820207097030031997813407132032001078756498045640872061124741 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable_auto_req_mode.113840028991633140820207097030031997813407132032001078756
498045640872061124741
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.109498276932541180116921071820596076206241215966599071281209031481842662220950
Short name T747
Test name
Test status
Simulation time 24963823 ps
CPU time 1.12 seconds
Started Nov 22 01:35:07 PM PST 23
Finished Nov 22 01:35:15 PM PST 23
Peak memory 230212 kb
Host smart-7643ed4f-cd23-4832-887c-de887e0d5a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109498276932541180116921071820596076206241215966599071281209031481842662220950 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.edn_err.109498276932541180116921071820596076206241215966599071281209031481842662220950
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.13033742352084842870085049780314369965568274280370539947875398001569317617397
Short name T384
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Nov 22 01:35:04 PM PST 23
Finished Nov 22 01:35:07 PM PST 23
Peak memory 205876 kb
Host smart-a298455e-0148-45bb-b21d-dffaf007b874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13033742352084842870085049780314369965568274280370539947875398001569317617397 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.edn_genbits.13033742352084842870085049780314369965568274280370539947875398001569317617397
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.45228680325666519447713225479347337171367086380537962099836403408971099117894
Short name T734
Test name
Test status
Simulation time 18439183 ps
CPU time 1.15 seconds
Started Nov 22 01:35:05 PM PST 23
Finished Nov 22 01:35:13 PM PST 23
Peak memory 222192 kb
Host smart-2a89bf9f-32c7-41ba-9f11-49df251bbdaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45228680325666519447713225479347337171367086380537962099836403408971099117894 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.edn_intr.45228680325666519447713225479347337171367086380537962099836403408971099117894
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.12887094975904614552834213558147071672102112367237170629285129802874763302284
Short name T16
Test name
Test status
Simulation time 13059183 ps
CPU time 0.89 seconds
Started Nov 22 01:35:06 PM PST 23
Finished Nov 22 01:35:12 PM PST 23
Peak memory 205324 kb
Host smart-912affb8-0e6b-4a3f-aa83-fec259db9479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12887094975904614552834213558147071672102112367237170629285129802874763302284 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 38.edn_smoke.12887094975904614552834213558147071672102112367237170629285129802874763302284
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.111779748123054190093155295460600107613119980557344778613509646083711117077382
Short name T759
Test name
Test status
Simulation time 154489183 ps
CPU time 3.89 seconds
Started Nov 22 01:35:05 PM PST 23
Finished Nov 22 01:35:15 PM PST 23
Peak memory 206336 kb
Host smart-3173d74c-538c-4389-b33f-da2b27e1a167
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111779748123054190093155295460600107613119980557344778613509646083711117077382 -assert nopo
stproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.111779748123054190093155295460600107613119980557344778613509646083711117077382
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.23136522584633889019451569132684784584519698954104106544015152378809788319249
Short name T472
Test name
Test status
Simulation time 41708099183 ps
CPU time 1080.33 seconds
Started Nov 22 01:35:06 PM PST 23
Finished Nov 22 01:53:13 PM PST 23
Peak memory 215868 kb
Host smart-ed7c5764-2ac4-4590-8bde-d40ba8b26cb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231365225846338890194515691
32684784584519698954104106544015152378809788319249 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.23136522584
633889019451569132684784584519698954104106544015152378809788319249
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.11864322477459120818982344118667845393928583957502203427847747524359187890294
Short name T703
Test name
Test status
Simulation time 18259183 ps
CPU time 1.03 seconds
Started Nov 22 01:35:31 PM PST 23
Finished Nov 22 01:35:33 PM PST 23
Peak memory 205556 kb
Host smart-669193f7-f97c-4d7c-b7a5-6f50889f500a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11864322477459120818982344118667845393928583957502203427847747524359187890294 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 39.edn_alert.11864322477459120818982344118667845393928583957502203427847747524359187890294
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.10376817074571558016081564208751021618941769924557856231376772042891523516637
Short name T670
Test name
Test status
Simulation time 28184990 ps
CPU time 0.91 seconds
Started Nov 22 01:35:30 PM PST 23
Finished Nov 22 01:35:31 PM PST 23
Peak memory 205504 kb
Host smart-eacce606-bddd-4a75-8500-23ba32be2a3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10376817074571558016081564208751021618941769924557856231376772042891523516637 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.edn_alert_test.10376817074571558016081564208751021618941769924557856231376772042891523516637
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.5062239611294629881426669320445467132596292431868644750997701475799191313820
Short name T545
Test name
Test status
Simulation time 12219183 ps
CPU time 0.85 seconds
Started Nov 22 01:35:37 PM PST 23
Finished Nov 22 01:35:42 PM PST 23
Peak memory 214880 kb
Host smart-38de4934-524d-4188-8470-fdf77fbac561
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5062239611294629881426669320445467132596292431868644750997701475799191313820 -assert nopostproc
+UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.edn_disable.5062239611294629881426669320445467132596292431868644750997701475799191313820
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.79390408173766880853592058338175417020364243988606235862318481358726686415919
Short name T571
Test name
Test status
Simulation time 14969183 ps
CPU time 0.87 seconds
Started Nov 22 01:35:37 PM PST 23
Finished Nov 22 01:35:42 PM PST 23
Peak memory 214868 kb
Host smart-a74d2ff2-88c5-40a8-a562-c5d7342ffdee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79390408173766880853592058338175417020364243988606235862318481358726686415919 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable_auto_req_mode.7939040817376688085359205833817541702036424398860623586231
8481358726686415919
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.31794757145865371364916698081617233370441441685268326654577465050320238775707
Short name T899
Test name
Test status
Simulation time 24963823 ps
CPU time 1.18 seconds
Started Nov 22 01:35:35 PM PST 23
Finished Nov 22 01:35:40 PM PST 23
Peak memory 230456 kb
Host smart-20309422-b0c5-4047-8d0f-a297d0045e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31794757145865371364916698081617233370441441685268326654577465050320238775707 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.edn_err.31794757145865371364916698081617233370441441685268326654577465050320238775707
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.55771549680502012513808591643012244111750578631106407603172906776765121677837
Short name T724
Test name
Test status
Simulation time 17999183 ps
CPU time 1.18 seconds
Started Nov 22 01:35:05 PM PST 23
Finished Nov 22 01:35:07 PM PST 23
Peak memory 205812 kb
Host smart-26727eef-f06f-45ef-ad69-12671f6e66c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55771549680502012513808591643012244111750578631106407603172906776765121677837 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.edn_genbits.55771549680502012513808591643012244111750578631106407603172906776765121677837
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.45239720931497164118538647053155120206722513468511761761919744962799180484274
Short name T37
Test name
Test status
Simulation time 18439183 ps
CPU time 1.18 seconds
Started Nov 22 01:35:34 PM PST 23
Finished Nov 22 01:35:36 PM PST 23
Peak memory 222168 kb
Host smart-4c1ca9a7-4fa3-47ee-80b3-2b7899c94024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45239720931497164118538647053155120206722513468511761761919744962799180484274 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.edn_intr.45239720931497164118538647053155120206722513468511761761919744962799180484274
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.111589220221606996216180735723093202560120628387263486913375603407623896595738
Short name T675
Test name
Test status
Simulation time 13059183 ps
CPU time 0.85 seconds
Started Nov 22 01:35:06 PM PST 23
Finished Nov 22 01:35:13 PM PST 23
Peak memory 205288 kb
Host smart-7cc94f1d-9bf4-4b83-b912-8c8c62e047a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111589220221606996216180735723093202560120628387263486913375603407623896595738 -assert nopostproc +UVM_TESTNAME=edn_smok
e_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 39.edn_smoke.111589220221606996216180735723093202560120628387263486913375603407623896595738
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.28101785237841198403907994710159676742409379269927018976394852041590761043921
Short name T667
Test name
Test status
Simulation time 154489183 ps
CPU time 3.94 seconds
Started Nov 22 01:35:11 PM PST 23
Finished Nov 22 01:35:19 PM PST 23
Peak memory 206300 kb
Host smart-832b1cd6-21d7-4ebe-bc64-9e5f7c4be7ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28101785237841198403907994710159676742409379269927018976394852041590761043921 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.28101785237841198403907994710159676742409379269927018976394852041590761043921
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.91708741510969667902026126916784161431347259861759690193286833005189948049026
Short name T649
Test name
Test status
Simulation time 41708099183 ps
CPU time 1086.89 seconds
Started Nov 22 01:35:39 PM PST 23
Finished Nov 22 01:53:49 PM PST 23
Peak memory 215832 kb
Host smart-4735b0e9-7f0b-4ad7-817f-cc9d19e5035b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917087415109696679020261269
16784161431347259861759690193286833005189948049026 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.91708741510
969667902026126916784161431347259861759690193286833005189948049026
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.3125421401980014515743390481140381007293028495331811592439532673094159048742
Short name T688
Test name
Test status
Simulation time 18259183 ps
CPU time 0.99 seconds
Started Nov 22 01:31:50 PM PST 23
Finished Nov 22 01:31:52 PM PST 23
Peak memory 205592 kb
Host smart-17062548-26f5-4576-904a-dee77a97ebee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125421401980014515743390481140381007293028495331811592439532673094159048742 -assert nopostproc +UVM_TESTNAME=edn_alert_
test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.edn_alert.3125421401980014515743390481140381007293028495331811592439532673094159048742
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.101905845942106385466698200176415797455361901426795534592669345833472893279120
Short name T410
Test name
Test status
Simulation time 28184990 ps
CPU time 0.88 seconds
Started Nov 22 01:31:50 PM PST 23
Finished Nov 22 01:31:51 PM PST 23
Peak memory 205500 kb
Host smart-abef6278-bc74-4ab3-8af8-d3961450e95e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101905845942106385466698200176415797455361901426795534592669345833472893279120 -assert nopostp
roc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 4.edn_alert_test.101905845942106385466698200176415797455361901426795534592669345833472893279120
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.98795743770120079486185560422526011398424856814058235172925136808115104402170
Short name T28
Test name
Test status
Simulation time 12219183 ps
CPU time 0.88 seconds
Started Nov 22 01:31:53 PM PST 23
Finished Nov 22 01:31:54 PM PST 23
Peak memory 214664 kb
Host smart-d653c8a7-d9ef-4796-bb03-d30c062657e7
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98795743770120079486185560422526011398424856814058235172925136808115104402170 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.edn_disable.98795743770120079486185560422526011398424856814058235172925136808115104402170
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.47813985691515553996518021574213804745063630705507955112228969594217903331085
Short name T980
Test name
Test status
Simulation time 14969183 ps
CPU time 0.92 seconds
Started Nov 22 01:31:51 PM PST 23
Finished Nov 22 01:31:53 PM PST 23
Peak memory 214900 kb
Host smart-24e23f84-9859-4b5f-8fb2-d3bfc0d29a29
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47813985691515553996518021574213804745063630705507955112228969594217903331085 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable_auto_req_mode.47813985691515553996518021574213804745063630705507955112228
969594217903331085
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.42226827198010211122410164275837541613067629528469076909713603943322173878432
Short name T948
Test name
Test status
Simulation time 24963823 ps
CPU time 1.14 seconds
Started Nov 22 01:31:50 PM PST 23
Finished Nov 22 01:31:53 PM PST 23
Peak memory 230484 kb
Host smart-c0545344-a1d7-4268-acde-5ed9fb2cb3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42226827198010211122410164275837541613067629528469076909713603943322173878432 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
edn_err.42226827198010211122410164275837541613067629528469076909713603943322173878432
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.65708839461747827155946908997823705354126785899324621686977700971105096797071
Short name T531
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:31:51 PM PST 23
Finished Nov 22 01:31:53 PM PST 23
Peak memory 205840 kb
Host smart-e66793ba-4bac-4823-9b72-ac7ec85cbaf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65708839461747827155946908997823705354126785899324621686977700971105096797071 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.edn_genbits.65708839461747827155946908997823705354126785899324621686977700971105096797071
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.60635142690211617052879883317712210936483550236547009576080601918305229763925
Short name T13
Test name
Test status
Simulation time 18439183 ps
CPU time 1.08 seconds
Started Nov 22 01:31:51 PM PST 23
Finished Nov 22 01:31:54 PM PST 23
Peak memory 222128 kb
Host smart-9e0a4cce-afbc-4053-a183-9c26a8548773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60635142690211617052879883317712210936483550236547009576080601918305229763925 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.edn_intr.60635142690211617052879883317712210936483550236547009576080601918305229763925
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.84923966605833341478117140189115965884079272186713227403769485339290119708446
Short name T898
Test name
Test status
Simulation time 11759183 ps
CPU time 0.88 seconds
Started Nov 22 01:31:49 PM PST 23
Finished Nov 22 01:31:51 PM PST 23
Peak memory 205284 kb
Host smart-2185ba2c-84e5-4775-ad5a-b29284f40688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84923966605833341478117140189115965884079272186713227403769485339290119708446 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.edn_regwen.84923966605833341478117140189115965884079272186713227403769485339290119708446
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.452534870505987734255485276389023047113984806195430024161714946567858082012
Short name T53
Test name
Test status
Simulation time 717215632 ps
CPU time 5.9 seconds
Started Nov 22 01:31:51 PM PST 23
Finished Nov 22 01:31:58 PM PST 23
Peak memory 234028 kb
Host smart-842aaeaf-9d5e-4e17-b9ea-7cc15868bf9b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452534870505987734255485276389023047113984806195430024161714946567858082012 -assert nopostproc
+UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 4.edn_sec_cm.452534870505987734255485276389023047113984806195430024161714946567858082012
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.33863436669728794913535416108026443087397682658872773329533329482635690040069
Short name T401
Test name
Test status
Simulation time 13059183 ps
CPU time 0.86 seconds
Started Nov 22 01:31:50 PM PST 23
Finished Nov 22 01:31:52 PM PST 23
Peak memory 205312 kb
Host smart-6c29c93e-3a57-42b8-87cc-ca98544c108f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33863436669728794913535416108026443087397682658872773329533329482635690040069 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.edn_smoke.33863436669728794913535416108026443087397682658872773329533329482635690040069
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.67668432302633373267904171846207921487854003572790816541399153454544187536823
Short name T718
Test name
Test status
Simulation time 154489183 ps
CPU time 3.94 seconds
Started Nov 22 01:31:51 PM PST 23
Finished Nov 22 01:31:56 PM PST 23
Peak memory 206260 kb
Host smart-9281e56d-47c1-4cc7-b7a5-c53d7fc54193
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67668432302633373267904171846207921487854003572790816541399153454544187536823 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.67668432302633373267904171846207921487854003572790816541399153454544187536823
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.58626846481239177792854157868827952841028051537277372531214374194191022409222
Short name T558
Test name
Test status
Simulation time 41708099183 ps
CPU time 1104.02 seconds
Started Nov 22 01:31:53 PM PST 23
Finished Nov 22 01:50:18 PM PST 23
Peak memory 215576 kb
Host smart-630fe290-283b-4157-8e66-fb376b3885b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586268464812391777928541578
68827952841028051537277372531214374194191022409222 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.586268464812
39177792854157868827952841028051537277372531214374194191022409222
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.36732810734062089794312492258793790840896085566683403282522218489880933055272
Short name T818
Test name
Test status
Simulation time 18259183 ps
CPU time 0.98 seconds
Started Nov 22 01:35:32 PM PST 23
Finished Nov 22 01:35:35 PM PST 23
Peak memory 205572 kb
Host smart-ed84d170-21a1-482d-a478-b7f37f93c656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36732810734062089794312492258793790840896085566683403282522218489880933055272 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 40.edn_alert.36732810734062089794312492258793790840896085566683403282522218489880933055272
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.35963784521413493551589474419375319996610194644033891386215929301264458783374
Short name T841
Test name
Test status
Simulation time 28184990 ps
CPU time 0.9 seconds
Started Nov 22 01:35:31 PM PST 23
Finished Nov 22 01:35:34 PM PST 23
Peak memory 205512 kb
Host smart-9d175cc0-feb4-4427-a666-06f8c8e171b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35963784521413493551589474419375319996610194644033891386215929301264458783374 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.edn_alert_test.35963784521413493551589474419375319996610194644033891386215929301264458783374
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.85405486122264821120446614484062362178092756018265369831293404776559898160443
Short name T363
Test name
Test status
Simulation time 12219183 ps
CPU time 0.96 seconds
Started Nov 22 01:35:33 PM PST 23
Finished Nov 22 01:35:35 PM PST 23
Peak memory 214784 kb
Host smart-28b60a1b-3fcd-4d04-8f81-63a8342dbd62
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85405486122264821120446614484062362178092756018265369831293404776559898160443 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.edn_disable.85405486122264821120446614484062362178092756018265369831293404776559898160443
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.35053891069528183170208355932797995854855684118984472257048337956414602821757
Short name T637
Test name
Test status
Simulation time 14969183 ps
CPU time 0.9 seconds
Started Nov 22 01:35:40 PM PST 23
Finished Nov 22 01:35:44 PM PST 23
Peak memory 214880 kb
Host smart-c6a74a7d-bb4b-4ec5-b3a1-2dc81c0845af
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35053891069528183170208355932797995854855684118984472257048337956414602821757 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable_auto_req_mode.3505389106952818317020835593279799585485568411898447225704
8337956414602821757
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.51248194731611297214595882534388288758496422642579762730537472800358489435472
Short name T583
Test name
Test status
Simulation time 24963823 ps
CPU time 1.24 seconds
Started Nov 22 01:35:29 PM PST 23
Finished Nov 22 01:35:31 PM PST 23
Peak memory 230440 kb
Host smart-45293b1f-bfc6-4e63-8654-b9e42813dbb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51248194731611297214595882534388288758496422642579762730537472800358489435472 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.edn_err.51248194731611297214595882534388288758496422642579762730537472800358489435472
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.57955023266769532032298795671692866635665965829025895943448939610732466693595
Short name T580
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 22 01:35:38 PM PST 23
Finished Nov 22 01:35:42 PM PST 23
Peak memory 205848 kb
Host smart-68d50bc7-dffe-41e7-b92c-02be89d58f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57955023266769532032298795671692866635665965829025895943448939610732466693595 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.edn_genbits.57955023266769532032298795671692866635665965829025895943448939610732466693595
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.74742358684563273347351993905105657887978500683705464444780484276624033880182
Short name T356
Test name
Test status
Simulation time 18439183 ps
CPU time 1.13 seconds
Started Nov 22 01:35:30 PM PST 23
Finished Nov 22 01:35:33 PM PST 23
Peak memory 222240 kb
Host smart-0f33c709-1c02-4371-b213-543ebf41b403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74742358684563273347351993905105657887978500683705464444780484276624033880182 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.edn_intr.74742358684563273347351993905105657887978500683705464444780484276624033880182
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.37236942671300883007397667499365070998188735286712282878809778749198275728387
Short name T298
Test name
Test status
Simulation time 13059183 ps
CPU time 0.85 seconds
Started Nov 22 01:35:35 PM PST 23
Finished Nov 22 01:35:40 PM PST 23
Peak memory 205368 kb
Host smart-c929c8c5-2913-4885-8529-972af84b1ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37236942671300883007397667499365070998188735286712282878809778749198275728387 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 40.edn_smoke.37236942671300883007397667499365070998188735286712282878809778749198275728387
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.498185725476115657332800660993330615944741433009759796986501876072793239787
Short name T932
Test name
Test status
Simulation time 154489183 ps
CPU time 3.91 seconds
Started Nov 22 01:35:35 PM PST 23
Finished Nov 22 01:35:42 PM PST 23
Peak memory 206368 kb
Host smart-87eaab02-f3e6-4919-9a52-3d6606820306
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498185725476115657332800660993330615944741433009759796986501876072793239787 -assert nopostp
roc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.498185725476115657332800660993330615944741433009759796986501876072793239787
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.898783653483102801375630808856342675685515919306766118625419178751229070721
Short name T351
Test name
Test status
Simulation time 41708099183 ps
CPU time 1091.39 seconds
Started Nov 22 01:35:40 PM PST 23
Finished Nov 22 01:53:54 PM PST 23
Peak memory 215760 kb
Host smart-550698a8-8cbe-40d8-9b6b-a12f43be4c5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898783653483102801375630808
856342675685515919306766118625419178751229070721 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.8987836534831
02801375630808856342675685515919306766118625419178751229070721
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.66251196278336176289787663851478644956501845791309950936678162028222066092078
Short name T497
Test name
Test status
Simulation time 18259183 ps
CPU time 0.99 seconds
Started Nov 22 01:35:38 PM PST 23
Finished Nov 22 01:35:42 PM PST 23
Peak memory 205580 kb
Host smart-7a68fcea-7d91-4246-8709-31030c08b0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66251196278336176289787663851478644956501845791309950936678162028222066092078 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 41.edn_alert.66251196278336176289787663851478644956501845791309950936678162028222066092078
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.26904458373317108585770788135878902142565151130283176106015836938139238837921
Short name T521
Test name
Test status
Simulation time 28184990 ps
CPU time 0.89 seconds
Started Nov 22 01:35:28 PM PST 23
Finished Nov 22 01:35:30 PM PST 23
Peak memory 205468 kb
Host smart-dca33f0d-4734-4688-9a6f-12a0fd27e386
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26904458373317108585770788135878902142565151130283176106015836938139238837921 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.edn_alert_test.26904458373317108585770788135878902142565151130283176106015836938139238837921
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.2426838608200732250719495155293549904365665545755513793776439797510954892617
Short name T67
Test name
Test status
Simulation time 12219183 ps
CPU time 0.92 seconds
Started Nov 22 01:35:38 PM PST 23
Finished Nov 22 01:35:42 PM PST 23
Peak memory 214880 kb
Host smart-a5347857-e995-4715-aabd-597425e5e3f1
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426838608200732250719495155293549904365665545755513793776439797510954892617 -assert nopostproc
+UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.edn_disable.2426838608200732250719495155293549904365665545755513793776439797510954892617
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.64241767992718769593441254809177757001936325995457476144538710933477304746323
Short name T931
Test name
Test status
Simulation time 14969183 ps
CPU time 0.92 seconds
Started Nov 22 01:35:38 PM PST 23
Finished Nov 22 01:35:42 PM PST 23
Peak memory 214852 kb
Host smart-5e8264dc-732c-415e-8d86-825832989444
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64241767992718769593441254809177757001936325995457476144538710933477304746323 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable_auto_req_mode.6424176799271876959344125480917775700193632599545747614453
8710933477304746323
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.9810089324118685136774484569124356960171228109860887523109796683756752585847
Short name T294
Test name
Test status
Simulation time 24963823 ps
CPU time 1.14 seconds
Started Nov 22 01:35:30 PM PST 23
Finished Nov 22 01:35:33 PM PST 23
Peak memory 230460 kb
Host smart-f0c0ef81-f3e8-4b47-9fab-56cfd1c2029e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9810089324118685136774484569124356960171228109860887523109796683756752585847 -assert nopostproc +UVM_TESTNAME=edn_err_te
st +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
edn_err.9810089324118685136774484569124356960171228109860887523109796683756752585847
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.53636451035787900156736504228273979043046125642751847541162300598017860063677
Short name T904
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 22 01:35:40 PM PST 23
Finished Nov 22 01:35:44 PM PST 23
Peak memory 205820 kb
Host smart-42165cb4-c86c-44da-9302-68bc21792fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53636451035787900156736504228273979043046125642751847541162300598017860063677 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.edn_genbits.53636451035787900156736504228273979043046125642751847541162300598017860063677
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.103334446329748661159610020878534620740002455179630012686399047988850830355131
Short name T525
Test name
Test status
Simulation time 18439183 ps
CPU time 1.11 seconds
Started Nov 22 01:35:36 PM PST 23
Finished Nov 22 01:35:40 PM PST 23
Peak memory 222248 kb
Host smart-df2591ab-1c32-4755-87ac-2624ff3bc1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103334446329748661159610020878534620740002455179630012686399047988850830355131 -assert nopostproc +UVM_TESTNAME=edn_intr
_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.edn_intr.103334446329748661159610020878534620740002455179630012686399047988850830355131
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.75393981456349255684827388696237332864335145571257415322995022674762785534885
Short name T593
Test name
Test status
Simulation time 13059183 ps
CPU time 0.93 seconds
Started Nov 22 01:35:45 PM PST 23
Finished Nov 22 01:35:48 PM PST 23
Peak memory 205372 kb
Host smart-228d5453-7d00-4711-9bbc-46a5942fbe73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75393981456349255684827388696237332864335145571257415322995022674762785534885 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 41.edn_smoke.75393981456349255684827388696237332864335145571257415322995022674762785534885
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.3727925121246614969298447879614195107862483547039219559851461211908151952864
Short name T568
Test name
Test status
Simulation time 154489183 ps
CPU time 3.95 seconds
Started Nov 22 01:35:32 PM PST 23
Finished Nov 22 01:35:38 PM PST 23
Peak memory 206384 kb
Host smart-b39bed15-cf69-43ed-9f55-06d9ea550293
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727925121246614969298447879614195107862483547039219559851461211908151952864 -assert nopost
proc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.3727925121246614969298447879614195107862483547039219559851461211908151952864
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.2650658403804657754209526964446824366665032843766009388701629765163086942843
Short name T258
Test name
Test status
Simulation time 41708099183 ps
CPU time 1084.99 seconds
Started Nov 22 01:35:38 PM PST 23
Finished Nov 22 01:53:46 PM PST 23
Peak memory 215864 kb
Host smart-4e873083-4874-4659-bdd0-43b039cda403
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265065840380465775420952696
4446824366665032843766009388701629765163086942843 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.265065840380
4657754209526964446824366665032843766009388701629765163086942843
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.3433642385491191494185950527970673801352894046841586875078534264571451635138
Short name T43
Test name
Test status
Simulation time 18259183 ps
CPU time 0.99 seconds
Started Nov 22 01:35:28 PM PST 23
Finished Nov 22 01:35:29 PM PST 23
Peak memory 205480 kb
Host smart-3f2979bf-a093-4abe-8791-3c2fc4d9e16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433642385491191494185950527970673801352894046841586875078534264571451635138 -assert nopostproc +UVM_TESTNAME=edn_alert_
test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.edn_alert.3433642385491191494185950527970673801352894046841586875078534264571451635138
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.84213229832632982903761061024853310565969777613873745304381920335827181476229
Short name T589
Test name
Test status
Simulation time 28184990 ps
CPU time 0.88 seconds
Started Nov 22 01:35:34 PM PST 23
Finished Nov 22 01:35:35 PM PST 23
Peak memory 205540 kb
Host smart-f49a9e03-65cb-472c-81c9-45b53df6dbd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84213229832632982903761061024853310565969777613873745304381920335827181476229 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.edn_alert_test.84213229832632982903761061024853310565969777613873745304381920335827181476229
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.15700481314889606071321726752541521682439471882866027307883646068332834917098
Short name T582
Test name
Test status
Simulation time 12219183 ps
CPU time 0.9 seconds
Started Nov 22 01:35:30 PM PST 23
Finished Nov 22 01:35:32 PM PST 23
Peak memory 214832 kb
Host smart-f60f9658-91cb-4b11-87d9-af1a2c7e573a
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15700481314889606071321726752541521682439471882866027307883646068332834917098 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.edn_disable.15700481314889606071321726752541521682439471882866027307883646068332834917098
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.62369007677310301202773690996980573007149360219107496765305997322071701427961
Short name T712
Test name
Test status
Simulation time 14969183 ps
CPU time 0.88 seconds
Started Nov 22 01:35:39 PM PST 23
Finished Nov 22 01:35:42 PM PST 23
Peak memory 214896 kb
Host smart-fd864624-90df-4d2d-ba22-4f892f2b4c58
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62369007677310301202773690996980573007149360219107496765305997322071701427961 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable_auto_req_mode.6236900767731030120277369099698057300714936021910749676530
5997322071701427961
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.97638763805359311156464809006698985225862126597058482608575604093726671701815
Short name T922
Test name
Test status
Simulation time 24963823 ps
CPU time 1.17 seconds
Started Nov 22 01:35:31 PM PST 23
Finished Nov 22 01:35:33 PM PST 23
Peak memory 230436 kb
Host smart-982e88c8-7559-431a-b8da-2cddf4e2422f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97638763805359311156464809006698985225862126597058482608575604093726671701815 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.edn_err.97638763805359311156464809006698985225862126597058482608575604093726671701815
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.84623648306599967130683147634682444920013308353603625107557443940708417973306
Short name T835
Test name
Test status
Simulation time 17999183 ps
CPU time 1.15 seconds
Started Nov 22 01:35:30 PM PST 23
Finished Nov 22 01:35:33 PM PST 23
Peak memory 205852 kb
Host smart-da1a400f-4461-4605-825f-e0eaf4fbc94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84623648306599967130683147634682444920013308353603625107557443940708417973306 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.edn_genbits.84623648306599967130683147634682444920013308353603625107557443940708417973306
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.45406766925787551207704854867011871302226381429373816134383019584526605119776
Short name T445
Test name
Test status
Simulation time 18439183 ps
CPU time 1.13 seconds
Started Nov 22 01:35:35 PM PST 23
Finished Nov 22 01:35:39 PM PST 23
Peak memory 222108 kb
Host smart-196ac3cf-417c-4a49-82e0-9fa0b97f5ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45406766925787551207704854867011871302226381429373816134383019584526605119776 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.edn_intr.45406766925787551207704854867011871302226381429373816134383019584526605119776
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.36958262827382040865135861290285689156468904687549699130177778943533829270813
Short name T738
Test name
Test status
Simulation time 13059183 ps
CPU time 0.87 seconds
Started Nov 22 01:35:38 PM PST 23
Finished Nov 22 01:35:42 PM PST 23
Peak memory 205372 kb
Host smart-7873fdc0-3837-455c-9a6b-d662254de2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36958262827382040865135861290285689156468904687549699130177778943533829270813 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 42.edn_smoke.36958262827382040865135861290285689156468904687549699130177778943533829270813
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.43495829287555140975835673610146128517157735095392513435866855599021953778533
Short name T619
Test name
Test status
Simulation time 154489183 ps
CPU time 4.09 seconds
Started Nov 22 01:35:35 PM PST 23
Finished Nov 22 01:35:43 PM PST 23
Peak memory 206372 kb
Host smart-d708b00f-5abf-42bb-b90b-87c5bc0ec830
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43495829287555140975835673610146128517157735095392513435866855599021953778533 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.43495829287555140975835673610146128517157735095392513435866855599021953778533
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.77960748339270554205984896970971564768232683054575134308803403509331304114715
Short name T829
Test name
Test status
Simulation time 41708099183 ps
CPU time 1020.97 seconds
Started Nov 22 01:35:31 PM PST 23
Finished Nov 22 01:52:34 PM PST 23
Peak memory 215868 kb
Host smart-2d7e7c61-3d65-44f8-adeb-4a860c020ceb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779607483392705542059848969
70971564768232683054575134308803403509331304114715 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.77960748339
270554205984896970971564768232683054575134308803403509331304114715
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.2625639037699991937254176955558548063466068812914357678474315396984702548605
Short name T281
Test name
Test status
Simulation time 18259183 ps
CPU time 0.96 seconds
Started Nov 22 01:35:36 PM PST 23
Finished Nov 22 01:35:40 PM PST 23
Peak memory 205488 kb
Host smart-ef27beb0-378b-4917-a351-4682cc8dffd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625639037699991937254176955558548063466068812914357678474315396984702548605 -assert nopostproc +UVM_TESTNAME=edn_alert_
test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.edn_alert.2625639037699991937254176955558548063466068812914357678474315396984702548605
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.59084594593792192327067120113541017619667153264934595511652145912194412097873
Short name T748
Test name
Test status
Simulation time 28184990 ps
CPU time 0.88 seconds
Started Nov 22 01:35:32 PM PST 23
Finished Nov 22 01:35:35 PM PST 23
Peak memory 205540 kb
Host smart-4c60bb4a-6ae5-44da-ac49-e5a3be333aab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59084594593792192327067120113541017619667153264934595511652145912194412097873 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.edn_alert_test.59084594593792192327067120113541017619667153264934595511652145912194412097873
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.69090015323125028045871726511279912361931405156168484178116921637497852611446
Short name T68
Test name
Test status
Simulation time 12219183 ps
CPU time 0.84 seconds
Started Nov 22 01:35:36 PM PST 23
Finished Nov 22 01:35:41 PM PST 23
Peak memory 214768 kb
Host smart-a121886c-4644-43a0-a024-c74713ff9ed1
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69090015323125028045871726511279912361931405156168484178116921637497852611446 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.edn_disable.69090015323125028045871726511279912361931405156168484178116921637497852611446
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.104994383580189521825039029450097692745232267461222092604914696725533798323449
Short name T361
Test name
Test status
Simulation time 14969183 ps
CPU time 0.91 seconds
Started Nov 22 01:35:30 PM PST 23
Finished Nov 22 01:35:32 PM PST 23
Peak memory 214828 kb
Host smart-eddbbbbc-0aab-4ccf-878a-3e38d1713746
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104994383580189521825039029450097692745232267461222092604914696725533798323449 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable_auto_req_mode.104994383580189521825039029450097692745232267461222092604
914696725533798323449
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.88236569573826872270524902273383090459916008413971107289812321117246828470133
Short name T916
Test name
Test status
Simulation time 24963823 ps
CPU time 1.17 seconds
Started Nov 22 01:35:36 PM PST 23
Finished Nov 22 01:35:41 PM PST 23
Peak memory 230464 kb
Host smart-68aa48de-bdf4-4b54-b569-f85608f4e30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88236569573826872270524902273383090459916008413971107289812321117246828470133 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.edn_err.88236569573826872270524902273383090459916008413971107289812321117246828470133
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.106136563211398767232015063210262295473525942691426914956322018780240285340743
Short name T454
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 22 01:35:38 PM PST 23
Finished Nov 22 01:35:42 PM PST 23
Peak memory 205804 kb
Host smart-9cda2b68-34d0-4b14-90fa-95bada7d0b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106136563211398767232015063210262295473525942691426914956322018780240285340743 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 43.edn_genbits.106136563211398767232015063210262295473525942691426914956322018780240285340743
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.41903916012118743809514635959395187938624990553387850933365372823821624610283
Short name T650
Test name
Test status
Simulation time 18439183 ps
CPU time 1.17 seconds
Started Nov 22 01:35:38 PM PST 23
Finished Nov 22 01:35:42 PM PST 23
Peak memory 222244 kb
Host smart-04f93cc2-447e-441b-bd8d-057b051d2269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41903916012118743809514635959395187938624990553387850933365372823821624610283 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.edn_intr.41903916012118743809514635959395187938624990553387850933365372823821624610283
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.34288440379981754986947742544686235233221546514258866223093474605110430918841
Short name T381
Test name
Test status
Simulation time 13059183 ps
CPU time 0.86 seconds
Started Nov 22 01:35:37 PM PST 23
Finished Nov 22 01:35:41 PM PST 23
Peak memory 205360 kb
Host smart-b12f2347-7f52-422d-9f77-0ece82f3b967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34288440379981754986947742544686235233221546514258866223093474605110430918841 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 43.edn_smoke.34288440379981754986947742544686235233221546514258866223093474605110430918841
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.20482491467970533541911170301460361604771839091225058722072534722417707131118
Short name T822
Test name
Test status
Simulation time 154489183 ps
CPU time 3.97 seconds
Started Nov 22 01:35:38 PM PST 23
Finished Nov 22 01:35:45 PM PST 23
Peak memory 206372 kb
Host smart-7932834d-a78d-4698-9fed-413c12bb54da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20482491467970533541911170301460361604771839091225058722072534722417707131118 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.20482491467970533541911170301460361604771839091225058722072534722417707131118
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.98588894048207717479184886385127215720337970774581254369548226953338334801776
Short name T337
Test name
Test status
Simulation time 41708099183 ps
CPU time 1067.74 seconds
Started Nov 22 01:35:35 PM PST 23
Finished Nov 22 01:53:26 PM PST 23
Peak memory 215836 kb
Host smart-89d0b1cd-4134-496e-af19-320dabbcadd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985888940482077174791848863
85127215720337970774581254369548226953338334801776 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.98588894048
207717479184886385127215720337970774581254369548226953338334801776
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.94168521195800512932209981371798699579430495295644970081253096989764283934057
Short name T647
Test name
Test status
Simulation time 18259183 ps
CPU time 1 seconds
Started Nov 22 01:35:38 PM PST 23
Finished Nov 22 01:35:42 PM PST 23
Peak memory 205484 kb
Host smart-403b4fcb-3887-4aeb-b68a-437fb193b46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94168521195800512932209981371798699579430495295644970081253096989764283934057 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 44.edn_alert.94168521195800512932209981371798699579430495295644970081253096989764283934057
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.25000526540347156657622977716290284366177189999194213238345986465052949057964
Short name T309
Test name
Test status
Simulation time 28184990 ps
CPU time 0.89 seconds
Started Nov 22 01:35:39 PM PST 23
Finished Nov 22 01:35:43 PM PST 23
Peak memory 205476 kb
Host smart-6d2a1c90-df56-486d-bd62-0436d9bf3621
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25000526540347156657622977716290284366177189999194213238345986465052949057964 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.edn_alert_test.25000526540347156657622977716290284366177189999194213238345986465052949057964
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.58833110622226856325067962281150758704774874047938614622864289553239552619937
Short name T27
Test name
Test status
Simulation time 12219183 ps
CPU time 0.87 seconds
Started Nov 22 01:35:32 PM PST 23
Finished Nov 22 01:35:35 PM PST 23
Peak memory 214712 kb
Host smart-65a2bd4e-91c9-4fbc-a073-b18d652818b6
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58833110622226856325067962281150758704774874047938614622864289553239552619937 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.edn_disable.58833110622226856325067962281150758704774874047938614622864289553239552619937
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.107707203667658949937563812803647928797907097541473522237519024096954723355655
Short name T732
Test name
Test status
Simulation time 14969183 ps
CPU time 0.88 seconds
Started Nov 22 01:35:42 PM PST 23
Finished Nov 22 01:35:46 PM PST 23
Peak memory 214888 kb
Host smart-4b4fff2c-01d3-4cb9-869e-d1e3c1606164
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107707203667658949937563812803647928797907097541473522237519024096954723355655 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable_auto_req_mode.107707203667658949937563812803647928797907097541473522237
519024096954723355655
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.113830009308465457364336791260330255300991668302714255343970816639315934138357
Short name T368
Test name
Test status
Simulation time 24963823 ps
CPU time 1.23 seconds
Started Nov 22 01:35:42 PM PST 23
Finished Nov 22 01:35:47 PM PST 23
Peak memory 230440 kb
Host smart-1938d002-3788-4d41-8730-6b31c61a927a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113830009308465457364336791260330255300991668302714255343970816639315934138357 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.edn_err.113830009308465457364336791260330255300991668302714255343970816639315934138357
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.115726096546151738202395786284421787405074730717724409941499210070146783349049
Short name T769
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Nov 22 01:35:30 PM PST 23
Finished Nov 22 01:35:32 PM PST 23
Peak memory 205804 kb
Host smart-44cf8b16-bd02-4841-ac74-ef4144407d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115726096546151738202395786284421787405074730717724409941499210070146783349049 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 44.edn_genbits.115726096546151738202395786284421787405074730717724409941499210070146783349049
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.92889339101288787214453698085961037075656599294009748478263978781304027567265
Short name T883
Test name
Test status
Simulation time 18439183 ps
CPU time 1.1 seconds
Started Nov 22 01:35:40 PM PST 23
Finished Nov 22 01:35:44 PM PST 23
Peak memory 222260 kb
Host smart-6fefbc13-b9bb-4add-b50d-5adad1089b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92889339101288787214453698085961037075656599294009748478263978781304027567265 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.edn_intr.92889339101288787214453698085961037075656599294009748478263978781304027567265
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.69599908462387972179741223533974287930935524974619186519101208740060672524389
Short name T444
Test name
Test status
Simulation time 13059183 ps
CPU time 0.83 seconds
Started Nov 22 01:35:33 PM PST 23
Finished Nov 22 01:35:35 PM PST 23
Peak memory 205268 kb
Host smart-8a271160-2ec3-4c0d-8689-fbf5a7bf5d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69599908462387972179741223533974287930935524974619186519101208740060672524389 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 44.edn_smoke.69599908462387972179741223533974287930935524974619186519101208740060672524389
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.57624136207700737737125126367795120630118244135681762249773256504847292294122
Short name T543
Test name
Test status
Simulation time 154489183 ps
CPU time 3.95 seconds
Started Nov 22 01:35:40 PM PST 23
Finished Nov 22 01:35:46 PM PST 23
Peak memory 206296 kb
Host smart-71a53408-baf0-42ca-bad2-5048b05c3991
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57624136207700737737125126367795120630118244135681762249773256504847292294122 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.57624136207700737737125126367795120630118244135681762249773256504847292294122
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.15951820170895669479233591488104733806273196472864541289114953837624248593473
Short name T483
Test name
Test status
Simulation time 41708099183 ps
CPU time 1073.78 seconds
Started Nov 22 01:35:38 PM PST 23
Finished Nov 22 01:53:35 PM PST 23
Peak memory 215880 kb
Host smart-afd05dcb-0887-44f2-8b41-24c2a0deea69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159518201708956694792335914
88104733806273196472864541289114953837624248593473 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.15951820170
895669479233591488104733806273196472864541289114953837624248593473
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.114776435649206049802907033355450158495433847612729176574572004809601290898746
Short name T450
Test name
Test status
Simulation time 18259183 ps
CPU time 0.99 seconds
Started Nov 22 01:35:39 PM PST 23
Finished Nov 22 01:35:43 PM PST 23
Peak memory 205568 kb
Host smart-afac9f83-712b-459d-a2cc-becab1b0583d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114776435649206049802907033355450158495433847612729176574572004809601290898746 -assert nopostproc +UVM_TESTNAME=edn_aler
t_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 45.edn_alert.114776435649206049802907033355450158495433847612729176574572004809601290898746
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.50445217472659440687203622058832829288427053200817968969248769155772800625323
Short name T945
Test name
Test status
Simulation time 28184990 ps
CPU time 0.86 seconds
Started Nov 22 01:35:40 PM PST 23
Finished Nov 22 01:35:43 PM PST 23
Peak memory 205524 kb
Host smart-2b7b88ea-2029-4002-be7a-9ca5fdbabbf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50445217472659440687203622058832829288427053200817968969248769155772800625323 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.edn_alert_test.50445217472659440687203622058832829288427053200817968969248769155772800625323
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.48384828810072136288247101901276952042863936573237502233855588126295026065938
Short name T730
Test name
Test status
Simulation time 12219183 ps
CPU time 0.86 seconds
Started Nov 22 01:35:39 PM PST 23
Finished Nov 22 01:35:42 PM PST 23
Peak memory 214768 kb
Host smart-9bee68e0-880c-494a-857e-03245b556214
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48384828810072136288247101901276952042863936573237502233855588126295026065938 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.edn_disable.48384828810072136288247101901276952042863936573237502233855588126295026065938
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.24134427840740784510591893931229160351864349542824211317142708015670773152077
Short name T715
Test name
Test status
Simulation time 14969183 ps
CPU time 0.92 seconds
Started Nov 22 01:35:42 PM PST 23
Finished Nov 22 01:35:47 PM PST 23
Peak memory 214920 kb
Host smart-b0b0df13-5610-4dea-b16a-60c0352082c7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24134427840740784510591893931229160351864349542824211317142708015670773152077 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable_auto_req_mode.2413442784074078451059189393122916035186434954282421131714
2708015670773152077
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.30882250186859997259009283480583914879385355321568134130201467439677078533787
Short name T938
Test name
Test status
Simulation time 24963823 ps
CPU time 1.2 seconds
Started Nov 22 01:35:40 PM PST 23
Finished Nov 22 01:35:45 PM PST 23
Peak memory 230408 kb
Host smart-8e3bdf9a-9569-4203-9949-3f9eff2ed5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30882250186859997259009283480583914879385355321568134130201467439677078533787 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.edn_err.30882250186859997259009283480583914879385355321568134130201467439677078533787
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.51030715189730138394088254578378346284152777295482649950702878528614383813515
Short name T786
Test name
Test status
Simulation time 17999183 ps
CPU time 1.04 seconds
Started Nov 22 01:35:38 PM PST 23
Finished Nov 22 01:35:42 PM PST 23
Peak memory 205668 kb
Host smart-7b13283f-0dc8-45e1-a287-3370534ee5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51030715189730138394088254578378346284152777295482649950702878528614383813515 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.edn_genbits.51030715189730138394088254578378346284152777295482649950702878528614383813515
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.65079781975685669372319876989805569426722903440338167403697243117980167900886
Short name T36
Test name
Test status
Simulation time 18439183 ps
CPU time 1.13 seconds
Started Nov 22 01:35:39 PM PST 23
Finished Nov 22 01:35:43 PM PST 23
Peak memory 222272 kb
Host smart-bbc40215-1128-4f93-a23c-5d5cec246160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65079781975685669372319876989805569426722903440338167403697243117980167900886 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.edn_intr.65079781975685669372319876989805569426722903440338167403697243117980167900886
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.31215896204169960132813283898195651386996507888672894711558387309565649894190
Short name T856
Test name
Test status
Simulation time 13059183 ps
CPU time 0.86 seconds
Started Nov 22 01:35:37 PM PST 23
Finished Nov 22 01:35:41 PM PST 23
Peak memory 205256 kb
Host smart-8a4bb857-c24d-4d38-b0e0-24baae90b417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31215896204169960132813283898195651386996507888672894711558387309565649894190 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 45.edn_smoke.31215896204169960132813283898195651386996507888672894711558387309565649894190
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.37299908374374634880987269020790613340776202296949123743174259161973036479053
Short name T906
Test name
Test status
Simulation time 154489183 ps
CPU time 4.01 seconds
Started Nov 22 01:35:39 PM PST 23
Finished Nov 22 01:35:45 PM PST 23
Peak memory 206376 kb
Host smart-a5f55099-eabc-48ac-9ae3-2f9deb4950f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37299908374374634880987269020790613340776202296949123743174259161973036479053 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.37299908374374634880987269020790613340776202296949123743174259161973036479053
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.3920508421134776853605644030349625402506554713205063681025938504108404866980
Short name T847
Test name
Test status
Simulation time 41708099183 ps
CPU time 1065.84 seconds
Started Nov 22 01:35:41 PM PST 23
Finished Nov 22 01:53:31 PM PST 23
Peak memory 215788 kb
Host smart-3570e0f4-8232-4a88-9f12-71e9a9e78ac7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392050842113477685360564403
0349625402506554713205063681025938504108404866980 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.392050842113
4776853605644030349625402506554713205063681025938504108404866980
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.115255166628850571976309859276277929004123088327053244686876551732121458645827
Short name T885
Test name
Test status
Simulation time 18259183 ps
CPU time 1.01 seconds
Started Nov 22 01:35:40 PM PST 23
Finished Nov 22 01:35:44 PM PST 23
Peak memory 205612 kb
Host smart-dfbe9290-7d31-4256-b86a-91e1a4044ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115255166628850571976309859276277929004123088327053244686876551732121458645827 -assert nopostproc +UVM_TESTNAME=edn_aler
t_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 46.edn_alert.115255166628850571976309859276277929004123088327053244686876551732121458645827
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.101961853682910596106717776415725275159837946667625193657731055572527168432532
Short name T587
Test name
Test status
Simulation time 28184990 ps
CPU time 0.9 seconds
Started Nov 22 01:35:42 PM PST 23
Finished Nov 22 01:35:47 PM PST 23
Peak memory 205536 kb
Host smart-817a1ed9-4e5b-4d4c-8506-5ba9080e4ec2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101961853682910596106717776415725275159837946667625193657731055572527168432532 -assert nopostp
roc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 46.edn_alert_test.101961853682910596106717776415725275159837946667625193657731055572527168432532
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.51727710791425848392479554142520323224577064454909460886969329231098530573437
Short name T911
Test name
Test status
Simulation time 12219183 ps
CPU time 0.95 seconds
Started Nov 22 01:35:38 PM PST 23
Finished Nov 22 01:35:42 PM PST 23
Peak memory 214916 kb
Host smart-1b4b0222-3dbb-4dc0-aff7-2548e05e9d2a
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51727710791425848392479554142520323224577064454909460886969329231098530573437 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.edn_disable.51727710791425848392479554142520323224577064454909460886969329231098530573437
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.38769907734279508541048062797551649227173560249274925717428069946296730795441
Short name T320
Test name
Test status
Simulation time 14969183 ps
CPU time 0.98 seconds
Started Nov 22 01:35:43 PM PST 23
Finished Nov 22 01:35:47 PM PST 23
Peak memory 214920 kb
Host smart-7440915a-0720-4dc2-b008-9ed28cd3bf79
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38769907734279508541048062797551649227173560249274925717428069946296730795441 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable_auto_req_mode.3876990773427950854104806279755164922717356024927492571742
8069946296730795441
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.6258802801046147657415412006793450522089037910510965556533584283142667069306
Short name T645
Test name
Test status
Simulation time 24963823 ps
CPU time 1.19 seconds
Started Nov 22 01:35:37 PM PST 23
Finished Nov 22 01:35:42 PM PST 23
Peak memory 230420 kb
Host smart-ff5cda1d-d358-4c7e-8e45-e742e9583a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6258802801046147657415412006793450522089037910510965556533584283142667069306 -assert nopostproc +UVM_TESTNAME=edn_err_te
st +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
edn_err.6258802801046147657415412006793450522089037910510965556533584283142667069306
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.38929291319722584406790079925222459205650224911857521989774019455574393492590
Short name T752
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 22 01:35:39 PM PST 23
Finished Nov 22 01:35:43 PM PST 23
Peak memory 205848 kb
Host smart-c296b33b-3c68-4dea-abca-5a64f55d3ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38929291319722584406790079925222459205650224911857521989774019455574393492590 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.edn_genbits.38929291319722584406790079925222459205650224911857521989774019455574393492590
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.59584810393426348134571359182540689928867815654134157786057130677302478113569
Short name T690
Test name
Test status
Simulation time 18439183 ps
CPU time 1.17 seconds
Started Nov 22 01:35:43 PM PST 23
Finished Nov 22 01:35:47 PM PST 23
Peak memory 222284 kb
Host smart-30c88b92-b8e6-4dbe-9a9e-7ced2aefc29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59584810393426348134571359182540689928867815654134157786057130677302478113569 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.edn_intr.59584810393426348134571359182540689928867815654134157786057130677302478113569
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.113994653871023421304808925830633263236972188834823047668288603345766748810124
Short name T698
Test name
Test status
Simulation time 13059183 ps
CPU time 0.9 seconds
Started Nov 22 01:35:41 PM PST 23
Finished Nov 22 01:35:45 PM PST 23
Peak memory 205308 kb
Host smart-1386adb9-0482-4f93-a244-37d3b22230e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113994653871023421304808925830633263236972188834823047668288603345766748810124 -assert nopostproc +UVM_TESTNAME=edn_smok
e_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 46.edn_smoke.113994653871023421304808925830633263236972188834823047668288603345766748810124
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.113241611628120547719055393213264979522508098464612587559962521277843616788049
Short name T758
Test name
Test status
Simulation time 154489183 ps
CPU time 3.77 seconds
Started Nov 22 01:35:41 PM PST 23
Finished Nov 22 01:35:47 PM PST 23
Peak memory 206400 kb
Host smart-6856ea72-0fd1-4f67-9046-fe9f03b01fc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113241611628120547719055393213264979522508098464612587559962521277843616788049 -assert nopo
stproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.113241611628120547719055393213264979522508098464612587559962521277843616788049
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.60993369796017220729418530336346536440342520415009417416351200999893342286966
Short name T708
Test name
Test status
Simulation time 41708099183 ps
CPU time 1058.36 seconds
Started Nov 22 01:35:38 PM PST 23
Finished Nov 22 01:53:20 PM PST 23
Peak memory 215872 kb
Host smart-ec04812b-ef99-464e-9b37-73866dca46bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609933697960172207294185303
36346536440342520415009417416351200999893342286966 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.60993369796
017220729418530336346536440342520415009417416351200999893342286966
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.11480663491775970023122130479625852540450892258795742692754634446935081584854
Short name T695
Test name
Test status
Simulation time 18259183 ps
CPU time 0.96 seconds
Started Nov 22 01:35:42 PM PST 23
Finished Nov 22 01:35:47 PM PST 23
Peak memory 205608 kb
Host smart-d1810306-e6fc-4d8f-bd16-5ae2120577e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11480663491775970023122130479625852540450892258795742692754634446935081584854 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 47.edn_alert.11480663491775970023122130479625852540450892258795742692754634446935081584854
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.64649447752212788469046937274941387470207802856738518906589021597684219291010
Short name T595
Test name
Test status
Simulation time 28184990 ps
CPU time 0.88 seconds
Started Nov 22 01:35:46 PM PST 23
Finished Nov 22 01:35:49 PM PST 23
Peak memory 205424 kb
Host smart-37dd5587-f000-45e6-9ffc-1c50a22bbd7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64649447752212788469046937274941387470207802856738518906589021597684219291010 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.edn_alert_test.64649447752212788469046937274941387470207802856738518906589021597684219291010
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.39545685639664181496438153159177234310374837494172196936171692808386285338818
Short name T423
Test name
Test status
Simulation time 12219183 ps
CPU time 0.87 seconds
Started Nov 22 01:35:42 PM PST 23
Finished Nov 22 01:35:46 PM PST 23
Peak memory 214900 kb
Host smart-81b77168-5d1d-4c25-8a49-bb6e88979b67
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39545685639664181496438153159177234310374837494172196936171692808386285338818 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.edn_disable.39545685639664181496438153159177234310374837494172196936171692808386285338818
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.9396931401034658902064760211385984094853397044991659809837641090272760768083
Short name T383
Test name
Test status
Simulation time 14969183 ps
CPU time 0.96 seconds
Started Nov 22 01:35:42 PM PST 23
Finished Nov 22 01:35:46 PM PST 23
Peak memory 214916 kb
Host smart-567b046c-42a6-40a4-a0c5-aa0eb8c3b961
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9396931401034658902064760211385984094853397044991659809837641090272760768083 -assert nopostproc
+UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable_auto_req_mode.93969314010346589020647602113859840948533970449916598098376
41090272760768083
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.91921685909306575586327186408702537381423678283778378137883553076270683284431
Short name T823
Test name
Test status
Simulation time 24963823 ps
CPU time 1.12 seconds
Started Nov 22 01:35:42 PM PST 23
Finished Nov 22 01:35:47 PM PST 23
Peak memory 230528 kb
Host smart-136ec2e7-b1ea-4c85-8cce-290ad9136a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91921685909306575586327186408702537381423678283778378137883553076270683284431 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.edn_err.91921685909306575586327186408702537381423678283778378137883553076270683284431
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.27094600090626628957597507339432510692573358677215630221503318644407158127033
Short name T408
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:35:42 PM PST 23
Finished Nov 22 01:35:47 PM PST 23
Peak memory 205848 kb
Host smart-ea864924-c35b-479b-9ee6-812776a7a402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27094600090626628957597507339432510692573358677215630221503318644407158127033 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.edn_genbits.27094600090626628957597507339432510692573358677215630221503318644407158127033
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.96639574576160688933313218559820891151630460233240447795878333466891588196846
Short name T541
Test name
Test status
Simulation time 18439183 ps
CPU time 1.18 seconds
Started Nov 22 01:35:43 PM PST 23
Finished Nov 22 01:35:47 PM PST 23
Peak memory 222332 kb
Host smart-ca9ba37e-c453-401e-8d71-29f79ca3d15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96639574576160688933313218559820891151630460233240447795878333466891588196846 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.edn_intr.96639574576160688933313218559820891151630460233240447795878333466891588196846
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.38930274266442470685288890626570025828566215965202138377590685915092870288406
Short name T428
Test name
Test status
Simulation time 13059183 ps
CPU time 0.87 seconds
Started Nov 22 01:35:41 PM PST 23
Finished Nov 22 01:35:46 PM PST 23
Peak memory 205368 kb
Host smart-416c0116-934b-4a73-9e41-0bf224749e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38930274266442470685288890626570025828566215965202138377590685915092870288406 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 47.edn_smoke.38930274266442470685288890626570025828566215965202138377590685915092870288406
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.77345315679598561311560475771300667199948635528954954919551735482811690018198
Short name T265
Test name
Test status
Simulation time 154489183 ps
CPU time 4.03 seconds
Started Nov 22 01:35:40 PM PST 23
Finished Nov 22 01:35:47 PM PST 23
Peak memory 206392 kb
Host smart-cc7b5e97-7170-4739-ab8a-62636da4a9c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77345315679598561311560475771300667199948635528954954919551735482811690018198 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.77345315679598561311560475771300667199948635528954954919551735482811690018198
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.2348851617145708457240181110919460407460341086567486026797693716762408227626
Short name T594
Test name
Test status
Simulation time 41708099183 ps
CPU time 1076.36 seconds
Started Nov 22 01:35:40 PM PST 23
Finished Nov 22 01:53:39 PM PST 23
Peak memory 215888 kb
Host smart-202d1db1-1308-4fc3-8826-0bdc415606f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234885161714570845724018111
0919460407460341086567486026797693716762408227626 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.234885161714
5708457240181110919460407460341086567486026797693716762408227626
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.81870288954872548320382623335810769896505152915495042698375729514195901437600
Short name T348
Test name
Test status
Simulation time 18259183 ps
CPU time 0.95 seconds
Started Nov 22 01:35:44 PM PST 23
Finished Nov 22 01:35:48 PM PST 23
Peak memory 205488 kb
Host smart-8b4c3ba3-5369-438c-8af6-6a9320384e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81870288954872548320382623335810769896505152915495042698375729514195901437600 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 48.edn_alert.81870288954872548320382623335810769896505152915495042698375729514195901437600
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.48444320420418017962421379531735246804434853672378827089660314832387594016797
Short name T912
Test name
Test status
Simulation time 28184990 ps
CPU time 0.86 seconds
Started Nov 22 01:35:34 PM PST 23
Finished Nov 22 01:35:37 PM PST 23
Peak memory 205540 kb
Host smart-e30f2448-65fb-4212-a4c6-c08f273de704
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48444320420418017962421379531735246804434853672378827089660314832387594016797 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.edn_alert_test.48444320420418017962421379531735246804434853672378827089660314832387594016797
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.98847260750247593415036035909032862431646864251275093213002326661164598578619
Short name T849
Test name
Test status
Simulation time 12219183 ps
CPU time 0.86 seconds
Started Nov 22 01:35:40 PM PST 23
Finished Nov 22 01:35:43 PM PST 23
Peak memory 214836 kb
Host smart-b265243c-7ac7-44b6-bed6-2546335a7bcf
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98847260750247593415036035909032862431646864251275093213002326661164598578619 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.edn_disable.98847260750247593415036035909032862431646864251275093213002326661164598578619
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.40109916722265728482670783835965681110430169610797069659713431777422035838049
Short name T630
Test name
Test status
Simulation time 14969183 ps
CPU time 0.86 seconds
Started Nov 22 01:35:40 PM PST 23
Finished Nov 22 01:35:43 PM PST 23
Peak memory 214828 kb
Host smart-cdb23053-a2e9-493c-9c90-1fd7e17c77bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40109916722265728482670783835965681110430169610797069659713431777422035838049 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable_auto_req_mode.4010991672226572848267078383596568111043016961079706965971
3431777422035838049
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.97655468810683184406296939822770168621417595712781989748806213304977796631491
Short name T352
Test name
Test status
Simulation time 24963823 ps
CPU time 1.15 seconds
Started Nov 22 01:35:40 PM PST 23
Finished Nov 22 01:35:44 PM PST 23
Peak memory 230404 kb
Host smart-371c5e11-9bb3-4880-8b6e-f6596b5a985e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97655468810683184406296939822770168621417595712781989748806213304977796631491 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.edn_err.97655468810683184406296939822770168621417595712781989748806213304977796631491
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.16702693368026188437440589636123000510838419142021710328138509251653733023146
Short name T297
Test name
Test status
Simulation time 17999183 ps
CPU time 1.06 seconds
Started Nov 22 01:35:45 PM PST 23
Finished Nov 22 01:35:48 PM PST 23
Peak memory 205668 kb
Host smart-3cea07eb-34e7-482f-bc16-f05aadd04b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16702693368026188437440589636123000510838419142021710328138509251653733023146 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.edn_genbits.16702693368026188437440589636123000510838419142021710328138509251653733023146
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.64488536166233596786868123996173068913847707010562036090425832585690435079923
Short name T739
Test name
Test status
Simulation time 18439183 ps
CPU time 1.11 seconds
Started Nov 22 01:35:45 PM PST 23
Finished Nov 22 01:35:48 PM PST 23
Peak memory 222088 kb
Host smart-da51feed-829c-413d-9232-0272162379fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64488536166233596786868123996173068913847707010562036090425832585690435079923 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.edn_intr.64488536166233596786868123996173068913847707010562036090425832585690435079923
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.13431236693700687742218868087969576941208136685752807619782126509757197310675
Short name T771
Test name
Test status
Simulation time 13059183 ps
CPU time 0.84 seconds
Started Nov 22 01:35:43 PM PST 23
Finished Nov 22 01:35:47 PM PST 23
Peak memory 205400 kb
Host smart-e890b826-4cf3-4423-b022-b7403b1067ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13431236693700687742218868087969576941208136685752807619782126509757197310675 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 48.edn_smoke.13431236693700687742218868087969576941208136685752807619782126509757197310675
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.27014820020351351410031830699808489576878971477587897337894865982960094995928
Short name T313
Test name
Test status
Simulation time 154489183 ps
CPU time 4.07 seconds
Started Nov 22 01:35:42 PM PST 23
Finished Nov 22 01:35:50 PM PST 23
Peak memory 206400 kb
Host smart-7325aaa5-a6b8-499c-ab07-5e694eb8c4e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27014820020351351410031830699808489576878971477587897337894865982960094995928 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.27014820020351351410031830699808489576878971477587897337894865982960094995928
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.84549005934231011422591791561184435512537678807869549914246154255707078691976
Short name T517
Test name
Test status
Simulation time 41708099183 ps
CPU time 1049.62 seconds
Started Nov 22 01:35:44 PM PST 23
Finished Nov 22 01:53:16 PM PST 23
Peak memory 215764 kb
Host smart-f671b1b1-8992-45d2-86d9-2ac8762c928a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845490059342310114225917915
61184435512537678807869549914246154255707078691976 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.84549005934
231011422591791561184435512537678807869549914246154255707078691976
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.72412868140956266491592275711376461874740127514728222362441151637212233995776
Short name T720
Test name
Test status
Simulation time 18259183 ps
CPU time 1 seconds
Started Nov 22 01:35:38 PM PST 23
Finished Nov 22 01:35:42 PM PST 23
Peak memory 205560 kb
Host smart-7cd6dcc3-e508-4610-83a1-cd7039a67f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72412868140956266491592275711376461874740127514728222362441151637212233995776 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 49.edn_alert.72412868140956266491592275711376461874740127514728222362441151637212233995776
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.42704731194755504332748328973936680305027749515272935366514917955475748660825
Short name T807
Test name
Test status
Simulation time 28184990 ps
CPU time 0.85 seconds
Started Nov 22 01:35:35 PM PST 23
Finished Nov 22 01:35:40 PM PST 23
Peak memory 205444 kb
Host smart-31f00762-0b3f-45d2-8614-446b00703e4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42704731194755504332748328973936680305027749515272935366514917955475748660825 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.edn_alert_test.42704731194755504332748328973936680305027749515272935366514917955475748660825
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.91365222325310757404480336087815190830740728763060652818327465882557500557499
Short name T70
Test name
Test status
Simulation time 12219183 ps
CPU time 0.82 seconds
Started Nov 22 01:35:36 PM PST 23
Finished Nov 22 01:35:40 PM PST 23
Peak memory 214808 kb
Host smart-e3fcf8fc-2353-4a84-8fcb-1abd592a2b63
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91365222325310757404480336087815190830740728763060652818327465882557500557499 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.edn_disable.91365222325310757404480336087815190830740728763060652818327465882557500557499
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.59101478418363849260745756974167642535761502471505439546848250862669085214250
Short name T22
Test name
Test status
Simulation time 14969183 ps
CPU time 0.87 seconds
Started Nov 22 01:35:35 PM PST 23
Finished Nov 22 01:35:40 PM PST 23
Peak memory 214800 kb
Host smart-59b0d3d0-a21d-4b68-9c33-6a6982ca420f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59101478418363849260745756974167642535761502471505439546848250862669085214250 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable_auto_req_mode.5910147841836384926074575697416764253576150247150543954684
8250862669085214250
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.27845600128736613516115190025125241177775218602716367268319218073565728620517
Short name T977
Test name
Test status
Simulation time 24963823 ps
CPU time 1.23 seconds
Started Nov 22 01:35:34 PM PST 23
Finished Nov 22 01:35:38 PM PST 23
Peak memory 230496 kb
Host smart-78192f08-5573-4741-bdba-50500efb7fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27845600128736613516115190025125241177775218602716367268319218073565728620517 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.edn_err.27845600128736613516115190025125241177775218602716367268319218073565728620517
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.55308869747923123521021988414490822053612188438487574814672806404725511035185
Short name T913
Test name
Test status
Simulation time 17999183 ps
CPU time 1.05 seconds
Started Nov 22 01:35:36 PM PST 23
Finished Nov 22 01:35:41 PM PST 23
Peak memory 205740 kb
Host smart-0cecb1f4-809e-4a73-9e0d-07e62a311dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55308869747923123521021988414490822053612188438487574814672806404725511035185 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.edn_genbits.55308869747923123521021988414490822053612188438487574814672806404725511035185
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.8361422492265318201969345430079678327944869738610472638309394766634799495070
Short name T813
Test name
Test status
Simulation time 18439183 ps
CPU time 1.06 seconds
Started Nov 22 01:35:33 PM PST 23
Finished Nov 22 01:35:35 PM PST 23
Peak memory 222172 kb
Host smart-d3f5d1fe-4b3a-46ba-b25e-5595fe525a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8361422492265318201969345430079678327944869738610472638309394766634799495070 -assert nopostproc +UVM_TESTNAME=edn_intr_t
est +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.edn_intr.8361422492265318201969345430079678327944869738610472638309394766634799495070
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.38592991480959497143709319987615563193835307836812279048670909552407907210002
Short name T875
Test name
Test status
Simulation time 13059183 ps
CPU time 0.86 seconds
Started Nov 22 01:35:40 PM PST 23
Finished Nov 22 01:35:43 PM PST 23
Peak memory 205340 kb
Host smart-a052880d-64df-4b2f-a5db-8eef02c4895d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38592991480959497143709319987615563193835307836812279048670909552407907210002 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 49.edn_smoke.38592991480959497143709319987615563193835307836812279048670909552407907210002
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.57511812244472520359353654187722393141462069198081286392793304892173290132834
Short name T465
Test name
Test status
Simulation time 154489183 ps
CPU time 3.91 seconds
Started Nov 22 01:35:39 PM PST 23
Finished Nov 22 01:35:46 PM PST 23
Peak memory 206336 kb
Host smart-0fa3333c-c7cd-439a-be7d-77dfe6d56155
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57511812244472520359353654187722393141462069198081286392793304892173290132834 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.57511812244472520359353654187722393141462069198081286392793304892173290132834
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.36351588444058363523882933187100272811445976320356710261372409110945065389741
Short name T44
Test name
Test status
Simulation time 41708099183 ps
CPU time 1100.24 seconds
Started Nov 22 01:35:34 PM PST 23
Finished Nov 22 01:53:56 PM PST 23
Peak memory 215880 kb
Host smart-da725b98-d2d4-43bb-a4e6-7270e1006dad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363515884440583635238829331
87100272811445976320356710261372409110945065389741 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.36351588444
058363523882933187100272811445976320356710261372409110945065389741
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.99752996312341457656244707655919371060913475471066253912685467285842658975722
Short name T834
Test name
Test status
Simulation time 18259183 ps
CPU time 0.99 seconds
Started Nov 22 01:31:49 PM PST 23
Finished Nov 22 01:31:51 PM PST 23
Peak memory 205468 kb
Host smart-b0f857a8-e594-4488-b832-3d5cfba40de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99752996312341457656244707655919371060913475471066253912685467285842658975722 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.edn_alert.99752996312341457656244707655919371060913475471066253912685467285842658975722
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.70250663615441963327093505328105649820218226047080582637887158227164694232578
Short name T567
Test name
Test status
Simulation time 28184990 ps
CPU time 0.86 seconds
Started Nov 22 01:31:52 PM PST 23
Finished Nov 22 01:31:54 PM PST 23
Peak memory 205408 kb
Host smart-6a83542a-5cf3-4a08-b30c-6bc1acf27375
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70250663615441963327093505328105649820218226047080582637887158227164694232578 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.edn_alert_test.70250663615441963327093505328105649820218226047080582637887158227164694232578
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.107370081783700732205941081475601859917248718390178417636427946008605035235912
Short name T29
Test name
Test status
Simulation time 12219183 ps
CPU time 0.85 seconds
Started Nov 22 01:31:51 PM PST 23
Finished Nov 22 01:31:53 PM PST 23
Peak memory 214860 kb
Host smart-7a3b9c40-b83b-4a19-86f7-00c9b1d80e9d
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107370081783700732205941081475601859917248718390178417636427946008605035235912 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 5.edn_disable.107370081783700732205941081475601859917248718390178417636427946008605035235912
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.43111428475674967317870261066385191289089611727205153564109406972754386720157
Short name T817
Test name
Test status
Simulation time 14969183 ps
CPU time 0.89 seconds
Started Nov 22 01:31:50 PM PST 23
Finished Nov 22 01:31:51 PM PST 23
Peak memory 214888 kb
Host smart-7c153825-411b-4389-9e89-9d52d6aade90
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43111428475674967317870261066385191289089611727205153564109406972754386720157 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable_auto_req_mode.43111428475674967317870261066385191289089611727205153564109
406972754386720157
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.65986552802244671564843646979758139693315402006678739930929198165424578891483
Short name T871
Test name
Test status
Simulation time 24963823 ps
CPU time 1.12 seconds
Started Nov 22 01:31:50 PM PST 23
Finished Nov 22 01:31:53 PM PST 23
Peak memory 230500 kb
Host smart-d126b76c-12c0-4f41-8696-0627a61115ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65986552802244671564843646979758139693315402006678739930929198165424578891483 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
edn_err.65986552802244671564843646979758139693315402006678739930929198165424578891483
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.85340978041208436009750622352229832689223255984398411080607528404921242511533
Short name T477
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:31:50 PM PST 23
Finished Nov 22 01:31:52 PM PST 23
Peak memory 205868 kb
Host smart-85ce15b8-548f-41be-99ee-638aee9f32b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85340978041208436009750622352229832689223255984398411080607528404921242511533 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.edn_genbits.85340978041208436009750622352229832689223255984398411080607528404921242511533
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.110452837506097502431048630719335028448034395278291773514775457054702206532687
Short name T515
Test name
Test status
Simulation time 18439183 ps
CPU time 1.14 seconds
Started Nov 22 01:31:53 PM PST 23
Finished Nov 22 01:31:55 PM PST 23
Peak memory 222188 kb
Host smart-9ee41e6a-cafc-4e99-9342-1e35fadc74b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110452837506097502431048630719335028448034395278291773514775457054702206532687 -assert nopostproc +UVM_TESTNAME=edn_intr
_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.edn_intr.110452837506097502431048630719335028448034395278291773514775457054702206532687
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.92137370556235751216321079581000428770339384136363066242241552862500072169893
Short name T94
Test name
Test status
Simulation time 11759183 ps
CPU time 0.87 seconds
Started Nov 22 01:31:51 PM PST 23
Finished Nov 22 01:31:53 PM PST 23
Peak memory 205224 kb
Host smart-a7f0cc40-9a5d-4bbc-9334-b4d8a7022183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92137370556235751216321079581000428770339384136363066242241552862500072169893 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.edn_regwen.92137370556235751216321079581000428770339384136363066242241552862500072169893
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.51826469858042647273727366789658685837065731105087715227523220509685801902088
Short name T908
Test name
Test status
Simulation time 13059183 ps
CPU time 0.85 seconds
Started Nov 22 01:31:49 PM PST 23
Finished Nov 22 01:31:51 PM PST 23
Peak memory 205328 kb
Host smart-57acf5c5-9c03-4348-a5f6-3c1d47233a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51826469858042647273727366789658685837065731105087715227523220509685801902088 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.edn_smoke.51826469858042647273727366789658685837065731105087715227523220509685801902088
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.10998469907689464998224167289441137737882445467744564499385287889533542874264
Short name T238
Test name
Test status
Simulation time 154489183 ps
CPU time 4.03 seconds
Started Nov 22 01:31:50 PM PST 23
Finished Nov 22 01:31:55 PM PST 23
Peak memory 206372 kb
Host smart-9144d91f-d7a9-48e2-8b96-4dd7710781d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10998469907689464998224167289441137737882445467744564499385287889533542874264 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.10998469907689464998224167289441137737882445467744564499385287889533542874264
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.62033984834902903242650186543856227792642423526705618347563924351895090721615
Short name T499
Test name
Test status
Simulation time 41708099183 ps
CPU time 1047.13 seconds
Started Nov 22 01:31:49 PM PST 23
Finished Nov 22 01:49:18 PM PST 23
Peak memory 215832 kb
Host smart-7837e568-d670-4863-a616-1e23d71d841d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620339848349029032426501865
43856227792642423526705618347563924351895090721615 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.620339848349
02903242650186543856227792642423526705618347563924351895090721615
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.12622369485542992187416775749172868090681475035146958744324979434716417981044
Short name T556
Test name
Test status
Simulation time 24963823 ps
CPU time 1.08 seconds
Started Nov 22 01:35:39 PM PST 23
Finished Nov 22 01:35:43 PM PST 23
Peak memory 230304 kb
Host smart-3a6dc67e-212e-4035-b2e8-864e615bdb22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12622369485542992187416775749172868090681475035146958744324979434716417981044 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50
.edn_err.12622369485542992187416775749172868090681475035146958744324979434716417981044
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.17087094365633520468302121578348455900811515016497486282661309890440513072693
Short name T245
Test name
Test status
Simulation time 17999183 ps
CPU time 1.15 seconds
Started Nov 22 01:35:35 PM PST 23
Finished Nov 22 01:35:40 PM PST 23
Peak memory 205840 kb
Host smart-cb1ec0fd-d8fb-4476-a00f-9e3fd3feab7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17087094365633520468302121578348455900811515016497486282661309890440513072693 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 50.edn_genbits.17087094365633520468302121578348455900811515016497486282661309890440513072693
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.44430456561276265886888009586890209507755434271009064395524989442424381873838
Short name T669
Test name
Test status
Simulation time 24963823 ps
CPU time 1.14 seconds
Started Nov 22 01:35:38 PM PST 23
Finished Nov 22 01:35:42 PM PST 23
Peak memory 230368 kb
Host smart-c84485ba-06c6-4fa7-bc6d-bf0473186b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44430456561276265886888009586890209507755434271009064395524989442424381873838 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51
.edn_err.44430456561276265886888009586890209507755434271009064395524989442424381873838
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.76544253733920605363808139583494190847062748578684516864465563017379931398199
Short name T508
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:35:36 PM PST 23
Finished Nov 22 01:35:41 PM PST 23
Peak memory 205804 kb
Host smart-903036ae-54e2-440f-bac6-ff1e124ab678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76544253733920605363808139583494190847062748578684516864465563017379931398199 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 51.edn_genbits.76544253733920605363808139583494190847062748578684516864465563017379931398199
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.79435818093566880285802818514251539266139637206768375632992150783120003812984
Short name T918
Test name
Test status
Simulation time 24963823 ps
CPU time 1.1 seconds
Started Nov 22 01:35:32 PM PST 23
Finished Nov 22 01:35:35 PM PST 23
Peak memory 230412 kb
Host smart-a0662ef1-a539-4e4b-ac49-e9226127aaa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79435818093566880285802818514251539266139637206768375632992150783120003812984 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52
.edn_err.79435818093566880285802818514251539266139637206768375632992150783120003812984
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.41566920607065864091301636994127291225954741927706505651894168907463895194158
Short name T246
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Nov 22 01:35:35 PM PST 23
Finished Nov 22 01:35:39 PM PST 23
Peak memory 205820 kb
Host smart-ddbad2fd-3d1c-46a1-88c8-0295feaf2d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41566920607065864091301636994127291225954741927706505651894168907463895194158 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 52.edn_genbits.41566920607065864091301636994127291225954741927706505651894168907463895194158
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.115725739088163218444853731234888701606297304815797618436869633199619162367313
Short name T398
Test name
Test status
Simulation time 24963823 ps
CPU time 1.08 seconds
Started Nov 22 01:35:38 PM PST 23
Finished Nov 22 01:35:42 PM PST 23
Peak memory 230312 kb
Host smart-0c22c63e-184d-48f4-b8ba-36e4a8f01e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115725739088163218444853731234888701606297304815797618436869633199619162367313 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
3.edn_err.115725739088163218444853731234888701606297304815797618436869633199619162367313
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.85354420396938850156465434804587906293779375074755166177657258149407059153027
Short name T535
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 22 01:35:38 PM PST 23
Finished Nov 22 01:35:42 PM PST 23
Peak memory 205768 kb
Host smart-b5868e64-4cd6-4990-ad39-8f6de5ee12c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85354420396938850156465434804587906293779375074755166177657258149407059153027 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 53.edn_genbits.85354420396938850156465434804587906293779375074755166177657258149407059153027
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.74187959926176347335031719350374015907380376119939694345663760900827484372184
Short name T523
Test name
Test status
Simulation time 24963823 ps
CPU time 1.12 seconds
Started Nov 22 01:35:37 PM PST 23
Finished Nov 22 01:35:42 PM PST 23
Peak memory 230408 kb
Host smart-32623eae-2b03-4fb4-b7d1-955dfe9e331f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74187959926176347335031719350374015907380376119939694345663760900827484372184 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54
.edn_err.74187959926176347335031719350374015907380376119939694345663760900827484372184
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.98402967793451653556506792717381218346465226414386796366162883133475280747011
Short name T339
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:35:35 PM PST 23
Finished Nov 22 01:35:40 PM PST 23
Peak memory 205808 kb
Host smart-3db1dc84-51ec-4809-85db-7ba728bd2d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98402967793451653556506792717381218346465226414386796366162883133475280747011 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 54.edn_genbits.98402967793451653556506792717381218346465226414386796366162883133475280747011
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.79994849111806330169666641358476184935672631516175330488751325390854989748784
Short name T825
Test name
Test status
Simulation time 24963823 ps
CPU time 1.09 seconds
Started Nov 22 01:35:36 PM PST 23
Finished Nov 22 01:35:40 PM PST 23
Peak memory 230352 kb
Host smart-c81df18d-8a0e-462c-9ea3-d47628a24e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79994849111806330169666641358476184935672631516175330488751325390854989748784 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55
.edn_err.79994849111806330169666641358476184935672631516175330488751325390854989748784
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.105184982746360757071074080152607256206276296370413236160783886752137265148088
Short name T737
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 22 01:35:39 PM PST 23
Finished Nov 22 01:35:43 PM PST 23
Peak memory 205804 kb
Host smart-14d0be93-aa5d-4ac9-8d8d-0b029dca5a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105184982746360757071074080152607256206276296370413236160783886752137265148088 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 55.edn_genbits.105184982746360757071074080152607256206276296370413236160783886752137265148088
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.54382225152840007901688727935061205283507537334226765916788295666173124903067
Short name T586
Test name
Test status
Simulation time 24963823 ps
CPU time 1.13 seconds
Started Nov 22 01:35:39 PM PST 23
Finished Nov 22 01:35:43 PM PST 23
Peak memory 230404 kb
Host smart-45c40d3c-c1d2-44f1-aeed-eed6b1c3c396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54382225152840007901688727935061205283507537334226765916788295666173124903067 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56
.edn_err.54382225152840007901688727935061205283507537334226765916788295666173124903067
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.46024030654994943817779504090215916532893566216209156915577712880118387509304
Short name T430
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 22 01:35:38 PM PST 23
Finished Nov 22 01:35:42 PM PST 23
Peak memory 205740 kb
Host smart-12af90e7-73e2-4c98-9e1e-91267e1f88bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46024030654994943817779504090215916532893566216209156915577712880118387509304 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 56.edn_genbits.46024030654994943817779504090215916532893566216209156915577712880118387509304
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.100109539876101168441595191240382319788195731316731903884179960539492605652040
Short name T310
Test name
Test status
Simulation time 24963823 ps
CPU time 1.12 seconds
Started Nov 22 01:35:37 PM PST 23
Finished Nov 22 01:35:42 PM PST 23
Peak memory 230464 kb
Host smart-8561517d-9117-400e-85a0-33446a30423c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100109539876101168441595191240382319788195731316731903884179960539492605652040 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
7.edn_err.100109539876101168441595191240382319788195731316731903884179960539492605652040
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.33667210993009666252580795544396169098376920538525386497937857809715914638698
Short name T815
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Nov 22 01:35:37 PM PST 23
Finished Nov 22 01:35:42 PM PST 23
Peak memory 205820 kb
Host smart-0d11f14b-894a-476f-b08d-70a8262592f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33667210993009666252580795544396169098376920538525386497937857809715914638698 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 57.edn_genbits.33667210993009666252580795544396169098376920538525386497937857809715914638698
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.32064024789934309937142878349353564456239341574595120634511442780124205185581
Short name T373
Test name
Test status
Simulation time 24963823 ps
CPU time 1.13 seconds
Started Nov 22 01:35:38 PM PST 23
Finished Nov 22 01:35:42 PM PST 23
Peak memory 230440 kb
Host smart-98ee1d1a-bd30-4412-a05e-f8d847eea743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32064024789934309937142878349353564456239341574595120634511442780124205185581 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58
.edn_err.32064024789934309937142878349353564456239341574595120634511442780124205185581
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.3309446495504325976747562478522115431381798011709246559383613844108072092739
Short name T388
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 22 01:35:38 PM PST 23
Finished Nov 22 01:35:42 PM PST 23
Peak memory 205840 kb
Host smart-4fb03fee-be2b-47f5-8da4-43e7c00e6fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309446495504325976747562478522115431381798011709246559383613844108072092739 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 58.edn_genbits.3309446495504325976747562478522115431381798011709246559383613844108072092739
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.39895186620487254017826791229955851890539029330902180149899792440038972103597
Short name T328
Test name
Test status
Simulation time 24963823 ps
CPU time 1.14 seconds
Started Nov 22 01:35:36 PM PST 23
Finished Nov 22 01:35:40 PM PST 23
Peak memory 230456 kb
Host smart-1dc84121-07df-4081-88e1-f6836f3923af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39895186620487254017826791229955851890539029330902180149899792440038972103597 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59
.edn_err.39895186620487254017826791229955851890539029330902180149899792440038972103597
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.46689572172310958176628609022215169615044053138890347303743573954512446796502
Short name T585
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:35:35 PM PST 23
Finished Nov 22 01:35:40 PM PST 23
Peak memory 205780 kb
Host smart-6f42976f-0862-4b59-b1ac-8e8ecf920767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46689572172310958176628609022215169615044053138890347303743573954512446796502 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 59.edn_genbits.46689572172310958176628609022215169615044053138890347303743573954512446796502
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.77011406055820133582541938602926689345936386386901056779714910531811308108701
Short name T757
Test name
Test status
Simulation time 18259183 ps
CPU time 0.93 seconds
Started Nov 22 01:31:50 PM PST 23
Finished Nov 22 01:31:53 PM PST 23
Peak memory 205404 kb
Host smart-29bdd21d-1dcf-4155-bb1e-26a571bcc478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77011406055820133582541938602926689345936386386901056779714910531811308108701 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.edn_alert.77011406055820133582541938602926689345936386386901056779714910531811308108701
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.53510290665383059726289831502175892968629071566968590070746491929362816283783
Short name T626
Test name
Test status
Simulation time 28184990 ps
CPU time 0.83 seconds
Started Nov 22 01:31:50 PM PST 23
Finished Nov 22 01:31:53 PM PST 23
Peak memory 205332 kb
Host smart-75c5ce2f-2bf6-4abb-ad7c-a46d85fb22ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53510290665383059726289831502175892968629071566968590070746491929362816283783 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.edn_alert_test.53510290665383059726289831502175892968629071566968590070746491929362816283783
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.89480603311954467543527947456836112041864629354744249151789573544995684680644
Short name T66
Test name
Test status
Simulation time 12219183 ps
CPU time 0.86 seconds
Started Nov 22 01:31:49 PM PST 23
Finished Nov 22 01:31:51 PM PST 23
Peak memory 214832 kb
Host smart-b38706e5-1ab6-4326-946d-58696f2df53c
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89480603311954467543527947456836112041864629354744249151789573544995684680644 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.edn_disable.89480603311954467543527947456836112041864629354744249151789573544995684680644
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.18119154321526869700288438755004122388790642681700451291856586718950608709812
Short name T280
Test name
Test status
Simulation time 14969183 ps
CPU time 0.88 seconds
Started Nov 22 01:31:49 PM PST 23
Finished Nov 22 01:31:51 PM PST 23
Peak memory 214900 kb
Host smart-9a843d14-3ae0-4d5f-a460-53ba194c6b9f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18119154321526869700288438755004122388790642681700451291856586718950608709812 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable_auto_req_mode.18119154321526869700288438755004122388790642681700451291856
586718950608709812
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.11168035901882778011374647289996681266854578890464061841186164046175943872353
Short name T623
Test name
Test status
Simulation time 24963823 ps
CPU time 1.19 seconds
Started Nov 22 01:31:51 PM PST 23
Finished Nov 22 01:31:53 PM PST 23
Peak memory 230456 kb
Host smart-e670422b-55e2-4156-91d1-85f868389beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11168035901882778011374647289996681266854578890464061841186164046175943872353 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
edn_err.11168035901882778011374647289996681266854578890464061841186164046175943872353
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.26078823939068724556777437770303433753937197584280962931779555896107945734946
Short name T804
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 22 01:31:51 PM PST 23
Finished Nov 22 01:31:53 PM PST 23
Peak memory 205864 kb
Host smart-32b76e5f-4947-40c4-b0ef-e50aed4960cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26078823939068724556777437770303433753937197584280962931779555896107945734946 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.edn_genbits.26078823939068724556777437770303433753937197584280962931779555896107945734946
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.107650816223334757150875884096743223186316668305863825967665326670550444143069
Short name T699
Test name
Test status
Simulation time 18439183 ps
CPU time 1.13 seconds
Started Nov 22 01:31:50 PM PST 23
Finished Nov 22 01:31:52 PM PST 23
Peak memory 222240 kb
Host smart-c33dcb83-ced7-4b1d-beda-25718db3ce70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107650816223334757150875884096743223186316668305863825967665326670550444143069 -assert nopostproc +UVM_TESTNAME=edn_intr
_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.edn_intr.107650816223334757150875884096743223186316668305863825967665326670550444143069
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.37762644681161490455130457818149674020844327440823807683730373132069525281857
Short name T704
Test name
Test status
Simulation time 11759183 ps
CPU time 0.85 seconds
Started Nov 22 01:31:49 PM PST 23
Finished Nov 22 01:31:51 PM PST 23
Peak memory 205276 kb
Host smart-47d84df5-1b9b-4083-9b86-d9a2f4b76257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37762644681161490455130457818149674020844327440823807683730373132069525281857 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.edn_regwen.37762644681161490455130457818149674020844327440823807683730373132069525281857
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.17202566560170989281538102912649154729508141736418741012316067541563226643960
Short name T642
Test name
Test status
Simulation time 13059183 ps
CPU time 0.87 seconds
Started Nov 22 01:31:49 PM PST 23
Finished Nov 22 01:31:50 PM PST 23
Peak memory 205360 kb
Host smart-309dec6c-37fa-4fbb-b90a-8dd721fd965c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17202566560170989281538102912649154729508141736418741012316067541563226643960 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.edn_smoke.17202566560170989281538102912649154729508141736418741012316067541563226643960
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.33388003104667395954672107653453826634447324018446167301207228523216407651590
Short name T809
Test name
Test status
Simulation time 154489183 ps
CPU time 3.84 seconds
Started Nov 22 01:31:50 PM PST 23
Finished Nov 22 01:31:56 PM PST 23
Peak memory 206316 kb
Host smart-e64ce990-1b67-4686-b5f5-e82d2ee12984
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33388003104667395954672107653453826634447324018446167301207228523216407651590 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.33388003104667395954672107653453826634447324018446167301207228523216407651590
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.100766007216129991596900066603133761714068498072857289259739393860052545938731
Short name T617
Test name
Test status
Simulation time 41708099183 ps
CPU time 1073.94 seconds
Started Nov 22 01:31:50 PM PST 23
Finished Nov 22 01:49:46 PM PST 23
Peak memory 215868 kb
Host smart-da2cd24e-dc0b-4f75-8b96-cb2a32a8fdc4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100766007216129991596900066
603133761714068498072857289259739393860052545938731 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.10076600721
6129991596900066603133761714068498072857289259739393860052545938731
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.15010611832390098491792558893231887548564586291739699967808958461853975748875
Short name T597
Test name
Test status
Simulation time 24963823 ps
CPU time 1.12 seconds
Started Nov 22 01:35:36 PM PST 23
Finished Nov 22 01:35:40 PM PST 23
Peak memory 230424 kb
Host smart-e195be15-7fa6-4245-a0d7-b50fd548a5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15010611832390098491792558893231887548564586291739699967808958461853975748875 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60
.edn_err.15010611832390098491792558893231887548564586291739699967808958461853975748875
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.56188071147313863734398612054273799686624712389310555626977758309549603114058
Short name T449
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:35:35 PM PST 23
Finished Nov 22 01:35:40 PM PST 23
Peak memory 205812 kb
Host smart-c7be65ad-9378-4348-8f2a-60028f0efd44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56188071147313863734398612054273799686624712389310555626977758309549603114058 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 60.edn_genbits.56188071147313863734398612054273799686624712389310555626977758309549603114058
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.55906010283308666141886454414160140564572793992469823065126451432066932000205
Short name T632
Test name
Test status
Simulation time 24963823 ps
CPU time 1.17 seconds
Started Nov 22 01:35:38 PM PST 23
Finished Nov 22 01:35:42 PM PST 23
Peak memory 230440 kb
Host smart-ca34980f-b429-426e-85c9-02cd332ec480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55906010283308666141886454414160140564572793992469823065126451432066932000205 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61
.edn_err.55906010283308666141886454414160140564572793992469823065126451432066932000205
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.46144007574051515209831343900345514039042295272690507425142676944103326276685
Short name T300
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 22 01:35:38 PM PST 23
Finished Nov 22 01:35:42 PM PST 23
Peak memory 205836 kb
Host smart-e8877d90-6e73-4662-a96a-2f0b1a4eb028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46144007574051515209831343900345514039042295272690507425142676944103326276685 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 61.edn_genbits.46144007574051515209831343900345514039042295272690507425142676944103326276685
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.74995740666883203756843043164081927481633330715915310172346787687286011461851
Short name T307
Test name
Test status
Simulation time 24963823 ps
CPU time 1.14 seconds
Started Nov 22 01:35:42 PM PST 23
Finished Nov 22 01:35:47 PM PST 23
Peak memory 230440 kb
Host smart-5d42c00a-d40d-47b7-9333-23b97ca2ce88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74995740666883203756843043164081927481633330715915310172346787687286011461851 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62
.edn_err.74995740666883203756843043164081927481633330715915310172346787687286011461851
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.35981734948280158771242917519244199017060521404573375279301766658336370593250
Short name T579
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:35:42 PM PST 23
Finished Nov 22 01:35:46 PM PST 23
Peak memory 205832 kb
Host smart-0e2fadf0-bde3-4ccf-9df3-7d154efc9246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35981734948280158771242917519244199017060521404573375279301766658336370593250 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 62.edn_genbits.35981734948280158771242917519244199017060521404573375279301766658336370593250
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.110514979738812573849095755514002920411306617196810374123687153573546645176087
Short name T489
Test name
Test status
Simulation time 24963823 ps
CPU time 1.08 seconds
Started Nov 22 01:35:38 PM PST 23
Finished Nov 22 01:35:42 PM PST 23
Peak memory 230328 kb
Host smart-96b83638-f6ea-4a22-8892-9bbd2bcce219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110514979738812573849095755514002920411306617196810374123687153573546645176087 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
3.edn_err.110514979738812573849095755514002920411306617196810374123687153573546645176087
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.54029811871600793200275494955021421715574796568880601427171825712591640212336
Short name T761
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Nov 22 01:35:37 PM PST 23
Finished Nov 22 01:35:42 PM PST 23
Peak memory 205816 kb
Host smart-4e9c53ef-519b-4733-8aac-0915018e05a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54029811871600793200275494955021421715574796568880601427171825712591640212336 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 63.edn_genbits.54029811871600793200275494955021421715574796568880601427171825712591640212336
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.64560599614797451309184413235929022440160988088604829463668757391767621282256
Short name T964
Test name
Test status
Simulation time 24963823 ps
CPU time 1.12 seconds
Started Nov 22 01:35:39 PM PST 23
Finished Nov 22 01:35:43 PM PST 23
Peak memory 230404 kb
Host smart-645c0a77-b36f-4c16-8f26-8cb0dab6a0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64560599614797451309184413235929022440160988088604829463668757391767621282256 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64
.edn_err.64560599614797451309184413235929022440160988088604829463668757391767621282256
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.91657468746553512817141114008813512353279118426585715599917512600774475503454
Short name T266
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 22 01:35:35 PM PST 23
Finished Nov 22 01:35:40 PM PST 23
Peak memory 205780 kb
Host smart-35894e63-52e0-40bb-bc2c-b351a1b0db3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91657468746553512817141114008813512353279118426585715599917512600774475503454 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 64.edn_genbits.91657468746553512817141114008813512353279118426585715599917512600774475503454
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.3493940945965331935974733494213914100646919098117244408221529134710115216680
Short name T610
Test name
Test status
Simulation time 24963823 ps
CPU time 1.12 seconds
Started Nov 22 01:35:42 PM PST 23
Finished Nov 22 01:35:47 PM PST 23
Peak memory 230476 kb
Host smart-00bcdc86-ee76-41b3-9e0f-5a6eff615d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493940945965331935974733494213914100646919098117244408221529134710115216680 -assert nopostproc +UVM_TESTNAME=edn_err_te
st +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.
edn_err.3493940945965331935974733494213914100646919098117244408221529134710115216680
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.67890976194719511722310037994927530466662043952743323826001485546812740482761
Short name T503
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Nov 22 01:35:42 PM PST 23
Finished Nov 22 01:35:46 PM PST 23
Peak memory 205860 kb
Host smart-0a35f03b-327b-4eee-b85f-b5c8958b0729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67890976194719511722310037994927530466662043952743323826001485546812740482761 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 65.edn_genbits.67890976194719511722310037994927530466662043952743323826001485546812740482761
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.22686262445954154413235394431530336584064461785332840653103092272557382274511
Short name T19
Test name
Test status
Simulation time 24963823 ps
CPU time 1.09 seconds
Started Nov 22 01:35:42 PM PST 23
Finished Nov 22 01:35:47 PM PST 23
Peak memory 230480 kb
Host smart-5878fc9d-ee58-4d4c-bc66-9205ead46763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22686262445954154413235394431530336584064461785332840653103092272557382274511 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66
.edn_err.22686262445954154413235394431530336584064461785332840653103092272557382274511
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.115213450053994097530392537607296532637489018075932980042044082367527381777142
Short name T943
Test name
Test status
Simulation time 17999183 ps
CPU time 1.18 seconds
Started Nov 22 01:35:42 PM PST 23
Finished Nov 22 01:35:47 PM PST 23
Peak memory 205844 kb
Host smart-da87432b-c710-43e9-b52d-8d0b4fa29c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115213450053994097530392537607296532637489018075932980042044082367527381777142 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 66.edn_genbits.115213450053994097530392537607296532637489018075932980042044082367527381777142
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.105957095774596673512275167474018154852419754607084279346467286258348663786570
Short name T838
Test name
Test status
Simulation time 24963823 ps
CPU time 1.11 seconds
Started Nov 22 01:35:43 PM PST 23
Finished Nov 22 01:35:47 PM PST 23
Peak memory 230520 kb
Host smart-ba40eda1-7652-433e-b64d-a99dce1cb71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105957095774596673512275167474018154852419754607084279346467286258348663786570 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
7.edn_err.105957095774596673512275167474018154852419754607084279346467286258348663786570
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.53273301475696204728461319661369302588225242389410054754552830887437432449976
Short name T854
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 22 01:35:40 PM PST 23
Finished Nov 22 01:35:44 PM PST 23
Peak memory 205804 kb
Host smart-9875db62-6e19-4659-9468-e50626f66a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53273301475696204728461319661369302588225242389410054754552830887437432449976 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 67.edn_genbits.53273301475696204728461319661369302588225242389410054754552830887437432449976
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.73294041440658696118944094647372197914120782547198902105248091988675781684432
Short name T456
Test name
Test status
Simulation time 24963823 ps
CPU time 1.16 seconds
Started Nov 22 01:35:54 PM PST 23
Finished Nov 22 01:35:56 PM PST 23
Peak memory 230440 kb
Host smart-8a6111ac-ad57-4c8c-80e2-373e67181f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73294041440658696118944094647372197914120782547198902105248091988675781684432 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68
.edn_err.73294041440658696118944094647372197914120782547198902105248091988675781684432
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.114326586817552323138415725540471843610283475755386545520005889467392082145714
Short name T529
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:35:42 PM PST 23
Finished Nov 22 01:35:47 PM PST 23
Peak memory 205844 kb
Host smart-f9a60faf-7303-4563-9ab3-76fe4881e6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114326586817552323138415725540471843610283475755386545520005889467392082145714 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 68.edn_genbits.114326586817552323138415725540471843610283475755386545520005889467392082145714
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.108593448107959414465170147268686399897090313525197660671487742064480517428084
Short name T35
Test name
Test status
Simulation time 24963823 ps
CPU time 1.18 seconds
Started Nov 22 01:35:55 PM PST 23
Finished Nov 22 01:35:57 PM PST 23
Peak memory 230452 kb
Host smart-933adf1e-cffc-42fb-bcd2-898478600d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108593448107959414465170147268686399897090313525197660671487742064480517428084 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
9.edn_err.108593448107959414465170147268686399897090313525197660671487742064480517428084
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.41259493577593048390906861341517478543273462293947425540687955030974420376355
Short name T464
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:35:55 PM PST 23
Finished Nov 22 01:35:57 PM PST 23
Peak memory 205876 kb
Host smart-aa286e67-0369-4219-b46c-224991ee4f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41259493577593048390906861341517478543273462293947425540687955030974420376355 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 69.edn_genbits.41259493577593048390906861341517478543273462293947425540687955030974420376355
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.101225763117109904078828662242129846045514831701917841077504767749236152062370
Short name T439
Test name
Test status
Simulation time 18259183 ps
CPU time 0.97 seconds
Started Nov 22 01:33:23 PM PST 23
Finished Nov 22 01:33:25 PM PST 23
Peak memory 205532 kb
Host smart-193b7191-040a-453d-af08-12ba5cc98da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101225763117109904078828662242129846045514831701917841077504767749236152062370 -assert nopostproc +UVM_TESTNAME=edn_aler
t_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.edn_alert.101225763117109904078828662242129846045514831701917841077504767749236152062370
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.105418871857923972994019740383988959229071097959005853148116811130678380419442
Short name T731
Test name
Test status
Simulation time 28184990 ps
CPU time 0.87 seconds
Started Nov 22 01:33:22 PM PST 23
Finished Nov 22 01:33:24 PM PST 23
Peak memory 205520 kb
Host smart-c1739eb1-54c6-47bf-b0e3-bfa950d6c234
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105418871857923972994019740383988959229071097959005853148116811130678380419442 -assert nopostp
roc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 7.edn_alert_test.105418871857923972994019740383988959229071097959005853148116811130678380419442
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.29035693838204363108110026913166867446655929354011971557245912604490700665290
Short name T400
Test name
Test status
Simulation time 12219183 ps
CPU time 0.84 seconds
Started Nov 22 01:33:23 PM PST 23
Finished Nov 22 01:33:24 PM PST 23
Peak memory 214688 kb
Host smart-d2390389-1e3e-4322-9444-ed90a3b40390
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29035693838204363108110026913166867446655929354011971557245912604490700665290 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.edn_disable.29035693838204363108110026913166867446655929354011971557245912604490700665290
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.24817468163533170191392525180917163227660039729804560207331029683148052868662
Short name T23
Test name
Test status
Simulation time 14969183 ps
CPU time 0.94 seconds
Started Nov 22 01:33:23 PM PST 23
Finished Nov 22 01:33:25 PM PST 23
Peak memory 214872 kb
Host smart-576d8625-6e2e-4bcd-861a-79148b1e4f41
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24817468163533170191392525180917163227660039729804560207331029683148052868662 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable_auto_req_mode.24817468163533170191392525180917163227660039729804560207331
029683148052868662
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.10972481094679020584428832507639256981757370233879280273979314056350709229142
Short name T940
Test name
Test status
Simulation time 24963823 ps
CPU time 1.15 seconds
Started Nov 22 01:33:23 PM PST 23
Finished Nov 22 01:33:25 PM PST 23
Peak memory 230504 kb
Host smart-1ce20df3-2209-41d7-a2b6-caf6e4b06f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10972481094679020584428832507639256981757370233879280273979314056350709229142 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
edn_err.10972481094679020584428832507639256981757370233879280273979314056350709229142
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.114873648571972777907682375744512604701400037687556422863223869727088375897522
Short name T666
Test name
Test status
Simulation time 17999183 ps
CPU time 1.17 seconds
Started Nov 22 01:31:51 PM PST 23
Finished Nov 22 01:31:53 PM PST 23
Peak memory 205760 kb
Host smart-a0673f43-c74a-4d62-b868-6c1db10e109b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114873648571972777907682375744512604701400037687556422863223869727088375897522 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 7.edn_genbits.114873648571972777907682375744512604701400037687556422863223869727088375897522
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.68498314573809018969048412171028653720403291477578970974328419857055029703542
Short name T518
Test name
Test status
Simulation time 18439183 ps
CPU time 1.09 seconds
Started Nov 22 01:33:23 PM PST 23
Finished Nov 22 01:33:25 PM PST 23
Peak memory 222276 kb
Host smart-b2f283c5-e4ac-4f63-a690-d27fc66cd362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68498314573809018969048412171028653720403291477578970974328419857055029703542 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.edn_intr.68498314573809018969048412171028653720403291477578970974328419857055029703542
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.87129164853802754449430536240447398447087960823692681606867919681147523663850
Short name T811
Test name
Test status
Simulation time 11759183 ps
CPU time 0.87 seconds
Started Nov 22 01:31:49 PM PST 23
Finished Nov 22 01:31:50 PM PST 23
Peak memory 205272 kb
Host smart-50ca8e96-4c82-4d9f-a892-b60d600e8320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87129164853802754449430536240447398447087960823692681606867919681147523663850 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.edn_regwen.87129164853802754449430536240447398447087960823692681606867919681147523663850
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.27975617610651623158603160459785256911102857843546381989777041321821909520389
Short name T801
Test name
Test status
Simulation time 13059183 ps
CPU time 0.93 seconds
Started Nov 22 01:31:50 PM PST 23
Finished Nov 22 01:31:53 PM PST 23
Peak memory 205352 kb
Host smart-211131ee-a345-4cd0-9540-61df5a3f97b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27975617610651623158603160459785256911102857843546381989777041321821909520389 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.edn_smoke.27975617610651623158603160459785256911102857843546381989777041321821909520389
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.57877663099868382184860267533657568485298721127725004514723002977935639489763
Short name T34
Test name
Test status
Simulation time 154489183 ps
CPU time 3.91 seconds
Started Nov 22 01:33:13 PM PST 23
Finished Nov 22 01:33:18 PM PST 23
Peak memory 206380 kb
Host smart-df23562c-4c74-43ce-a962-5b10b32ba82b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57877663099868382184860267533657568485298721127725004514723002977935639489763 -assert nopos
tproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.57877663099868382184860267533657568485298721127725004514723002977935639489763
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.84757939642094325179003330708735665016997015111104976914580793557397483092590
Short name T324
Test name
Test status
Simulation time 41708099183 ps
CPU time 1074.29 seconds
Started Nov 22 01:33:14 PM PST 23
Finished Nov 22 01:51:09 PM PST 23
Peak memory 215828 kb
Host smart-446d61ec-88ec-4f5b-ae36-a49f59d8ca2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847579396420943251790033307
08735665016997015111104976914580793557397483092590 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.847579396420
94325179003330708735665016997015111104976914580793557397483092590
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.90743115372789216626511197901121490525915252936815948647203683444735868560955
Short name T684
Test name
Test status
Simulation time 24963823 ps
CPU time 1.13 seconds
Started Nov 22 01:36:00 PM PST 23
Finished Nov 22 01:36:01 PM PST 23
Peak memory 230460 kb
Host smart-9fb98684-5d90-47f8-88cd-3cac26aae6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90743115372789216626511197901121490525915252936815948647203683444735868560955 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70
.edn_err.90743115372789216626511197901121490525915252936815948647203683444735868560955
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.81487799954939724863063400580692888256154210801498579891322589270323137895165
Short name T663
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:35:56 PM PST 23
Finished Nov 22 01:35:59 PM PST 23
Peak memory 205836 kb
Host smart-5416f796-591f-4622-8df1-75059afaa527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81487799954939724863063400580692888256154210801498579891322589270323137895165 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 70.edn_genbits.81487799954939724863063400580692888256154210801498579891322589270323137895165
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.85521477049159198697143725422338069312726337821899452112357636089459342181037
Short name T627
Test name
Test status
Simulation time 24963823 ps
CPU time 1.22 seconds
Started Nov 22 01:35:56 PM PST 23
Finished Nov 22 01:35:58 PM PST 23
Peak memory 230440 kb
Host smart-d1608e98-1691-4c7b-b114-c0827e41d1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85521477049159198697143725422338069312726337821899452112357636089459342181037 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71
.edn_err.85521477049159198697143725422338069312726337821899452112357636089459342181037
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.37619268994431718266464824548403768373547699463804503760514928409397540767419
Short name T560
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Nov 22 01:35:58 PM PST 23
Finished Nov 22 01:36:00 PM PST 23
Peak memory 205820 kb
Host smart-0726efc0-0026-411c-87a4-39400ec15177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37619268994431718266464824548403768373547699463804503760514928409397540767419 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 71.edn_genbits.37619268994431718266464824548403768373547699463804503760514928409397540767419
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.64856333165947331096724758983067576008359498601970090730287807759491066803696
Short name T800
Test name
Test status
Simulation time 24963823 ps
CPU time 1.18 seconds
Started Nov 22 01:35:55 PM PST 23
Finished Nov 22 01:35:57 PM PST 23
Peak memory 230504 kb
Host smart-cecb0a9e-a3cc-434b-8bbf-b8e4c904dc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64856333165947331096724758983067576008359498601970090730287807759491066803696 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72
.edn_err.64856333165947331096724758983067576008359498601970090730287807759491066803696
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.62246709667701946842782339173938382093827883292975131987992322866173642496970
Short name T55
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Nov 22 01:35:55 PM PST 23
Finished Nov 22 01:35:56 PM PST 23
Peak memory 205840 kb
Host smart-7d3ace1a-cc27-432a-99cb-650de8d9b01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62246709667701946842782339173938382093827883292975131987992322866173642496970 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 72.edn_genbits.62246709667701946842782339173938382093827883292975131987992322866173642496970
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.29467108669734025473306844017904905379538391285559802802867015045660146435396
Short name T963
Test name
Test status
Simulation time 24963823 ps
CPU time 1.1 seconds
Started Nov 22 01:36:01 PM PST 23
Finished Nov 22 01:36:03 PM PST 23
Peak memory 230348 kb
Host smart-3c487e74-fb9f-4cb2-bb9e-f307914c3ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29467108669734025473306844017904905379538391285559802802867015045660146435396 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73
.edn_err.29467108669734025473306844017904905379538391285559802802867015045660146435396
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.2374102315024223252663299679381702588219321522934061450023464334132989217239
Short name T544
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 22 01:35:57 PM PST 23
Finished Nov 22 01:35:59 PM PST 23
Peak memory 205760 kb
Host smart-82c19075-29dd-492f-9b3c-366a0393a38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374102315024223252663299679381702588219321522934061450023464334132989217239 -assert nopostproc +UVM_TESTNAME=edn_genbit
s_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 73.edn_genbits.2374102315024223252663299679381702588219321522934061450023464334132989217239
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.84402747400066013596011380205462954394976251422716786390648216305260255655161
Short name T802
Test name
Test status
Simulation time 24963823 ps
CPU time 1.15 seconds
Started Nov 22 01:35:55 PM PST 23
Finished Nov 22 01:35:57 PM PST 23
Peak memory 230440 kb
Host smart-70e9719b-3a27-4633-85bf-acb08958851d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84402747400066013596011380205462954394976251422716786390648216305260255655161 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74
.edn_err.84402747400066013596011380205462954394976251422716786390648216305260255655161
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.25866282942394371539938976201251321542499063141769425117477176712351689872919
Short name T366
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 22 01:35:57 PM PST 23
Finished Nov 22 01:35:59 PM PST 23
Peak memory 205764 kb
Host smart-2c70c9f2-c18b-4de1-8314-4fd4590fcb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25866282942394371539938976201251321542499063141769425117477176712351689872919 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 74.edn_genbits.25866282942394371539938976201251321542499063141769425117477176712351689872919
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.49369302868654677151108009953105698409581662798899046746590114257416608062289
Short name T969
Test name
Test status
Simulation time 24963823 ps
CPU time 1.15 seconds
Started Nov 22 01:36:01 PM PST 23
Finished Nov 22 01:36:03 PM PST 23
Peak memory 230348 kb
Host smart-d36d42f1-172d-4226-9121-40e544dd21c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49369302868654677151108009953105698409581662798899046746590114257416608062289 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75
.edn_err.49369302868654677151108009953105698409581662798899046746590114257416608062289
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.36711214176237987657530004673248415643357853266178259292034790378729909849727
Short name T434
Test name
Test status
Simulation time 17999183 ps
CPU time 1.06 seconds
Started Nov 22 01:35:56 PM PST 23
Finished Nov 22 01:35:58 PM PST 23
Peak memory 205848 kb
Host smart-cac9ecdb-9fd4-4968-b4c5-d43aa0f81344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36711214176237987657530004673248415643357853266178259292034790378729909849727 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 75.edn_genbits.36711214176237987657530004673248415643357853266178259292034790378729909849727
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.91149215552841070387839798293642779891959325960404605150922769760308857418806
Short name T790
Test name
Test status
Simulation time 24963823 ps
CPU time 1.13 seconds
Started Nov 22 01:35:59 PM PST 23
Finished Nov 22 01:36:00 PM PST 23
Peak memory 230424 kb
Host smart-b2c9f0b1-89ce-4305-ab63-1cd7debfb8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91149215552841070387839798293642779891959325960404605150922769760308857418806 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76
.edn_err.91149215552841070387839798293642779891959325960404605150922769760308857418806
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.78515191060219440647952820421014909043365187365707931505222613913620890266812
Short name T548
Test name
Test status
Simulation time 17999183 ps
CPU time 1.17 seconds
Started Nov 22 01:35:54 PM PST 23
Finished Nov 22 01:35:55 PM PST 23
Peak memory 205820 kb
Host smart-eea41ab9-d65f-43a1-8483-157d21cdb7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78515191060219440647952820421014909043365187365707931505222613913620890266812 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 76.edn_genbits.78515191060219440647952820421014909043365187365707931505222613913620890266812
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.69653618529195838130066215236810527478274107244305801095286201889195716463752
Short name T38
Test name
Test status
Simulation time 24963823 ps
CPU time 1.25 seconds
Started Nov 22 01:35:55 PM PST 23
Finished Nov 22 01:35:58 PM PST 23
Peak memory 230440 kb
Host smart-edd3981f-73fe-45ec-8142-68206db69eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69653618529195838130066215236810527478274107244305801095286201889195716463752 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77
.edn_err.69653618529195838130066215236810527478274107244305801095286201889195716463752
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.70290745385910141321529624775275787899694908892705926797103496612193242507560
Short name T276
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 22 01:35:55 PM PST 23
Finished Nov 22 01:35:57 PM PST 23
Peak memory 205792 kb
Host smart-729533b0-602e-4e5d-a733-98c646aa5f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70290745385910141321529624775275787899694908892705926797103496612193242507560 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 77.edn_genbits.70290745385910141321529624775275787899694908892705926797103496612193242507560
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.104923602989620904436063704616084019170036917731171625361193512420370609263109
Short name T11
Test name
Test status
Simulation time 24963823 ps
CPU time 1.14 seconds
Started Nov 22 01:36:01 PM PST 23
Finished Nov 22 01:36:03 PM PST 23
Peak memory 230348 kb
Host smart-14a7edf9-f4bb-4032-ae09-66f63d8f7e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104923602989620904436063704616084019170036917731171625361193512420370609263109 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
8.edn_err.104923602989620904436063704616084019170036917731171625361193512420370609263109
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.48784234002050280251277469175794672832371075499181293158420949944955783764902
Short name T270
Test name
Test status
Simulation time 17999183 ps
CPU time 1.13 seconds
Started Nov 22 01:35:58 PM PST 23
Finished Nov 22 01:36:00 PM PST 23
Peak memory 205856 kb
Host smart-51abb02b-c005-46e6-a8d7-99c681dce369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48784234002050280251277469175794672832371075499181293158420949944955783764902 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 78.edn_genbits.48784234002050280251277469175794672832371075499181293158420949944955783764902
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.82898481532623304392465089533421793788362599114055774724455967230007658499757
Short name T413
Test name
Test status
Simulation time 24963823 ps
CPU time 1.13 seconds
Started Nov 22 01:36:02 PM PST 23
Finished Nov 22 01:36:04 PM PST 23
Peak memory 230440 kb
Host smart-9537aacd-8ff8-4d33-94f5-be80466be634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82898481532623304392465089533421793788362599114055774724455967230007658499757 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79
.edn_err.82898481532623304392465089533421793788362599114055774724455967230007658499757
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.103003200711820523092183139345402710016888364782059028464337433905661828746910
Short name T773
Test name
Test status
Simulation time 17999183 ps
CPU time 1.15 seconds
Started Nov 22 01:36:00 PM PST 23
Finished Nov 22 01:36:03 PM PST 23
Peak memory 205848 kb
Host smart-f3f1aa7a-711e-44d9-99d8-426656071ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103003200711820523092183139345402710016888364782059028464337433905661828746910 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 79.edn_genbits.103003200711820523092183139345402710016888364782059028464337433905661828746910
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.101072429643601034878047870741790898703295474495450534793181477515940854107949
Short name T547
Test name
Test status
Simulation time 18259183 ps
CPU time 0.95 seconds
Started Nov 22 01:33:21 PM PST 23
Finished Nov 22 01:33:23 PM PST 23
Peak memory 205420 kb
Host smart-9147ced5-485f-45cd-b8d9-7dbc64a04fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101072429643601034878047870741790898703295474495450534793181477515940854107949 -assert nopostproc +UVM_TESTNAME=edn_aler
t_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.edn_alert.101072429643601034878047870741790898703295474495450534793181477515940854107949
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.40895778555064734221456545053416585824418010922198914221856364585443409362731
Short name T574
Test name
Test status
Simulation time 28184990 ps
CPU time 0.87 seconds
Started Nov 22 01:33:26 PM PST 23
Finished Nov 22 01:33:27 PM PST 23
Peak memory 205488 kb
Host smart-b7806d00-97ce-4c7c-8039-a5ff7bb6db69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40895778555064734221456545053416585824418010922198914221856364585443409362731 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.edn_alert_test.40895778555064734221456545053416585824418010922198914221856364585443409362731
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.115140968143986201416543733261822162389950930512934693530410029002339379515981
Short name T867
Test name
Test status
Simulation time 12219183 ps
CPU time 0.96 seconds
Started Nov 22 01:33:23 PM PST 23
Finished Nov 22 01:33:25 PM PST 23
Peak memory 214888 kb
Host smart-ea327c01-1f93-4a95-888d-a197995a8f14
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115140968143986201416543733261822162389950930512934693530410029002339379515981 -assert nopostpr
oc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 8.edn_disable.115140968143986201416543733261822162389950930512934693530410029002339379515981
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.82630588346813352659784762064729295887546162136349571707211597599871391276054
Short name T658
Test name
Test status
Simulation time 14969183 ps
CPU time 0.93 seconds
Started Nov 22 01:33:23 PM PST 23
Finished Nov 22 01:33:25 PM PST 23
Peak memory 214888 kb
Host smart-5285939e-07a9-4c24-86f1-00dd911815f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82630588346813352659784762064729295887546162136349571707211597599871391276054 -assert nopostpro
c +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable_auto_req_mode.82630588346813352659784762064729295887546162136349571707211
597599871391276054
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.106542147523120481629038511802142173541052180805749546339464401398313380729224
Short name T864
Test name
Test status
Simulation time 24963823 ps
CPU time 1.15 seconds
Started Nov 22 01:33:24 PM PST 23
Finished Nov 22 01:33:27 PM PST 23
Peak memory 230356 kb
Host smart-4f795d91-b8f8-4bb9-a708-7fc3f2f26b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106542147523120481629038511802142173541052180805749546339464401398313380729224 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.edn_err.106542147523120481629038511802142173541052180805749546339464401398313380729224
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.33240364851703693917858247615129618247423348513786125003247178946023845859926
Short name T770
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:33:24 PM PST 23
Finished Nov 22 01:33:27 PM PST 23
Peak memory 205840 kb
Host smart-6361c22b-db54-4451-9dde-54b9b5760b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33240364851703693917858247615129618247423348513786125003247178946023845859926 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.edn_genbits.33240364851703693917858247615129618247423348513786125003247178946023845859926
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.58312139468331551458667017696298156685801344359344682422283785838383348506430
Short name T285
Test name
Test status
Simulation time 18439183 ps
CPU time 1.16 seconds
Started Nov 22 01:33:23 PM PST 23
Finished Nov 22 01:33:25 PM PST 23
Peak memory 222084 kb
Host smart-107a0443-a926-40a3-916b-24196ae5aea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58312139468331551458667017696298156685801344359344682422283785838383348506430 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.edn_intr.58312139468331551458667017696298156685801344359344682422283785838383348506430
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.45858082137561775040354434841835518553468332283558093037121714928100933758651
Short name T95
Test name
Test status
Simulation time 11759183 ps
CPU time 0.87 seconds
Started Nov 22 01:33:25 PM PST 23
Finished Nov 22 01:33:27 PM PST 23
Peak memory 205304 kb
Host smart-6bd68ef1-db01-4104-b3d9-8f358068ec09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45858082137561775040354434841835518553468332283558093037121714928100933758651 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.edn_regwen.45858082137561775040354434841835518553468332283558093037121714928100933758651
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.6429260717436738895527744779023832824088354007559611335571703537638175019093
Short name T905
Test name
Test status
Simulation time 13059183 ps
CPU time 0.96 seconds
Started Nov 22 01:33:23 PM PST 23
Finished Nov 22 01:33:26 PM PST 23
Peak memory 205320 kb
Host smart-24b0ed81-8c91-4209-a00e-833f402b35b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6429260717436738895527744779023832824088354007559611335571703537638175019093 -assert nopostproc +UVM_TESTNAME=edn_smoke_
test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.edn_smoke.6429260717436738895527744779023832824088354007559611335571703537638175019093
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.111967081411547785530112927886032701601653445710737318579347524181771327407266
Short name T814
Test name
Test status
Simulation time 154489183 ps
CPU time 4.03 seconds
Started Nov 22 01:33:23 PM PST 23
Finished Nov 22 01:33:28 PM PST 23
Peak memory 206308 kb
Host smart-0dcaa6aa-cfd1-4b95-b469-7562415ff9d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111967081411547785530112927886032701601653445710737318579347524181771327407266 -assert nopo
stproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.111967081411547785530112927886032701601653445710737318579347524181771327407266
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.83013784809754862103985262804058695664320325556380612115168381309091386156926
Short name T896
Test name
Test status
Simulation time 41708099183 ps
CPU time 1102.89 seconds
Started Nov 22 01:33:23 PM PST 23
Finished Nov 22 01:51:47 PM PST 23
Peak memory 215804 kb
Host smart-0ae744d9-a3d8-4e79-b0ba-def4443e4a78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830137848097548621039852628
04058695664320325556380612115168381309091386156926 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.830137848097
54862103985262804058695664320325556380612115168381309091386156926
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.86896608029608626303985645726145644802794555851206275855662092249442912976903
Short name T57
Test name
Test status
Simulation time 24963823 ps
CPU time 1.13 seconds
Started Nov 22 01:35:57 PM PST 23
Finished Nov 22 01:35:59 PM PST 23
Peak memory 230444 kb
Host smart-ca32b5b3-9960-4fd3-bcb6-77fd401da7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86896608029608626303985645726145644802794555851206275855662092249442912976903 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80
.edn_err.86896608029608626303985645726145644802794555851206275855662092249442912976903
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.87523533913660241745814633324695644750740960587394413524302297886854549604106
Short name T578
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:35:57 PM PST 23
Finished Nov 22 01:35:59 PM PST 23
Peak memory 205804 kb
Host smart-d7b9929c-ed26-4538-bc8d-d684d3e3da34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87523533913660241745814633324695644750740960587394413524302297886854549604106 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 80.edn_genbits.87523533913660241745814633324695644750740960587394413524302297886854549604106
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.4429189201584291508618020334491592162504260045528793788526376294216888657180
Short name T778
Test name
Test status
Simulation time 24963823 ps
CPU time 1.13 seconds
Started Nov 22 01:35:57 PM PST 23
Finished Nov 22 01:35:59 PM PST 23
Peak memory 230400 kb
Host smart-985befcd-1c75-485b-9323-95d1b673acba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4429189201584291508618020334491592162504260045528793788526376294216888657180 -assert nopostproc +UVM_TESTNAME=edn_err_te
st +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.
edn_err.4429189201584291508618020334491592162504260045528793788526376294216888657180
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.73137855130167795033065502285184356682001010666920358558080105958430734201129
Short name T506
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:35:59 PM PST 23
Finished Nov 22 01:36:01 PM PST 23
Peak memory 205744 kb
Host smart-7343f952-5737-4573-baf0-9583fccad6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73137855130167795033065502285184356682001010666920358558080105958430734201129 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 81.edn_genbits.73137855130167795033065502285184356682001010666920358558080105958430734201129
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.28257618654014552578521444495967689500669963678637538211928916923774199920425
Short name T865
Test name
Test status
Simulation time 24963823 ps
CPU time 1.19 seconds
Started Nov 22 01:36:07 PM PST 23
Finished Nov 22 01:36:08 PM PST 23
Peak memory 230364 kb
Host smart-ba37d0cd-80a4-49d4-8fdb-a8e254327fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28257618654014552578521444495967689500669963678637538211928916923774199920425 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82
.edn_err.28257618654014552578521444495967689500669963678637538211928916923774199920425
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.59791093169700093863887829494974068918789364666784619180616668712662167656285
Short name T803
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 22 01:35:59 PM PST 23
Finished Nov 22 01:36:01 PM PST 23
Peak memory 205856 kb
Host smart-85336f7c-3f65-48ea-98f2-b4a48952bb94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59791093169700093863887829494974068918789364666784619180616668712662167656285 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 82.edn_genbits.59791093169700093863887829494974068918789364666784619180616668712662167656285
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.8607578114233182027361667721088718693124088371593781333759692903876568591371
Short name T92
Test name
Test status
Simulation time 24963823 ps
CPU time 1.16 seconds
Started Nov 22 01:36:07 PM PST 23
Finished Nov 22 01:36:09 PM PST 23
Peak memory 230436 kb
Host smart-492ed755-c00d-4fa5-9a71-a2e3fbaf1674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8607578114233182027361667721088718693124088371593781333759692903876568591371 -assert nopostproc +UVM_TESTNAME=edn_err_te
st +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.
edn_err.8607578114233182027361667721088718693124088371593781333759692903876568591371
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.105771546280302032281814589980123721953264709750785551609955119311526169944456
Short name T250
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:36:01 PM PST 23
Finished Nov 22 01:36:03 PM PST 23
Peak memory 205848 kb
Host smart-e1dd4ada-0358-4c1d-98a5-56ad61b70df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105771546280302032281814589980123721953264709750785551609955119311526169944456 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 83.edn_genbits.105771546280302032281814589980123721953264709750785551609955119311526169944456
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.78810040858626718512639229945222194964440800893861919271684825160637924092162
Short name T926
Test name
Test status
Simulation time 24963823 ps
CPU time 1.12 seconds
Started Nov 22 01:36:08 PM PST 23
Finished Nov 22 01:36:09 PM PST 23
Peak memory 230380 kb
Host smart-b6177a3d-ae44-4b59-a53c-599e9ad8bc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78810040858626718512639229945222194964440800893861919271684825160637924092162 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84
.edn_err.78810040858626718512639229945222194964440800893861919271684825160637924092162
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.55665876430070666942740026777019803286882243592095854521100715254134880928885
Short name T78
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:36:22 PM PST 23
Finished Nov 22 01:36:24 PM PST 23
Peak memory 205840 kb
Host smart-3f9a27f6-3254-416e-8a36-d2d8a9da8d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55665876430070666942740026777019803286882243592095854521100715254134880928885 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 84.edn_genbits.55665876430070666942740026777019803286882243592095854521100715254134880928885
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.4077879981676251143848941277004554233065314954150254128038942307006574211833
Short name T638
Test name
Test status
Simulation time 24963823 ps
CPU time 1.18 seconds
Started Nov 22 01:36:19 PM PST 23
Finished Nov 22 01:36:21 PM PST 23
Peak memory 230436 kb
Host smart-99bd20ff-c6ab-487a-ab6d-a16200900662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077879981676251143848941277004554233065314954150254128038942307006574211833 -assert nopostproc +UVM_TESTNAME=edn_err_te
st +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.
edn_err.4077879981676251143848941277004554233065314954150254128038942307006574211833
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.36584093256148064307144471698953476939679063810022988339695170386290669856987
Short name T417
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 22 01:36:18 PM PST 23
Finished Nov 22 01:36:20 PM PST 23
Peak memory 205848 kb
Host smart-c995750d-55d4-4781-9c93-cd5f8f18bd60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36584093256148064307144471698953476939679063810022988339695170386290669856987 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 85.edn_genbits.36584093256148064307144471698953476939679063810022988339695170386290669856987
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.1282914837864367209266385379650278446745448396130469032746143208738299374918
Short name T870
Test name
Test status
Simulation time 24963823 ps
CPU time 1.17 seconds
Started Nov 22 01:36:17 PM PST 23
Finished Nov 22 01:36:19 PM PST 23
Peak memory 230452 kb
Host smart-5edafaa6-74cc-40ca-bb0e-df93be33612b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282914837864367209266385379650278446745448396130469032746143208738299374918 -assert nopostproc +UVM_TESTNAME=edn_err_te
st +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.
edn_err.1282914837864367209266385379650278446745448396130469032746143208738299374918
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.59413888655203531796179932642040384517966330382958198648849232214063877664682
Short name T61
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Nov 22 01:36:19 PM PST 23
Finished Nov 22 01:36:21 PM PST 23
Peak memory 205804 kb
Host smart-fab8edf7-463e-4635-8d11-48dba381785c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59413888655203531796179932642040384517966330382958198648849232214063877664682 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 86.edn_genbits.59413888655203531796179932642040384517966330382958198648849232214063877664682
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.109193256512778368793247743844008545533614881976553942196762882629004884259320
Short name T354
Test name
Test status
Simulation time 24963823 ps
CPU time 1.22 seconds
Started Nov 22 01:36:01 PM PST 23
Finished Nov 22 01:36:03 PM PST 23
Peak memory 230324 kb
Host smart-c72f4eaf-f09e-49ac-bbc1-5b097bf6110b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109193256512778368793247743844008545533614881976553942196762882629004884259320 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
7.edn_err.109193256512778368793247743844008545533614881976553942196762882629004884259320
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.58044374884014914092174617770284053425326099711418559066159187976340034400496
Short name T636
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:36:00 PM PST 23
Finished Nov 22 01:36:02 PM PST 23
Peak memory 205844 kb
Host smart-0ece4dff-1021-4fe1-a4bd-a33877ce8de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58044374884014914092174617770284053425326099711418559066159187976340034400496 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 87.edn_genbits.58044374884014914092174617770284053425326099711418559066159187976340034400496
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.19861529089337076494911285228064657363666806226537684259045390406796512139681
Short name T639
Test name
Test status
Simulation time 24963823 ps
CPU time 1.19 seconds
Started Nov 22 01:36:28 PM PST 23
Finished Nov 22 01:36:30 PM PST 23
Peak memory 230412 kb
Host smart-87303d64-9bcf-4f0c-8d27-6d80e79292d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19861529089337076494911285228064657363666806226537684259045390406796512139681 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88
.edn_err.19861529089337076494911285228064657363666806226537684259045390406796512139681
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.98128028336755712150518965791911623394280436545366861591235335097188050164395
Short name T268
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:36:18 PM PST 23
Finished Nov 22 01:36:20 PM PST 23
Peak memory 205804 kb
Host smart-0e48a6a5-16c8-4969-9b7a-c85723c82097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98128028336755712150518965791911623394280436545366861591235335097188050164395 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 88.edn_genbits.98128028336755712150518965791911623394280436545366861591235335097188050164395
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.45695695102257576468002071274106286439424229639867056385457613131171018974430
Short name T600
Test name
Test status
Simulation time 24963823 ps
CPU time 1.25 seconds
Started Nov 22 01:36:22 PM PST 23
Finished Nov 22 01:36:24 PM PST 23
Peak memory 230440 kb
Host smart-14c2ccb2-52db-44b1-96d4-c0f917323d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45695695102257576468002071274106286439424229639867056385457613131171018974430 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89
.edn_err.45695695102257576468002071274106286439424229639867056385457613131171018974430
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.93828153634805626521990610351077106588275658136386472740261604094998958375340
Short name T851
Test name
Test status
Simulation time 17999183 ps
CPU time 1.09 seconds
Started Nov 22 01:36:07 PM PST 23
Finished Nov 22 01:36:09 PM PST 23
Peak memory 205900 kb
Host smart-93a26e89-a9ac-4f5a-b641-09d1c66f2aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93828153634805626521990610351077106588275658136386472740261604094998958375340 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 89.edn_genbits.93828153634805626521990610351077106588275658136386472740261604094998958375340
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.89215105637909608672238350305279909597063033642667317328032692318083902424942
Short name T604
Test name
Test status
Simulation time 18259183 ps
CPU time 0.99 seconds
Started Nov 22 01:33:24 PM PST 23
Finished Nov 22 01:33:26 PM PST 23
Peak memory 205580 kb
Host smart-03add5e8-a7ca-4522-99e1-a5b5882d8bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89215105637909608672238350305279909597063033642667317328032692318083902424942 -assert nopostproc +UVM_TESTNAME=edn_alert
_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.edn_alert.89215105637909608672238350305279909597063033642667317328032692318083902424942
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.38487142566414802575611753203755492335502916514227433955023554310517160824292
Short name T808
Test name
Test status
Simulation time 28184990 ps
CPU time 0.86 seconds
Started Nov 22 01:33:23 PM PST 23
Finished Nov 22 01:33:26 PM PST 23
Peak memory 205476 kb
Host smart-f2b9150c-691a-4f7a-9aaf-dc5ca8433309
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38487142566414802575611753203755492335502916514227433955023554310517160824292 -assert nopostpr
oc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.edn_alert_test.38487142566414802575611753203755492335502916514227433955023554310517160824292
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.22461050386521171653699120702521613634881660103937673686054668246206794404217
Short name T421
Test name
Test status
Simulation time 12219183 ps
CPU time 0.86 seconds
Started Nov 22 01:33:24 PM PST 23
Finished Nov 22 01:33:26 PM PST 23
Peak memory 214812 kb
Host smart-a0652cb6-ecac-4df5-ac40-7f9ebe4c225f
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22461050386521171653699120702521613634881660103937673686054668246206794404217 -assert nopostpro
c +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.edn_disable.22461050386521171653699120702521613634881660103937673686054668246206794404217
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.3183967721850422905050724603058458580290306251951257003767905136603867351121
Short name T382
Test name
Test status
Simulation time 14969183 ps
CPU time 0.94 seconds
Started Nov 22 01:33:21 PM PST 23
Finished Nov 22 01:33:23 PM PST 23
Peak memory 214756 kb
Host smart-df398e37-d8c4-426f-baec-1b594050f4d2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183967721850422905050724603058458580290306251951257003767905136603867351121 -assert nopostproc
+UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable_auto_req_mode.318396772185042290505072460305845858029030625195125700376790
5136603867351121
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.16242975722947701510941410918955642512263918850390562394350460897993991758277
Short name T933
Test name
Test status
Simulation time 24963823 ps
CPU time 1.16 seconds
Started Nov 22 01:33:24 PM PST 23
Finished Nov 22 01:33:27 PM PST 23
Peak memory 230424 kb
Host smart-e7938af6-53fb-4f01-8925-c1d4004d8236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16242975722947701510941410918955642512263918850390562394350460897993991758277 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
edn_err.16242975722947701510941410918955642512263918850390562394350460897993991758277
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.57734506349842546284847796521619883797650711381541325337942274525382703254551
Short name T54
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 22 01:33:26 PM PST 23
Finished Nov 22 01:33:28 PM PST 23
Peak memory 205772 kb
Host smart-200e4b6d-a9b8-4319-bf74-40a6cac5ceb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57734506349842546284847796521619883797650711381541325337942274525382703254551 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.edn_genbits.57734506349842546284847796521619883797650711381541325337942274525382703254551
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.30102297793314175124071742839806298254933311270263904863441454759951570972132
Short name T602
Test name
Test status
Simulation time 18439183 ps
CPU time 1.13 seconds
Started Nov 22 01:33:23 PM PST 23
Finished Nov 22 01:33:25 PM PST 23
Peak memory 222252 kb
Host smart-b54da34f-2916-4275-87ce-725b6f9578cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30102297793314175124071742839806298254933311270263904863441454759951570972132 -assert nopostproc +UVM_TESTNAME=edn_intr_
test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.edn_intr.30102297793314175124071742839806298254933311270263904863441454759951570972132
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.102717307839554012227224479596935692147872246776516672455193386994373036060274
Short name T756
Test name
Test status
Simulation time 11759183 ps
CPU time 0.89 seconds
Started Nov 22 01:33:22 PM PST 23
Finished Nov 22 01:33:24 PM PST 23
Peak memory 205320 kb
Host smart-744b3447-9ecb-4dd8-81b8-baed27d2f8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102717307839554012227224479596935692147872246776516672455193386994373036060274 -assert nopostproc +UVM_TESTNAME=edn_smok
e_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 9.edn_regwen.102717307839554012227224479596935692147872246776516672455193386994373036060274
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.79633058774106226560058660840370656385357449631666961463899459018506244379380
Short name T72
Test name
Test status
Simulation time 13059183 ps
CPU time 0.9 seconds
Started Nov 22 01:33:23 PM PST 23
Finished Nov 22 01:33:25 PM PST 23
Peak memory 205464 kb
Host smart-7e857743-62c5-4724-844e-725ba6f863b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79633058774106226560058660840370656385357449631666961463899459018506244379380 -assert nopostproc +UVM_TESTNAME=edn_smoke
_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.edn_smoke.79633058774106226560058660840370656385357449631666961463899459018506244379380
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.7847154967962264932256812160962624566004452411538458889870963831863044482927
Short name T694
Test name
Test status
Simulation time 154489183 ps
CPU time 4.05 seconds
Started Nov 22 01:33:22 PM PST 23
Finished Nov 22 01:33:27 PM PST 23
Peak memory 206352 kb
Host smart-35872bfa-c59e-4f20-b4a7-8a3d252110a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7847154967962264932256812160962624566004452411538458889870963831863044482927 -assert nopost
proc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.7847154967962264932256812160962624566004452411538458889870963831863044482927
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.94405507372297456533940348336737946901281658756433691499529152752713955770168
Short name T848
Test name
Test status
Simulation time 41708099183 ps
CPU time 1088.02 seconds
Started Nov 22 01:33:24 PM PST 23
Finished Nov 22 01:51:34 PM PST 23
Peak memory 215864 kb
Host smart-345141ba-3f3b-44ad-b545-31a3e939ea71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944055073722974565339403483
36737946901281658756433691499529152752713955770168 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.944055073722
97456533940348336737946901281658756433691499529152752713955770168
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.23332800775186833124913237700441321910775058517283200263798411521529759552161
Short name T686
Test name
Test status
Simulation time 24963823 ps
CPU time 1.16 seconds
Started Nov 22 01:36:28 PM PST 23
Finished Nov 22 01:36:31 PM PST 23
Peak memory 230436 kb
Host smart-f4ded51e-01c4-46ef-af81-7026a7b05358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23332800775186833124913237700441321910775058517283200263798411521529759552161 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90
.edn_err.23332800775186833124913237700441321910775058517283200263798411521529759552161
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.17537863217338932543914425618480789839570240482851053734370740984305284289695
Short name T390
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:36:24 PM PST 23
Finished Nov 22 01:36:26 PM PST 23
Peak memory 205840 kb
Host smart-4955ccaa-7412-411d-a7e8-6e5d685432dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17537863217338932543914425618480789839570240482851053734370740984305284289695 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 90.edn_genbits.17537863217338932543914425618480789839570240482851053734370740984305284289695
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.104865743364809634345381965327400897725886860540811321763837297794297699088248
Short name T505
Test name
Test status
Simulation time 24963823 ps
CPU time 1.14 seconds
Started Nov 22 01:36:27 PM PST 23
Finished Nov 22 01:36:29 PM PST 23
Peak memory 230412 kb
Host smart-f6b5f43d-9ca5-449d-9b38-dc632af728c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104865743364809634345381965327400897725886860540811321763837297794297699088248 -assert nopostproc +UVM_TESTNAME=edn_err_
test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
1.edn_err.104865743364809634345381965327400897725886860540811321763837297794297699088248
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.56912408353722878400787265775843525555291915952656066064932502424278966270791
Short name T648
Test name
Test status
Simulation time 17999183 ps
CPU time 1.12 seconds
Started Nov 22 01:36:51 PM PST 23
Finished Nov 22 01:36:57 PM PST 23
Peak memory 205840 kb
Host smart-907824d1-ff24-4fa0-9f46-ab244e8180bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56912408353722878400787265775843525555291915952656066064932502424278966270791 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 91.edn_genbits.56912408353722878400787265775843525555291915952656066064932502424278966270791
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.53942568742175634188453725771601544063309734291777851476870259677523445878361
Short name T959
Test name
Test status
Simulation time 24963823 ps
CPU time 1.14 seconds
Started Nov 22 01:36:51 PM PST 23
Finished Nov 22 01:36:55 PM PST 23
Peak memory 230468 kb
Host smart-c7c6628a-9056-4a94-a0f2-b186e3bf1c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53942568742175634188453725771601544063309734291777851476870259677523445878361 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92
.edn_err.53942568742175634188453725771601544063309734291777851476870259677523445878361
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.100420815907306806677881309869084412041204080558917327542794252348602292652124
Short name T282
Test name
Test status
Simulation time 17999183 ps
CPU time 1.08 seconds
Started Nov 22 01:36:32 PM PST 23
Finished Nov 22 01:36:34 PM PST 23
Peak memory 205752 kb
Host smart-ebb2b456-2182-417d-bfe7-b0acd14ad346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100420815907306806677881309869084412041204080558917327542794252348602292652124 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 92.edn_genbits.100420815907306806677881309869084412041204080558917327542794252348602292652124
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.41325770969940127979666916462179249345710596778136076976136913809772332394289
Short name T717
Test name
Test status
Simulation time 24963823 ps
CPU time 1.15 seconds
Started Nov 22 01:35:53 PM PST 23
Finished Nov 22 01:35:55 PM PST 23
Peak memory 230416 kb
Host smart-8e566f2a-807d-489c-a74d-8ed794071fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41325770969940127979666916462179249345710596778136076976136913809772332394289 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93
.edn_err.41325770969940127979666916462179249345710596778136076976136913809772332394289
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.104983254152284925085856956085016531102852715543541683964278005940091883771596
Short name T360
Test name
Test status
Simulation time 17999183 ps
CPU time 1.14 seconds
Started Nov 22 01:36:34 PM PST 23
Finished Nov 22 01:36:35 PM PST 23
Peak memory 205852 kb
Host smart-0eacbc10-8db8-4e03-9b1d-78a7b483957f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104983254152284925085856956085016531102852715543541683964278005940091883771596 -assert nopostproc +UVM_TESTNAME=edn_genb
its_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 93.edn_genbits.104983254152284925085856956085016531102852715543541683964278005940091883771596
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.24359941910799907711768547514267917516290446352242860968913442205826563391167
Short name T949
Test name
Test status
Simulation time 24963823 ps
CPU time 1.12 seconds
Started Nov 22 01:35:55 PM PST 23
Finished Nov 22 01:35:58 PM PST 23
Peak memory 230432 kb
Host smart-0e2e50dc-a02a-4b0b-84b6-a9fd622233d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24359941910799907711768547514267917516290446352242860968913442205826563391167 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94
.edn_err.24359941910799907711768547514267917516290446352242860968913442205826563391167
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.97395575226546026429474640672453150561465105968210028134236264915952974446537
Short name T519
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:35:56 PM PST 23
Finished Nov 22 01:35:58 PM PST 23
Peak memory 205856 kb
Host smart-5f35c28c-9b9a-4f7e-9d39-9e47b7176bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97395575226546026429474640672453150561465105968210028134236264915952974446537 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 94.edn_genbits.97395575226546026429474640672453150561465105968210028134236264915952974446537
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.75815071860015695016090435885819204671587848805209787853651757975105553161776
Short name T791
Test name
Test status
Simulation time 24963823 ps
CPU time 1.17 seconds
Started Nov 22 01:35:54 PM PST 23
Finished Nov 22 01:35:56 PM PST 23
Peak memory 230408 kb
Host smart-5bdd3d0f-25ce-4bb0-84dd-246ef091f94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75815071860015695016090435885819204671587848805209787853651757975105553161776 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95
.edn_err.75815071860015695016090435885819204671587848805209787853651757975105553161776
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.69680069730642796485496137098874373810247352813945658835565160840376542688842
Short name T405
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:35:56 PM PST 23
Finished Nov 22 01:35:58 PM PST 23
Peak memory 205860 kb
Host smart-b34509c8-ff9b-4b43-9818-cab22e8300b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69680069730642796485496137098874373810247352813945658835565160840376542688842 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 95.edn_genbits.69680069730642796485496137098874373810247352813945658835565160840376542688842
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.18691889714606984976785081089469301969185589944989176055571230405256485740096
Short name T900
Test name
Test status
Simulation time 24963823 ps
CPU time 1.13 seconds
Started Nov 22 01:36:26 PM PST 23
Finished Nov 22 01:36:27 PM PST 23
Peak memory 230448 kb
Host smart-01323c14-490a-4746-aae3-606ebb72f010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18691889714606984976785081089469301969185589944989176055571230405256485740096 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96
.edn_err.18691889714606984976785081089469301969185589944989176055571230405256485740096
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.94433121919777077064921224802634279470972521680038149733267882809351154740008
Short name T243
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:36:16 PM PST 23
Finished Nov 22 01:36:18 PM PST 23
Peak memory 205804 kb
Host smart-3f07641d-927d-478a-9c1c-328188100efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94433121919777077064921224802634279470972521680038149733267882809351154740008 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 96.edn_genbits.94433121919777077064921224802634279470972521680038149733267882809351154740008
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.83705396090880941777331723438669065435861016717877171447926343456893364216847
Short name T415
Test name
Test status
Simulation time 24963823 ps
CPU time 1.19 seconds
Started Nov 22 01:36:00 PM PST 23
Finished Nov 22 01:36:03 PM PST 23
Peak memory 230408 kb
Host smart-539705c7-3e2f-4d86-986a-c6e30c26e2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83705396090880941777331723438669065435861016717877171447926343456893364216847 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97
.edn_err.83705396090880941777331723438669065435861016717877171447926343456893364216847
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.39007716911669836954938352878039868036583853872679051809003763345921815813835
Short name T254
Test name
Test status
Simulation time 17999183 ps
CPU time 1.07 seconds
Started Nov 22 01:36:08 PM PST 23
Finished Nov 22 01:36:10 PM PST 23
Peak memory 205784 kb
Host smart-4dd752f8-18d6-4dbb-9548-1169b9fe3c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39007716911669836954938352878039868036583853872679051809003763345921815813835 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 97.edn_genbits.39007716911669836954938352878039868036583853872679051809003763345921815813835
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.36280622674639044499210621134454980831702309665678389080511244493501980329657
Short name T301
Test name
Test status
Simulation time 24963823 ps
CPU time 1.14 seconds
Started Nov 22 01:36:16 PM PST 23
Finished Nov 22 01:36:18 PM PST 23
Peak memory 230292 kb
Host smart-4ff2d94e-7373-4931-a0a4-c797de3e255f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36280622674639044499210621134454980831702309665678389080511244493501980329657 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98
.edn_err.36280622674639044499210621134454980831702309665678389080511244493501980329657
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.87488303212827248965434127888027073771032696618176915899990699770704596391091
Short name T344
Test name
Test status
Simulation time 17999183 ps
CPU time 1.11 seconds
Started Nov 22 01:36:16 PM PST 23
Finished Nov 22 01:36:18 PM PST 23
Peak memory 205772 kb
Host smart-7045c662-29fd-4f66-bd57-ae292be71e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87488303212827248965434127888027073771032696618176915899990699770704596391091 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 98.edn_genbits.87488303212827248965434127888027073771032696618176915899990699770704596391091
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.85193380359167371078051642563772962730771642920039256646382889394183361108855
Short name T474
Test name
Test status
Simulation time 24963823 ps
CPU time 1.19 seconds
Started Nov 22 01:36:18 PM PST 23
Finished Nov 22 01:36:20 PM PST 23
Peak memory 230456 kb
Host smart-74ec3c67-0f63-48f8-9790-804db34f8fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85193380359167371078051642563772962730771642920039256646382889394183361108855 -assert nopostproc +UVM_TESTNAME=edn_err_t
est +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99
.edn_err.85193380359167371078051642563772962730771642920039256646382889394183361108855
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.71758560286415733740969480955496568502770888566402892254403765791182947617689
Short name T59
Test name
Test status
Simulation time 17999183 ps
CPU time 1.1 seconds
Started Nov 22 01:36:15 PM PST 23
Finished Nov 22 01:36:17 PM PST 23
Peak memory 205848 kb
Host smart-1caa1c77-b7ae-446f-b2e6-99324d960609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71758560286415733740969480955496568502770888566402892254403765791182947617689 -assert nopostproc +UVM_TESTNAME=edn_genbi
ts_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 99.edn_genbits.71758560286415733740969480955496568502770888566402892254403765791182947617689
Directory /workspace/99.edn_genbits/latest
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