Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.72 99.02 92.39 96.79 91.45 98.62 99.77 99.00


Total test records in report: 974
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T127 /workspace/coverage/default/46.edn_disable.1896058044 Dec 20 12:53:52 PM PST 23 Dec 20 12:54:01 PM PST 23 11143480 ps
T274 /workspace/coverage/default/133.edn_genbits.3267013680 Dec 20 12:54:48 PM PST 23 Dec 20 12:55:05 PM PST 23 16455519 ps
T779 /workspace/coverage/default/41.edn_smoke.1703235283 Dec 20 12:53:49 PM PST 23 Dec 20 12:53:57 PM PST 23 14321266 ps
T780 /workspace/coverage/default/11.edn_smoke.1653565739 Dec 20 12:52:50 PM PST 23 Dec 20 12:53:03 PM PST 23 21000450 ps
T781 /workspace/coverage/default/16.edn_alert_test.2829930731 Dec 20 12:53:04 PM PST 23 Dec 20 12:53:19 PM PST 23 14649052 ps
T782 /workspace/coverage/default/112.edn_genbits.2066243205 Dec 20 12:54:40 PM PST 23 Dec 20 12:54:53 PM PST 23 35788272 ps
T783 /workspace/coverage/default/192.edn_genbits.1554145306 Dec 20 12:55:00 PM PST 23 Dec 20 12:55:22 PM PST 23 31106978 ps
T784 /workspace/coverage/default/11.edn_err.1866659960 Dec 20 12:52:51 PM PST 23 Dec 20 12:53:06 PM PST 23 23222754 ps
T785 /workspace/coverage/default/42.edn_genbits.414167375 Dec 20 12:53:50 PM PST 23 Dec 20 12:53:58 PM PST 23 33504088 ps
T786 /workspace/coverage/default/40.edn_stress_all.2569242709 Dec 20 12:53:49 PM PST 23 Dec 20 12:54:00 PM PST 23 228659873 ps
T787 /workspace/coverage/default/44.edn_alert_test.3330674213 Dec 20 12:53:56 PM PST 23 Dec 20 12:54:07 PM PST 23 34533900 ps
T162 /workspace/coverage/default/33.edn_disable.3869793324 Dec 20 12:53:42 PM PST 23 Dec 20 12:53:49 PM PST 23 13065916 ps
T788 /workspace/coverage/default/20.edn_err.354967281 Dec 20 12:53:30 PM PST 23 Dec 20 12:53:34 PM PST 23 18021402 ps
T789 /workspace/coverage/default/21.edn_alert_test.2023565059 Dec 20 12:53:35 PM PST 23 Dec 20 12:53:39 PM PST 23 38405189 ps
T332 /workspace/coverage/default/45.edn_genbits.2971986951 Dec 20 12:53:51 PM PST 23 Dec 20 12:54:00 PM PST 23 23813127 ps
T790 /workspace/coverage/default/155.edn_genbits.3466816951 Dec 20 12:54:45 PM PST 23 Dec 20 12:55:00 PM PST 23 241536746 ps
T791 /workspace/coverage/default/10.edn_alert.3788118471 Dec 20 12:52:44 PM PST 23 Dec 20 12:52:57 PM PST 23 32944283 ps
T792 /workspace/coverage/default/184.edn_genbits.256996519 Dec 20 12:54:50 PM PST 23 Dec 20 12:55:10 PM PST 23 28640893 ps
T793 /workspace/coverage/default/32.edn_stress_all_with_rand_reset.3150239059 Dec 20 12:53:41 PM PST 23 Dec 20 01:03:04 PM PST 23 245639449650 ps
T794 /workspace/coverage/default/297.edn_genbits.3013699054 Dec 20 12:55:02 PM PST 23 Dec 20 12:55:25 PM PST 23 17002101 ps
T795 /workspace/coverage/default/22.edn_genbits.1209569133 Dec 20 12:53:34 PM PST 23 Dec 20 12:53:38 PM PST 23 13616330 ps
T796 /workspace/coverage/default/235.edn_genbits.3030024610 Dec 20 12:54:57 PM PST 23 Dec 20 12:55:18 PM PST 23 18229899 ps
T797 /workspace/coverage/default/23.edn_genbits.4123524405 Dec 20 12:53:29 PM PST 23 Dec 20 12:53:34 PM PST 23 34219316 ps
T318 /workspace/coverage/default/20.edn_alert.793316158 Dec 20 12:53:13 PM PST 23 Dec 20 12:53:28 PM PST 23 56392786 ps
T798 /workspace/coverage/default/251.edn_genbits.4164855874 Dec 20 12:55:02 PM PST 23 Dec 20 12:55:25 PM PST 23 52742017 ps
T799 /workspace/coverage/default/4.edn_intr.3003493270 Dec 20 12:51:52 PM PST 23 Dec 20 12:52:07 PM PST 23 19680159 ps
T800 /workspace/coverage/default/31.edn_stress_all_with_rand_reset.990037663 Dec 20 12:53:38 PM PST 23 Dec 20 01:13:12 PM PST 23 47175134606 ps
T106 /workspace/coverage/default/2.edn_disable_auto_req_mode.1152267239 Dec 20 12:52:06 PM PST 23 Dec 20 12:52:25 PM PST 23 77098785 ps
T801 /workspace/coverage/default/26.edn_err.3087769373 Dec 20 12:53:39 PM PST 23 Dec 20 12:53:44 PM PST 23 104911266 ps
T802 /workspace/coverage/default/164.edn_genbits.1132761369 Dec 20 12:54:48 PM PST 23 Dec 20 12:55:04 PM PST 23 23031739 ps
T803 /workspace/coverage/default/121.edn_genbits.352161547 Dec 20 12:55:00 PM PST 23 Dec 20 12:55:21 PM PST 23 20720211 ps
T804 /workspace/coverage/default/43.edn_stress_all_with_rand_reset.3586346686 Dec 20 12:53:51 PM PST 23 Dec 20 01:00:42 PM PST 23 37303831933 ps
T805 /workspace/coverage/default/41.edn_alert.3128886276 Dec 20 12:53:56 PM PST 23 Dec 20 12:54:06 PM PST 23 28338909 ps
T806 /workspace/coverage/default/18.edn_err.2825292122 Dec 20 12:53:12 PM PST 23 Dec 20 12:53:27 PM PST 23 18282477 ps
T807 /workspace/coverage/default/30.edn_intr.1680991462 Dec 20 12:53:44 PM PST 23 Dec 20 12:53:51 PM PST 23 20315638 ps
T808 /workspace/coverage/default/210.edn_genbits.2046031709 Dec 20 12:54:53 PM PST 23 Dec 20 12:55:14 PM PST 23 108835665 ps
T320 /workspace/coverage/default/2.edn_regwen.1102558569 Dec 20 12:52:01 PM PST 23 Dec 20 12:52:18 PM PST 23 21174812 ps
T809 /workspace/coverage/default/46.edn_genbits.800469492 Dec 20 12:53:56 PM PST 23 Dec 20 12:54:06 PM PST 23 14457027 ps
T810 /workspace/coverage/default/28.edn_disable.3795732430 Dec 20 12:53:47 PM PST 23 Dec 20 12:53:53 PM PST 23 17242270 ps
T811 /workspace/coverage/default/65.edn_genbits.2168616677 Dec 20 12:54:39 PM PST 23 Dec 20 12:54:52 PM PST 23 16968952 ps
T812 /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2516270760 Dec 20 12:53:36 PM PST 23 Dec 20 01:26:38 PM PST 23 319707664293 ps
T813 /workspace/coverage/default/277.edn_genbits.2931657776 Dec 20 12:54:55 PM PST 23 Dec 20 12:55:13 PM PST 23 23937040 ps
T814 /workspace/coverage/default/147.edn_genbits.2213387468 Dec 20 12:54:49 PM PST 23 Dec 20 12:55:08 PM PST 23 20755991 ps
T815 /workspace/coverage/default/22.edn_stress_all_with_rand_reset.4294380978 Dec 20 12:53:31 PM PST 23 Dec 20 01:03:31 PM PST 23 23970677884 ps
T816 /workspace/coverage/default/8.edn_err.1017795809 Dec 20 12:52:44 PM PST 23 Dec 20 12:52:57 PM PST 23 19781145 ps
T817 /workspace/coverage/default/29.edn_err.855537643 Dec 20 12:53:42 PM PST 23 Dec 20 12:53:49 PM PST 23 69221155 ps
T818 /workspace/coverage/default/173.edn_genbits.4060903481 Dec 20 12:54:47 PM PST 23 Dec 20 12:56:28 PM PST 23 4273683598 ps
T819 /workspace/coverage/default/1.edn_disable_auto_req_mode.1940193186 Dec 20 12:51:54 PM PST 23 Dec 20 12:52:09 PM PST 23 195155382 ps
T820 /workspace/coverage/default/36.edn_stress_all_with_rand_reset.3690816560 Dec 20 12:53:56 PM PST 23 Dec 20 01:07:39 PM PST 23 36463654785 ps
T821 /workspace/coverage/default/6.edn_stress_all.508102196 Dec 20 12:52:32 PM PST 23 Dec 20 12:52:46 PM PST 23 164253550 ps
T822 /workspace/coverage/default/18.edn_intr.1135228054 Dec 20 12:53:10 PM PST 23 Dec 20 12:53:24 PM PST 23 21262541 ps
T823 /workspace/coverage/default/211.edn_genbits.735665774 Dec 20 12:54:48 PM PST 23 Dec 20 12:55:07 PM PST 23 18631582 ps
T824 /workspace/coverage/default/49.edn_smoke.63095417 Dec 20 12:53:54 PM PST 23 Dec 20 12:54:03 PM PST 23 46281996 ps
T825 /workspace/coverage/default/47.edn_intr.931562266 Dec 20 12:53:56 PM PST 23 Dec 20 12:54:07 PM PST 23 31644217 ps
T826 /workspace/coverage/default/39.edn_stress_all_with_rand_reset.2365548965 Dec 20 12:53:50 PM PST 23 Dec 20 01:12:21 PM PST 23 87477977024 ps
T827 /workspace/coverage/default/97.edn_genbits.1776686693 Dec 20 12:54:52 PM PST 23 Dec 20 12:55:11 PM PST 23 14106528 ps
T828 /workspace/coverage/default/23.edn_stress_all_with_rand_reset.2484363851 Dec 20 12:53:35 PM PST 23 Dec 20 01:08:48 PM PST 23 71410142586 ps
T829 /workspace/coverage/default/14.edn_stress_all_with_rand_reset.91025768 Dec 20 12:53:01 PM PST 23 Dec 20 01:07:28 PM PST 23 68487000742 ps
T830 /workspace/coverage/default/77.edn_err.869658407 Dec 20 12:54:40 PM PST 23 Dec 20 12:54:52 PM PST 23 46240078 ps
T831 /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2214182881 Dec 20 12:53:02 PM PST 23 Dec 20 01:06:29 PM PST 23 67418494746 ps
T832 /workspace/coverage/default/9.edn_disable.354924231 Dec 20 12:52:41 PM PST 23 Dec 20 12:52:53 PM PST 23 12850123 ps
T833 /workspace/coverage/default/14.edn_alert.817388654 Dec 20 12:52:55 PM PST 23 Dec 20 12:53:10 PM PST 23 37563928 ps
T834 /workspace/coverage/default/202.edn_genbits.3326581573 Dec 20 12:54:48 PM PST 23 Dec 20 12:55:07 PM PST 23 61209992 ps
T835 /workspace/coverage/default/44.edn_stress_all_with_rand_reset.940735556 Dec 20 12:53:48 PM PST 23 Dec 20 12:56:39 PM PST 23 7552795657 ps
T836 /workspace/coverage/default/24.edn_alert.3355622659 Dec 20 12:53:40 PM PST 23 Dec 20 12:53:46 PM PST 23 18258771 ps
T837 /workspace/coverage/default/14.edn_alert_test.4073674659 Dec 20 12:52:54 PM PST 23 Dec 20 12:53:09 PM PST 23 23565497 ps
T838 /workspace/coverage/default/12.edn_genbits.1447797909 Dec 20 12:52:48 PM PST 23 Dec 20 12:53:01 PM PST 23 19659977 ps
T125 /workspace/coverage/default/29.edn_disable.3881293838 Dec 20 12:53:48 PM PST 23 Dec 20 12:53:56 PM PST 23 14036058 ps
T839 /workspace/coverage/default/7.edn_alert_test.2552054747 Dec 20 12:52:42 PM PST 23 Dec 20 12:52:54 PM PST 23 13908566 ps
T840 /workspace/coverage/default/229.edn_genbits.38106716 Dec 20 12:54:59 PM PST 23 Dec 20 12:55:21 PM PST 23 17265345 ps
T841 /workspace/coverage/default/232.edn_genbits.3435368588 Dec 20 12:55:05 PM PST 23 Dec 20 12:55:29 PM PST 23 16044671 ps
T842 /workspace/coverage/default/43.edn_alert_test.1188117947 Dec 20 12:53:53 PM PST 23 Dec 20 12:54:01 PM PST 23 13758697 ps
T843 /workspace/coverage/default/238.edn_genbits.3756462443 Dec 20 12:54:45 PM PST 23 Dec 20 12:54:59 PM PST 23 20623835 ps
T844 /workspace/coverage/default/38.edn_err.906571167 Dec 20 12:53:45 PM PST 23 Dec 20 12:53:52 PM PST 23 55841048 ps
T50 /workspace/coverage/default/0.edn_sec_cm.1129724663 Dec 20 12:51:53 PM PST 23 Dec 20 12:52:14 PM PST 23 4198444805 ps
T845 /workspace/coverage/default/88.edn_genbits.3475286226 Dec 20 12:55:01 PM PST 23 Dec 20 12:55:24 PM PST 23 110438284 ps
T846 /workspace/coverage/default/49.edn_genbits.3405091766 Dec 20 12:53:57 PM PST 23 Dec 20 12:54:08 PM PST 23 48971492 ps
T847 /workspace/coverage/default/106.edn_genbits.3939718649 Dec 20 12:55:02 PM PST 23 Dec 20 12:55:24 PM PST 23 62762273 ps
T224 /workspace/coverage/default/42.edn_disable_auto_req_mode.3356000398 Dec 20 12:53:49 PM PST 23 Dec 20 12:53:57 PM PST 23 25675245 ps
T848 /workspace/coverage/default/7.edn_disable_auto_req_mode.2736842274 Dec 20 12:52:45 PM PST 23 Dec 20 12:52:58 PM PST 23 26450322 ps
T849 /workspace/coverage/default/294.edn_genbits.1342662687 Dec 20 12:55:00 PM PST 23 Dec 20 12:55:21 PM PST 23 19398401 ps
T850 /workspace/coverage/default/292.edn_genbits.3830366432 Dec 20 12:55:00 PM PST 23 Dec 20 12:55:22 PM PST 23 41610806 ps
T851 /workspace/coverage/default/160.edn_genbits.1989323958 Dec 20 12:54:49 PM PST 23 Dec 20 12:55:07 PM PST 23 14854789 ps
T852 /workspace/coverage/default/4.edn_smoke.432840140 Dec 20 12:51:55 PM PST 23 Dec 20 12:52:11 PM PST 23 16342456 ps
T853 /workspace/coverage/default/240.edn_genbits.3820997481 Dec 20 12:54:46 PM PST 23 Dec 20 12:55:01 PM PST 23 16164294 ps
T854 /workspace/coverage/default/11.edn_stress_all.1616187670 Dec 20 12:52:51 PM PST 23 Dec 20 12:53:07 PM PST 23 283120612 ps
T855 /workspace/coverage/default/44.edn_stress_all.1737060136 Dec 20 12:53:50 PM PST 23 Dec 20 12:53:58 PM PST 23 37114822 ps
T856 /workspace/coverage/default/33.edn_smoke.965831661 Dec 20 12:53:42 PM PST 23 Dec 20 12:53:49 PM PST 23 41690259 ps
T322 /workspace/coverage/default/39.edn_alert.2284768619 Dec 20 12:53:51 PM PST 23 Dec 20 12:53:59 PM PST 23 29798917 ps
T857 /workspace/coverage/default/36.edn_alert.121743632 Dec 20 12:53:51 PM PST 23 Dec 20 12:53:59 PM PST 23 21727004 ps
T858 /workspace/coverage/default/13.edn_intr.2134418358 Dec 20 12:53:00 PM PST 23 Dec 20 12:53:13 PM PST 23 19247407 ps
T309 /workspace/coverage/default/1.edn_regwen.3552748294 Dec 20 12:51:52 PM PST 23 Dec 20 12:52:08 PM PST 23 123121270 ps
T859 /workspace/coverage/default/2.edn_alert.3589240870 Dec 20 12:52:00 PM PST 23 Dec 20 12:52:17 PM PST 23 64162100 ps
T860 /workspace/coverage/default/120.edn_genbits.368673226 Dec 20 12:54:41 PM PST 23 Dec 20 12:54:53 PM PST 23 15802500 ps
T861 /workspace/coverage/default/32.edn_stress_all.27957126 Dec 20 12:53:42 PM PST 23 Dec 20 12:53:53 PM PST 23 2432505147 ps
T862 /workspace/coverage/default/150.edn_genbits.3555444180 Dec 20 12:54:48 PM PST 23 Dec 20 12:55:04 PM PST 23 173068637 ps
T863 /workspace/coverage/default/6.edn_genbits.3122313239 Dec 20 12:52:29 PM PST 23 Dec 20 12:52:44 PM PST 23 72099598 ps
T864 /workspace/coverage/default/9.edn_stress_all.3675588970 Dec 20 12:52:42 PM PST 23 Dec 20 12:52:55 PM PST 23 152241430 ps
T865 /workspace/coverage/default/208.edn_genbits.872553915 Dec 20 12:54:54 PM PST 23 Dec 20 12:55:13 PM PST 23 49327966 ps
T866 /workspace/coverage/default/11.edn_stress_all_with_rand_reset.425327286 Dec 20 12:52:51 PM PST 23 Dec 20 01:16:27 PM PST 23 122398914402 ps
T867 /workspace/coverage/default/252.edn_genbits.911195809 Dec 20 12:54:51 PM PST 23 Dec 20 12:55:10 PM PST 23 16623975 ps
T868 /workspace/coverage/default/47.edn_alert.3569173004 Dec 20 12:53:54 PM PST 23 Dec 20 12:54:03 PM PST 23 63074907 ps
T869 /workspace/coverage/default/154.edn_genbits.3375069503 Dec 20 12:54:48 PM PST 23 Dec 20 12:55:06 PM PST 23 31154015 ps
T870 /workspace/coverage/default/98.edn_genbits.202605486 Dec 20 12:54:55 PM PST 23 Dec 20 12:55:14 PM PST 23 35697848 ps
T871 /workspace/coverage/default/46.edn_stress_all.283378991 Dec 20 12:53:56 PM PST 23 Dec 20 12:54:08 PM PST 23 111183355 ps
T872 /workspace/coverage/default/73.edn_genbits.865511340 Dec 20 12:54:43 PM PST 23 Dec 20 12:54:57 PM PST 23 41218842 ps
T873 /workspace/coverage/default/71.edn_genbits.1529710015 Dec 20 12:54:40 PM PST 23 Dec 20 12:54:53 PM PST 23 116748785 ps
T336 /workspace/coverage/default/134.edn_genbits.1651652755 Dec 20 12:54:47 PM PST 23 Dec 20 12:55:03 PM PST 23 81084797 ps
T874 /workspace/coverage/default/6.edn_alert_test.1068342589 Dec 20 12:52:30 PM PST 23 Dec 20 12:52:44 PM PST 23 13965853 ps
T875 /workspace/coverage/default/6.edn_stress_all_with_rand_reset.457910193 Dec 20 12:52:30 PM PST 23 Dec 20 12:57:22 PM PST 23 45207173023 ps
T149 /workspace/coverage/default/33.edn_disable_auto_req_mode.2712877330 Dec 20 12:53:47 PM PST 23 Dec 20 12:53:54 PM PST 23 20798158 ps
T876 /workspace/coverage/default/50.edn_genbits.2204027818 Dec 20 12:53:56 PM PST 23 Dec 20 12:54:06 PM PST 23 56235269 ps
T877 /workspace/coverage/default/78.edn_err.3236111548 Dec 20 12:54:38 PM PST 23 Dec 20 12:54:51 PM PST 23 19669085 ps
T878 /workspace/coverage/default/206.edn_genbits.1866298048 Dec 20 12:54:52 PM PST 23 Dec 20 12:55:11 PM PST 23 32452396 ps
T879 /workspace/coverage/default/72.edn_genbits.219939081 Dec 20 12:54:38 PM PST 23 Dec 20 12:54:52 PM PST 23 45823162 ps
T880 /workspace/coverage/default/81.edn_err.1748929174 Dec 20 12:54:44 PM PST 23 Dec 20 12:54:58 PM PST 23 24146172 ps
T881 /workspace/coverage/default/24.edn_genbits.1861149748 Dec 20 12:53:40 PM PST 23 Dec 20 12:53:46 PM PST 23 16531431 ps
T882 /workspace/coverage/default/40.edn_intr.434107856 Dec 20 12:53:45 PM PST 23 Dec 20 12:53:52 PM PST 23 22298046 ps
T883 /workspace/coverage/default/39.edn_alert_test.2931809030 Dec 20 12:53:51 PM PST 23 Dec 20 12:54:00 PM PST 23 220190376 ps
T261 /workspace/coverage/default/259.edn_genbits.184533931 Dec 20 12:54:57 PM PST 23 Dec 20 12:55:19 PM PST 23 138386602 ps
T884 /workspace/coverage/default/42.edn_alert_test.2789927143 Dec 20 12:53:55 PM PST 23 Dec 20 12:54:04 PM PST 23 30321970 ps
T885 /workspace/coverage/default/204.edn_genbits.685988504 Dec 20 12:54:48 PM PST 23 Dec 20 12:55:06 PM PST 23 18723269 ps
T886 /workspace/coverage/default/38.edn_smoke.3873618392 Dec 20 12:53:52 PM PST 23 Dec 20 12:54:00 PM PST 23 23136909 ps
T887 /workspace/coverage/default/105.edn_genbits.3807596026 Dec 20 12:54:57 PM PST 23 Dec 20 12:55:16 PM PST 23 38548388 ps
T888 /workspace/coverage/default/17.edn_smoke.1226858572 Dec 20 12:53:04 PM PST 23 Dec 20 12:53:19 PM PST 23 14181225 ps
T889 /workspace/coverage/default/40.edn_disable_auto_req_mode.922789515 Dec 20 12:53:50 PM PST 23 Dec 20 12:53:57 PM PST 23 30177830 ps
T890 /workspace/coverage/default/137.edn_genbits.2813780925 Dec 20 12:54:55 PM PST 23 Dec 20 12:55:14 PM PST 23 41477764 ps
T891 /workspace/coverage/default/149.edn_genbits.1803800145 Dec 20 12:54:50 PM PST 23 Dec 20 12:55:09 PM PST 23 25268696 ps
T892 /workspace/coverage/default/18.edn_alert.1407978565 Dec 20 12:53:11 PM PST 23 Dec 20 12:53:26 PM PST 23 20911780 ps
T893 /workspace/coverage/default/35.edn_alert_test.1798396200 Dec 20 12:53:54 PM PST 23 Dec 20 12:54:04 PM PST 23 33941953 ps
T894 /workspace/coverage/default/201.edn_genbits.2413631305 Dec 20 12:54:48 PM PST 23 Dec 20 12:55:07 PM PST 23 21754188 ps
T895 /workspace/coverage/default/37.edn_err.794090956 Dec 20 12:53:52 PM PST 23 Dec 20 12:54:01 PM PST 23 37513173 ps
T896 /workspace/coverage/default/34.edn_disable.1266210977 Dec 20 12:53:46 PM PST 23 Dec 20 12:53:52 PM PST 23 38298235 ps
T897 /workspace/coverage/default/237.edn_genbits.2184346080 Dec 20 12:54:50 PM PST 23 Dec 20 12:55:09 PM PST 23 35882232 ps
T898 /workspace/coverage/default/181.edn_genbits.4020620610 Dec 20 12:54:52 PM PST 23 Dec 20 12:55:12 PM PST 23 67717260 ps
T899 /workspace/coverage/default/170.edn_genbits.2697240620 Dec 20 12:54:55 PM PST 23 Dec 20 12:55:14 PM PST 23 124014349 ps
T119 /workspace/coverage/default/49.edn_disable.2751636477 Dec 20 12:53:56 PM PST 23 Dec 20 12:54:06 PM PST 23 73696603 ps
T900 /workspace/coverage/default/16.edn_genbits.3334892049 Dec 20 12:53:00 PM PST 23 Dec 20 12:53:15 PM PST 23 29970401 ps
T901 /workspace/coverage/default/49.edn_intr.2019808281 Dec 20 12:53:55 PM PST 23 Dec 20 12:54:04 PM PST 23 20944441 ps
T902 /workspace/coverage/default/4.edn_disable_auto_req_mode.918885604 Dec 20 12:52:32 PM PST 23 Dec 20 12:52:46 PM PST 23 34423618 ps
T903 /workspace/coverage/default/28.edn_alert.1316097331 Dec 20 12:53:43 PM PST 23 Dec 20 12:53:50 PM PST 23 233435946 ps
T904 /workspace/coverage/default/128.edn_genbits.1551452987 Dec 20 12:54:48 PM PST 23 Dec 20 12:55:07 PM PST 23 32372937 ps
T905 /workspace/coverage/default/19.edn_stress_all_with_rand_reset.2934763472 Dec 20 12:53:09 PM PST 23 Dec 20 01:10:37 PM PST 23 42095688567 ps
T906 /workspace/coverage/default/270.edn_genbits.3400265310 Dec 20 12:55:01 PM PST 23 Dec 20 12:55:23 PM PST 23 85072637 ps
T907 /workspace/coverage/default/20.edn_disable.1283547300 Dec 20 12:53:30 PM PST 23 Dec 20 12:53:34 PM PST 23 10741831 ps
T908 /workspace/coverage/default/152.edn_genbits.730746354 Dec 20 12:54:51 PM PST 23 Dec 20 12:55:10 PM PST 23 21273708 ps
T150 /workspace/coverage/default/16.edn_disable_auto_req_mode.3477049273 Dec 20 12:53:02 PM PST 23 Dec 20 12:53:16 PM PST 23 68011142 ps
T269 /workspace/coverage/default/275.edn_genbits.373292640 Dec 20 12:54:58 PM PST 23 Dec 20 12:55:18 PM PST 23 36529284 ps
T909 /workspace/coverage/default/39.edn_genbits.1428792819 Dec 20 12:53:50 PM PST 23 Dec 20 12:53:57 PM PST 23 111830472 ps
T910 /workspace/coverage/default/47.edn_alert_test.2575827470 Dec 20 12:53:53 PM PST 23 Dec 20 12:54:01 PM PST 23 21352407 ps
T169 /workspace/coverage/default/17.edn_err.3922379957 Dec 20 12:53:08 PM PST 23 Dec 20 12:53:23 PM PST 23 19731521 ps
T911 /workspace/coverage/default/2.edn_disable.517943483 Dec 20 12:52:00 PM PST 23 Dec 20 12:52:17 PM PST 23 31546842 ps
T912 /workspace/coverage/default/13.edn_stress_all.2338099334 Dec 20 12:52:56 PM PST 23 Dec 20 12:53:14 PM PST 23 524792603 ps
T913 /workspace/coverage/default/0.edn_regwen.4038367070 Dec 20 12:51:55 PM PST 23 Dec 20 12:52:10 PM PST 23 20214516 ps
T914 /workspace/coverage/default/86.edn_genbits.934486252 Dec 20 12:54:42 PM PST 23 Dec 20 12:54:55 PM PST 23 172265886 ps
T915 /workspace/coverage/default/24.edn_intr.2970791912 Dec 20 12:53:39 PM PST 23 Dec 20 12:53:44 PM PST 23 21521353 ps
T916 /workspace/coverage/default/45.edn_stress_all_with_rand_reset.3114693460 Dec 20 12:53:56 PM PST 23 Dec 20 01:15:21 PM PST 23 51458499595 ps
T917 /workspace/coverage/default/45.edn_stress_all.1142451471 Dec 20 12:53:55 PM PST 23 Dec 20 12:54:07 PM PST 23 775635981 ps
T918 /workspace/coverage/default/41.edn_disable_auto_req_mode.1396246424 Dec 20 12:53:47 PM PST 23 Dec 20 12:53:54 PM PST 23 61580415 ps
T172 /workspace/coverage/default/99.edn_err.1674777915 Dec 20 12:54:57 PM PST 23 Dec 20 12:55:18 PM PST 23 21663173 ps
T919 /workspace/coverage/default/34.edn_err.3874021533 Dec 20 12:53:42 PM PST 23 Dec 20 12:53:48 PM PST 23 21572827 ps
T920 /workspace/coverage/default/38.edn_alert.3534262140 Dec 20 12:53:41 PM PST 23 Dec 20 12:53:48 PM PST 23 20300665 ps
T921 /workspace/coverage/default/45.edn_disable_auto_req_mode.1076537877 Dec 20 12:53:56 PM PST 23 Dec 20 12:54:08 PM PST 23 73227847 ps
T922 /workspace/coverage/default/12.edn_err.3995588689 Dec 20 12:52:54 PM PST 23 Dec 20 12:53:09 PM PST 23 34430415 ps
T923 /workspace/coverage/default/223.edn_genbits.145651224 Dec 20 12:54:57 PM PST 23 Dec 20 12:55:19 PM PST 23 54906955 ps
T924 /workspace/coverage/default/24.edn_disable_auto_req_mode.235703005 Dec 20 12:53:37 PM PST 23 Dec 20 12:53:43 PM PST 23 33200715 ps
T925 /workspace/coverage/default/64.edn_genbits.1010259399 Dec 20 12:54:41 PM PST 23 Dec 20 12:54:53 PM PST 23 15614780 ps
T926 /workspace/coverage/default/57.edn_err.1510003543 Dec 20 12:54:29 PM PST 23 Dec 20 12:54:44 PM PST 23 71957404 ps
T927 /workspace/coverage/default/1.edn_err.1768014828 Dec 20 12:51:54 PM PST 23 Dec 20 12:52:10 PM PST 23 81251298 ps
T928 /workspace/coverage/default/98.edn_err.2558668525 Dec 20 12:54:52 PM PST 23 Dec 20 12:55:11 PM PST 23 54876743 ps
T929 /workspace/coverage/default/100.edn_genbits.3819623640 Dec 20 12:54:59 PM PST 23 Dec 20 12:55:21 PM PST 23 16277025 ps
T930 /workspace/coverage/default/22.edn_alert.2473123209 Dec 20 12:53:36 PM PST 23 Dec 20 12:53:40 PM PST 23 28652516 ps
T931 /workspace/coverage/default/141.edn_genbits.1894341479 Dec 20 12:54:59 PM PST 23 Dec 20 12:55:21 PM PST 23 19989638 ps
T932 /workspace/coverage/default/157.edn_genbits.2729949895 Dec 20 12:54:46 PM PST 23 Dec 20 12:55:02 PM PST 23 30761176 ps
T933 /workspace/coverage/default/22.edn_err.1867284245 Dec 20 12:53:34 PM PST 23 Dec 20 12:53:38 PM PST 23 51297183 ps
T934 /workspace/coverage/default/21.edn_stress_all_with_rand_reset.1784689956 Dec 20 12:53:31 PM PST 23 Dec 20 01:02:17 PM PST 23 88355636598 ps
T230 /workspace/coverage/default/24.edn_err.3914161943 Dec 20 12:53:35 PM PST 23 Dec 20 12:53:39 PM PST 23 31899357 ps
T935 /workspace/coverage/default/77.edn_genbits.1542278168 Dec 20 12:54:38 PM PST 23 Dec 20 12:54:51 PM PST 23 60102707 ps
T936 /workspace/coverage/default/19.edn_genbits.3190119403 Dec 20 12:53:15 PM PST 23 Dec 20 12:53:29 PM PST 23 17624637 ps
T937 /workspace/coverage/default/167.edn_genbits.1482204651 Dec 20 12:54:45 PM PST 23 Dec 20 12:55:00 PM PST 23 55136056 ps
T938 /workspace/coverage/default/0.edn_disable.1199818953 Dec 20 12:51:52 PM PST 23 Dec 20 12:52:07 PM PST 23 20460202 ps
T939 /workspace/coverage/default/260.edn_genbits.1418042104 Dec 20 12:55:02 PM PST 23 Dec 20 12:55:24 PM PST 23 25988200 ps
T940 /workspace/coverage/default/101.edn_genbits.1793676877 Dec 20 12:54:59 PM PST 23 Dec 20 12:55:21 PM PST 23 15760065 ps
T226 /workspace/coverage/default/8.edn_disable_auto_req_mode.3287725043 Dec 20 12:52:41 PM PST 23 Dec 20 12:52:53 PM PST 23 85088010 ps
T941 /workspace/coverage/default/12.edn_intr.655649585 Dec 20 12:52:50 PM PST 23 Dec 20 12:53:04 PM PST 23 19705739 ps
T942 /workspace/coverage/default/39.edn_intr.1248331652 Dec 20 12:53:54 PM PST 23 Dec 20 12:54:03 PM PST 23 19578747 ps
T943 /workspace/coverage/default/32.edn_genbits.2723818559 Dec 20 12:53:46 PM PST 23 Dec 20 12:53:53 PM PST 23 17192844 ps
T944 /workspace/coverage/default/146.edn_genbits.1284884465 Dec 20 12:54:55 PM PST 23 Dec 20 12:55:14 PM PST 23 87598644 ps
T945 /workspace/coverage/default/34.edn_alert_test.1294232663 Dec 20 12:53:40 PM PST 23 Dec 20 12:53:45 PM PST 23 61286914 ps
T946 /workspace/coverage/default/27.edn_smoke.4049761846 Dec 20 12:53:39 PM PST 23 Dec 20 12:53:44 PM PST 23 40580877 ps
T947 /workspace/coverage/default/21.edn_genbits.2910331338 Dec 20 12:53:36 PM PST 23 Dec 20 12:53:41 PM PST 23 23273186 ps
T948 /workspace/coverage/default/177.edn_genbits.1415773096 Dec 20 12:54:50 PM PST 23 Dec 20 12:55:09 PM PST 23 29670090 ps
T112 /workspace/coverage/default/25.edn_intr.2121230052 Dec 20 12:53:40 PM PST 23 Dec 20 12:53:46 PM PST 23 24545224 ps
T949 /workspace/coverage/default/281.edn_genbits.760495257 Dec 20 12:54:55 PM PST 23 Dec 20 12:55:23 PM PST 23 112272657 ps
T950 /workspace/coverage/default/221.edn_genbits.4120746417 Dec 20 12:55:00 PM PST 23 Dec 20 12:55:21 PM PST 23 86431695 ps
T166 /workspace/coverage/default/75.edn_err.4112227150 Dec 20 12:54:35 PM PST 23 Dec 20 12:54:48 PM PST 23 36294169 ps
T951 /workspace/coverage/default/244.edn_genbits.3793762159 Dec 20 12:54:49 PM PST 23 Dec 20 12:55:08 PM PST 23 38790421 ps
T952 /workspace/coverage/default/25.edn_alert_test.1995272461 Dec 20 12:53:36 PM PST 23 Dec 20 12:53:40 PM PST 23 23393441 ps
T953 /workspace/coverage/default/34.edn_intr.2244952288 Dec 20 12:53:44 PM PST 23 Dec 20 12:53:51 PM PST 23 20137225 ps
T954 /workspace/coverage/default/273.edn_genbits.1855238591 Dec 20 12:54:57 PM PST 23 Dec 20 12:55:22 PM PST 23 653729081 ps
T955 /workspace/coverage/default/47.edn_disable.3152552526 Dec 20 12:53:55 PM PST 23 Dec 20 12:54:05 PM PST 23 23153745 ps
T956 /workspace/coverage/default/17.edn_intr.3593636269 Dec 20 12:53:10 PM PST 23 Dec 20 12:53:24 PM PST 23 23926652 ps
T957 /workspace/coverage/default/269.edn_genbits.3018764932 Dec 20 12:54:55 PM PST 23 Dec 20 12:55:14 PM PST 23 88143183 ps
T958 /workspace/coverage/default/158.edn_genbits.2598159006 Dec 20 12:54:51 PM PST 23 Dec 20 12:55:10 PM PST 23 27843794 ps
T959 /workspace/coverage/default/29.edn_genbits.660583679 Dec 20 12:53:47 PM PST 23 Dec 20 12:53:55 PM PST 23 16130874 ps
T51 /workspace/coverage/default/1.edn_sec_cm.180989433 Dec 20 12:52:08 PM PST 23 Dec 20 12:52:35 PM PST 23 531445686 ps
T262 /workspace/coverage/default/215.edn_genbits.4183459735 Dec 20 12:54:50 PM PST 23 Dec 20 12:55:11 PM PST 23 100659282 ps
T960 /workspace/coverage/default/29.edn_stress_all.3011639215 Dec 20 12:53:42 PM PST 23 Dec 20 12:53:51 PM PST 23 678605599 ps
T342 /workspace/coverage/default/119.edn_genbits.595038414 Dec 20 12:54:39 PM PST 23 Dec 20 12:54:51 PM PST 23 22967352 ps
T961 /workspace/coverage/default/44.edn_intr.1637269911 Dec 20 12:53:51 PM PST 23 Dec 20 12:53:58 PM PST 23 26660898 ps
T962 /workspace/coverage/default/23.edn_disable_auto_req_mode.1603607601 Dec 20 12:53:37 PM PST 23 Dec 20 12:53:42 PM PST 23 31292442 ps
T963 /workspace/coverage/default/9.edn_intr.588610927 Dec 20 12:52:49 PM PST 23 Dec 20 12:53:02 PM PST 23 33096876 ps
T964 /workspace/coverage/default/24.edn_stress_all.3568367783 Dec 20 12:53:37 PM PST 23 Dec 20 12:53:44 PM PST 23 567716679 ps
T965 /workspace/coverage/default/70.edn_genbits.1251397880 Dec 20 12:54:38 PM PST 23 Dec 20 12:54:51 PM PST 23 76379281 ps
T966 /workspace/coverage/default/283.edn_genbits.4011661726 Dec 20 12:54:57 PM PST 23 Dec 20 12:55:18 PM PST 23 68700737 ps
T967 /workspace/coverage/default/11.edn_alert_test.581350967 Dec 20 12:52:49 PM PST 23 Dec 20 12:53:03 PM PST 23 15765326 ps
T968 /workspace/coverage/default/95.edn_err.2009511393 Dec 20 12:54:50 PM PST 23 Dec 20 12:55:09 PM PST 23 52385317 ps
T969 /workspace/coverage/default/14.edn_genbits.2742475652 Dec 20 12:52:55 PM PST 23 Dec 20 12:53:10 PM PST 23 80690716 ps
T323 /workspace/coverage/default/45.edn_alert.3293401854 Dec 20 12:53:56 PM PST 23 Dec 20 12:54:05 PM PST 23 27769580 ps
T970 /workspace/coverage/default/14.edn_intr.895971660 Dec 20 12:52:57 PM PST 23 Dec 20 12:53:12 PM PST 23 22200212 ps
T971 /workspace/coverage/default/16.edn_intr.393095896 Dec 20 12:53:06 PM PST 23 Dec 20 12:53:20 PM PST 23 22134730 ps
T972 /workspace/coverage/default/29.edn_disable_auto_req_mode.507096565 Dec 20 12:53:46 PM PST 23 Dec 20 12:53:52 PM PST 23 53538313 ps
T973 /workspace/coverage/default/74.edn_err.2696885834 Dec 20 12:54:38 PM PST 23 Dec 20 12:54:51 PM PST 23 29007100 ps
T974 /workspace/coverage/default/36.edn_alert_test.2287177397 Dec 20 12:53:55 PM PST 23 Dec 20 12:54:04 PM PST 23 17995034 ps

Test location /workspace/coverage/default/194.edn_genbits.2697767491
Short name T19
Test name
Test status
Simulation time 46754198 ps
CPU time 1.2 seconds
Started Dec 20 12:54:52 PM PST 23
Finished Dec 20 12:55:12 PM PST 23
Peak memory 205796 kb
Host smart-e4b290ae-ab4b-4db7-b412-f143bba427c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697767491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2697767491
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_err.3035082806
Short name T2
Test name
Test status
Simulation time 26216918 ps
CPU time 1.26 seconds
Started Dec 20 12:53:51 PM PST 23
Finished Dec 20 12:54:01 PM PST 23
Peak memory 228560 kb
Host smart-4900ca20-5761-4c22-9875-9e3ee0aab2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035082806 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.3035082806
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/45.edn_disable.2287002630
Short name T17
Test name
Test status
Simulation time 11086628 ps
CPU time 0.87 seconds
Started Dec 20 12:53:55 PM PST 23
Finished Dec 20 12:54:05 PM PST 23
Peak memory 214456 kb
Host smart-5e417bcd-2cce-4193-ba59-a8fceb725488
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287002630 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.2287002630
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1199697772
Short name T180
Test name
Test status
Simulation time 337094552 ps
CPU time 2.48 seconds
Started Dec 20 12:26:23 PM PST 23
Finished Dec 20 12:26:59 PM PST 23
Peak memory 206120 kb
Host smart-d327d021-3f68-4482-8c7e-ecb3aa9c8e32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199697772 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.1199697772
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/default/4.edn_sec_cm.2288136238
Short name T22
Test name
Test status
Simulation time 634405382 ps
CPU time 2.97 seconds
Started Dec 20 12:52:31 PM PST 23
Finished Dec 20 12:52:47 PM PST 23
Peak memory 233224 kb
Host smart-a4ead088-3a2b-443d-9ede-ac10d16877ff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288136238 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.2288136238
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.947194829
Short name T93
Test name
Test status
Simulation time 68946620919 ps
CPU time 1562.75 seconds
Started Dec 20 12:53:48 PM PST 23
Finished Dec 20 01:19:58 PM PST 23
Peak memory 217916 kb
Host smart-0cb27f71-137a-4c8f-a35b-0d977db18176
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947194829 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.947194829
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/126.edn_genbits.1955373917
Short name T8
Test name
Test status
Simulation time 43555168 ps
CPU time 1.69 seconds
Started Dec 20 12:54:48 PM PST 23
Finished Dec 20 12:55:07 PM PST 23
Peak memory 214308 kb
Host smart-cd4de70e-848e-456b-82df-55dbffb93ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955373917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.1955373917
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2309489792
Short name T27
Test name
Test status
Simulation time 19813513 ps
CPU time 1.25 seconds
Started Dec 20 12:25:26 PM PST 23
Finished Dec 20 12:25:52 PM PST 23
Peak memory 214328 kb
Host smart-7e254325-0675-47ce-a3f8-853882d37e51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309489792 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.2309489792
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.3691939737
Short name T148
Test name
Test status
Simulation time 22490988 ps
CPU time 0.95 seconds
Started Dec 20 12:53:38 PM PST 23
Finished Dec 20 12:53:44 PM PST 23
Peak memory 214588 kb
Host smart-64cd050b-4b7b-4ebc-9ba0-d8972ac12866
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691939737 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.3691939737
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.3190279039
Short name T40
Test name
Test status
Simulation time 22208219 ps
CPU time 0.8 seconds
Started Dec 20 12:25:28 PM PST 23
Finished Dec 20 12:25:56 PM PST 23
Peak memory 205748 kb
Host smart-56057860-8f3c-442e-b645-1acd6c4ad4e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190279039 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.3190279039
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/default/3.edn_sec_cm.2346804387
Short name T24
Test name
Test status
Simulation time 2012740470 ps
CPU time 2.92 seconds
Started Dec 20 12:52:01 PM PST 23
Finished Dec 20 12:52:20 PM PST 23
Peak memory 232948 kb
Host smart-58b416da-0104-45d2-a21b-0da8a2ecaff2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346804387 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.2346804387
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.672500774
Short name T188
Test name
Test status
Simulation time 226331772 ps
CPU time 5.98 seconds
Started Dec 20 12:25:08 PM PST 23
Finished Dec 20 12:25:33 PM PST 23
Peak memory 206076 kb
Host smart-50ea288a-bad6-4b73-821d-ef841d00fd88
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672500774 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.672500774
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/default/42.edn_intr.550985708
Short name T64
Test name
Test status
Simulation time 30282603 ps
CPU time 0.81 seconds
Started Dec 20 12:53:47 PM PST 23
Finished Dec 20 12:53:54 PM PST 23
Peak memory 214308 kb
Host smart-4c7116bc-53eb-433f-be1d-ba86aa5488b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550985708 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.550985708
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.471701072
Short name T155
Test name
Test status
Simulation time 27019598 ps
CPU time 1.05 seconds
Started Dec 20 12:53:55 PM PST 23
Finished Dec 20 12:54:05 PM PST 23
Peak memory 214648 kb
Host smart-96b4b375-a4dc-4266-961f-ee560920ff02
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471701072 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_di
sable_auto_req_mode.471701072
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_alert.3420985550
Short name T236
Test name
Test status
Simulation time 18659991 ps
CPU time 0.96 seconds
Started Dec 20 12:52:36 PM PST 23
Finished Dec 20 12:52:50 PM PST 23
Peak memory 205804 kb
Host smart-d38e6305-c08d-412e-ad2a-c754e050a144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420985550 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.3420985550
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.4059301639
Short name T132
Test name
Test status
Simulation time 290365274 ps
CPU time 1.15 seconds
Started Dec 20 12:53:40 PM PST 23
Finished Dec 20 12:53:46 PM PST 23
Peak memory 214572 kb
Host smart-657d2d47-12ec-4316-b57f-81e7f2629328
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059301639 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.4059301639
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_disable.2680669644
Short name T168
Test name
Test status
Simulation time 54877763 ps
CPU time 0.83 seconds
Started Dec 20 12:51:59 PM PST 23
Finished Dec 20 12:52:15 PM PST 23
Peak memory 214244 kb
Host smart-c1e6b5be-a31d-46ec-b60e-014626df3306
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680669644 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.2680669644
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/34.edn_genbits.1976328509
Short name T32
Test name
Test status
Simulation time 38295659 ps
CPU time 1.02 seconds
Started Dec 20 12:53:44 PM PST 23
Finished Dec 20 12:53:51 PM PST 23
Peak memory 205224 kb
Host smart-3bca314f-6e2e-4136-b740-3d0ceff7491e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976328509 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.1976328509
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_disable.935273646
Short name T115
Test name
Test status
Simulation time 24334067 ps
CPU time 0.82 seconds
Started Dec 20 12:53:09 PM PST 23
Finished Dec 20 12:53:24 PM PST 23
Peak memory 214380 kb
Host smart-91df87b8-19ef-4592-b0c0-d8ed70dcc5eb
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935273646 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.935273646
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/0.edn_regwen.4038367070
Short name T913
Test name
Test status
Simulation time 20214516 ps
CPU time 0.86 seconds
Started Dec 20 12:51:55 PM PST 23
Finished Dec 20 12:52:10 PM PST 23
Peak memory 205088 kb
Host smart-48e906a2-2e8b-47c5-a639-f632e4ffba75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038367070 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.4038367070
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_disable.517943483
Short name T911
Test name
Test status
Simulation time 31546842 ps
CPU time 0.83 seconds
Started Dec 20 12:52:00 PM PST 23
Finished Dec 20 12:52:17 PM PST 23
Peak memory 214320 kb
Host smart-a648da04-d866-469d-a16b-45db0ba18c46
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517943483 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.517943483
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable.3879705959
Short name T122
Test name
Test status
Simulation time 16713267 ps
CPU time 0.86 seconds
Started Dec 20 12:53:49 PM PST 23
Finished Dec 20 12:53:57 PM PST 23
Peak memory 214076 kb
Host smart-eaf4f651-fa8e-4720-b9b7-c2548a8eef3d
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879705959 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.3879705959
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/4.edn_err.1344474072
Short name T7
Test name
Test status
Simulation time 46382338 ps
CPU time 1.26 seconds
Started Dec 20 12:52:29 PM PST 23
Finished Dec 20 12:52:44 PM PST 23
Peak memory 227648 kb
Host smart-c51a181f-ec5d-4817-a20c-162f60710091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344474072 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.1344474072
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/0.edn_intr.2095860948
Short name T88
Test name
Test status
Simulation time 58265570 ps
CPU time 0.8 seconds
Started Dec 20 12:51:48 PM PST 23
Finished Dec 20 12:52:01 PM PST 23
Peak memory 214152 kb
Host smart-d98173f8-bb91-447f-a050-ff273aed99f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095860948 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.2095860948
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.600275181
Short name T257
Test name
Test status
Simulation time 68932678164 ps
CPU time 1522.31 seconds
Started Dec 20 12:53:45 PM PST 23
Finished Dec 20 01:19:13 PM PST 23
Peak memory 216272 kb
Host smart-0e9ac11e-24d9-446b-b342-6195cb8fe9c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600275181 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.600275181
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.851333315
Short name T5
Test name
Test status
Simulation time 110616574518 ps
CPU time 849.35 seconds
Started Dec 20 12:52:08 PM PST 23
Finished Dec 20 01:06:36 PM PST 23
Peak memory 215172 kb
Host smart-b3a5ecb4-2999-42a2-b049-2b8c27b1134f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851333315 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.851333315
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/139.edn_genbits.3077209816
Short name T264
Test name
Test status
Simulation time 34941114 ps
CPU time 0.97 seconds
Started Dec 20 12:54:57 PM PST 23
Finished Dec 20 12:55:18 PM PST 23
Peak memory 205428 kb
Host smart-ef315415-4de1-4191-9121-a5413d97035c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077209816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.3077209816
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.1720237295
Short name T185
Test name
Test status
Simulation time 948097759 ps
CPU time 5.22 seconds
Started Dec 20 12:25:19 PM PST 23
Finished Dec 20 12:25:46 PM PST 23
Peak memory 214424 kb
Host smart-07ae134b-1c33-445a-83d8-9c4d86634501
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720237295 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.1720237295
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.3356000398
Short name T224
Test name
Test status
Simulation time 25675245 ps
CPU time 1.06 seconds
Started Dec 20 12:53:49 PM PST 23
Finished Dec 20 12:53:57 PM PST 23
Peak memory 214568 kb
Host smart-a2cb5f21-bec9-48df-bc43-4b42994c4884
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356000398 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.3356000398
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_disable.1958523205
Short name T117
Test name
Test status
Simulation time 15274133 ps
CPU time 0.91 seconds
Started Dec 20 12:53:57 PM PST 23
Finished Dec 20 12:54:08 PM PST 23
Peak memory 214576 kb
Host smart-6bb4f579-3c90-4fcd-a986-28544423422f
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958523205 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.1958523205
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/107.edn_genbits.2116240597
Short name T345
Test name
Test status
Simulation time 29992448 ps
CPU time 1.23 seconds
Started Dec 20 12:54:39 PM PST 23
Finished Dec 20 12:54:53 PM PST 23
Peak memory 213264 kb
Host smart-7fd7d13d-f702-4316-b2a9-7ac7c5841cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116240597 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.2116240597
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_disable.4251997923
Short name T598
Test name
Test status
Simulation time 14108643 ps
CPU time 0.87 seconds
Started Dec 20 12:52:48 PM PST 23
Finished Dec 20 12:53:01 PM PST 23
Peak memory 214480 kb
Host smart-c39664a3-aa47-4d01-9294-31baa0d5d6ea
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251997923 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.4251997923
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.4128208001
Short name T137
Test name
Test status
Simulation time 52997377 ps
CPU time 1.03 seconds
Started Dec 20 12:52:51 PM PST 23
Finished Dec 20 12:53:06 PM PST 23
Peak memory 214716 kb
Host smart-87ce99fe-0ae4-4833-9d8f-abc7b30b1bca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128208001 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.4128208001
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_disable.3524969367
Short name T225
Test name
Test status
Simulation time 13612886 ps
CPU time 0.88 seconds
Started Dec 20 12:52:58 PM PST 23
Finished Dec 20 12:53:12 PM PST 23
Peak memory 214480 kb
Host smart-4aa104f8-ce82-418b-984d-90a3c8fd8e3b
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524969367 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.3524969367
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.1489261970
Short name T142
Test name
Test status
Simulation time 94438873 ps
CPU time 0.94 seconds
Started Dec 20 12:52:55 PM PST 23
Finished Dec 20 12:53:10 PM PST 23
Peak memory 214644 kb
Host smart-bcc19715-ff43-4153-b8a8-3e6e095dea6a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489261970 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.1489261970
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_disable.1338289221
Short name T101
Test name
Test status
Simulation time 11605896 ps
CPU time 0.83 seconds
Started Dec 20 12:53:01 PM PST 23
Finished Dec 20 12:53:15 PM PST 23
Peak memory 214372 kb
Host smart-7c854ab6-51dd-4c6d-bb4f-13653f62cd9b
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338289221 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.1338289221
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable.1305426143
Short name T170
Test name
Test status
Simulation time 22293548 ps
CPU time 0.83 seconds
Started Dec 20 12:53:33 PM PST 23
Finished Dec 20 12:53:37 PM PST 23
Peak memory 214308 kb
Host smart-34c25f48-a05c-4bd0-a8ef-862f5e57da07
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305426143 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.1305426143
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.1970312127
Short name T157
Test name
Test status
Simulation time 29850159 ps
CPU time 0.94 seconds
Started Dec 20 12:53:43 PM PST 23
Finished Dec 20 12:53:50 PM PST 23
Peak memory 214620 kb
Host smart-18dcd236-5a8d-493b-a5d2-868b97eb4809
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970312127 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.1970312127
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.279536327
Short name T283
Test name
Test status
Simulation time 169568588 ps
CPU time 0.85 seconds
Started Dec 20 12:26:16 PM PST 23
Finished Dec 20 12:26:48 PM PST 23
Peak memory 206088 kb
Host smart-6d1fc2a7-a815-44ec-a6b5-4163775cc4a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279536327 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.279536327
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/default/169.edn_genbits.2347817933
Short name T248
Test name
Test status
Simulation time 122726579 ps
CPU time 0.88 seconds
Started Dec 20 12:54:48 PM PST 23
Finished Dec 20 12:55:06 PM PST 23
Peak memory 205280 kb
Host smart-2158d4a6-cb2d-4d3e-a07e-dc23dc974e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347817933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.2347817933
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.871795014
Short name T52
Test name
Test status
Simulation time 28736616 ps
CPU time 1.05 seconds
Started Dec 20 12:54:53 PM PST 23
Finished Dec 20 12:55:12 PM PST 23
Peak memory 205476 kb
Host smart-88b180b2-3687-493e-8a4b-2a66e7c864a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871795014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.871795014
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_regwen.2105910620
Short name T241
Test name
Test status
Simulation time 16196949 ps
CPU time 0.89 seconds
Started Dec 20 12:52:44 PM PST 23
Finished Dec 20 12:52:57 PM PST 23
Peak memory 204844 kb
Host smart-70050dd4-1c7f-4a6c-ba14-6dbe4a8d08e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105910620 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.2105910620
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_alert.694542763
Short name T315
Test name
Test status
Simulation time 126010232 ps
CPU time 0.94 seconds
Started Dec 20 12:51:53 PM PST 23
Finished Dec 20 12:52:08 PM PST 23
Peak memory 206008 kb
Host smart-095a0007-f106-4389-b362-965b8c35aec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694542763 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.694542763
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert.3975603935
Short name T316
Test name
Test status
Simulation time 51193100 ps
CPU time 0.98 seconds
Started Dec 20 12:52:59 PM PST 23
Finished Dec 20 12:53:13 PM PST 23
Peak memory 205076 kb
Host smart-c5b9d91a-bf4b-4eba-a8d8-4a7ea43dd5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975603935 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.3975603935
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert.357989665
Short name T234
Test name
Test status
Simulation time 33820225 ps
CPU time 0.97 seconds
Started Dec 20 12:53:38 PM PST 23
Finished Dec 20 12:53:43 PM PST 23
Peak memory 205836 kb
Host smart-8970de60-8933-4b18-8b58-39b947b76f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357989665 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.357989665
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.539690895
Short name T293
Test name
Test status
Simulation time 137079136 ps
CPU time 0.96 seconds
Started Dec 20 12:54:46 PM PST 23
Finished Dec 20 12:55:02 PM PST 23
Peak memory 205176 kb
Host smart-fdbcf7e3-6289-4716-bfb9-e827238fc453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539690895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.539690895
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.2167781849
Short name T276
Test name
Test status
Simulation time 20316943 ps
CPU time 1.02 seconds
Started Dec 20 12:54:49 PM PST 23
Finished Dec 20 12:55:07 PM PST 23
Peak memory 214248 kb
Host smart-dc0b7ff1-214e-4d8b-b315-6b94158809c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167781849 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.2167781849
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_genbits.513436957
Short name T331
Test name
Test status
Simulation time 34177315 ps
CPU time 0.88 seconds
Started Dec 20 12:54:48 PM PST 23
Finished Dec 20 12:55:06 PM PST 23
Peak memory 205088 kb
Host smart-8be44447-f6a3-4111-be48-a8b42f12f6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513436957 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.513436957
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.645632801
Short name T201
Test name
Test status
Simulation time 96748883 ps
CPU time 2.34 seconds
Started Dec 20 12:25:24 PM PST 23
Finished Dec 20 12:25:52 PM PST 23
Peak memory 206116 kb
Host smart-6341312d-7648-41a0-b39b-d5568981493a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645632801 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.645632801
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/default/1.edn_regwen.3552748294
Short name T309
Test name
Test status
Simulation time 123121270 ps
CPU time 0.89 seconds
Started Dec 20 12:51:52 PM PST 23
Finished Dec 20 12:52:08 PM PST 23
Peak memory 204688 kb
Host smart-c6b40f06-eaab-4ec0-a0ab-73272e7362a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552748294 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.3552748294
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/110.edn_genbits.2061251043
Short name T705
Test name
Test status
Simulation time 39864942 ps
CPU time 1.14 seconds
Started Dec 20 12:54:42 PM PST 23
Finished Dec 20 12:54:55 PM PST 23
Peak memory 214292 kb
Host smart-b091a601-b5b7-4b23-b654-c627858cd8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061251043 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2061251043
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.612273028
Short name T326
Test name
Test status
Simulation time 15853409 ps
CPU time 0.93 seconds
Started Dec 20 12:54:42 PM PST 23
Finished Dec 20 12:54:56 PM PST 23
Peak memory 205020 kb
Host smart-246aa8d0-ac84-48f5-9144-abb8f1fdb546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612273028 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.612273028
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_stress_all.1036062867
Short name T607
Test name
Test status
Simulation time 75670327 ps
CPU time 1.63 seconds
Started Dec 20 12:53:11 PM PST 23
Finished Dec 20 12:53:26 PM PST 23
Peak memory 205488 kb
Host smart-e659a47b-72ab-4cd2-9957-b16eaa245c75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036062867 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.1036062867
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/247.edn_genbits.2316363347
Short name T268
Test name
Test status
Simulation time 101453264 ps
CPU time 1.49 seconds
Started Dec 20 12:54:49 PM PST 23
Finished Dec 20 12:55:07 PM PST 23
Peak memory 214336 kb
Host smart-f8ae003b-83cc-4f11-8c4f-83d2f3685c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316363347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.2316363347
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.628545472
Short name T709
Test name
Test status
Simulation time 16868855 ps
CPU time 0.95 seconds
Started Dec 20 12:55:01 PM PST 23
Finished Dec 20 12:55:24 PM PST 23
Peak memory 205132 kb
Host smart-cd81c13a-160d-4c3d-940a-ed989eec81ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628545472 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.628545472
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.3520378787
Short name T87
Test name
Test status
Simulation time 25729403 ps
CPU time 1.29 seconds
Started Dec 20 12:53:53 PM PST 23
Finished Dec 20 12:54:02 PM PST 23
Peak memory 228336 kb
Host smart-3a16aa21-07a9-4fb7-9eb4-382b28fe92ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520378787 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.3520378787
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/12.edn_alert_test.2807186443
Short name T473
Test name
Test status
Simulation time 34378284 ps
CPU time 0.97 seconds
Started Dec 20 12:52:58 PM PST 23
Finished Dec 20 12:53:12 PM PST 23
Peak memory 205284 kb
Host smart-420e4107-6240-4772-a8ad-0294248398d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807186443 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2807186443
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_intr.3146787025
Short name T81
Test name
Test status
Simulation time 18490655 ps
CPU time 0.96 seconds
Started Dec 20 12:53:35 PM PST 23
Finished Dec 20 12:53:39 PM PST 23
Peak memory 214616 kb
Host smart-bc13a313-646f-43a4-87b2-ad36d356654d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146787025 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.3146787025
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/244.edn_genbits.3793762159
Short name T951
Test name
Test status
Simulation time 38790421 ps
CPU time 1.48 seconds
Started Dec 20 12:54:49 PM PST 23
Finished Dec 20 12:55:08 PM PST 23
Peak memory 214204 kb
Host smart-cc693026-6a2b-4027-a859-98e5bbc3ce88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793762159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.3793762159
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3901818822
Short name T212
Test name
Test status
Simulation time 29229314 ps
CPU time 1.02 seconds
Started Dec 20 12:27:37 PM PST 23
Finished Dec 20 12:28:13 PM PST 23
Peak memory 206096 kb
Host smart-b01fa6e7-1b09-4978-9c23-9e0b0872e2f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901818822 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.3901818822
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/default/16.edn_intr.393095896
Short name T971
Test name
Test status
Simulation time 22134730 ps
CPU time 1.02 seconds
Started Dec 20 12:53:06 PM PST 23
Finished Dec 20 12:53:20 PM PST 23
Peak memory 225900 kb
Host smart-7d9e9ec3-f592-4e91-befe-623fdb34c01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393095896 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.393095896
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.367833519
Short name T360
Test name
Test status
Simulation time 78084470 ps
CPU time 0.76 seconds
Started Dec 20 12:26:01 PM PST 23
Finished Dec 20 12:26:25 PM PST 23
Peak memory 205984 kb
Host smart-17d42221-9a94-4077-bbe4-63828ff1730b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367833519 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.367833519
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/default/105.edn_genbits.3807596026
Short name T887
Test name
Test status
Simulation time 38548388 ps
CPU time 1.06 seconds
Started Dec 20 12:54:57 PM PST 23
Finished Dec 20 12:55:16 PM PST 23
Peak memory 205344 kb
Host smart-3a4ab640-ddb4-48e5-91fd-c7e4c932d077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807596026 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.3807596026
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.3785195912
Short name T478
Test name
Test status
Simulation time 27590116 ps
CPU time 0.99 seconds
Started Dec 20 12:54:57 PM PST 23
Finished Dec 20 12:55:18 PM PST 23
Peak memory 205436 kb
Host smart-e44e2ccc-3f28-4657-b3e8-6d3deafecad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785195912 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.3785195912
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.2338528232
Short name T312
Test name
Test status
Simulation time 93760438 ps
CPU time 0.88 seconds
Started Dec 20 12:52:48 PM PST 23
Finished Dec 20 12:53:01 PM PST 23
Peak memory 205164 kb
Host smart-4696d5c0-02b0-477f-a7ba-7246940bb141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338528232 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.2338528232
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.595038414
Short name T342
Test name
Test status
Simulation time 22967352 ps
CPU time 0.91 seconds
Started Dec 20 12:54:39 PM PST 23
Finished Dec 20 12:54:51 PM PST 23
Peak memory 205024 kb
Host smart-ff8d84bd-f0eb-405c-85b9-2d32a8248f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595038414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.595038414
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.3267013680
Short name T274
Test name
Test status
Simulation time 16455519 ps
CPU time 0.95 seconds
Started Dec 20 12:54:48 PM PST 23
Finished Dec 20 12:55:05 PM PST 23
Peak memory 204952 kb
Host smart-23bf116d-9b06-4c8b-a83b-e4754bd5001a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267013680 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.3267013680
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.1651652755
Short name T336
Test name
Test status
Simulation time 81084797 ps
CPU time 0.87 seconds
Started Dec 20 12:54:47 PM PST 23
Finished Dec 20 12:55:03 PM PST 23
Peak memory 205088 kb
Host smart-57cebedb-02c4-4788-b998-9261ac2a9a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651652755 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.1651652755
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2214182881
Short name T831
Test name
Test status
Simulation time 67418494746 ps
CPU time 794.01 seconds
Started Dec 20 12:53:02 PM PST 23
Finished Dec 20 01:06:29 PM PST 23
Peak memory 214928 kb
Host smart-7610e6a2-cf2c-4ba7-b032-63dc62643080
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214182881 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.2214182881
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/188.edn_genbits.239511322
Short name T335
Test name
Test status
Simulation time 66165954 ps
CPU time 0.96 seconds
Started Dec 20 12:55:00 PM PST 23
Finished Dec 20 12:55:22 PM PST 23
Peak memory 205872 kb
Host smart-76b4d1a9-2494-4b92-88eb-73dfc1d64e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239511322 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.239511322
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_regwen.1102558569
Short name T320
Test name
Test status
Simulation time 21174812 ps
CPU time 0.83 seconds
Started Dec 20 12:52:01 PM PST 23
Finished Dec 20 12:52:18 PM PST 23
Peak memory 204908 kb
Host smart-809f8acb-24f7-43f9-b364-173db09e1089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102558569 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.1102558569
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/215.edn_genbits.4183459735
Short name T262
Test name
Test status
Simulation time 100659282 ps
CPU time 2.43 seconds
Started Dec 20 12:54:50 PM PST 23
Finished Dec 20 12:55:11 PM PST 23
Peak memory 214260 kb
Host smart-6ebdc25f-dff6-407e-9d79-71973a285581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183459735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.4183459735
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.1832882541
Short name T272
Test name
Test status
Simulation time 30827243 ps
CPU time 1.1 seconds
Started Dec 20 12:55:02 PM PST 23
Finished Dec 20 12:55:24 PM PST 23
Peak memory 214240 kb
Host smart-2365ca6d-a256-4fbe-9b2e-cb90c394b8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832882541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.1832882541
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_disable.509334898
Short name T113
Test name
Test status
Simulation time 14562706 ps
CPU time 0.83 seconds
Started Dec 20 12:53:39 PM PST 23
Finished Dec 20 12:53:44 PM PST 23
Peak memory 214408 kb
Host smart-9af6ba79-02ba-4d22-9074-8da68df935cf
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509334898 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.509334898
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable.3881293838
Short name T125
Test name
Test status
Simulation time 14036058 ps
CPU time 0.88 seconds
Started Dec 20 12:53:48 PM PST 23
Finished Dec 20 12:53:56 PM PST 23
Peak memory 214472 kb
Host smart-65105549-90fa-4f1b-bcd8-f43cb4eb82f3
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881293838 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.3881293838
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable.3934277943
Short name T126
Test name
Test status
Simulation time 40594967 ps
CPU time 0.83 seconds
Started Dec 20 12:53:42 PM PST 23
Finished Dec 20 12:53:48 PM PST 23
Peak memory 214464 kb
Host smart-4bef5401-ccf3-43f0-907f-a1bd8dba4d60
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934277943 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.3934277943
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.111586116
Short name T108
Test name
Test status
Simulation time 67990308 ps
CPU time 0.92 seconds
Started Dec 20 12:53:55 PM PST 23
Finished Dec 20 12:54:05 PM PST 23
Peak memory 206184 kb
Host smart-833acd8b-67f6-4225-b045-e1bf2642e533
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111586116 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_di
sable_auto_req_mode.111586116
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/114.edn_genbits.2127554302
Short name T9
Test name
Test status
Simulation time 49932736 ps
CPU time 1.22 seconds
Started Dec 20 12:54:48 PM PST 23
Finished Dec 20 12:55:05 PM PST 23
Peak memory 214296 kb
Host smart-ae53b27b-9a25-4fb6-9bcb-bbde97bd0f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127554302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.2127554302
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2685519980
Short name T388
Test name
Test status
Simulation time 32457811 ps
CPU time 1.4 seconds
Started Dec 20 12:25:44 PM PST 23
Finished Dec 20 12:26:13 PM PST 23
Peak memory 206076 kb
Host smart-1e15e5d8-6a12-4896-9031-5ccc49f78b9e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685519980 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.2685519980
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.639194550
Short name T197
Test name
Test status
Simulation time 244641246 ps
CPU time 3.51 seconds
Started Dec 20 12:25:27 PM PST 23
Finished Dec 20 12:25:56 PM PST 23
Peak memory 206108 kb
Host smart-041c7af9-b998-4307-b704-78805d2bbe1b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639194550 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.639194550
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.4125591751
Short name T442
Test name
Test status
Simulation time 19928203 ps
CPU time 0.91 seconds
Started Dec 20 12:26:27 PM PST 23
Finished Dec 20 12:27:02 PM PST 23
Peak memory 206076 kb
Host smart-6296b2da-c121-4987-b11c-c232d0bf7dcb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125591751 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.4125591751
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2392306218
Short name T179
Test name
Test status
Simulation time 292734696 ps
CPU time 1.14 seconds
Started Dec 20 12:25:33 PM PST 23
Finished Dec 20 12:26:04 PM PST 23
Peak memory 214452 kb
Host smart-5c0bd5da-07b1-42d1-9598-1216eefc3580
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392306218 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.2392306218
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.2178946065
Short name T353
Test name
Test status
Simulation time 15992964 ps
CPU time 0.87 seconds
Started Dec 20 12:25:22 PM PST 23
Finished Dec 20 12:25:47 PM PST 23
Peak memory 205972 kb
Host smart-b86b7434-0e0a-492f-b613-03fe8ac658e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178946065 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.2178946065
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1730558442
Short name T416
Test name
Test status
Simulation time 39438941 ps
CPU time 0.94 seconds
Started Dec 20 12:28:46 PM PST 23
Finished Dec 20 12:29:21 PM PST 23
Peak memory 205044 kb
Host smart-531adff6-77be-4c5c-985d-63488a0e58ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730558442 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.1730558442
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3746032711
Short name T199
Test name
Test status
Simulation time 357259074 ps
CPU time 1.39 seconds
Started Dec 20 12:24:25 PM PST 23
Finished Dec 20 12:24:59 PM PST 23
Peak memory 206020 kb
Host smart-5b581eaf-f90a-4484-8e8b-3ee98c074302
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746032711 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.3746032711
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.4159043281
Short name T206
Test name
Test status
Simulation time 72622746 ps
CPU time 1.46 seconds
Started Dec 20 12:24:38 PM PST 23
Finished Dec 20 12:25:13 PM PST 23
Peak memory 206132 kb
Host smart-a689f75f-5a0b-4dfb-bb53-f0254288023a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159043281 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.4159043281
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1841222556
Short name T396
Test name
Test status
Simulation time 216832088 ps
CPU time 3.18 seconds
Started Dec 20 12:25:21 PM PST 23
Finished Dec 20 12:25:48 PM PST 23
Peak memory 206076 kb
Host smart-21c996a4-c46e-4e44-81fe-d9c57e01d946
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841222556 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.1841222556
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.427188418
Short name T453
Test name
Test status
Simulation time 53518835 ps
CPU time 0.9 seconds
Started Dec 20 12:24:34 PM PST 23
Finished Dec 20 12:25:08 PM PST 23
Peak memory 206012 kb
Host smart-60858602-91d1-4d69-a881-791204e7bc0a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427188418 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.427188418
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3890245806
Short name T184
Test name
Test status
Simulation time 69401146 ps
CPU time 1.13 seconds
Started Dec 20 12:25:07 PM PST 23
Finished Dec 20 12:25:28 PM PST 23
Peak memory 216132 kb
Host smart-793c5e29-38ac-46d9-8e47-fc6946290c90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890245806 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.3890245806
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.713034767
Short name T409
Test name
Test status
Simulation time 18701324 ps
CPU time 0.8 seconds
Started Dec 20 12:25:18 PM PST 23
Finished Dec 20 12:25:40 PM PST 23
Peak memory 205924 kb
Host smart-99f7165f-07ad-4f52-9b69-5aa8789e1b3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713034767 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.713034767
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.2724907246
Short name T391
Test name
Test status
Simulation time 230784857 ps
CPU time 0.83 seconds
Started Dec 20 12:25:17 PM PST 23
Finished Dec 20 12:25:38 PM PST 23
Peak memory 205968 kb
Host smart-2aed4cb4-b74f-4f47-aa6a-14fbfd07f277
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724907246 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.2724907246
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.275475748
Short name T452
Test name
Test status
Simulation time 64995749 ps
CPU time 1.32 seconds
Started Dec 20 12:24:31 PM PST 23
Finished Dec 20 12:25:03 PM PST 23
Peak memory 206068 kb
Host smart-ab627f7b-79ef-465a-86ee-7a7b053395d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275475748 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_out
standing.275475748
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.310008591
Short name T373
Test name
Test status
Simulation time 48547058 ps
CPU time 1.68 seconds
Started Dec 20 12:25:46 PM PST 23
Finished Dec 20 12:26:14 PM PST 23
Peak memory 214432 kb
Host smart-53c4460f-73de-4992-989c-f471a12cf0f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310008591 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.310008591
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3908476675
Short name T450
Test name
Test status
Simulation time 136104328 ps
CPU time 1.78 seconds
Started Dec 20 12:25:14 PM PST 23
Finished Dec 20 12:25:34 PM PST 23
Peak memory 206044 kb
Host smart-c897e322-f846-46e2-ad1a-00f16e9b0a2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908476675 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.3908476675
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.61185000
Short name T372
Test name
Test status
Simulation time 41342887 ps
CPU time 1.61 seconds
Started Dec 20 12:26:11 PM PST 23
Finished Dec 20 12:26:41 PM PST 23
Peak memory 214364 kb
Host smart-89646e49-539c-40f7-a75e-7f3ec4e59aca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61185000 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.61185000
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.1690903157
Short name T390
Test name
Test status
Simulation time 13026242 ps
CPU time 0.84 seconds
Started Dec 20 12:26:07 PM PST 23
Finished Dec 20 12:26:34 PM PST 23
Peak memory 206172 kb
Host smart-96c5d831-2152-40c3-acf5-63ba4c89eb3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690903157 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.1690903157
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.1316171123
Short name T387
Test name
Test status
Simulation time 21117551 ps
CPU time 0.81 seconds
Started Dec 20 12:24:44 PM PST 23
Finished Dec 20 12:25:17 PM PST 23
Peak memory 205884 kb
Host smart-24d8f9d0-93b1-4273-b568-83329e1293e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316171123 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.1316171123
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.3889529869
Short name T200
Test name
Test status
Simulation time 152627327 ps
CPU time 4.51 seconds
Started Dec 20 12:25:56 PM PST 23
Finished Dec 20 12:26:24 PM PST 23
Peak memory 214400 kb
Host smart-95a063b8-3b9e-4f73-80f1-a664b6700502
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889529869 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.3889529869
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3405295164
Short name T440
Test name
Test status
Simulation time 88512738 ps
CPU time 2.32 seconds
Started Dec 20 12:26:41 PM PST 23
Finished Dec 20 12:27:15 PM PST 23
Peak memory 206076 kb
Host smart-530ef198-e410-46e6-8369-03479ba9fb15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405295164 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.3405295164
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.4045272912
Short name T181
Test name
Test status
Simulation time 88146115 ps
CPU time 1.71 seconds
Started Dec 20 12:26:11 PM PST 23
Finished Dec 20 12:26:40 PM PST 23
Peak memory 214352 kb
Host smart-0b662e8b-20ed-4da1-b3c9-0c0ee93c6975
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045272912 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.4045272912
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.1669021282
Short name T211
Test name
Test status
Simulation time 14734966 ps
CPU time 0.91 seconds
Started Dec 20 12:25:21 PM PST 23
Finished Dec 20 12:25:45 PM PST 23
Peak memory 206072 kb
Host smart-5d6f4eb5-182b-4f5b-be8b-79c49e99ab72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669021282 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.1669021282
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.1790513120
Short name T398
Test name
Test status
Simulation time 22006902 ps
CPU time 0.83 seconds
Started Dec 20 12:25:32 PM PST 23
Finished Dec 20 12:26:01 PM PST 23
Peak memory 206060 kb
Host smart-b445fcd6-61ce-4c58-aa0c-a89582e35bea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790513120 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.1790513120
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1532515972
Short name T393
Test name
Test status
Simulation time 19721090 ps
CPU time 1.17 seconds
Started Dec 20 12:24:33 PM PST 23
Finished Dec 20 12:25:05 PM PST 23
Peak memory 206116 kb
Host smart-f48a9d30-cecd-4fbc-8a0d-dd66f5654488
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532515972 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.1532515972
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.975098906
Short name T376
Test name
Test status
Simulation time 85673980 ps
CPU time 1.61 seconds
Started Dec 20 12:26:05 PM PST 23
Finished Dec 20 12:26:30 PM PST 23
Peak memory 214336 kb
Host smart-450898c5-bb57-481e-ba44-a0446b4728ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975098906 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.975098906
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1180678604
Short name T395
Test name
Test status
Simulation time 217994082 ps
CPU time 1.95 seconds
Started Dec 20 12:26:01 PM PST 23
Finished Dec 20 12:26:26 PM PST 23
Peak memory 206152 kb
Host smart-743cb5e3-eb85-41a9-8d37-e88bc83230c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180678604 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1180678604
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.309962332
Short name T193
Test name
Test status
Simulation time 117564644 ps
CPU time 1.4 seconds
Started Dec 20 12:25:24 PM PST 23
Finished Dec 20 12:25:50 PM PST 23
Peak memory 214344 kb
Host smart-0929c985-ca20-41df-8bc8-e2ec7f92473b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309962332 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.309962332
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.1744376661
Short name T441
Test name
Test status
Simulation time 22505673 ps
CPU time 0.82 seconds
Started Dec 20 12:24:50 PM PST 23
Finished Dec 20 12:25:20 PM PST 23
Peak memory 205916 kb
Host smart-b0e48511-4a4d-4d10-ac78-105d07e13a91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744376661 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.1744376661
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.3889643537
Short name T383
Test name
Test status
Simulation time 21949057 ps
CPU time 0.82 seconds
Started Dec 20 12:26:12 PM PST 23
Finished Dec 20 12:26:41 PM PST 23
Peak memory 206044 kb
Host smart-535dbb07-5daa-433d-85ad-9518e30c996f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889643537 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.3889643537
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.4086469834
Short name T352
Test name
Test status
Simulation time 62650626 ps
CPU time 1.09 seconds
Started Dec 20 12:25:48 PM PST 23
Finished Dec 20 12:26:15 PM PST 23
Peak memory 206028 kb
Host smart-1d240495-b9b8-46a6-a76e-f0a355140665
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086469834 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.4086469834
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.3635724983
Short name T368
Test name
Test status
Simulation time 344981633 ps
CPU time 3.15 seconds
Started Dec 20 12:25:18 PM PST 23
Finished Dec 20 12:25:41 PM PST 23
Peak memory 214384 kb
Host smart-92cfa998-e667-4745-b10f-e20b4ef17a2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635724983 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3635724983
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3097660327
Short name T400
Test name
Test status
Simulation time 92751378 ps
CPU time 2.62 seconds
Started Dec 20 12:24:33 PM PST 23
Finished Dec 20 12:25:08 PM PST 23
Peak memory 206096 kb
Host smart-50d911f9-2b64-40b8-95a9-335e698087ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097660327 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.3097660327
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.120140416
Short name T210
Test name
Test status
Simulation time 12350697 ps
CPU time 0.88 seconds
Started Dec 20 12:24:30 PM PST 23
Finished Dec 20 12:25:03 PM PST 23
Peak memory 206072 kb
Host smart-05e4be29-fb69-45ef-9cf9-12f98008a353
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120140416 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.120140416
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.883242319
Short name T361
Test name
Test status
Simulation time 12498961 ps
CPU time 0.85 seconds
Started Dec 20 12:24:40 PM PST 23
Finished Dec 20 12:25:13 PM PST 23
Peak memory 206056 kb
Host smart-50e2a2e3-394d-4c7d-80b3-d306c1c13edf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883242319 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.883242319
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.343568701
Short name T403
Test name
Test status
Simulation time 18970366 ps
CPU time 0.89 seconds
Started Dec 20 12:24:58 PM PST 23
Finished Dec 20 12:25:24 PM PST 23
Peak memory 206124 kb
Host smart-dcc8e490-f175-4c30-8906-62b48545abba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343568701 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_ou
tstanding.343568701
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.359425781
Short name T457
Test name
Test status
Simulation time 70332582 ps
CPU time 2.45 seconds
Started Dec 20 12:24:37 PM PST 23
Finished Dec 20 12:25:13 PM PST 23
Peak memory 214320 kb
Host smart-d8842586-6602-4f9d-beb5-1322cb2ed346
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359425781 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.359425781
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1412783833
Short name T430
Test name
Test status
Simulation time 94970516 ps
CPU time 2.52 seconds
Started Dec 20 12:24:44 PM PST 23
Finished Dec 20 12:25:19 PM PST 23
Peak memory 206092 kb
Host smart-108934df-d2ba-46aa-ba47-474f0931a12f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412783833 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1412783833
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3525983019
Short name T434
Test name
Test status
Simulation time 142074709 ps
CPU time 1.17 seconds
Started Dec 20 12:25:26 PM PST 23
Finished Dec 20 12:25:52 PM PST 23
Peak memory 214332 kb
Host smart-fdc055d3-eff8-431c-b7d2-37c0c98a4523
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525983019 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.3525983019
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.681465525
Short name T203
Test name
Test status
Simulation time 20915740 ps
CPU time 0.84 seconds
Started Dec 20 12:25:22 PM PST 23
Finished Dec 20 12:25:47 PM PST 23
Peak memory 205944 kb
Host smart-c4795cc5-f33b-48df-8470-25fe0a530abe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681465525 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.681465525
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.1179043596
Short name T425
Test name
Test status
Simulation time 47230394 ps
CPU time 0.93 seconds
Started Dec 20 12:25:36 PM PST 23
Finished Dec 20 12:26:06 PM PST 23
Peak memory 205980 kb
Host smart-99d04422-57b9-44df-ae53-bb7a64be7436
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179043596 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.1179043596
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.1680337138
Short name T189
Test name
Test status
Simulation time 80347868 ps
CPU time 1.08 seconds
Started Dec 20 12:26:28 PM PST 23
Finished Dec 20 12:27:03 PM PST 23
Peak memory 205984 kb
Host smart-1818b937-5f01-4f3e-8b9d-d186c8bb9fe1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680337138 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.1680337138
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.1085119923
Short name T198
Test name
Test status
Simulation time 88710559 ps
CPU time 3.08 seconds
Started Dec 20 12:25:25 PM PST 23
Finished Dec 20 12:25:53 PM PST 23
Peak memory 214520 kb
Host smart-196b0e4a-f0a4-4928-8569-47e28f6e8197
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085119923 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.1085119923
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.26420251
Short name T455
Test name
Test status
Simulation time 289074263 ps
CPU time 2.07 seconds
Started Dec 20 12:25:24 PM PST 23
Finished Dec 20 12:25:51 PM PST 23
Peak memory 206136 kb
Host smart-d9d96b99-27cd-41c9-a92d-d22e2e51e027
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26420251 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.26420251
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.587719970
Short name T178
Test name
Test status
Simulation time 25706779 ps
CPU time 1.5 seconds
Started Dec 20 12:25:02 PM PST 23
Finished Dec 20 12:25:26 PM PST 23
Peak memory 214468 kb
Host smart-721006c9-af62-4911-857c-ace4dc4239f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587719970 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.587719970
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.2497160266
Short name T209
Test name
Test status
Simulation time 38660538 ps
CPU time 0.83 seconds
Started Dec 20 12:29:41 PM PST 23
Finished Dec 20 12:30:01 PM PST 23
Peak memory 205880 kb
Host smart-64f58ec6-8bc3-44a8-8927-0e30df9e4e7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497160266 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.2497160266
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.273919156
Short name T371
Test name
Test status
Simulation time 92971025 ps
CPU time 0.86 seconds
Started Dec 20 12:24:39 PM PST 23
Finished Dec 20 12:25:13 PM PST 23
Peak memory 206108 kb
Host smart-d8b5dcf1-5eb0-462f-8e8f-f9c37fda73fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273919156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.273919156
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1911465876
Short name T381
Test name
Test status
Simulation time 35818073 ps
CPU time 1.01 seconds
Started Dec 20 12:24:37 PM PST 23
Finished Dec 20 12:25:11 PM PST 23
Peak memory 206048 kb
Host smart-73307692-4382-4708-9021-e0c498725784
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911465876 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.1911465876
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.2791979987
Short name T357
Test name
Test status
Simulation time 72295869 ps
CPU time 1.82 seconds
Started Dec 20 12:25:22 PM PST 23
Finished Dec 20 12:25:48 PM PST 23
Peak memory 214456 kb
Host smart-6fe36967-de56-4531-9f12-5314a41f59a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791979987 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.2791979987
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.742444062
Short name T438
Test name
Test status
Simulation time 45860108 ps
CPU time 1.54 seconds
Started Dec 20 12:26:42 PM PST 23
Finished Dec 20 12:27:15 PM PST 23
Peak memory 206144 kb
Host smart-f8dee582-0b30-424c-8d16-285a2b46efbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742444062 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.742444062
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3306260343
Short name T410
Test name
Test status
Simulation time 21923977 ps
CPU time 1.2 seconds
Started Dec 20 12:26:13 PM PST 23
Finished Dec 20 12:26:44 PM PST 23
Peak memory 214376 kb
Host smart-d50ca76d-5e52-4386-a71c-764dc26b871b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306260343 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.3306260343
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.1765247571
Short name T411
Test name
Test status
Simulation time 26155417 ps
CPU time 0.9 seconds
Started Dec 20 12:28:43 PM PST 23
Finished Dec 20 12:29:16 PM PST 23
Peak memory 205036 kb
Host smart-dd7d8ad0-aa91-4cfb-8b99-11246a2f65f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765247571 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1765247571
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.826478283
Short name T355
Test name
Test status
Simulation time 28861800 ps
CPU time 0.83 seconds
Started Dec 20 12:25:44 PM PST 23
Finished Dec 20 12:26:12 PM PST 23
Peak memory 206164 kb
Host smart-843955b0-48a0-492f-8038-a3d467e81ddd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826478283 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.826478283
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3323076826
Short name T182
Test name
Test status
Simulation time 30717591 ps
CPU time 1.32 seconds
Started Dec 20 12:24:33 PM PST 23
Finished Dec 20 12:25:06 PM PST 23
Peak memory 205968 kb
Host smart-6a8e2ca5-60c5-4f93-9514-f7159eecdf5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323076826 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.3323076826
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.831766141
Short name T429
Test name
Test status
Simulation time 787239670 ps
CPU time 3.77 seconds
Started Dec 20 12:29:31 PM PST 23
Finished Dec 20 12:29:56 PM PST 23
Peak memory 214220 kb
Host smart-81df6a12-1d73-44d1-8463-5a3de4524c90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831766141 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.831766141
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3398208124
Short name T445
Test name
Test status
Simulation time 113067991 ps
CPU time 0.93 seconds
Started Dec 20 12:25:21 PM PST 23
Finished Dec 20 12:25:46 PM PST 23
Peak memory 206068 kb
Host smart-0a5bfa37-5e10-4462-825f-b9e3aabebb8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398208124 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3398208124
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.861547153
Short name T405
Test name
Test status
Simulation time 65100596 ps
CPU time 0.91 seconds
Started Dec 20 12:25:31 PM PST 23
Finished Dec 20 12:26:00 PM PST 23
Peak memory 206044 kb
Host smart-6037cc09-8927-4598-83dc-1d3abe3e6f93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861547153 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.861547153
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3623096130
Short name T404
Test name
Test status
Simulation time 44726139 ps
CPU time 1.14 seconds
Started Dec 20 12:25:04 PM PST 23
Finished Dec 20 12:25:26 PM PST 23
Peak memory 206156 kb
Host smart-182473df-d4c1-4524-9f21-12d8d44a1346
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623096130 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.3623096130
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.3481682805
Short name T446
Test name
Test status
Simulation time 97209433 ps
CPU time 3.14 seconds
Started Dec 20 12:26:13 PM PST 23
Finished Dec 20 12:26:46 PM PST 23
Peak memory 214404 kb
Host smart-13d04faa-19d9-48cb-807e-377092165744
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481682805 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.3481682805
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1425259732
Short name T191
Test name
Test status
Simulation time 13879129 ps
CPU time 0.92 seconds
Started Dec 20 12:25:01 PM PST 23
Finished Dec 20 12:25:25 PM PST 23
Peak memory 206080 kb
Host smart-b335e94c-c01b-4ceb-8c07-d13a92b7c5d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425259732 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.1425259732
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.48287382
Short name T422
Test name
Test status
Simulation time 38513401 ps
CPU time 0.84 seconds
Started Dec 20 12:25:36 PM PST 23
Finished Dec 20 12:26:06 PM PST 23
Peak memory 206100 kb
Host smart-49743d15-ef51-4799-8d84-519f40ced0c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48287382 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.48287382
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.799564861
Short name T375
Test name
Test status
Simulation time 13861621 ps
CPU time 0.85 seconds
Started Dec 20 12:25:35 PM PST 23
Finished Dec 20 12:26:05 PM PST 23
Peak memory 206036 kb
Host smart-45975c09-e55d-415d-a591-d0bdda8a2e05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799564861 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.799564861
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1176329960
Short name T196
Test name
Test status
Simulation time 126875875 ps
CPU time 1.3 seconds
Started Dec 20 12:26:13 PM PST 23
Finished Dec 20 12:26:43 PM PST 23
Peak memory 206124 kb
Host smart-67e24c8e-a094-4eb9-b7bc-ec87e0824bd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176329960 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.1176329960
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.3189211821
Short name T392
Test name
Test status
Simulation time 102317176 ps
CPU time 2.05 seconds
Started Dec 20 12:25:00 PM PST 23
Finished Dec 20 12:25:26 PM PST 23
Peak memory 214500 kb
Host smart-90b895bf-b033-41ea-8630-de8bc899f319
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189211821 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3189211821
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.562278062
Short name T437
Test name
Test status
Simulation time 952470914 ps
CPU time 2.19 seconds
Started Dec 20 12:25:57 PM PST 23
Finished Dec 20 12:26:22 PM PST 23
Peak memory 206168 kb
Host smart-1e1d849f-71bf-46a6-882a-f32c83b9e977
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562278062 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.562278062
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3010831639
Short name T21
Test name
Test status
Simulation time 17148908 ps
CPU time 1.06 seconds
Started Dec 20 12:26:45 PM PST 23
Finished Dec 20 12:27:17 PM PST 23
Peak memory 214428 kb
Host smart-ac154872-e232-44b3-a748-61b8d25468d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010831639 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3010831639
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.647555023
Short name T207
Test name
Test status
Simulation time 36071525 ps
CPU time 0.84 seconds
Started Dec 20 12:25:19 PM PST 23
Finished Dec 20 12:25:42 PM PST 23
Peak memory 206104 kb
Host smart-a026495c-07bd-4fde-8071-e638f677b0a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647555023 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.647555023
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.2911102946
Short name T394
Test name
Test status
Simulation time 36972577 ps
CPU time 0.79 seconds
Started Dec 20 12:25:21 PM PST 23
Finished Dec 20 12:25:45 PM PST 23
Peak memory 206040 kb
Host smart-eaff4b59-46bf-42f0-8118-589c93b0cbfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911102946 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2911102946
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1540130589
Short name T377
Test name
Test status
Simulation time 13651793 ps
CPU time 0.88 seconds
Started Dec 20 12:26:47 PM PST 23
Finished Dec 20 12:27:18 PM PST 23
Peak memory 205964 kb
Host smart-39e2cf30-a7f4-486e-863b-10327dc06139
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540130589 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.1540130589
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.2189887398
Short name T26
Test name
Test status
Simulation time 394013173 ps
CPU time 3.87 seconds
Started Dec 20 12:25:16 PM PST 23
Finished Dec 20 12:25:40 PM PST 23
Peak memory 214484 kb
Host smart-a4bd7df0-6860-4b48-8af4-9804086e4a01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189887398 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.2189887398
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1252392799
Short name T247
Test name
Test status
Simulation time 155556845 ps
CPU time 1.4 seconds
Started Dec 20 12:25:50 PM PST 23
Finished Dec 20 12:26:17 PM PST 23
Peak memory 206120 kb
Host smart-11b6969d-578a-4f21-9ba4-8ee271ef4cb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252392799 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1252392799
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1492192810
Short name T382
Test name
Test status
Simulation time 41294589 ps
CPU time 1.12 seconds
Started Dec 20 12:25:14 PM PST 23
Finished Dec 20 12:25:34 PM PST 23
Peak memory 206148 kb
Host smart-cda94f37-f45b-4f49-94cf-a921dc644712
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492192810 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.1492192810
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1681523750
Short name T369
Test name
Test status
Simulation time 22997051 ps
CPU time 0.87 seconds
Started Dec 20 12:24:31 PM PST 23
Finished Dec 20 12:25:03 PM PST 23
Peak memory 206120 kb
Host smart-58c1bbaa-012e-4222-90f8-7eb2b3e91955
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681523750 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1681523750
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.619465807
Short name T433
Test name
Test status
Simulation time 78531705 ps
CPU time 1.18 seconds
Started Dec 20 12:25:21 PM PST 23
Finished Dec 20 12:25:46 PM PST 23
Peak memory 214236 kb
Host smart-26fc5b73-b5a0-4be2-9230-a0100c9e50ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619465807 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.619465807
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.2471592228
Short name T399
Test name
Test status
Simulation time 47821828 ps
CPU time 0.83 seconds
Started Dec 20 12:24:35 PM PST 23
Finished Dec 20 12:25:09 PM PST 23
Peak memory 206068 kb
Host smart-6311bbcb-c0a1-4f91-acb5-f6e9a14cb36a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471592228 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.2471592228
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.420732771
Short name T285
Test name
Test status
Simulation time 30499860 ps
CPU time 0.75 seconds
Started Dec 20 12:25:03 PM PST 23
Finished Dec 20 12:25:25 PM PST 23
Peak memory 205884 kb
Host smart-9c9f5c9d-9db4-46c2-a80e-48c679e9cf6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420732771 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.420732771
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3617142742
Short name T38
Test name
Test status
Simulation time 106377746 ps
CPU time 0.98 seconds
Started Dec 20 12:25:14 PM PST 23
Finished Dec 20 12:25:34 PM PST 23
Peak memory 206168 kb
Host smart-e32fe667-4504-440b-8373-7dfa9e4f755d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617142742 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.3617142742
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.3037188004
Short name T449
Test name
Test status
Simulation time 130981607 ps
CPU time 3.6 seconds
Started Dec 20 12:25:10 PM PST 23
Finished Dec 20 12:25:32 PM PST 23
Peak memory 214380 kb
Host smart-2b7e2c97-5e8b-41da-900c-6dd1a2695a26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037188004 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.3037188004
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1384574300
Short name T418
Test name
Test status
Simulation time 80462889 ps
CPU time 2.01 seconds
Started Dec 20 12:25:20 PM PST 23
Finished Dec 20 12:25:44 PM PST 23
Peak memory 206248 kb
Host smart-bc6db790-73a6-4c1c-b228-0cc2906dd4a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384574300 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.1384574300
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.3258475167
Short name T232
Test name
Test status
Simulation time 14869366 ps
CPU time 0.85 seconds
Started Dec 20 12:25:26 PM PST 23
Finished Dec 20 12:25:53 PM PST 23
Peak memory 205980 kb
Host smart-0559be90-8efe-4940-962e-9f1db2ac3ad8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258475167 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.3258475167
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.1938207682
Short name T432
Test name
Test status
Simulation time 45765034 ps
CPU time 0.8 seconds
Started Dec 20 12:25:29 PM PST 23
Finished Dec 20 12:25:56 PM PST 23
Peak memory 206088 kb
Host smart-6b737aaa-e3a6-4beb-816a-25250fbd825b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938207682 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.1938207682
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.2517709519
Short name T417
Test name
Test status
Simulation time 31985982 ps
CPU time 0.8 seconds
Started Dec 20 12:26:52 PM PST 23
Finished Dec 20 12:27:22 PM PST 23
Peak memory 205892 kb
Host smart-d83bf298-cd9e-461c-9e88-464a6cc50d3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517709519 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.2517709519
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.1213221349
Short name T423
Test name
Test status
Simulation time 17751413 ps
CPU time 0.76 seconds
Started Dec 20 12:25:30 PM PST 23
Finished Dec 20 12:26:05 PM PST 23
Peak memory 205912 kb
Host smart-12cd54c3-20d7-44ac-a21d-23c5abae77bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213221349 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.1213221349
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.3738334772
Short name T358
Test name
Test status
Simulation time 96057400 ps
CPU time 0.87 seconds
Started Dec 20 12:25:04 PM PST 23
Finished Dec 20 12:25:26 PM PST 23
Peak memory 206176 kb
Host smart-5ef341ce-e780-4cc1-974d-4c566f0bc34f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738334772 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.3738334772
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.3877414141
Short name T284
Test name
Test status
Simulation time 60910177 ps
CPU time 0.8 seconds
Started Dec 20 12:26:05 PM PST 23
Finished Dec 20 12:26:30 PM PST 23
Peak memory 205892 kb
Host smart-2b1852b9-b821-41b2-97fd-e5541dc3fb7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877414141 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3877414141
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.1554756290
Short name T435
Test name
Test status
Simulation time 22971459 ps
CPU time 0.9 seconds
Started Dec 20 12:26:08 PM PST 23
Finished Dec 20 12:26:35 PM PST 23
Peak memory 206012 kb
Host smart-5ac7f46b-4ceb-425a-a893-9498c92eb11d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554756290 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.1554756290
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.1708813048
Short name T451
Test name
Test status
Simulation time 11240442 ps
CPU time 0.81 seconds
Started Dec 20 12:26:08 PM PST 23
Finished Dec 20 12:26:35 PM PST 23
Peak memory 206080 kb
Host smart-edca233a-aeed-453f-b5b1-23917d184ace
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708813048 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1708813048
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.3328979467
Short name T431
Test name
Test status
Simulation time 22560663 ps
CPU time 0.82 seconds
Started Dec 20 12:26:11 PM PST 23
Finished Dec 20 12:26:38 PM PST 23
Peak memory 206092 kb
Host smart-93fe520d-c48e-429c-a07c-a95483dd4b80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328979467 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.3328979467
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.2405972791
Short name T354
Test name
Test status
Simulation time 14084869 ps
CPU time 0.89 seconds
Started Dec 20 12:25:12 PM PST 23
Finished Dec 20 12:25:31 PM PST 23
Peak memory 206040 kb
Host smart-e4210585-ec24-4761-9893-e6815f9b018a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405972791 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.2405972791
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3628336501
Short name T192
Test name
Test status
Simulation time 22921196 ps
CPU time 1.11 seconds
Started Dec 20 12:24:28 PM PST 23
Finished Dec 20 12:25:02 PM PST 23
Peak memory 206176 kb
Host smart-1ad1f141-22c8-4620-812c-5fa74c468394
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628336501 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.3628336501
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3016819330
Short name T348
Test name
Test status
Simulation time 377458136 ps
CPU time 3.28 seconds
Started Dec 20 12:24:34 PM PST 23
Finished Dec 20 12:25:10 PM PST 23
Peak memory 206232 kb
Host smart-53b4aacb-4674-4819-a1c6-bfa403fe98b3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016819330 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.3016819330
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.965765925
Short name T443
Test name
Test status
Simulation time 63520667 ps
CPU time 0.97 seconds
Started Dec 20 12:24:29 PM PST 23
Finished Dec 20 12:25:02 PM PST 23
Peak memory 206060 kb
Host smart-6929b2de-7694-4a93-9449-dd6549df788f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965765925 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.965765925
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2980024788
Short name T384
Test name
Test status
Simulation time 31459252 ps
CPU time 1.07 seconds
Started Dec 20 12:24:42 PM PST 23
Finished Dec 20 12:25:16 PM PST 23
Peak memory 214292 kb
Host smart-a7e3d6f3-19cd-4c40-9928-fe353bbc0372
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980024788 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2980024788
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.1032959862
Short name T208
Test name
Test status
Simulation time 15522976 ps
CPU time 0.89 seconds
Started Dec 20 12:24:35 PM PST 23
Finished Dec 20 12:25:09 PM PST 23
Peak memory 206088 kb
Host smart-c22f0655-0e7a-42ac-b08c-a4a1a53defa7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032959862 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.1032959862
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.4025876133
Short name T187
Test name
Test status
Simulation time 22534389 ps
CPU time 1.06 seconds
Started Dec 20 12:24:56 PM PST 23
Finished Dec 20 12:25:23 PM PST 23
Peak memory 205956 kb
Host smart-63e9768c-96c9-4c96-b3c3-3b2a6add3f75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025876133 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.4025876133
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.485649706
Short name T379
Test name
Test status
Simulation time 58665047 ps
CPU time 2.09 seconds
Started Dec 20 12:25:19 PM PST 23
Finished Dec 20 12:25:43 PM PST 23
Peak memory 216880 kb
Host smart-51198983-30e8-4152-9182-d316b5ebb1ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485649706 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.485649706
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3016832354
Short name T183
Test name
Test status
Simulation time 130970945 ps
CPU time 1.32 seconds
Started Dec 20 12:24:25 PM PST 23
Finished Dec 20 12:24:59 PM PST 23
Peak memory 206256 kb
Host smart-babee63c-01af-44a2-a6fc-0c0ece1baf05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016832354 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.3016832354
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.1894686419
Short name T282
Test name
Test status
Simulation time 15907470 ps
CPU time 0.92 seconds
Started Dec 20 12:26:51 PM PST 23
Finished Dec 20 12:27:21 PM PST 23
Peak memory 206056 kb
Host smart-cecde8da-8088-424e-9f71-5811a7e2f0cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894686419 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.1894686419
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.1835513976
Short name T385
Test name
Test status
Simulation time 22189920 ps
CPU time 0.78 seconds
Started Dec 20 12:25:10 PM PST 23
Finished Dec 20 12:25:30 PM PST 23
Peak memory 206072 kb
Host smart-57f8323c-02e5-43ac-9b88-ff70aec32cf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835513976 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.1835513976
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.2452311416
Short name T42
Test name
Test status
Simulation time 14559339 ps
CPU time 0.85 seconds
Started Dec 20 12:25:21 PM PST 23
Finished Dec 20 12:25:46 PM PST 23
Peak memory 206092 kb
Host smart-cbb29164-2689-4fd5-9806-68f4bde97eec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452311416 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2452311416
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.3224800682
Short name T456
Test name
Test status
Simulation time 24099969 ps
CPU time 0.83 seconds
Started Dec 20 12:26:57 PM PST 23
Finished Dec 20 12:27:27 PM PST 23
Peak memory 206040 kb
Host smart-8ff1de8a-c4cb-49fd-9de0-8120f3fc1270
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224800682 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3224800682
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.3127307367
Short name T427
Test name
Test status
Simulation time 34704270 ps
CPU time 0.8 seconds
Started Dec 20 12:25:16 PM PST 23
Finished Dec 20 12:25:36 PM PST 23
Peak memory 205960 kb
Host smart-66c78b77-fd25-45e5-8b49-d03674190733
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127307367 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.3127307367
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.1612868184
Short name T424
Test name
Test status
Simulation time 12900382 ps
CPU time 0.82 seconds
Started Dec 20 12:26:56 PM PST 23
Finished Dec 20 12:27:26 PM PST 23
Peak memory 206040 kb
Host smart-59c33dc5-8713-46f6-be4a-dfc2c6fb89e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612868184 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1612868184
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.4385760
Short name T419
Test name
Test status
Simulation time 13753753 ps
CPU time 0.85 seconds
Started Dec 20 12:26:53 PM PST 23
Finished Dec 20 12:27:24 PM PST 23
Peak memory 206016 kb
Host smart-1687e426-a607-48e0-815f-35617ff0e779
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4385760 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.4385760
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.2180919016
Short name T194
Test name
Test status
Simulation time 12791475 ps
CPU time 0.81 seconds
Started Dec 20 12:26:52 PM PST 23
Finished Dec 20 12:27:22 PM PST 23
Peak memory 206040 kb
Host smart-4f6d761f-5788-443c-9013-e4395896538d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180919016 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.2180919016
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.3283095806
Short name T378
Test name
Test status
Simulation time 11221462 ps
CPU time 0.84 seconds
Started Dec 20 12:26:01 PM PST 23
Finished Dec 20 12:26:25 PM PST 23
Peak memory 206104 kb
Host smart-0f4a71aa-8576-4c4b-bda6-a19b2b8cf973
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283095806 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.3283095806
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.1090553800
Short name T413
Test name
Test status
Simulation time 18374085 ps
CPU time 0.95 seconds
Started Dec 20 12:25:18 PM PST 23
Finished Dec 20 12:25:39 PM PST 23
Peak memory 206240 kb
Host smart-bc04f8d0-3faa-4381-b616-c252fd4d6295
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090553800 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.1090553800
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.739112515
Short name T204
Test name
Test status
Simulation time 23665510 ps
CPU time 1.07 seconds
Started Dec 20 12:29:15 PM PST 23
Finished Dec 20 12:29:41 PM PST 23
Peak memory 205596 kb
Host smart-a07b6e74-5672-4097-b1bb-afb7423c4cd3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739112515 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.739112515
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.877405711
Short name T447
Test name
Test status
Simulation time 177049548 ps
CPU time 4.98 seconds
Started Dec 20 12:24:44 PM PST 23
Finished Dec 20 12:25:21 PM PST 23
Peak memory 206068 kb
Host smart-558659a6-0ea8-452d-9429-8a05e589e5dc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877405711 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.877405711
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.567115607
Short name T39
Test name
Test status
Simulation time 38407542 ps
CPU time 0.83 seconds
Started Dec 20 12:25:49 PM PST 23
Finished Dec 20 12:26:16 PM PST 23
Peak memory 206096 kb
Host smart-f2892998-b6c7-410d-b852-4df50965a7ab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567115607 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.567115607
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2031064384
Short name T370
Test name
Test status
Simulation time 24968227 ps
CPU time 1.19 seconds
Started Dec 20 12:25:38 PM PST 23
Finished Dec 20 12:26:08 PM PST 23
Peak memory 214332 kb
Host smart-7a0c0866-dc80-45b7-8d81-45fcc9135db8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031064384 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.2031064384
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.1979215355
Short name T374
Test name
Test status
Simulation time 25181562 ps
CPU time 0.79 seconds
Started Dec 20 12:25:24 PM PST 23
Finished Dec 20 12:25:50 PM PST 23
Peak memory 206032 kb
Host smart-c78ba8d8-7acb-4995-9bcb-28bbe881d1dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979215355 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.1979215355
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.3578999778
Short name T365
Test name
Test status
Simulation time 24284855 ps
CPU time 0.84 seconds
Started Dec 20 12:26:00 PM PST 23
Finished Dec 20 12:26:30 PM PST 23
Peak memory 206088 kb
Host smart-907f2eb7-3dd3-4edc-a21a-e5637e6d9e08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578999778 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.3578999778
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.822393848
Short name T213
Test name
Test status
Simulation time 19519326 ps
CPU time 0.93 seconds
Started Dec 20 12:26:03 PM PST 23
Finished Dec 20 12:26:26 PM PST 23
Peak memory 206100 kb
Host smart-da1fb2cc-1f5a-47e3-a09b-b16a6147152d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822393848 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_out
standing.822393848
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.1651004443
Short name T402
Test name
Test status
Simulation time 22275876 ps
CPU time 1.38 seconds
Started Dec 20 12:25:22 PM PST 23
Finished Dec 20 12:25:47 PM PST 23
Peak memory 214292 kb
Host smart-15c236f7-434a-4631-b6ac-84b46a9239cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651004443 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.1651004443
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.615753056
Short name T246
Test name
Test status
Simulation time 292768981 ps
CPU time 1.68 seconds
Started Dec 20 12:24:29 PM PST 23
Finished Dec 20 12:25:03 PM PST 23
Peak memory 206072 kb
Host smart-a5f1f4d9-d3a6-4e9a-aeb5-36d058630da8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615753056 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.615753056
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.2358270321
Short name T366
Test name
Test status
Simulation time 12808007 ps
CPU time 0.85 seconds
Started Dec 20 12:25:22 PM PST 23
Finished Dec 20 12:25:47 PM PST 23
Peak memory 205952 kb
Host smart-3e84fd6f-c661-4aed-82e5-19713c8ccb99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358270321 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.2358270321
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.312466182
Short name T351
Test name
Test status
Simulation time 14066873 ps
CPU time 0.83 seconds
Started Dec 20 12:26:36 PM PST 23
Finished Dec 20 12:27:10 PM PST 23
Peak memory 206144 kb
Host smart-de50fdbf-0e84-4513-9bf6-825548ac0292
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312466182 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.312466182
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.2524887520
Short name T41
Test name
Test status
Simulation time 48257292 ps
CPU time 0.83 seconds
Started Dec 20 12:25:17 PM PST 23
Finished Dec 20 12:25:37 PM PST 23
Peak memory 206076 kb
Host smart-b2dd122b-9cad-4372-a592-741376a18ba8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524887520 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.2524887520
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.3667317582
Short name T408
Test name
Test status
Simulation time 17636528 ps
CPU time 0.9 seconds
Started Dec 20 12:25:21 PM PST 23
Finished Dec 20 12:25:45 PM PST 23
Peak memory 206044 kb
Host smart-e57dd7fb-0a1e-435d-b66f-7854e9552d07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667317582 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.3667317582
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.4090506659
Short name T401
Test name
Test status
Simulation time 42034523 ps
CPU time 0.8 seconds
Started Dec 20 12:25:19 PM PST 23
Finished Dec 20 12:25:42 PM PST 23
Peak memory 205892 kb
Host smart-9b311d08-c49d-4f5f-8c3f-771be422a6c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090506659 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.4090506659
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.805505365
Short name T386
Test name
Test status
Simulation time 45286091 ps
CPU time 0.81 seconds
Started Dec 20 12:27:04 PM PST 23
Finished Dec 20 12:27:34 PM PST 23
Peak memory 205912 kb
Host smart-9c89370d-46ec-4bfe-b008-300aebe4eaac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805505365 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.805505365
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.3736031863
Short name T281
Test name
Test status
Simulation time 21302739 ps
CPU time 0.76 seconds
Started Dec 20 12:25:20 PM PST 23
Finished Dec 20 12:25:43 PM PST 23
Peak memory 205884 kb
Host smart-f4c105dc-075d-4843-8e3f-a3047bce0b39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736031863 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.3736031863
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.31758549
Short name T407
Test name
Test status
Simulation time 64187364 ps
CPU time 0.87 seconds
Started Dec 20 12:25:16 PM PST 23
Finished Dec 20 12:25:36 PM PST 23
Peak memory 206088 kb
Host smart-8f83f14b-aa24-4c0e-8ddf-d16290541db8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31758549 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.31758549
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.3026483076
Short name T406
Test name
Test status
Simulation time 48514976 ps
CPU time 0.83 seconds
Started Dec 20 12:25:09 PM PST 23
Finished Dec 20 12:25:29 PM PST 23
Peak memory 206144 kb
Host smart-0b03428f-e910-4500-b100-3b8ebb0c82b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026483076 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.3026483076
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.967180798
Short name T389
Test name
Test status
Simulation time 12698880 ps
CPU time 0.86 seconds
Started Dec 20 12:25:20 PM PST 23
Finished Dec 20 12:25:43 PM PST 23
Peak memory 205980 kb
Host smart-c663a10b-d266-49f5-9195-1b1269cf0b88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967180798 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.967180798
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3097083654
Short name T367
Test name
Test status
Simulation time 73642312 ps
CPU time 1.3 seconds
Started Dec 20 12:25:47 PM PST 23
Finished Dec 20 12:26:15 PM PST 23
Peak memory 214328 kb
Host smart-81995563-fb27-4e4e-a839-657e1ef1ac91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097083654 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.3097083654
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.167540194
Short name T195
Test name
Test status
Simulation time 15130459 ps
CPU time 0.83 seconds
Started Dec 20 12:26:02 PM PST 23
Finished Dec 20 12:26:25 PM PST 23
Peak memory 206040 kb
Host smart-18d07362-555f-4a91-9d71-f24e6e12fa53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167540194 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.167540194
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.3387489705
Short name T356
Test name
Test status
Simulation time 21660584 ps
CPU time 0.77 seconds
Started Dec 20 12:24:31 PM PST 23
Finished Dec 20 12:25:03 PM PST 23
Peak memory 205924 kb
Host smart-9003fe6e-8fa9-4889-9ac3-da3ad6af7ec5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387489705 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.3387489705
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1989189867
Short name T397
Test name
Test status
Simulation time 29212036 ps
CPU time 1.04 seconds
Started Dec 20 12:25:34 PM PST 23
Finished Dec 20 12:26:04 PM PST 23
Peak memory 206124 kb
Host smart-81595349-ab8c-4393-8a0d-7acbd626c3f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989189867 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.1989189867
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.871655085
Short name T364
Test name
Test status
Simulation time 32267517 ps
CPU time 2.16 seconds
Started Dec 20 12:26:53 PM PST 23
Finished Dec 20 12:27:24 PM PST 23
Peak memory 214372 kb
Host smart-f816dd81-c2a2-4a45-8d2f-a7340d817ec6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871655085 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.871655085
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3843634214
Short name T428
Test name
Test status
Simulation time 59652429 ps
CPU time 1.69 seconds
Started Dec 20 12:24:55 PM PST 23
Finished Dec 20 12:25:24 PM PST 23
Peak memory 206124 kb
Host smart-2aba31b5-45a7-4b2a-9e3b-dbf14d138c84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843634214 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.3843634214
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3393172088
Short name T412
Test name
Test status
Simulation time 63469895 ps
CPU time 1.05 seconds
Started Dec 20 12:24:36 PM PST 23
Finished Dec 20 12:25:11 PM PST 23
Peak memory 214340 kb
Host smart-c127f5c1-d46f-4c57-9684-4cd778851667
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393172088 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.3393172088
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.1345385571
Short name T186
Test name
Test status
Simulation time 37838735 ps
CPU time 0.8 seconds
Started Dec 20 12:25:14 PM PST 23
Finished Dec 20 12:25:34 PM PST 23
Peak memory 205820 kb
Host smart-d8340539-19de-498c-9ba0-4a745a25ee76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345385571 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.1345385571
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.114428420
Short name T415
Test name
Test status
Simulation time 40311583 ps
CPU time 0.77 seconds
Started Dec 20 12:28:59 PM PST 23
Finished Dec 20 12:29:33 PM PST 23
Peak memory 205364 kb
Host smart-3c925fd4-3488-4f6d-a4f6-309580ad23b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114428420 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.114428420
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2767886513
Short name T448
Test name
Test status
Simulation time 70334395 ps
CPU time 1.29 seconds
Started Dec 20 12:27:31 PM PST 23
Finished Dec 20 12:28:10 PM PST 23
Peak memory 206084 kb
Host smart-9170fcd4-ecfb-4cf5-9bd0-95e7ac7ae80e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767886513 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.2767886513
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.2257079950
Short name T359
Test name
Test status
Simulation time 251070022 ps
CPU time 2.3 seconds
Started Dec 20 12:25:22 PM PST 23
Finished Dec 20 12:25:49 PM PST 23
Peak memory 214492 kb
Host smart-39427711-1753-4a4e-84a1-a345a078ec3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257079950 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.2257079950
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3252256615
Short name T243
Test name
Test status
Simulation time 114126474 ps
CPU time 2.54 seconds
Started Dec 20 12:24:30 PM PST 23
Finished Dec 20 12:25:04 PM PST 23
Peak memory 205936 kb
Host smart-fff143be-7e8d-4342-99e7-553eb6de31bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252256615 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.3252256615
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2770812680
Short name T380
Test name
Test status
Simulation time 39202054 ps
CPU time 1.01 seconds
Started Dec 20 12:26:03 PM PST 23
Finished Dec 20 12:26:26 PM PST 23
Peak memory 214344 kb
Host smart-1e5f58b6-3b3a-4c23-82f6-e67e956c419f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770812680 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2770812680
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.2447040412
Short name T205
Test name
Test status
Simulation time 49309183 ps
CPU time 0.77 seconds
Started Dec 20 12:26:11 PM PST 23
Finished Dec 20 12:26:38 PM PST 23
Peak memory 205888 kb
Host smart-21ffd17c-84e3-4b89-9d08-2fe424d81718
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447040412 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.2447040412
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.427894788
Short name T454
Test name
Test status
Simulation time 13534382 ps
CPU time 0.82 seconds
Started Dec 20 12:29:09 PM PST 23
Finished Dec 20 12:29:39 PM PST 23
Peak memory 205572 kb
Host smart-54e1f4f7-ac0a-4905-a633-6b12cf857397
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427894788 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.427894788
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.127794114
Short name T190
Test name
Test status
Simulation time 30878808 ps
CPU time 1.04 seconds
Started Dec 20 12:26:25 PM PST 23
Finished Dec 20 12:27:00 PM PST 23
Peak memory 206032 kb
Host smart-dceae1d0-3b27-4923-8ff2-52b40f233fce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127794114 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_out
standing.127794114
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.2597551048
Short name T439
Test name
Test status
Simulation time 138346777 ps
CPU time 4.43 seconds
Started Dec 20 12:24:37 PM PST 23
Finished Dec 20 12:25:16 PM PST 23
Peak memory 214408 kb
Host smart-2bf49b0f-abcb-498d-8ffc-19d366d38e81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597551048 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2597551048
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1907611960
Short name T245
Test name
Test status
Simulation time 553231529 ps
CPU time 2.11 seconds
Started Dec 20 12:24:33 PM PST 23
Finished Dec 20 12:25:08 PM PST 23
Peak memory 206120 kb
Host smart-c14b1590-460b-4158-957d-990b7adae18f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907611960 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.1907611960
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.697384545
Short name T363
Test name
Test status
Simulation time 22671642 ps
CPU time 0.98 seconds
Started Dec 20 12:25:57 PM PST 23
Finished Dec 20 12:26:21 PM PST 23
Peak memory 206088 kb
Host smart-7e905b01-bfec-475e-b727-d5067cc484b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697384545 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.697384545
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.3736732409
Short name T350
Test name
Test status
Simulation time 34389022 ps
CPU time 0.88 seconds
Started Dec 20 12:25:20 PM PST 23
Finished Dec 20 12:25:44 PM PST 23
Peak memory 206040 kb
Host smart-be9e1456-52e4-44bc-9047-7b1aa354c714
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736732409 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.3736732409
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.3259118269
Short name T436
Test name
Test status
Simulation time 38359390 ps
CPU time 0.84 seconds
Started Dec 20 12:24:47 PM PST 23
Finished Dec 20 12:25:19 PM PST 23
Peak memory 206108 kb
Host smart-ae7309d1-d45f-4a6a-b171-2b1e8f96e696
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259118269 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.3259118269
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2859065571
Short name T362
Test name
Test status
Simulation time 46127653 ps
CPU time 1.11 seconds
Started Dec 20 12:25:24 PM PST 23
Finished Dec 20 12:25:50 PM PST 23
Peak memory 206068 kb
Host smart-9fb81128-924b-440f-810b-ea85538d699f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859065571 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.2859065571
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.1296591440
Short name T426
Test name
Test status
Simulation time 111521150 ps
CPU time 3.79 seconds
Started Dec 20 12:26:07 PM PST 23
Finished Dec 20 12:26:37 PM PST 23
Peak memory 214500 kb
Host smart-841f23ea-a9ca-4bce-97f0-bca2872bf0c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296591440 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.1296591440
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2172702272
Short name T202
Test name
Test status
Simulation time 64130142 ps
CPU time 1.8 seconds
Started Dec 20 12:24:31 PM PST 23
Finished Dec 20 12:25:04 PM PST 23
Peak memory 206024 kb
Host smart-d016eaf3-583f-46ae-9bfe-7cd9e30e4b93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172702272 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.2172702272
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.4102688475
Short name T420
Test name
Test status
Simulation time 28446331 ps
CPU time 0.97 seconds
Started Dec 20 12:24:34 PM PST 23
Finished Dec 20 12:25:07 PM PST 23
Peak memory 206104 kb
Host smart-1610b9a0-7bcb-463c-9a40-45118bc57b38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102688475 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.4102688475
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.1781223541
Short name T444
Test name
Test status
Simulation time 12887900 ps
CPU time 0.91 seconds
Started Dec 20 12:26:12 PM PST 23
Finished Dec 20 12:26:42 PM PST 23
Peak memory 206048 kb
Host smart-7a76a84f-31f8-4851-abc6-16360a746276
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781223541 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.1781223541
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.1368220609
Short name T349
Test name
Test status
Simulation time 32997001 ps
CPU time 0.75 seconds
Started Dec 20 12:26:23 PM PST 23
Finished Dec 20 12:26:57 PM PST 23
Peak memory 205892 kb
Host smart-1b381aef-058e-4b45-b6f9-5f17ed359030
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368220609 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.1368220609
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1497474275
Short name T421
Test name
Test status
Simulation time 29810326 ps
CPU time 1.3 seconds
Started Dec 20 12:26:06 PM PST 23
Finished Dec 20 12:26:31 PM PST 23
Peak memory 206168 kb
Host smart-f125a7d8-da4d-49e2-816b-4e01e902d1c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497474275 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.1497474275
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.399841864
Short name T414
Test name
Test status
Simulation time 57107007 ps
CPU time 2.06 seconds
Started Dec 20 12:24:45 PM PST 23
Finished Dec 20 12:25:19 PM PST 23
Peak memory 214364 kb
Host smart-2bb6731f-3659-4f96-9371-fb15d147bb0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399841864 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.399841864
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2135289659
Short name T244
Test name
Test status
Simulation time 150293168 ps
CPU time 2.16 seconds
Started Dec 20 12:25:04 PM PST 23
Finished Dec 20 12:25:28 PM PST 23
Peak memory 205988 kb
Host smart-39f578c1-57b9-4085-bf0f-33e968063efb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135289659 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.2135289659
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.3081409897
Short name T311
Test name
Test status
Simulation time 155385055 ps
CPU time 0.88 seconds
Started Dec 20 12:51:53 PM PST 23
Finished Dec 20 12:52:08 PM PST 23
Peak memory 205068 kb
Host smart-ff4555af-5334-4be1-8fb7-2c3fbffa8817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081409897 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.3081409897
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.256711920
Short name T715
Test name
Test status
Simulation time 31063189 ps
CPU time 0.97 seconds
Started Dec 20 12:51:54 PM PST 23
Finished Dec 20 12:52:09 PM PST 23
Peak memory 204800 kb
Host smart-d60ea9f8-bac3-49d1-b05a-8ee44136003a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256711920 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.256711920
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.1199818953
Short name T938
Test name
Test status
Simulation time 20460202 ps
CPU time 0.82 seconds
Started Dec 20 12:51:52 PM PST 23
Finished Dec 20 12:52:07 PM PST 23
Peak memory 214408 kb
Host smart-e38467ec-5916-46c1-ac8e-1fb9d6d57933
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199818953 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.1199818953
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.2274971503
Short name T134
Test name
Test status
Simulation time 44051793 ps
CPU time 0.92 seconds
Started Dec 20 12:51:55 PM PST 23
Finished Dec 20 12:52:10 PM PST 23
Peak memory 214612 kb
Host smart-667da905-22d7-4492-a024-bc9deed8cc0d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274971503 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.2274971503
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.477052875
Short name T151
Test name
Test status
Simulation time 40642408 ps
CPU time 0.96 seconds
Started Dec 20 12:51:54 PM PST 23
Finished Dec 20 12:52:09 PM PST 23
Peak memory 214508 kb
Host smart-06870d9f-c513-4e8a-b772-0fa92b28f7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477052875 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.477052875
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.4155632373
Short name T583
Test name
Test status
Simulation time 15936375 ps
CPU time 0.94 seconds
Started Dec 20 12:52:16 PM PST 23
Finished Dec 20 12:52:35 PM PST 23
Peak memory 205420 kb
Host smart-4dc87590-30a0-4140-80e4-2919b7994253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155632373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.4155632373
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_sec_cm.1129724663
Short name T50
Test name
Test status
Simulation time 4198444805 ps
CPU time 6.22 seconds
Started Dec 20 12:51:53 PM PST 23
Finished Dec 20 12:52:14 PM PST 23
Peak memory 234880 kb
Host smart-8b113f9d-19c2-4f93-96eb-6e6d8388e9b6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129724663 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.1129724663
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.2270455023
Short name T559
Test name
Test status
Simulation time 20723593 ps
CPU time 0.82 seconds
Started Dec 20 12:52:14 PM PST 23
Finished Dec 20 12:52:34 PM PST 23
Peak memory 204796 kb
Host smart-a9770dfc-1520-48e3-8a03-406baabb8cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270455023 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.2270455023
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.4151566089
Short name T60
Test name
Test status
Simulation time 139508332 ps
CPU time 2.09 seconds
Started Dec 20 12:51:49 PM PST 23
Finished Dec 20 12:52:05 PM PST 23
Peak memory 206116 kb
Host smart-cf4411cc-1abc-4999-bea4-d04b2fcfffe3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151566089 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.4151566089
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.3739117579
Short name T620
Test name
Test status
Simulation time 40067154168 ps
CPU time 517.95 seconds
Started Dec 20 12:51:51 PM PST 23
Finished Dec 20 01:00:43 PM PST 23
Peak memory 216252 kb
Host smart-f0bcf726-3982-4385-a5a2-6a1dceafb6c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739117579 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.3739117579
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert_test.2738697421
Short name T546
Test name
Test status
Simulation time 15752130 ps
CPU time 0.88 seconds
Started Dec 20 12:52:00 PM PST 23
Finished Dec 20 12:52:17 PM PST 23
Peak memory 204544 kb
Host smart-2e513cf0-05cb-4b70-8d26-a12faadaa223
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738697421 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.2738697421
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.1940193186
Short name T819
Test name
Test status
Simulation time 195155382 ps
CPU time 1.12 seconds
Started Dec 20 12:51:54 PM PST 23
Finished Dec 20 12:52:09 PM PST 23
Peak memory 214656 kb
Host smart-6c514af7-3cc8-48d6-9696-bec09ce13f06
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940193186 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.1940193186
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.1768014828
Short name T927
Test name
Test status
Simulation time 81251298 ps
CPU time 1 seconds
Started Dec 20 12:51:54 PM PST 23
Finished Dec 20 12:52:10 PM PST 23
Peak memory 214884 kb
Host smart-60eb02fc-89fc-4d20-a75b-6b828def9fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768014828 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.1768014828
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.4056736314
Short name T625
Test name
Test status
Simulation time 23745576 ps
CPU time 1.06 seconds
Started Dec 20 12:51:56 PM PST 23
Finished Dec 20 12:52:11 PM PST 23
Peak memory 205480 kb
Host smart-e1a6b725-f704-4e5d-9bc2-d7b20f7a8ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056736314 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.4056736314
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.1934534327
Short name T522
Test name
Test status
Simulation time 24621361 ps
CPU time 0.89 seconds
Started Dec 20 12:51:52 PM PST 23
Finished Dec 20 12:52:08 PM PST 23
Peak memory 214640 kb
Host smart-46a2205c-8a05-433a-abda-59bbd7de1e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934534327 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.1934534327
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_sec_cm.180989433
Short name T51
Test name
Test status
Simulation time 531445686 ps
CPU time 7.6 seconds
Started Dec 20 12:52:08 PM PST 23
Finished Dec 20 12:52:35 PM PST 23
Peak memory 231976 kb
Host smart-79683950-79fe-43d1-81eb-1a7a2c61f2e7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180989433 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.180989433
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.3115861909
Short name T694
Test name
Test status
Simulation time 39876318 ps
CPU time 0.88 seconds
Started Dec 20 12:51:56 PM PST 23
Finished Dec 20 12:52:12 PM PST 23
Peak memory 205072 kb
Host smart-d411544b-8896-425b-96dd-2008c1bbe36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115861909 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.3115861909
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.1359948612
Short name T654
Test name
Test status
Simulation time 17133596 ps
CPU time 0.88 seconds
Started Dec 20 12:51:58 PM PST 23
Finished Dec 20 12:52:14 PM PST 23
Peak memory 204412 kb
Host smart-05c28ae4-1fc7-4430-90d9-957311870a02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359948612 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.1359948612
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.307099956
Short name T683
Test name
Test status
Simulation time 52537642669 ps
CPU time 295.09 seconds
Started Dec 20 12:51:54 PM PST 23
Finished Dec 20 12:57:03 PM PST 23
Peak memory 215332 kb
Host smart-894cd343-802a-499e-811e-27e4f5a24655
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307099956 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.307099956
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.3788118471
Short name T791
Test name
Test status
Simulation time 32944283 ps
CPU time 0.93 seconds
Started Dec 20 12:52:44 PM PST 23
Finished Dec 20 12:52:57 PM PST 23
Peak memory 205408 kb
Host smart-bc70332e-9970-4751-9e62-c110dd0f4175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788118471 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.3788118471
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.3904926381
Short name T774
Test name
Test status
Simulation time 42929644 ps
CPU time 0.83 seconds
Started Dec 20 12:52:51 PM PST 23
Finished Dec 20 12:53:05 PM PST 23
Peak memory 204620 kb
Host smart-241ad76c-1c89-4b7c-8ef7-2e2f9241c335
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904926381 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.3904926381
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_err.547201098
Short name T175
Test name
Test status
Simulation time 32104081 ps
CPU time 0.94 seconds
Started Dec 20 12:52:49 PM PST 23
Finished Dec 20 12:53:02 PM PST 23
Peak memory 221632 kb
Host smart-224da73c-906d-4501-80ea-e6ea970a6521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547201098 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.547201098
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.3884478418
Short name T507
Test name
Test status
Simulation time 54151408 ps
CPU time 0.87 seconds
Started Dec 20 12:52:41 PM PST 23
Finished Dec 20 12:52:53 PM PST 23
Peak memory 204772 kb
Host smart-9f32e75f-2d48-423a-8d90-8f24520de931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884478418 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.3884478418
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.1399972082
Short name T584
Test name
Test status
Simulation time 61116880 ps
CPU time 0.83 seconds
Started Dec 20 12:52:42 PM PST 23
Finished Dec 20 12:52:54 PM PST 23
Peak memory 214284 kb
Host smart-12a63738-3738-4b46-b5dd-dee165b3e57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399972082 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.1399972082
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.4122501768
Short name T707
Test name
Test status
Simulation time 19736233 ps
CPU time 0.83 seconds
Started Dec 20 12:52:42 PM PST 23
Finished Dec 20 12:52:53 PM PST 23
Peak memory 204904 kb
Host smart-1d79526d-f22e-4102-b10a-d77a70f4f21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122501768 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.4122501768
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.2362988338
Short name T218
Test name
Test status
Simulation time 103851357 ps
CPU time 2.87 seconds
Started Dec 20 12:52:49 PM PST 23
Finished Dec 20 12:53:04 PM PST 23
Peak memory 205968 kb
Host smart-66043e46-1e3f-4b4f-ac7b-8abaf0792731
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362988338 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.2362988338
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/100.edn_genbits.3819623640
Short name T929
Test name
Test status
Simulation time 16277025 ps
CPU time 1.04 seconds
Started Dec 20 12:54:59 PM PST 23
Finished Dec 20 12:55:21 PM PST 23
Peak memory 205480 kb
Host smart-a9d1a010-70d2-4621-b317-4dea4da279cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819623640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.3819623640
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.1793676877
Short name T940
Test name
Test status
Simulation time 15760065 ps
CPU time 0.95 seconds
Started Dec 20 12:54:59 PM PST 23
Finished Dec 20 12:55:21 PM PST 23
Peak memory 205060 kb
Host smart-8eabff6a-a78a-4d45-802e-d5112ec7efe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793676877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.1793676877
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.82572051
Short name T720
Test name
Test status
Simulation time 79707253 ps
CPU time 0.91 seconds
Started Dec 20 12:54:59 PM PST 23
Finished Dec 20 12:55:21 PM PST 23
Peak memory 205620 kb
Host smart-d0563eae-e4d2-45ee-9b2a-d84c6ebbeba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82572051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.82572051
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.1236059319
Short name T770
Test name
Test status
Simulation time 285954297 ps
CPU time 3.69 seconds
Started Dec 20 12:54:57 PM PST 23
Finished Dec 20 12:55:19 PM PST 23
Peak memory 214092 kb
Host smart-04ee0cb5-aaaf-42b5-a6c2-47fc94d888be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236059319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.1236059319
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.1899136948
Short name T602
Test name
Test status
Simulation time 54338515 ps
CPU time 0.86 seconds
Started Dec 20 12:54:40 PM PST 23
Finished Dec 20 12:54:52 PM PST 23
Peak memory 205072 kb
Host smart-f81c2168-6230-4b68-b6be-13606763a046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899136948 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.1899136948
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.3939718649
Short name T847
Test name
Test status
Simulation time 62762273 ps
CPU time 1.21 seconds
Started Dec 20 12:55:02 PM PST 23
Finished Dec 20 12:55:24 PM PST 23
Peak memory 205560 kb
Host smart-5c76f870-50eb-41cb-a3ee-65adbdeb83ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939718649 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.3939718649
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.112235499
Short name T576
Test name
Test status
Simulation time 15973680 ps
CPU time 0.91 seconds
Started Dec 20 12:54:39 PM PST 23
Finished Dec 20 12:54:52 PM PST 23
Peak memory 204932 kb
Host smart-190a4337-b3da-4dcc-b9cf-2b8a8eecbae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112235499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.112235499
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.581350967
Short name T967
Test name
Test status
Simulation time 15765326 ps
CPU time 0.88 seconds
Started Dec 20 12:52:49 PM PST 23
Finished Dec 20 12:53:03 PM PST 23
Peak memory 204376 kb
Host smart-7c96f0b8-550f-4605-9fca-a0a0abdba1b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581350967 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.581350967
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.3105927826
Short name T775
Test name
Test status
Simulation time 16544726 ps
CPU time 0.92 seconds
Started Dec 20 12:52:52 PM PST 23
Finished Dec 20 12:53:07 PM PST 23
Peak memory 214596 kb
Host smart-6469aefc-ce0a-4e04-b203-d812de8ae1d3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105927826 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.3105927826
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.1866659960
Short name T784
Test name
Test status
Simulation time 23222754 ps
CPU time 1.15 seconds
Started Dec 20 12:52:51 PM PST 23
Finished Dec 20 12:53:06 PM PST 23
Peak memory 216116 kb
Host smart-df1ae720-0773-494b-98bf-98fe1585f79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866659960 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.1866659960
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.1099522131
Short name T483
Test name
Test status
Simulation time 58472344 ps
CPU time 0.99 seconds
Started Dec 20 12:52:51 PM PST 23
Finished Dec 20 12:53:06 PM PST 23
Peak memory 205580 kb
Host smart-94eef349-e5aa-4c27-a100-9a8ed41d5c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099522131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1099522131
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.4075559026
Short name T92
Test name
Test status
Simulation time 19138232 ps
CPU time 1 seconds
Started Dec 20 12:52:51 PM PST 23
Finished Dec 20 12:53:07 PM PST 23
Peak memory 214572 kb
Host smart-ece3ed17-09e6-479d-9ebd-f2d281c69351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075559026 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.4075559026
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.1653565739
Short name T780
Test name
Test status
Simulation time 21000450 ps
CPU time 0.86 seconds
Started Dec 20 12:52:50 PM PST 23
Finished Dec 20 12:53:03 PM PST 23
Peak memory 204796 kb
Host smart-728c34d5-0b58-4701-955f-5914b39b4af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653565739 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.1653565739
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.1616187670
Short name T854
Test name
Test status
Simulation time 283120612 ps
CPU time 3.13 seconds
Started Dec 20 12:52:51 PM PST 23
Finished Dec 20 12:53:07 PM PST 23
Peak memory 206068 kb
Host smart-5184abf9-5ca1-4372-a959-3548287b1d23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616187670 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1616187670
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.425327286
Short name T866
Test name
Test status
Simulation time 122398914402 ps
CPU time 1402.29 seconds
Started Dec 20 12:52:51 PM PST 23
Finished Dec 20 01:16:27 PM PST 23
Peak memory 216680 kb
Host smart-02f76829-ba5a-4053-9933-bdfaf24bde36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425327286 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.425327286
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/111.edn_genbits.4189108250
Short name T732
Test name
Test status
Simulation time 61870124 ps
CPU time 2.27 seconds
Started Dec 20 12:54:48 PM PST 23
Finished Dec 20 12:55:06 PM PST 23
Peak memory 214252 kb
Host smart-a3f1b983-f3ae-4138-b4c5-3e2d311aae5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189108250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.4189108250
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.2066243205
Short name T782
Test name
Test status
Simulation time 35788272 ps
CPU time 1.65 seconds
Started Dec 20 12:54:40 PM PST 23
Finished Dec 20 12:54:53 PM PST 23
Peak memory 214268 kb
Host smart-b0f9a124-0528-4807-9c84-eca694eecabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066243205 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.2066243205
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.3451811447
Short name T288
Test name
Test status
Simulation time 151798301 ps
CPU time 3 seconds
Started Dec 20 12:54:39 PM PST 23
Finished Dec 20 12:54:54 PM PST 23
Peak memory 214172 kb
Host smart-4756d2e7-62db-494a-89ff-3ebe95155378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451811447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.3451811447
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.2860181835
Short name T1
Test name
Test status
Simulation time 28220036 ps
CPU time 0.96 seconds
Started Dec 20 12:54:40 PM PST 23
Finished Dec 20 12:54:52 PM PST 23
Peak memory 205488 kb
Host smart-d85bbc05-1239-496e-be9d-ecbcc7e87339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860181835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.2860181835
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.1120174040
Short name T330
Test name
Test status
Simulation time 50224225 ps
CPU time 0.91 seconds
Started Dec 20 12:54:39 PM PST 23
Finished Dec 20 12:54:52 PM PST 23
Peak memory 204916 kb
Host smart-e39d02b7-7d8d-4595-9f99-bc3895de4e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120174040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.1120174040
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.3013424607
Short name T59
Test name
Test status
Simulation time 76246749 ps
CPU time 2.74 seconds
Started Dec 20 12:54:45 PM PST 23
Finished Dec 20 12:55:01 PM PST 23
Peak memory 214224 kb
Host smart-884685a5-36dd-4386-b87c-1c5f1a78279f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013424607 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.3013424607
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.973756773
Short name T697
Test name
Test status
Simulation time 63016715 ps
CPU time 0.9 seconds
Started Dec 20 12:53:01 PM PST 23
Finished Dec 20 12:53:14 PM PST 23
Peak memory 206064 kb
Host smart-888f4ef7-63c3-41aa-80c1-6f34afe8d328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973756773 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.973756773
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_disable.1706654375
Short name T161
Test name
Test status
Simulation time 77265300 ps
CPU time 0.82 seconds
Started Dec 20 12:52:59 PM PST 23
Finished Dec 20 12:53:13 PM PST 23
Peak memory 214264 kb
Host smart-5ade8393-0b13-4579-931d-cf9a4ede50ad
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706654375 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.1706654375
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.1041409115
Short name T708
Test name
Test status
Simulation time 48555008 ps
CPU time 0.97 seconds
Started Dec 20 12:53:03 PM PST 23
Finished Dec 20 12:53:17 PM PST 23
Peak memory 206332 kb
Host smart-7e82afc6-d0f7-44c4-94de-65a477c6355f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041409115 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.1041409115
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.3995588689
Short name T922
Test name
Test status
Simulation time 34430415 ps
CPU time 0.83 seconds
Started Dec 20 12:52:54 PM PST 23
Finished Dec 20 12:53:09 PM PST 23
Peak memory 215772 kb
Host smart-4757c99e-6481-44b6-b1a9-2998bbda1704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995588689 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.3995588689
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.1447797909
Short name T838
Test name
Test status
Simulation time 19659977 ps
CPU time 0.99 seconds
Started Dec 20 12:52:48 PM PST 23
Finished Dec 20 12:53:01 PM PST 23
Peak memory 205272 kb
Host smart-ad7e4949-2533-4561-b9a3-1d15da3f2998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447797909 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.1447797909
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.655649585
Short name T941
Test name
Test status
Simulation time 19705739 ps
CPU time 1.05 seconds
Started Dec 20 12:52:50 PM PST 23
Finished Dec 20 12:53:04 PM PST 23
Peak memory 214156 kb
Host smart-af787643-5b6e-4c09-be60-0475849c2d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655649585 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.655649585
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.2203863754
Short name T622
Test name
Test status
Simulation time 32446855 ps
CPU time 0.81 seconds
Started Dec 20 12:52:48 PM PST 23
Finished Dec 20 12:53:01 PM PST 23
Peak memory 204504 kb
Host smart-878376e5-b545-46dc-8401-a9655df99bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203863754 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2203863754
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.844300345
Short name T251
Test name
Test status
Simulation time 302469100 ps
CPU time 1.98 seconds
Started Dec 20 12:52:48 PM PST 23
Finished Dec 20 12:53:02 PM PST 23
Peak memory 205968 kb
Host smart-a8d334d9-d5e8-420d-8add-508ea88e85b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844300345 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.844300345
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.4066624284
Short name T667
Test name
Test status
Simulation time 54816400150 ps
CPU time 1216.2 seconds
Started Dec 20 12:52:52 PM PST 23
Finished Dec 20 01:13:22 PM PST 23
Peak memory 215328 kb
Host smart-1bbeecc0-9ccf-487c-a1e0-be600454497c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066624284 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.4066624284
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.368673226
Short name T860
Test name
Test status
Simulation time 15802500 ps
CPU time 0.94 seconds
Started Dec 20 12:54:41 PM PST 23
Finished Dec 20 12:54:53 PM PST 23
Peak memory 205488 kb
Host smart-a00ceea4-17cf-480a-91ce-9a73c2790a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368673226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.368673226
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.352161547
Short name T803
Test name
Test status
Simulation time 20720211 ps
CPU time 0.97 seconds
Started Dec 20 12:55:00 PM PST 23
Finished Dec 20 12:55:21 PM PST 23
Peak memory 205620 kb
Host smart-09551ae3-66db-4710-ac5e-038204064feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352161547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.352161547
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.2248747735
Short name T590
Test name
Test status
Simulation time 42574172 ps
CPU time 0.93 seconds
Started Dec 20 12:54:49 PM PST 23
Finished Dec 20 12:55:07 PM PST 23
Peak memory 206044 kb
Host smart-9c567ae0-6773-42f1-8dd3-4b642beeda32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248747735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.2248747735
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.3610528724
Short name T100
Test name
Test status
Simulation time 53098541 ps
CPU time 1.75 seconds
Started Dec 20 12:54:45 PM PST 23
Finished Dec 20 12:55:00 PM PST 23
Peak memory 214052 kb
Host smart-1328ea32-335b-4d3e-9e52-5f5dd5f6d8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610528724 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.3610528724
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.3451509881
Short name T270
Test name
Test status
Simulation time 19744593 ps
CPU time 0.95 seconds
Started Dec 20 12:54:45 PM PST 23
Finished Dec 20 12:55:00 PM PST 23
Peak memory 205084 kb
Host smart-26b3c184-7673-4f7e-bca6-4927f5053193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451509881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.3451509881
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.2196622916
Short name T77
Test name
Test status
Simulation time 30791852 ps
CPU time 0.97 seconds
Started Dec 20 12:54:44 PM PST 23
Finished Dec 20 12:54:59 PM PST 23
Peak memory 205536 kb
Host smart-f4275301-ba54-4268-a796-752dece03d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196622916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.2196622916
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.2225054616
Short name T37
Test name
Test status
Simulation time 29613060 ps
CPU time 1.07 seconds
Started Dec 20 12:54:49 PM PST 23
Finished Dec 20 12:55:07 PM PST 23
Peak memory 205500 kb
Host smart-3b5d6ac3-6438-4ac6-af9b-84e9992b598d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225054616 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.2225054616
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.1551452987
Short name T904
Test name
Test status
Simulation time 32372937 ps
CPU time 0.99 seconds
Started Dec 20 12:54:48 PM PST 23
Finished Dec 20 12:55:07 PM PST 23
Peak memory 205152 kb
Host smart-5ff20991-d7e3-4af1-9bb5-b742b85a320a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551452987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.1551452987
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.1142955482
Short name T292
Test name
Test status
Simulation time 17846976 ps
CPU time 0.92 seconds
Started Dec 20 12:54:45 PM PST 23
Finished Dec 20 12:55:00 PM PST 23
Peak memory 204980 kb
Host smart-a8451fe0-5741-47e9-a423-fbab97de82e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142955482 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.1142955482
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.3965471558
Short name T305
Test name
Test status
Simulation time 43146962 ps
CPU time 0.9 seconds
Started Dec 20 12:52:57 PM PST 23
Finished Dec 20 12:53:11 PM PST 23
Peak memory 205692 kb
Host smart-195eb87d-6729-4d4e-a24f-8e5051b1db8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965471558 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.3965471558
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.775627209
Short name T460
Test name
Test status
Simulation time 16821247 ps
CPU time 0.9 seconds
Started Dec 20 12:52:54 PM PST 23
Finished Dec 20 12:53:09 PM PST 23
Peak memory 205516 kb
Host smart-b0b9b7b5-2aad-4b34-b3a3-1f7525f3ce5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775627209 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.775627209
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_err.3672069717
Short name T214
Test name
Test status
Simulation time 31290827 ps
CPU time 1.02 seconds
Started Dec 20 12:52:58 PM PST 23
Finished Dec 20 12:53:12 PM PST 23
Peak memory 214792 kb
Host smart-59036a8a-0651-4d1a-a823-4e4b82da213f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672069717 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.3672069717
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.132560404
Short name T479
Test name
Test status
Simulation time 18811277 ps
CPU time 0.96 seconds
Started Dec 20 12:53:00 PM PST 23
Finished Dec 20 12:53:14 PM PST 23
Peak memory 205552 kb
Host smart-704fbc89-653a-4166-9081-dbe44abfeeb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132560404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.132560404
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.2134418358
Short name T858
Test name
Test status
Simulation time 19247407 ps
CPU time 1.03 seconds
Started Dec 20 12:53:00 PM PST 23
Finished Dec 20 12:53:13 PM PST 23
Peak memory 214124 kb
Host smart-7b7cedc6-a9c4-4924-91fd-9dbd03a100b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134418358 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.2134418358
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.1778446130
Short name T757
Test name
Test status
Simulation time 218774181 ps
CPU time 0.83 seconds
Started Dec 20 12:52:55 PM PST 23
Finished Dec 20 12:53:10 PM PST 23
Peak memory 204692 kb
Host smart-4fd70562-6ea9-47bb-9cc8-7b7f5eec1a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778446130 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.1778446130
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.2338099334
Short name T912
Test name
Test status
Simulation time 524792603 ps
CPU time 3.1 seconds
Started Dec 20 12:52:56 PM PST 23
Finished Dec 20 12:53:14 PM PST 23
Peak memory 206172 kb
Host smart-62126c8f-74f4-497f-8ad6-1379f9d029fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338099334 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.2338099334
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.10920833
Short name T532
Test name
Test status
Simulation time 307565829340 ps
CPU time 886.16 seconds
Started Dec 20 12:52:56 PM PST 23
Finished Dec 20 01:07:56 PM PST 23
Peak memory 215728 kb
Host smart-b34bc749-a2cd-4a0f-87a0-7b67fe10e803
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10920833 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.10920833
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.2622353573
Short name T511
Test name
Test status
Simulation time 16845275 ps
CPU time 0.94 seconds
Started Dec 20 12:54:54 PM PST 23
Finished Dec 20 12:55:13 PM PST 23
Peak memory 205136 kb
Host smart-1ade661d-e35c-435a-8864-c8e611902be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622353573 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.2622353573
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.2501856096
Short name T666
Test name
Test status
Simulation time 21273574 ps
CPU time 1.03 seconds
Started Dec 20 12:54:55 PM PST 23
Finished Dec 20 12:55:14 PM PST 23
Peak memory 205080 kb
Host smart-0558d6b6-7baf-4825-9d42-df5e603f537d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501856096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.2501856096
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.3783145864
Short name T603
Test name
Test status
Simulation time 15525880 ps
CPU time 0.98 seconds
Started Dec 20 12:54:54 PM PST 23
Finished Dec 20 12:55:13 PM PST 23
Peak memory 205308 kb
Host smart-caee1b43-5825-4bbe-a4f1-d86c30f907da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783145864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.3783145864
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.929741094
Short name T596
Test name
Test status
Simulation time 147767876 ps
CPU time 3.28 seconds
Started Dec 20 12:54:54 PM PST 23
Finished Dec 20 12:55:16 PM PST 23
Peak memory 214216 kb
Host smart-878742b5-9edc-4fa7-ad8e-3ff70b9fe737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929741094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.929741094
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.1014434589
Short name T763
Test name
Test status
Simulation time 58561335 ps
CPU time 2.14 seconds
Started Dec 20 12:54:51 PM PST 23
Finished Dec 20 12:55:12 PM PST 23
Peak memory 214328 kb
Host smart-e2b8c31a-b667-42ac-8175-f0faae9c21c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014434589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.1014434589
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.2813780925
Short name T890
Test name
Test status
Simulation time 41477764 ps
CPU time 1.13 seconds
Started Dec 20 12:54:55 PM PST 23
Finished Dec 20 12:55:14 PM PST 23
Peak memory 214332 kb
Host smart-6463e956-5c09-42ee-8878-6a19ee3c7637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813780925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.2813780925
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.1142242085
Short name T506
Test name
Test status
Simulation time 35456872 ps
CPU time 0.99 seconds
Started Dec 20 12:54:52 PM PST 23
Finished Dec 20 12:55:11 PM PST 23
Peak memory 205552 kb
Host smart-834da768-564d-4f1c-bb44-18b42604dc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142242085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.1142242085
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.817388654
Short name T833
Test name
Test status
Simulation time 37563928 ps
CPU time 0.95 seconds
Started Dec 20 12:52:55 PM PST 23
Finished Dec 20 12:53:10 PM PST 23
Peak memory 205136 kb
Host smart-ae8746db-23ab-4db3-9367-826b69ebec92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817388654 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.817388654
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.4073674659
Short name T837
Test name
Test status
Simulation time 23565497 ps
CPU time 0.86 seconds
Started Dec 20 12:52:54 PM PST 23
Finished Dec 20 12:53:09 PM PST 23
Peak memory 204664 kb
Host smart-ed225aaa-dbc5-4dd5-b379-7aa63bc55dd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073674659 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.4073674659
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.2454608538
Short name T103
Test name
Test status
Simulation time 47819440 ps
CPU time 0.8 seconds
Started Dec 20 12:52:58 PM PST 23
Finished Dec 20 12:53:12 PM PST 23
Peak memory 214384 kb
Host smart-3b81adff-8fee-4dbc-af32-94d3e8726a4a
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454608538 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.2454608538
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.4225189639
Short name T128
Test name
Test status
Simulation time 125599614 ps
CPU time 0.92 seconds
Started Dec 20 12:52:58 PM PST 23
Finished Dec 20 12:53:12 PM PST 23
Peak memory 214568 kb
Host smart-97893cb5-f1d6-4d73-99cf-b7465dfbc328
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225189639 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.4225189639
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.1809666737
Short name T227
Test name
Test status
Simulation time 19157692 ps
CPU time 1.19 seconds
Started Dec 20 12:53:00 PM PST 23
Finished Dec 20 12:53:14 PM PST 23
Peak memory 221884 kb
Host smart-91c7c550-095c-4fcb-8e9d-b4655e9f5743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809666737 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.1809666737
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.2742475652
Short name T969
Test name
Test status
Simulation time 80690716 ps
CPU time 0.86 seconds
Started Dec 20 12:52:55 PM PST 23
Finished Dec 20 12:53:10 PM PST 23
Peak memory 205048 kb
Host smart-d4a97c24-6d8e-47c6-9cb2-094782949dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742475652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.2742475652
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.895971660
Short name T970
Test name
Test status
Simulation time 22200212 ps
CPU time 0.97 seconds
Started Dec 20 12:52:57 PM PST 23
Finished Dec 20 12:53:12 PM PST 23
Peak memory 214608 kb
Host smart-7b63f34f-a753-4ed3-a319-8e38eb097e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895971660 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.895971660
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.3058305366
Short name T754
Test name
Test status
Simulation time 20161280 ps
CPU time 0.85 seconds
Started Dec 20 12:52:59 PM PST 23
Finished Dec 20 12:53:13 PM PST 23
Peak memory 204940 kb
Host smart-e6141722-9584-4043-a33a-03d144f3300f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058305366 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.3058305366
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.1381416740
Short name T482
Test name
Test status
Simulation time 98613352 ps
CPU time 2.56 seconds
Started Dec 20 12:52:56 PM PST 23
Finished Dec 20 12:53:13 PM PST 23
Peak memory 205756 kb
Host smart-b33097b8-64bf-4ecb-b5bf-546a7b889148
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381416740 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.1381416740
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.91025768
Short name T829
Test name
Test status
Simulation time 68487000742 ps
CPU time 853.73 seconds
Started Dec 20 12:53:01 PM PST 23
Finished Dec 20 01:07:28 PM PST 23
Peak memory 215264 kb
Host smart-ce20d5cf-b4bb-4dac-ac29-794c2ff055b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91025768 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.91025768
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.1016577496
Short name T730
Test name
Test status
Simulation time 47293978 ps
CPU time 0.87 seconds
Started Dec 20 12:54:55 PM PST 23
Finished Dec 20 12:55:13 PM PST 23
Peak memory 205168 kb
Host smart-f9aae909-538e-46f6-a381-d7b330c36728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016577496 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.1016577496
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.1894341479
Short name T931
Test name
Test status
Simulation time 19989638 ps
CPU time 1.01 seconds
Started Dec 20 12:54:59 PM PST 23
Finished Dec 20 12:55:21 PM PST 23
Peak memory 205552 kb
Host smart-1b9840f7-2818-4b19-81d3-96f506e8e917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894341479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.1894341479
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.1695414286
Short name T633
Test name
Test status
Simulation time 118328421 ps
CPU time 0.95 seconds
Started Dec 20 12:54:52 PM PST 23
Finished Dec 20 12:55:11 PM PST 23
Peak memory 205208 kb
Host smart-bd066516-e48b-4655-af07-a5c8aabc2160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695414286 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.1695414286
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.1567438599
Short name T346
Test name
Test status
Simulation time 82152041 ps
CPU time 2.32 seconds
Started Dec 20 12:54:52 PM PST 23
Finished Dec 20 12:55:13 PM PST 23
Peak memory 214324 kb
Host smart-2521c442-eb64-479f-b7e3-558ed0a04538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567438599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.1567438599
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.310071092
Short name T718
Test name
Test status
Simulation time 34037017 ps
CPU time 1.01 seconds
Started Dec 20 12:54:50 PM PST 23
Finished Dec 20 12:55:10 PM PST 23
Peak memory 205012 kb
Host smart-a0c69ad0-2091-4907-b0ae-67f75e244eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310071092 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.310071092
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.1284884465
Short name T944
Test name
Test status
Simulation time 87598644 ps
CPU time 1.23 seconds
Started Dec 20 12:54:55 PM PST 23
Finished Dec 20 12:55:14 PM PST 23
Peak memory 205340 kb
Host smart-e2c650f7-1a5b-49b0-bace-7fde7557b9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284884465 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.1284884465
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.2213387468
Short name T814
Test name
Test status
Simulation time 20755991 ps
CPU time 1.04 seconds
Started Dec 20 12:54:49 PM PST 23
Finished Dec 20 12:55:08 PM PST 23
Peak memory 214228 kb
Host smart-7b34a7ed-3668-44ac-8f51-d5fa40b7f2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213387468 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.2213387468
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.1592946539
Short name T518
Test name
Test status
Simulation time 91523234 ps
CPU time 1.16 seconds
Started Dec 20 12:54:50 PM PST 23
Finished Dec 20 12:55:10 PM PST 23
Peak memory 205228 kb
Host smart-edba9913-f3e3-420c-9519-5ed20a8354b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592946539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.1592946539
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.1803800145
Short name T891
Test name
Test status
Simulation time 25268696 ps
CPU time 0.85 seconds
Started Dec 20 12:54:50 PM PST 23
Finished Dec 20 12:55:09 PM PST 23
Peak memory 204908 kb
Host smart-4a08b251-4529-4a28-95ec-345a44d74907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803800145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.1803800145
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.1250420569
Short name T238
Test name
Test status
Simulation time 31160217 ps
CPU time 0.97 seconds
Started Dec 20 12:53:01 PM PST 23
Finished Dec 20 12:53:15 PM PST 23
Peak memory 206024 kb
Host smart-349f7c58-b446-493a-b123-9cb71bb6ab12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250420569 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.1250420569
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.245313106
Short name T486
Test name
Test status
Simulation time 53942022 ps
CPU time 0.88 seconds
Started Dec 20 12:53:03 PM PST 23
Finished Dec 20 12:53:18 PM PST 23
Peak memory 204704 kb
Host smart-1a4013b7-579e-4c94-9f4b-3de7ef3e2b9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245313106 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.245313106
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.288531953
Short name T105
Test name
Test status
Simulation time 44845995 ps
CPU time 0.98 seconds
Started Dec 20 12:53:21 PM PST 23
Finished Dec 20 12:53:32 PM PST 23
Peak memory 214708 kb
Host smart-23fe43ec-69e1-4f0d-a6bb-4f13394c25ba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288531953 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_di
sable_auto_req_mode.288531953
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.2246574229
Short name T48
Test name
Test status
Simulation time 17945193 ps
CPU time 1.09 seconds
Started Dec 20 12:53:01 PM PST 23
Finished Dec 20 12:53:15 PM PST 23
Peak memory 221728 kb
Host smart-f76410ba-82ac-486b-b44d-055f5108d26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246574229 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.2246574229
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.2110837834
Short name T11
Test name
Test status
Simulation time 33919124 ps
CPU time 1.34 seconds
Started Dec 20 12:52:55 PM PST 23
Finished Dec 20 12:53:10 PM PST 23
Peak memory 214300 kb
Host smart-0dba8f0d-7546-4237-a2d1-ae120b56b56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110837834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.2110837834
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.2561602093
Short name T45
Test name
Test status
Simulation time 30225785 ps
CPU time 0.93 seconds
Started Dec 20 12:53:00 PM PST 23
Finished Dec 20 12:53:13 PM PST 23
Peak memory 221880 kb
Host smart-2872795b-30f9-476e-83ce-8c36de72cf08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561602093 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.2561602093
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.1654087374
Short name T569
Test name
Test status
Simulation time 18005169 ps
CPU time 0.88 seconds
Started Dec 20 12:52:59 PM PST 23
Finished Dec 20 12:53:13 PM PST 23
Peak memory 204828 kb
Host smart-37489d88-22f8-45f0-884b-85ca12bdd345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654087374 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.1654087374
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.2629154584
Short name T340
Test name
Test status
Simulation time 607552114 ps
CPU time 3.86 seconds
Started Dec 20 12:52:55 PM PST 23
Finished Dec 20 12:53:13 PM PST 23
Peak memory 205848 kb
Host smart-e1d28ca4-86d2-4583-9c0e-363586768888
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629154584 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.2629154584
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.2997942554
Short name T216
Test name
Test status
Simulation time 51444948909 ps
CPU time 428.99 seconds
Started Dec 20 12:53:02 PM PST 23
Finished Dec 20 01:00:24 PM PST 23
Peak memory 215604 kb
Host smart-23217213-7534-4426-ae45-b9f6c3c7d5c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997942554 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.2997942554
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.3555444180
Short name T862
Test name
Test status
Simulation time 173068637 ps
CPU time 1.16 seconds
Started Dec 20 12:54:48 PM PST 23
Finished Dec 20 12:55:04 PM PST 23
Peak memory 205596 kb
Host smart-a29fca87-a3c0-40e2-a41f-dc502e56a367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555444180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.3555444180
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.2672939955
Short name T298
Test name
Test status
Simulation time 36480618 ps
CPU time 0.96 seconds
Started Dec 20 12:54:49 PM PST 23
Finished Dec 20 12:55:07 PM PST 23
Peak memory 205528 kb
Host smart-fe7a8324-f5eb-4242-ad07-4c202ca674dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672939955 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.2672939955
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.730746354
Short name T908
Test name
Test status
Simulation time 21273708 ps
CPU time 0.98 seconds
Started Dec 20 12:54:51 PM PST 23
Finished Dec 20 12:55:10 PM PST 23
Peak memory 205292 kb
Host smart-4e85039f-3f70-441f-b896-b68866380ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730746354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.730746354
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.1351246865
Short name T468
Test name
Test status
Simulation time 62282528 ps
CPU time 1.11 seconds
Started Dec 20 12:54:48 PM PST 23
Finished Dec 20 12:55:06 PM PST 23
Peak memory 205604 kb
Host smart-21429ca5-ef4c-425e-b6de-697a5bba8e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351246865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.1351246865
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.3375069503
Short name T869
Test name
Test status
Simulation time 31154015 ps
CPU time 0.94 seconds
Started Dec 20 12:54:48 PM PST 23
Finished Dec 20 12:55:06 PM PST 23
Peak memory 204976 kb
Host smart-7e7d66d1-5adf-46cf-a431-bb24fd65b838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375069503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.3375069503
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.3466816951
Short name T790
Test name
Test status
Simulation time 241536746 ps
CPU time 1.15 seconds
Started Dec 20 12:54:45 PM PST 23
Finished Dec 20 12:55:00 PM PST 23
Peak memory 205484 kb
Host smart-4390ab87-77ea-487d-b595-ae2bb9e75003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466816951 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.3466816951
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.340176887
Short name T582
Test name
Test status
Simulation time 47696604 ps
CPU time 1 seconds
Started Dec 20 12:54:53 PM PST 23
Finished Dec 20 12:55:12 PM PST 23
Peak memory 214224 kb
Host smart-688698a6-b8ab-4820-8324-730b39f40e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340176887 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.340176887
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.2729949895
Short name T932
Test name
Test status
Simulation time 30761176 ps
CPU time 0.99 seconds
Started Dec 20 12:54:46 PM PST 23
Finished Dec 20 12:55:02 PM PST 23
Peak memory 205440 kb
Host smart-12330208-d015-4f8c-afc0-5b4977799c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729949895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.2729949895
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.2598159006
Short name T958
Test name
Test status
Simulation time 27843794 ps
CPU time 1.01 seconds
Started Dec 20 12:54:51 PM PST 23
Finished Dec 20 12:55:10 PM PST 23
Peak memory 205076 kb
Host smart-7c6cdc09-d8e5-4f3e-887c-1d4862635b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598159006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.2598159006
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert_test.2829930731
Short name T781
Test name
Test status
Simulation time 14649052 ps
CPU time 0.79 seconds
Started Dec 20 12:53:04 PM PST 23
Finished Dec 20 12:53:19 PM PST 23
Peak memory 204380 kb
Host smart-5823c50a-f422-4466-a0c9-013fca9a9f5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829930731 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.2829930731
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.4147430257
Short name T564
Test name
Test status
Simulation time 13625905 ps
CPU time 0.86 seconds
Started Dec 20 12:53:01 PM PST 23
Finished Dec 20 12:53:15 PM PST 23
Peak memory 214596 kb
Host smart-72469c54-adbe-456e-92bc-c66ddf50b1e4
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147430257 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.4147430257
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.3477049273
Short name T150
Test name
Test status
Simulation time 68011142 ps
CPU time 0.96 seconds
Started Dec 20 12:53:02 PM PST 23
Finished Dec 20 12:53:16 PM PST 23
Peak memory 214628 kb
Host smart-d47f8ffe-2cc5-45cd-b230-80cced2e5211
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477049273 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.3477049273
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.2394589232
Short name T588
Test name
Test status
Simulation time 44226052 ps
CPU time 1.22 seconds
Started Dec 20 12:53:06 PM PST 23
Finished Dec 20 12:53:21 PM PST 23
Peak memory 221892 kb
Host smart-266bfe40-b053-4f54-ae36-24815314f20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394589232 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.2394589232
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.3334892049
Short name T900
Test name
Test status
Simulation time 29970401 ps
CPU time 0.92 seconds
Started Dec 20 12:53:00 PM PST 23
Finished Dec 20 12:53:15 PM PST 23
Peak memory 204968 kb
Host smart-5e21f0e7-fce3-491a-ad64-8975665c7731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334892049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.3334892049
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_smoke.405284859
Short name T490
Test name
Test status
Simulation time 26718322 ps
CPU time 0.87 seconds
Started Dec 20 12:53:04 PM PST 23
Finished Dec 20 12:53:19 PM PST 23
Peak memory 204732 kb
Host smart-dfc45078-55a3-4a4a-b2e0-832c9aa60c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405284859 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.405284859
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.3442253043
Short name T481
Test name
Test status
Simulation time 398898796 ps
CPU time 4.08 seconds
Started Dec 20 12:53:01 PM PST 23
Finished Dec 20 12:53:17 PM PST 23
Peak memory 206024 kb
Host smart-ca313ece-0eb1-4b06-8032-a47460a5ab22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442253043 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.3442253043
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/160.edn_genbits.1989323958
Short name T851
Test name
Test status
Simulation time 14854789 ps
CPU time 1 seconds
Started Dec 20 12:54:49 PM PST 23
Finished Dec 20 12:55:07 PM PST 23
Peak memory 206032 kb
Host smart-c62b5cdb-86dc-4f27-8c79-fa3986827424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989323958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1989323958
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.946724224
Short name T287
Test name
Test status
Simulation time 57507135 ps
CPU time 0.98 seconds
Started Dec 20 12:54:43 PM PST 23
Finished Dec 20 12:54:58 PM PST 23
Peak memory 205268 kb
Host smart-d5f4123d-b939-4910-b89c-b2c3380ae99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946724224 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.946724224
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.228579354
Short name T768
Test name
Test status
Simulation time 70900620 ps
CPU time 2.58 seconds
Started Dec 20 12:54:49 PM PST 23
Finished Dec 20 12:55:09 PM PST 23
Peak memory 214308 kb
Host smart-bfad2f1c-8866-4767-99ed-5c97b9060ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228579354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.228579354
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.3300950185
Short name T551
Test name
Test status
Simulation time 13218700 ps
CPU time 0.96 seconds
Started Dec 20 12:54:55 PM PST 23
Finished Dec 20 12:55:14 PM PST 23
Peak memory 205032 kb
Host smart-7c6010ca-4364-4bd9-a067-162862709b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300950185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.3300950185
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.1132761369
Short name T802
Test name
Test status
Simulation time 23031739 ps
CPU time 0.96 seconds
Started Dec 20 12:54:48 PM PST 23
Finished Dec 20 12:55:04 PM PST 23
Peak memory 205364 kb
Host smart-b367876c-17a4-449a-8de5-26ba19f0aaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132761369 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.1132761369
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.4026719553
Short name T278
Test name
Test status
Simulation time 229444701 ps
CPU time 3.26 seconds
Started Dec 20 12:54:51 PM PST 23
Finished Dec 20 12:55:13 PM PST 23
Peak memory 213548 kb
Host smart-b8ad0659-2d41-4b1b-8d82-6b01e9ae1832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026719553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.4026719553
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.3336315692
Short name T523
Test name
Test status
Simulation time 13357701 ps
CPU time 0.91 seconds
Started Dec 20 12:54:49 PM PST 23
Finished Dec 20 12:55:08 PM PST 23
Peak memory 205212 kb
Host smart-f696e94c-3463-42f9-8157-3c2a9fa2028b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336315692 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.3336315692
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.1482204651
Short name T937
Test name
Test status
Simulation time 55136056 ps
CPU time 0.92 seconds
Started Dec 20 12:54:45 PM PST 23
Finished Dec 20 12:55:00 PM PST 23
Peak memory 205164 kb
Host smart-9c6f9a9e-9894-4a7e-9b90-75eea0d98113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482204651 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.1482204651
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.2232081750
Short name T706
Test name
Test status
Simulation time 30276016 ps
CPU time 0.95 seconds
Started Dec 20 12:54:49 PM PST 23
Finished Dec 20 12:55:07 PM PST 23
Peak memory 205072 kb
Host smart-07504bcc-faad-4d7c-8ea8-e3b16ed63c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232081750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.2232081750
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.1309112510
Short name T615
Test name
Test status
Simulation time 63761179 ps
CPU time 0.93 seconds
Started Dec 20 12:53:10 PM PST 23
Finished Dec 20 12:53:24 PM PST 23
Peak memory 205412 kb
Host smart-63922b0c-2ea6-4c81-98fd-5514089dd6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309112510 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.1309112510
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.2111009156
Short name T772
Test name
Test status
Simulation time 24503852 ps
CPU time 0.89 seconds
Started Dec 20 12:53:09 PM PST 23
Finished Dec 20 12:53:23 PM PST 23
Peak memory 204708 kb
Host smart-2c3e628f-9efd-47cf-b316-3e2db5239fc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111009156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.2111009156
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.608755626
Short name T72
Test name
Test status
Simulation time 10815428 ps
CPU time 0.87 seconds
Started Dec 20 12:53:13 PM PST 23
Finished Dec 20 12:53:28 PM PST 23
Peak memory 214024 kb
Host smart-b9977b37-ef4b-4f84-b289-ce4e9a55d1e1
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608755626 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.608755626
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.1777607466
Short name T289
Test name
Test status
Simulation time 20670298 ps
CPU time 0.94 seconds
Started Dec 20 12:53:11 PM PST 23
Finished Dec 20 12:53:26 PM PST 23
Peak memory 214560 kb
Host smart-ea6e8e50-28f0-4812-89f1-946b3815f323
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777607466 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.1777607466
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.3922379957
Short name T169
Test name
Test status
Simulation time 19731521 ps
CPU time 1.13 seconds
Started Dec 20 12:53:08 PM PST 23
Finished Dec 20 12:53:23 PM PST 23
Peak memory 221740 kb
Host smart-a335762a-e9e3-4571-87f1-33316c14219a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922379957 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.3922379957
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.2322018351
Short name T347
Test name
Test status
Simulation time 108452623 ps
CPU time 2.75 seconds
Started Dec 20 12:53:13 PM PST 23
Finished Dec 20 12:53:29 PM PST 23
Peak memory 214256 kb
Host smart-1ddbc6d4-a25e-47c3-af74-f10508b949c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322018351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.2322018351
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.3593636269
Short name T956
Test name
Test status
Simulation time 23926652 ps
CPU time 0.85 seconds
Started Dec 20 12:53:10 PM PST 23
Finished Dec 20 12:53:24 PM PST 23
Peak memory 214648 kb
Host smart-9538d558-dc9f-4f69-bb58-8b175ebc68f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593636269 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3593636269
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.1226858572
Short name T888
Test name
Test status
Simulation time 14181225 ps
CPU time 0.88 seconds
Started Dec 20 12:53:04 PM PST 23
Finished Dec 20 12:53:19 PM PST 23
Peak memory 204972 kb
Host smart-7f876727-751e-4096-9408-09a01c45c6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226858572 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.1226858572
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.2174210848
Short name T651
Test name
Test status
Simulation time 262534127 ps
CPU time 2.98 seconds
Started Dec 20 12:53:08 PM PST 23
Finished Dec 20 12:53:25 PM PST 23
Peak memory 205492 kb
Host smart-a41c4749-1269-45f7-b8db-176eba6364b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174210848 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.2174210848
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.4149587957
Short name T529
Test name
Test status
Simulation time 30730646908 ps
CPU time 261.98 seconds
Started Dec 20 12:53:11 PM PST 23
Finished Dec 20 12:57:47 PM PST 23
Peak memory 214536 kb
Host smart-db80ea59-b0f3-46dc-8aa5-48450e371c44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149587957 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.4149587957
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.2697240620
Short name T899
Test name
Test status
Simulation time 124014349 ps
CPU time 0.88 seconds
Started Dec 20 12:54:55 PM PST 23
Finished Dec 20 12:55:14 PM PST 23
Peak memory 205056 kb
Host smart-9dbe8248-af52-481c-997b-67f09f11b49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697240620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.2697240620
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.3313872733
Short name T681
Test name
Test status
Simulation time 243353546 ps
CPU time 0.96 seconds
Started Dec 20 12:55:01 PM PST 23
Finished Dec 20 12:55:24 PM PST 23
Peak memory 205240 kb
Host smart-fef1b148-e947-4d9e-be13-2daf956a9a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313872733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.3313872733
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.1251008662
Short name T488
Test name
Test status
Simulation time 29323283 ps
CPU time 0.91 seconds
Started Dec 20 12:54:51 PM PST 23
Finished Dec 20 12:55:10 PM PST 23
Peak memory 205144 kb
Host smart-177c6d3c-b517-436e-9da8-a78894cdaa74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251008662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.1251008662
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.4060903481
Short name T818
Test name
Test status
Simulation time 4273683598 ps
CPU time 85.7 seconds
Started Dec 20 12:54:47 PM PST 23
Finished Dec 20 12:56:28 PM PST 23
Peak memory 214176 kb
Host smart-f76e0936-e905-4f2a-8807-5295845df54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060903481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.4060903481
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.859377646
Short name T734
Test name
Test status
Simulation time 31190225 ps
CPU time 1.01 seconds
Started Dec 20 12:54:55 PM PST 23
Finished Dec 20 12:55:14 PM PST 23
Peak memory 205972 kb
Host smart-424fbf83-d8fc-4a75-b85a-d583eb868c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859377646 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.859377646
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.2428248310
Short name T10
Test name
Test status
Simulation time 66423917 ps
CPU time 0.99 seconds
Started Dec 20 12:54:44 PM PST 23
Finished Dec 20 12:54:59 PM PST 23
Peak memory 214232 kb
Host smart-3519b246-0e49-4666-a571-4a4d54f845e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428248310 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.2428248310
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.153326912
Short name T20
Test name
Test status
Simulation time 31685613 ps
CPU time 0.95 seconds
Started Dec 20 12:54:49 PM PST 23
Finished Dec 20 12:55:07 PM PST 23
Peak memory 205272 kb
Host smart-4bbe7b1d-3d96-44e3-88ac-6431cffb6a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153326912 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.153326912
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.1415773096
Short name T948
Test name
Test status
Simulation time 29670090 ps
CPU time 1.01 seconds
Started Dec 20 12:54:50 PM PST 23
Finished Dec 20 12:55:09 PM PST 23
Peak memory 214216 kb
Host smart-c11e98d0-1f32-4028-949d-8d6657dd87b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415773096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.1415773096
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.674049749
Short name T741
Test name
Test status
Simulation time 44481079 ps
CPU time 0.86 seconds
Started Dec 20 12:54:49 PM PST 23
Finished Dec 20 12:55:08 PM PST 23
Peak memory 205188 kb
Host smart-8559c648-956a-4487-bbef-5fabecabd3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674049749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.674049749
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.179699333
Short name T107
Test name
Test status
Simulation time 157251512 ps
CPU time 1.99 seconds
Started Dec 20 12:54:51 PM PST 23
Finished Dec 20 12:55:11 PM PST 23
Peak memory 213996 kb
Host smart-bb4aff0d-e0e0-4eaf-81b0-7d81422bac5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179699333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.179699333
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.1407978565
Short name T892
Test name
Test status
Simulation time 20911780 ps
CPU time 1 seconds
Started Dec 20 12:53:11 PM PST 23
Finished Dec 20 12:53:26 PM PST 23
Peak memory 205772 kb
Host smart-ff7f0df0-7434-4b90-b219-4c668da7c051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407978565 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.1407978565
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.998138124
Short name T462
Test name
Test status
Simulation time 38010844 ps
CPU time 0.94 seconds
Started Dec 20 12:53:10 PM PST 23
Finished Dec 20 12:53:24 PM PST 23
Peak memory 205228 kb
Host smart-99802a36-0155-44ad-9076-c65fae9e1e13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998138124 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.998138124
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.2322976092
Short name T638
Test name
Test status
Simulation time 11124927 ps
CPU time 0.82 seconds
Started Dec 20 12:53:13 PM PST 23
Finished Dec 20 12:53:28 PM PST 23
Peak memory 214244 kb
Host smart-0453a3cb-2352-4601-94b2-4480f5c2933d
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322976092 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2322976092
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.3247781654
Short name T133
Test name
Test status
Simulation time 88034093 ps
CPU time 1.03 seconds
Started Dec 20 12:53:09 PM PST 23
Finished Dec 20 12:53:24 PM PST 23
Peak memory 214560 kb
Host smart-f7e64cf7-73b0-49b9-b794-8eb0ea789bb7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247781654 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.3247781654
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.2825292122
Short name T806
Test name
Test status
Simulation time 18282477 ps
CPU time 1.4 seconds
Started Dec 20 12:53:12 PM PST 23
Finished Dec 20 12:53:27 PM PST 23
Peak memory 221804 kb
Host smart-55f6b936-08af-473f-adeb-bd44403e4b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825292122 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.2825292122
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.526331754
Short name T671
Test name
Test status
Simulation time 39578800 ps
CPU time 0.87 seconds
Started Dec 20 12:53:09 PM PST 23
Finished Dec 20 12:53:24 PM PST 23
Peak memory 205204 kb
Host smart-148aefa9-9a7e-4a31-8777-12ee5928d85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526331754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.526331754
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.1135228054
Short name T822
Test name
Test status
Simulation time 21262541 ps
CPU time 1.04 seconds
Started Dec 20 12:53:10 PM PST 23
Finished Dec 20 12:53:24 PM PST 23
Peak memory 221600 kb
Host smart-bb33eb54-2de3-49ce-b21e-0522e86b33f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135228054 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1135228054
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.1896544711
Short name T661
Test name
Test status
Simulation time 12246415 ps
CPU time 0.83 seconds
Started Dec 20 12:53:10 PM PST 23
Finished Dec 20 12:53:24 PM PST 23
Peak memory 204636 kb
Host smart-09341a01-5a30-4966-8634-df770665748b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896544711 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.1896544711
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.3499411792
Short name T759
Test name
Test status
Simulation time 60482526 ps
CPU time 1.71 seconds
Started Dec 20 12:53:11 PM PST 23
Finished Dec 20 12:53:26 PM PST 23
Peak memory 205232 kb
Host smart-4cafd802-cb10-4fee-840d-cec87e5d59a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499411792 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.3499411792
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.4068454288
Short name T96
Test name
Test status
Simulation time 754796673902 ps
CPU time 1505.28 seconds
Started Dec 20 12:53:13 PM PST 23
Finished Dec 20 01:18:32 PM PST 23
Peak memory 218212 kb
Host smart-476ca36b-a0c4-4ff1-944a-245fd2b6c3e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068454288 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.4068454288
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.3570730892
Short name T530
Test name
Test status
Simulation time 17072305 ps
CPU time 0.89 seconds
Started Dec 20 12:54:51 PM PST 23
Finished Dec 20 12:55:10 PM PST 23
Peak memory 204976 kb
Host smart-fc44072c-695d-4e49-ae7c-f6427aee464c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570730892 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.3570730892
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.4020620610
Short name T898
Test name
Test status
Simulation time 67717260 ps
CPU time 1 seconds
Started Dec 20 12:54:52 PM PST 23
Finished Dec 20 12:55:12 PM PST 23
Peak memory 205644 kb
Host smart-16dca9d0-2791-4f2f-b7ec-4c3dfdc200b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020620610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.4020620610
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.2383905177
Short name T547
Test name
Test status
Simulation time 103020514 ps
CPU time 2.39 seconds
Started Dec 20 12:54:54 PM PST 23
Finished Dec 20 12:55:14 PM PST 23
Peak memory 214264 kb
Host smart-46a7fcf4-ccac-4aaa-bf77-3e3ed945670f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383905177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.2383905177
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.3530883094
Short name T748
Test name
Test status
Simulation time 52602421 ps
CPU time 1.2 seconds
Started Dec 20 12:54:52 PM PST 23
Finished Dec 20 12:55:12 PM PST 23
Peak memory 214260 kb
Host smart-dfe513e3-e7a6-4a33-a894-281c3cc2c45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530883094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.3530883094
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.256996519
Short name T792
Test name
Test status
Simulation time 28640893 ps
CPU time 0.92 seconds
Started Dec 20 12:54:50 PM PST 23
Finished Dec 20 12:55:10 PM PST 23
Peak memory 205040 kb
Host smart-3283c5b2-d85e-4780-bf1a-be110e08e3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256996519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.256996519
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.2272659455
Short name T527
Test name
Test status
Simulation time 61956066 ps
CPU time 1.52 seconds
Started Dec 20 12:54:53 PM PST 23
Finished Dec 20 12:55:13 PM PST 23
Peak memory 214304 kb
Host smart-80e7507d-a60d-49b0-856b-6d80fce13701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272659455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.2272659455
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.1369555125
Short name T256
Test name
Test status
Simulation time 18591691 ps
CPU time 0.97 seconds
Started Dec 20 12:54:51 PM PST 23
Finished Dec 20 12:55:10 PM PST 23
Peak memory 205016 kb
Host smart-85bdfaba-e561-42cf-a515-6fcd54c37b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369555125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.1369555125
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.3042789972
Short name T696
Test name
Test status
Simulation time 268826304 ps
CPU time 1.42 seconds
Started Dec 20 12:55:00 PM PST 23
Finished Dec 20 12:55:23 PM PST 23
Peak memory 205492 kb
Host smart-80afe151-2333-4cb6-b6e9-fa06729d6a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042789972 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.3042789972
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.768315848
Short name T672
Test name
Test status
Simulation time 45388152 ps
CPU time 0.93 seconds
Started Dec 20 12:54:56 PM PST 23
Finished Dec 20 12:55:15 PM PST 23
Peak memory 205232 kb
Host smart-91436db3-75f6-45a8-a367-a76773ab57f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768315848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.768315848
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.777523314
Short name T324
Test name
Test status
Simulation time 68325209 ps
CPU time 1 seconds
Started Dec 20 12:53:10 PM PST 23
Finished Dec 20 12:53:25 PM PST 23
Peak memory 205352 kb
Host smart-240b36a5-445f-4f58-863f-627657c99988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777523314 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.777523314
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.3939424303
Short name T492
Test name
Test status
Simulation time 14931152 ps
CPU time 0.91 seconds
Started Dec 20 12:53:09 PM PST 23
Finished Dec 20 12:53:23 PM PST 23
Peak memory 204628 kb
Host smart-24f6ff30-7473-4b6a-bead-cfc787cb939f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939424303 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.3939424303
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.2221839211
Short name T577
Test name
Test status
Simulation time 37121732 ps
CPU time 0.9 seconds
Started Dec 20 12:53:14 PM PST 23
Finished Dec 20 12:53:28 PM PST 23
Peak memory 214652 kb
Host smart-d734193f-74ce-48bc-92d1-1c011ee1eb8f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221839211 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.2221839211
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.431978537
Short name T43
Test name
Test status
Simulation time 32169940 ps
CPU time 1.11 seconds
Started Dec 20 12:53:12 PM PST 23
Finished Dec 20 12:53:26 PM PST 23
Peak memory 228448 kb
Host smart-a78541ed-d29f-4e93-ba9b-6bf0b894b30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431978537 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.431978537
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.3190119403
Short name T936
Test name
Test status
Simulation time 17624637 ps
CPU time 1.05 seconds
Started Dec 20 12:53:15 PM PST 23
Finished Dec 20 12:53:29 PM PST 23
Peak memory 205440 kb
Host smart-10c60acd-759e-43de-bf36-374eff4b82e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190119403 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.3190119403
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.4090799772
Short name T742
Test name
Test status
Simulation time 23176765 ps
CPU time 0.89 seconds
Started Dec 20 12:53:13 PM PST 23
Finished Dec 20 12:53:27 PM PST 23
Peak memory 214632 kb
Host smart-13c9d19e-f380-4c45-8a9d-6880ac46e48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090799772 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.4090799772
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.3755558684
Short name T578
Test name
Test status
Simulation time 32222944 ps
CPU time 0.76 seconds
Started Dec 20 12:53:08 PM PST 23
Finished Dec 20 12:53:23 PM PST 23
Peak memory 204636 kb
Host smart-b6c9fb04-1f5c-4d3b-8494-8be6b18a2a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755558684 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.3755558684
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.3741218960
Short name T548
Test name
Test status
Simulation time 135983833 ps
CPU time 3.06 seconds
Started Dec 20 12:53:12 PM PST 23
Finished Dec 20 12:53:28 PM PST 23
Peak memory 206004 kb
Host smart-ef7991ae-5dca-4ff9-a796-85291688ed2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741218960 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.3741218960
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.2934763472
Short name T905
Test name
Test status
Simulation time 42095688567 ps
CPU time 1034.29 seconds
Started Dec 20 12:53:09 PM PST 23
Finished Dec 20 01:10:37 PM PST 23
Peak memory 216024 kb
Host smart-74d239b5-c1d4-4000-b06b-fdda019fd342
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934763472 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.2934763472
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.2777433838
Short name T558
Test name
Test status
Simulation time 123890663 ps
CPU time 2.68 seconds
Started Dec 20 12:54:52 PM PST 23
Finished Dec 20 12:55:13 PM PST 23
Peak memory 214236 kb
Host smart-c5bd58d9-10d0-401f-ae33-a92d0c8c1e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777433838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.2777433838
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.2561312844
Short name T541
Test name
Test status
Simulation time 34557942 ps
CPU time 0.9 seconds
Started Dec 20 12:54:59 PM PST 23
Finished Dec 20 12:55:20 PM PST 23
Peak memory 204660 kb
Host smart-0b4486a0-ccb8-4e3f-b28f-e8f81729babb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561312844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2561312844
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.1554145306
Short name T783
Test name
Test status
Simulation time 31106978 ps
CPU time 1.06 seconds
Started Dec 20 12:55:00 PM PST 23
Finished Dec 20 12:55:22 PM PST 23
Peak memory 205132 kb
Host smart-b7ef018f-86df-40b7-807d-a97d29cdbd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554145306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.1554145306
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.1582273716
Short name T250
Test name
Test status
Simulation time 21101161 ps
CPU time 1.03 seconds
Started Dec 20 12:54:49 PM PST 23
Finished Dec 20 12:55:08 PM PST 23
Peak memory 205572 kb
Host smart-a87e87ff-417e-42bd-9585-408cee8e55b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582273716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.1582273716
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.2699518886
Short name T341
Test name
Test status
Simulation time 57003842 ps
CPU time 1.09 seconds
Started Dec 20 12:54:51 PM PST 23
Finished Dec 20 12:55:11 PM PST 23
Peak memory 205592 kb
Host smart-f833346c-e71b-4c5d-be9a-a25e78b4f8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699518886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.2699518886
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.997547874
Short name T18
Test name
Test status
Simulation time 73366366 ps
CPU time 1.04 seconds
Started Dec 20 12:55:01 PM PST 23
Finished Dec 20 12:55:24 PM PST 23
Peak memory 205552 kb
Host smart-7fda17a8-a690-4ca5-8e60-34726364fc47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997547874 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.997547874
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.4013711410
Short name T295
Test name
Test status
Simulation time 41602624 ps
CPU time 0.91 seconds
Started Dec 20 12:54:48 PM PST 23
Finished Dec 20 12:55:04 PM PST 23
Peak memory 205188 kb
Host smart-28579fc5-f8b7-4337-ad9c-5546f79e0e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013711410 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.4013711410
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.3215532223
Short name T487
Test name
Test status
Simulation time 136998909 ps
CPU time 1.03 seconds
Started Dec 20 12:55:06 PM PST 23
Finished Dec 20 12:55:28 PM PST 23
Peak memory 205480 kb
Host smart-c5d1ef12-918a-46b0-82e8-e0a10171d74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215532223 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.3215532223
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.4202643968
Short name T71
Test name
Test status
Simulation time 61378899 ps
CPU time 0.93 seconds
Started Dec 20 12:54:55 PM PST 23
Finished Dec 20 12:55:13 PM PST 23
Peak memory 205044 kb
Host smart-113d64a2-f3c4-4690-9273-433f2549b228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202643968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.4202643968
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.3589240870
Short name T859
Test name
Test status
Simulation time 64162100 ps
CPU time 0.96 seconds
Started Dec 20 12:52:00 PM PST 23
Finished Dec 20 12:52:17 PM PST 23
Peak memory 205244 kb
Host smart-2d7f3713-12fe-4090-b423-06beb4e382be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589240870 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.3589240870
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.3716015082
Short name T762
Test name
Test status
Simulation time 28961579 ps
CPU time 0.85 seconds
Started Dec 20 12:51:55 PM PST 23
Finished Dec 20 12:52:11 PM PST 23
Peak memory 204680 kb
Host smart-18e290cb-0c0b-4efb-b073-f4e8864853ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716015082 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.3716015082
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.1152267239
Short name T106
Test name
Test status
Simulation time 77098785 ps
CPU time 0.97 seconds
Started Dec 20 12:52:06 PM PST 23
Finished Dec 20 12:52:25 PM PST 23
Peak memory 214680 kb
Host smart-cbcc996a-a4db-4a4e-9ec8-1c0212208dfe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152267239 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.1152267239
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.212832704
Short name T229
Test name
Test status
Simulation time 53899766 ps
CPU time 0.77 seconds
Started Dec 20 12:51:54 PM PST 23
Finished Dec 20 12:52:09 PM PST 23
Peak memory 215872 kb
Host smart-3f3abac2-5569-48d9-b072-4ab32ac5da51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212832704 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.212832704
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.3592791879
Short name T717
Test name
Test status
Simulation time 50397404 ps
CPU time 0.84 seconds
Started Dec 20 12:51:55 PM PST 23
Finished Dec 20 12:52:10 PM PST 23
Peak memory 204996 kb
Host smart-83feb52c-1145-4b0e-b604-247659055fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592791879 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.3592791879
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.768180960
Short name T67
Test name
Test status
Simulation time 36754217 ps
CPU time 0.86 seconds
Started Dec 20 12:52:00 PM PST 23
Finished Dec 20 12:52:17 PM PST 23
Peak memory 214356 kb
Host smart-19931bce-eae0-4c5e-8a53-763c7c20749b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768180960 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.768180960
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_sec_cm.3510702336
Short name T23
Test name
Test status
Simulation time 334188197 ps
CPU time 3.08 seconds
Started Dec 20 12:51:59 PM PST 23
Finished Dec 20 12:52:18 PM PST 23
Peak memory 231908 kb
Host smart-72c14b42-8bec-4166-88a6-d73959e48e40
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510702336 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.3510702336
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.1298854997
Short name T695
Test name
Test status
Simulation time 14313176 ps
CPU time 0.86 seconds
Started Dec 20 12:52:01 PM PST 23
Finished Dec 20 12:52:18 PM PST 23
Peak memory 204476 kb
Host smart-f16258f2-695c-46c5-a331-368bc9c58b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298854997 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.1298854997
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.1658576629
Short name T489
Test name
Test status
Simulation time 328065109 ps
CPU time 3.22 seconds
Started Dec 20 12:51:54 PM PST 23
Finished Dec 20 12:52:11 PM PST 23
Peak memory 205988 kb
Host smart-f4753a72-7c6c-46b9-9136-72960becc642
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658576629 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.1658576629
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.2838355866
Short name T731
Test name
Test status
Simulation time 156174438414 ps
CPU time 855.32 seconds
Started Dec 20 12:51:56 PM PST 23
Finished Dec 20 01:06:26 PM PST 23
Peak memory 216804 kb
Host smart-93bc7c62-2274-4cfa-9bba-00a367cbbb93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838355866 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.2838355866
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.793316158
Short name T318
Test name
Test status
Simulation time 56392786 ps
CPU time 0.96 seconds
Started Dec 20 12:53:13 PM PST 23
Finished Dec 20 12:53:28 PM PST 23
Peak memory 205792 kb
Host smart-c7a67aa6-bae5-4b1a-83d2-76092c384478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793316158 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.793316158
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.1021707314
Short name T519
Test name
Test status
Simulation time 56058587 ps
CPU time 0.91 seconds
Started Dec 20 12:53:32 PM PST 23
Finished Dec 20 12:53:35 PM PST 23
Peak memory 204464 kb
Host smart-32f58cdd-5b0f-4e59-bdde-c422912cb101
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021707314 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.1021707314
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.1283547300
Short name T907
Test name
Test status
Simulation time 10741831 ps
CPU time 0.8 seconds
Started Dec 20 12:53:30 PM PST 23
Finished Dec 20 12:53:34 PM PST 23
Peak memory 214348 kb
Host smart-abf4d7c2-61cf-4bb4-b51c-0f5957e39566
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283547300 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.1283547300
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.2999678354
Short name T570
Test name
Test status
Simulation time 158036210 ps
CPU time 0.97 seconds
Started Dec 20 12:53:31 PM PST 23
Finished Dec 20 12:53:34 PM PST 23
Peak memory 206272 kb
Host smart-2914f85f-c6a1-4c0c-a8ed-00035b83c8f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999678354 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.2999678354
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.354967281
Short name T788
Test name
Test status
Simulation time 18021402 ps
CPU time 1 seconds
Started Dec 20 12:53:30 PM PST 23
Finished Dec 20 12:53:34 PM PST 23
Peak memory 215948 kb
Host smart-2d378bf4-0ffa-4d03-8fc8-9c628771c7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354967281 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.354967281
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.3548921177
Short name T606
Test name
Test status
Simulation time 24674697 ps
CPU time 0.85 seconds
Started Dec 20 12:53:11 PM PST 23
Finished Dec 20 12:53:25 PM PST 23
Peak memory 204940 kb
Host smart-66af1e04-3874-4d07-bdc9-8bbf9ecf10db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548921177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.3548921177
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.952680687
Short name T91
Test name
Test status
Simulation time 20078608 ps
CPU time 1.03 seconds
Started Dec 20 12:53:13 PM PST 23
Finished Dec 20 12:53:27 PM PST 23
Peak memory 214608 kb
Host smart-6210111c-e830-4bbc-be8e-8d58777e4a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952680687 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.952680687
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.2780977269
Short name T658
Test name
Test status
Simulation time 13911313 ps
CPU time 0.89 seconds
Started Dec 20 12:53:08 PM PST 23
Finished Dec 20 12:53:23 PM PST 23
Peak memory 204820 kb
Host smart-bc8703a4-d3aa-4596-86b4-ebb292582fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780977269 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.2780977269
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.3514378757
Short name T767
Test name
Test status
Simulation time 98618177372 ps
CPU time 2321.34 seconds
Started Dec 20 12:53:13 PM PST 23
Finished Dec 20 01:32:08 PM PST 23
Peak memory 226568 kb
Host smart-c186cadc-0578-48fe-bdfc-6e5462c0f9c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514378757 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.3514378757
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.3166025857
Short name T777
Test name
Test status
Simulation time 83990413 ps
CPU time 0.89 seconds
Started Dec 20 12:54:53 PM PST 23
Finished Dec 20 12:55:12 PM PST 23
Peak memory 204992 kb
Host smart-c191f43f-5947-4786-a7f4-a80e2b4960a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166025857 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.3166025857
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.2413631305
Short name T894
Test name
Test status
Simulation time 21754188 ps
CPU time 1.1 seconds
Started Dec 20 12:54:48 PM PST 23
Finished Dec 20 12:55:07 PM PST 23
Peak memory 205892 kb
Host smart-6716710e-c5a2-4fe1-9ce8-1ee3f7b573c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413631305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.2413631305
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.3326581573
Short name T834
Test name
Test status
Simulation time 61209992 ps
CPU time 1.05 seconds
Started Dec 20 12:54:48 PM PST 23
Finished Dec 20 12:55:07 PM PST 23
Peak memory 205492 kb
Host smart-8822f8ee-806c-4999-bafb-3945556b99ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326581573 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.3326581573
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.3868157396
Short name T461
Test name
Test status
Simulation time 56007035 ps
CPU time 0.85 seconds
Started Dec 20 12:54:49 PM PST 23
Finished Dec 20 12:55:08 PM PST 23
Peak memory 205236 kb
Host smart-ca8f4c4a-cc32-4096-ab5a-19e13b1f1b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868157396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.3868157396
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.685988504
Short name T885
Test name
Test status
Simulation time 18723269 ps
CPU time 1 seconds
Started Dec 20 12:54:48 PM PST 23
Finished Dec 20 12:55:06 PM PST 23
Peak memory 205156 kb
Host smart-d475410e-e083-4f0f-8f6d-fb3e798ee5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685988504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.685988504
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.2940124199
Short name T616
Test name
Test status
Simulation time 139179029 ps
CPU time 1.84 seconds
Started Dec 20 12:54:55 PM PST 23
Finished Dec 20 12:55:14 PM PST 23
Peak memory 214216 kb
Host smart-eafcfbb9-28c7-4129-8049-df15a3dd9de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940124199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.2940124199
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.1866298048
Short name T878
Test name
Test status
Simulation time 32452396 ps
CPU time 0.94 seconds
Started Dec 20 12:54:52 PM PST 23
Finished Dec 20 12:55:11 PM PST 23
Peak memory 204948 kb
Host smart-68d577d4-08a7-4c04-a1b3-9b93e540c44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866298048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.1866298048
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.1249912554
Short name T612
Test name
Test status
Simulation time 56183571 ps
CPU time 0.93 seconds
Started Dec 20 12:54:52 PM PST 23
Finished Dec 20 12:55:11 PM PST 23
Peak memory 204868 kb
Host smart-36e2098a-219b-45a8-b14c-57edd29c0c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249912554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.1249912554
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.872553915
Short name T865
Test name
Test status
Simulation time 49327966 ps
CPU time 0.91 seconds
Started Dec 20 12:54:54 PM PST 23
Finished Dec 20 12:55:13 PM PST 23
Peak memory 205288 kb
Host smart-e3043ea5-31a7-475d-9883-d3b50a0c7081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872553915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.872553915
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.4092771541
Short name T327
Test name
Test status
Simulation time 95834668 ps
CPU time 0.89 seconds
Started Dec 20 12:54:57 PM PST 23
Finished Dec 20 12:55:17 PM PST 23
Peak memory 204948 kb
Host smart-ee0d5ac9-9a17-44b4-af3c-a5654706e211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092771541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.4092771541
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.3326207493
Short name T688
Test name
Test status
Simulation time 61385711 ps
CPU time 0.86 seconds
Started Dec 20 12:53:33 PM PST 23
Finished Dec 20 12:53:37 PM PST 23
Peak memory 205248 kb
Host smart-7d71f024-eb45-4037-938d-10552456c8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326207493 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3326207493
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.2023565059
Short name T789
Test name
Test status
Simulation time 38405189 ps
CPU time 0.8 seconds
Started Dec 20 12:53:35 PM PST 23
Finished Dec 20 12:53:39 PM PST 23
Peak memory 204240 kb
Host smart-04e3d843-1140-4359-a576-0e7b3deabd2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023565059 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.2023565059
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.3276304813
Short name T116
Test name
Test status
Simulation time 12550283 ps
CPU time 0.89 seconds
Started Dec 20 12:53:36 PM PST 23
Finished Dec 20 12:53:40 PM PST 23
Peak memory 214524 kb
Host smart-4ee2556b-ab9d-4056-b02a-3aee1de1c218
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276304813 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.3276304813
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.3828445369
Short name T495
Test name
Test status
Simulation time 21160957 ps
CPU time 0.98 seconds
Started Dec 20 12:53:30 PM PST 23
Finished Dec 20 12:53:34 PM PST 23
Peak memory 214648 kb
Host smart-680a4418-4a40-475d-9c01-3113cf788b78
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828445369 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.3828445369
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.2156204123
Short name T531
Test name
Test status
Simulation time 35926354 ps
CPU time 1.12 seconds
Started Dec 20 12:53:37 PM PST 23
Finished Dec 20 12:53:42 PM PST 23
Peak memory 221780 kb
Host smart-9db6ae96-4ff5-41aa-8ad7-186bad892246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156204123 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.2156204123
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.2910331338
Short name T947
Test name
Test status
Simulation time 23273186 ps
CPU time 1.08 seconds
Started Dec 20 12:53:36 PM PST 23
Finished Dec 20 12:53:41 PM PST 23
Peak memory 205616 kb
Host smart-8ff388ff-50a6-4a23-96c6-e2d1c25dc40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910331338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.2910331338
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.3433156658
Short name T657
Test name
Test status
Simulation time 21850293 ps
CPU time 0.91 seconds
Started Dec 20 12:53:33 PM PST 23
Finished Dec 20 12:53:38 PM PST 23
Peak memory 214584 kb
Host smart-7ba081a8-edda-4dd3-8479-668993b527b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433156658 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.3433156658
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.625387705
Short name T618
Test name
Test status
Simulation time 93602786 ps
CPU time 0.9 seconds
Started Dec 20 12:53:33 PM PST 23
Finished Dec 20 12:53:37 PM PST 23
Peak memory 204884 kb
Host smart-95a0d7c4-ce77-462b-af83-0e985b630e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625387705 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.625387705
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.1963054800
Short name T631
Test name
Test status
Simulation time 153558999 ps
CPU time 3.44 seconds
Started Dec 20 12:53:38 PM PST 23
Finished Dec 20 12:53:46 PM PST 23
Peak memory 205988 kb
Host smart-532eafb4-5d7b-456d-b705-ed27ec904ad1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963054800 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.1963054800
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.1784689956
Short name T934
Test name
Test status
Simulation time 88355636598 ps
CPU time 523.29 seconds
Started Dec 20 12:53:31 PM PST 23
Finished Dec 20 01:02:17 PM PST 23
Peak memory 214536 kb
Host smart-da559840-4f58-4369-a9c1-69ba94d12211
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784689956 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.1784689956
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.2046031709
Short name T808
Test name
Test status
Simulation time 108835665 ps
CPU time 2.19 seconds
Started Dec 20 12:54:53 PM PST 23
Finished Dec 20 12:55:14 PM PST 23
Peak memory 214256 kb
Host smart-939cc6be-6234-4bb6-ad21-47b98b4f4ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046031709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.2046031709
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.735665774
Short name T823
Test name
Test status
Simulation time 18631582 ps
CPU time 1.12 seconds
Started Dec 20 12:54:48 PM PST 23
Finished Dec 20 12:55:07 PM PST 23
Peak memory 205572 kb
Host smart-9c844370-d72c-45a1-9fce-5e3c33c076c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735665774 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.735665774
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.300529751
Short name T740
Test name
Test status
Simulation time 50012677 ps
CPU time 0.89 seconds
Started Dec 20 12:54:51 PM PST 23
Finished Dec 20 12:55:10 PM PST 23
Peak memory 205284 kb
Host smart-a6975e7d-105d-4834-9b28-9addd139ab1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300529751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.300529751
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3599150029
Short name T271
Test name
Test status
Simulation time 18792886 ps
CPU time 1.09 seconds
Started Dec 20 12:54:55 PM PST 23
Finished Dec 20 12:55:14 PM PST 23
Peak memory 205104 kb
Host smart-6cef696f-1359-419d-aeeb-fb531791ae2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599150029 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3599150029
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.2026510096
Short name T301
Test name
Test status
Simulation time 17171659 ps
CPU time 1.03 seconds
Started Dec 20 12:54:53 PM PST 23
Finished Dec 20 12:55:13 PM PST 23
Peak memory 205520 kb
Host smart-316f5fe1-23fb-45e2-96ab-ff872f4b32c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026510096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.2026510096
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.296587199
Short name T692
Test name
Test status
Simulation time 28850803 ps
CPU time 1.34 seconds
Started Dec 20 12:54:55 PM PST 23
Finished Dec 20 12:55:14 PM PST 23
Peak memory 214324 kb
Host smart-feb3c28c-a082-4ea7-b9c6-e4747a27bd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296587199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.296587199
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.131247247
Short name T561
Test name
Test status
Simulation time 22645290 ps
CPU time 1.21 seconds
Started Dec 20 12:54:50 PM PST 23
Finished Dec 20 12:55:10 PM PST 23
Peak memory 214220 kb
Host smart-79e0fc12-9508-44fb-864c-5c032d5250e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131247247 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.131247247
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.1250142656
Short name T29
Test name
Test status
Simulation time 16110062 ps
CPU time 0.98 seconds
Started Dec 20 12:54:49 PM PST 23
Finished Dec 20 12:55:07 PM PST 23
Peak memory 205148 kb
Host smart-a8fe78cb-2e79-4132-8b19-040955efa5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250142656 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.1250142656
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.4109904915
Short name T634
Test name
Test status
Simulation time 76033634 ps
CPU time 1.02 seconds
Started Dec 20 12:54:51 PM PST 23
Finished Dec 20 12:55:11 PM PST 23
Peak memory 205536 kb
Host smart-c494eea1-af48-4558-ad29-a661b99df7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109904915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.4109904915
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.2473123209
Short name T930
Test name
Test status
Simulation time 28652516 ps
CPU time 0.92 seconds
Started Dec 20 12:53:36 PM PST 23
Finished Dec 20 12:53:40 PM PST 23
Peak memory 206028 kb
Host smart-a3904c36-4e4d-4860-953c-a6fbfe1afc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473123209 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.2473123209
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.1078401774
Short name T494
Test name
Test status
Simulation time 15603321 ps
CPU time 0.87 seconds
Started Dec 20 12:53:31 PM PST 23
Finished Dec 20 12:53:35 PM PST 23
Peak memory 204640 kb
Host smart-05987006-0732-4de6-ac4f-2e0479fa2d22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078401774 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.1078401774
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.1384862725
Short name T167
Test name
Test status
Simulation time 18610546 ps
CPU time 0.78 seconds
Started Dec 20 12:53:29 PM PST 23
Finished Dec 20 12:53:34 PM PST 23
Peak memory 214196 kb
Host smart-0f6e9418-1f62-4565-9bdf-e4809dffe8d8
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384862725 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.1384862725
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.2345766449
Short name T153
Test name
Test status
Simulation time 37034960 ps
CPU time 0.97 seconds
Started Dec 20 12:53:31 PM PST 23
Finished Dec 20 12:53:35 PM PST 23
Peak memory 214536 kb
Host smart-1fee75c2-db63-4444-a5cd-dd7bd078e862
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345766449 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.2345766449
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.1867284245
Short name T933
Test name
Test status
Simulation time 51297183 ps
CPU time 0.8 seconds
Started Dec 20 12:53:34 PM PST 23
Finished Dec 20 12:53:38 PM PST 23
Peak memory 214348 kb
Host smart-0143e80f-769f-4d55-93c3-b3c6e0be69ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867284245 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.1867284245
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.1209569133
Short name T795
Test name
Test status
Simulation time 13616330 ps
CPU time 0.89 seconds
Started Dec 20 12:53:34 PM PST 23
Finished Dec 20 12:53:38 PM PST 23
Peak memory 205156 kb
Host smart-9efc1830-d65e-4160-80da-38fa37fd58a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209569133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.1209569133
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.2156001080
Short name T12
Test name
Test status
Simulation time 24475712 ps
CPU time 1.06 seconds
Started Dec 20 12:53:31 PM PST 23
Finished Dec 20 12:53:35 PM PST 23
Peak memory 221728 kb
Host smart-87b3a9a6-f931-4ab9-88cf-b827df7dba62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156001080 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.2156001080
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.566893482
Short name T458
Test name
Test status
Simulation time 25448552 ps
CPU time 0.8 seconds
Started Dec 20 12:53:33 PM PST 23
Finished Dec 20 12:53:37 PM PST 23
Peak memory 204656 kb
Host smart-b40eb145-a35d-43f3-a9dd-b738900cd5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566893482 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.566893482
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.58734688
Short name T53
Test name
Test status
Simulation time 307639051 ps
CPU time 2.06 seconds
Started Dec 20 12:53:33 PM PST 23
Finished Dec 20 12:53:39 PM PST 23
Peak memory 205692 kb
Host smart-8f53cf55-3390-4f43-918b-b1c3ceb46963
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58734688 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.58734688
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.4294380978
Short name T815
Test name
Test status
Simulation time 23970677884 ps
CPU time 597.73 seconds
Started Dec 20 12:53:31 PM PST 23
Finished Dec 20 01:03:31 PM PST 23
Peak memory 214684 kb
Host smart-7bf51a95-adf3-494b-b6c5-1a11556df025
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294380978 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.4294380978
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.3013847796
Short name T556
Test name
Test status
Simulation time 48161308 ps
CPU time 0.9 seconds
Started Dec 20 12:54:52 PM PST 23
Finished Dec 20 12:55:12 PM PST 23
Peak memory 204956 kb
Host smart-4f4e2f19-6632-4ed1-9b7b-ad0bc9d53716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013847796 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.3013847796
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.4120746417
Short name T950
Test name
Test status
Simulation time 86431695 ps
CPU time 0.91 seconds
Started Dec 20 12:55:00 PM PST 23
Finished Dec 20 12:55:21 PM PST 23
Peak memory 205048 kb
Host smart-ffc2111b-7461-4070-bbd0-993b0bc2d87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120746417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.4120746417
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.231733034
Short name T273
Test name
Test status
Simulation time 26331830 ps
CPU time 1.07 seconds
Started Dec 20 12:55:02 PM PST 23
Finished Dec 20 12:55:25 PM PST 23
Peak memory 205740 kb
Host smart-df3ef4c7-7089-4854-b336-0dbd24c4ecfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231733034 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.231733034
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.145651224
Short name T923
Test name
Test status
Simulation time 54906955 ps
CPU time 2.12 seconds
Started Dec 20 12:54:57 PM PST 23
Finished Dec 20 12:55:19 PM PST 23
Peak memory 214012 kb
Host smart-c9d2991e-499f-44c0-a8e8-a598d4b2f0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145651224 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.145651224
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.2557039858
Short name T343
Test name
Test status
Simulation time 180854319 ps
CPU time 1.01 seconds
Started Dec 20 12:54:59 PM PST 23
Finished Dec 20 12:55:19 PM PST 23
Peak memory 205312 kb
Host smart-428212c6-1a93-4cca-b64a-33132aac0757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557039858 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.2557039858
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.4252054725
Short name T337
Test name
Test status
Simulation time 30307880 ps
CPU time 1.2 seconds
Started Dec 20 12:55:01 PM PST 23
Finished Dec 20 12:55:23 PM PST 23
Peak memory 205464 kb
Host smart-de1ecac9-2c1f-480f-92c8-357ba36eaad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252054725 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.4252054725
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.1665552595
Short name T299
Test name
Test status
Simulation time 23328456 ps
CPU time 1.04 seconds
Started Dec 20 12:55:06 PM PST 23
Finished Dec 20 12:55:28 PM PST 23
Peak memory 205492 kb
Host smart-e0cb1108-7479-4fcd-8021-6243f4ae4135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665552595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.1665552595
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.287431912
Short name T549
Test name
Test status
Simulation time 30067026 ps
CPU time 1.48 seconds
Started Dec 20 12:55:00 PM PST 23
Finished Dec 20 12:55:22 PM PST 23
Peak memory 214220 kb
Host smart-9990d8c7-70d8-4491-b85b-c3454917ca56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287431912 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.287431912
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.3613462035
Short name T647
Test name
Test status
Simulation time 59235438 ps
CPU time 2.41 seconds
Started Dec 20 12:55:02 PM PST 23
Finished Dec 20 12:55:25 PM PST 23
Peak memory 214104 kb
Host smart-15681309-37ce-4ed4-8a12-a87afd1b6732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613462035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.3613462035
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.38106716
Short name T840
Test name
Test status
Simulation time 17265345 ps
CPU time 1.07 seconds
Started Dec 20 12:54:59 PM PST 23
Finished Dec 20 12:55:21 PM PST 23
Peak memory 205308 kb
Host smart-5437ce7e-df0e-43bf-9739-12d984481df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38106716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.38106716
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.1924779663
Short name T610
Test name
Test status
Simulation time 72738058 ps
CPU time 0.96 seconds
Started Dec 20 12:53:32 PM PST 23
Finished Dec 20 12:53:35 PM PST 23
Peak memory 205252 kb
Host smart-ccba2f31-f1a1-4571-8369-9baddba4567c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924779663 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.1924779663
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.1740904891
Short name T554
Test name
Test status
Simulation time 18835112 ps
CPU time 0.75 seconds
Started Dec 20 12:53:34 PM PST 23
Finished Dec 20 12:53:38 PM PST 23
Peak memory 204288 kb
Host smart-0cb6b5da-4188-4446-a4c9-d487c073b39d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740904891 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.1740904891
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.1603607601
Short name T962
Test name
Test status
Simulation time 31292442 ps
CPU time 1.07 seconds
Started Dec 20 12:53:37 PM PST 23
Finished Dec 20 12:53:42 PM PST 23
Peak memory 214616 kb
Host smart-472ab405-8478-4155-9b9d-36eba35fb967
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603607601 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.1603607601
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.3102260219
Short name T25
Test name
Test status
Simulation time 45806426 ps
CPU time 0.83 seconds
Started Dec 20 12:53:44 PM PST 23
Finished Dec 20 12:53:51 PM PST 23
Peak memory 215576 kb
Host smart-0cebecd6-08c4-4276-84c1-d275fc563fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102260219 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.3102260219
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.4123524405
Short name T797
Test name
Test status
Simulation time 34219316 ps
CPU time 1.11 seconds
Started Dec 20 12:53:29 PM PST 23
Finished Dec 20 12:53:34 PM PST 23
Peak memory 214232 kb
Host smart-54498e88-3b4e-43b0-a577-da4b1e9d5087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123524405 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.4123524405
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_smoke.2002109458
Short name T513
Test name
Test status
Simulation time 13152563 ps
CPU time 0.86 seconds
Started Dec 20 12:53:36 PM PST 23
Finished Dec 20 12:53:39 PM PST 23
Peak memory 204744 kb
Host smart-a0561188-bb52-4954-8348-e3b3bd5d5ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002109458 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.2002109458
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.442234248
Short name T464
Test name
Test status
Simulation time 140868923 ps
CPU time 1.96 seconds
Started Dec 20 12:53:33 PM PST 23
Finished Dec 20 12:53:38 PM PST 23
Peak memory 205952 kb
Host smart-0b2aa785-530f-44ab-96de-6512c284e4ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442234248 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.442234248
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.2484363851
Short name T828
Test name
Test status
Simulation time 71410142586 ps
CPU time 910.3 seconds
Started Dec 20 12:53:35 PM PST 23
Finished Dec 20 01:08:48 PM PST 23
Peak memory 216084 kb
Host smart-bfeb41ee-9f8c-45f8-a807-fb908c0986f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484363851 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.2484363851
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.32207964
Short name T669
Test name
Test status
Simulation time 58387396 ps
CPU time 1.06 seconds
Started Dec 20 12:55:02 PM PST 23
Finished Dec 20 12:55:25 PM PST 23
Peak memory 205112 kb
Host smart-880dc1f1-9941-4fae-8aaf-a07376a543b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32207964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.32207964
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.156145315
Short name T249
Test name
Test status
Simulation time 54861140 ps
CPU time 1 seconds
Started Dec 20 12:54:49 PM PST 23
Finished Dec 20 12:55:08 PM PST 23
Peak memory 205496 kb
Host smart-117125b9-9575-422b-82f7-47ec01fd304e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156145315 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.156145315
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.3435368588
Short name T841
Test name
Test status
Simulation time 16044671 ps
CPU time 0.97 seconds
Started Dec 20 12:55:05 PM PST 23
Finished Dec 20 12:55:29 PM PST 23
Peak memory 205336 kb
Host smart-c657c14c-9124-4de7-a33b-beaf5bdd71e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435368588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.3435368588
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.1278637408
Short name T574
Test name
Test status
Simulation time 52575959 ps
CPU time 1.09 seconds
Started Dec 20 12:54:57 PM PST 23
Finished Dec 20 12:55:15 PM PST 23
Peak memory 205416 kb
Host smart-371c0d8c-7f3e-404b-b874-1978d5b412cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278637408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.1278637408
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.2212850096
Short name T769
Test name
Test status
Simulation time 58986554 ps
CPU time 0.95 seconds
Started Dec 20 12:54:55 PM PST 23
Finished Dec 20 12:55:14 PM PST 23
Peak memory 205044 kb
Host smart-efe56610-d6f3-4f00-b994-63f9f0e6b633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212850096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.2212850096
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.3030024610
Short name T796
Test name
Test status
Simulation time 18229899 ps
CPU time 1.18 seconds
Started Dec 20 12:54:57 PM PST 23
Finished Dec 20 12:55:18 PM PST 23
Peak memory 214308 kb
Host smart-c114b058-bd4b-471c-acdc-644e4611ee91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030024610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.3030024610
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.2067637645
Short name T477
Test name
Test status
Simulation time 39552006 ps
CPU time 0.97 seconds
Started Dec 20 12:54:57 PM PST 23
Finished Dec 20 12:55:16 PM PST 23
Peak memory 205324 kb
Host smart-491aec92-0d76-4e54-8db8-04cd5a15872a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067637645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.2067637645
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.2184346080
Short name T897
Test name
Test status
Simulation time 35882232 ps
CPU time 1.18 seconds
Started Dec 20 12:54:50 PM PST 23
Finished Dec 20 12:55:09 PM PST 23
Peak memory 205604 kb
Host smart-32b38b9e-cbbd-425a-8901-c3f58ca88b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184346080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.2184346080
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.3756462443
Short name T843
Test name
Test status
Simulation time 20623835 ps
CPU time 1 seconds
Started Dec 20 12:54:45 PM PST 23
Finished Dec 20 12:54:59 PM PST 23
Peak memory 214224 kb
Host smart-f5914e71-b80b-4663-b5f8-2c06c4065979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756462443 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.3756462443
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.1913279985
Short name T611
Test name
Test status
Simulation time 41032266 ps
CPU time 0.93 seconds
Started Dec 20 12:54:55 PM PST 23
Finished Dec 20 12:55:14 PM PST 23
Peak memory 205128 kb
Host smart-56c033d8-f0c5-4457-9042-b85ffc4f71a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913279985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.1913279985
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.3355622659
Short name T836
Test name
Test status
Simulation time 18258771 ps
CPU time 0.92 seconds
Started Dec 20 12:53:40 PM PST 23
Finished Dec 20 12:53:46 PM PST 23
Peak memory 205004 kb
Host smart-7eb60558-0ee6-4823-b657-b6f2ab8e99fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355622659 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.3355622659
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.2168103438
Short name T758
Test name
Test status
Simulation time 42254858 ps
CPU time 0.82 seconds
Started Dec 20 12:53:35 PM PST 23
Finished Dec 20 12:53:39 PM PST 23
Peak memory 204444 kb
Host smart-7a9a79fb-a0d6-41d2-8379-d239dc3e4abf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168103438 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.2168103438
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.235703005
Short name T924
Test name
Test status
Simulation time 33200715 ps
CPU time 1.09 seconds
Started Dec 20 12:53:37 PM PST 23
Finished Dec 20 12:53:43 PM PST 23
Peak memory 214576 kb
Host smart-3e16e79e-c8be-40bd-ae24-1a3b3036344b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235703005 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_di
sable_auto_req_mode.235703005
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.3914161943
Short name T230
Test name
Test status
Simulation time 31899357 ps
CPU time 0.88 seconds
Started Dec 20 12:53:35 PM PST 23
Finished Dec 20 12:53:39 PM PST 23
Peak memory 214748 kb
Host smart-de8d3b6f-acc7-4a57-9491-6ec22323d8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914161943 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.3914161943
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.1861149748
Short name T881
Test name
Test status
Simulation time 16531431 ps
CPU time 0.99 seconds
Started Dec 20 12:53:40 PM PST 23
Finished Dec 20 12:53:46 PM PST 23
Peak memory 214272 kb
Host smart-bf17c8a5-8729-4c66-968f-fcc63d57b5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861149748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1861149748
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.2970791912
Short name T915
Test name
Test status
Simulation time 21521353 ps
CPU time 0.93 seconds
Started Dec 20 12:53:39 PM PST 23
Finished Dec 20 12:53:44 PM PST 23
Peak memory 214516 kb
Host smart-2004abac-30b4-4415-b09d-53c5e3f49b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970791912 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.2970791912
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.121060370
Short name T614
Test name
Test status
Simulation time 26284456 ps
CPU time 0.85 seconds
Started Dec 20 12:53:37 PM PST 23
Finished Dec 20 12:53:42 PM PST 23
Peak memory 204744 kb
Host smart-1c65bfdc-0f15-41db-820d-53a84d8ae71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121060370 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.121060370
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.3568367783
Short name T964
Test name
Test status
Simulation time 567716679 ps
CPU time 3.84 seconds
Started Dec 20 12:53:37 PM PST 23
Finished Dec 20 12:53:44 PM PST 23
Peak memory 206216 kb
Host smart-2c49a450-c435-4b73-9107-b02c84cb8f7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568367783 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.3568367783
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.1510143267
Short name T552
Test name
Test status
Simulation time 52279300497 ps
CPU time 322.79 seconds
Started Dec 20 12:53:36 PM PST 23
Finished Dec 20 12:59:03 PM PST 23
Peak memory 214712 kb
Host smart-e7996c89-256b-4399-a28e-0d8994fa0b85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510143267 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1510143267
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.3820997481
Short name T853
Test name
Test status
Simulation time 16164294 ps
CPU time 0.94 seconds
Started Dec 20 12:54:46 PM PST 23
Finished Dec 20 12:55:01 PM PST 23
Peak memory 205192 kb
Host smart-f5aefea6-2ab5-481b-8344-5c9581f23906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820997481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.3820997481
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.2941691751
Short name T686
Test name
Test status
Simulation time 120863244 ps
CPU time 0.93 seconds
Started Dec 20 12:54:51 PM PST 23
Finished Dec 20 12:55:10 PM PST 23
Peak memory 205244 kb
Host smart-63b26482-0483-485e-b410-ded88764c581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941691751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.2941691751
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.3484568599
Short name T333
Test name
Test status
Simulation time 43545551 ps
CPU time 1.11 seconds
Started Dec 20 12:54:50 PM PST 23
Finished Dec 20 12:55:10 PM PST 23
Peak memory 205552 kb
Host smart-9c9f0f5d-0675-4b79-93f5-0760488877ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484568599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.3484568599
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.1599025037
Short name T676
Test name
Test status
Simulation time 35914761 ps
CPU time 0.96 seconds
Started Dec 20 12:54:49 PM PST 23
Finished Dec 20 12:55:07 PM PST 23
Peak memory 205652 kb
Host smart-8dd7016d-6725-4209-9738-647621838a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599025037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.1599025037
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.4095378726
Short name T515
Test name
Test status
Simulation time 36430504 ps
CPU time 1.16 seconds
Started Dec 20 12:54:47 PM PST 23
Finished Dec 20 12:55:03 PM PST 23
Peak memory 205588 kb
Host smart-9618b0d3-1e3c-497a-9df8-4d61e825a534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095378726 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.4095378726
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.3580743148
Short name T510
Test name
Test status
Simulation time 26817111 ps
CPU time 1.28 seconds
Started Dec 20 12:54:48 PM PST 23
Finished Dec 20 12:55:07 PM PST 23
Peak memory 205784 kb
Host smart-f281960b-d0fa-4048-9777-a551fce31848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580743148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.3580743148
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.993292597
Short name T54
Test name
Test status
Simulation time 14816499 ps
CPU time 0.96 seconds
Started Dec 20 12:54:51 PM PST 23
Finished Dec 20 12:55:10 PM PST 23
Peak memory 205268 kb
Host smart-fad05ec4-326c-4cb4-9ab4-cefd4c27db51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993292597 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.993292597
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert_test.1995272461
Short name T952
Test name
Test status
Simulation time 23393441 ps
CPU time 1.02 seconds
Started Dec 20 12:53:36 PM PST 23
Finished Dec 20 12:53:40 PM PST 23
Peak memory 204700 kb
Host smart-9f1e8c7b-d19a-48a1-8694-e7653d251be4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995272461 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.1995272461
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.3339085294
Short name T118
Test name
Test status
Simulation time 12752261 ps
CPU time 0.84 seconds
Started Dec 20 12:53:33 PM PST 23
Finished Dec 20 12:53:37 PM PST 23
Peak memory 214572 kb
Host smart-382c9b51-caf4-454b-b054-1522e692ebd6
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339085294 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.3339085294
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.203215292
Short name T135
Test name
Test status
Simulation time 102993093 ps
CPU time 0.89 seconds
Started Dec 20 12:53:38 PM PST 23
Finished Dec 20 12:53:43 PM PST 23
Peak memory 214588 kb
Host smart-671c06ca-376f-4238-a145-33dfb12884b8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203215292 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_di
sable_auto_req_mode.203215292
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.2711306640
Short name T505
Test name
Test status
Simulation time 25319643 ps
CPU time 0.96 seconds
Started Dec 20 12:53:35 PM PST 23
Finished Dec 20 12:53:39 PM PST 23
Peak memory 215856 kb
Host smart-4d4f14c1-f481-4c60-baca-a2cdafb7bc7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711306640 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.2711306640
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.3831298519
Short name T677
Test name
Test status
Simulation time 116080081 ps
CPU time 1.03 seconds
Started Dec 20 12:53:36 PM PST 23
Finished Dec 20 12:53:41 PM PST 23
Peak memory 205816 kb
Host smart-890c26af-eda6-460a-96ba-f02360850fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831298519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3831298519
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.2121230052
Short name T112
Test name
Test status
Simulation time 24545224 ps
CPU time 0.86 seconds
Started Dec 20 12:53:40 PM PST 23
Finished Dec 20 12:53:46 PM PST 23
Peak memory 214320 kb
Host smart-7cd2674c-0639-452f-8ad5-bb185d45a925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121230052 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.2121230052
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.3511830478
Short name T649
Test name
Test status
Simulation time 12656789 ps
CPU time 0.84 seconds
Started Dec 20 12:53:40 PM PST 23
Finished Dec 20 12:53:46 PM PST 23
Peak memory 204920 kb
Host smart-1417423c-6c3a-4574-a956-60adb6a8552f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511830478 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.3511830478
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.3736989132
Short name T659
Test name
Test status
Simulation time 150555396 ps
CPU time 1.96 seconds
Started Dec 20 12:53:42 PM PST 23
Finished Dec 20 12:53:50 PM PST 23
Peak memory 206068 kb
Host smart-af8a1178-f76e-4451-be33-4523042916fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736989132 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.3736989132
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.4152781994
Short name T704
Test name
Test status
Simulation time 73638484271 ps
CPU time 1765.64 seconds
Started Dec 20 12:53:37 PM PST 23
Finished Dec 20 01:23:07 PM PST 23
Peak memory 221628 kb
Host smart-7c9c307b-14e2-485d-a0e5-bd06d8904b36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152781994 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.4152781994
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.3739857779
Short name T480
Test name
Test status
Simulation time 72789659 ps
CPU time 1.04 seconds
Started Dec 20 12:55:00 PM PST 23
Finished Dec 20 12:55:22 PM PST 23
Peak memory 205416 kb
Host smart-a5744ceb-78cb-4dfb-80b0-cfb9892368d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739857779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.3739857779
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.4164855874
Short name T798
Test name
Test status
Simulation time 52742017 ps
CPU time 0.96 seconds
Started Dec 20 12:55:02 PM PST 23
Finished Dec 20 12:55:25 PM PST 23
Peak memory 205000 kb
Host smart-459d6a39-3414-4bc5-89e7-94a8265f34a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164855874 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.4164855874
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.911195809
Short name T867
Test name
Test status
Simulation time 16623975 ps
CPU time 0.94 seconds
Started Dec 20 12:54:51 PM PST 23
Finished Dec 20 12:55:10 PM PST 23
Peak memory 205292 kb
Host smart-1bcdf24f-94d6-446b-b51d-ab473c4f402f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911195809 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.911195809
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.2616909514
Short name T562
Test name
Test status
Simulation time 213611653 ps
CPU time 2.8 seconds
Started Dec 20 12:54:57 PM PST 23
Finished Dec 20 12:55:19 PM PST 23
Peak memory 214060 kb
Host smart-9196d629-7771-4749-8d1f-bd4032afd019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616909514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.2616909514
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.279734495
Short name T617
Test name
Test status
Simulation time 96126010 ps
CPU time 1.19 seconds
Started Dec 20 12:54:55 PM PST 23
Finished Dec 20 12:55:14 PM PST 23
Peak memory 214036 kb
Host smart-b8f55556-218b-464b-8f04-8d6281197b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279734495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.279734495
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.11482020
Short name T623
Test name
Test status
Simulation time 37286687 ps
CPU time 0.89 seconds
Started Dec 20 12:55:01 PM PST 23
Finished Dec 20 12:55:23 PM PST 23
Peak memory 205328 kb
Host smart-6963ebea-f076-4f8e-8bd5-53185b9e8bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11482020 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.11482020
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.3950974497
Short name T750
Test name
Test status
Simulation time 19087999 ps
CPU time 1.03 seconds
Started Dec 20 12:54:56 PM PST 23
Finished Dec 20 12:55:14 PM PST 23
Peak memory 205420 kb
Host smart-c244ac7f-6771-455f-bad2-35f5a990d7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950974497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.3950974497
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.741932169
Short name T744
Test name
Test status
Simulation time 56819474 ps
CPU time 0.91 seconds
Started Dec 20 12:54:54 PM PST 23
Finished Dec 20 12:55:13 PM PST 23
Peak memory 205164 kb
Host smart-61b4f767-5b9a-4f97-8604-a726445434b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741932169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.741932169
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.1577036495
Short name T300
Test name
Test status
Simulation time 35981755 ps
CPU time 1.02 seconds
Started Dec 20 12:54:51 PM PST 23
Finished Dec 20 12:55:10 PM PST 23
Peak memory 205852 kb
Host smart-53f5624c-e84c-4ed0-8736-ce55130f42bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577036495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.1577036495
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.184533931
Short name T261
Test name
Test status
Simulation time 138386602 ps
CPU time 2.96 seconds
Started Dec 20 12:54:57 PM PST 23
Finished Dec 20 12:55:19 PM PST 23
Peak memory 214072 kb
Host smart-1153279e-a9e2-4db3-8a48-94135b5b393d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184533931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.184533931
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.1883890488
Short name T685
Test name
Test status
Simulation time 180968540 ps
CPU time 0.99 seconds
Started Dec 20 12:53:42 PM PST 23
Finished Dec 20 12:53:49 PM PST 23
Peak memory 205996 kb
Host smart-118923d6-f754-424f-aa87-14025952b7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883890488 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.1883890488
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.1584927469
Short name T525
Test name
Test status
Simulation time 24859348 ps
CPU time 0.91 seconds
Started Dec 20 12:53:42 PM PST 23
Finished Dec 20 12:53:48 PM PST 23
Peak memory 204672 kb
Host smart-db18814e-3dfe-4f7b-bd05-4e7564c755ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584927469 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.1584927469
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.2928293328
Short name T581
Test name
Test status
Simulation time 14576304 ps
CPU time 0.82 seconds
Started Dec 20 12:53:39 PM PST 23
Finished Dec 20 12:53:44 PM PST 23
Peak memory 214424 kb
Host smart-b800820d-725a-467e-a3a4-9304f0a94736
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928293328 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.2928293328
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_err.3087769373
Short name T801
Test name
Test status
Simulation time 104911266 ps
CPU time 0.9 seconds
Started Dec 20 12:53:39 PM PST 23
Finished Dec 20 12:53:44 PM PST 23
Peak memory 215912 kb
Host smart-1e73a5b9-1726-4fc4-9a50-6647397b2a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087769373 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.3087769373
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.1661757714
Short name T33
Test name
Test status
Simulation time 22016808 ps
CPU time 1.09 seconds
Started Dec 20 12:53:39 PM PST 23
Finished Dec 20 12:53:44 PM PST 23
Peak memory 205472 kb
Host smart-8a63662a-df23-42e7-bc50-8723b760b197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661757714 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.1661757714
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.1151742202
Short name T746
Test name
Test status
Simulation time 31050275 ps
CPU time 0.96 seconds
Started Dec 20 12:53:36 PM PST 23
Finished Dec 20 12:53:41 PM PST 23
Peak memory 214176 kb
Host smart-1580fdee-08d8-4d65-8db2-e824eff69c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151742202 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.1151742202
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.1400254710
Short name T776
Test name
Test status
Simulation time 36605302 ps
CPU time 0.82 seconds
Started Dec 20 12:53:39 PM PST 23
Finished Dec 20 12:53:44 PM PST 23
Peak memory 204816 kb
Host smart-3197ba65-3d58-4153-9c55-98d964a85caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400254710 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.1400254710
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.3386699399
Short name T597
Test name
Test status
Simulation time 59156047 ps
CPU time 1.66 seconds
Started Dec 20 12:53:38 PM PST 23
Finished Dec 20 12:53:44 PM PST 23
Peak memory 205720 kb
Host smart-15ce233a-7b28-485c-ae95-33ecee89a5ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386699399 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3386699399
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.2638163937
Short name T605
Test name
Test status
Simulation time 72157671827 ps
CPU time 801.1 seconds
Started Dec 20 12:53:37 PM PST 23
Finished Dec 20 01:07:02 PM PST 23
Peak memory 215232 kb
Host smart-d05876cc-738c-4237-9a60-6aa1f9fa71aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638163937 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.2638163937
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.1418042104
Short name T939
Test name
Test status
Simulation time 25988200 ps
CPU time 0.86 seconds
Started Dec 20 12:55:02 PM PST 23
Finished Dec 20 12:55:24 PM PST 23
Peak memory 204744 kb
Host smart-84d53a8e-df9a-4874-b2b9-b0279e28da40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418042104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.1418042104
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.4108717932
Short name T733
Test name
Test status
Simulation time 18739447 ps
CPU time 1.06 seconds
Started Dec 20 12:55:02 PM PST 23
Finished Dec 20 12:55:24 PM PST 23
Peak memory 205220 kb
Host smart-c9214214-af00-458d-a9c5-fb608f2f267e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108717932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.4108717932
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.2251598480
Short name T280
Test name
Test status
Simulation time 283580169 ps
CPU time 3.51 seconds
Started Dec 20 12:55:00 PM PST 23
Finished Dec 20 12:55:24 PM PST 23
Peak memory 214112 kb
Host smart-8445188c-dec8-4edb-8122-b0528c990666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251598480 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.2251598480
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.1082727324
Short name T266
Test name
Test status
Simulation time 45016472 ps
CPU time 0.99 seconds
Started Dec 20 12:54:55 PM PST 23
Finished Dec 20 12:55:14 PM PST 23
Peak memory 204972 kb
Host smart-ed5e9ebb-b5f4-4687-9f9c-ee0e8d0f732f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082727324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.1082727324
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.3600942145
Short name T259
Test name
Test status
Simulation time 51455771 ps
CPU time 0.93 seconds
Started Dec 20 12:55:00 PM PST 23
Finished Dec 20 12:55:21 PM PST 23
Peak memory 205064 kb
Host smart-e66c5bdc-d092-47ce-9bc5-62b89f5a87c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600942145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.3600942145
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.571376154
Short name T699
Test name
Test status
Simulation time 63984978 ps
CPU time 1.09 seconds
Started Dec 20 12:54:59 PM PST 23
Finished Dec 20 12:55:21 PM PST 23
Peak memory 214208 kb
Host smart-91773046-7f60-4d8a-b3ec-bd62eb1ff2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571376154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.571376154
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.3944463851
Short name T729
Test name
Test status
Simulation time 52254479 ps
CPU time 0.91 seconds
Started Dec 20 12:54:54 PM PST 23
Finished Dec 20 12:55:13 PM PST 23
Peak memory 205084 kb
Host smart-08c1b478-bf2c-430e-affb-d559fdf30e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944463851 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.3944463851
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.1423213520
Short name T739
Test name
Test status
Simulation time 282534194 ps
CPU time 4.24 seconds
Started Dec 20 12:55:00 PM PST 23
Finished Dec 20 12:55:25 PM PST 23
Peak memory 214216 kb
Host smart-31a2b54f-76aa-4f6d-b214-0400fd1824e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423213520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.1423213520
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1571327839
Short name T568
Test name
Test status
Simulation time 31255021 ps
CPU time 0.92 seconds
Started Dec 20 12:54:54 PM PST 23
Finished Dec 20 12:55:13 PM PST 23
Peak memory 205204 kb
Host smart-77c15e96-5a18-4c4f-bcf6-1e03ca3026f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571327839 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1571327839
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.3018764932
Short name T957
Test name
Test status
Simulation time 88143183 ps
CPU time 1.15 seconds
Started Dec 20 12:54:55 PM PST 23
Finished Dec 20 12:55:14 PM PST 23
Peak memory 213540 kb
Host smart-e03fbcee-725f-4dfa-8f67-776c4215d7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018764932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.3018764932
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.1674817141
Short name T308
Test name
Test status
Simulation time 19874632 ps
CPU time 0.97 seconds
Started Dec 20 12:53:38 PM PST 23
Finished Dec 20 12:53:43 PM PST 23
Peak memory 206104 kb
Host smart-8b15a771-2c06-40fb-aa3a-09a7ae4b46fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674817141 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.1674817141
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.1506417255
Short name T99
Test name
Test status
Simulation time 16850766 ps
CPU time 0.91 seconds
Started Dec 20 12:53:40 PM PST 23
Finished Dec 20 12:53:45 PM PST 23
Peak memory 205236 kb
Host smart-3d720e9d-e53a-45b0-bbc9-a20001dab5c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506417255 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1506417255
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.790193271
Short name T160
Test name
Test status
Simulation time 26486517 ps
CPU time 0.78 seconds
Started Dec 20 12:53:40 PM PST 23
Finished Dec 20 12:53:45 PM PST 23
Peak memory 214476 kb
Host smart-68f1144b-1e55-46f6-8d2c-3eb6ada6bd20
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790193271 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.790193271
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.711444071
Short name T778
Test name
Test status
Simulation time 63205742 ps
CPU time 0.97 seconds
Started Dec 20 12:53:40 PM PST 23
Finished Dec 20 12:53:46 PM PST 23
Peak memory 214676 kb
Host smart-d01f2be8-5a94-4e63-9130-68a0f2ab8334
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711444071 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_di
sable_auto_req_mode.711444071
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.3079878013
Short name T46
Test name
Test status
Simulation time 44810862 ps
CPU time 0.87 seconds
Started Dec 20 12:53:40 PM PST 23
Finished Dec 20 12:53:45 PM PST 23
Peak memory 221380 kb
Host smart-3ef7a37f-f044-488c-9e1a-1866791e2c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079878013 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.3079878013
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.1627015790
Short name T648
Test name
Test status
Simulation time 32280303 ps
CPU time 0.97 seconds
Started Dec 20 12:53:40 PM PST 23
Finished Dec 20 12:53:46 PM PST 23
Peak memory 205196 kb
Host smart-709554db-02d1-452a-b860-b0ed37f0e0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627015790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.1627015790
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.3597810576
Short name T542
Test name
Test status
Simulation time 23511543 ps
CPU time 1.04 seconds
Started Dec 20 12:53:40 PM PST 23
Finished Dec 20 12:53:46 PM PST 23
Peak memory 221736 kb
Host smart-1a0bdf93-4de6-4b5c-8abc-13b0ad9d7173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597810576 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.3597810576
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.4049761846
Short name T946
Test name
Test status
Simulation time 40580877 ps
CPU time 0.79 seconds
Started Dec 20 12:53:39 PM PST 23
Finished Dec 20 12:53:44 PM PST 23
Peak memory 204792 kb
Host smart-bf74fa9d-e98f-41af-86e1-7503c22adfce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049761846 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.4049761846
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.2552638832
Short name T255
Test name
Test status
Simulation time 174495165 ps
CPU time 3.98 seconds
Started Dec 20 12:53:38 PM PST 23
Finished Dec 20 12:53:47 PM PST 23
Peak memory 206076 kb
Host smart-877f5b4e-1fa9-4c9c-89f6-a0542f1fd412
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552638832 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.2552638832
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/270.edn_genbits.3400265310
Short name T906
Test name
Test status
Simulation time 85072637 ps
CPU time 1.21 seconds
Started Dec 20 12:55:01 PM PST 23
Finished Dec 20 12:55:23 PM PST 23
Peak memory 214256 kb
Host smart-5ef0c00e-3325-492a-a979-1caade19a8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400265310 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.3400265310
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.1624898234
Short name T687
Test name
Test status
Simulation time 231009387 ps
CPU time 3.51 seconds
Started Dec 20 12:55:00 PM PST 23
Finished Dec 20 12:55:24 PM PST 23
Peak memory 214112 kb
Host smart-b9dea12c-965d-4b60-b694-7d08f602bd1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624898234 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.1624898234
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.3255286505
Short name T595
Test name
Test status
Simulation time 53114223 ps
CPU time 1.01 seconds
Started Dec 20 12:55:00 PM PST 23
Finished Dec 20 12:55:22 PM PST 23
Peak memory 214364 kb
Host smart-3fceb452-9860-4811-8dd7-b43362a933c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255286505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.3255286505
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.1855238591
Short name T954
Test name
Test status
Simulation time 653729081 ps
CPU time 5.49 seconds
Started Dec 20 12:54:57 PM PST 23
Finished Dec 20 12:55:22 PM PST 23
Peak memory 214244 kb
Host smart-75f4bc2e-89fc-4394-9a75-d8ccb7912a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855238591 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.1855238591
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.992980833
Short name T721
Test name
Test status
Simulation time 70455848 ps
CPU time 1.01 seconds
Started Dec 20 12:55:00 PM PST 23
Finished Dec 20 12:55:21 PM PST 23
Peak memory 205304 kb
Host smart-88bace39-79bf-4a56-85e4-5b8c2f89a48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992980833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.992980833
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.373292640
Short name T269
Test name
Test status
Simulation time 36529284 ps
CPU time 1.1 seconds
Started Dec 20 12:54:58 PM PST 23
Finished Dec 20 12:55:18 PM PST 23
Peak memory 214208 kb
Host smart-6dbb5736-d997-4712-b979-01adb0cd0381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373292640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.373292640
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.1534497372
Short name T565
Test name
Test status
Simulation time 54637291 ps
CPU time 1.12 seconds
Started Dec 20 12:54:57 PM PST 23
Finished Dec 20 12:55:18 PM PST 23
Peak memory 214288 kb
Host smart-7850a07e-3f8d-4067-8357-148c786be7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534497372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.1534497372
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.2931657776
Short name T813
Test name
Test status
Simulation time 23937040 ps
CPU time 0.88 seconds
Started Dec 20 12:54:55 PM PST 23
Finished Dec 20 12:55:13 PM PST 23
Peak memory 205044 kb
Host smart-4a854897-6c87-49e5-b0e4-34ee0eff797c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931657776 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.2931657776
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.3954677733
Short name T579
Test name
Test status
Simulation time 371904469 ps
CPU time 3.09 seconds
Started Dec 20 12:54:57 PM PST 23
Finished Dec 20 12:55:20 PM PST 23
Peak memory 214096 kb
Host smart-1a4fe9b8-5098-4223-9dff-029a16bb900b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954677733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3954677733
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.2137175559
Short name T502
Test name
Test status
Simulation time 21622578 ps
CPU time 1.09 seconds
Started Dec 20 12:55:00 PM PST 23
Finished Dec 20 12:55:22 PM PST 23
Peak memory 205792 kb
Host smart-4e6438b5-6990-4ea9-ba5b-577316860cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137175559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.2137175559
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.1316097331
Short name T903
Test name
Test status
Simulation time 233435946 ps
CPU time 0.89 seconds
Started Dec 20 12:53:43 PM PST 23
Finished Dec 20 12:53:50 PM PST 23
Peak memory 205304 kb
Host smart-c6333b75-202f-4dca-a706-095539447bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316097331 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.1316097331
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.197647213
Short name T463
Test name
Test status
Simulation time 21905912 ps
CPU time 0.91 seconds
Started Dec 20 12:53:47 PM PST 23
Finished Dec 20 12:53:54 PM PST 23
Peak memory 204536 kb
Host smart-67885687-4f2f-404e-bb9a-4066096815fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197647213 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.197647213
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.3795732430
Short name T810
Test name
Test status
Simulation time 17242270 ps
CPU time 0.78 seconds
Started Dec 20 12:53:47 PM PST 23
Finished Dec 20 12:53:53 PM PST 23
Peak memory 214376 kb
Host smart-c31bd0c2-5711-4e4e-88f1-dd9129d63f1e
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795732430 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.3795732430
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_err.3227835153
Short name T690
Test name
Test status
Simulation time 19010765 ps
CPU time 1.08 seconds
Started Dec 20 12:53:41 PM PST 23
Finished Dec 20 12:53:47 PM PST 23
Peak memory 214320 kb
Host smart-39c614e3-139a-4afc-bc78-6cada2fa674c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227835153 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.3227835153
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.3768673933
Short name T258
Test name
Test status
Simulation time 15904651 ps
CPU time 0.95 seconds
Started Dec 20 12:53:46 PM PST 23
Finished Dec 20 12:53:53 PM PST 23
Peak memory 205256 kb
Host smart-ad660e56-6d88-404e-a7bb-8d8838628e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768673933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.3768673933
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.4091948239
Short name T630
Test name
Test status
Simulation time 22410409 ps
CPU time 0.98 seconds
Started Dec 20 12:53:47 PM PST 23
Finished Dec 20 12:53:54 PM PST 23
Peak memory 225752 kb
Host smart-ec30ac2d-52c2-45ad-b70a-ed2d293602da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091948239 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.4091948239
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.857659679
Short name T628
Test name
Test status
Simulation time 11945848 ps
CPU time 0.91 seconds
Started Dec 20 12:53:38 PM PST 23
Finished Dec 20 12:53:44 PM PST 23
Peak memory 204748 kb
Host smart-a8e610df-5ba2-4839-9355-3ccaba5b8fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857659679 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.857659679
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.459943357
Short name T700
Test name
Test status
Simulation time 559108167 ps
CPU time 2.97 seconds
Started Dec 20 12:53:47 PM PST 23
Finished Dec 20 12:53:56 PM PST 23
Peak memory 206032 kb
Host smart-59a61b4f-9508-45fb-9d36-bcc541e7b1ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459943357 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.459943357
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.2481185945
Short name T509
Test name
Test status
Simulation time 262250905814 ps
CPU time 1700.09 seconds
Started Dec 20 12:53:40 PM PST 23
Finished Dec 20 01:22:06 PM PST 23
Peak memory 221132 kb
Host smart-1f9b0abd-71ba-4c13-b31f-8a9f7304269d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481185945 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.2481185945
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.178212664
Short name T485
Test name
Test status
Simulation time 19228527 ps
CPU time 1.02 seconds
Started Dec 20 12:54:55 PM PST 23
Finished Dec 20 12:55:14 PM PST 23
Peak memory 205104 kb
Host smart-18bd4e18-316a-425d-9de9-58d5609bbc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178212664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.178212664
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.760495257
Short name T949
Test name
Test status
Simulation time 112272657 ps
CPU time 1.86 seconds
Started Dec 20 12:54:55 PM PST 23
Finished Dec 20 12:55:23 PM PST 23
Peak memory 214136 kb
Host smart-5309f887-e0e7-4520-a143-06a0720ce913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760495257 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.760495257
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.2914632974
Short name T761
Test name
Test status
Simulation time 97830532 ps
CPU time 1.02 seconds
Started Dec 20 12:55:06 PM PST 23
Finished Dec 20 12:55:28 PM PST 23
Peak memory 205096 kb
Host smart-e0cdafde-ad1d-4baf-8f38-4196d5a62884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914632974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.2914632974
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.4011661726
Short name T966
Test name
Test status
Simulation time 68700737 ps
CPU time 1 seconds
Started Dec 20 12:54:57 PM PST 23
Finished Dec 20 12:55:18 PM PST 23
Peak memory 205516 kb
Host smart-cf4eec56-416b-461d-ae9c-f094b8d1a224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011661726 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.4011661726
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.1471942445
Short name T296
Test name
Test status
Simulation time 87836491 ps
CPU time 0.95 seconds
Started Dec 20 12:55:01 PM PST 23
Finished Dec 20 12:55:24 PM PST 23
Peak memory 205404 kb
Host smart-cabe38ca-beb5-4748-aa4a-8fe486b6b92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471942445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.1471942445
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.1624866181
Short name T275
Test name
Test status
Simulation time 33994248 ps
CPU time 1.08 seconds
Started Dec 20 12:55:02 PM PST 23
Finished Dec 20 12:55:25 PM PST 23
Peak memory 214300 kb
Host smart-bbea6143-6ee3-4f34-89ea-47c64b787ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624866181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.1624866181
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.3751524311
Short name T58
Test name
Test status
Simulation time 49382116 ps
CPU time 1.17 seconds
Started Dec 20 12:55:00 PM PST 23
Finished Dec 20 12:55:22 PM PST 23
Peak memory 205512 kb
Host smart-e7256bde-5558-4e9e-9ced-e2ec2a35e155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751524311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.3751524311
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.2695187349
Short name T474
Test name
Test status
Simulation time 27568358 ps
CPU time 0.93 seconds
Started Dec 20 12:55:04 PM PST 23
Finished Dec 20 12:55:27 PM PST 23
Peak memory 205052 kb
Host smart-0c4dfb6a-13cf-4eaf-8375-07c6f7ce8d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695187349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.2695187349
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.2579924985
Short name T722
Test name
Test status
Simulation time 20395428 ps
CPU time 1.02 seconds
Started Dec 20 12:53:43 PM PST 23
Finished Dec 20 12:53:51 PM PST 23
Peak memory 205352 kb
Host smart-1fd2d42d-3f32-40e6-8f44-14a5fecf3443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579924985 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.2579924985
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.168837244
Short name T73
Test name
Test status
Simulation time 68609001 ps
CPU time 0.8 seconds
Started Dec 20 12:53:47 PM PST 23
Finished Dec 20 12:53:54 PM PST 23
Peak memory 204296 kb
Host smart-69f2bb87-100a-4535-8f72-c2665b7dd793
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168837244 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.168837244
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.507096565
Short name T972
Test name
Test status
Simulation time 53538313 ps
CPU time 0.89 seconds
Started Dec 20 12:53:46 PM PST 23
Finished Dec 20 12:53:52 PM PST 23
Peak memory 214612 kb
Host smart-9ecd1458-7743-4218-a605-12d755fa0779
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507096565 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_di
sable_auto_req_mode.507096565
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.855537643
Short name T817
Test name
Test status
Simulation time 69221155 ps
CPU time 1.03 seconds
Started Dec 20 12:53:42 PM PST 23
Finished Dec 20 12:53:49 PM PST 23
Peak memory 214836 kb
Host smart-de4a0ffc-0d7f-4d44-88c3-84a29f4ff547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855537643 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.855537643
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.660583679
Short name T959
Test name
Test status
Simulation time 16130874 ps
CPU time 0.93 seconds
Started Dec 20 12:53:47 PM PST 23
Finished Dec 20 12:53:55 PM PST 23
Peak memory 204964 kb
Host smart-a845c472-d9ae-4c83-becf-133d96b70765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660583679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.660583679
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.2582710442
Short name T476
Test name
Test status
Simulation time 28070343 ps
CPU time 0.83 seconds
Started Dec 20 12:53:44 PM PST 23
Finished Dec 20 12:53:51 PM PST 23
Peak memory 214156 kb
Host smart-38627df8-9741-4047-8ee1-6a158ace2f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582710442 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.2582710442
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.1687794727
Short name T680
Test name
Test status
Simulation time 22410200 ps
CPU time 0.79 seconds
Started Dec 20 12:53:42 PM PST 23
Finished Dec 20 12:53:49 PM PST 23
Peak memory 204728 kb
Host smart-d51da238-1dfa-401a-ace9-e3f5a13795f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687794727 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.1687794727
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.3011639215
Short name T960
Test name
Test status
Simulation time 678605599 ps
CPU time 3.45 seconds
Started Dec 20 12:53:42 PM PST 23
Finished Dec 20 12:53:51 PM PST 23
Peak memory 205912 kb
Host smart-e612505f-b10d-4358-9e23-bfb682004293
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011639215 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.3011639215
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.1057945959
Short name T619
Test name
Test status
Simulation time 57837526138 ps
CPU time 1360.07 seconds
Started Dec 20 12:53:46 PM PST 23
Finished Dec 20 01:16:32 PM PST 23
Peak memory 217232 kb
Host smart-0f24184a-5f6b-49ba-9dce-6ec2dd65f426
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057945959 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.1057945959
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/291.edn_genbits.2455104897
Short name T627
Test name
Test status
Simulation time 165273130 ps
CPU time 1 seconds
Started Dec 20 12:55:00 PM PST 23
Finished Dec 20 12:55:22 PM PST 23
Peak memory 205704 kb
Host smart-e1b41e29-fbe0-4266-874a-90245bd8b5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455104897 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.2455104897
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.3830366432
Short name T850
Test name
Test status
Simulation time 41610806 ps
CPU time 1.09 seconds
Started Dec 20 12:55:00 PM PST 23
Finished Dec 20 12:55:22 PM PST 23
Peak memory 205604 kb
Host smart-1ec9b61b-2b26-4cd5-b1bb-2f9e004b4186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830366432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.3830366432
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.2305255331
Short name T267
Test name
Test status
Simulation time 22596678 ps
CPU time 1.2 seconds
Started Dec 20 12:55:12 PM PST 23
Finished Dec 20 12:55:31 PM PST 23
Peak memory 214224 kb
Host smart-04fed8d9-f3e5-4e37-8ce7-fab12400857b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305255331 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2305255331
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.1342662687
Short name T849
Test name
Test status
Simulation time 19398401 ps
CPU time 0.97 seconds
Started Dec 20 12:55:00 PM PST 23
Finished Dec 20 12:55:21 PM PST 23
Peak memory 205208 kb
Host smart-ac6d86ab-0d03-43b0-95e7-f592eccc082f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342662687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.1342662687
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.1039735077
Short name T641
Test name
Test status
Simulation time 17840050 ps
CPU time 1.01 seconds
Started Dec 20 12:55:14 PM PST 23
Finished Dec 20 12:55:32 PM PST 23
Peak memory 213988 kb
Host smart-ae974374-b179-4b13-9f80-7b9ac3877edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039735077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.1039735077
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.568415559
Short name T563
Test name
Test status
Simulation time 50045315 ps
CPU time 1.21 seconds
Started Dec 20 12:55:06 PM PST 23
Finished Dec 20 12:55:29 PM PST 23
Peak memory 213988 kb
Host smart-5ca98eb7-36ca-4d67-8257-50496db0ffce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568415559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.568415559
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.3013699054
Short name T794
Test name
Test status
Simulation time 17002101 ps
CPU time 1 seconds
Started Dec 20 12:55:02 PM PST 23
Finished Dec 20 12:55:25 PM PST 23
Peak memory 205384 kb
Host smart-ca533491-429c-43b1-b155-c81a736ec0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013699054 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.3013699054
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.3205209032
Short name T36
Test name
Test status
Simulation time 29560583 ps
CPU time 1 seconds
Started Dec 20 12:55:15 PM PST 23
Finished Dec 20 12:55:33 PM PST 23
Peak memory 204916 kb
Host smart-33a16487-679d-4f25-af86-2ad0c4875f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205209032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.3205209032
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.3796542890
Short name T698
Test name
Test status
Simulation time 23803734 ps
CPU time 1.11 seconds
Started Dec 20 12:55:23 PM PST 23
Finished Dec 20 12:55:38 PM PST 23
Peak memory 205316 kb
Host smart-297cc98c-f0b6-4668-9b7f-dccffaec985c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796542890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.3796542890
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.3931332291
Short name T314
Test name
Test status
Simulation time 31595190 ps
CPU time 0.91 seconds
Started Dec 20 12:52:11 PM PST 23
Finished Dec 20 12:52:31 PM PST 23
Peak memory 206036 kb
Host smart-def2d6f5-5db2-4efc-bd89-7982f09ff184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931332291 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.3931332291
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.2098343181
Short name T601
Test name
Test status
Simulation time 29049719 ps
CPU time 0.87 seconds
Started Dec 20 12:52:08 PM PST 23
Finished Dec 20 12:52:27 PM PST 23
Peak memory 204648 kb
Host smart-7be33a31-d7a2-40f1-b07c-ac7e5419f979
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098343181 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.2098343181
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.1492492101
Short name T102
Test name
Test status
Simulation time 18771413 ps
CPU time 0.86 seconds
Started Dec 20 12:52:08 PM PST 23
Finished Dec 20 12:52:28 PM PST 23
Peak memory 214408 kb
Host smart-ef6ab60b-1a22-4072-97aa-6ff5d989c757
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492492101 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.1492492101
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.95052551
Short name T756
Test name
Test status
Simulation time 54342282 ps
CPU time 1.01 seconds
Started Dec 20 12:52:05 PM PST 23
Finished Dec 20 12:52:24 PM PST 23
Peak memory 214608 kb
Host smart-6a7163ed-9c2a-4b05-934d-d078db9ec23f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95052551 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disa
ble_auto_req_mode.95052551
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.1585312016
Short name T302
Test name
Test status
Simulation time 24420858 ps
CPU time 1.1 seconds
Started Dec 20 12:52:07 PM PST 23
Finished Dec 20 12:52:26 PM PST 23
Peak memory 215964 kb
Host smart-0f4fa015-627f-4966-b2c5-ff62df2c9b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585312016 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.1585312016
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.3504089351
Short name T63
Test name
Test status
Simulation time 19797355 ps
CPU time 0.97 seconds
Started Dec 20 12:52:06 PM PST 23
Finished Dec 20 12:52:25 PM PST 23
Peak memory 205280 kb
Host smart-789f5153-af08-43f8-95d6-ef590f90d209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504089351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.3504089351
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.709973710
Short name T90
Test name
Test status
Simulation time 20930467 ps
CPU time 0.89 seconds
Started Dec 20 12:52:08 PM PST 23
Finished Dec 20 12:52:28 PM PST 23
Peak memory 214560 kb
Host smart-40a0bec7-3e30-4d5a-bb9e-89bed4e8c235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709973710 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.709973710
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.1076058429
Short name T304
Test name
Test status
Simulation time 33203324 ps
CPU time 0.87 seconds
Started Dec 20 12:52:11 PM PST 23
Finished Dec 20 12:52:31 PM PST 23
Peak memory 204760 kb
Host smart-df0c226d-c3cd-4448-b96d-0a874202be64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076058429 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.1076058429
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_smoke.2817260983
Short name T724
Test name
Test status
Simulation time 39045135 ps
CPU time 0.8 seconds
Started Dec 20 12:52:01 PM PST 23
Finished Dec 20 12:52:18 PM PST 23
Peak memory 204768 kb
Host smart-5a6d8e3d-f691-4f93-b579-3392420b186a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817260983 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.2817260983
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.4101241253
Short name T528
Test name
Test status
Simulation time 332660621 ps
CPU time 2.14 seconds
Started Dec 20 12:51:59 PM PST 23
Finished Dec 20 12:52:16 PM PST 23
Peak memory 205644 kb
Host smart-40525097-7229-4974-a1a2-e53e2512fa1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101241253 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.4101241253
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3665900834
Short name T286
Test name
Test status
Simulation time 77133955547 ps
CPU time 437.75 seconds
Started Dec 20 12:52:00 PM PST 23
Finished Dec 20 12:59:34 PM PST 23
Peak memory 215468 kb
Host smart-7c641047-dd05-4df7-b6ab-ad87af108cf8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665900834 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3665900834
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.2531186115
Short name T233
Test name
Test status
Simulation time 81051085 ps
CPU time 0.96 seconds
Started Dec 20 12:53:39 PM PST 23
Finished Dec 20 12:53:44 PM PST 23
Peak memory 205996 kb
Host smart-1c40c939-4c17-437d-8498-68dfc80d471b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531186115 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.2531186115
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.4287980061
Short name T689
Test name
Test status
Simulation time 24523242 ps
CPU time 0.86 seconds
Started Dec 20 12:53:41 PM PST 23
Finished Dec 20 12:53:46 PM PST 23
Peak memory 204784 kb
Host smart-449ac4fb-d3fb-40cf-a95d-ff9a8ac08e21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287980061 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.4287980061
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.3769666893
Short name T120
Test name
Test status
Simulation time 24990772 ps
CPU time 0.82 seconds
Started Dec 20 12:53:40 PM PST 23
Finished Dec 20 12:53:45 PM PST 23
Peak memory 214432 kb
Host smart-05475af1-045e-43cd-b25e-ff222f3259eb
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769666893 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.3769666893
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.2683671471
Short name T104
Test name
Test status
Simulation time 35731780 ps
CPU time 0.9 seconds
Started Dec 20 12:53:37 PM PST 23
Finished Dec 20 12:53:42 PM PST 23
Peak memory 214476 kb
Host smart-05b0322f-d2bd-44c2-807e-5488a3435242
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683671471 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.2683671471
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.541754065
Short name T765
Test name
Test status
Simulation time 20555931 ps
CPU time 0.89 seconds
Started Dec 20 12:53:51 PM PST 23
Finished Dec 20 12:53:59 PM PST 23
Peak memory 215640 kb
Host smart-6a4d72bf-29aa-4886-ba76-c7ff4cd778f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541754065 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.541754065
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.2337748768
Short name T294
Test name
Test status
Simulation time 28487974 ps
CPU time 0.98 seconds
Started Dec 20 12:53:52 PM PST 23
Finished Dec 20 12:54:00 PM PST 23
Peak memory 205244 kb
Host smart-6f87202f-e6b6-4e77-bb03-f8909e119205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337748768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.2337748768
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.1680991462
Short name T807
Test name
Test status
Simulation time 20315638 ps
CPU time 0.98 seconds
Started Dec 20 12:53:44 PM PST 23
Finished Dec 20 12:53:51 PM PST 23
Peak memory 214360 kb
Host smart-bc51c0b0-5e4f-4156-82ff-ed93d7caced9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680991462 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.1680991462
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.1023906790
Short name T572
Test name
Test status
Simulation time 14991303 ps
CPU time 0.87 seconds
Started Dec 20 12:53:47 PM PST 23
Finished Dec 20 12:53:54 PM PST 23
Peak memory 204992 kb
Host smart-6d08efd0-047e-4131-aba1-a57bf71252cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023906790 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.1023906790
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.1014059160
Short name T674
Test name
Test status
Simulation time 42396775 ps
CPU time 0.93 seconds
Started Dec 20 12:53:51 PM PST 23
Finished Dec 20 12:53:59 PM PST 23
Peak memory 204396 kb
Host smart-b35d0980-53a0-49ef-aa48-d7e17a846fd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014059160 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.1014059160
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2516270760
Short name T812
Test name
Test status
Simulation time 319707664293 ps
CPU time 1979.43 seconds
Started Dec 20 12:53:36 PM PST 23
Finished Dec 20 01:26:38 PM PST 23
Peak memory 223768 kb
Host smart-03a71ca2-b820-4780-99ed-e77fed40e60f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516270760 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.2516270760
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.1699392642
Short name T589
Test name
Test status
Simulation time 87704627 ps
CPU time 0.99 seconds
Started Dec 20 12:53:40 PM PST 23
Finished Dec 20 12:53:46 PM PST 23
Peak memory 205388 kb
Host smart-d53a1101-aa9a-4fb4-b4bf-87be44566086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699392642 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.1699392642
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.3462898938
Short name T645
Test name
Test status
Simulation time 28916485 ps
CPU time 0.76 seconds
Started Dec 20 12:53:38 PM PST 23
Finished Dec 20 12:53:42 PM PST 23
Peak memory 203948 kb
Host smart-8c09fde3-6b08-45f1-bd41-c7ec34d1f24e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462898938 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.3462898938
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.3904695625
Short name T673
Test name
Test status
Simulation time 75985440 ps
CPU time 0.81 seconds
Started Dec 20 12:53:41 PM PST 23
Finished Dec 20 12:53:47 PM PST 23
Peak memory 214132 kb
Host smart-bc2e4dd9-4552-44f3-ba88-be1f97b25936
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904695625 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.3904695625
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.2926930831
Short name T110
Test name
Test status
Simulation time 51667956 ps
CPU time 1.01 seconds
Started Dec 20 12:53:35 PM PST 23
Finished Dec 20 12:53:39 PM PST 23
Peak memory 214608 kb
Host smart-d2a39185-fb8a-40f1-b46e-652c624625d1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926930831 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.2926930831
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.1384272606
Short name T608
Test name
Test status
Simulation time 47752336 ps
CPU time 0.94 seconds
Started Dec 20 12:53:37 PM PST 23
Finished Dec 20 12:53:42 PM PST 23
Peak memory 215852 kb
Host smart-ef0df527-70f5-41de-b32d-618716ca4cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384272606 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.1384272606
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.132460751
Short name T500
Test name
Test status
Simulation time 15402502 ps
CPU time 1 seconds
Started Dec 20 12:53:35 PM PST 23
Finished Dec 20 12:53:39 PM PST 23
Peak memory 214228 kb
Host smart-1f45aa8f-34aa-4e8a-a1db-c32c80664a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132460751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.132460751
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.394334362
Short name T80
Test name
Test status
Simulation time 19974353 ps
CPU time 1.12 seconds
Started Dec 20 12:53:38 PM PST 23
Finished Dec 20 12:53:43 PM PST 23
Peak memory 225752 kb
Host smart-03e39ca2-88e5-419a-8aef-e928e8250e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394334362 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.394334362
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.4208997649
Short name T467
Test name
Test status
Simulation time 46518929 ps
CPU time 0.86 seconds
Started Dec 20 12:53:38 PM PST 23
Finished Dec 20 12:53:43 PM PST 23
Peak memory 204916 kb
Host smart-135839f0-be59-440f-bfa3-dfc35f6b7dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208997649 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.4208997649
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.663938530
Short name T4
Test name
Test status
Simulation time 1248295802 ps
CPU time 2.54 seconds
Started Dec 20 12:53:40 PM PST 23
Finished Dec 20 12:53:47 PM PST 23
Peak memory 205592 kb
Host smart-9a7a8465-1688-47d0-9956-e2ad21a05109
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663938530 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.663938530
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.990037663
Short name T800
Test name
Test status
Simulation time 47175134606 ps
CPU time 1169.75 seconds
Started Dec 20 12:53:38 PM PST 23
Finished Dec 20 01:13:12 PM PST 23
Peak memory 216520 kb
Host smart-ff2abfb4-4fa0-4a11-9def-f74af4afbacc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990037663 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.990037663
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.3069582126
Short name T14
Test name
Test status
Simulation time 19036798 ps
CPU time 0.96 seconds
Started Dec 20 12:53:45 PM PST 23
Finished Dec 20 12:53:51 PM PST 23
Peak memory 206044 kb
Host smart-b88e1fbc-fbd6-4df4-b1f5-d8bd3a6aee22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069582126 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.3069582126
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.896021226
Short name T540
Test name
Test status
Simulation time 12266650 ps
CPU time 0.88 seconds
Started Dec 20 12:53:41 PM PST 23
Finished Dec 20 12:53:48 PM PST 23
Peak memory 204480 kb
Host smart-0d6dd78d-f4a0-4408-b0a3-83a37a0cfe03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896021226 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.896021226
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.4109097673
Short name T665
Test name
Test status
Simulation time 22603072 ps
CPU time 1 seconds
Started Dec 20 12:53:44 PM PST 23
Finished Dec 20 12:53:51 PM PST 23
Peak memory 214576 kb
Host smart-8ce1020b-c69e-4940-9f62-41c59d3ecbd2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109097673 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.4109097673
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.382293473
Short name T131
Test name
Test status
Simulation time 30815805 ps
CPU time 1.07 seconds
Started Dec 20 12:53:46 PM PST 23
Finished Dec 20 12:53:53 PM PST 23
Peak memory 214476 kb
Host smart-7bec32f5-a6cc-45cf-8970-bdb69028b2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382293473 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.382293473
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.2723818559
Short name T943
Test name
Test status
Simulation time 17192844 ps
CPU time 0.97 seconds
Started Dec 20 12:53:46 PM PST 23
Finished Dec 20 12:53:53 PM PST 23
Peak memory 205296 kb
Host smart-e1215576-c012-43d3-8f8a-b664ccbc7bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723818559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.2723818559
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.2948344021
Short name T13
Test name
Test status
Simulation time 20023706 ps
CPU time 1.12 seconds
Started Dec 20 12:53:42 PM PST 23
Finished Dec 20 12:53:49 PM PST 23
Peak memory 221656 kb
Host smart-be0d6f78-a4ef-46e4-b96c-89640d42985c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948344021 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.2948344021
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.3489497924
Short name T604
Test name
Test status
Simulation time 20920788 ps
CPU time 0.79 seconds
Started Dec 20 12:53:44 PM PST 23
Finished Dec 20 12:53:51 PM PST 23
Peak memory 204900 kb
Host smart-762aa00d-7588-4400-87c6-337e5829961d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489497924 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.3489497924
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.27957126
Short name T861
Test name
Test status
Simulation time 2432505147 ps
CPU time 5.09 seconds
Started Dec 20 12:53:42 PM PST 23
Finished Dec 20 12:53:53 PM PST 23
Peak memory 206024 kb
Host smart-6048f651-23cb-46d6-8adc-bf99c1543316
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27957126 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.27957126
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.3150239059
Short name T793
Test name
Test status
Simulation time 245639449650 ps
CPU time 557.04 seconds
Started Dec 20 12:53:41 PM PST 23
Finished Dec 20 01:03:04 PM PST 23
Peak memory 215660 kb
Host smart-93fc4375-4f74-4159-99ea-5561488d1616
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150239059 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.3150239059
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.1851473334
Short name T239
Test name
Test status
Simulation time 17155401 ps
CPU time 0.96 seconds
Started Dec 20 12:53:41 PM PST 23
Finished Dec 20 12:53:48 PM PST 23
Peak memory 206000 kb
Host smart-49b112de-08a5-40ef-bb61-e479b9e7d0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851473334 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.1851473334
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.3290336422
Short name T465
Test name
Test status
Simulation time 14959006 ps
CPU time 0.91 seconds
Started Dec 20 12:53:42 PM PST 23
Finished Dec 20 12:53:49 PM PST 23
Peak memory 204628 kb
Host smart-6fb962c4-18a5-4dc3-8332-34bb8e82b327
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290336422 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.3290336422
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.3869793324
Short name T162
Test name
Test status
Simulation time 13065916 ps
CPU time 0.89 seconds
Started Dec 20 12:53:42 PM PST 23
Finished Dec 20 12:53:49 PM PST 23
Peak memory 214536 kb
Host smart-2ea41baf-a725-4880-bcfd-0d203ba55219
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869793324 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.3869793324
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.2712877330
Short name T149
Test name
Test status
Simulation time 20798158 ps
CPU time 0.95 seconds
Started Dec 20 12:53:47 PM PST 23
Finished Dec 20 12:53:54 PM PST 23
Peak memory 214552 kb
Host smart-f519542b-1525-464d-91e9-e77d1784f0fa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712877330 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.2712877330
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.2770967537
Short name T538
Test name
Test status
Simulation time 21416329 ps
CPU time 0.87 seconds
Started Dec 20 12:53:42 PM PST 23
Finished Dec 20 12:53:48 PM PST 23
Peak memory 215964 kb
Host smart-81c965ae-7437-4530-a9ff-52aaaa7b539a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770967537 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.2770967537
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.613083309
Short name T514
Test name
Test status
Simulation time 17017329 ps
CPU time 1.05 seconds
Started Dec 20 12:53:42 PM PST 23
Finished Dec 20 12:53:49 PM PST 23
Peak memory 205540 kb
Host smart-3270e768-6ac1-4f72-8cd2-6821c82307ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613083309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.613083309
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.499814674
Short name T84
Test name
Test status
Simulation time 27293749 ps
CPU time 0.8 seconds
Started Dec 20 12:53:54 PM PST 23
Finished Dec 20 12:54:03 PM PST 23
Peak memory 214200 kb
Host smart-70e7e434-738a-46c5-a52d-4abe31a5c1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499814674 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.499814674
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.965831661
Short name T856
Test name
Test status
Simulation time 41690259 ps
CPU time 0.82 seconds
Started Dec 20 12:53:42 PM PST 23
Finished Dec 20 12:53:49 PM PST 23
Peak memory 204960 kb
Host smart-1a20ddb3-6a35-4759-960b-d11ac7ab086d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965831661 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.965831661
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.1418612472
Short name T504
Test name
Test status
Simulation time 260297652 ps
CPU time 3.31 seconds
Started Dec 20 12:53:46 PM PST 23
Finished Dec 20 12:53:55 PM PST 23
Peak memory 205812 kb
Host smart-57ae7b47-8ae2-45ea-8f64-e8bdce9e4990
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418612472 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.1418612472
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.3408884326
Short name T593
Test name
Test status
Simulation time 258402803310 ps
CPU time 790 seconds
Started Dec 20 12:53:44 PM PST 23
Finished Dec 20 01:07:00 PM PST 23
Peak memory 215360 kb
Host smart-43ac1a33-d807-4f63-ac12-69b3b88a7387
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408884326 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.3408884326
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.2739848654
Short name T670
Test name
Test status
Simulation time 53922327 ps
CPU time 0.88 seconds
Started Dec 20 12:53:41 PM PST 23
Finished Dec 20 12:53:47 PM PST 23
Peak memory 206032 kb
Host smart-b9d6cb66-b6af-4f3b-9c94-414b1db2606f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739848654 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.2739848654
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.1294232663
Short name T945
Test name
Test status
Simulation time 61286914 ps
CPU time 0.89 seconds
Started Dec 20 12:53:40 PM PST 23
Finished Dec 20 12:53:45 PM PST 23
Peak memory 204508 kb
Host smart-26a91c42-0c16-4127-bcf6-328179561931
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294232663 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1294232663
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.1266210977
Short name T896
Test name
Test status
Simulation time 38298235 ps
CPU time 0.81 seconds
Started Dec 20 12:53:46 PM PST 23
Finished Dec 20 12:53:52 PM PST 23
Peak memory 214332 kb
Host smart-c8b0352f-e7e4-4e26-904a-00605ef054f8
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266210977 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.1266210977
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_err.3874021533
Short name T919
Test name
Test status
Simulation time 21572827 ps
CPU time 1.13 seconds
Started Dec 20 12:53:42 PM PST 23
Finished Dec 20 12:53:48 PM PST 23
Peak memory 215896 kb
Host smart-ea9ba847-0eec-4b95-8cf5-34b2ea16392d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874021533 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.3874021533
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_intr.2244952288
Short name T953
Test name
Test status
Simulation time 20137225 ps
CPU time 0.89 seconds
Started Dec 20 12:53:44 PM PST 23
Finished Dec 20 12:53:51 PM PST 23
Peak memory 214440 kb
Host smart-33c468fb-c493-4479-af0e-5c5d94004a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244952288 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.2244952288
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.2099714810
Short name T491
Test name
Test status
Simulation time 25654781 ps
CPU time 0.86 seconds
Started Dec 20 12:53:42 PM PST 23
Finished Dec 20 12:53:49 PM PST 23
Peak memory 204848 kb
Host smart-814323ea-3ca8-4a22-b282-f0000cd007eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099714810 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.2099714810
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.3335970115
Short name T773
Test name
Test status
Simulation time 355992891 ps
CPU time 2.21 seconds
Started Dec 20 12:53:42 PM PST 23
Finished Dec 20 12:53:50 PM PST 23
Peak memory 205948 kb
Host smart-6e4696df-848c-4c0c-95fe-a25adcd624ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335970115 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.3335970115
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.3368152033
Short name T567
Test name
Test status
Simulation time 50988742576 ps
CPU time 1139.39 seconds
Started Dec 20 12:53:46 PM PST 23
Finished Dec 20 01:12:52 PM PST 23
Peak memory 214976 kb
Host smart-2137147e-dd3a-4c33-9854-a86ec539bdad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368152033 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.3368152033
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.1528677602
Short name T753
Test name
Test status
Simulation time 21342242 ps
CPU time 1.08 seconds
Started Dec 20 12:53:54 PM PST 23
Finished Dec 20 12:54:04 PM PST 23
Peak memory 205404 kb
Host smart-2e841a6c-b714-46a8-91de-365f9eb9f0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528677602 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.1528677602
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.1798396200
Short name T893
Test name
Test status
Simulation time 33941953 ps
CPU time 0.86 seconds
Started Dec 20 12:53:54 PM PST 23
Finished Dec 20 12:54:04 PM PST 23
Peak memory 204440 kb
Host smart-45bf532b-4702-4630-a649-5ae24bcfa99a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798396200 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1798396200
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.962902119
Short name T35
Test name
Test status
Simulation time 13022676 ps
CPU time 0.87 seconds
Started Dec 20 12:53:42 PM PST 23
Finished Dec 20 12:53:49 PM PST 23
Peak memory 214572 kb
Host smart-3e98adb0-5649-481d-81c9-276fc9cd6582
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962902119 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.962902119
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.558714184
Short name T136
Test name
Test status
Simulation time 27081789 ps
CPU time 1.04 seconds
Started Dec 20 12:53:49 PM PST 23
Finished Dec 20 12:53:56 PM PST 23
Peak memory 214572 kb
Host smart-d96761b6-9551-4965-a798-d1c0b7b1e2b6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558714184 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_di
sable_auto_req_mode.558714184
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.3972004931
Short name T496
Test name
Test status
Simulation time 298255818 ps
CPU time 1.18 seconds
Started Dec 20 12:53:41 PM PST 23
Finished Dec 20 12:53:48 PM PST 23
Peak memory 214524 kb
Host smart-40612835-3d9e-41f3-a28e-cd2eeee53209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972004931 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.3972004931
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.1672215083
Short name T344
Test name
Test status
Simulation time 13297240 ps
CPU time 0.85 seconds
Started Dec 20 12:53:47 PM PST 23
Finished Dec 20 12:53:54 PM PST 23
Peak memory 204948 kb
Host smart-7d14ca94-fc67-46be-a4be-8690a1c917e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672215083 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.1672215083
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.2972830285
Short name T591
Test name
Test status
Simulation time 18864450 ps
CPU time 1.04 seconds
Started Dec 20 12:53:50 PM PST 23
Finished Dec 20 12:53:58 PM PST 23
Peak memory 221204 kb
Host smart-b7b61868-4bea-4b85-b68b-0c4f3c1b7ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972830285 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.2972830285
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.317459142
Short name T534
Test name
Test status
Simulation time 15805343 ps
CPU time 0.89 seconds
Started Dec 20 12:53:51 PM PST 23
Finished Dec 20 12:53:59 PM PST 23
Peak memory 205012 kb
Host smart-bd002c1b-f916-468d-9551-f44fdb4a9d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317459142 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.317459142
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.1086046324
Short name T702
Test name
Test status
Simulation time 19498123 ps
CPU time 0.97 seconds
Started Dec 20 12:53:42 PM PST 23
Finished Dec 20 12:53:49 PM PST 23
Peak memory 204516 kb
Host smart-32a10a5e-571a-44ca-acb6-7a3d9b8424a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086046324 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.1086046324
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.3479607466
Short name T57
Test name
Test status
Simulation time 69353469609 ps
CPU time 737.25 seconds
Started Dec 20 12:53:42 PM PST 23
Finished Dec 20 01:06:05 PM PST 23
Peak memory 215260 kb
Host smart-6387da53-d30b-4278-95f2-0fd3b2ca2438
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479607466 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.3479607466
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.121743632
Short name T857
Test name
Test status
Simulation time 21727004 ps
CPU time 0.98 seconds
Started Dec 20 12:53:51 PM PST 23
Finished Dec 20 12:53:59 PM PST 23
Peak memory 205896 kb
Host smart-788f828d-510c-4f19-aa4d-1609e69c283a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121743632 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.121743632
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.2287177397
Short name T974
Test name
Test status
Simulation time 17995034 ps
CPU time 0.82 seconds
Started Dec 20 12:53:55 PM PST 23
Finished Dec 20 12:54:04 PM PST 23
Peak memory 204588 kb
Host smart-59522f43-87b8-4fe5-baa3-faafd4d05d15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287177397 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.2287177397
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.1644336430
Short name T222
Test name
Test status
Simulation time 42483707 ps
CPU time 0.8 seconds
Started Dec 20 12:53:55 PM PST 23
Finished Dec 20 12:54:04 PM PST 23
Peak memory 214308 kb
Host smart-12151013-edb8-400d-b288-72763eff1496
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644336430 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.1644336430
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.659432273
Short name T156
Test name
Test status
Simulation time 22514616 ps
CPU time 1 seconds
Started Dec 20 12:53:46 PM PST 23
Finished Dec 20 12:53:52 PM PST 23
Peak memory 214632 kb
Host smart-c65c077a-470b-49c8-90c9-9ee46ffa0723
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659432273 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_di
sable_auto_req_mode.659432273
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.1317673462
Short name T632
Test name
Test status
Simulation time 44763886 ps
CPU time 1.01 seconds
Started Dec 20 12:53:45 PM PST 23
Finished Dec 20 12:53:52 PM PST 23
Peak memory 216888 kb
Host smart-27e67068-ffad-4312-afcc-92599a75c930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317673462 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1317673462
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.1135789313
Short name T328
Test name
Test status
Simulation time 52872279 ps
CPU time 0.85 seconds
Started Dec 20 12:53:49 PM PST 23
Finished Dec 20 12:53:57 PM PST 23
Peak memory 205100 kb
Host smart-0364e44e-8167-427c-9680-4c3f20420bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135789313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.1135789313
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.2689995078
Short name T585
Test name
Test status
Simulation time 46134375 ps
CPU time 0.94 seconds
Started Dec 20 12:53:51 PM PST 23
Finished Dec 20 12:54:00 PM PST 23
Peak memory 221596 kb
Host smart-154d8370-8dc1-4da9-914f-5da9b46d0a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689995078 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.2689995078
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.2528846687
Short name T469
Test name
Test status
Simulation time 13362005 ps
CPU time 0.89 seconds
Started Dec 20 12:53:54 PM PST 23
Finished Dec 20 12:54:04 PM PST 23
Peak memory 204632 kb
Host smart-864f2e55-f7b7-4e0d-a58a-34c8e57fd9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528846687 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.2528846687
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.2729224495
Short name T501
Test name
Test status
Simulation time 37332558 ps
CPU time 1.05 seconds
Started Dec 20 12:53:48 PM PST 23
Finished Dec 20 12:53:56 PM PST 23
Peak memory 205244 kb
Host smart-5df93b27-e4db-487e-9f7b-ead075412e09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729224495 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.2729224495
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.3690816560
Short name T820
Test name
Test status
Simulation time 36463654785 ps
CPU time 814.94 seconds
Started Dec 20 12:53:56 PM PST 23
Finished Dec 20 01:07:39 PM PST 23
Peak memory 216044 kb
Host smart-cd6baec4-b836-4991-a07d-8db8c0b5bae7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690816560 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.3690816560
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.1726899272
Short name T313
Test name
Test status
Simulation time 33648304 ps
CPU time 0.89 seconds
Started Dec 20 12:53:53 PM PST 23
Finished Dec 20 12:54:01 PM PST 23
Peak memory 205404 kb
Host smart-a7b3fab7-ffb4-4eab-b460-5194012df578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726899272 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.1726899272
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.1244008123
Short name T747
Test name
Test status
Simulation time 70613625 ps
CPU time 0.79 seconds
Started Dec 20 12:53:47 PM PST 23
Finished Dec 20 12:53:54 PM PST 23
Peak memory 204188 kb
Host smart-ff7cd623-22e0-45e5-a5a3-c56a8a7e5c36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244008123 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.1244008123
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.490095752
Short name T223
Test name
Test status
Simulation time 99791943 ps
CPU time 1.05 seconds
Started Dec 20 12:53:47 PM PST 23
Finished Dec 20 12:53:54 PM PST 23
Peak memory 214564 kb
Host smart-d2b8eb73-c8dd-444f-ab48-c12b73d83926
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490095752 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_di
sable_auto_req_mode.490095752
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.794090956
Short name T895
Test name
Test status
Simulation time 37513173 ps
CPU time 0.92 seconds
Started Dec 20 12:53:52 PM PST 23
Finished Dec 20 12:54:01 PM PST 23
Peak memory 214244 kb
Host smart-2642a83d-d3e2-488b-ab4d-04ef5b9d0d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794090956 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.794090956
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.1952427485
Short name T329
Test name
Test status
Simulation time 8723427277 ps
CPU time 96.44 seconds
Started Dec 20 12:53:55 PM PST 23
Finished Dec 20 12:55:40 PM PST 23
Peak memory 214264 kb
Host smart-a3d3ebd2-c8f9-4d19-95e2-df80b54e403c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952427485 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1952427485
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.2955524009
Short name T83
Test name
Test status
Simulation time 21534955 ps
CPU time 1 seconds
Started Dec 20 12:53:55 PM PST 23
Finished Dec 20 12:54:04 PM PST 23
Peak memory 225640 kb
Host smart-09b3ee78-40db-4871-bd70-e27c1748d9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955524009 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2955524009
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.3232311829
Short name T526
Test name
Test status
Simulation time 16285040 ps
CPU time 0.94 seconds
Started Dec 20 12:53:52 PM PST 23
Finished Dec 20 12:54:01 PM PST 23
Peak memory 205004 kb
Host smart-d35a6681-a29d-46b3-b99a-4036383def12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232311829 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.3232311829
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.1850690160
Short name T738
Test name
Test status
Simulation time 139771606 ps
CPU time 3.09 seconds
Started Dec 20 12:53:52 PM PST 23
Finished Dec 20 12:54:03 PM PST 23
Peak memory 206016 kb
Host smart-4ee7bf83-9613-4a5f-aa15-ddbf00688335
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850690160 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.1850690160
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.2248038624
Short name T94
Test name
Test status
Simulation time 99375078659 ps
CPU time 2167.34 seconds
Started Dec 20 12:53:55 PM PST 23
Finished Dec 20 01:30:11 PM PST 23
Peak memory 222496 kb
Host smart-26b0130e-b4f5-4604-9d49-538746fba94a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248038624 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.2248038624
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.3534262140
Short name T920
Test name
Test status
Simulation time 20300665 ps
CPU time 0.99 seconds
Started Dec 20 12:53:41 PM PST 23
Finished Dec 20 12:53:48 PM PST 23
Peak memory 205744 kb
Host smart-2e25ee42-3343-4012-a1bb-d249f061e9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534262140 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.3534262140
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.2571076346
Short name T70
Test name
Test status
Simulation time 137397110 ps
CPU time 0.89 seconds
Started Dec 20 12:53:44 PM PST 23
Finished Dec 20 12:53:51 PM PST 23
Peak memory 204588 kb
Host smart-83de4ef4-eff4-407c-8910-ea8907f644d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571076346 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.2571076346
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.2325096897
Short name T123
Test name
Test status
Simulation time 41102325 ps
CPU time 0.83 seconds
Started Dec 20 12:53:45 PM PST 23
Finished Dec 20 12:53:52 PM PST 23
Peak memory 214424 kb
Host smart-71a5bba4-7d16-41a3-b482-f93237baeabf
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325096897 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.2325096897
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.4265044164
Short name T703
Test name
Test status
Simulation time 98552499 ps
CPU time 0.89 seconds
Started Dec 20 12:53:51 PM PST 23
Finished Dec 20 12:53:58 PM PST 23
Peak memory 214560 kb
Host smart-8d7e8788-e3ed-4a09-96d6-4f36ec76f7cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265044164 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.4265044164
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.906571167
Short name T844
Test name
Test status
Simulation time 55841048 ps
CPU time 0.99 seconds
Started Dec 20 12:53:45 PM PST 23
Finished Dec 20 12:53:52 PM PST 23
Peak memory 216072 kb
Host smart-4ddf4442-277b-42de-baca-52cec48e72c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906571167 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.906571167
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.3309773712
Short name T34
Test name
Test status
Simulation time 16090075 ps
CPU time 1.1 seconds
Started Dec 20 12:53:47 PM PST 23
Finished Dec 20 12:53:54 PM PST 23
Peak memory 205384 kb
Host smart-bb1298c4-4a90-40a0-8a25-3c0e6e9cf842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309773712 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.3309773712
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.1585299412
Short name T749
Test name
Test status
Simulation time 19965750 ps
CPU time 0.92 seconds
Started Dec 20 12:53:43 PM PST 23
Finished Dec 20 12:53:50 PM PST 23
Peak memory 214516 kb
Host smart-5c4726cf-2cbf-4eec-b06c-ec01ee5f22b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585299412 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1585299412
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.3873618392
Short name T886
Test name
Test status
Simulation time 23136909 ps
CPU time 0.81 seconds
Started Dec 20 12:53:52 PM PST 23
Finished Dec 20 12:54:00 PM PST 23
Peak memory 204504 kb
Host smart-c912c219-0494-4df7-9439-543de826ac6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873618392 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.3873618392
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.512117110
Short name T545
Test name
Test status
Simulation time 335519825 ps
CPU time 3.94 seconds
Started Dec 20 12:53:56 PM PST 23
Finished Dec 20 12:54:09 PM PST 23
Peak memory 206004 kb
Host smart-43a6a441-5a2a-45fc-83da-787d746575df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512117110 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.512117110
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.695961301
Short name T520
Test name
Test status
Simulation time 28051326752 ps
CPU time 285.79 seconds
Started Dec 20 12:53:49 PM PST 23
Finished Dec 20 12:58:41 PM PST 23
Peak memory 215392 kb
Host smart-69cbea46-a993-46b3-885a-ea402f3e3b66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695961301 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.695961301
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.2284768619
Short name T322
Test name
Test status
Simulation time 29798917 ps
CPU time 1 seconds
Started Dec 20 12:53:51 PM PST 23
Finished Dec 20 12:53:59 PM PST 23
Peak memory 205796 kb
Host smart-dcfda911-06a4-439f-b382-0efbb0127416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284768619 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2284768619
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.2931809030
Short name T883
Test name
Test status
Simulation time 220190376 ps
CPU time 1.42 seconds
Started Dec 20 12:53:51 PM PST 23
Finished Dec 20 12:54:00 PM PST 23
Peak memory 205196 kb
Host smart-71726f50-330e-4580-927a-d7c79bd4244a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931809030 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.2931809030
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.646744660
Short name T173
Test name
Test status
Simulation time 16016506 ps
CPU time 0.79 seconds
Started Dec 20 12:53:49 PM PST 23
Finished Dec 20 12:53:57 PM PST 23
Peak memory 214376 kb
Host smart-38ab650a-a1ed-429e-8417-3ed7c7251e35
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646744660 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.646744660
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.2091290800
Short name T144
Test name
Test status
Simulation time 110622689 ps
CPU time 0.93 seconds
Started Dec 20 12:53:46 PM PST 23
Finished Dec 20 12:53:53 PM PST 23
Peak memory 214612 kb
Host smart-46f2c0ca-1842-4f0f-a852-407dc9e45d1f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091290800 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.2091290800
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.2992636975
Short name T714
Test name
Test status
Simulation time 47350004 ps
CPU time 1.08 seconds
Started Dec 20 12:53:45 PM PST 23
Finished Dec 20 12:53:52 PM PST 23
Peak memory 221832 kb
Host smart-8bcaec88-1eb5-40c2-89cc-b1de8afcb5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992636975 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.2992636975
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.1428792819
Short name T909
Test name
Test status
Simulation time 111830472 ps
CPU time 1.06 seconds
Started Dec 20 12:53:50 PM PST 23
Finished Dec 20 12:53:57 PM PST 23
Peak memory 205488 kb
Host smart-bb38f5a1-b33f-431b-9936-d5e3aa7942cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428792819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.1428792819
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.1248331652
Short name T942
Test name
Test status
Simulation time 19578747 ps
CPU time 1.13 seconds
Started Dec 20 12:53:54 PM PST 23
Finished Dec 20 12:54:03 PM PST 23
Peak memory 221504 kb
Host smart-228d9673-4a23-4abc-82de-b66a8bbf0013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248331652 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.1248331652
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.28787124
Short name T97
Test name
Test status
Simulation time 20038912 ps
CPU time 0.95 seconds
Started Dec 20 12:53:54 PM PST 23
Finished Dec 20 12:54:04 PM PST 23
Peak memory 204972 kb
Host smart-0a4baabd-ec41-495a-b8e1-b884ebd2ab46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28787124 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.28787124
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.2470489586
Short name T642
Test name
Test status
Simulation time 205602970 ps
CPU time 1.43 seconds
Started Dec 20 12:53:47 PM PST 23
Finished Dec 20 12:53:55 PM PST 23
Peak memory 205856 kb
Host smart-de7f153f-b676-484b-8c8a-45bbe732979e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470489586 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.2470489586
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.2365548965
Short name T826
Test name
Test status
Simulation time 87477977024 ps
CPU time 1104.32 seconds
Started Dec 20 12:53:50 PM PST 23
Finished Dec 20 01:12:21 PM PST 23
Peak memory 218504 kb
Host smart-ffb3edbc-af13-4300-ab05-f1724947e3ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365548965 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.2365548965
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.3355744785
Short name T235
Test name
Test status
Simulation time 17238109 ps
CPU time 0.96 seconds
Started Dec 20 12:51:51 PM PST 23
Finished Dec 20 12:52:07 PM PST 23
Peak memory 205996 kb
Host smart-bb016412-8813-451f-bdbf-11244cd3c87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355744785 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.3355744785
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.1744149365
Short name T653
Test name
Test status
Simulation time 31256699 ps
CPU time 0.96 seconds
Started Dec 20 12:52:28 PM PST 23
Finished Dec 20 12:52:43 PM PST 23
Peak memory 204688 kb
Host smart-8229c631-15f5-4cec-96a2-80b4021a7172
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744149365 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.1744149365
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.597952554
Short name T124
Test name
Test status
Simulation time 42581168 ps
CPU time 0.85 seconds
Started Dec 20 12:52:29 PM PST 23
Finished Dec 20 12:52:43 PM PST 23
Peak memory 214408 kb
Host smart-81c7705c-d781-480a-a33f-083f26bc94e4
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597952554 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.597952554
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.918885604
Short name T902
Test name
Test status
Simulation time 34423618 ps
CPU time 0.98 seconds
Started Dec 20 12:52:32 PM PST 23
Finished Dec 20 12:52:46 PM PST 23
Peak memory 214632 kb
Host smart-a52ed203-e5c6-438f-be0f-e003f145c61c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918885604 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_dis
able_auto_req_mode.918885604
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_genbits.218185145
Short name T339
Test name
Test status
Simulation time 62566085 ps
CPU time 1 seconds
Started Dec 20 12:52:08 PM PST 23
Finished Dec 20 12:52:27 PM PST 23
Peak memory 205560 kb
Host smart-d63b712e-ec50-41cd-a9c2-023e62c606a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218185145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.218185145
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.3003493270
Short name T799
Test name
Test status
Simulation time 19680159 ps
CPU time 0.91 seconds
Started Dec 20 12:51:52 PM PST 23
Finished Dec 20 12:52:07 PM PST 23
Peak memory 214448 kb
Host smart-531d96c9-9604-44e8-8bd4-fadf7ab1d9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003493270 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.3003493270
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.920193276
Short name T317
Test name
Test status
Simulation time 33900114 ps
CPU time 0.84 seconds
Started Dec 20 12:52:10 PM PST 23
Finished Dec 20 12:52:30 PM PST 23
Peak memory 204964 kb
Host smart-35ebe18a-0005-4bcd-928d-896ae1430698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920193276 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.920193276
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_smoke.432840140
Short name T852
Test name
Test status
Simulation time 16342456 ps
CPU time 0.87 seconds
Started Dec 20 12:51:55 PM PST 23
Finished Dec 20 12:52:11 PM PST 23
Peak memory 204652 kb
Host smart-6640b78a-0ba1-4284-9371-2c9c09a7c8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432840140 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.432840140
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.842133110
Short name T640
Test name
Test status
Simulation time 67269991 ps
CPU time 1.89 seconds
Started Dec 20 12:51:50 PM PST 23
Finished Dec 20 12:52:05 PM PST 23
Peak memory 205704 kb
Host smart-5d6de1c8-b6e5-43e8-9072-ba8453877094
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842133110 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.842133110
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_alert.3945386337
Short name T16
Test name
Test status
Simulation time 53775958 ps
CPU time 0.93 seconds
Started Dec 20 12:53:49 PM PST 23
Finished Dec 20 12:53:57 PM PST 23
Peak memory 206032 kb
Host smart-e740e670-6645-4c0a-a220-bdecab8cd5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945386337 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.3945386337
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.4205885734
Short name T636
Test name
Test status
Simulation time 70305722 ps
CPU time 0.81 seconds
Started Dec 20 12:53:46 PM PST 23
Finished Dec 20 12:53:53 PM PST 23
Peak memory 204332 kb
Host smart-8bcca22b-a54d-4240-8e37-3916c4020d16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205885734 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.4205885734
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.388304186
Short name T69
Test name
Test status
Simulation time 50780356 ps
CPU time 0.82 seconds
Started Dec 20 12:53:45 PM PST 23
Finished Dec 20 12:53:52 PM PST 23
Peak memory 214388 kb
Host smart-3621e595-0174-4a32-b357-d7e559d680bc
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388304186 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.388304186
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.922789515
Short name T889
Test name
Test status
Simulation time 30177830 ps
CPU time 1.03 seconds
Started Dec 20 12:53:50 PM PST 23
Finished Dec 20 12:53:57 PM PST 23
Peak memory 214412 kb
Host smart-6236df86-0e07-4849-a40a-9acd1dda9686
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922789515 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_di
sable_auto_req_mode.922789515
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.1623343367
Short name T662
Test name
Test status
Simulation time 28583732 ps
CPU time 0.82 seconds
Started Dec 20 12:53:51 PM PST 23
Finished Dec 20 12:54:00 PM PST 23
Peak memory 215432 kb
Host smart-c3c44686-7841-42b6-941b-9fe4b7990bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623343367 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.1623343367
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.882851640
Short name T764
Test name
Test status
Simulation time 192559369 ps
CPU time 1 seconds
Started Dec 20 12:53:44 PM PST 23
Finished Dec 20 12:53:51 PM PST 23
Peak memory 205672 kb
Host smart-54212c17-3e5d-4d2a-bb30-527ebde7c23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882851640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.882851640
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.434107856
Short name T882
Test name
Test status
Simulation time 22298046 ps
CPU time 0.95 seconds
Started Dec 20 12:53:45 PM PST 23
Finished Dec 20 12:53:52 PM PST 23
Peak memory 225368 kb
Host smart-2a554ae3-ddeb-402c-b72c-bf5dd3cf7d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434107856 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.434107856
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.2276644636
Short name T664
Test name
Test status
Simulation time 74337615 ps
CPU time 0.93 seconds
Started Dec 20 12:53:54 PM PST 23
Finished Dec 20 12:54:04 PM PST 23
Peak memory 204896 kb
Host smart-3543fd7f-fbad-46da-bf83-7d4ed72d1ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276644636 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.2276644636
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.2569242709
Short name T786
Test name
Test status
Simulation time 228659873 ps
CPU time 4.35 seconds
Started Dec 20 12:53:49 PM PST 23
Finished Dec 20 12:54:00 PM PST 23
Peak memory 205972 kb
Host smart-b087bcdf-90b3-4d62-aa5e-42b56363b451
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569242709 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.2569242709
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_alert.3128886276
Short name T805
Test name
Test status
Simulation time 28338909 ps
CPU time 0.91 seconds
Started Dec 20 12:53:56 PM PST 23
Finished Dec 20 12:54:06 PM PST 23
Peak memory 206008 kb
Host smart-cb65568c-bef4-4cb6-80e6-effcc10fea4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128886276 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.3128886276
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.1096290989
Short name T624
Test name
Test status
Simulation time 43500303 ps
CPU time 0.82 seconds
Started Dec 20 12:53:44 PM PST 23
Finished Dec 20 12:53:51 PM PST 23
Peak memory 204644 kb
Host smart-48e42929-71f7-4c72-aec8-8908d1a41739
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096290989 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.1096290989
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.4221546353
Short name T171
Test name
Test status
Simulation time 12382950 ps
CPU time 0.82 seconds
Started Dec 20 12:53:49 PM PST 23
Finished Dec 20 12:53:57 PM PST 23
Peak memory 214468 kb
Host smart-14f2d893-364a-4b5d-aa03-a4c0f2c023a8
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221546353 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.4221546353
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.1396246424
Short name T918
Test name
Test status
Simulation time 61580415 ps
CPU time 0.91 seconds
Started Dec 20 12:53:47 PM PST 23
Finished Dec 20 12:53:54 PM PST 23
Peak memory 214520 kb
Host smart-16799c7d-6c1a-4d4e-96ce-f36c822f29d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396246424 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.1396246424
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.1784475186
Short name T650
Test name
Test status
Simulation time 21804448 ps
CPU time 0.83 seconds
Started Dec 20 12:53:51 PM PST 23
Finished Dec 20 12:53:59 PM PST 23
Peak memory 215936 kb
Host smart-fca73ae0-2359-447a-99cf-25a7e9e2ae4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784475186 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.1784475186
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.2552902124
Short name T646
Test name
Test status
Simulation time 71528085 ps
CPU time 1.71 seconds
Started Dec 20 12:53:44 PM PST 23
Finished Dec 20 12:53:52 PM PST 23
Peak memory 214328 kb
Host smart-97c9c44a-dd2d-4662-ad50-4674c2162545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552902124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.2552902124
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.3229015132
Short name T536
Test name
Test status
Simulation time 20776897 ps
CPU time 1.18 seconds
Started Dec 20 12:53:49 PM PST 23
Finished Dec 20 12:53:57 PM PST 23
Peak memory 221448 kb
Host smart-551625a1-dcc7-4f3f-8e1c-b18a2e169692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229015132 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.3229015132
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.1703235283
Short name T779
Test name
Test status
Simulation time 14321266 ps
CPU time 0.84 seconds
Started Dec 20 12:53:49 PM PST 23
Finished Dec 20 12:53:57 PM PST 23
Peak memory 204616 kb
Host smart-2cac71c3-b8c9-45d9-bf48-f7fcec210e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703235283 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.1703235283
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.250686210
Short name T543
Test name
Test status
Simulation time 77549663 ps
CPU time 2.09 seconds
Started Dec 20 12:53:51 PM PST 23
Finished Dec 20 12:54:00 PM PST 23
Peak memory 205900 kb
Host smart-94cc5a9c-a8be-4e35-bda1-6bbd07bf1ab3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250686210 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.250686210
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_alert.3131675931
Short name T15
Test name
Test status
Simulation time 59249339 ps
CPU time 0.91 seconds
Started Dec 20 12:53:51 PM PST 23
Finished Dec 20 12:54:00 PM PST 23
Peak memory 205900 kb
Host smart-49b2d80e-a1c7-4bbc-8954-f3cdbd943b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131675931 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.3131675931
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.2789927143
Short name T884
Test name
Test status
Simulation time 30321970 ps
CPU time 0.91 seconds
Started Dec 20 12:53:55 PM PST 23
Finished Dec 20 12:54:04 PM PST 23
Peak memory 204516 kb
Host smart-dd02534d-d94d-4ed0-a560-5f651e25522f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789927143 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.2789927143
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.3514707848
Short name T121
Test name
Test status
Simulation time 60718258 ps
CPU time 0.86 seconds
Started Dec 20 12:53:51 PM PST 23
Finished Dec 20 12:54:00 PM PST 23
Peak memory 214276 kb
Host smart-570ebc2e-85d4-4987-870a-9ddd817b5dd8
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514707848 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.3514707848
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_err.3666682905
Short name T752
Test name
Test status
Simulation time 32525465 ps
CPU time 0.96 seconds
Started Dec 20 12:53:55 PM PST 23
Finished Dec 20 12:54:05 PM PST 23
Peak memory 221848 kb
Host smart-edf2c28a-ba17-4f5b-8254-c132b295c3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666682905 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.3666682905
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.414167375
Short name T785
Test name
Test status
Simulation time 33504088 ps
CPU time 1.38 seconds
Started Dec 20 12:53:50 PM PST 23
Finished Dec 20 12:53:58 PM PST 23
Peak memory 214112 kb
Host smart-8777f0bd-a77b-40a3-8c8c-26da496e901c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414167375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.414167375
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_smoke.1638075210
Short name T644
Test name
Test status
Simulation time 15101688 ps
CPU time 0.89 seconds
Started Dec 20 12:53:51 PM PST 23
Finished Dec 20 12:53:59 PM PST 23
Peak memory 204760 kb
Host smart-295779cf-e132-43ef-aca7-7101e414fe68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638075210 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.1638075210
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.3070864105
Short name T639
Test name
Test status
Simulation time 133878372 ps
CPU time 1.8 seconds
Started Dec 20 12:53:49 PM PST 23
Finished Dec 20 12:53:58 PM PST 23
Peak memory 205428 kb
Host smart-0a96c932-7e21-4321-a318-d15038960eb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070864105 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.3070864105
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.3418246544
Short name T95
Test name
Test status
Simulation time 142465995714 ps
CPU time 768.09 seconds
Started Dec 20 12:53:55 PM PST 23
Finished Dec 20 01:06:52 PM PST 23
Peak memory 215560 kb
Host smart-eefc8be7-81f3-4d75-9429-f7ea851bf87f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418246544 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.3418246544
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.1959869772
Short name T98
Test name
Test status
Simulation time 22182615 ps
CPU time 1.01 seconds
Started Dec 20 12:53:45 PM PST 23
Finished Dec 20 12:53:52 PM PST 23
Peak memory 205444 kb
Host smart-1c7c031b-f216-4321-94a4-41955edc35b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959869772 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.1959869772
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.1188117947
Short name T842
Test name
Test status
Simulation time 13758697 ps
CPU time 0.84 seconds
Started Dec 20 12:53:53 PM PST 23
Finished Dec 20 12:54:01 PM PST 23
Peak memory 204444 kb
Host smart-ccf39195-8b03-49be-85ed-532b2a29d65c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188117947 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.1188117947
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.1910799922
Short name T143
Test name
Test status
Simulation time 35679228 ps
CPU time 0.93 seconds
Started Dec 20 12:53:53 PM PST 23
Finished Dec 20 12:54:01 PM PST 23
Peak memory 215612 kb
Host smart-3f7ceb15-bf4d-4228-abba-2ec557fb56be
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910799922 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.1910799922
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_genbits.3383135965
Short name T252
Test name
Test status
Simulation time 15979581 ps
CPU time 1.07 seconds
Started Dec 20 12:53:51 PM PST 23
Finished Dec 20 12:54:00 PM PST 23
Peak memory 205528 kb
Host smart-4bf32514-9215-410a-877e-3064ed24cab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383135965 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.3383135965
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.741649275
Short name T716
Test name
Test status
Simulation time 34173780 ps
CPU time 1.02 seconds
Started Dec 20 12:53:55 PM PST 23
Finished Dec 20 12:54:04 PM PST 23
Peak memory 221412 kb
Host smart-c1b74844-88ca-472a-a2c7-e9cb0a6fbc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741649275 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.741649275
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.1511212471
Short name T693
Test name
Test status
Simulation time 76895737 ps
CPU time 0.85 seconds
Started Dec 20 12:53:55 PM PST 23
Finished Dec 20 12:54:04 PM PST 23
Peak memory 204636 kb
Host smart-534fcebc-7195-408d-bf67-f49ff39d10d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511212471 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.1511212471
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.2096991298
Short name T550
Test name
Test status
Simulation time 230612748 ps
CPU time 3.66 seconds
Started Dec 20 12:53:53 PM PST 23
Finished Dec 20 12:54:04 PM PST 23
Peak memory 206012 kb
Host smart-38a91b8b-93f8-488b-890b-0577b956b2d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096991298 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.2096991298
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.3586346686
Short name T804
Test name
Test status
Simulation time 37303831933 ps
CPU time 403.39 seconds
Started Dec 20 12:53:51 PM PST 23
Finished Dec 20 01:00:42 PM PST 23
Peak memory 215000 kb
Host smart-018f6792-79b6-41df-9b67-a90d027e60ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586346686 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.3586346686
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.1233402741
Short name T310
Test name
Test status
Simulation time 31405706 ps
CPU time 0.93 seconds
Started Dec 20 12:53:52 PM PST 23
Finished Dec 20 12:54:01 PM PST 23
Peak memory 205776 kb
Host smart-ca369df1-fd0c-459d-854b-33f76e74bfa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233402741 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.1233402741
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.3330674213
Short name T787
Test name
Test status
Simulation time 34533900 ps
CPU time 1.14 seconds
Started Dec 20 12:53:56 PM PST 23
Finished Dec 20 12:54:07 PM PST 23
Peak memory 204616 kb
Host smart-159d85cc-a6aa-485c-9da1-a783f1874dc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330674213 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.3330674213
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.928879822
Short name T154
Test name
Test status
Simulation time 82398177 ps
CPU time 1 seconds
Started Dec 20 12:53:57 PM PST 23
Finished Dec 20 12:54:08 PM PST 23
Peak memory 214588 kb
Host smart-aa9c7941-c15d-44e7-95d2-f0a5c9c284f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928879822 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_di
sable_auto_req_mode.928879822
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.3384070898
Short name T592
Test name
Test status
Simulation time 22982028 ps
CPU time 1.12 seconds
Started Dec 20 12:53:52 PM PST 23
Finished Dec 20 12:54:01 PM PST 23
Peak memory 215708 kb
Host smart-99e2cdbf-fa57-4c9d-87d6-151c28ff7ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384070898 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.3384070898
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.1301581764
Short name T55
Test name
Test status
Simulation time 39959768 ps
CPU time 0.97 seconds
Started Dec 20 12:53:53 PM PST 23
Finished Dec 20 12:54:01 PM PST 23
Peak memory 213976 kb
Host smart-b09ac03a-28f9-4957-ba42-1a4ef7aa99cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301581764 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.1301581764
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.1637269911
Short name T961
Test name
Test status
Simulation time 26660898 ps
CPU time 0.87 seconds
Started Dec 20 12:53:51 PM PST 23
Finished Dec 20 12:53:58 PM PST 23
Peak memory 214304 kb
Host smart-4f61c53c-a244-425b-a115-efbe63fef285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637269911 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.1637269911
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.2807599427
Short name T751
Test name
Test status
Simulation time 14122545 ps
CPU time 0.93 seconds
Started Dec 20 12:53:46 PM PST 23
Finished Dec 20 12:53:52 PM PST 23
Peak memory 204668 kb
Host smart-6e79e9bc-94e6-40b0-abf8-db71dbc63c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807599427 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.2807599427
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.1737060136
Short name T855
Test name
Test status
Simulation time 37114822 ps
CPU time 1.35 seconds
Started Dec 20 12:53:50 PM PST 23
Finished Dec 20 12:53:58 PM PST 23
Peak memory 205920 kb
Host smart-fca466ec-5026-4ce2-a954-5a949ac47364
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737060136 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1737060136
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.940735556
Short name T835
Test name
Test status
Simulation time 7552795657 ps
CPU time 163.37 seconds
Started Dec 20 12:53:48 PM PST 23
Finished Dec 20 12:56:39 PM PST 23
Peak memory 215448 kb
Host smart-746fd5fa-1471-403b-9fd2-78e28d0c7ce5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940735556 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.940735556
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.3293401854
Short name T323
Test name
Test status
Simulation time 27769580 ps
CPU time 0.93 seconds
Started Dec 20 12:53:56 PM PST 23
Finished Dec 20 12:54:05 PM PST 23
Peak memory 205664 kb
Host smart-a1478fb4-4c2a-43f3-acfb-ae5a159344e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293401854 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.3293401854
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.4289595052
Short name T726
Test name
Test status
Simulation time 39358222 ps
CPU time 0.84 seconds
Started Dec 20 12:53:51 PM PST 23
Finished Dec 20 12:54:00 PM PST 23
Peak memory 205012 kb
Host smart-2b2690cc-136c-460a-a5a3-3b11272d5201
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289595052 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.4289595052
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.1076537877
Short name T921
Test name
Test status
Simulation time 73227847 ps
CPU time 1.16 seconds
Started Dec 20 12:53:56 PM PST 23
Finished Dec 20 12:54:08 PM PST 23
Peak memory 214604 kb
Host smart-762a7564-dbd9-4e5d-8796-7b609f7555a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076537877 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.1076537877
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.3548099498
Short name T736
Test name
Test status
Simulation time 31417125 ps
CPU time 0.93 seconds
Started Dec 20 12:53:56 PM PST 23
Finished Dec 20 12:54:06 PM PST 23
Peak memory 221732 kb
Host smart-22bf723f-1219-4805-b1a4-2b40c3858f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548099498 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.3548099498
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.2971986951
Short name T332
Test name
Test status
Simulation time 23813127 ps
CPU time 0.9 seconds
Started Dec 20 12:53:51 PM PST 23
Finished Dec 20 12:54:00 PM PST 23
Peak memory 205112 kb
Host smart-77aa36aa-f8b9-458c-bb50-c2e4a96ee1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971986951 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.2971986951
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.4114388172
Short name T79
Test name
Test status
Simulation time 33298300 ps
CPU time 0.84 seconds
Started Dec 20 12:53:52 PM PST 23
Finished Dec 20 12:54:01 PM PST 23
Peak memory 214312 kb
Host smart-1d627811-cecf-448d-aaf6-9df4300e9564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114388172 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.4114388172
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.2565348403
Short name T652
Test name
Test status
Simulation time 42889463 ps
CPU time 0.86 seconds
Started Dec 20 12:53:51 PM PST 23
Finished Dec 20 12:54:00 PM PST 23
Peak memory 204760 kb
Host smart-95fc82bc-2a15-43c3-ae2c-e872f87ce526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565348403 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.2565348403
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.1142451471
Short name T917
Test name
Test status
Simulation time 775635981 ps
CPU time 3.43 seconds
Started Dec 20 12:53:55 PM PST 23
Finished Dec 20 12:54:07 PM PST 23
Peak memory 206004 kb
Host smart-a20e9022-a51f-41e2-8e5b-028e649efc6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142451471 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1142451471
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.3114693460
Short name T916
Test name
Test status
Simulation time 51458499595 ps
CPU time 1276.17 seconds
Started Dec 20 12:53:56 PM PST 23
Finished Dec 20 01:15:21 PM PST 23
Peak memory 215668 kb
Host smart-4300f0c4-bfca-4352-8c8e-a163fdd4c876
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114693460 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.3114693460
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.2069015310
Short name T682
Test name
Test status
Simulation time 17704234 ps
CPU time 0.94 seconds
Started Dec 20 12:53:56 PM PST 23
Finished Dec 20 12:54:07 PM PST 23
Peak memory 205236 kb
Host smart-d38e20fb-b9b1-41f2-b709-6c1c1f0d578c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069015310 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.2069015310
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.4076646496
Short name T660
Test name
Test status
Simulation time 15355113 ps
CPU time 0.87 seconds
Started Dec 20 12:53:53 PM PST 23
Finished Dec 20 12:54:01 PM PST 23
Peak memory 205232 kb
Host smart-6d27de12-67cd-459b-a23f-2ddd1f74513a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076646496 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.4076646496
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.1896058044
Short name T127
Test name
Test status
Simulation time 11143480 ps
CPU time 0.86 seconds
Started Dec 20 12:53:52 PM PST 23
Finished Dec 20 12:54:01 PM PST 23
Peak memory 214464 kb
Host smart-2b2f1381-b6fe-4477-a370-12127aaba718
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896058044 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.1896058044
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.2667322958
Short name T303
Test name
Test status
Simulation time 28794180 ps
CPU time 0.99 seconds
Started Dec 20 12:53:54 PM PST 23
Finished Dec 20 12:54:03 PM PST 23
Peak memory 214568 kb
Host smart-4337eb06-5113-466e-bccb-ff709bb67e71
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667322958 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.2667322958
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.1801937838
Short name T111
Test name
Test status
Simulation time 23101029 ps
CPU time 1.08 seconds
Started Dec 20 12:53:50 PM PST 23
Finished Dec 20 12:53:57 PM PST 23
Peak memory 214648 kb
Host smart-ce0c56e1-653e-452d-a9b6-3f71744b858c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801937838 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.1801937838
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.800469492
Short name T809
Test name
Test status
Simulation time 14457027 ps
CPU time 0.93 seconds
Started Dec 20 12:53:56 PM PST 23
Finished Dec 20 12:54:06 PM PST 23
Peak memory 205044 kb
Host smart-5298b8c4-0355-4d8d-8108-50a1ee9b1e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800469492 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.800469492
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.3247292453
Short name T471
Test name
Test status
Simulation time 58871591 ps
CPU time 0.82 seconds
Started Dec 20 12:53:55 PM PST 23
Finished Dec 20 12:54:05 PM PST 23
Peak memory 214380 kb
Host smart-5142472d-1ee5-4f6a-a58c-fe7dc5d60530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247292453 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.3247292453
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.2826107004
Short name T466
Test name
Test status
Simulation time 18127500 ps
CPU time 0.89 seconds
Started Dec 20 12:53:52 PM PST 23
Finished Dec 20 12:54:01 PM PST 23
Peak memory 204980 kb
Host smart-e43b24af-1820-4a75-b03b-191d0f593d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826107004 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.2826107004
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.283378991
Short name T871
Test name
Test status
Simulation time 111183355 ps
CPU time 2.57 seconds
Started Dec 20 12:53:56 PM PST 23
Finished Dec 20 12:54:08 PM PST 23
Peak memory 205852 kb
Host smart-ffbb9478-3311-4b72-8242-e65882d79187
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283378991 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.283378991
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.2620498944
Short name T503
Test name
Test status
Simulation time 94418992972 ps
CPU time 1073.38 seconds
Started Dec 20 12:53:53 PM PST 23
Finished Dec 20 01:11:54 PM PST 23
Peak memory 214708 kb
Host smart-b9b629d3-79b1-49fb-94a8-2dec1dbfc5c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620498944 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.2620498944
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.3569173004
Short name T868
Test name
Test status
Simulation time 63074907 ps
CPU time 0.97 seconds
Started Dec 20 12:53:54 PM PST 23
Finished Dec 20 12:54:03 PM PST 23
Peak memory 205248 kb
Host smart-c259fa32-fa0e-4e80-972f-694627764363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569173004 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.3569173004
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.2575827470
Short name T910
Test name
Test status
Simulation time 21352407 ps
CPU time 0.98 seconds
Started Dec 20 12:53:53 PM PST 23
Finished Dec 20 12:54:01 PM PST 23
Peak memory 204744 kb
Host smart-f1c6b0af-08eb-4f6c-8e49-dc7e9edbbc1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575827470 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.2575827470
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.3152552526
Short name T955
Test name
Test status
Simulation time 23153745 ps
CPU time 0.85 seconds
Started Dec 20 12:53:55 PM PST 23
Finished Dec 20 12:54:05 PM PST 23
Peak memory 206228 kb
Host smart-4d285d21-b9ca-45d9-8cc5-8dbf501baa98
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152552526 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.3152552526
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_err.1424729183
Short name T512
Test name
Test status
Simulation time 39752239 ps
CPU time 0.83 seconds
Started Dec 20 12:53:52 PM PST 23
Finished Dec 20 12:54:01 PM PST 23
Peak memory 215632 kb
Host smart-8cfd6ff6-20bd-4036-a814-91578d85cddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424729183 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.1424729183
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.3048384667
Short name T679
Test name
Test status
Simulation time 34763335 ps
CPU time 1.08 seconds
Started Dec 20 12:53:53 PM PST 23
Finished Dec 20 12:54:02 PM PST 23
Peak memory 214020 kb
Host smart-dcd4657e-8dc2-4979-b0f2-1342dc199cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048384667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3048384667
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.931562266
Short name T825
Test name
Test status
Simulation time 31644217 ps
CPU time 0.97 seconds
Started Dec 20 12:53:56 PM PST 23
Finished Dec 20 12:54:07 PM PST 23
Peak memory 225512 kb
Host smart-17fe82d1-2ec1-4f37-86e7-dbf354d0759b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931562266 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.931562266
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.3457472248
Short name T643
Test name
Test status
Simulation time 22914279 ps
CPU time 0.89 seconds
Started Dec 20 12:53:53 PM PST 23
Finished Dec 20 12:54:01 PM PST 23
Peak memory 204712 kb
Host smart-2b6de506-91f4-44f8-8bfc-d83b7c1a61aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457472248 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.3457472248
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.511438890
Short name T684
Test name
Test status
Simulation time 409806115 ps
CPU time 3.98 seconds
Started Dec 20 12:53:55 PM PST 23
Finished Dec 20 12:54:08 PM PST 23
Peak memory 205860 kb
Host smart-5529fed3-cce2-4a31-8060-0a3b9830c9f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511438890 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.511438890
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.1161387046
Short name T701
Test name
Test status
Simulation time 86637097574 ps
CPU time 1969.44 seconds
Started Dec 20 12:53:53 PM PST 23
Finished Dec 20 01:26:50 PM PST 23
Peak memory 223384 kb
Host smart-98e712c3-5675-4145-80e1-0f3d039d644b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161387046 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.1161387046
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.1496692318
Short name T319
Test name
Test status
Simulation time 49100479 ps
CPU time 0.91 seconds
Started Dec 20 12:53:57 PM PST 23
Finished Dec 20 12:54:08 PM PST 23
Peak memory 205992 kb
Host smart-33ca4b40-4723-47f3-922a-79dd106c76fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496692318 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.1496692318
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.3867810171
Short name T599
Test name
Test status
Simulation time 33584234 ps
CPU time 0.76 seconds
Started Dec 20 12:53:55 PM PST 23
Finished Dec 20 12:54:04 PM PST 23
Peak memory 204252 kb
Host smart-70eee4fa-7a24-43b1-84fe-83a824a56d6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867810171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.3867810171
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_err.318972054
Short name T521
Test name
Test status
Simulation time 19368152 ps
CPU time 1.02 seconds
Started Dec 20 12:53:56 PM PST 23
Finished Dec 20 12:54:07 PM PST 23
Peak memory 215744 kb
Host smart-4474a9a1-927b-46a8-9c39-dc15fa2ee5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318972054 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.318972054
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.1824988276
Short name T755
Test name
Test status
Simulation time 36544848 ps
CPU time 1.69 seconds
Started Dec 20 12:53:54 PM PST 23
Finished Dec 20 12:54:04 PM PST 23
Peak memory 214164 kb
Host smart-70611654-b0e8-4baa-b5d3-cce5664d7331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824988276 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.1824988276
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.1210310495
Short name T89
Test name
Test status
Simulation time 28790146 ps
CPU time 0.92 seconds
Started Dec 20 12:53:56 PM PST 23
Finished Dec 20 12:54:07 PM PST 23
Peak memory 225288 kb
Host smart-c02bd7dd-0b3d-4ecd-bcbc-a78f6846ca99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210310495 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.1210310495
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.2026560189
Short name T484
Test name
Test status
Simulation time 49431406 ps
CPU time 0.84 seconds
Started Dec 20 12:53:56 PM PST 23
Finished Dec 20 12:54:05 PM PST 23
Peak memory 204704 kb
Host smart-b9dd1563-dbe0-414c-9826-97a36d76840b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026560189 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.2026560189
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.3589589490
Short name T727
Test name
Test status
Simulation time 190632554 ps
CPU time 3.81 seconds
Started Dec 20 12:53:50 PM PST 23
Finished Dec 20 12:54:01 PM PST 23
Peak memory 214144 kb
Host smart-1a534991-e0ce-4d7b-a04a-082cab1406f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589589490 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.3589589490
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.1229617713
Short name T573
Test name
Test status
Simulation time 145825354177 ps
CPU time 525.27 seconds
Started Dec 20 12:53:57 PM PST 23
Finished Dec 20 01:02:52 PM PST 23
Peak memory 215164 kb
Host smart-934b3e8f-0a66-4f08-96c0-43dccf492b86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229617713 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.1229617713
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.241433115
Short name T49
Test name
Test status
Simulation time 33001754 ps
CPU time 0.95 seconds
Started Dec 20 12:53:53 PM PST 23
Finished Dec 20 12:54:02 PM PST 23
Peak memory 205236 kb
Host smart-8fe33604-4326-4c72-9f84-ffacec517354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241433115 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.241433115
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.462046450
Short name T459
Test name
Test status
Simulation time 28051204 ps
CPU time 0.86 seconds
Started Dec 20 12:53:54 PM PST 23
Finished Dec 20 12:54:03 PM PST 23
Peak memory 204720 kb
Host smart-eb9ebde2-fc9b-4667-9489-239cea9ef582
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462046450 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.462046450
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.2751636477
Short name T119
Test name
Test status
Simulation time 73696603 ps
CPU time 0.78 seconds
Started Dec 20 12:53:56 PM PST 23
Finished Dec 20 12:54:06 PM PST 23
Peak memory 214392 kb
Host smart-bde65302-6468-485f-bac9-6783510fa9e3
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751636477 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2751636477
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.3546937799
Short name T219
Test name
Test status
Simulation time 335730349 ps
CPU time 1.2 seconds
Started Dec 20 12:53:54 PM PST 23
Finished Dec 20 12:54:04 PM PST 23
Peak memory 214720 kb
Host smart-e94ca9d0-9cd4-4add-836c-fe619327c27d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546937799 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.3546937799
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.360798627
Short name T176
Test name
Test status
Simulation time 30439677 ps
CPU time 0.95 seconds
Started Dec 20 12:53:56 PM PST 23
Finished Dec 20 12:54:05 PM PST 23
Peak memory 221632 kb
Host smart-a6f6ae77-3d27-4fe1-a327-3e7cf69a94eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360798627 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.360798627
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.3405091766
Short name T846
Test name
Test status
Simulation time 48971492 ps
CPU time 1.13 seconds
Started Dec 20 12:53:57 PM PST 23
Finished Dec 20 12:54:08 PM PST 23
Peak memory 205676 kb
Host smart-35dd1ae1-3838-406a-9395-372f21dcd856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405091766 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3405091766
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.2019808281
Short name T901
Test name
Test status
Simulation time 20944441 ps
CPU time 0.9 seconds
Started Dec 20 12:53:55 PM PST 23
Finished Dec 20 12:54:04 PM PST 23
Peak memory 214428 kb
Host smart-93eae797-ff5b-40fa-97c9-f3ba0651c391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019808281 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.2019808281
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.63095417
Short name T824
Test name
Test status
Simulation time 46281996 ps
CPU time 0.84 seconds
Started Dec 20 12:53:54 PM PST 23
Finished Dec 20 12:54:03 PM PST 23
Peak memory 204968 kb
Host smart-3795f0f3-bc93-42ac-a496-0c76bcf545a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63095417 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.63095417
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.2343205505
Short name T586
Test name
Test status
Simulation time 487775405 ps
CPU time 3.12 seconds
Started Dec 20 12:53:56 PM PST 23
Finished Dec 20 12:54:09 PM PST 23
Peak memory 205840 kb
Host smart-5f5a6f5e-de9d-41b3-ba94-8de164541cb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343205505 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2343205505
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.2467724911
Short name T571
Test name
Test status
Simulation time 187875963480 ps
CPU time 1025.15 seconds
Started Dec 20 12:53:54 PM PST 23
Finished Dec 20 01:11:08 PM PST 23
Peak memory 214988 kb
Host smart-c8604db9-ebdd-4cf4-964a-0444d6e0642a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467724911 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.2467724911
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert_test.1150157198
Short name T713
Test name
Test status
Simulation time 38390972 ps
CPU time 0.79 seconds
Started Dec 20 12:52:32 PM PST 23
Finished Dec 20 12:52:46 PM PST 23
Peak memory 204384 kb
Host smart-984fda15-a492-4808-9468-75c69146e520
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150157198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.1150157198
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.4031673020
Short name T177
Test name
Test status
Simulation time 12326640 ps
CPU time 0.85 seconds
Started Dec 20 12:52:30 PM PST 23
Finished Dec 20 12:52:44 PM PST 23
Peak memory 214648 kb
Host smart-c77e004c-606d-4e19-b872-2d9a3bb22502
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031673020 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.4031673020
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.729632227
Short name T516
Test name
Test status
Simulation time 31131807 ps
CPU time 1 seconds
Started Dec 20 12:52:30 PM PST 23
Finished Dec 20 12:52:44 PM PST 23
Peak memory 214580 kb
Host smart-f3bc229d-c873-48d3-bf28-01fdd4008104
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729632227 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_dis
able_auto_req_mode.729632227
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.3583515250
Short name T164
Test name
Test status
Simulation time 79371623 ps
CPU time 0.98 seconds
Started Dec 20 12:52:31 PM PST 23
Finished Dec 20 12:52:45 PM PST 23
Peak memory 217060 kb
Host smart-4c80cd30-4958-41cb-afc3-3294a90bcafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583515250 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.3583515250
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.929696144
Short name T497
Test name
Test status
Simulation time 30471978 ps
CPU time 0.95 seconds
Started Dec 20 12:52:32 PM PST 23
Finished Dec 20 12:52:46 PM PST 23
Peak memory 205696 kb
Host smart-5dae1ce9-74ea-407c-b456-269a7696e1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929696144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.929696144
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.2343818984
Short name T85
Test name
Test status
Simulation time 19740507 ps
CPU time 1.04 seconds
Started Dec 20 12:52:34 PM PST 23
Finished Dec 20 12:52:48 PM PST 23
Peak memory 214592 kb
Host smart-22d91ea3-e4b7-4a48-bb5c-e7e68d1a0efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343818984 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.2343818984
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.3716631404
Short name T242
Test name
Test status
Simulation time 74121357 ps
CPU time 0.91 seconds
Started Dec 20 12:52:28 PM PST 23
Finished Dec 20 12:52:43 PM PST 23
Peak memory 204804 kb
Host smart-d0087f2c-fa74-4c5e-93a3-cac26abae7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716631404 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.3716631404
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.4089365982
Short name T553
Test name
Test status
Simulation time 60519088 ps
CPU time 0.83 seconds
Started Dec 20 12:52:28 PM PST 23
Finished Dec 20 12:52:43 PM PST 23
Peak memory 204772 kb
Host smart-f53728d2-247d-4bee-8fde-3f70e498880e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089365982 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.4089365982
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.28116558
Short name T68
Test name
Test status
Simulation time 38890426 ps
CPU time 0.99 seconds
Started Dec 20 12:52:29 PM PST 23
Finished Dec 20 12:52:43 PM PST 23
Peak memory 204784 kb
Host smart-a14ab82e-ed7f-4b83-a5fe-1471a7726d63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28116558 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.28116558
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.1299058622
Short name T626
Test name
Test status
Simulation time 55961741053 ps
CPU time 387.92 seconds
Started Dec 20 12:52:29 PM PST 23
Finished Dec 20 12:59:11 PM PST 23
Peak memory 214612 kb
Host smart-d7144e91-4ecc-4b5e-9967-cfa9314b0875
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299058622 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.1299058622
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.1685338489
Short name T231
Test name
Test status
Simulation time 18377091 ps
CPU time 1.01 seconds
Started Dec 20 12:53:52 PM PST 23
Finished Dec 20 12:54:01 PM PST 23
Peak memory 215848 kb
Host smart-c392b23a-5d16-4803-a740-904f53f7882f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685338489 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.1685338489
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.2204027818
Short name T876
Test name
Test status
Simulation time 56235269 ps
CPU time 0.94 seconds
Started Dec 20 12:53:56 PM PST 23
Finished Dec 20 12:54:06 PM PST 23
Peak memory 204984 kb
Host smart-d13f0d81-5e08-4e43-b374-942a80a76a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204027818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.2204027818
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.1398681584
Short name T65
Test name
Test status
Simulation time 27792188 ps
CPU time 0.79 seconds
Started Dec 20 12:53:52 PM PST 23
Finished Dec 20 12:54:00 PM PST 23
Peak memory 215608 kb
Host smart-657ca06a-8ad1-448d-be7a-4251bbcf9c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398681584 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.1398681584
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.988851298
Short name T253
Test name
Test status
Simulation time 69518438 ps
CPU time 1.07 seconds
Started Dec 20 12:53:53 PM PST 23
Finished Dec 20 12:54:02 PM PST 23
Peak memory 214300 kb
Host smart-e036db8b-c72c-4f5f-b50b-f388091c35c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988851298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.988851298
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.3080693700
Short name T760
Test name
Test status
Simulation time 21818225 ps
CPU time 0.88 seconds
Started Dec 20 12:53:53 PM PST 23
Finished Dec 20 12:54:02 PM PST 23
Peak memory 215664 kb
Host smart-945a13dc-de7e-4ab0-9ae3-d867ee6d49ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080693700 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.3080693700
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.3077941777
Short name T508
Test name
Test status
Simulation time 208090072 ps
CPU time 2.37 seconds
Started Dec 20 12:53:56 PM PST 23
Finished Dec 20 12:54:08 PM PST 23
Peak memory 214204 kb
Host smart-dcf9bfb4-16da-4f07-9057-600da8658d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077941777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3077941777
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.2278337470
Short name T78
Test name
Test status
Simulation time 27287707 ps
CPU time 0.94 seconds
Started Dec 20 12:53:55 PM PST 23
Finished Dec 20 12:54:04 PM PST 23
Peak memory 215728 kb
Host smart-e1fa6474-2757-4a0d-92d5-ed73bc5f7b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278337470 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.2278337470
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.1130653544
Short name T766
Test name
Test status
Simulation time 32488302 ps
CPU time 0.94 seconds
Started Dec 20 12:53:53 PM PST 23
Finished Dec 20 12:54:01 PM PST 23
Peak memory 205188 kb
Host smart-d1dc6fa4-4c24-4fb3-876a-8366203598ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130653544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.1130653544
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_genbits.2346687950
Short name T600
Test name
Test status
Simulation time 252861547 ps
CPU time 1.05 seconds
Started Dec 20 12:53:55 PM PST 23
Finished Dec 20 12:54:04 PM PST 23
Peak memory 205556 kb
Host smart-96b6b382-855e-428b-9fca-fac418e52886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346687950 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.2346687950
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.2079016406
Short name T152
Test name
Test status
Simulation time 19418670 ps
CPU time 1.12 seconds
Started Dec 20 12:54:35 PM PST 23
Finished Dec 20 12:54:49 PM PST 23
Peak memory 228280 kb
Host smart-67eba48b-6ba8-4805-97ab-a11ec0b3c731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079016406 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.2079016406
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.638568445
Short name T61
Test name
Test status
Simulation time 25620794 ps
CPU time 0.89 seconds
Started Dec 20 12:53:56 PM PST 23
Finished Dec 20 12:54:06 PM PST 23
Peak memory 205140 kb
Host smart-0f9af127-43ec-4b22-b322-b531ffe8691e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638568445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.638568445
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.1892314714
Short name T130
Test name
Test status
Simulation time 33538161 ps
CPU time 1.12 seconds
Started Dec 20 12:54:33 PM PST 23
Finished Dec 20 12:54:48 PM PST 23
Peak memory 228312 kb
Host smart-21523236-e0f2-4d4e-a1d1-9ce80d1f7598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892314714 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.1892314714
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.235899179
Short name T254
Test name
Test status
Simulation time 33669029 ps
CPU time 0.81 seconds
Started Dec 20 12:54:29 PM PST 23
Finished Dec 20 12:54:44 PM PST 23
Peak memory 205020 kb
Host smart-75257496-50c2-4ccd-b5d9-72feb4eb5016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235899179 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.235899179
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.1510003543
Short name T926
Test name
Test status
Simulation time 71957404 ps
CPU time 1.09 seconds
Started Dec 20 12:54:29 PM PST 23
Finished Dec 20 12:54:44 PM PST 23
Peak memory 214836 kb
Host smart-1ef21752-de6d-4b72-91fd-583ed1529ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510003543 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.1510003543
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.109131977
Short name T75
Test name
Test status
Simulation time 14583113 ps
CPU time 0.97 seconds
Started Dec 20 12:54:32 PM PST 23
Finished Dec 20 12:54:47 PM PST 23
Peak memory 205336 kb
Host smart-bc31a125-a834-4de2-a482-47750d733a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109131977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.109131977
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.394249174
Short name T663
Test name
Test status
Simulation time 52796581 ps
CPU time 0.77 seconds
Started Dec 20 12:54:32 PM PST 23
Finished Dec 20 12:54:47 PM PST 23
Peak memory 215836 kb
Host smart-fe583bea-b92a-46fc-b078-f7ff16814208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394249174 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.394249174
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.3934038544
Short name T594
Test name
Test status
Simulation time 26801029 ps
CPU time 0.96 seconds
Started Dec 20 12:54:31 PM PST 23
Finished Dec 20 12:54:46 PM PST 23
Peak memory 205308 kb
Host smart-487f770b-85a6-4120-9bda-1c159b2d59e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934038544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.3934038544
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.1099909573
Short name T675
Test name
Test status
Simulation time 221393752 ps
CPU time 1.14 seconds
Started Dec 20 12:54:31 PM PST 23
Finished Dec 20 12:54:46 PM PST 23
Peak memory 221760 kb
Host smart-03e07654-fd24-4a01-821c-b5b0457ee710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099909573 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.1099909573
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.3057642464
Short name T290
Test name
Test status
Simulation time 31681218 ps
CPU time 1.48 seconds
Started Dec 20 12:54:41 PM PST 23
Finished Dec 20 12:54:53 PM PST 23
Peak memory 214196 kb
Host smart-584acba9-05ec-4e34-8bae-276d40bfced7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057642464 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3057642464
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.1131397133
Short name T735
Test name
Test status
Simulation time 51266770 ps
CPU time 0.96 seconds
Started Dec 20 12:52:30 PM PST 23
Finished Dec 20 12:52:44 PM PST 23
Peak memory 205316 kb
Host smart-8bc9c73a-9ab5-4756-832b-9ed1bb27065e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131397133 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.1131397133
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.1068342589
Short name T874
Test name
Test status
Simulation time 13965853 ps
CPU time 0.84 seconds
Started Dec 20 12:52:30 PM PST 23
Finished Dec 20 12:52:44 PM PST 23
Peak memory 204584 kb
Host smart-747ff806-6d60-4bd6-ad7e-b013ffa47434
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068342589 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.1068342589
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.2010156203
Short name T114
Test name
Test status
Simulation time 13286759 ps
CPU time 0.92 seconds
Started Dec 20 12:52:30 PM PST 23
Finished Dec 20 12:52:44 PM PST 23
Peak memory 214512 kb
Host smart-cf4dbaef-6112-4050-9590-f6073045056e
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010156203 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.2010156203
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.897193664
Short name T228
Test name
Test status
Simulation time 62515747 ps
CPU time 1.01 seconds
Started Dec 20 12:52:37 PM PST 23
Finished Dec 20 12:52:50 PM PST 23
Peak memory 214668 kb
Host smart-e0be31b5-2c91-4f3a-be52-cb8f6af26972
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897193664 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_dis
able_auto_req_mode.897193664
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.4117788670
Short name T66
Test name
Test status
Simulation time 23278129 ps
CPU time 0.96 seconds
Started Dec 20 12:52:30 PM PST 23
Finished Dec 20 12:52:44 PM PST 23
Peak memory 215796 kb
Host smart-66500c74-bbef-4e8e-8993-6fc0d0cbe3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117788670 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.4117788670
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.3122313239
Short name T863
Test name
Test status
Simulation time 72099598 ps
CPU time 1.9 seconds
Started Dec 20 12:52:29 PM PST 23
Finished Dec 20 12:52:44 PM PST 23
Peak memory 214200 kb
Host smart-273ff89d-79a6-45e3-ac58-22c6836933fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122313239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.3122313239
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.79943987
Short name T82
Test name
Test status
Simulation time 23685252 ps
CPU time 0.93 seconds
Started Dec 20 12:52:30 PM PST 23
Finished Dec 20 12:52:44 PM PST 23
Peak memory 214496 kb
Host smart-1ff9db59-6b3c-4e16-b3f0-f7dba1630561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79943987 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.79943987
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.589384581
Short name T240
Test name
Test status
Simulation time 21121714 ps
CPU time 0.87 seconds
Started Dec 20 12:52:34 PM PST 23
Finished Dec 20 12:52:48 PM PST 23
Peak memory 205024 kb
Host smart-eb8ec7fd-0436-4ac4-a18e-9c70bc4d527a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589384581 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.589384581
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.2407594312
Short name T524
Test name
Test status
Simulation time 37127892 ps
CPU time 0.8 seconds
Started Dec 20 12:52:29 PM PST 23
Finished Dec 20 12:52:43 PM PST 23
Peak memory 204788 kb
Host smart-77c78f98-dccb-4188-98df-118f901df082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407594312 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.2407594312
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.508102196
Short name T821
Test name
Test status
Simulation time 164253550 ps
CPU time 1.28 seconds
Started Dec 20 12:52:32 PM PST 23
Finished Dec 20 12:52:46 PM PST 23
Peak memory 205316 kb
Host smart-07fa0a55-0019-4a8a-8a09-73c70c6588af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508102196 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.508102196
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.457910193
Short name T875
Test name
Test status
Simulation time 45207173023 ps
CPU time 278.82 seconds
Started Dec 20 12:52:30 PM PST 23
Finished Dec 20 12:57:22 PM PST 23
Peak memory 217080 kb
Host smart-91d20d33-dc79-43c0-83a8-83bf1760c5d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457910193 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.457910193
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.2685101185
Short name T725
Test name
Test status
Simulation time 27910393 ps
CPU time 0.95 seconds
Started Dec 20 12:54:37 PM PST 23
Finished Dec 20 12:54:51 PM PST 23
Peak memory 221808 kb
Host smart-cf6b764d-1a09-4aa8-a3ed-829749bd6328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685101185 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.2685101185
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.1862219197
Short name T260
Test name
Test status
Simulation time 40448041 ps
CPU time 0.93 seconds
Started Dec 20 12:54:43 PM PST 23
Finished Dec 20 12:54:57 PM PST 23
Peak memory 205348 kb
Host smart-192280cf-d742-4806-a09c-67aaf7de81bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862219197 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.1862219197
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.1067727720
Short name T771
Test name
Test status
Simulation time 20111091 ps
CPU time 1.12 seconds
Started Dec 20 12:54:38 PM PST 23
Finished Dec 20 12:54:52 PM PST 23
Peak memory 228580 kb
Host smart-5845ab8f-a60b-4556-8f34-21a8dead4f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067727720 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.1067727720
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.3544376172
Short name T609
Test name
Test status
Simulation time 118267411 ps
CPU time 1 seconds
Started Dec 20 12:54:41 PM PST 23
Finished Dec 20 12:54:53 PM PST 23
Peak memory 214132 kb
Host smart-5f4a9c65-8482-41eb-b987-8b16e3971f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544376172 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.3544376172
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.2975651543
Short name T163
Test name
Test status
Simulation time 33142177 ps
CPU time 0.83 seconds
Started Dec 20 12:54:41 PM PST 23
Finished Dec 20 12:54:52 PM PST 23
Peak memory 215512 kb
Host smart-b768b7b9-e569-4084-aafb-df462fc4cb93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975651543 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.2975651543
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.129401366
Short name T728
Test name
Test status
Simulation time 81206002 ps
CPU time 0.84 seconds
Started Dec 20 12:54:43 PM PST 23
Finished Dec 20 12:54:56 PM PST 23
Peak memory 205212 kb
Host smart-3e47b4b2-407e-44c7-88d1-85e6adfbed7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129401366 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.129401366
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.86873891
Short name T560
Test name
Test status
Simulation time 39553788 ps
CPU time 0.79 seconds
Started Dec 20 12:54:38 PM PST 23
Finished Dec 20 12:54:52 PM PST 23
Peak memory 214268 kb
Host smart-e7fd7ab6-4ea4-4379-8f4d-80c4591220a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86873891 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.86873891
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.3873191356
Short name T678
Test name
Test status
Simulation time 30344748 ps
CPU time 1.07 seconds
Started Dec 20 12:54:37 PM PST 23
Finished Dec 20 12:54:51 PM PST 23
Peak memory 214164 kb
Host smart-9f42dc29-fd5e-423c-8f33-7ea530ffaa1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873191356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.3873191356
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.3490302986
Short name T165
Test name
Test status
Simulation time 22830893 ps
CPU time 0.85 seconds
Started Dec 20 12:54:36 PM PST 23
Finished Dec 20 12:54:49 PM PST 23
Peak memory 215496 kb
Host smart-cf1aa761-dbd1-4a03-87c6-4513294db564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490302986 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.3490302986
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.1010259399
Short name T925
Test name
Test status
Simulation time 15614780 ps
CPU time 0.99 seconds
Started Dec 20 12:54:41 PM PST 23
Finished Dec 20 12:54:53 PM PST 23
Peak memory 214288 kb
Host smart-7b1b10f1-297a-4da1-bb9b-85b3d21e0112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010259399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.1010259399
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.863094931
Short name T711
Test name
Test status
Simulation time 22599808 ps
CPU time 0.9 seconds
Started Dec 20 12:54:48 PM PST 23
Finished Dec 20 12:55:04 PM PST 23
Peak memory 215764 kb
Host smart-3976f4d1-4391-40a3-b872-23663d99a989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863094931 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.863094931
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.2168616677
Short name T811
Test name
Test status
Simulation time 16968952 ps
CPU time 1.02 seconds
Started Dec 20 12:54:39 PM PST 23
Finished Dec 20 12:54:52 PM PST 23
Peak memory 205624 kb
Host smart-e148d8e2-c1dd-4c55-9fe9-f22789f45c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168616677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.2168616677
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.831261046
Short name T637
Test name
Test status
Simulation time 46263587 ps
CPU time 1.03 seconds
Started Dec 20 12:54:39 PM PST 23
Finished Dec 20 12:54:52 PM PST 23
Peak memory 214588 kb
Host smart-c74e5c1a-2f04-452a-a8ba-a3c78d92f953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831261046 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.831261046
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.3084125684
Short name T297
Test name
Test status
Simulation time 25411392 ps
CPU time 0.97 seconds
Started Dec 20 12:54:43 PM PST 23
Finished Dec 20 12:54:57 PM PST 23
Peak memory 205580 kb
Host smart-8445803e-d81a-4141-9212-ce78ca56efbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084125684 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.3084125684
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.4211747240
Short name T146
Test name
Test status
Simulation time 70326685 ps
CPU time 0.88 seconds
Started Dec 20 12:54:39 PM PST 23
Finished Dec 20 12:54:52 PM PST 23
Peak memory 215692 kb
Host smart-61f650f8-bdeb-4fe2-bf7f-1f69b82a78b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211747240 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.4211747240
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.2459863272
Short name T28
Test name
Test status
Simulation time 68662607 ps
CPU time 0.93 seconds
Started Dec 20 12:54:39 PM PST 23
Finished Dec 20 12:54:52 PM PST 23
Peak memory 205276 kb
Host smart-1ef9b158-091f-43a1-b867-25bd51b5c9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459863272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.2459863272
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.869474854
Short name T129
Test name
Test status
Simulation time 42532598 ps
CPU time 1.14 seconds
Started Dec 20 12:54:39 PM PST 23
Finished Dec 20 12:54:53 PM PST 23
Peak memory 214576 kb
Host smart-95df9763-e4c0-4ece-9f94-bef7c38460d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869474854 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.869474854
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.1767780995
Short name T74
Test name
Test status
Simulation time 19226008 ps
CPU time 1.15 seconds
Started Dec 20 12:54:39 PM PST 23
Finished Dec 20 12:54:52 PM PST 23
Peak memory 205712 kb
Host smart-802aa5b6-7353-429a-9481-736f935d1ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767780995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.1767780995
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.983097438
Short name T86
Test name
Test status
Simulation time 21327621 ps
CPU time 1.08 seconds
Started Dec 20 12:54:37 PM PST 23
Finished Dec 20 12:54:51 PM PST 23
Peak memory 214744 kb
Host smart-70cb518a-db35-4d20-b91d-cf68f44a6340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983097438 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.983097438
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.3455987180
Short name T470
Test name
Test status
Simulation time 54271289 ps
CPU time 0.89 seconds
Started Dec 20 12:54:39 PM PST 23
Finished Dec 20 12:54:52 PM PST 23
Peak memory 205204 kb
Host smart-51cfaffc-c1e1-461e-90f0-d1d753107abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455987180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.3455987180
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.3084576606
Short name T237
Test name
Test status
Simulation time 19751556 ps
CPU time 1 seconds
Started Dec 20 12:52:28 PM PST 23
Finished Dec 20 12:52:43 PM PST 23
Peak memory 206072 kb
Host smart-a41a966f-ce7e-48b4-879c-7d30a1200416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084576606 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.3084576606
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.2552054747
Short name T839
Test name
Test status
Simulation time 13908566 ps
CPU time 0.86 seconds
Started Dec 20 12:52:42 PM PST 23
Finished Dec 20 12:52:54 PM PST 23
Peak memory 204652 kb
Host smart-e4d87004-09be-46f5-a453-6c3a4fe9a0d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552054747 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.2552054747
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.374270455
Short name T498
Test name
Test status
Simulation time 36473090 ps
CPU time 0.82 seconds
Started Dec 20 12:52:32 PM PST 23
Finished Dec 20 12:52:45 PM PST 23
Peak memory 214424 kb
Host smart-e1f198d6-b0da-49df-b09a-2f9ea67b2179
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374270455 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.374270455
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.2736842274
Short name T848
Test name
Test status
Simulation time 26450322 ps
CPU time 1.05 seconds
Started Dec 20 12:52:45 PM PST 23
Finished Dec 20 12:52:58 PM PST 23
Peak memory 214624 kb
Host smart-247008c9-0d3d-4228-9904-dd8c92fba394
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736842274 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.2736842274
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.4109727474
Short name T621
Test name
Test status
Simulation time 46465948 ps
CPU time 0.94 seconds
Started Dec 20 12:52:27 PM PST 23
Finished Dec 20 12:52:42 PM PST 23
Peak memory 216028 kb
Host smart-59757df5-66df-4048-87e9-81f55c57a4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109727474 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.4109727474
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.2181417753
Short name T30
Test name
Test status
Simulation time 39551559 ps
CPU time 1.02 seconds
Started Dec 20 12:52:31 PM PST 23
Finished Dec 20 12:52:45 PM PST 23
Peak memory 205808 kb
Host smart-ccb668ea-88c4-4eaf-89f4-7e10b147ca76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181417753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.2181417753
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.1224525
Short name T719
Test name
Test status
Simulation time 20972269 ps
CPU time 0.98 seconds
Started Dec 20 12:52:30 PM PST 23
Finished Dec 20 12:52:44 PM PST 23
Peak memory 214392 kb
Host smart-4bd18aba-64b2-41d2-a694-21aa2ab3dc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224525 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.1224525
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.2757233018
Short name T325
Test name
Test status
Simulation time 40157261 ps
CPU time 0.84 seconds
Started Dec 20 12:52:29 PM PST 23
Finished Dec 20 12:52:43 PM PST 23
Peak memory 204780 kb
Host smart-6c717d51-3518-40e6-ab14-9c433e0dbbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757233018 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.2757233018
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.4164353920
Short name T62
Test name
Test status
Simulation time 12674200 ps
CPU time 0.83 seconds
Started Dec 20 12:52:28 PM PST 23
Finished Dec 20 12:52:42 PM PST 23
Peak memory 204656 kb
Host smart-e474055a-af1d-4c94-9a9e-259a0c8a4299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164353920 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.4164353920
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.3482448446
Short name T668
Test name
Test status
Simulation time 159905143 ps
CPU time 3.8 seconds
Started Dec 20 12:52:30 PM PST 23
Finished Dec 20 12:52:47 PM PST 23
Peak memory 206100 kb
Host smart-4a2aa54c-243d-47cf-b6da-89706c4e8fca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482448446 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.3482448446
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.2188670127
Short name T472
Test name
Test status
Simulation time 22141543506 ps
CPU time 464.4 seconds
Started Dec 20 12:52:30 PM PST 23
Finished Dec 20 01:00:28 PM PST 23
Peak memory 214504 kb
Host smart-5ce116a5-808a-4971-afaf-e5b7887fec4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188670127 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.2188670127
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.2786386763
Short name T221
Test name
Test status
Simulation time 43777893 ps
CPU time 1 seconds
Started Dec 20 12:54:38 PM PST 23
Finished Dec 20 12:54:51 PM PST 23
Peak memory 228316 kb
Host smart-13503ca7-d62b-4552-95d6-593260cdc37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786386763 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.2786386763
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.1251397880
Short name T965
Test name
Test status
Simulation time 76379281 ps
CPU time 1.2 seconds
Started Dec 20 12:54:38 PM PST 23
Finished Dec 20 12:54:51 PM PST 23
Peak memory 214212 kb
Host smart-0c8fb122-4ed0-4430-997f-8bd2a297c581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251397880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.1251397880
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.2798290815
Short name T635
Test name
Test status
Simulation time 24720671 ps
CPU time 1.13 seconds
Started Dec 20 12:54:39 PM PST 23
Finished Dec 20 12:54:53 PM PST 23
Peak memory 215064 kb
Host smart-5d77abc9-d1ed-42f7-81c4-b9592002a888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798290815 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.2798290815
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.1529710015
Short name T873
Test name
Test status
Simulation time 116748785 ps
CPU time 1.21 seconds
Started Dec 20 12:54:40 PM PST 23
Finished Dec 20 12:54:53 PM PST 23
Peak memory 214176 kb
Host smart-d531a196-d97d-41c9-810e-f0240d0254a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529710015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.1529710015
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.1051478083
Short name T220
Test name
Test status
Simulation time 20858516 ps
CPU time 1.09 seconds
Started Dec 20 12:54:42 PM PST 23
Finished Dec 20 12:54:55 PM PST 23
Peak memory 215952 kb
Host smart-b562db61-eb36-4425-b986-2cad7fd06689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051478083 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.1051478083
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.219939081
Short name T879
Test name
Test status
Simulation time 45823162 ps
CPU time 1.9 seconds
Started Dec 20 12:54:38 PM PST 23
Finished Dec 20 12:54:52 PM PST 23
Peak memory 214216 kb
Host smart-557801c9-a196-43e4-a714-c190c8148c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219939081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.219939081
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.3246489347
Short name T47
Test name
Test status
Simulation time 102398076 ps
CPU time 0.88 seconds
Started Dec 20 12:54:37 PM PST 23
Finished Dec 20 12:54:51 PM PST 23
Peak memory 221136 kb
Host smart-0901886e-1d30-4b4a-8ee3-e9cff40dfb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246489347 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.3246489347
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.865511340
Short name T872
Test name
Test status
Simulation time 41218842 ps
CPU time 0.9 seconds
Started Dec 20 12:54:43 PM PST 23
Finished Dec 20 12:54:57 PM PST 23
Peak memory 205088 kb
Host smart-4a06d866-1a6f-4b38-a5c0-a8e57cf53bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865511340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.865511340
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.2696885834
Short name T973
Test name
Test status
Simulation time 29007100 ps
CPU time 0.81 seconds
Started Dec 20 12:54:38 PM PST 23
Finished Dec 20 12:54:51 PM PST 23
Peak memory 215624 kb
Host smart-249a3973-fba4-4fb7-bc9c-4c25c8c070ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696885834 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.2696885834
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.1251303401
Short name T537
Test name
Test status
Simulation time 49342966 ps
CPU time 0.95 seconds
Started Dec 20 12:54:38 PM PST 23
Finished Dec 20 12:54:51 PM PST 23
Peak memory 205048 kb
Host smart-983d2678-99e6-4a58-b1b5-d95a6e4d7869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251303401 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.1251303401
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.4112227150
Short name T166
Test name
Test status
Simulation time 36294169 ps
CPU time 0.87 seconds
Started Dec 20 12:54:35 PM PST 23
Finished Dec 20 12:54:48 PM PST 23
Peak memory 220416 kb
Host smart-ed16b088-38d9-415f-b461-15f97eab4ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112227150 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.4112227150
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.1932960454
Short name T723
Test name
Test status
Simulation time 17794547 ps
CPU time 1.06 seconds
Started Dec 20 12:54:40 PM PST 23
Finished Dec 20 12:54:52 PM PST 23
Peak memory 205340 kb
Host smart-3664a2b1-4aa5-4b7a-965c-66ea2038039b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932960454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.1932960454
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.2419655053
Short name T145
Test name
Test status
Simulation time 19865544 ps
CPU time 1.39 seconds
Started Dec 20 12:54:35 PM PST 23
Finished Dec 20 12:54:49 PM PST 23
Peak memory 216008 kb
Host smart-b1cc42f7-6a86-4ee4-b99d-adb6bf1efd11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419655053 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.2419655053
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.3222989145
Short name T3
Test name
Test status
Simulation time 41384647 ps
CPU time 0.86 seconds
Started Dec 20 12:54:35 PM PST 23
Finished Dec 20 12:54:49 PM PST 23
Peak memory 205076 kb
Host smart-296efa3f-993a-4891-a0c4-fc1e133b77a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222989145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.3222989145
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.869658407
Short name T830
Test name
Test status
Simulation time 46240078 ps
CPU time 0.95 seconds
Started Dec 20 12:54:40 PM PST 23
Finished Dec 20 12:54:52 PM PST 23
Peak memory 215892 kb
Host smart-943c6c60-2cb2-4f76-9040-6ffac1d08336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869658407 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.869658407
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.1542278168
Short name T935
Test name
Test status
Simulation time 60102707 ps
CPU time 0.94 seconds
Started Dec 20 12:54:38 PM PST 23
Finished Dec 20 12:54:51 PM PST 23
Peak memory 205624 kb
Host smart-2eea3ec5-65d7-43ab-aaf5-edf5f9099770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542278168 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.1542278168
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.3236111548
Short name T877
Test name
Test status
Simulation time 19669085 ps
CPU time 1.16 seconds
Started Dec 20 12:54:38 PM PST 23
Finished Dec 20 12:54:51 PM PST 23
Peak memory 221608 kb
Host smart-065bb58e-ccb8-46a4-a277-b361df81d873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236111548 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.3236111548
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.2768930811
Short name T743
Test name
Test status
Simulation time 427695872 ps
CPU time 1.49 seconds
Started Dec 20 12:54:35 PM PST 23
Finished Dec 20 12:54:50 PM PST 23
Peak memory 214332 kb
Host smart-aae61276-b09b-4be9-abef-ce48d65ca355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768930811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.2768930811
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.1076034972
Short name T557
Test name
Test status
Simulation time 19156156 ps
CPU time 1 seconds
Started Dec 20 12:54:38 PM PST 23
Finished Dec 20 12:54:51 PM PST 23
Peak memory 215940 kb
Host smart-0c274153-1de6-49d6-9061-7942117e4406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076034972 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.1076034972
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.463016894
Short name T279
Test name
Test status
Simulation time 50861382 ps
CPU time 0.96 seconds
Started Dec 20 12:54:39 PM PST 23
Finished Dec 20 12:54:52 PM PST 23
Peak memory 214288 kb
Host smart-c3086aa1-0c64-4e58-b9c1-10c357d6dcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463016894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.463016894
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.1809210822
Short name T321
Test name
Test status
Simulation time 64175577 ps
CPU time 0.93 seconds
Started Dec 20 12:52:42 PM PST 23
Finished Dec 20 12:52:54 PM PST 23
Peak memory 205180 kb
Host smart-999972f2-6512-4d64-9606-0fec9e347790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809210822 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.1809210822
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.3475216044
Short name T533
Test name
Test status
Simulation time 33307961 ps
CPU time 0.94 seconds
Started Dec 20 12:52:41 PM PST 23
Finished Dec 20 12:52:53 PM PST 23
Peak memory 204764 kb
Host smart-63f52a82-80ac-485c-87da-39758ab8b8de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475216044 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.3475216044
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.4284868695
Short name T499
Test name
Test status
Simulation time 38111413 ps
CPU time 0.81 seconds
Started Dec 20 12:52:43 PM PST 23
Finished Dec 20 12:52:56 PM PST 23
Peak memory 214316 kb
Host smart-05d517d3-36ff-4ede-926d-eb9f51e2c929
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284868695 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.4284868695
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.3287725043
Short name T226
Test name
Test status
Simulation time 85088010 ps
CPU time 0.98 seconds
Started Dec 20 12:52:41 PM PST 23
Finished Dec 20 12:52:53 PM PST 23
Peak memory 214648 kb
Host smart-5f3cb96b-b3d3-4ea8-bf88-59badf85ba38
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287725043 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.3287725043
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.1017795809
Short name T816
Test name
Test status
Simulation time 19781145 ps
CPU time 1.01 seconds
Started Dec 20 12:52:44 PM PST 23
Finished Dec 20 12:52:57 PM PST 23
Peak memory 215832 kb
Host smart-780d5d8d-3062-437a-af51-2de29d635502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017795809 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.1017795809
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.629566761
Short name T691
Test name
Test status
Simulation time 29933326 ps
CPU time 0.96 seconds
Started Dec 20 12:52:43 PM PST 23
Finished Dec 20 12:52:55 PM PST 23
Peak memory 205608 kb
Host smart-bc1e6e58-f605-42c3-8ca2-fd9094f36366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629566761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.629566761
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.239567509
Short name T575
Test name
Test status
Simulation time 19409411 ps
CPU time 1.08 seconds
Started Dec 20 12:52:43 PM PST 23
Finished Dec 20 12:52:55 PM PST 23
Peak memory 221456 kb
Host smart-676eec2b-dd9d-4988-98eb-987bc41d5ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239567509 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.239567509
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.2491771232
Short name T307
Test name
Test status
Simulation time 39404938 ps
CPU time 0.83 seconds
Started Dec 20 12:52:43 PM PST 23
Finished Dec 20 12:52:55 PM PST 23
Peak memory 204688 kb
Host smart-d41a390e-daa3-41ae-84af-1b3ed0ba6260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491771232 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.2491771232
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.424001077
Short name T535
Test name
Test status
Simulation time 11872527 ps
CPU time 0.87 seconds
Started Dec 20 12:52:44 PM PST 23
Finished Dec 20 12:52:56 PM PST 23
Peak memory 204544 kb
Host smart-756e36c5-e0f8-4712-9262-f8ca18e83ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424001077 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.424001077
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.827083150
Short name T475
Test name
Test status
Simulation time 397452116 ps
CPU time 3.29 seconds
Started Dec 20 12:52:44 PM PST 23
Finished Dec 20 12:52:59 PM PST 23
Peak memory 206016 kb
Host smart-cddfb58e-4174-4f9d-adfd-2fd34c94b893
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827083150 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.827083150
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.3567721519
Short name T291
Test name
Test status
Simulation time 24675666144 ps
CPU time 617.41 seconds
Started Dec 20 12:52:42 PM PST 23
Finished Dec 20 01:03:10 PM PST 23
Peak memory 214636 kb
Host smart-57247cb9-d2fa-45fa-959b-9ae006717f69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567721519 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.3567721519
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.2155368180
Short name T6
Test name
Test status
Simulation time 95948821 ps
CPU time 1.22 seconds
Started Dec 20 12:54:39 PM PST 23
Finished Dec 20 12:54:52 PM PST 23
Peak memory 214604 kb
Host smart-b65b8198-6d89-4606-a32e-b28d12e34159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155368180 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.2155368180
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.2408697777
Short name T263
Test name
Test status
Simulation time 17598791 ps
CPU time 0.99 seconds
Started Dec 20 12:54:41 PM PST 23
Finished Dec 20 12:54:53 PM PST 23
Peak memory 205508 kb
Host smart-4c040fc7-4213-42b3-a8ff-c6938a7ba6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408697777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.2408697777
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.1748929174
Short name T880
Test name
Test status
Simulation time 24146172 ps
CPU time 1.03 seconds
Started Dec 20 12:54:44 PM PST 23
Finished Dec 20 12:54:58 PM PST 23
Peak memory 221540 kb
Host smart-1d267f70-7784-47cb-9356-4dcbae30283f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748929174 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.1748929174
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.2357728539
Short name T544
Test name
Test status
Simulation time 53307205 ps
CPU time 0.88 seconds
Started Dec 20 12:54:39 PM PST 23
Finished Dec 20 12:54:52 PM PST 23
Peak memory 204940 kb
Host smart-0d01c083-d9bf-410e-a30d-62d2ddc31747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357728539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.2357728539
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.4155434485
Short name T174
Test name
Test status
Simulation time 33326577 ps
CPU time 0.81 seconds
Started Dec 20 12:54:41 PM PST 23
Finished Dec 20 12:54:53 PM PST 23
Peak memory 215600 kb
Host smart-c8efc89b-8896-445d-97f5-a6d9a227387e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155434485 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.4155434485
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.3451315936
Short name T737
Test name
Test status
Simulation time 18283044 ps
CPU time 1.1 seconds
Started Dec 20 12:54:39 PM PST 23
Finished Dec 20 12:54:52 PM PST 23
Peak memory 205496 kb
Host smart-95e1b68b-e91d-4e7b-9719-dbaa4377600b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451315936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3451315936
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.4019404665
Short name T139
Test name
Test status
Simulation time 51364268 ps
CPU time 0.92 seconds
Started Dec 20 12:54:39 PM PST 23
Finished Dec 20 12:54:52 PM PST 23
Peak memory 214652 kb
Host smart-203a2d82-eb5e-4d86-b3ce-be18f975af70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019404665 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.4019404665
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.2070359650
Short name T656
Test name
Test status
Simulation time 95651638 ps
CPU time 0.93 seconds
Started Dec 20 12:54:38 PM PST 23
Finished Dec 20 12:54:51 PM PST 23
Peak memory 205316 kb
Host smart-f06352cb-690f-48a3-9a37-b551e22fdf58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070359650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.2070359650
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.961410166
Short name T140
Test name
Test status
Simulation time 26461573 ps
CPU time 1.26 seconds
Started Dec 20 12:54:41 PM PST 23
Finished Dec 20 12:54:54 PM PST 23
Peak memory 228344 kb
Host smart-0c48c50f-a9c3-4b37-be4f-a53072a911bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961410166 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.961410166
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.1592691120
Short name T265
Test name
Test status
Simulation time 19513575 ps
CPU time 0.97 seconds
Started Dec 20 12:54:44 PM PST 23
Finished Dec 20 12:54:59 PM PST 23
Peak memory 205300 kb
Host smart-d2c24250-a5d7-4d9c-a367-47362b7153d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592691120 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.1592691120
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.2987905407
Short name T613
Test name
Test status
Simulation time 33350532 ps
CPU time 1.17 seconds
Started Dec 20 12:54:42 PM PST 23
Finished Dec 20 12:54:56 PM PST 23
Peak memory 230120 kb
Host smart-fadda6e4-94f8-4a75-8412-8849dcdffdba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987905407 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.2987905407
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.3147206088
Short name T629
Test name
Test status
Simulation time 153100704 ps
CPU time 1.19 seconds
Started Dec 20 12:54:44 PM PST 23
Finished Dec 20 12:54:59 PM PST 23
Peak memory 205524 kb
Host smart-c10d10f8-57c7-43ff-83b0-1de937cc8587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147206088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.3147206088
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.1294998599
Short name T539
Test name
Test status
Simulation time 22914852 ps
CPU time 0.93 seconds
Started Dec 20 12:54:46 PM PST 23
Finished Dec 20 12:55:02 PM PST 23
Peak memory 215936 kb
Host smart-16a074a2-ab6c-4806-9223-6b5adec01d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294998599 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.1294998599
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.934486252
Short name T914
Test name
Test status
Simulation time 172265886 ps
CPU time 1.03 seconds
Started Dec 20 12:54:42 PM PST 23
Finished Dec 20 12:54:55 PM PST 23
Peak memory 205576 kb
Host smart-f6b2e41f-1b1c-4d5b-9be6-260a5132dda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934486252 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.934486252
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.637653997
Short name T555
Test name
Test status
Simulation time 29600081 ps
CPU time 0.9 seconds
Started Dec 20 12:54:45 PM PST 23
Finished Dec 20 12:54:59 PM PST 23
Peak memory 221244 kb
Host smart-68e32891-b2b1-4b77-92d0-39283fcecc8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637653997 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.637653997
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/88.edn_err.496982236
Short name T580
Test name
Test status
Simulation time 43262019 ps
CPU time 1.09 seconds
Started Dec 20 12:54:51 PM PST 23
Finished Dec 20 12:55:10 PM PST 23
Peak memory 213884 kb
Host smart-7e815c54-8fc0-4b71-a359-ffe3d1b17238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496982236 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.496982236
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.3475286226
Short name T845
Test name
Test status
Simulation time 110438284 ps
CPU time 2.17 seconds
Started Dec 20 12:55:01 PM PST 23
Finished Dec 20 12:55:24 PM PST 23
Peak memory 214356 kb
Host smart-ace0fc93-77fe-41ca-9b5c-c459a20791cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475286226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.3475286226
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.2645794952
Short name T158
Test name
Test status
Simulation time 36116814 ps
CPU time 0.8 seconds
Started Dec 20 12:54:57 PM PST 23
Finished Dec 20 12:55:18 PM PST 23
Peak memory 215480 kb
Host smart-78b88052-6371-486d-876d-59632df3f443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645794952 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.2645794952
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.2119580837
Short name T517
Test name
Test status
Simulation time 44406495 ps
CPU time 1.06 seconds
Started Dec 20 12:54:45 PM PST 23
Finished Dec 20 12:55:00 PM PST 23
Peak memory 205492 kb
Host smart-bd4cb9f5-bef6-4f65-abfa-324c9f59ed39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119580837 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.2119580837
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.3292849378
Short name T306
Test name
Test status
Simulation time 31141073 ps
CPU time 0.89 seconds
Started Dec 20 12:52:43 PM PST 23
Finished Dec 20 12:52:55 PM PST 23
Peak memory 205256 kb
Host smart-d7516a2c-b6a4-49bd-a5a3-e3f9bee8a8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292849378 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.3292849378
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.1301107800
Short name T566
Test name
Test status
Simulation time 32135510 ps
CPU time 0.73 seconds
Started Dec 20 12:52:40 PM PST 23
Finished Dec 20 12:52:52 PM PST 23
Peak memory 203780 kb
Host smart-e7eb0d7b-3ba5-4b55-913d-178dfecdc354
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301107800 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.1301107800
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.354924231
Short name T832
Test name
Test status
Simulation time 12850123 ps
CPU time 0.85 seconds
Started Dec 20 12:52:41 PM PST 23
Finished Dec 20 12:52:53 PM PST 23
Peak memory 214540 kb
Host smart-b8be0409-db09-4faf-a11e-09dd71c42cd6
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354924231 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.354924231
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.2622419866
Short name T76
Test name
Test status
Simulation time 129677632 ps
CPU time 1.04 seconds
Started Dec 20 12:52:44 PM PST 23
Finished Dec 20 12:52:56 PM PST 23
Peak memory 214684 kb
Host smart-e990fef2-7b2e-4b17-9f70-df16c5767d8b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622419866 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.2622419866
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.2010058467
Short name T141
Test name
Test status
Simulation time 38517177 ps
CPU time 1.07 seconds
Started Dec 20 12:52:43 PM PST 23
Finished Dec 20 12:52:56 PM PST 23
Peak memory 214560 kb
Host smart-4223f0ee-5d62-4a5f-9078-298dcc17d13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010058467 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.2010058467
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.2073814267
Short name T587
Test name
Test status
Simulation time 59464210 ps
CPU time 0.98 seconds
Started Dec 20 12:52:41 PM PST 23
Finished Dec 20 12:52:53 PM PST 23
Peak memory 205568 kb
Host smart-2a45f2ac-c192-454e-b8fb-11f93bc6f69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073814267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.2073814267
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.588610927
Short name T963
Test name
Test status
Simulation time 33096876 ps
CPU time 0.85 seconds
Started Dec 20 12:52:49 PM PST 23
Finished Dec 20 12:53:02 PM PST 23
Peak memory 214312 kb
Host smart-0d9386b8-fd94-448f-9793-d07d6cff91b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588610927 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.588610927
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_smoke.1788208900
Short name T493
Test name
Test status
Simulation time 46744980 ps
CPU time 0.85 seconds
Started Dec 20 12:52:43 PM PST 23
Finished Dec 20 12:52:55 PM PST 23
Peak memory 204924 kb
Host smart-9f66d4a8-c993-46bd-87fb-7f65280635de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788208900 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.1788208900
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.3675588970
Short name T864
Test name
Test status
Simulation time 152241430 ps
CPU time 2.45 seconds
Started Dec 20 12:52:42 PM PST 23
Finished Dec 20 12:52:55 PM PST 23
Peak memory 205908 kb
Host smart-e926fa62-c257-4ac9-9f2d-bf643e116aaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675588970 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.3675588970
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.3996451801
Short name T277
Test name
Test status
Simulation time 14638272182 ps
CPU time 317.79 seconds
Started Dec 20 12:52:42 PM PST 23
Finished Dec 20 12:58:10 PM PST 23
Peak memory 215052 kb
Host smart-4004713e-3db4-4ae1-92a4-8c9cc1abdcc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996451801 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.3996451801
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.2336318496
Short name T217
Test name
Test status
Simulation time 28792944 ps
CPU time 0.93 seconds
Started Dec 20 12:54:48 PM PST 23
Finished Dec 20 12:55:06 PM PST 23
Peak memory 216060 kb
Host smart-8439b731-b174-4268-aad3-f7930c265992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336318496 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.2336318496
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.207832426
Short name T745
Test name
Test status
Simulation time 12290823 ps
CPU time 0.89 seconds
Started Dec 20 12:54:55 PM PST 23
Finished Dec 20 12:55:14 PM PST 23
Peak memory 205068 kb
Host smart-660ebf08-917e-4006-b77f-28c7c8ed8465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207832426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.207832426
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.504792934
Short name T44
Test name
Test status
Simulation time 46430716 ps
CPU time 0.9 seconds
Started Dec 20 12:54:49 PM PST 23
Finished Dec 20 12:55:07 PM PST 23
Peak memory 221232 kb
Host smart-be405302-0fee-4aba-a169-8c42d4928f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504792934 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.504792934
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.2485579666
Short name T31
Test name
Test status
Simulation time 16995215 ps
CPU time 0.99 seconds
Started Dec 20 12:54:49 PM PST 23
Finished Dec 20 12:55:08 PM PST 23
Peak memory 205632 kb
Host smart-23807258-40e2-4083-bdf4-340f8f87d51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485579666 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.2485579666
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.3555849553
Short name T147
Test name
Test status
Simulation time 19845123 ps
CPU time 1.42 seconds
Started Dec 20 12:54:46 PM PST 23
Finished Dec 20 12:55:01 PM PST 23
Peak memory 229896 kb
Host smart-da707c73-58d6-40bc-a88f-7171bacf9786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555849553 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.3555849553
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.3375781081
Short name T56
Test name
Test status
Simulation time 17094973 ps
CPU time 0.93 seconds
Started Dec 20 12:54:52 PM PST 23
Finished Dec 20 12:55:11 PM PST 23
Peak memory 204952 kb
Host smart-f507d299-85cc-417a-b333-41c4cdc3d5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375781081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.3375781081
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.2164063140
Short name T138
Test name
Test status
Simulation time 23390918 ps
CPU time 1.18 seconds
Started Dec 20 12:54:50 PM PST 23
Finished Dec 20 12:55:09 PM PST 23
Peak memory 228444 kb
Host smart-bc4a28e1-93c5-46e7-9e9c-6bd9539b1906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164063140 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.2164063140
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.3180145221
Short name T334
Test name
Test status
Simulation time 74427818 ps
CPU time 1.22 seconds
Started Dec 20 12:54:53 PM PST 23
Finished Dec 20 12:55:13 PM PST 23
Peak memory 205516 kb
Host smart-d1248070-e92f-41a7-bf78-43de08224273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180145221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.3180145221
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.3538807775
Short name T159
Test name
Test status
Simulation time 20099488 ps
CPU time 1.03 seconds
Started Dec 20 12:54:55 PM PST 23
Finished Dec 20 12:55:14 PM PST 23
Peak memory 215656 kb
Host smart-0c2b1458-34bc-4e98-88d5-5fbe5ab77714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538807775 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.3538807775
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.1103384636
Short name T338
Test name
Test status
Simulation time 65950343 ps
CPU time 0.91 seconds
Started Dec 20 12:54:59 PM PST 23
Finished Dec 20 12:55:21 PM PST 23
Peak memory 204896 kb
Host smart-19744795-2874-42d1-8864-60413eaeb6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103384636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.1103384636
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.2009511393
Short name T968
Test name
Test status
Simulation time 52385317 ps
CPU time 0.95 seconds
Started Dec 20 12:54:50 PM PST 23
Finished Dec 20 12:55:09 PM PST 23
Peak memory 221892 kb
Host smart-ad6ba8c6-6531-463d-91db-3f1eaf83a4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009511393 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.2009511393
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.3221272164
Short name T712
Test name
Test status
Simulation time 16529361 ps
CPU time 1.09 seconds
Started Dec 20 12:55:01 PM PST 23
Finished Dec 20 12:55:23 PM PST 23
Peak memory 205504 kb
Host smart-efea6d53-c0f4-4a88-a76a-785d40afb8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221272164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.3221272164
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.3865811562
Short name T215
Test name
Test status
Simulation time 19161801 ps
CPU time 1.03 seconds
Started Dec 20 12:55:01 PM PST 23
Finished Dec 20 12:55:23 PM PST 23
Peak memory 214848 kb
Host smart-be79f9c8-302d-4e67-bf2e-bec518a7bdbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865811562 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.3865811562
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.413645461
Short name T710
Test name
Test status
Simulation time 25101076 ps
CPU time 0.92 seconds
Started Dec 20 12:54:50 PM PST 23
Finished Dec 20 12:55:10 PM PST 23
Peak memory 205464 kb
Host smart-55ab8f17-35dc-4afa-9695-bd6e6e4956be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413645461 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.413645461
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.3385174250
Short name T655
Test name
Test status
Simulation time 69296510 ps
CPU time 0.91 seconds
Started Dec 20 12:54:51 PM PST 23
Finished Dec 20 12:55:10 PM PST 23
Peak memory 221184 kb
Host smart-005a54b5-80a9-4f64-9f2c-d18f06112410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385174250 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.3385174250
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.1776686693
Short name T827
Test name
Test status
Simulation time 14106528 ps
CPU time 1.04 seconds
Started Dec 20 12:54:52 PM PST 23
Finished Dec 20 12:55:11 PM PST 23
Peak memory 205528 kb
Host smart-a737812e-4deb-41a7-ba44-54ce6517a337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776686693 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.1776686693
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.2558668525
Short name T928
Test name
Test status
Simulation time 54876743 ps
CPU time 1.34 seconds
Started Dec 20 12:54:52 PM PST 23
Finished Dec 20 12:55:11 PM PST 23
Peak memory 227720 kb
Host smart-c2d7fb5c-a76c-48ef-93dd-fde1b9db1e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558668525 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.2558668525
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.202605486
Short name T870
Test name
Test status
Simulation time 35697848 ps
CPU time 1.05 seconds
Started Dec 20 12:54:55 PM PST 23
Finished Dec 20 12:55:14 PM PST 23
Peak memory 214116 kb
Host smart-e04bc15e-3b88-4a17-95d9-d7b713b3c595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202605486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.202605486
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.1674777915
Short name T172
Test name
Test status
Simulation time 21663173 ps
CPU time 0.98 seconds
Started Dec 20 12:54:57 PM PST 23
Finished Dec 20 12:55:18 PM PST 23
Peak memory 221632 kb
Host smart-603ef7d1-2344-4010-ac8d-f6c1b942eaef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674777915 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.1674777915
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.1752865669
Short name T109
Test name
Test status
Simulation time 42264987 ps
CPU time 1.13 seconds
Started Dec 20 12:54:59 PM PST 23
Finished Dec 20 12:55:21 PM PST 23
Peak memory 214096 kb
Host smart-a0e59cdf-2510-4f24-8056-24d427ef0968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752865669 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.1752865669
Directory /workspace/99.edn_genbits/latest
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