Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.75 99.02 92.39 96.79 91.45 98.62 99.77 99.20


Total test records in report: 975
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T793 /workspace/coverage/default/39.edn_err.3503845244 Dec 24 01:43:31 PM PST 23 Dec 24 01:43:34 PM PST 23 33129236 ps
T794 /workspace/coverage/default/180.edn_genbits.200052141 Dec 24 01:44:06 PM PST 23 Dec 24 01:44:24 PM PST 23 31605996 ps
T795 /workspace/coverage/default/14.edn_disable_auto_req_mode.1544666756 Dec 24 01:42:39 PM PST 23 Dec 24 01:42:53 PM PST 23 82155391 ps
T796 /workspace/coverage/default/37.edn_genbits.1132508478 Dec 24 01:42:58 PM PST 23 Dec 24 01:43:18 PM PST 23 78880360 ps
T797 /workspace/coverage/default/77.edn_genbits.2951289904 Dec 24 01:44:02 PM PST 23 Dec 24 01:44:09 PM PST 23 20828037 ps
T798 /workspace/coverage/default/4.edn_alert.1935855889 Dec 24 01:42:16 PM PST 23 Dec 24 01:42:20 PM PST 23 62546622 ps
T799 /workspace/coverage/default/242.edn_genbits.1573719177 Dec 24 01:44:06 PM PST 23 Dec 24 01:44:23 PM PST 23 61859338 ps
T324 /workspace/coverage/default/1.edn_regwen.668553729 Dec 24 01:41:52 PM PST 23 Dec 24 01:41:55 PM PST 23 12355096 ps
T800 /workspace/coverage/default/95.edn_genbits.2471496359 Dec 24 01:44:11 PM PST 23 Dec 24 01:44:31 PM PST 23 32288409 ps
T801 /workspace/coverage/default/13.edn_stress_all.988773879 Dec 24 01:42:47 PM PST 23 Dec 24 01:43:06 PM PST 23 30927616 ps
T802 /workspace/coverage/default/286.edn_genbits.3222498953 Dec 24 01:44:05 PM PST 23 Dec 24 01:44:21 PM PST 23 96679107 ps
T803 /workspace/coverage/default/158.edn_genbits.3297694221 Dec 24 01:44:06 PM PST 23 Dec 24 01:44:25 PM PST 23 60184394 ps
T804 /workspace/coverage/default/102.edn_genbits.684301325 Dec 24 01:44:05 PM PST 23 Dec 24 01:44:20 PM PST 23 84691809 ps
T805 /workspace/coverage/default/70.edn_genbits.2944974291 Dec 24 01:44:05 PM PST 23 Dec 24 01:44:20 PM PST 23 20077208 ps
T806 /workspace/coverage/default/34.edn_disable.1282752802 Dec 24 01:43:03 PM PST 23 Dec 24 01:43:20 PM PST 23 32233008 ps
T807 /workspace/coverage/default/42.edn_alert_test.417821059 Dec 24 01:43:43 PM PST 23 Dec 24 01:43:45 PM PST 23 50855597 ps
T345 /workspace/coverage/default/259.edn_genbits.1139037880 Dec 24 01:44:09 PM PST 23 Dec 24 01:44:30 PM PST 23 14956835 ps
T808 /workspace/coverage/default/47.edn_alert_test.3493511735 Dec 24 01:44:00 PM PST 23 Dec 24 01:44:06 PM PST 23 31347506 ps
T809 /workspace/coverage/default/0.edn_intr.166451934 Dec 24 01:41:51 PM PST 23 Dec 24 01:41:55 PM PST 23 37426467 ps
T131 /workspace/coverage/default/9.edn_err.2457546330 Dec 24 01:42:32 PM PST 23 Dec 24 01:42:34 PM PST 23 42966958 ps
T810 /workspace/coverage/default/36.edn_disable_auto_req_mode.2396237743 Dec 24 01:43:08 PM PST 23 Dec 24 01:43:22 PM PST 23 19048030 ps
T24 /workspace/coverage/default/1.edn_sec_cm.580026990 Dec 24 01:41:52 PM PST 23 Dec 24 01:42:00 PM PST 23 469076747 ps
T811 /workspace/coverage/default/46.edn_disable_auto_req_mode.3981972985 Dec 24 01:43:59 PM PST 23 Dec 24 01:44:02 PM PST 23 110987029 ps
T812 /workspace/coverage/default/37.edn_smoke.348201074 Dec 24 01:43:07 PM PST 23 Dec 24 01:43:22 PM PST 23 30195920 ps
T813 /workspace/coverage/default/62.edn_genbits.451623878 Dec 24 01:44:01 PM PST 23 Dec 24 01:44:09 PM PST 23 62100900 ps
T143 /workspace/coverage/default/14.edn_disable.2210111949 Dec 24 01:42:46 PM PST 23 Dec 24 01:43:06 PM PST 23 19832080 ps
T814 /workspace/coverage/default/41.edn_smoke.2811213032 Dec 24 01:43:30 PM PST 23 Dec 24 01:43:33 PM PST 23 15712042 ps
T815 /workspace/coverage/default/225.edn_genbits.3725978886 Dec 24 01:44:04 PM PST 23 Dec 24 01:44:20 PM PST 23 60459733 ps
T816 /workspace/coverage/default/74.edn_err.267210529 Dec 24 01:43:58 PM PST 23 Dec 24 01:44:00 PM PST 23 47234231 ps
T817 /workspace/coverage/default/0.edn_stress_all_with_rand_reset.2895426349 Dec 24 01:42:18 PM PST 23 Dec 24 02:01:28 PM PST 23 675115619542 ps
T818 /workspace/coverage/default/66.edn_genbits.1870522181 Dec 24 01:44:04 PM PST 23 Dec 24 01:44:17 PM PST 23 17949147 ps
T819 /workspace/coverage/default/28.edn_stress_all.4120180502 Dec 24 01:42:49 PM PST 23 Dec 24 01:43:14 PM PST 23 280730567 ps
T820 /workspace/coverage/default/44.edn_genbits.2914915350 Dec 24 01:43:53 PM PST 23 Dec 24 01:43:57 PM PST 23 35266227 ps
T821 /workspace/coverage/default/91.edn_genbits.1767501054 Dec 24 01:44:03 PM PST 23 Dec 24 01:44:14 PM PST 23 53558275 ps
T212 /workspace/coverage/default/47.edn_disable.1753041080 Dec 24 01:43:59 PM PST 23 Dec 24 01:44:03 PM PST 23 11774636 ps
T822 /workspace/coverage/default/48.edn_alert_test.3179115425 Dec 24 01:44:04 PM PST 23 Dec 24 01:44:18 PM PST 23 26062967 ps
T823 /workspace/coverage/default/88.edn_err.3448590291 Dec 24 01:44:00 PM PST 23 Dec 24 01:44:06 PM PST 23 22465943 ps
T824 /workspace/coverage/default/138.edn_genbits.982255701 Dec 24 01:44:07 PM PST 23 Dec 24 01:44:27 PM PST 23 37805339 ps
T825 /workspace/coverage/default/280.edn_genbits.721805555 Dec 24 01:44:08 PM PST 23 Dec 24 01:44:29 PM PST 23 116559343 ps
T826 /workspace/coverage/default/35.edn_disable_auto_req_mode.3218005931 Dec 24 01:43:12 PM PST 23 Dec 24 01:43:23 PM PST 23 33935175 ps
T827 /workspace/coverage/default/258.edn_genbits.3802672976 Dec 24 01:44:09 PM PST 23 Dec 24 01:44:30 PM PST 23 63022343 ps
T828 /workspace/coverage/default/133.edn_genbits.2076001670 Dec 24 01:44:03 PM PST 23 Dec 24 01:44:13 PM PST 23 20828911 ps
T829 /workspace/coverage/default/25.edn_alert_test.2399712278 Dec 24 01:42:48 PM PST 23 Dec 24 01:43:09 PM PST 23 17793528 ps
T132 /workspace/coverage/default/2.edn_disable.1393552799 Dec 24 01:42:15 PM PST 23 Dec 24 01:42:17 PM PST 23 38241629 ps
T830 /workspace/coverage/default/17.edn_genbits.1805844393 Dec 24 01:42:39 PM PST 23 Dec 24 01:42:53 PM PST 23 36541349 ps
T150 /workspace/coverage/default/23.edn_disable.2361145668 Dec 24 01:42:44 PM PST 23 Dec 24 01:43:04 PM PST 23 18819440 ps
T831 /workspace/coverage/default/23.edn_alert_test.3559761043 Dec 24 01:42:46 PM PST 23 Dec 24 01:43:05 PM PST 23 104399172 ps
T832 /workspace/coverage/default/60.edn_err.1877716316 Dec 24 01:43:59 PM PST 23 Dec 24 01:44:03 PM PST 23 33266981 ps
T833 /workspace/coverage/default/235.edn_genbits.2822168611 Dec 24 01:44:03 PM PST 23 Dec 24 01:44:14 PM PST 23 148075888 ps
T145 /workspace/coverage/default/44.edn_disable.1171551145 Dec 24 01:43:50 PM PST 23 Dec 24 01:43:52 PM PST 23 13255859 ps
T146 /workspace/coverage/default/5.edn_disable.1554686699 Dec 24 01:42:41 PM PST 23 Dec 24 01:42:53 PM PST 23 19529165 ps
T834 /workspace/coverage/default/36.edn_intr.3518225085 Dec 24 01:43:13 PM PST 23 Dec 24 01:43:23 PM PST 23 85806602 ps
T835 /workspace/coverage/default/41.edn_disable.3482295416 Dec 24 01:43:31 PM PST 23 Dec 24 01:43:34 PM PST 23 11764304 ps
T836 /workspace/coverage/default/227.edn_genbits.1933465738 Dec 24 01:44:04 PM PST 23 Dec 24 01:44:19 PM PST 23 62545202 ps
T837 /workspace/coverage/default/284.edn_genbits.3989810736 Dec 24 01:44:11 PM PST 23 Dec 24 01:44:32 PM PST 23 60159131 ps
T204 /workspace/coverage/default/0.edn_err.3266922369 Dec 24 01:41:51 PM PST 23 Dec 24 01:41:53 PM PST 23 53352824 ps
T838 /workspace/coverage/default/4.edn_disable_auto_req_mode.3102401539 Dec 24 01:42:43 PM PST 23 Dec 24 01:43:02 PM PST 23 29751191 ps
T839 /workspace/coverage/default/121.edn_genbits.2062974657 Dec 24 01:44:01 PM PST 23 Dec 24 01:44:08 PM PST 23 30408809 ps
T268 /workspace/coverage/default/194.edn_genbits.3912007466 Dec 24 01:44:04 PM PST 23 Dec 24 01:44:20 PM PST 23 215938787 ps
T323 /workspace/coverage/default/8.edn_regwen.60071576 Dec 24 01:42:16 PM PST 23 Dec 24 01:42:19 PM PST 23 15671878 ps
T106 /workspace/coverage/default/43.edn_disable_auto_req_mode.1623147119 Dec 24 01:43:59 PM PST 23 Dec 24 01:44:03 PM PST 23 24188565 ps
T318 /workspace/coverage/default/23.edn_alert.1720664012 Dec 24 01:42:47 PM PST 23 Dec 24 01:43:06 PM PST 23 35526986 ps
T840 /workspace/coverage/default/21.edn_disable_auto_req_mode.2687723635 Dec 24 01:42:46 PM PST 23 Dec 24 01:43:05 PM PST 23 26439387 ps
T206 /workspace/coverage/default/2.edn_err.2847022166 Dec 24 01:42:40 PM PST 23 Dec 24 01:42:53 PM PST 23 31658743 ps
T320 /workspace/coverage/default/13.edn_alert.1661355933 Dec 24 01:42:42 PM PST 23 Dec 24 01:42:54 PM PST 23 64361090 ps
T841 /workspace/coverage/default/10.edn_disable_auto_req_mode.1744832285 Dec 24 01:42:43 PM PST 23 Dec 24 01:43:00 PM PST 23 30978330 ps
T842 /workspace/coverage/default/167.edn_genbits.613189340 Dec 24 01:44:01 PM PST 23 Dec 24 01:44:08 PM PST 23 25272604 ps
T843 /workspace/coverage/default/12.edn_alert.2276120413 Dec 24 01:42:46 PM PST 23 Dec 24 01:43:05 PM PST 23 17840697 ps
T844 /workspace/coverage/default/29.edn_err.2996705081 Dec 24 01:42:47 PM PST 23 Dec 24 01:43:07 PM PST 23 31383505 ps
T845 /workspace/coverage/default/134.edn_genbits.3660886368 Dec 24 01:44:04 PM PST 23 Dec 24 01:44:19 PM PST 23 54208921 ps
T846 /workspace/coverage/default/29.edn_alert.2432160101 Dec 24 01:42:46 PM PST 23 Dec 24 01:43:05 PM PST 23 55905243 ps
T847 /workspace/coverage/default/22.edn_smoke.1956951306 Dec 24 01:43:02 PM PST 23 Dec 24 01:43:20 PM PST 23 34211207 ps
T848 /workspace/coverage/default/40.edn_genbits.390597421 Dec 24 01:43:30 PM PST 23 Dec 24 01:43:34 PM PST 23 139906849 ps
T849 /workspace/coverage/default/24.edn_disable_auto_req_mode.2564145432 Dec 24 01:42:47 PM PST 23 Dec 24 01:43:06 PM PST 23 24910022 ps
T850 /workspace/coverage/default/46.edn_alert.3095822679 Dec 24 01:44:06 PM PST 23 Dec 24 01:44:25 PM PST 23 62912244 ps
T195 /workspace/coverage/default/26.edn_disable_auto_req_mode.3135060960 Dec 24 01:42:49 PM PST 23 Dec 24 01:43:13 PM PST 23 94479939 ps
T851 /workspace/coverage/default/5.edn_genbits.2347555094 Dec 24 01:42:45 PM PST 23 Dec 24 01:43:05 PM PST 23 54617530 ps
T92 /workspace/coverage/default/40.edn_intr.366701494 Dec 24 01:43:34 PM PST 23 Dec 24 01:43:42 PM PST 23 32562587 ps
T852 /workspace/coverage/default/33.edn_intr.2807029632 Dec 24 01:43:00 PM PST 23 Dec 24 01:43:19 PM PST 23 39011935 ps
T853 /workspace/coverage/default/42.edn_disable_auto_req_mode.2598966606 Dec 24 01:43:31 PM PST 23 Dec 24 01:43:34 PM PST 23 41894564 ps
T854 /workspace/coverage/default/3.edn_stress_all.910492265 Dec 24 01:42:44 PM PST 23 Dec 24 01:43:06 PM PST 23 56294232 ps
T855 /workspace/coverage/default/14.edn_alert_test.493929770 Dec 24 01:42:49 PM PST 23 Dec 24 01:43:13 PM PST 23 75287215 ps
T856 /workspace/coverage/default/7.edn_disable_auto_req_mode.1218984651 Dec 24 01:42:22 PM PST 23 Dec 24 01:42:24 PM PST 23 13755636 ps
T346 /workspace/coverage/default/214.edn_genbits.1387495046 Dec 24 01:44:02 PM PST 23 Dec 24 01:44:10 PM PST 23 17152931 ps
T857 /workspace/coverage/default/15.edn_err.639848286 Dec 24 01:42:44 PM PST 23 Dec 24 01:43:05 PM PST 23 19061555 ps
T858 /workspace/coverage/default/94.edn_err.4097468202 Dec 24 01:44:05 PM PST 23 Dec 24 01:44:22 PM PST 23 23660172 ps
T859 /workspace/coverage/default/41.edn_stress_all_with_rand_reset.3238998512 Dec 24 01:43:27 PM PST 23 Dec 24 01:52:21 PM PST 23 85924882862 ps
T111 /workspace/coverage/default/59.edn_err.3522797420 Dec 24 01:43:57 PM PST 23 Dec 24 01:43:59 PM PST 23 44804029 ps
T860 /workspace/coverage/default/136.edn_genbits.1738922906 Dec 24 01:44:05 PM PST 23 Dec 24 01:44:20 PM PST 23 24968832 ps
T861 /workspace/coverage/default/29.edn_alert_test.4227311176 Dec 24 01:42:53 PM PST 23 Dec 24 01:43:16 PM PST 23 50120613 ps
T862 /workspace/coverage/default/101.edn_genbits.399368067 Dec 24 01:44:07 PM PST 23 Dec 24 01:44:27 PM PST 23 94490390 ps
T863 /workspace/coverage/default/19.edn_alert.1653155428 Dec 24 01:42:49 PM PST 23 Dec 24 01:43:13 PM PST 23 20751875 ps
T864 /workspace/coverage/default/34.edn_alert_test.2254994635 Dec 24 01:42:57 PM PST 23 Dec 24 01:43:17 PM PST 23 55404211 ps
T865 /workspace/coverage/default/13.edn_disable.2876920523 Dec 24 01:42:38 PM PST 23 Dec 24 01:42:53 PM PST 23 58778098 ps
T866 /workspace/coverage/default/26.edn_disable.1471056226 Dec 24 01:45:04 PM PST 23 Dec 24 01:45:06 PM PST 23 18874261 ps
T177 /workspace/coverage/default/51.edn_err.4220969995 Dec 24 01:44:21 PM PST 23 Dec 24 01:44:37 PM PST 23 33277818 ps
T327 /workspace/coverage/default/38.edn_alert.2357947112 Dec 24 01:43:33 PM PST 23 Dec 24 01:43:39 PM PST 23 36066891 ps
T867 /workspace/coverage/default/278.edn_genbits.2534317637 Dec 24 01:44:14 PM PST 23 Dec 24 01:44:35 PM PST 23 39844092 ps
T287 /workspace/coverage/default/51.edn_genbits.2485731877 Dec 24 01:44:08 PM PST 23 Dec 24 01:44:29 PM PST 23 21205107 ps
T868 /workspace/coverage/default/14.edn_err.2154209566 Dec 24 01:42:39 PM PST 23 Dec 24 01:42:53 PM PST 23 20962086 ps
T869 /workspace/coverage/default/47.edn_intr.1644024396 Dec 24 01:43:57 PM PST 23 Dec 24 01:43:59 PM PST 23 30871867 ps
T870 /workspace/coverage/default/3.edn_disable.1738457053 Dec 24 01:42:37 PM PST 23 Dec 24 01:42:44 PM PST 23 19021870 ps
T871 /workspace/coverage/default/18.edn_disable_auto_req_mode.4041996439 Dec 24 01:42:44 PM PST 23 Dec 24 01:43:05 PM PST 23 24804191 ps
T872 /workspace/coverage/default/45.edn_err.599057745 Dec 24 01:44:02 PM PST 23 Dec 24 01:44:10 PM PST 23 32263104 ps
T873 /workspace/coverage/default/4.edn_err.2421570796 Dec 24 01:42:18 PM PST 23 Dec 24 01:42:21 PM PST 23 42162812 ps
T874 /workspace/coverage/default/9.edn_alert.26393069 Dec 24 01:42:45 PM PST 23 Dec 24 01:43:05 PM PST 23 51629495 ps
T875 /workspace/coverage/default/17.edn_intr.1572895314 Dec 24 01:42:40 PM PST 23 Dec 24 01:42:53 PM PST 23 42557295 ps
T876 /workspace/coverage/default/127.edn_genbits.3743350694 Dec 24 01:44:02 PM PST 23 Dec 24 01:44:09 PM PST 23 15794408 ps
T194 /workspace/coverage/default/72.edn_err.2791137541 Dec 24 01:44:02 PM PST 23 Dec 24 01:44:10 PM PST 23 39153037 ps
T877 /workspace/coverage/default/32.edn_disable.32035627 Dec 24 01:43:04 PM PST 23 Dec 24 01:43:21 PM PST 23 57281780 ps
T878 /workspace/coverage/default/124.edn_genbits.3719192594 Dec 24 01:44:04 PM PST 23 Dec 24 01:44:18 PM PST 23 131445632 ps
T879 /workspace/coverage/default/81.edn_genbits.3336288845 Dec 24 01:43:59 PM PST 23 Dec 24 01:44:03 PM PST 23 63716331 ps
T329 /workspace/coverage/default/6.edn_regwen.1543967896 Dec 24 01:42:19 PM PST 23 Dec 24 01:42:22 PM PST 23 36286707 ps
T880 /workspace/coverage/default/248.edn_genbits.262006268 Dec 24 01:44:11 PM PST 23 Dec 24 01:44:32 PM PST 23 155924868 ps
T881 /workspace/coverage/default/10.edn_stress_all_with_rand_reset.4066501379 Dec 24 01:42:40 PM PST 23 Dec 24 01:59:03 PM PST 23 43898179914 ps
T882 /workspace/coverage/default/3.edn_intr.2357208723 Dec 24 01:42:38 PM PST 23 Dec 24 01:42:47 PM PST 23 20195459 ps
T883 /workspace/coverage/default/24.edn_intr.3208113695 Dec 24 01:42:52 PM PST 23 Dec 24 01:43:16 PM PST 23 30293506 ps
T884 /workspace/coverage/default/9.edn_disable.901370508 Dec 24 01:42:30 PM PST 23 Dec 24 01:42:32 PM PST 23 11255022 ps
T885 /workspace/coverage/default/52.edn_err.1409835472 Dec 24 01:44:04 PM PST 23 Dec 24 01:44:18 PM PST 23 25865104 ps
T196 /workspace/coverage/default/44.edn_disable_auto_req_mode.1248654565 Dec 24 01:43:58 PM PST 23 Dec 24 01:44:00 PM PST 23 58465820 ps
T886 /workspace/coverage/default/21.edn_alert.3350570511 Dec 24 01:42:42 PM PST 23 Dec 24 01:42:56 PM PST 23 41418111 ps
T887 /workspace/coverage/default/14.edn_genbits.3601883839 Dec 24 01:42:39 PM PST 23 Dec 24 01:42:54 PM PST 23 78661572 ps
T888 /workspace/coverage/default/34.edn_genbits.2868429053 Dec 24 01:43:08 PM PST 23 Dec 24 01:43:22 PM PST 23 25565607 ps
T889 /workspace/coverage/default/39.edn_alert.1650015376 Dec 24 01:43:39 PM PST 23 Dec 24 01:43:44 PM PST 23 65158722 ps
T890 /workspace/coverage/default/254.edn_genbits.2612744336 Dec 24 01:44:08 PM PST 23 Dec 24 01:44:28 PM PST 23 29043627 ps
T891 /workspace/coverage/default/130.edn_genbits.2161020814 Dec 24 01:44:04 PM PST 23 Dec 24 01:44:18 PM PST 23 202138294 ps
T892 /workspace/coverage/default/132.edn_genbits.2611280739 Dec 24 01:44:05 PM PST 23 Dec 24 01:44:20 PM PST 23 31365177 ps
T115 /workspace/coverage/default/48.edn_disable_auto_req_mode.451933839 Dec 24 01:44:12 PM PST 23 Dec 24 01:44:33 PM PST 23 19926173 ps
T44 /workspace/coverage/default/0.edn_sec_cm.3146874451 Dec 24 01:41:53 PM PST 23 Dec 24 01:42:05 PM PST 23 426737038 ps
T893 /workspace/coverage/default/166.edn_genbits.309577226 Dec 24 01:44:03 PM PST 23 Dec 24 01:44:16 PM PST 23 32364851 ps
T894 /workspace/coverage/default/39.edn_stress_all.3609863206 Dec 24 01:43:27 PM PST 23 Dec 24 01:43:31 PM PST 23 301503140 ps
T179 /workspace/coverage/default/37.edn_err.958386074 Dec 24 01:43:22 PM PST 23 Dec 24 01:43:25 PM PST 23 23163917 ps
T895 /workspace/coverage/default/5.edn_intr.1214326158 Dec 24 01:41:57 PM PST 23 Dec 24 01:42:04 PM PST 23 20856309 ps
T896 /workspace/coverage/default/174.edn_genbits.3483406409 Dec 24 01:44:04 PM PST 23 Dec 24 01:44:18 PM PST 23 56952018 ps
T897 /workspace/coverage/default/17.edn_disable.2923684753 Dec 24 01:42:46 PM PST 23 Dec 24 01:43:05 PM PST 23 17835948 ps
T898 /workspace/coverage/default/49.edn_err.3498056521 Dec 24 01:44:11 PM PST 23 Dec 24 01:44:32 PM PST 23 105539306 ps
T899 /workspace/coverage/default/73.edn_err.2145726005 Dec 24 01:44:00 PM PST 23 Dec 24 01:44:06 PM PST 23 30378942 ps
T900 /workspace/coverage/default/200.edn_genbits.3609442379 Dec 24 01:44:05 PM PST 23 Dec 24 01:44:20 PM PST 23 17873433 ps
T901 /workspace/coverage/default/42.edn_stress_all_with_rand_reset.2109519051 Dec 24 01:43:32 PM PST 23 Dec 24 01:49:25 PM PST 23 28489943219 ps
T902 /workspace/coverage/default/30.edn_disable_auto_req_mode.4123701276 Dec 24 01:42:53 PM PST 23 Dec 24 01:43:17 PM PST 23 149326869 ps
T903 /workspace/coverage/default/63.edn_genbits.1452302924 Dec 24 01:43:51 PM PST 23 Dec 24 01:43:56 PM PST 23 230237624 ps
T904 /workspace/coverage/default/47.edn_stress_all.2388896548 Dec 24 01:43:49 PM PST 23 Dec 24 01:43:54 PM PST 23 576394010 ps
T905 /workspace/coverage/default/29.edn_stress_all_with_rand_reset.3928493710 Dec 24 01:42:47 PM PST 23 Dec 24 02:04:01 PM PST 23 193809651122 ps
T107 /workspace/coverage/default/12.edn_disable_auto_req_mode.2735932482 Dec 24 01:42:43 PM PST 23 Dec 24 01:43:03 PM PST 23 28455866 ps
T906 /workspace/coverage/default/29.edn_disable_auto_req_mode.2304313028 Dec 24 01:42:50 PM PST 23 Dec 24 01:43:14 PM PST 23 20838687 ps
T907 /workspace/coverage/default/234.edn_genbits.2616279942 Dec 24 01:44:04 PM PST 23 Dec 24 01:44:18 PM PST 23 19268710 ps
T908 /workspace/coverage/default/11.edn_smoke.1449941317 Dec 24 01:42:48 PM PST 23 Dec 24 01:43:11 PM PST 23 14116638 ps
T909 /workspace/coverage/default/68.edn_err.2359110645 Dec 24 01:44:12 PM PST 23 Dec 24 01:44:33 PM PST 23 87331627 ps
T910 /workspace/coverage/default/111.edn_genbits.1534562186 Dec 24 01:44:02 PM PST 23 Dec 24 01:44:09 PM PST 23 19144901 ps
T911 /workspace/coverage/default/45.edn_smoke.1246444007 Dec 24 01:44:01 PM PST 23 Dec 24 01:44:08 PM PST 23 13741009 ps
T288 /workspace/coverage/default/295.edn_genbits.1230517632 Dec 24 01:44:14 PM PST 23 Dec 24 01:44:34 PM PST 23 29828107 ps
T912 /workspace/coverage/default/45.edn_alert.3541807292 Dec 24 01:44:01 PM PST 23 Dec 24 01:44:08 PM PST 23 20800907 ps
T913 /workspace/coverage/default/41.edn_genbits.1012548729 Dec 24 01:43:35 PM PST 23 Dec 24 01:43:43 PM PST 23 56760691 ps
T914 /workspace/coverage/default/45.edn_alert_test.3982689529 Dec 24 01:43:58 PM PST 23 Dec 24 01:44:00 PM PST 23 24234926 ps
T198 /workspace/coverage/default/21.edn_err.4150981891 Dec 24 01:42:45 PM PST 23 Dec 24 01:43:05 PM PST 23 24559638 ps
T915 /workspace/coverage/default/201.edn_genbits.1539391637 Dec 24 01:44:03 PM PST 23 Dec 24 01:44:15 PM PST 23 64369842 ps
T916 /workspace/coverage/default/2.edn_genbits.977065059 Dec 24 01:42:38 PM PST 23 Dec 24 01:42:50 PM PST 23 78857428 ps
T348 /workspace/coverage/default/96.edn_genbits.4008373392 Dec 24 01:44:04 PM PST 23 Dec 24 01:44:19 PM PST 23 17661521 ps
T917 /workspace/coverage/default/17.edn_smoke.1057107968 Dec 24 01:42:38 PM PST 23 Dec 24 01:42:53 PM PST 23 36388410 ps
T918 /workspace/coverage/default/32.edn_genbits.294177798 Dec 24 01:42:54 PM PST 23 Dec 24 01:43:19 PM PST 23 324324659 ps
T919 /workspace/coverage/default/170.edn_genbits.3337189757 Dec 24 01:44:03 PM PST 23 Dec 24 01:44:15 PM PST 23 23295793 ps
T920 /workspace/coverage/default/29.edn_stress_all.3036363978 Dec 24 01:42:46 PM PST 23 Dec 24 01:43:05 PM PST 23 99515916 ps
T45 /workspace/coverage/default/2.edn_sec_cm.1456491797 Dec 24 01:42:44 PM PST 23 Dec 24 01:43:07 PM PST 23 650077166 ps
T921 /workspace/coverage/default/11.edn_intr.2668924881 Dec 24 01:42:47 PM PST 23 Dec 24 01:43:08 PM PST 23 32665900 ps
T922 /workspace/coverage/default/173.edn_genbits.436121785 Dec 24 01:44:03 PM PST 23 Dec 24 01:44:12 PM PST 23 59627696 ps
T923 /workspace/coverage/default/8.edn_stress_all_with_rand_reset.1867747213 Dec 24 01:42:15 PM PST 23 Dec 24 02:19:02 PM PST 23 98494948218 ps
T148 /workspace/coverage/default/10.edn_disable.3975209908 Dec 24 01:42:45 PM PST 23 Dec 24 01:43:05 PM PST 23 12480751 ps
T924 /workspace/coverage/default/92.edn_genbits.2242597991 Dec 24 01:44:05 PM PST 23 Dec 24 01:44:20 PM PST 23 62523200 ps
T925 /workspace/coverage/default/87.edn_genbits.839638947 Dec 24 01:43:57 PM PST 23 Dec 24 01:43:59 PM PST 23 129262699 ps
T926 /workspace/coverage/default/45.edn_disable_auto_req_mode.4090741649 Dec 24 01:44:01 PM PST 23 Dec 24 01:44:08 PM PST 23 60660893 ps
T927 /workspace/coverage/default/71.edn_genbits.2846556244 Dec 24 01:44:06 PM PST 23 Dec 24 01:44:24 PM PST 23 37801142 ps
T928 /workspace/coverage/default/169.edn_genbits.2191919585 Dec 24 01:44:04 PM PST 23 Dec 24 01:44:19 PM PST 23 15412571 ps
T929 /workspace/coverage/default/2.edn_disable_auto_req_mode.1916598163 Dec 24 01:42:02 PM PST 23 Dec 24 01:42:07 PM PST 23 17152206 ps
T930 /workspace/coverage/default/23.edn_stress_all.423008722 Dec 24 01:42:48 PM PST 23 Dec 24 01:43:14 PM PST 23 252612995 ps
T931 /workspace/coverage/default/18.edn_smoke.4012836504 Dec 24 01:42:45 PM PST 23 Dec 24 01:43:05 PM PST 23 30049664 ps
T932 /workspace/coverage/default/15.edn_stress_all.2571712006 Dec 24 01:42:42 PM PST 23 Dec 24 01:42:57 PM PST 23 282155462 ps
T330 /workspace/coverage/default/3.edn_regwen.1871306389 Dec 24 01:42:16 PM PST 23 Dec 24 01:42:19 PM PST 23 46154450 ps
T933 /workspace/coverage/default/43.edn_genbits.3175736808 Dec 24 01:43:32 PM PST 23 Dec 24 01:43:39 PM PST 23 28064003 ps
T934 /workspace/coverage/default/75.edn_err.3524798732 Dec 24 01:43:58 PM PST 23 Dec 24 01:44:01 PM PST 23 21272297 ps
T935 /workspace/coverage/default/25.edn_intr.2998877744 Dec 24 01:44:43 PM PST 23 Dec 24 01:44:46 PM PST 23 17711492 ps
T936 /workspace/coverage/default/277.edn_genbits.1127953216 Dec 24 01:44:08 PM PST 23 Dec 24 01:44:29 PM PST 23 20137756 ps
T199 /workspace/coverage/default/34.edn_disable_auto_req_mode.2606368758 Dec 24 01:42:54 PM PST 23 Dec 24 01:43:17 PM PST 23 42641718 ps
T937 /workspace/coverage/default/27.edn_disable.725564483 Dec 24 01:42:50 PM PST 23 Dec 24 01:43:14 PM PST 23 23077909 ps
T938 /workspace/coverage/default/23.edn_smoke.3909119928 Dec 24 01:42:45 PM PST 23 Dec 24 01:43:05 PM PST 23 16897969 ps
T939 /workspace/coverage/default/29.edn_smoke.3762585966 Dec 24 01:42:46 PM PST 23 Dec 24 01:43:05 PM PST 23 45720167 ps
T940 /workspace/coverage/default/28.edn_genbits.2983998450 Dec 24 01:42:49 PM PST 23 Dec 24 01:43:13 PM PST 23 56229978 ps
T941 /workspace/coverage/default/48.edn_smoke.3810147749 Dec 24 01:44:03 PM PST 23 Dec 24 01:44:12 PM PST 23 47781498 ps
T942 /workspace/coverage/default/6.edn_intr.2964633146 Dec 24 01:42:45 PM PST 23 Dec 24 01:43:05 PM PST 23 27951942 ps
T943 /workspace/coverage/default/24.edn_stress_all.906512521 Dec 24 01:42:45 PM PST 23 Dec 24 01:43:06 PM PST 23 847447628 ps
T944 /workspace/coverage/default/18.edn_stress_all.1825953747 Dec 24 01:42:38 PM PST 23 Dec 24 01:42:55 PM PST 23 209218834 ps
T945 /workspace/coverage/default/267.edn_genbits.3331548931 Dec 24 01:44:03 PM PST 23 Dec 24 01:44:12 PM PST 23 46878125 ps
T946 /workspace/coverage/default/55.edn_err.651440119 Dec 24 01:44:12 PM PST 23 Dec 24 01:44:33 PM PST 23 31138261 ps
T947 /workspace/coverage/default/42.edn_genbits.279217031 Dec 24 01:43:43 PM PST 23 Dec 24 01:43:45 PM PST 23 72404087 ps
T948 /workspace/coverage/default/38.edn_err.676572749 Dec 24 01:43:35 PM PST 23 Dec 24 01:43:42 PM PST 23 19521595 ps
T949 /workspace/coverage/default/33.edn_genbits.557662996 Dec 24 01:42:56 PM PST 23 Dec 24 01:43:17 PM PST 23 31425909 ps
T950 /workspace/coverage/default/260.edn_genbits.4118628266 Dec 24 01:44:07 PM PST 23 Dec 24 01:44:27 PM PST 23 59895855 ps
T951 /workspace/coverage/default/206.edn_genbits.4156887878 Dec 24 01:44:02 PM PST 23 Dec 24 01:44:10 PM PST 23 71840745 ps
T952 /workspace/coverage/default/40.edn_disable_auto_req_mode.582291605 Dec 24 01:43:31 PM PST 23 Dec 24 01:43:35 PM PST 23 24162132 ps
T328 /workspace/coverage/default/43.edn_alert.1721021602 Dec 24 01:43:50 PM PST 23 Dec 24 01:43:52 PM PST 23 68522683 ps
T953 /workspace/coverage/default/120.edn_genbits.142408780 Dec 24 01:44:01 PM PST 23 Dec 24 01:44:07 PM PST 23 146187742 ps
T325 /workspace/coverage/default/20.edn_alert.1999101541 Dec 24 01:43:07 PM PST 23 Dec 24 01:43:22 PM PST 23 34198823 ps
T954 /workspace/coverage/default/31.edn_alert.596924011 Dec 24 01:43:04 PM PST 23 Dec 24 01:43:21 PM PST 23 57929299 ps
T955 /workspace/coverage/default/38.edn_intr.1112802348 Dec 24 01:43:32 PM PST 23 Dec 24 01:43:39 PM PST 23 22146013 ps
T956 /workspace/coverage/default/112.edn_genbits.2422001280 Dec 24 01:44:01 PM PST 23 Dec 24 01:44:08 PM PST 23 243685746 ps
T957 /workspace/coverage/default/26.edn_alert.2134450110 Dec 24 01:42:46 PM PST 23 Dec 24 01:43:05 PM PST 23 59239754 ps
T958 /workspace/coverage/default/146.edn_genbits.3793099198 Dec 24 01:44:06 PM PST 23 Dec 24 01:44:24 PM PST 23 29466712 ps
T87 /workspace/coverage/default/54.edn_err.490943974 Dec 24 01:44:09 PM PST 23 Dec 24 01:44:30 PM PST 23 92725167 ps
T959 /workspace/coverage/default/89.edn_genbits.363228369 Dec 24 01:43:56 PM PST 23 Dec 24 01:43:59 PM PST 23 51423627 ps
T960 /workspace/coverage/default/13.edn_intr.3314289395 Dec 24 01:42:46 PM PST 23 Dec 24 01:43:05 PM PST 23 37743919 ps
T961 /workspace/coverage/default/143.edn_genbits.1640999818 Dec 24 01:44:04 PM PST 23 Dec 24 01:44:17 PM PST 23 17114025 ps
T962 /workspace/coverage/default/7.edn_alert.2650168823 Dec 24 01:42:17 PM PST 23 Dec 24 01:42:20 PM PST 23 53740131 ps
T963 /workspace/coverage/default/13.edn_stress_all_with_rand_reset.4223969642 Dec 24 01:42:38 PM PST 23 Dec 24 02:18:01 PM PST 23 1369895926959 ps
T964 /workspace/coverage/default/293.edn_genbits.1506131797 Dec 24 01:44:08 PM PST 23 Dec 24 01:44:28 PM PST 23 34038289 ps
T965 /workspace/coverage/default/161.edn_genbits.1415768109 Dec 24 01:44:11 PM PST 23 Dec 24 01:44:31 PM PST 23 17298860 ps
T90 /workspace/coverage/default/26.edn_intr.191539283 Dec 24 01:42:45 PM PST 23 Dec 24 01:43:05 PM PST 23 20544310 ps
T966 /workspace/coverage/default/32.edn_disable_auto_req_mode.671479024 Dec 24 01:43:12 PM PST 23 Dec 24 01:43:23 PM PST 23 28621613 ps
T967 /workspace/coverage/default/30.edn_err.3446797824 Dec 24 01:42:51 PM PST 23 Dec 24 01:43:14 PM PST 23 135470643 ps
T968 /workspace/coverage/default/32.edn_alert_test.1168049023 Dec 24 01:42:59 PM PST 23 Dec 24 01:43:18 PM PST 23 59383909 ps
T969 /workspace/coverage/default/33.edn_smoke.4043047996 Dec 24 01:42:59 PM PST 23 Dec 24 01:43:18 PM PST 23 15062697 ps
T970 /workspace/coverage/default/82.edn_err.1967078269 Dec 24 01:44:00 PM PST 23 Dec 24 01:44:06 PM PST 23 24754818 ps
T971 /workspace/coverage/default/266.edn_genbits.1701931718 Dec 24 01:44:04 PM PST 23 Dec 24 01:44:19 PM PST 23 52234349 ps
T972 /workspace/coverage/default/35.edn_alert.1969956810 Dec 24 01:43:06 PM PST 23 Dec 24 01:43:22 PM PST 23 64755642 ps
T973 /workspace/coverage/default/28.edn_stress_all_with_rand_reset.1232115932 Dec 24 01:44:43 PM PST 23 Dec 24 01:59:23 PM PST 23 166901273609 ps
T974 /workspace/coverage/default/30.edn_intr.660202355 Dec 24 01:43:00 PM PST 23 Dec 24 01:43:18 PM PST 23 17605378 ps
T975 /workspace/coverage/default/224.edn_genbits.862687179 Dec 24 01:44:06 PM PST 23 Dec 24 01:44:24 PM PST 23 32423131 ps

Test location /workspace/coverage/default/83.edn_genbits.2429274255
Short name T1
Test name
Test status
Simulation time 18689543 ps
CPU time 1.07 seconds
Started Dec 24 01:43:59 PM PST 23
Finished Dec 24 01:44:03 PM PST 23
Peak memory 214232 kb
Host smart-6db70379-e9f2-481a-ae63-a34ecb6678d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429274255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.2429274255
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/290.edn_genbits.1239505873
Short name T28
Test name
Test status
Simulation time 26885777 ps
CPU time 1.27 seconds
Started Dec 24 01:44:13 PM PST 23
Finished Dec 24 01:44:34 PM PST 23
Peak memory 205632 kb
Host smart-c1d44fba-8a74-4444-a22c-754a075074b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239505873 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.1239505873
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2168787247
Short name T151
Test name
Test status
Simulation time 284528333 ps
CPU time 2.19 seconds
Started Dec 24 12:55:17 PM PST 23
Finished Dec 24 12:55:21 PM PST 23
Peak memory 206092 kb
Host smart-f6c59fad-542f-432b-83e4-7d4ab9d315ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168787247 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.2168787247
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/default/3.edn_sec_cm.3166416245
Short name T22
Test name
Test status
Simulation time 1512520409 ps
CPU time 6.66 seconds
Started Dec 24 01:42:39 PM PST 23
Finished Dec 24 01:42:59 PM PST 23
Peak memory 234936 kb
Host smart-7230754c-4d42-4b7f-91f0-29e37dfc3b8d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166416245 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.3166416245
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/46.edn_stress_all.2084279457
Short name T5
Test name
Test status
Simulation time 185013916 ps
CPU time 2.13 seconds
Started Dec 24 01:43:59 PM PST 23
Finished Dec 24 01:44:04 PM PST 23
Peak memory 205780 kb
Host smart-3da73aca-d49e-4efa-8623-4852efa144d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084279457 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.2084279457
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_err.215716989
Short name T8
Test name
Test status
Simulation time 26223718 ps
CPU time 1.25 seconds
Started Dec 24 01:43:27 PM PST 23
Finished Dec 24 01:43:29 PM PST 23
Peak memory 216080 kb
Host smart-dca7e5c4-252e-493c-b7c4-f326530c5b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215716989 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.215716989
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/46.edn_disable.2082011766
Short name T74
Test name
Test status
Simulation time 23931773 ps
CPU time 0.85 seconds
Started Dec 24 01:44:03 PM PST 23
Finished Dec 24 01:44:14 PM PST 23
Peak memory 214228 kb
Host smart-dcab284d-70db-4618-a5ca-2fc56e35d912
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082011766 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.2082011766
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.3594454369
Short name T82
Test name
Test status
Simulation time 327464798547 ps
CPU time 2098.33 seconds
Started Dec 24 01:42:47 PM PST 23
Finished Dec 24 02:18:06 PM PST 23
Peak memory 224080 kb
Host smart-8a25afea-6d67-4934-a1d0-0fed776e49ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594454369 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.3594454369
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.1720244966
Short name T25
Test name
Test status
Simulation time 115819971 ps
CPU time 4.02 seconds
Started Dec 24 12:55:18 PM PST 23
Finished Dec 24 12:55:25 PM PST 23
Peak memory 214260 kb
Host smart-aa9252be-6c18-439f-8231-befa76daf04b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720244966 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.1720244966
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.806100106
Short name T73
Test name
Test status
Simulation time 77984708 ps
CPU time 0.98 seconds
Started Dec 24 01:42:44 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 214524 kb
Host smart-7b766322-fcb4-4d32-acac-51f8053b0d9f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806100106 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_di
sable_auto_req_mode.806100106
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_disable.3564729690
Short name T75
Test name
Test status
Simulation time 11539875 ps
CPU time 0.86 seconds
Started Dec 24 01:44:00 PM PST 23
Finished Dec 24 01:44:06 PM PST 23
Peak memory 214220 kb
Host smart-7b1f4065-1562-479e-96ec-5ff8d387e0ed
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564729690 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3564729690
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/14.edn_alert.51171202
Short name T18
Test name
Test status
Simulation time 57682774 ps
CPU time 0.94 seconds
Started Dec 24 01:42:36 PM PST 23
Finished Dec 24 01:42:43 PM PST 23
Peak memory 205344 kb
Host smart-848283ff-1cc8-4345-b127-368a981d4cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51171202 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.51171202
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.3898978085
Short name T222
Test name
Test status
Simulation time 17660831 ps
CPU time 0.8 seconds
Started Dec 24 12:55:24 PM PST 23
Finished Dec 24 12:55:29 PM PST 23
Peak memory 205756 kb
Host smart-c949b1f5-2ee6-4cf7-ac00-1ec80c43e6ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898978085 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.3898978085
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/default/1.edn_intr.1391799127
Short name T35
Test name
Test status
Simulation time 19123253 ps
CPU time 0.92 seconds
Started Dec 24 01:41:53 PM PST 23
Finished Dec 24 01:41:59 PM PST 23
Peak memory 214268 kb
Host smart-461aade3-b617-4556-8fd6-df4c1fafd01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391799127 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.1391799127
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_disable.2012566682
Short name T122
Test name
Test status
Simulation time 40304112 ps
CPU time 0.87 seconds
Started Dec 24 01:42:38 PM PST 23
Finished Dec 24 01:42:50 PM PST 23
Peak memory 214248 kb
Host smart-1655edd0-1f5b-46d5-9e07-3a18945cc6da
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012566682 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.2012566682
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/0.edn_regwen.1558048550
Short name T314
Test name
Test status
Simulation time 13568140 ps
CPU time 0.95 seconds
Started Dec 24 01:41:55 PM PST 23
Finished Dec 24 01:42:02 PM PST 23
Peak memory 204556 kb
Host smart-769514c4-c9b6-43d0-b7df-ed56653ba512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558048550 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.1558048550
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_disable.1393552799
Short name T132
Test name
Test status
Simulation time 38241629 ps
CPU time 0.85 seconds
Started Dec 24 01:42:15 PM PST 23
Finished Dec 24 01:42:17 PM PST 23
Peak memory 214232 kb
Host smart-9f3d96fa-ed2a-4858-83a3-4521cd418964
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393552799 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.1393552799
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.3135060960
Short name T195
Test name
Test status
Simulation time 94479939 ps
CPU time 1.1 seconds
Started Dec 24 01:42:49 PM PST 23
Finished Dec 24 01:43:13 PM PST 23
Peak memory 214492 kb
Host smart-758b41d4-548e-42b1-a955-654dd40dbff5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135060960 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.3135060960
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.2935890739
Short name T78
Test name
Test status
Simulation time 64779137 ps
CPU time 1 seconds
Started Dec 24 01:41:50 PM PST 23
Finished Dec 24 01:41:53 PM PST 23
Peak memory 214540 kb
Host smart-05f4cac8-4c5e-4f20-8d87-adb0fcdb4ca6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935890739 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.2935890739
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.2915741043
Short name T295
Test name
Test status
Simulation time 81737868266 ps
CPU time 989.94 seconds
Started Dec 24 01:43:29 PM PST 23
Finished Dec 24 02:00:01 PM PST 23
Peak memory 215952 kb
Host smart-7e34511b-0b5e-4a48-a2a2-e0ab80eae69c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915741043 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.2915741043
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.edn_disable.628820260
Short name T68
Test name
Test status
Simulation time 10850778 ps
CPU time 0.87 seconds
Started Dec 24 01:41:57 PM PST 23
Finished Dec 24 01:42:04 PM PST 23
Peak memory 214236 kb
Host smart-4cf94372-cce9-486a-b7d3-838b6417b71d
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628820260 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.628820260
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2129154825
Short name T155
Test name
Test status
Simulation time 153602488 ps
CPU time 1.6 seconds
Started Dec 24 12:55:16 PM PST 23
Finished Dec 24 12:55:20 PM PST 23
Peak memory 206152 kb
Host smart-e3aabe78-3be0-4c2d-986e-38d670719c58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129154825 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.2129154825
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/default/287.edn_genbits.3054193514
Short name T263
Test name
Test status
Simulation time 26511479 ps
CPU time 0.95 seconds
Started Dec 24 01:44:13 PM PST 23
Finished Dec 24 01:44:33 PM PST 23
Peak memory 205272 kb
Host smart-d2c65f02-a5ab-4628-8a12-902dde03a221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054193514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.3054193514
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.3589016537
Short name T180
Test name
Test status
Simulation time 56007651 ps
CPU time 0.96 seconds
Started Dec 24 01:42:50 PM PST 23
Finished Dec 24 01:43:14 PM PST 23
Peak memory 214420 kb
Host smart-3e3fa4ce-3630-4e4e-ad60-1bef5ca06348
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589016537 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.3589016537
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_genbits.1439604270
Short name T333
Test name
Test status
Simulation time 57228460 ps
CPU time 0.96 seconds
Started Dec 24 01:42:45 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 205896 kb
Host smart-1a117f2e-4565-44e2-acc8-0c0148e73c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439604270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.1439604270
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.3969275463
Short name T289
Test name
Test status
Simulation time 55873787 ps
CPU time 1.3 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:19 PM PST 23
Peak memory 214124 kb
Host smart-5b1e0513-4b06-4765-8cfa-6f0eda1bb631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969275463 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.3969275463
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_disable.3975209908
Short name T148
Test name
Test status
Simulation time 12480751 ps
CPU time 0.88 seconds
Started Dec 24 01:42:45 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 214372 kb
Host smart-f28ce91f-4d46-496f-8c9b-e7687cedbc09
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975209908 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.3975209908
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable.2361145668
Short name T150
Test name
Test status
Simulation time 18819440 ps
CPU time 0.82 seconds
Started Dec 24 01:42:44 PM PST 23
Finished Dec 24 01:43:04 PM PST 23
Peak memory 214152 kb
Host smart-7af0a9d7-d9b3-4a89-a861-a6011531a41b
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361145668 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.2361145668
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable.916550579
Short name T144
Test name
Test status
Simulation time 13048012 ps
CPU time 0.9 seconds
Started Dec 24 01:42:43 PM PST 23
Finished Dec 24 01:43:03 PM PST 23
Peak memory 214444 kb
Host smart-9e39dbbc-b444-4ee6-8104-337b9f0f5b91
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916550579 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.916550579
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/40.edn_intr.366701494
Short name T92
Test name
Test status
Simulation time 32562587 ps
CPU time 0.91 seconds
Started Dec 24 01:43:34 PM PST 23
Finished Dec 24 01:43:42 PM PST 23
Peak memory 224652 kb
Host smart-4ebebd06-eae1-45c1-9a8f-9921c37a8a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366701494 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.366701494
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/13.edn_disable.2876920523
Short name T865
Test name
Test status
Simulation time 58778098 ps
CPU time 0.82 seconds
Started Dec 24 01:42:38 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 214344 kb
Host smart-70b92353-23b5-4f17-988e-92e47ea57441
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876920523 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.2876920523
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.18212590
Short name T189
Test name
Test status
Simulation time 58397517 ps
CPU time 0.91 seconds
Started Dec 24 01:42:43 PM PST 23
Finished Dec 24 01:43:00 PM PST 23
Peak memory 214472 kb
Host smart-263161df-8dc8-4521-ba63-f868bb33830d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18212590 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_dis
able_auto_req_mode.18212590
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_disable.818468069
Short name T114
Test name
Test status
Simulation time 18387102 ps
CPU time 0.92 seconds
Started Dec 24 01:43:02 PM PST 23
Finished Dec 24 01:43:20 PM PST 23
Peak memory 214232 kb
Host smart-c2593f02-12c3-4e1f-98ff-c986d8f0833c
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818468069 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.818468069
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.2606368758
Short name T199
Test name
Test status
Simulation time 42641718 ps
CPU time 1.06 seconds
Started Dec 24 01:42:54 PM PST 23
Finished Dec 24 01:43:17 PM PST 23
Peak memory 214500 kb
Host smart-54b18587-d37b-47da-9707-00f414f4c3df
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606368758 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.2606368758
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/230.edn_genbits.1889178311
Short name T270
Test name
Test status
Simulation time 27362746 ps
CPU time 0.96 seconds
Started Dec 24 01:44:08 PM PST 23
Finished Dec 24 01:44:28 PM PST 23
Peak memory 205504 kb
Host smart-8e2a0d6c-042e-45ea-9c65-13902b752b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889178311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.1889178311
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_alert.3940249333
Short name T63
Test name
Test status
Simulation time 32193943 ps
CPU time 0.96 seconds
Started Dec 24 01:41:52 PM PST 23
Finished Dec 24 01:41:57 PM PST 23
Peak memory 205964 kb
Host smart-627688f1-e080-40db-8d6c-5f4ac504a2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940249333 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.3940249333
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert.1253797992
Short name T249
Test name
Test status
Simulation time 19992563 ps
CPU time 0.99 seconds
Started Dec 24 01:42:41 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 205960 kb
Host smart-3bcdaf6b-0915-4816-ad19-dd9dc4de4b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253797992 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.1253797992
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert.1999101541
Short name T325
Test name
Test status
Simulation time 34198823 ps
CPU time 0.93 seconds
Started Dec 24 01:43:07 PM PST 23
Finished Dec 24 01:43:22 PM PST 23
Peak memory 205472 kb
Host smart-e41b501b-c20e-4d53-800a-5172478ea119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999101541 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.1999101541
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/259.edn_genbits.1139037880
Short name T345
Test name
Test status
Simulation time 14956835 ps
CPU time 0.99 seconds
Started Dec 24 01:44:09 PM PST 23
Finished Dec 24 01:44:30 PM PST 23
Peak memory 205008 kb
Host smart-b6a25a59-709d-4823-b9a0-f08c5fba65b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139037880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.1139037880
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/270.edn_genbits.2278327330
Short name T277
Test name
Test status
Simulation time 79514875 ps
CPU time 1.91 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:18 PM PST 23
Peak memory 214132 kb
Host smart-f07fd37d-d7a1-41a3-857b-6cf079dacf28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278327330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2278327330
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.4166074434
Short name T310
Test name
Test status
Simulation time 21038646 ps
CPU time 1.16 seconds
Started Dec 24 01:44:05 PM PST 23
Finished Dec 24 01:44:22 PM PST 23
Peak memory 205784 kb
Host smart-3e3d3e09-bb0f-4eca-855f-c5665492ba2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166074434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.4166074434
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.3290717478
Short name T266
Test name
Test status
Simulation time 201095270 ps
CPU time 2.84 seconds
Started Dec 24 01:44:17 PM PST 23
Finished Dec 24 01:44:37 PM PST 23
Peak memory 214008 kb
Host smart-a8b69722-d324-43c7-8a76-c3fcfebcc0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290717478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.3290717478
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_regwen.1231693470
Short name T313
Test name
Test status
Simulation time 35706178 ps
CPU time 0.92 seconds
Started Dec 24 01:42:44 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 204824 kb
Host smart-afbad417-4182-43c5-afc8-d7fd406a52c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231693470 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.1231693470
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.986450953
Short name T260
Test name
Test status
Simulation time 604637358 ps
CPU time 2.25 seconds
Started Dec 24 12:54:48 PM PST 23
Finished Dec 24 12:54:55 PM PST 23
Peak memory 206060 kb
Host smart-0b675242-b62c-4600-a922-31cdb0cb6546
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986450953 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.986450953
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/default/107.edn_genbits.261261821
Short name T290
Test name
Test status
Simulation time 25901085 ps
CPU time 0.92 seconds
Started Dec 24 01:44:01 PM PST 23
Finished Dec 24 01:44:09 PM PST 23
Peak memory 204948 kb
Host smart-f47cb384-fd1c-4103-8724-d7575ba9e953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261261821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.261261821
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.3116935894
Short name T294
Test name
Test status
Simulation time 249030525601 ps
CPU time 1188.05 seconds
Started Dec 24 01:42:45 PM PST 23
Finished Dec 24 02:02:52 PM PST 23
Peak memory 217324 kb
Host smart-83e80195-d6f5-4bdc-bbce-9c8f31e08faa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116935894 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.3116935894
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/168.edn_genbits.3911406910
Short name T638
Test name
Test status
Simulation time 20606826 ps
CPU time 1.06 seconds
Started Dec 24 01:44:01 PM PST 23
Finished Dec 24 01:44:08 PM PST 23
Peak memory 205224 kb
Host smart-9e4bf2b3-a5b7-4138-89b3-9d2b6a694ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911406910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.3911406910
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.717369288
Short name T341
Test name
Test status
Simulation time 30437825 ps
CPU time 0.89 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:16 PM PST 23
Peak memory 205724 kb
Host smart-e6fdd4b1-c757-4bc5-94ce-7016d671e48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717369288 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.717369288
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_regwen.2394190371
Short name T252
Test name
Test status
Simulation time 24173039 ps
CPU time 0.86 seconds
Started Dec 24 01:41:54 PM PST 23
Finished Dec 24 01:42:00 PM PST 23
Peak memory 204692 kb
Host smart-962df95e-c974-4b60-85b1-7bcdd846919b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394190371 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.2394190371
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.1859351083
Short name T163
Test name
Test status
Simulation time 178763951 ps
CPU time 1.88 seconds
Started Dec 24 12:55:25 PM PST 23
Finished Dec 24 12:55:30 PM PST 23
Peak memory 214232 kb
Host smart-19c01e38-1d3a-4960-abdc-093e1b1d31a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859351083 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.1859351083
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/default/11.edn_alert_test.1456039064
Short name T103
Test name
Test status
Simulation time 25708478 ps
CPU time 0.85 seconds
Started Dec 24 01:42:38 PM PST 23
Finished Dec 24 01:42:48 PM PST 23
Peak memory 204544 kb
Host smart-91677242-1805-429f-a903-27a3c13ca647
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456039064 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.1456039064
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/54.edn_err.490943974
Short name T87
Test name
Test status
Simulation time 92725167 ps
CPU time 1.33 seconds
Started Dec 24 01:44:09 PM PST 23
Finished Dec 24 01:44:30 PM PST 23
Peak memory 218800 kb
Host smart-ec976b33-62b0-47ed-8742-28a90235741d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490943974 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.490943974
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/26.edn_intr.191539283
Short name T90
Test name
Test status
Simulation time 20544310 ps
CPU time 1.03 seconds
Started Dec 24 01:42:45 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 214532 kb
Host smart-bf02910b-b463-4137-bc31-c436d70d8598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191539283 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.191539283
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1597886095
Short name T26
Test name
Test status
Simulation time 19938535 ps
CPU time 1.42 seconds
Started Dec 24 12:54:56 PM PST 23
Finished Dec 24 12:55:02 PM PST 23
Peak memory 214152 kb
Host smart-e325e26b-2485-476d-a2e3-78b3f3ebddd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597886095 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.1597886095
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.3128910459
Short name T356
Test name
Test status
Simulation time 12653426 ps
CPU time 0.84 seconds
Started Dec 24 12:55:22 PM PST 23
Finished Dec 24 12:55:27 PM PST 23
Peak memory 205960 kb
Host smart-0c305ecb-60d3-4d48-935d-75eb6aa95514
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128910459 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.3128910459
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/default/1.edn_genbits.1598237997
Short name T9
Test name
Test status
Simulation time 19415036 ps
CPU time 1.04 seconds
Started Dec 24 01:41:54 PM PST 23
Finished Dec 24 01:42:00 PM PST 23
Peak memory 214196 kb
Host smart-7a35fd2b-797b-4589-922c-ca91d221db2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598237997 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.1598237997
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_stress_all.1392445490
Short name T597
Test name
Test status
Simulation time 229292231 ps
CPU time 1.44 seconds
Started Dec 24 01:42:42 PM PST 23
Finished Dec 24 01:42:54 PM PST 23
Peak memory 205940 kb
Host smart-8d947581-0cdf-4079-8fcc-35a36d743a5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392445490 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.1392445490
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/104.edn_genbits.2336262749
Short name T67
Test name
Test status
Simulation time 58946645 ps
CPU time 1.08 seconds
Started Dec 24 01:44:10 PM PST 23
Finished Dec 24 01:44:30 PM PST 23
Peak memory 205616 kb
Host smart-c0c4b6c8-864f-441b-8467-3f5d4e6d1b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336262749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.2336262749
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.47487325
Short name T342
Test name
Test status
Simulation time 45969845 ps
CPU time 0.91 seconds
Started Dec 24 01:44:02 PM PST 23
Finished Dec 24 01:44:11 PM PST 23
Peak memory 205108 kb
Host smart-bd357405-c069-41a8-aa0d-21d79beb58cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47487325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.47487325
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.3186069327
Short name T52
Test name
Test status
Simulation time 751433645 ps
CPU time 4.8 seconds
Started Dec 24 01:44:01 PM PST 23
Finished Dec 24 01:44:12 PM PST 23
Peak memory 214200 kb
Host smart-c2a31f3f-20f0-410e-ad82-0c87d6d25327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186069327 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.3186069327
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_err.3222761822
Short name T14
Test name
Test status
Simulation time 29464371 ps
CPU time 1.31 seconds
Started Dec 24 01:42:44 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 221716 kb
Host smart-d6fdf5fa-f0ee-43b7-a1f4-51b379bdcd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222761822 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.3222761822
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/125.edn_genbits.634235758
Short name T32
Test name
Test status
Simulation time 24925737 ps
CPU time 1 seconds
Started Dec 24 01:44:03 PM PST 23
Finished Dec 24 01:44:13 PM PST 23
Peak memory 204980 kb
Host smart-0d60a5c4-98b9-4890-bb47-6c61b334f9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634235758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.634235758
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.2717353854
Short name T276
Test name
Test status
Simulation time 58304023 ps
CPU time 0.98 seconds
Started Dec 24 01:44:06 PM PST 23
Finished Dec 24 01:44:24 PM PST 23
Peak memory 205196 kb
Host smart-a87bdde8-706b-45b7-9286-e73f2913ec55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717353854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.2717353854
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.2613878371
Short name T284
Test name
Test status
Simulation time 27589470 ps
CPU time 1.47 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:19 PM PST 23
Peak memory 214268 kb
Host smart-83d98244-5ccd-49f5-8ee2-df3d8c57d294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613878371 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.2613878371
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.1720664012
Short name T318
Test name
Test status
Simulation time 35526986 ps
CPU time 1 seconds
Started Dec 24 01:42:47 PM PST 23
Finished Dec 24 01:43:06 PM PST 23
Peak memory 205904 kb
Host smart-b5ee9aea-3450-440e-b8eb-4e98c50fc640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720664012 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.1720664012
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/295.edn_genbits.1230517632
Short name T288
Test name
Test status
Simulation time 29828107 ps
CPU time 0.96 seconds
Started Dec 24 01:44:14 PM PST 23
Finished Dec 24 01:44:34 PM PST 23
Peak memory 205628 kb
Host smart-37b450a3-236b-494a-ba04-2ced5efa172b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230517632 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.1230517632
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_regwen.1871306389
Short name T330
Test name
Test status
Simulation time 46154450 ps
CPU time 0.9 seconds
Started Dec 24 01:42:16 PM PST 23
Finished Dec 24 01:42:19 PM PST 23
Peak memory 204764 kb
Host smart-d9c45255-d436-4b74-9961-aa79a37b317e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871306389 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.1871306389
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/38.edn_alert.2357947112
Short name T327
Test name
Test status
Simulation time 36066891 ps
CPU time 0.92 seconds
Started Dec 24 01:43:33 PM PST 23
Finished Dec 24 01:43:39 PM PST 23
Peak memory 205296 kb
Host smart-4deec019-b7df-4d2e-a229-68f3be53ca64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357947112 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.2357947112
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/18.edn_intr.1947622516
Short name T85
Test name
Test status
Simulation time 21305172 ps
CPU time 0.89 seconds
Started Dec 24 01:42:38 PM PST 23
Finished Dec 24 01:42:52 PM PST 23
Peak memory 214332 kb
Host smart-e3b1e32f-b008-4110-a6a1-dfbe498aa84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947622516 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1947622516
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.787319189
Short name T108
Test name
Test status
Simulation time 49496178 ps
CPU time 1.02 seconds
Started Dec 24 01:42:43 PM PST 23
Finished Dec 24 01:43:02 PM PST 23
Peak memory 206380 kb
Host smart-fefed0bd-3469-413a-873d-192ded26fa8e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787319189 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_dis
able_auto_req_mode.787319189
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/219.edn_genbits.296383653
Short name T31
Test name
Test status
Simulation time 65753467 ps
CPU time 1.79 seconds
Started Dec 24 01:44:07 PM PST 23
Finished Dec 24 01:44:26 PM PST 23
Peak memory 213668 kb
Host smart-42e01326-3a84-4511-9646-bd047663396a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296383653 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.296383653
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.2735932482
Short name T107
Test name
Test status
Simulation time 28455866 ps
CPU time 1.04 seconds
Started Dec 24 01:42:43 PM PST 23
Finished Dec 24 01:43:03 PM PST 23
Peak memory 214464 kb
Host smart-3b7f0fda-41be-492f-b875-2139b900fded
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735932482 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.2735932482
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_disable.2210111949
Short name T143
Test name
Test status
Simulation time 19832080 ps
CPU time 0.84 seconds
Started Dec 24 01:42:46 PM PST 23
Finished Dec 24 01:43:06 PM PST 23
Peak memory 214320 kb
Host smart-dfe0fedb-80a9-4c81-81d1-d8e9488ecc9a
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210111949 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.2210111949
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.755373642
Short name T160
Test name
Test status
Simulation time 70105005 ps
CPU time 1.48 seconds
Started Dec 24 12:54:21 PM PST 23
Finished Dec 24 12:54:25 PM PST 23
Peak memory 206044 kb
Host smart-4bdd7e8c-6a6e-4ce7-a586-100c287aba8a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755373642 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.755373642
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.414671236
Short name T426
Test name
Test status
Simulation time 799724883 ps
CPU time 3.21 seconds
Started Dec 24 12:54:21 PM PST 23
Finished Dec 24 12:54:26 PM PST 23
Peak memory 205968 kb
Host smart-3fde5cfe-531b-42f2-91d3-fe1a024415c0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414671236 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.414671236
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.548557160
Short name T232
Test name
Test status
Simulation time 23430879 ps
CPU time 0.85 seconds
Started Dec 24 12:54:07 PM PST 23
Finished Dec 24 12:54:13 PM PST 23
Peak memory 205964 kb
Host smart-759aebd0-851e-46b3-8d4e-23216665fe1d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548557160 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.548557160
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1473015710
Short name T405
Test name
Test status
Simulation time 39822003 ps
CPU time 1.1 seconds
Started Dec 24 12:54:06 PM PST 23
Finished Dec 24 12:54:13 PM PST 23
Peak memory 214292 kb
Host smart-6dc4599a-a848-48d1-8191-30c37165acd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473015710 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.1473015710
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.2777853817
Short name T431
Test name
Test status
Simulation time 16112094 ps
CPU time 0.93 seconds
Started Dec 24 12:54:12 PM PST 23
Finished Dec 24 12:54:19 PM PST 23
Peak memory 206000 kb
Host smart-1b295f04-09fa-4d7f-af71-30d06bb5ac1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777853817 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.2777853817
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.3121165252
Short name T363
Test name
Test status
Simulation time 56923483 ps
CPU time 0.78 seconds
Started Dec 24 12:54:20 PM PST 23
Finished Dec 24 12:54:24 PM PST 23
Peak memory 205700 kb
Host smart-88575eda-092b-49d4-a7a9-ac5a8f2d8c11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121165252 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.3121165252
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.89144302
Short name T159
Test name
Test status
Simulation time 68502204 ps
CPU time 1 seconds
Started Dec 24 12:54:19 PM PST 23
Finished Dec 24 12:54:23 PM PST 23
Peak memory 206048 kb
Host smart-44ae9154-d4fa-435c-8aa8-3030ddc72d34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89144302 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_outs
tanding.89144302
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.2696458034
Short name T391
Test name
Test status
Simulation time 45817917 ps
CPU time 2.96 seconds
Started Dec 24 12:54:04 PM PST 23
Finished Dec 24 12:54:15 PM PST 23
Peak memory 214256 kb
Host smart-386f7d91-383e-44ba-9ecf-103fbf77f95d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696458034 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.2696458034
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1039150982
Short name T259
Test name
Test status
Simulation time 188294809 ps
CPU time 1.66 seconds
Started Dec 24 12:54:13 PM PST 23
Finished Dec 24 12:54:20 PM PST 23
Peak memory 206020 kb
Host smart-6ecae3f0-0fa6-4691-9fc3-1024463b074c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039150982 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.1039150982
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1374282095
Short name T241
Test name
Test status
Simulation time 34239865 ps
CPU time 1.43 seconds
Started Dec 24 12:54:52 PM PST 23
Finished Dec 24 12:54:58 PM PST 23
Peak memory 205864 kb
Host smart-ee7871f2-bbdc-4e16-ac65-f6d7a06207ef
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374282095 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.1374282095
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2525392382
Short name T402
Test name
Test status
Simulation time 1477704462 ps
CPU time 2.98 seconds
Started Dec 24 12:54:54 PM PST 23
Finished Dec 24 12:55:03 PM PST 23
Peak memory 206108 kb
Host smart-e38506fc-0466-4b5f-a434-7bd98855408b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525392382 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2525392382
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2801208464
Short name T224
Test name
Test status
Simulation time 36331305 ps
CPU time 0.78 seconds
Started Dec 24 12:54:52 PM PST 23
Finished Dec 24 12:54:59 PM PST 23
Peak memory 205852 kb
Host smart-0a2a67eb-f3ce-4969-a0ee-9a3fa33a44a2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801208464 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.2801208464
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.1454987056
Short name T219
Test name
Test status
Simulation time 25732587 ps
CPU time 0.88 seconds
Started Dec 24 12:54:55 PM PST 23
Finished Dec 24 12:55:01 PM PST 23
Peak memory 205996 kb
Host smart-406a5d85-a15f-49e7-9499-337c5919bc2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454987056 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.1454987056
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.3583728728
Short name T380
Test name
Test status
Simulation time 135738291 ps
CPU time 0.84 seconds
Started Dec 24 12:54:57 PM PST 23
Finished Dec 24 12:55:01 PM PST 23
Peak memory 205928 kb
Host smart-012bcfdb-aad6-4981-8599-b917170cf248
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583728728 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3583728728
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2000299714
Short name T169
Test name
Test status
Simulation time 93086786 ps
CPU time 1.08 seconds
Started Dec 24 12:54:47 PM PST 23
Finished Dec 24 12:54:54 PM PST 23
Peak memory 205980 kb
Host smart-e7b44840-8b6e-4bab-b06f-5dea3d91cd17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000299714 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.2000299714
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.2770102210
Short name T156
Test name
Test status
Simulation time 849715204 ps
CPU time 2.37 seconds
Started Dec 24 12:54:11 PM PST 23
Finished Dec 24 12:54:20 PM PST 23
Peak memory 214240 kb
Host smart-3e3791d1-ce4f-48cb-b051-2b96bc4d55bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770102210 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.2770102210
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1814350601
Short name T427
Test name
Test status
Simulation time 117489407 ps
CPU time 2.32 seconds
Started Dec 24 12:54:11 PM PST 23
Finished Dec 24 12:54:20 PM PST 23
Peak memory 206012 kb
Host smart-a49a8a14-290f-4b4c-8d11-be442df2d42d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814350601 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.1814350601
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3744102141
Short name T161
Test name
Test status
Simulation time 40836217 ps
CPU time 1.14 seconds
Started Dec 24 12:55:16 PM PST 23
Finished Dec 24 12:55:20 PM PST 23
Peak memory 214260 kb
Host smart-42e34bd9-4f88-4ca1-8a6c-738d438cee42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744102141 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.3744102141
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.1426286357
Short name T378
Test name
Test status
Simulation time 22864173 ps
CPU time 0.87 seconds
Started Dec 24 12:55:19 PM PST 23
Finished Dec 24 12:55:23 PM PST 23
Peak memory 206056 kb
Host smart-1a4052d0-5876-4ef2-aae0-cfa9dfba2ed7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426286357 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.1426286357
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2774837515
Short name T221
Test name
Test status
Simulation time 16009215 ps
CPU time 0.99 seconds
Started Dec 24 12:55:18 PM PST 23
Finished Dec 24 12:55:22 PM PST 23
Peak memory 205912 kb
Host smart-9e94ae8c-7149-43ab-8ab3-77dc146031c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774837515 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.2774837515
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3480233145
Short name T258
Test name
Test status
Simulation time 392982988 ps
CPU time 2.13 seconds
Started Dec 24 12:55:18 PM PST 23
Finished Dec 24 12:55:23 PM PST 23
Peak memory 205948 kb
Host smart-c5154204-5a75-452e-86dc-b325f002c301
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480233145 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.3480233145
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1447010009
Short name T439
Test name
Test status
Simulation time 83130642 ps
CPU time 1.14 seconds
Started Dec 24 12:55:25 PM PST 23
Finished Dec 24 12:55:29 PM PST 23
Peak memory 215740 kb
Host smart-ed390e41-076a-4806-ac21-35d4dea5911f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447010009 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.1447010009
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.924693307
Short name T359
Test name
Test status
Simulation time 22749725 ps
CPU time 0.83 seconds
Started Dec 24 12:55:21 PM PST 23
Finished Dec 24 12:55:25 PM PST 23
Peak memory 206024 kb
Host smart-ea72787c-c737-401c-ada9-31ab937a399d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924693307 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.924693307
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2998736321
Short name T236
Test name
Test status
Simulation time 14687249 ps
CPU time 0.93 seconds
Started Dec 24 12:55:21 PM PST 23
Finished Dec 24 12:55:26 PM PST 23
Peak memory 205972 kb
Host smart-e6501020-8e40-4770-9fc7-1e6f5b8026d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998736321 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.2998736321
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.874823501
Short name T256
Test name
Test status
Simulation time 90412732 ps
CPU time 2.38 seconds
Started Dec 24 12:55:16 PM PST 23
Finished Dec 24 12:55:21 PM PST 23
Peak memory 214320 kb
Host smart-714a10d6-5799-4735-b0b8-7b1b083d5407
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874823501 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.874823501
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1693915588
Short name T109
Test name
Test status
Simulation time 48789006 ps
CPU time 1.68 seconds
Started Dec 24 12:55:19 PM PST 23
Finished Dec 24 12:55:23 PM PST 23
Peak memory 206092 kb
Host smart-e214545e-5029-40da-8d68-e7b78e3b0b01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693915588 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1693915588
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1969781695
Short name T369
Test name
Test status
Simulation time 25219406 ps
CPU time 1.2 seconds
Started Dec 24 12:55:22 PM PST 23
Finished Dec 24 12:55:27 PM PST 23
Peak memory 214244 kb
Host smart-2b864ffa-a4c1-44c6-890c-e5cd96ee6218
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969781695 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1969781695
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.4104821440
Short name T367
Test name
Test status
Simulation time 44632443 ps
CPU time 0.86 seconds
Started Dec 24 12:55:27 PM PST 23
Finished Dec 24 12:55:31 PM PST 23
Peak memory 206004 kb
Host smart-ff42c371-04d2-42d6-b1d8-dc7638dc1917
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104821440 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.4104821440
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.344205006
Short name T393
Test name
Test status
Simulation time 41284201 ps
CPU time 0.83 seconds
Started Dec 24 12:55:26 PM PST 23
Finished Dec 24 12:55:29 PM PST 23
Peak memory 206020 kb
Host smart-be2c2aae-6bd9-45c6-9131-518ff727b526
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344205006 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.344205006
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1703265741
Short name T243
Test name
Test status
Simulation time 13752581 ps
CPU time 0.96 seconds
Started Dec 24 12:55:22 PM PST 23
Finished Dec 24 12:55:26 PM PST 23
Peak memory 205892 kb
Host smart-917239f0-8a6d-4f2b-b4f1-3b259feca1bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703265741 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.1703265741
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.627347802
Short name T162
Test name
Test status
Simulation time 120856889 ps
CPU time 2.18 seconds
Started Dec 24 12:55:26 PM PST 23
Finished Dec 24 12:55:31 PM PST 23
Peak memory 214224 kb
Host smart-45fb43e5-676f-41bf-b27f-0f53fcc25a31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627347802 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.627347802
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2496971007
Short name T228
Test name
Test status
Simulation time 63026359 ps
CPU time 1.77 seconds
Started Dec 24 12:55:27 PM PST 23
Finished Dec 24 12:55:31 PM PST 23
Peak memory 205876 kb
Host smart-b00c3cfb-9bd4-4fc4-be5a-04d38db74aad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496971007 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.2496971007
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1615353497
Short name T238
Test name
Test status
Simulation time 15438154 ps
CPU time 1.1 seconds
Started Dec 24 12:55:26 PM PST 23
Finished Dec 24 12:55:30 PM PST 23
Peak memory 214300 kb
Host smart-77e1124c-9f8f-4b51-a5df-d8efa8fed5f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615353497 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.1615353497
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.4236717847
Short name T447
Test name
Test status
Simulation time 35717411 ps
CPU time 0.83 seconds
Started Dec 24 12:55:22 PM PST 23
Finished Dec 24 12:55:27 PM PST 23
Peak memory 205820 kb
Host smart-114a19a0-f1af-4519-ae25-494295bffaac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236717847 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.4236717847
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.1675837210
Short name T293
Test name
Test status
Simulation time 27822395 ps
CPU time 0.81 seconds
Started Dec 24 12:55:21 PM PST 23
Finished Dec 24 12:55:26 PM PST 23
Peak memory 205976 kb
Host smart-602f0a16-a71e-46ca-b1d4-1806dc63cab2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675837210 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.1675837210
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2158687168
Short name T362
Test name
Test status
Simulation time 52312659 ps
CPU time 1.05 seconds
Started Dec 24 12:55:29 PM PST 23
Finished Dec 24 12:55:33 PM PST 23
Peak memory 205992 kb
Host smart-570bd33c-0673-45b9-9449-d67e7e2fb982
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158687168 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.2158687168
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1982552220
Short name T399
Test name
Test status
Simulation time 391230640 ps
CPU time 2.38 seconds
Started Dec 24 12:55:23 PM PST 23
Finished Dec 24 12:55:29 PM PST 23
Peak memory 206188 kb
Host smart-bb511a0c-8648-4212-9ec4-a8c0f1c0ba19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982552220 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1982552220
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.4010959427
Short name T387
Test name
Test status
Simulation time 114977236 ps
CPU time 1.29 seconds
Started Dec 24 12:55:25 PM PST 23
Finished Dec 24 12:55:29 PM PST 23
Peak memory 215716 kb
Host smart-c7c4837e-a96d-4085-91d1-6510562fa796
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010959427 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.4010959427
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.2233572380
Short name T382
Test name
Test status
Simulation time 58676004 ps
CPU time 0.91 seconds
Started Dec 24 12:55:23 PM PST 23
Finished Dec 24 12:55:27 PM PST 23
Peak memory 205992 kb
Host smart-17b4167c-dbc9-4593-a39d-0729297bdb05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233572380 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.2233572380
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.879280779
Short name T351
Test name
Test status
Simulation time 29634571 ps
CPU time 0.82 seconds
Started Dec 24 12:55:27 PM PST 23
Finished Dec 24 12:55:31 PM PST 23
Peak memory 205828 kb
Host smart-85f2c01c-d349-4d9e-9d19-d118e3fb5795
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879280779 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.879280779
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2564124708
Short name T394
Test name
Test status
Simulation time 16472731 ps
CPU time 0.99 seconds
Started Dec 24 12:55:25 PM PST 23
Finished Dec 24 12:55:29 PM PST 23
Peak memory 206036 kb
Host smart-eb8b87a1-646e-4470-bb53-294bb090a29a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564124708 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.2564124708
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.3757470980
Short name T446
Test name
Test status
Simulation time 24191866 ps
CPU time 1.62 seconds
Started Dec 24 12:55:26 PM PST 23
Finished Dec 24 12:55:31 PM PST 23
Peak memory 214316 kb
Host smart-3927aae4-bb52-4396-9f03-2ccc6b7d79ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757470980 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.3757470980
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1409699902
Short name T171
Test name
Test status
Simulation time 201218682 ps
CPU time 1.61 seconds
Started Dec 24 12:55:27 PM PST 23
Finished Dec 24 12:55:31 PM PST 23
Peak memory 205880 kb
Host smart-acb44320-c69c-493d-8d72-8f86b065ee5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409699902 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1409699902
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1816242351
Short name T240
Test name
Test status
Simulation time 23369151 ps
CPU time 1.25 seconds
Started Dec 24 12:55:24 PM PST 23
Finished Dec 24 12:55:29 PM PST 23
Peak memory 214252 kb
Host smart-793af0f5-4e66-49b9-b18d-dcaca35106c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816242351 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.1816242351
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.2120965295
Short name T158
Test name
Test status
Simulation time 35975570 ps
CPU time 0.81 seconds
Started Dec 24 12:55:27 PM PST 23
Finished Dec 24 12:55:30 PM PST 23
Peak memory 205812 kb
Host smart-b7fc2eba-dfa0-4181-84e5-c042a50491f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120965295 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.2120965295
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.2183252901
Short name T429
Test name
Test status
Simulation time 35927018 ps
CPU time 0.91 seconds
Started Dec 24 12:55:27 PM PST 23
Finished Dec 24 12:55:31 PM PST 23
Peak memory 205992 kb
Host smart-81b53e56-4f40-4edc-8bad-72364eef9b52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183252901 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.2183252901
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2675660081
Short name T226
Test name
Test status
Simulation time 56846967 ps
CPU time 0.86 seconds
Started Dec 24 12:55:30 PM PST 23
Finished Dec 24 12:55:33 PM PST 23
Peak memory 205992 kb
Host smart-209bc35d-1533-40bb-a5db-0c260f5d0672
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675660081 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.2675660081
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.1186440588
Short name T372
Test name
Test status
Simulation time 99531528 ps
CPU time 2.4 seconds
Started Dec 24 12:55:31 PM PST 23
Finished Dec 24 12:55:35 PM PST 23
Peak memory 214180 kb
Host smart-a2d7ec3c-166d-4912-b3e7-a9af224fc0aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186440588 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.1186440588
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1710655415
Short name T448
Test name
Test status
Simulation time 259703491 ps
CPU time 1.46 seconds
Started Dec 24 12:55:23 PM PST 23
Finished Dec 24 12:55:28 PM PST 23
Peak memory 206008 kb
Host smart-11721e08-8659-4b64-b7ec-2723d4e9a144
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710655415 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.1710655415
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1917484147
Short name T27
Test name
Test status
Simulation time 25254020 ps
CPU time 1.24 seconds
Started Dec 24 12:56:03 PM PST 23
Finished Dec 24 12:56:08 PM PST 23
Peak memory 216140 kb
Host smart-6a221556-c259-4596-8364-4509b3e619b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917484147 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.1917484147
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.3198250015
Short name T225
Test name
Test status
Simulation time 21551368 ps
CPU time 0.8 seconds
Started Dec 24 12:55:26 PM PST 23
Finished Dec 24 12:55:30 PM PST 23
Peak memory 205832 kb
Host smart-c4f7f0d9-95b1-4669-8dd2-ae578e7c8183
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198250015 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.3198250015
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3389863272
Short name T444
Test name
Test status
Simulation time 20391182 ps
CPU time 0.82 seconds
Started Dec 24 12:55:25 PM PST 23
Finished Dec 24 12:55:29 PM PST 23
Peak memory 205840 kb
Host smart-dad762e2-eae5-450c-b3d6-eb242924041f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389863272 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3389863272
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3751010261
Short name T227
Test name
Test status
Simulation time 85742568 ps
CPU time 0.89 seconds
Started Dec 24 12:55:28 PM PST 23
Finished Dec 24 12:55:32 PM PST 23
Peak memory 205992 kb
Host smart-a94dd99b-6049-4641-93bc-cac018b9ba84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751010261 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.3751010261
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.1606323017
Short name T396
Test name
Test status
Simulation time 111121121 ps
CPU time 2.28 seconds
Started Dec 24 12:55:31 PM PST 23
Finished Dec 24 12:55:35 PM PST 23
Peak memory 214176 kb
Host smart-27a3edb9-bf87-43c7-9443-0b8dd6800766
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606323017 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.1606323017
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3388778318
Short name T435
Test name
Test status
Simulation time 163068339 ps
CPU time 2.39 seconds
Started Dec 24 12:55:24 PM PST 23
Finished Dec 24 12:55:30 PM PST 23
Peak memory 206024 kb
Host smart-bd36b842-31d1-43dd-8d47-511e9e39ac70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388778318 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.3388778318
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1903266962
Short name T440
Test name
Test status
Simulation time 29460820 ps
CPU time 1.32 seconds
Started Dec 24 12:56:00 PM PST 23
Finished Dec 24 12:56:03 PM PST 23
Peak memory 214276 kb
Host smart-edcf5314-2cac-45aa-8ff8-7ad4850aa938
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903266962 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.1903266962
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.3202887886
Short name T234
Test name
Test status
Simulation time 47852130 ps
CPU time 0.91 seconds
Started Dec 24 12:56:03 PM PST 23
Finished Dec 24 12:56:08 PM PST 23
Peak memory 206056 kb
Host smart-87e63ae5-42ca-429a-9eaa-f548d67f69e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202887886 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.3202887886
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.941084104
Short name T357
Test name
Test status
Simulation time 39489191 ps
CPU time 0.86 seconds
Started Dec 24 12:56:03 PM PST 23
Finished Dec 24 12:56:08 PM PST 23
Peak memory 205852 kb
Host smart-29b8db0b-403a-42f5-bc9f-08c2fbf4d526
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941084104 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.941084104
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1311983059
Short name T403
Test name
Test status
Simulation time 130803054 ps
CPU time 1.06 seconds
Started Dec 24 12:56:02 PM PST 23
Finished Dec 24 12:56:06 PM PST 23
Peak memory 205996 kb
Host smart-697b01be-6f98-416e-86f8-37987b1834dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311983059 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.1311983059
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.516280556
Short name T381
Test name
Test status
Simulation time 199051114 ps
CPU time 3.86 seconds
Started Dec 24 12:56:06 PM PST 23
Finished Dec 24 12:56:14 PM PST 23
Peak memory 214256 kb
Host smart-07256efd-7e94-4f64-8360-570b2bd45fed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516280556 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.516280556
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.477505596
Short name T257
Test name
Test status
Simulation time 317482000 ps
CPU time 2.53 seconds
Started Dec 24 12:56:04 PM PST 23
Finished Dec 24 12:56:10 PM PST 23
Peak memory 205992 kb
Host smart-b2f9118c-8634-45c0-b0c1-2357fdc147c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477505596 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.477505596
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2217656306
Short name T164
Test name
Test status
Simulation time 59849952 ps
CPU time 1.05 seconds
Started Dec 24 12:55:56 PM PST 23
Finished Dec 24 12:55:58 PM PST 23
Peak memory 214148 kb
Host smart-d065604d-4cde-4bc5-8d47-b33ce3151070
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217656306 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.2217656306
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.92209520
Short name T157
Test name
Test status
Simulation time 14404461 ps
CPU time 0.89 seconds
Started Dec 24 12:56:05 PM PST 23
Finished Dec 24 12:56:11 PM PST 23
Peak memory 205904 kb
Host smart-e103631c-b046-4e7d-a0bf-6790e099b5c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92209520 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.92209520
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.2192183133
Short name T237
Test name
Test status
Simulation time 157448752 ps
CPU time 0.85 seconds
Started Dec 24 12:56:02 PM PST 23
Finished Dec 24 12:56:06 PM PST 23
Peak memory 205804 kb
Host smart-281ef9c6-0c78-4de3-b596-238505b34b05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192183133 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2192183133
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3622587258
Short name T443
Test name
Test status
Simulation time 14369885 ps
CPU time 1.02 seconds
Started Dec 24 12:55:55 PM PST 23
Finished Dec 24 12:55:58 PM PST 23
Peak memory 205940 kb
Host smart-386f8e43-6bf9-4cef-a2a0-81acd8a77582
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622587258 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.3622587258
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.1204603407
Short name T153
Test name
Test status
Simulation time 166830662 ps
CPU time 1.89 seconds
Started Dec 24 12:56:02 PM PST 23
Finished Dec 24 12:56:08 PM PST 23
Peak memory 214260 kb
Host smart-4a79fe68-520b-4d7d-8177-dc86f5cebc7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204603407 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.1204603407
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1581183252
Short name T254
Test name
Test status
Simulation time 178174018 ps
CPU time 1.61 seconds
Started Dec 24 12:55:59 PM PST 23
Finished Dec 24 12:56:03 PM PST 23
Peak memory 205996 kb
Host smart-f662f88d-52f9-4ea5-b593-eb97c6d8b9cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581183252 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1581183252
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.105598861
Short name T218
Test name
Test status
Simulation time 147565586 ps
CPU time 1.22 seconds
Started Dec 24 12:56:04 PM PST 23
Finished Dec 24 12:56:10 PM PST 23
Peak memory 214260 kb
Host smart-02c670e4-d0bf-4f69-bacf-eda102163b83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105598861 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.105598861
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.1748612909
Short name T231
Test name
Test status
Simulation time 24694427 ps
CPU time 0.85 seconds
Started Dec 24 12:56:02 PM PST 23
Finished Dec 24 12:56:07 PM PST 23
Peak memory 206080 kb
Host smart-41eee989-c24b-404b-acef-8c547335e5b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748612909 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.1748612909
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.3497691126
Short name T398
Test name
Test status
Simulation time 18531121 ps
CPU time 0.82 seconds
Started Dec 24 12:56:00 PM PST 23
Finished Dec 24 12:56:02 PM PST 23
Peak memory 206020 kb
Host smart-fb7f74aa-0c3b-483f-8c2d-c6cde250de40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497691126 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.3497691126
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.2306020128
Short name T418
Test name
Test status
Simulation time 27284224 ps
CPU time 1.3 seconds
Started Dec 24 12:55:59 PM PST 23
Finished Dec 24 12:56:02 PM PST 23
Peak memory 205952 kb
Host smart-e0aadd95-02bc-430a-9127-88264a88ebe7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306020128 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.2306020128
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.3999505438
Short name T388
Test name
Test status
Simulation time 54290012 ps
CPU time 1.76 seconds
Started Dec 24 12:56:04 PM PST 23
Finished Dec 24 12:56:10 PM PST 23
Peak memory 214452 kb
Host smart-7fe51af8-7d51-4ec8-bcc3-47164205a9ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999505438 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.3999505438
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2610676222
Short name T425
Test name
Test status
Simulation time 74669002 ps
CPU time 2.23 seconds
Started Dec 24 12:56:05 PM PST 23
Finished Dec 24 12:56:12 PM PST 23
Peak memory 205976 kb
Host smart-89e7d41c-3d7c-4280-923d-fd5b41c3906a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610676222 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.2610676222
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1749074282
Short name T374
Test name
Test status
Simulation time 25578781 ps
CPU time 1.17 seconds
Started Dec 24 12:54:50 PM PST 23
Finished Dec 24 12:54:54 PM PST 23
Peak memory 206056 kb
Host smart-5737f19d-fbeb-4e64-871f-8b68ec46f887
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749074282 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.1749074282
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.259074745
Short name T235
Test name
Test status
Simulation time 61607968 ps
CPU time 3.25 seconds
Started Dec 24 12:54:59 PM PST 23
Finished Dec 24 12:55:05 PM PST 23
Peak memory 206088 kb
Host smart-49e041ac-23c9-4925-9693-49e19f8708ba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259074745 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.259074745
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1787090129
Short name T370
Test name
Test status
Simulation time 18505760 ps
CPU time 1.01 seconds
Started Dec 24 12:54:49 PM PST 23
Finished Dec 24 12:54:54 PM PST 23
Peak memory 205952 kb
Host smart-2132776e-4f42-41c0-bf85-cca0dd1a5192
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787090129 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1787090129
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2275501402
Short name T152
Test name
Test status
Simulation time 24611570 ps
CPU time 1.08 seconds
Started Dec 24 12:54:48 PM PST 23
Finished Dec 24 12:54:54 PM PST 23
Peak memory 206048 kb
Host smart-de1aa641-ac00-4a2b-ae8b-93c532130b62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275501402 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.2275501402
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.3766643929
Short name T385
Test name
Test status
Simulation time 36238790 ps
CPU time 0.81 seconds
Started Dec 24 12:54:48 PM PST 23
Finished Dec 24 12:54:54 PM PST 23
Peak memory 205720 kb
Host smart-471552ec-508b-4eff-aaf8-24da7407b0b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766643929 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.3766643929
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.1531690733
Short name T355
Test name
Test status
Simulation time 14367213 ps
CPU time 0.86 seconds
Started Dec 24 12:54:54 PM PST 23
Finished Dec 24 12:55:01 PM PST 23
Peak memory 205912 kb
Host smart-6368175a-d19e-422e-832f-206e6b2e9082
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531690733 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1531690733
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.551482266
Short name T167
Test name
Test status
Simulation time 13034922 ps
CPU time 0.91 seconds
Started Dec 24 12:54:59 PM PST 23
Finished Dec 24 12:55:03 PM PST 23
Peak memory 206008 kb
Host smart-390cee08-7695-4fb8-8ac6-f428a612c709
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551482266 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_out
standing.551482266
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.2276845245
Short name T373
Test name
Test status
Simulation time 228231638 ps
CPU time 3.9 seconds
Started Dec 24 12:54:51 PM PST 23
Finished Dec 24 12:54:59 PM PST 23
Peak memory 214368 kb
Host smart-9f411173-8855-49c2-b657-95896a878b6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276845245 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.2276845245
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.488383071
Short name T423
Test name
Test status
Simulation time 82824663 ps
CPU time 0.83 seconds
Started Dec 24 12:55:55 PM PST 23
Finished Dec 24 12:55:58 PM PST 23
Peak memory 205852 kb
Host smart-afb9a759-7985-4304-b019-d782e478368a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488383071 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.488383071
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.4039628851
Short name T354
Test name
Test status
Simulation time 170008905 ps
CPU time 0.81 seconds
Started Dec 24 12:56:09 PM PST 23
Finished Dec 24 12:56:13 PM PST 23
Peak memory 205852 kb
Host smart-0a2241f0-2af2-4630-bf30-162e66f572a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039628851 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.4039628851
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.2724090884
Short name T409
Test name
Test status
Simulation time 50984337 ps
CPU time 0.81 seconds
Started Dec 24 12:56:00 PM PST 23
Finished Dec 24 12:56:03 PM PST 23
Peak memory 206048 kb
Host smart-f3708eae-e9bc-4bbe-84c9-9d1230008d19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724090884 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.2724090884
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.2480433052
Short name T220
Test name
Test status
Simulation time 12831498 ps
CPU time 0.85 seconds
Started Dec 24 12:55:54 PM PST 23
Finished Dec 24 12:55:57 PM PST 23
Peak memory 205972 kb
Host smart-f3b63ee5-0a91-4199-b893-eaa347f6067a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480433052 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.2480433052
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.2751546940
Short name T416
Test name
Test status
Simulation time 87998851 ps
CPU time 0.79 seconds
Started Dec 24 12:56:02 PM PST 23
Finished Dec 24 12:56:07 PM PST 23
Peak memory 205828 kb
Host smart-219089ca-bdd9-4091-9d52-a24d8b17eb74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751546940 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.2751546940
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.2026855470
Short name T360
Test name
Test status
Simulation time 44468763 ps
CPU time 0.81 seconds
Started Dec 24 12:55:57 PM PST 23
Finished Dec 24 12:56:00 PM PST 23
Peak memory 206008 kb
Host smart-caf98014-bd4d-47b0-9a02-0504005b3743
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026855470 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.2026855470
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.1470258217
Short name T404
Test name
Test status
Simulation time 26210742 ps
CPU time 0.87 seconds
Started Dec 24 12:56:09 PM PST 23
Finished Dec 24 12:56:13 PM PST 23
Peak memory 205852 kb
Host smart-3faf9a3f-f207-42a8-aee2-6a33bbee722b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470258217 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.1470258217
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.3081757652
Short name T292
Test name
Test status
Simulation time 40291166 ps
CPU time 0.78 seconds
Started Dec 24 12:56:00 PM PST 23
Finished Dec 24 12:56:03 PM PST 23
Peak memory 205824 kb
Host smart-26768a76-a7ee-4a8a-9ddd-e6f14999f104
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081757652 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3081757652
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.2907701669
Short name T376
Test name
Test status
Simulation time 15754611 ps
CPU time 0.87 seconds
Started Dec 24 12:56:04 PM PST 23
Finished Dec 24 12:56:09 PM PST 23
Peak memory 205944 kb
Host smart-093a70b4-1162-45e8-be79-0a87ea54652a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907701669 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2907701669
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.3952071433
Short name T419
Test name
Test status
Simulation time 25016780 ps
CPU time 0.88 seconds
Started Dec 24 12:56:01 PM PST 23
Finished Dec 24 12:56:05 PM PST 23
Peak memory 205924 kb
Host smart-4de6388e-acad-4a5c-912a-b03a2a0f8cda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952071433 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.3952071433
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3308850605
Short name T244
Test name
Test status
Simulation time 123278997 ps
CPU time 1.36 seconds
Started Dec 24 12:54:51 PM PST 23
Finished Dec 24 12:54:56 PM PST 23
Peak memory 206032 kb
Host smart-382acf3f-e195-4ffc-8450-9f8c3fabb182
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308850605 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.3308850605
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.98316665
Short name T411
Test name
Test status
Simulation time 201574810 ps
CPU time 2.88 seconds
Started Dec 24 12:54:53 PM PST 23
Finished Dec 24 12:55:02 PM PST 23
Peak memory 206052 kb
Host smart-c4617efa-d5ce-4f35-9bdc-e701857a73fd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98316665 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.98316665
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2150391742
Short name T441
Test name
Test status
Simulation time 108154970 ps
CPU time 0.89 seconds
Started Dec 24 12:54:52 PM PST 23
Finished Dec 24 12:54:59 PM PST 23
Peak memory 206016 kb
Host smart-816afb88-56bf-44a6-b89d-7c3c993f6a50
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150391742 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2150391742
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2341805921
Short name T217
Test name
Test status
Simulation time 139682655 ps
CPU time 1.33 seconds
Started Dec 24 12:54:50 PM PST 23
Finished Dec 24 12:54:55 PM PST 23
Peak memory 214240 kb
Host smart-955d46bd-80c8-4c63-bffa-b497dec238b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341805921 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2341805921
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.1028420812
Short name T379
Test name
Test status
Simulation time 36968402 ps
CPU time 0.83 seconds
Started Dec 24 12:54:56 PM PST 23
Finished Dec 24 12:55:01 PM PST 23
Peak memory 205924 kb
Host smart-b4b262e1-7c7e-4be9-9fde-e5b0b3c33d14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028420812 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.1028420812
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.4048474728
Short name T358
Test name
Test status
Simulation time 44743833 ps
CPU time 0.86 seconds
Started Dec 24 12:54:53 PM PST 23
Finished Dec 24 12:55:00 PM PST 23
Peak memory 205976 kb
Host smart-ce2bc528-1aa9-43a0-9378-91671ece9fbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048474728 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.4048474728
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.431874836
Short name T436
Test name
Test status
Simulation time 35121043 ps
CPU time 1.13 seconds
Started Dec 24 12:54:52 PM PST 23
Finished Dec 24 12:54:59 PM PST 23
Peak memory 205976 kb
Host smart-2856f77d-b0f7-4366-b480-50b2f0139cf5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431874836 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_out
standing.431874836
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.411896395
Short name T413
Test name
Test status
Simulation time 39019637 ps
CPU time 2.68 seconds
Started Dec 24 12:54:47 PM PST 23
Finished Dec 24 12:54:56 PM PST 23
Peak memory 214332 kb
Host smart-a489fd3f-65fc-4b9c-8d3e-4b2e7810d7e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411896395 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.411896395
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.547581770
Short name T172
Test name
Test status
Simulation time 82630453 ps
CPU time 2.29 seconds
Started Dec 24 12:54:53 PM PST 23
Finished Dec 24 12:55:01 PM PST 23
Peak memory 206064 kb
Host smart-2337bc26-5191-468f-9e07-1b652698ac8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547581770 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.547581770
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.3130587339
Short name T366
Test name
Test status
Simulation time 12345823 ps
CPU time 0.82 seconds
Started Dec 24 12:56:01 PM PST 23
Finished Dec 24 12:56:05 PM PST 23
Peak memory 205928 kb
Host smart-feb33a67-0d3f-4934-8fa0-f96581bc79b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130587339 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.3130587339
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.294014248
Short name T353
Test name
Test status
Simulation time 15994576 ps
CPU time 0.89 seconds
Started Dec 24 12:56:12 PM PST 23
Finished Dec 24 12:56:16 PM PST 23
Peak memory 206036 kb
Host smart-2e6afcca-9d96-42a1-878e-8bf288382019
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294014248 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.294014248
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.1168929094
Short name T361
Test name
Test status
Simulation time 13469426 ps
CPU time 0.87 seconds
Started Dec 24 12:55:57 PM PST 23
Finished Dec 24 12:56:00 PM PST 23
Peak memory 206000 kb
Host smart-1db9e087-42f0-4eab-adba-867e31568d83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168929094 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.1168929094
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.1028814497
Short name T401
Test name
Test status
Simulation time 35704670 ps
CPU time 0.82 seconds
Started Dec 24 12:55:58 PM PST 23
Finished Dec 24 12:56:01 PM PST 23
Peak memory 205808 kb
Host smart-8e1191d0-7685-4ce0-a43d-0244ca51b6f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028814497 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.1028814497
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.1547813035
Short name T364
Test name
Test status
Simulation time 27291229 ps
CPU time 0.88 seconds
Started Dec 24 12:56:00 PM PST 23
Finished Dec 24 12:56:03 PM PST 23
Peak memory 205928 kb
Host smart-56fcff0e-5f09-41e6-a509-088b6a60067c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547813035 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.1547813035
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.3853416359
Short name T377
Test name
Test status
Simulation time 65560304 ps
CPU time 0.89 seconds
Started Dec 24 12:56:05 PM PST 23
Finished Dec 24 12:56:11 PM PST 23
Peak memory 206032 kb
Host smart-6709809f-bede-44ab-af0b-927a28e3dfe6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853416359 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.3853416359
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.867726447
Short name T428
Test name
Test status
Simulation time 146841558 ps
CPU time 0.79 seconds
Started Dec 24 12:56:08 PM PST 23
Finished Dec 24 12:56:13 PM PST 23
Peak memory 205796 kb
Host smart-76d175a2-82ee-4bfc-92fe-6b459d56adea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867726447 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.867726447
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.2624629111
Short name T239
Test name
Test status
Simulation time 27433899 ps
CPU time 0.78 seconds
Started Dec 24 12:56:27 PM PST 23
Finished Dec 24 12:56:29 PM PST 23
Peak memory 205988 kb
Host smart-ae1b19fa-5876-4b9f-bc1f-6653e8a2b6f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624629111 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.2624629111
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.814876881
Short name T445
Test name
Test status
Simulation time 11371099 ps
CPU time 0.79 seconds
Started Dec 24 12:56:05 PM PST 23
Finished Dec 24 12:56:11 PM PST 23
Peak memory 205996 kb
Host smart-cf9bc0e5-b48e-43a7-9a58-b1515c3ede2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814876881 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.814876881
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.2064376224
Short name T375
Test name
Test status
Simulation time 20599565 ps
CPU time 0.8 seconds
Started Dec 24 12:55:57 PM PST 23
Finished Dec 24 12:56:00 PM PST 23
Peak memory 206016 kb
Host smart-459c155b-8e31-43c3-8c90-48a8dd64b34e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064376224 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.2064376224
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.132897437
Short name T433
Test name
Test status
Simulation time 78800927 ps
CPU time 1.11 seconds
Started Dec 24 12:55:00 PM PST 23
Finished Dec 24 12:55:04 PM PST 23
Peak memory 205944 kb
Host smart-18060752-4019-4030-8139-7bcd34ebb645
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132897437 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.132897437
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.1788477560
Short name T242
Test name
Test status
Simulation time 184278023 ps
CPU time 3.07 seconds
Started Dec 24 12:54:50 PM PST 23
Finished Dec 24 12:54:57 PM PST 23
Peak memory 205976 kb
Host smart-635d1ebf-d09d-4f95-ad0b-b188b5d2a9c7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788477560 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.1788477560
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2930144590
Short name T223
Test name
Test status
Simulation time 39997971 ps
CPU time 0.84 seconds
Started Dec 24 12:54:56 PM PST 23
Finished Dec 24 12:55:01 PM PST 23
Peak memory 205956 kb
Host smart-94babff7-ba30-409c-9de0-0de4eaacd02e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930144590 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.2930144590
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2029909576
Short name T166
Test name
Test status
Simulation time 133141879 ps
CPU time 1.46 seconds
Started Dec 24 12:54:54 PM PST 23
Finished Dec 24 12:55:01 PM PST 23
Peak memory 214276 kb
Host smart-38099f2c-2ee4-46e8-b665-54f38c583d02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029909576 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.2029909576
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.617917794
Short name T395
Test name
Test status
Simulation time 12178285 ps
CPU time 0.83 seconds
Started Dec 24 12:54:58 PM PST 23
Finished Dec 24 12:55:02 PM PST 23
Peak memory 205728 kb
Host smart-d19ac7ee-4686-4c50-a223-eb565f654ef9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617917794 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.617917794
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.2984139850
Short name T36
Test name
Test status
Simulation time 51217247 ps
CPU time 0.85 seconds
Started Dec 24 12:54:57 PM PST 23
Finished Dec 24 12:55:01 PM PST 23
Peak memory 206020 kb
Host smart-99fdbf77-d310-400f-94b1-c101aa624305
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984139850 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.2984139850
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.563824967
Short name T417
Test name
Test status
Simulation time 22477128 ps
CPU time 1.07 seconds
Started Dec 24 12:54:57 PM PST 23
Finished Dec 24 12:55:02 PM PST 23
Peak memory 205952 kb
Host smart-8e161134-26e8-4617-9b40-950307cb4615
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563824967 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_out
standing.563824967
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.3929506600
Short name T392
Test name
Test status
Simulation time 282418312 ps
CPU time 1.95 seconds
Started Dec 24 12:54:53 PM PST 23
Finished Dec 24 12:55:01 PM PST 23
Peak memory 214132 kb
Host smart-a720595b-59a5-4ac9-b262-3c34bae2e9cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929506600 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.3929506600
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2786663450
Short name T410
Test name
Test status
Simulation time 144953913 ps
CPU time 3.24 seconds
Started Dec 24 12:54:50 PM PST 23
Finished Dec 24 12:54:57 PM PST 23
Peak memory 206068 kb
Host smart-2704b3c7-8cb5-4fe0-95ee-5a4194debc1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786663450 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.2786663450
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.1647861922
Short name T37
Test name
Test status
Simulation time 13274731 ps
CPU time 0.82 seconds
Started Dec 24 12:56:00 PM PST 23
Finished Dec 24 12:56:02 PM PST 23
Peak memory 205960 kb
Host smart-72f43f5e-20a7-452b-a885-488e17e894ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647861922 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.1647861922
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.1104659591
Short name T412
Test name
Test status
Simulation time 16622930 ps
CPU time 0.88 seconds
Started Dec 24 12:55:56 PM PST 23
Finished Dec 24 12:55:59 PM PST 23
Peak memory 205860 kb
Host smart-8aa2c93f-7425-4cff-beac-4590970ece6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104659591 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1104659591
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.3933379074
Short name T352
Test name
Test status
Simulation time 81237242 ps
CPU time 0.85 seconds
Started Dec 24 12:56:03 PM PST 23
Finished Dec 24 12:56:07 PM PST 23
Peak memory 205700 kb
Host smart-2fa460e1-b371-4fe6-bc04-35392fd6c1b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933379074 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.3933379074
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.694192350
Short name T255
Test name
Test status
Simulation time 55767268 ps
CPU time 0.79 seconds
Started Dec 24 12:55:59 PM PST 23
Finished Dec 24 12:56:02 PM PST 23
Peak memory 205580 kb
Host smart-c7a34fa6-9825-4ffa-b70f-f663d7bd023d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694192350 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.694192350
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.2238571820
Short name T437
Test name
Test status
Simulation time 51705626 ps
CPU time 0.84 seconds
Started Dec 24 12:56:07 PM PST 23
Finished Dec 24 12:56:12 PM PST 23
Peak memory 205920 kb
Host smart-17ff055f-8059-4d49-9e82-ba8b297b2f70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238571820 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.2238571820
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.2651445927
Short name T229
Test name
Test status
Simulation time 61100133 ps
CPU time 0.82 seconds
Started Dec 24 12:56:22 PM PST 23
Finished Dec 24 12:56:25 PM PST 23
Peak memory 205936 kb
Host smart-5e53ac8a-0292-40b4-9205-4606286eaf88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651445927 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.2651445927
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.2567082794
Short name T386
Test name
Test status
Simulation time 27508867 ps
CPU time 0.85 seconds
Started Dec 24 12:56:01 PM PST 23
Finished Dec 24 12:56:03 PM PST 23
Peak memory 206008 kb
Host smart-c693aded-90ca-49e0-b6f5-e890d8c3c71e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567082794 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.2567082794
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.1515078098
Short name T434
Test name
Test status
Simulation time 28902820 ps
CPU time 0.82 seconds
Started Dec 24 12:55:56 PM PST 23
Finished Dec 24 12:55:58 PM PST 23
Peak memory 205764 kb
Host smart-fa59b1e6-639e-43ce-86a9-e669273e6108
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515078098 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.1515078098
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.1430609381
Short name T442
Test name
Test status
Simulation time 18864254 ps
CPU time 0.78 seconds
Started Dec 24 12:56:01 PM PST 23
Finished Dec 24 12:56:05 PM PST 23
Peak memory 205744 kb
Host smart-e21d3790-b7f8-4afc-a370-bda66a53971c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430609381 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.1430609381
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.2864947031
Short name T390
Test name
Test status
Simulation time 69162901 ps
CPU time 0.82 seconds
Started Dec 24 12:56:05 PM PST 23
Finished Dec 24 12:56:11 PM PST 23
Peak memory 205816 kb
Host smart-b9726de1-a3e6-4f80-80da-bb1714842bc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864947031 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.2864947031
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3840992833
Short name T389
Test name
Test status
Simulation time 84136039 ps
CPU time 1.22 seconds
Started Dec 24 12:55:19 PM PST 23
Finished Dec 24 12:55:23 PM PST 23
Peak memory 206084 kb
Host smart-e5ee8e1d-a485-4449-a875-e307c5b617a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840992833 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.3840992833
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.3229647139
Short name T400
Test name
Test status
Simulation time 21042081 ps
CPU time 0.92 seconds
Started Dec 24 12:54:49 PM PST 23
Finished Dec 24 12:54:54 PM PST 23
Peak memory 206124 kb
Host smart-d9a074b2-5a5c-4c7d-ae47-c9325e0c8973
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229647139 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.3229647139
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.1836791250
Short name T414
Test name
Test status
Simulation time 39723717 ps
CPU time 0.83 seconds
Started Dec 24 12:54:49 PM PST 23
Finished Dec 24 12:54:54 PM PST 23
Peak memory 205712 kb
Host smart-359fe562-7c5d-47c5-a385-3b6e6098e6cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836791250 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.1836791250
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.530730573
Short name T383
Test name
Test status
Simulation time 26487291 ps
CPU time 1.16 seconds
Started Dec 24 12:54:53 PM PST 23
Finished Dec 24 12:55:01 PM PST 23
Peak memory 205916 kb
Host smart-99bcb07f-6088-4343-916c-1b32218c3553
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530730573 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_out
standing.530730573
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.2841142335
Short name T450
Test name
Test status
Simulation time 235667086 ps
CPU time 4.23 seconds
Started Dec 24 12:54:55 PM PST 23
Finished Dec 24 12:55:04 PM PST 23
Peak memory 214260 kb
Host smart-7f9b10b4-09b1-42db-a57a-d85c28cc7c36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841142335 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.2841142335
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.4230949316
Short name T430
Test name
Test status
Simulation time 413582087 ps
CPU time 1.57 seconds
Started Dec 24 12:54:47 PM PST 23
Finished Dec 24 12:54:54 PM PST 23
Peak memory 205908 kb
Host smart-33dcf860-1506-4807-98e2-411c3488216e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230949316 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.4230949316
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3360430667
Short name T170
Test name
Test status
Simulation time 77274174 ps
CPU time 0.93 seconds
Started Dec 24 12:55:19 PM PST 23
Finished Dec 24 12:55:23 PM PST 23
Peak memory 206076 kb
Host smart-ae8d7c36-533e-4d82-9e2e-f1682a22ecfc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360430667 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.3360430667
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.1386804379
Short name T408
Test name
Test status
Simulation time 20012682 ps
CPU time 0.99 seconds
Started Dec 24 12:55:19 PM PST 23
Finished Dec 24 12:55:22 PM PST 23
Peak memory 205944 kb
Host smart-ae349f18-eee1-4bbf-9338-417a2fddfa42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386804379 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.1386804379
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.1886573926
Short name T421
Test name
Test status
Simulation time 51743724 ps
CPU time 0.82 seconds
Started Dec 24 12:55:18 PM PST 23
Finished Dec 24 12:55:22 PM PST 23
Peak memory 205752 kb
Host smart-c84e89f1-39d9-4437-9579-0d6f905a55e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886573926 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.1886573926
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.24517175
Short name T420
Test name
Test status
Simulation time 55258966 ps
CPU time 1.26 seconds
Started Dec 24 12:55:20 PM PST 23
Finished Dec 24 12:55:24 PM PST 23
Peak memory 205896 kb
Host smart-aed5ef86-df41-4f7c-863b-5806e20035dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24517175 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_outs
tanding.24517175
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.4099119842
Short name T449
Test name
Test status
Simulation time 69450448 ps
CPU time 2.43 seconds
Started Dec 24 12:55:14 PM PST 23
Finished Dec 24 12:55:18 PM PST 23
Peak memory 214264 kb
Host smart-b6758b70-5d9d-4148-8dda-67de18e8e2f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099119842 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.4099119842
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2738386055
Short name T371
Test name
Test status
Simulation time 184772296 ps
CPU time 1.34 seconds
Started Dec 24 12:55:29 PM PST 23
Finished Dec 24 12:55:33 PM PST 23
Peak memory 214144 kb
Host smart-98102758-d513-430c-ab4b-90ecf3bfa9b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738386055 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2738386055
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.3045091782
Short name T168
Test name
Test status
Simulation time 14035470 ps
CPU time 0.87 seconds
Started Dec 24 12:55:19 PM PST 23
Finished Dec 24 12:55:23 PM PST 23
Peak memory 205924 kb
Host smart-44a4a123-b667-4f83-967c-ee24b5a61b91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045091782 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.3045091782
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.2724342687
Short name T397
Test name
Test status
Simulation time 20445025 ps
CPU time 0.82 seconds
Started Dec 24 12:55:14 PM PST 23
Finished Dec 24 12:55:17 PM PST 23
Peak memory 205904 kb
Host smart-7ca9e9fb-b2d4-4fc0-8727-8f44ce35b2fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724342687 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.2724342687
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.296522750
Short name T406
Test name
Test status
Simulation time 50412919 ps
CPU time 1.05 seconds
Started Dec 24 12:55:14 PM PST 23
Finished Dec 24 12:55:17 PM PST 23
Peak memory 206060 kb
Host smart-83a7645b-a8a6-4bd7-8806-d9954d8fade4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296522750 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_out
standing.296522750
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.1855574734
Short name T415
Test name
Test status
Simulation time 65792118 ps
CPU time 2.39 seconds
Started Dec 24 12:55:15 PM PST 23
Finished Dec 24 12:55:19 PM PST 23
Peak memory 214260 kb
Host smart-7bbfd87f-f10a-478c-9bb8-f99170e22232
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855574734 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.1855574734
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1843602065
Short name T368
Test name
Test status
Simulation time 121420844 ps
CPU time 1.41 seconds
Started Dec 24 12:55:15 PM PST 23
Finished Dec 24 12:55:19 PM PST 23
Peak memory 206096 kb
Host smart-0a9cac66-ac6a-44d3-bfc0-0489f593582a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843602065 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.1843602065
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3161781854
Short name T165
Test name
Test status
Simulation time 26647741 ps
CPU time 1.16 seconds
Started Dec 24 12:55:21 PM PST 23
Finished Dec 24 12:55:25 PM PST 23
Peak memory 214328 kb
Host smart-f259feb3-0e68-4f10-872f-4a84960cc888
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161781854 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3161781854
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.1386022785
Short name T233
Test name
Test status
Simulation time 43154802 ps
CPU time 0.82 seconds
Started Dec 24 12:55:15 PM PST 23
Finished Dec 24 12:55:18 PM PST 23
Peak memory 206016 kb
Host smart-7e328920-9e1c-4fb1-90cd-12319998c7c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386022785 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.1386022785
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.1744418810
Short name T384
Test name
Test status
Simulation time 16298758 ps
CPU time 0.93 seconds
Started Dec 24 12:55:16 PM PST 23
Finished Dec 24 12:55:19 PM PST 23
Peak memory 205976 kb
Host smart-5a69106b-c524-4c51-8b84-c1f229b0619e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744418810 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1744418810
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.357313299
Short name T407
Test name
Test status
Simulation time 25588490 ps
CPU time 0.87 seconds
Started Dec 24 12:55:19 PM PST 23
Finished Dec 24 12:55:22 PM PST 23
Peak memory 206036 kb
Host smart-09876d42-59c4-49d6-984d-082d58ac44d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357313299 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_out
standing.357313299
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.2693903837
Short name T365
Test name
Test status
Simulation time 261756342 ps
CPU time 2.78 seconds
Started Dec 24 12:55:17 PM PST 23
Finished Dec 24 12:55:23 PM PST 23
Peak memory 217504 kb
Host smart-1e792e20-2531-4b05-8a78-a374c572b431
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693903837 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.2693903837
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2152357100
Short name T422
Test name
Test status
Simulation time 28472471 ps
CPU time 1.12 seconds
Started Dec 24 12:55:17 PM PST 23
Finished Dec 24 12:55:20 PM PST 23
Peak memory 214304 kb
Host smart-7cfa83f5-e3af-4908-b492-48fb7db9c66a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152357100 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.2152357100
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.503972989
Short name T230
Test name
Test status
Simulation time 33127485 ps
CPU time 0.83 seconds
Started Dec 24 12:55:16 PM PST 23
Finished Dec 24 12:55:19 PM PST 23
Peak memory 205936 kb
Host smart-634a8fc7-fb05-43f4-9f39-0db0e1548212
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503972989 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.503972989
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.839778642
Short name T424
Test name
Test status
Simulation time 24964405 ps
CPU time 0.87 seconds
Started Dec 24 12:55:20 PM PST 23
Finished Dec 24 12:55:24 PM PST 23
Peak memory 206040 kb
Host smart-758251d0-55c1-4004-9943-ca0b665cb24d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839778642 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.839778642
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.774702205
Short name T438
Test name
Test status
Simulation time 41049085 ps
CPU time 0.92 seconds
Started Dec 24 12:55:23 PM PST 23
Finished Dec 24 12:55:28 PM PST 23
Peak memory 205976 kb
Host smart-1453a090-e73c-423e-b97d-b112987d8608
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774702205 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_out
standing.774702205
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.3818013888
Short name T154
Test name
Test status
Simulation time 195632856 ps
CPU time 2.01 seconds
Started Dec 24 12:55:18 PM PST 23
Finished Dec 24 12:55:22 PM PST 23
Peak memory 214204 kb
Host smart-16c59878-c5ea-4d50-a61f-2e00c11bcda8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818013888 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.3818013888
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3935229453
Short name T432
Test name
Test status
Simulation time 312823458 ps
CPU time 2.27 seconds
Started Dec 24 12:55:19 PM PST 23
Finished Dec 24 12:55:24 PM PST 23
Peak memory 205992 kb
Host smart-88ca26b4-d5ff-4400-8297-9eee4bd8ec84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935229453 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.3935229453
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.2684979481
Short name T584
Test name
Test status
Simulation time 117271870 ps
CPU time 0.96 seconds
Started Dec 24 01:41:49 PM PST 23
Finished Dec 24 01:41:51 PM PST 23
Peak memory 205288 kb
Host smart-93140300-ebdc-49c1-a644-b747a2c42a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684979481 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.2684979481
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.83688600
Short name T484
Test name
Test status
Simulation time 24531025 ps
CPU time 0.81 seconds
Started Dec 24 01:41:55 PM PST 23
Finished Dec 24 01:42:02 PM PST 23
Peak memory 204336 kb
Host smart-56c3b031-c7a6-4aa8-8536-7e0f16fc2210
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83688600 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.83688600
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.1323623633
Short name T117
Test name
Test status
Simulation time 19930580 ps
CPU time 0.83 seconds
Started Dec 24 01:41:51 PM PST 23
Finished Dec 24 01:41:55 PM PST 23
Peak memory 214148 kb
Host smart-1bf55237-0744-470f-9270-dab66dfd91e7
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323623633 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.1323623633
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_err.3266922369
Short name T204
Test name
Test status
Simulation time 53352824 ps
CPU time 1.03 seconds
Started Dec 24 01:41:51 PM PST 23
Finished Dec 24 01:41:53 PM PST 23
Peak memory 216760 kb
Host smart-1588f4bc-de09-43a6-9942-0371dc3a031b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266922369 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.3266922369
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.316674020
Short name T33
Test name
Test status
Simulation time 16315380 ps
CPU time 0.94 seconds
Started Dec 24 01:41:52 PM PST 23
Finished Dec 24 01:41:57 PM PST 23
Peak memory 205000 kb
Host smart-c5179ac7-d3d5-4c1f-99f1-ebfbd538351a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316674020 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.316674020
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.166451934
Short name T809
Test name
Test status
Simulation time 37426467 ps
CPU time 0.95 seconds
Started Dec 24 01:41:51 PM PST 23
Finished Dec 24 01:41:55 PM PST 23
Peak memory 214428 kb
Host smart-53a67a90-2bcc-43fb-b11f-4a7921401d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166451934 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.166451934
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_sec_cm.3146874451
Short name T44
Test name
Test status
Simulation time 426737038 ps
CPU time 6.55 seconds
Started Dec 24 01:41:53 PM PST 23
Finished Dec 24 01:42:05 PM PST 23
Peak memory 232924 kb
Host smart-4a697c54-b33e-4ff5-9d66-e4781bc740cd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146874451 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.3146874451
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.3632183014
Short name T563
Test name
Test status
Simulation time 21535613 ps
CPU time 0.88 seconds
Started Dec 24 01:41:52 PM PST 23
Finished Dec 24 01:41:55 PM PST 23
Peak memory 204648 kb
Host smart-3672c3b6-119f-4f03-bed2-eefeb63eb0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632183014 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.3632183014
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.261031827
Short name T567
Test name
Test status
Simulation time 327661003 ps
CPU time 2.9 seconds
Started Dec 24 01:41:54 PM PST 23
Finished Dec 24 01:42:03 PM PST 23
Peak memory 205956 kb
Host smart-f46d8946-f8b2-4a5f-9b80-79269a42007d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261031827 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.261031827
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.2895426349
Short name T817
Test name
Test status
Simulation time 675115619542 ps
CPU time 1147.48 seconds
Started Dec 24 01:42:18 PM PST 23
Finished Dec 24 02:01:28 PM PST 23
Peak memory 216980 kb
Host smart-40889450-fdf1-49e5-8ddb-e3d036a3477a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895426349 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.2895426349
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert_test.970476703
Short name T673
Test name
Test status
Simulation time 15077861 ps
CPU time 0.86 seconds
Started Dec 24 01:41:54 PM PST 23
Finished Dec 24 01:42:01 PM PST 23
Peak memory 205184 kb
Host smart-b7d5bd4b-04ff-4ee5-9e68-4863cd36a6cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970476703 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.970476703
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.1144785255
Short name T542
Test name
Test status
Simulation time 89879495 ps
CPU time 1.08 seconds
Started Dec 24 01:41:54 PM PST 23
Finished Dec 24 01:42:02 PM PST 23
Peak memory 214356 kb
Host smart-9b57df29-86d9-4b66-a8e2-b9928aeeb657
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144785255 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.1144785255
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.656268655
Short name T137
Test name
Test status
Simulation time 19590427 ps
CPU time 1.11 seconds
Started Dec 24 01:42:19 PM PST 23
Finished Dec 24 01:42:22 PM PST 23
Peak memory 214456 kb
Host smart-e3b461c9-74ed-494e-a25f-666a65809195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656268655 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.656268655
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_regwen.668553729
Short name T324
Test name
Test status
Simulation time 12355096 ps
CPU time 0.9 seconds
Started Dec 24 01:41:52 PM PST 23
Finished Dec 24 01:41:55 PM PST 23
Peak memory 204648 kb
Host smart-0fab3412-f80b-46b3-83f1-a206d64dd6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668553729 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.668553729
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.580026990
Short name T24
Test name
Test status
Simulation time 469076747 ps
CPU time 4 seconds
Started Dec 24 01:41:52 PM PST 23
Finished Dec 24 01:42:00 PM PST 23
Peak memory 231876 kb
Host smart-69347d0a-ec51-4be0-aa11-e7212e35bea5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580026990 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.580026990
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.84277465
Short name T463
Test name
Test status
Simulation time 13028987 ps
CPU time 0.89 seconds
Started Dec 24 01:42:17 PM PST 23
Finished Dec 24 01:42:20 PM PST 23
Peak memory 204708 kb
Host smart-1b1ca897-21f0-4386-a2fc-b5069c514094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84277465 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.84277465
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.3423784327
Short name T717
Test name
Test status
Simulation time 169032188 ps
CPU time 1.01 seconds
Started Dec 24 01:41:49 PM PST 23
Finished Dec 24 01:41:51 PM PST 23
Peak memory 204868 kb
Host smart-eef439a4-0bb0-42bc-aa8f-34cf104373ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423784327 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.3423784327
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.3946504098
Short name T494
Test name
Test status
Simulation time 43023497083 ps
CPU time 490.5 seconds
Started Dec 24 01:41:55 PM PST 23
Finished Dec 24 01:50:12 PM PST 23
Peak memory 215304 kb
Host smart-7f2f65b7-23f6-4aa3-9d18-be5ee178f6c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946504098 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.3946504098
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert_test.2275206217
Short name T769
Test name
Test status
Simulation time 140190099 ps
CPU time 0.82 seconds
Started Dec 24 01:42:46 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 204160 kb
Host smart-f10a300b-8b92-4489-b9c3-c87be3d9ffa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275206217 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2275206217
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.1744832285
Short name T841
Test name
Test status
Simulation time 30978330 ps
CPU time 1.02 seconds
Started Dec 24 01:42:43 PM PST 23
Finished Dec 24 01:43:00 PM PST 23
Peak memory 214516 kb
Host smart-00d92ea8-40a8-42e6-8cb6-b5767b08af8b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744832285 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.1744832285
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.2521790065
Short name T193
Test name
Test status
Simulation time 35786510 ps
CPU time 1.05 seconds
Started Dec 24 01:42:47 PM PST 23
Finished Dec 24 01:43:08 PM PST 23
Peak memory 214412 kb
Host smart-3e23f86b-ded0-4b74-851a-7a7d9fbfde95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521790065 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.2521790065
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.69441921
Short name T692
Test name
Test status
Simulation time 18522554 ps
CPU time 1.2 seconds
Started Dec 24 01:42:39 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 205932 kb
Host smart-ba1620a4-0cff-493d-898f-7cc2e45db62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69441921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.69441921
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.4019399635
Short name T706
Test name
Test status
Simulation time 33640206 ps
CPU time 0.84 seconds
Started Dec 24 01:42:40 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 214236 kb
Host smart-4a153340-4e39-4385-a43c-95c7ff3d6215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019399635 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.4019399635
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.2254102974
Short name T477
Test name
Test status
Simulation time 27925561 ps
CPU time 0.89 seconds
Started Dec 24 01:42:44 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 204640 kb
Host smart-979bca7e-5c9d-44ed-a30d-cea4a4c07791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254102974 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.2254102974
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.4066501379
Short name T881
Test name
Test status
Simulation time 43898179914 ps
CPU time 971.2 seconds
Started Dec 24 01:42:40 PM PST 23
Finished Dec 24 01:59:03 PM PST 23
Peak memory 214844 kb
Host smart-9551a437-72b8-4483-ba66-ae42b4f826cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066501379 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.4066501379
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.1037582256
Short name T779
Test name
Test status
Simulation time 17846059 ps
CPU time 1.1 seconds
Started Dec 24 01:44:07 PM PST 23
Finished Dec 24 01:44:26 PM PST 23
Peak memory 205560 kb
Host smart-81bfe77c-ddac-43d8-9db2-a33995a4c608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037582256 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.1037582256
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.399368067
Short name T862
Test name
Test status
Simulation time 94490390 ps
CPU time 0.92 seconds
Started Dec 24 01:44:07 PM PST 23
Finished Dec 24 01:44:27 PM PST 23
Peak memory 205056 kb
Host smart-ab9457fb-5a9f-484d-b6af-061b5b600d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399368067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.399368067
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.684301325
Short name T804
Test name
Test status
Simulation time 84691809 ps
CPU time 1.17 seconds
Started Dec 24 01:44:05 PM PST 23
Finished Dec 24 01:44:20 PM PST 23
Peak memory 205604 kb
Host smart-58b1ecdb-acae-4976-826f-9f7920388a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684301325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.684301325
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.3047873680
Short name T576
Test name
Test status
Simulation time 149860922 ps
CPU time 1.24 seconds
Started Dec 24 01:44:07 PM PST 23
Finished Dec 24 01:44:26 PM PST 23
Peak memory 205360 kb
Host smart-bccb83d3-b7ed-494d-bc79-4be08d5fc4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047873680 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.3047873680
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.2368269267
Short name T575
Test name
Test status
Simulation time 14795767 ps
CPU time 1.04 seconds
Started Dec 24 01:44:06 PM PST 23
Finished Dec 24 01:44:24 PM PST 23
Peak memory 205696 kb
Host smart-bbbb8e9e-b89a-4705-972c-83f5c8b9241e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368269267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.2368269267
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.1196994237
Short name T307
Test name
Test status
Simulation time 46423381 ps
CPU time 0.95 seconds
Started Dec 24 01:44:05 PM PST 23
Finished Dec 24 01:44:19 PM PST 23
Peak memory 205256 kb
Host smart-9d2edef8-6ea4-4ff8-aa50-b82337cd8b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196994237 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1196994237
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.1351889110
Short name T337
Test name
Test status
Simulation time 27909833 ps
CPU time 1 seconds
Started Dec 24 01:44:03 PM PST 23
Finished Dec 24 01:44:14 PM PST 23
Peak memory 205412 kb
Host smart-c4cb49d6-7f8b-4293-82a7-5de67928a3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351889110 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.1351889110
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.347690833
Short name T760
Test name
Test status
Simulation time 27615630 ps
CPU time 1.08 seconds
Started Dec 24 01:44:02 PM PST 23
Finished Dec 24 01:44:11 PM PST 23
Peak memory 214128 kb
Host smart-1c948a24-5126-4050-9995-a2a6d889062b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347690833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.347690833
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.3542144911
Short name T691
Test name
Test status
Simulation time 63733607 ps
CPU time 0.99 seconds
Started Dec 24 01:42:47 PM PST 23
Finished Dec 24 01:43:06 PM PST 23
Peak memory 205332 kb
Host smart-1b00e31c-5b9b-47bf-883f-c7d28d6d6134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542144911 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.3542144911
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_disable.3041751073
Short name T205
Test name
Test status
Simulation time 27261227 ps
CPU time 0.77 seconds
Started Dec 24 01:42:46 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 214332 kb
Host smart-c4bf2a1e-83e3-41dd-a037-c3149e604f8d
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041751073 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3041751073
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_err.649484357
Short name T203
Test name
Test status
Simulation time 44233424 ps
CPU time 1 seconds
Started Dec 24 01:42:49 PM PST 23
Finished Dec 24 01:43:13 PM PST 23
Peak memory 221132 kb
Host smart-92d4ded1-8f39-4448-a61c-f6097e3a0515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649484357 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.649484357
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.1176037763
Short name T280
Test name
Test status
Simulation time 151121688 ps
CPU time 1.05 seconds
Started Dec 24 01:42:48 PM PST 23
Finished Dec 24 01:43:10 PM PST 23
Peak memory 205048 kb
Host smart-9fe0f63f-0aa2-4d68-83a2-a8121e11d781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176037763 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1176037763
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.2668924881
Short name T921
Test name
Test status
Simulation time 32665900 ps
CPU time 0.87 seconds
Started Dec 24 01:42:47 PM PST 23
Finished Dec 24 01:43:08 PM PST 23
Peak memory 213896 kb
Host smart-cb78a711-c69f-40e0-b2e0-5d1354899d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668924881 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.2668924881
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.1449941317
Short name T908
Test name
Test status
Simulation time 14116638 ps
CPU time 0.93 seconds
Started Dec 24 01:42:48 PM PST 23
Finished Dec 24 01:43:11 PM PST 23
Peak memory 204880 kb
Host smart-a1305145-e8fa-4526-898a-7774dd4957c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449941317 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.1449941317
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.1101614426
Short name T737
Test name
Test status
Simulation time 416746880 ps
CPU time 4.31 seconds
Started Dec 24 01:42:44 PM PST 23
Finished Dec 24 01:43:08 PM PST 23
Peak memory 206064 kb
Host smart-40a3b9ce-c276-4acd-b1a6-7f73e71dc607
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101614426 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1101614426
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/110.edn_genbits.2606737643
Short name T605
Test name
Test status
Simulation time 254336280 ps
CPU time 1.06 seconds
Started Dec 24 01:44:07 PM PST 23
Finished Dec 24 01:44:27 PM PST 23
Peak memory 204920 kb
Host smart-6dc6d0dd-2600-4c0e-a036-54f10c0d42ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606737643 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2606737643
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.1534562186
Short name T910
Test name
Test status
Simulation time 19144901 ps
CPU time 1.04 seconds
Started Dec 24 01:44:02 PM PST 23
Finished Dec 24 01:44:09 PM PST 23
Peak memory 204980 kb
Host smart-56ea9b79-0ec5-4c08-95f2-afc45006d4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534562186 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.1534562186
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.2422001280
Short name T956
Test name
Test status
Simulation time 243685746 ps
CPU time 0.95 seconds
Started Dec 24 01:44:01 PM PST 23
Finished Dec 24 01:44:08 PM PST 23
Peak memory 205364 kb
Host smart-c0464686-2302-44a2-bf76-0563c306e34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422001280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.2422001280
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.1987080810
Short name T775
Test name
Test status
Simulation time 54729556 ps
CPU time 1 seconds
Started Dec 24 01:44:02 PM PST 23
Finished Dec 24 01:44:10 PM PST 23
Peak memory 205436 kb
Host smart-39d7c536-1553-4c77-869b-f5d110732095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987080810 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.1987080810
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.2473151179
Short name T640
Test name
Test status
Simulation time 88546792 ps
CPU time 0.99 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:19 PM PST 23
Peak memory 205152 kb
Host smart-13e7c647-4e51-421d-98b0-daad3bc45699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473151179 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.2473151179
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.1082768877
Short name T790
Test name
Test status
Simulation time 25080763 ps
CPU time 1.14 seconds
Started Dec 24 01:44:02 PM PST 23
Finished Dec 24 01:44:11 PM PST 23
Peak memory 205708 kb
Host smart-2e1b121a-d616-48dc-9b7d-c1b5ffda6b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082768877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.1082768877
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.823404139
Short name T466
Test name
Test status
Simulation time 129245969 ps
CPU time 2.69 seconds
Started Dec 24 01:44:01 PM PST 23
Finished Dec 24 01:44:33 PM PST 23
Peak memory 214164 kb
Host smart-1f4e0a18-afbc-4ab5-9035-f6b6130015e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823404139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.823404139
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.3907633771
Short name T343
Test name
Test status
Simulation time 45279624 ps
CPU time 0.92 seconds
Started Dec 24 01:44:02 PM PST 23
Finished Dec 24 01:44:09 PM PST 23
Peak memory 205252 kb
Host smart-dcb592b0-8c67-4fc3-a24f-5a52cf2fe673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907633771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3907633771
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.2276120413
Short name T843
Test name
Test status
Simulation time 17840697 ps
CPU time 1 seconds
Started Dec 24 01:42:46 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 205292 kb
Host smart-f9c97ed1-1869-4688-9476-514c27157c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276120413 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.2276120413
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.2274995210
Short name T549
Test name
Test status
Simulation time 14984714 ps
CPU time 0.91 seconds
Started Dec 24 01:42:37 PM PST 23
Finished Dec 24 01:42:44 PM PST 23
Peak memory 204572 kb
Host smart-f5e0979c-f9ea-4309-b1c1-ad5f07fc6a48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274995210 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2274995210
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.983089543
Short name T134
Test name
Test status
Simulation time 26386330 ps
CPU time 0.84 seconds
Started Dec 24 01:42:47 PM PST 23
Finished Dec 24 01:43:06 PM PST 23
Peak memory 214116 kb
Host smart-1e495589-5452-4dbe-83da-2fec6694e6bb
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983089543 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.983089543
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_genbits.608803901
Short name T705
Test name
Test status
Simulation time 40280326 ps
CPU time 1.07 seconds
Started Dec 24 01:42:49 PM PST 23
Finished Dec 24 01:43:13 PM PST 23
Peak memory 205344 kb
Host smart-efef50d1-5883-4a37-b323-303bfd43bfc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608803901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.608803901
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.20072994
Short name T713
Test name
Test status
Simulation time 25112984 ps
CPU time 0.95 seconds
Started Dec 24 01:42:39 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 214300 kb
Host smart-cc10f544-f27a-4129-891f-741577739b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20072994 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.20072994
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.909742176
Short name T503
Test name
Test status
Simulation time 24190775 ps
CPU time 0.87 seconds
Started Dec 24 01:42:38 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 204744 kb
Host smart-7516b3de-03b9-4e49-ada0-bed3d3ce6bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909742176 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.909742176
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.2239623424
Short name T623
Test name
Test status
Simulation time 68795086 ps
CPU time 1.41 seconds
Started Dec 24 01:42:38 PM PST 23
Finished Dec 24 01:42:52 PM PST 23
Peak memory 205164 kb
Host smart-f7bee054-391c-41c8-8886-0b538347fddc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239623424 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.2239623424
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.3247528255
Short name T538
Test name
Test status
Simulation time 63889454418 ps
CPU time 361.37 seconds
Started Dec 24 01:42:47 PM PST 23
Finished Dec 24 01:49:07 PM PST 23
Peak memory 215328 kb
Host smart-8c920ed8-7a73-46de-a4bb-884d452501ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247528255 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.3247528255
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.142408780
Short name T953
Test name
Test status
Simulation time 146187742 ps
CPU time 1.19 seconds
Started Dec 24 01:44:01 PM PST 23
Finished Dec 24 01:44:07 PM PST 23
Peak memory 214164 kb
Host smart-b16c5c8a-934c-4d7b-9a4c-7fab3853e5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142408780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.142408780
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.2062974657
Short name T839
Test name
Test status
Simulation time 30408809 ps
CPU time 1.09 seconds
Started Dec 24 01:44:01 PM PST 23
Finished Dec 24 01:44:08 PM PST 23
Peak memory 214144 kb
Host smart-b1c600c5-0af5-4104-8e0c-195ccffdc9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062974657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.2062974657
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.3236020791
Short name T338
Test name
Test status
Simulation time 43229275 ps
CPU time 0.87 seconds
Started Dec 24 01:44:02 PM PST 23
Finished Dec 24 01:44:10 PM PST 23
Peak memory 204976 kb
Host smart-1734c5f7-acf3-49ff-bf6b-453c79b765d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236020791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.3236020791
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.2169620624
Short name T350
Test name
Test status
Simulation time 209639961 ps
CPU time 3.13 seconds
Started Dec 24 01:44:02 PM PST 23
Finished Dec 24 01:44:13 PM PST 23
Peak memory 214176 kb
Host smart-54d06676-8b4d-42cb-8df6-197e2764bb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169620624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.2169620624
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.3719192594
Short name T878
Test name
Test status
Simulation time 131445632 ps
CPU time 1.13 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:18 PM PST 23
Peak memory 205388 kb
Host smart-a8ead4ac-176e-4575-9a01-f3d4336583ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719192594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.3719192594
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.3128259233
Short name T53
Test name
Test status
Simulation time 39663820 ps
CPU time 1.67 seconds
Started Dec 24 01:44:11 PM PST 23
Finished Dec 24 01:44:33 PM PST 23
Peak memory 213924 kb
Host smart-c88f12ca-af44-4a5c-82f0-801923c9841b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128259233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.3128259233
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.3743350694
Short name T876
Test name
Test status
Simulation time 15794408 ps
CPU time 0.96 seconds
Started Dec 24 01:44:02 PM PST 23
Finished Dec 24 01:44:09 PM PST 23
Peak memory 205112 kb
Host smart-9d5b2e4c-6772-4e67-b2eb-efd4e6855b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743350694 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.3743350694
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.3191296346
Short name T614
Test name
Test status
Simulation time 12065821 ps
CPU time 0.9 seconds
Started Dec 24 01:44:02 PM PST 23
Finished Dec 24 01:44:11 PM PST 23
Peak memory 205112 kb
Host smart-2c54b69f-5de6-4dce-9685-f234566f4f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191296346 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.3191296346
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.1631678042
Short name T51
Test name
Test status
Simulation time 39791123 ps
CPU time 1.3 seconds
Started Dec 24 01:44:03 PM PST 23
Finished Dec 24 01:44:15 PM PST 23
Peak memory 205356 kb
Host smart-230f4f77-bbc1-48e5-a41e-bcc44127a717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631678042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.1631678042
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.1661355933
Short name T320
Test name
Test status
Simulation time 64361090 ps
CPU time 0.97 seconds
Started Dec 24 01:42:42 PM PST 23
Finished Dec 24 01:42:54 PM PST 23
Peak memory 205940 kb
Host smart-9b86f030-6c93-4b93-b33f-d3c3b5554095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661355933 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.1661355933
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.4227794796
Short name T520
Test name
Test status
Simulation time 56925301 ps
CPU time 0.92 seconds
Started Dec 24 01:42:36 PM PST 23
Finished Dec 24 01:42:43 PM PST 23
Peak memory 205100 kb
Host smart-e010bf26-c2fc-4b5e-a67e-6aee0c40d2da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227794796 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.4227794796
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.1233285372
Short name T135
Test name
Test status
Simulation time 94448683 ps
CPU time 1.08 seconds
Started Dec 24 01:42:37 PM PST 23
Finished Dec 24 01:42:44 PM PST 23
Peak memory 214500 kb
Host smart-10d76e09-bd58-4413-b70f-52e0a44e4244
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233285372 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.1233285372
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.672457028
Short name T209
Test name
Test status
Simulation time 21531541 ps
CPU time 0.92 seconds
Started Dec 24 01:42:39 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 215484 kb
Host smart-469b7e28-cb30-4594-abd3-463456a0b614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672457028 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.672457028
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.3534553794
Short name T452
Test name
Test status
Simulation time 17124402 ps
CPU time 0.93 seconds
Started Dec 24 01:42:44 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 204800 kb
Host smart-8108fdc6-f973-49b8-8c98-4b9528299c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534553794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.3534553794
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.3314289395
Short name T960
Test name
Test status
Simulation time 37743919 ps
CPU time 0.89 seconds
Started Dec 24 01:42:46 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 214220 kb
Host smart-e74dde04-6f98-4b83-922a-e1a077525dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314289395 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.3314289395
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.1902801911
Short name T733
Test name
Test status
Simulation time 15907956 ps
CPU time 0.93 seconds
Started Dec 24 01:42:44 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 204672 kb
Host smart-e01e311e-de67-495d-b9f5-e755a9e64c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902801911 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.1902801911
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.988773879
Short name T801
Test name
Test status
Simulation time 30927616 ps
CPU time 0.97 seconds
Started Dec 24 01:42:47 PM PST 23
Finished Dec 24 01:43:06 PM PST 23
Peak memory 204236 kb
Host smart-b5c05ccd-66ab-44c6-8f57-185348c7c428
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988773879 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.988773879
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.4223969642
Short name T963
Test name
Test status
Simulation time 1369895926959 ps
CPU time 2111.96 seconds
Started Dec 24 01:42:38 PM PST 23
Finished Dec 24 02:18:01 PM PST 23
Peak memory 218848 kb
Host smart-e3ee40a7-e5f5-46cd-9a59-17a4db39de4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223969642 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.4223969642
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.2161020814
Short name T891
Test name
Test status
Simulation time 202138294 ps
CPU time 1.11 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:18 PM PST 23
Peak memory 205764 kb
Host smart-9f15efbb-1221-449d-8d97-b721a22d5bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161020814 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.2161020814
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.2412281522
Short name T616
Test name
Test status
Simulation time 23185376 ps
CPU time 1.09 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:19 PM PST 23
Peak memory 205584 kb
Host smart-59a7fef5-9399-4e03-8fbe-595e6f8b9964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412281522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.2412281522
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.2611280739
Short name T892
Test name
Test status
Simulation time 31365177 ps
CPU time 0.97 seconds
Started Dec 24 01:44:05 PM PST 23
Finished Dec 24 01:44:20 PM PST 23
Peak memory 204416 kb
Host smart-98854677-0bc1-4225-a8e2-865a9898cc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611280739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.2611280739
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.2076001670
Short name T828
Test name
Test status
Simulation time 20828911 ps
CPU time 1 seconds
Started Dec 24 01:44:03 PM PST 23
Finished Dec 24 01:44:13 PM PST 23
Peak memory 205236 kb
Host smart-1a29d219-1128-4180-9aa0-e7919dfaca7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076001670 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.2076001670
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.3660886368
Short name T845
Test name
Test status
Simulation time 54208921 ps
CPU time 0.95 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:19 PM PST 23
Peak memory 205480 kb
Host smart-2ca46881-1334-40c4-98df-946348e94d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660886368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.3660886368
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.2341759810
Short name T709
Test name
Test status
Simulation time 301039402 ps
CPU time 3.61 seconds
Started Dec 24 01:44:05 PM PST 23
Finished Dec 24 01:44:22 PM PST 23
Peak memory 214092 kb
Host smart-a2ca9215-330c-4d38-af6b-eff95be0fa66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341759810 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.2341759810
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.1738922906
Short name T860
Test name
Test status
Simulation time 24968832 ps
CPU time 1.04 seconds
Started Dec 24 01:44:05 PM PST 23
Finished Dec 24 01:44:20 PM PST 23
Peak memory 205556 kb
Host smart-c1629c0e-7635-455a-bd65-555c1f1ac59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738922906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.1738922906
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.1357523115
Short name T754
Test name
Test status
Simulation time 26580545 ps
CPU time 0.96 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:19 PM PST 23
Peak memory 205440 kb
Host smart-89700ee6-204d-4086-b180-0685db5a5962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357523115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1357523115
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.982255701
Short name T824
Test name
Test status
Simulation time 37805339 ps
CPU time 0.91 seconds
Started Dec 24 01:44:07 PM PST 23
Finished Dec 24 01:44:27 PM PST 23
Peak memory 205424 kb
Host smart-bed79014-92f9-453f-800e-42b8ca015d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982255701 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.982255701
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.222506919
Short name T744
Test name
Test status
Simulation time 69773036 ps
CPU time 1.09 seconds
Started Dec 24 01:44:05 PM PST 23
Finished Dec 24 01:44:21 PM PST 23
Peak memory 214156 kb
Host smart-1e256f8c-9f17-4f30-a5ec-92191ce1e9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222506919 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.222506919
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert_test.493929770
Short name T855
Test name
Test status
Simulation time 75287215 ps
CPU time 0.82 seconds
Started Dec 24 01:42:49 PM PST 23
Finished Dec 24 01:43:13 PM PST 23
Peak memory 205084 kb
Host smart-65fbf6cf-1b55-4707-8117-90ba6df495a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493929770 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.493929770
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.1544666756
Short name T795
Test name
Test status
Simulation time 82155391 ps
CPU time 1.06 seconds
Started Dec 24 01:42:39 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 214504 kb
Host smart-bbca703e-79f6-402e-a4cd-772f721b7835
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544666756 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.1544666756
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.2154209566
Short name T868
Test name
Test status
Simulation time 20962086 ps
CPU time 1.1 seconds
Started Dec 24 01:42:39 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 221696 kb
Host smart-d2fddc1e-a235-4b9f-bfed-d77cfb57c90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154209566 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.2154209566
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.3601883839
Short name T887
Test name
Test status
Simulation time 78661572 ps
CPU time 2.23 seconds
Started Dec 24 01:42:39 PM PST 23
Finished Dec 24 01:42:54 PM PST 23
Peak memory 213928 kb
Host smart-a5289523-9173-4f54-97bc-52ecf2935686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601883839 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.3601883839
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.1758706945
Short name T534
Test name
Test status
Simulation time 19956233 ps
CPU time 1.06 seconds
Started Dec 24 01:42:39 PM PST 23
Finished Dec 24 01:42:54 PM PST 23
Peak memory 214228 kb
Host smart-d42d0442-bbd5-4bc8-ae47-560d1496d0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758706945 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.1758706945
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.2314890855
Short name T675
Test name
Test status
Simulation time 15273443 ps
CPU time 0.91 seconds
Started Dec 24 01:42:43 PM PST 23
Finished Dec 24 01:43:03 PM PST 23
Peak memory 204848 kb
Host smart-ff20df55-621d-426a-a140-edf86b0af83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314890855 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.2314890855
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.2806267337
Short name T517
Test name
Test status
Simulation time 211985780 ps
CPU time 3.03 seconds
Started Dec 24 01:42:47 PM PST 23
Finished Dec 24 01:43:08 PM PST 23
Peak memory 205716 kb
Host smart-514e705a-cb5e-4f28-909c-a4b827767f84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806267337 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.2806267337
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/140.edn_genbits.3790382630
Short name T611
Test name
Test status
Simulation time 72289557 ps
CPU time 0.89 seconds
Started Dec 24 01:44:05 PM PST 23
Finished Dec 24 01:44:22 PM PST 23
Peak memory 204844 kb
Host smart-8b921240-d900-495d-8e0e-85d1ebdacbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790382630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.3790382630
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.2490112354
Short name T262
Test name
Test status
Simulation time 21943045 ps
CPU time 1.22 seconds
Started Dec 24 01:44:07 PM PST 23
Finished Dec 24 01:44:26 PM PST 23
Peak memory 205816 kb
Host smart-f735fb45-66c0-4d23-989c-fb63443a0b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490112354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.2490112354
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.1760832749
Short name T560
Test name
Test status
Simulation time 13310222 ps
CPU time 0.97 seconds
Started Dec 24 01:44:05 PM PST 23
Finished Dec 24 01:44:22 PM PST 23
Peak memory 205496 kb
Host smart-018e1b70-2668-4390-8f48-0fe640ba657b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760832749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.1760832749
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.1640999818
Short name T961
Test name
Test status
Simulation time 17114025 ps
CPU time 0.98 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:17 PM PST 23
Peak memory 205512 kb
Host smart-030cf5b2-4217-419e-8839-7bdf1fa5d386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640999818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.1640999818
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.4294281304
Short name T272
Test name
Test status
Simulation time 28517953 ps
CPU time 0.95 seconds
Started Dec 24 01:44:06 PM PST 23
Finished Dec 24 01:44:24 PM PST 23
Peak memory 205420 kb
Host smart-55c3a9db-832b-454f-9464-fa89ef470ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294281304 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.4294281304
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.3793099198
Short name T958
Test name
Test status
Simulation time 29466712 ps
CPU time 0.9 seconds
Started Dec 24 01:44:06 PM PST 23
Finished Dec 24 01:44:24 PM PST 23
Peak memory 204812 kb
Host smart-1783c424-24e6-450e-a188-12718b1b8249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793099198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.3793099198
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.4024456115
Short name T677
Test name
Test status
Simulation time 71808912 ps
CPU time 1.18 seconds
Started Dec 24 01:44:08 PM PST 23
Finished Dec 24 01:44:28 PM PST 23
Peak memory 213948 kb
Host smart-44694817-5fb5-4488-a151-67c9abed80d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024456115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.4024456115
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.2814910478
Short name T608
Test name
Test status
Simulation time 37942986 ps
CPU time 1.19 seconds
Started Dec 24 01:44:03 PM PST 23
Finished Dec 24 01:44:16 PM PST 23
Peak memory 214232 kb
Host smart-4fa84a67-f86d-4b27-95a7-8d2fbd4b8914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814910478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.2814910478
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.791609872
Short name T668
Test name
Test status
Simulation time 16948592 ps
CPU time 1.08 seconds
Started Dec 24 01:44:08 PM PST 23
Finished Dec 24 01:44:28 PM PST 23
Peak memory 205348 kb
Host smart-d9d27e6f-b847-409f-a0d6-3160284b1a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791609872 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.791609872
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.2600669126
Short name T742
Test name
Test status
Simulation time 19391447 ps
CPU time 0.98 seconds
Started Dec 24 01:42:47 PM PST 23
Finished Dec 24 01:43:06 PM PST 23
Peak memory 205624 kb
Host smart-64037da3-d079-433b-9b5a-620abe801f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600669126 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.2600669126
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.2327293439
Short name T665
Test name
Test status
Simulation time 45424923 ps
CPU time 0.98 seconds
Started Dec 24 01:42:52 PM PST 23
Finished Dec 24 01:43:15 PM PST 23
Peak memory 204472 kb
Host smart-f0a71abc-921d-448f-9e4e-21c8f65a8798
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327293439 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.2327293439
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.3185436228
Short name T123
Test name
Test status
Simulation time 22900707 ps
CPU time 0.85 seconds
Started Dec 24 01:42:48 PM PST 23
Finished Dec 24 01:43:09 PM PST 23
Peak memory 214280 kb
Host smart-6db62d4f-9985-4c79-99a0-97070e6492e4
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185436228 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.3185436228
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.3687751283
Short name T497
Test name
Test status
Simulation time 21596881 ps
CPU time 1.04 seconds
Started Dec 24 01:42:45 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 214556 kb
Host smart-85bd0fdb-ce6d-4808-b9d3-bf214db6c237
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687751283 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.3687751283
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.639848286
Short name T857
Test name
Test status
Simulation time 19061555 ps
CPU time 1.12 seconds
Started Dec 24 01:42:44 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 214140 kb
Host smart-394809df-7583-4420-bbff-f0c12f8923bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639848286 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.639848286
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.1630664941
Short name T633
Test name
Test status
Simulation time 16727538 ps
CPU time 1.05 seconds
Started Dec 24 01:42:45 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 214172 kb
Host smart-a7c9c8a4-3820-4cb7-a625-aa9f5cc7a7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630664941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.1630664941
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.1967894724
Short name T15
Test name
Test status
Simulation time 29455829 ps
CPU time 0.94 seconds
Started Dec 24 01:42:48 PM PST 23
Finished Dec 24 01:43:08 PM PST 23
Peak memory 221436 kb
Host smart-0ce1e56b-21a1-47bc-91dd-8324adbcde0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967894724 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.1967894724
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.2509576982
Short name T476
Test name
Test status
Simulation time 26098685 ps
CPU time 0.87 seconds
Started Dec 24 01:42:46 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 204696 kb
Host smart-d14b6b2d-e170-4e75-b8bd-5e86c7213211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509576982 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2509576982
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.2571712006
Short name T932
Test name
Test status
Simulation time 282155462 ps
CPU time 3.49 seconds
Started Dec 24 01:42:42 PM PST 23
Finished Dec 24 01:42:57 PM PST 23
Peak memory 205796 kb
Host smart-f886bbe6-9891-4111-9ad4-700ad29d54c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571712006 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.2571712006
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.1307506951
Short name T654
Test name
Test status
Simulation time 18264689264 ps
CPU time 453.09 seconds
Started Dec 24 01:42:49 PM PST 23
Finished Dec 24 01:50:45 PM PST 23
Peak memory 214876 kb
Host smart-0e58b0d5-21dd-4c6c-aa73-f09e228b5685
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307506951 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.1307506951
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.1404274346
Short name T656
Test name
Test status
Simulation time 190764579 ps
CPU time 3.25 seconds
Started Dec 24 01:44:09 PM PST 23
Finished Dec 24 01:44:32 PM PST 23
Peak memory 214136 kb
Host smart-2f3498e6-c8cf-4efb-9774-bb72d8cfab4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404274346 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.1404274346
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.3983369227
Short name T64
Test name
Test status
Simulation time 55543893 ps
CPU time 0.92 seconds
Started Dec 24 01:44:09 PM PST 23
Finished Dec 24 01:44:29 PM PST 23
Peak memory 205340 kb
Host smart-0c9fcf8c-69ad-4bfe-81db-732ab102eab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983369227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.3983369227
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.837475591
Short name T546
Test name
Test status
Simulation time 57334035 ps
CPU time 1 seconds
Started Dec 24 01:44:08 PM PST 23
Finished Dec 24 01:44:29 PM PST 23
Peak memory 213948 kb
Host smart-629b68f0-efc1-4d58-856f-1e6218f40151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837475591 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.837475591
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.2395352540
Short name T72
Test name
Test status
Simulation time 65998526 ps
CPU time 1.65 seconds
Started Dec 24 01:44:13 PM PST 23
Finished Dec 24 01:44:34 PM PST 23
Peak memory 214256 kb
Host smart-6bf96909-0616-4b21-b120-857b5057a5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395352540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.2395352540
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.1353830143
Short name T84
Test name
Test status
Simulation time 58866513 ps
CPU time 1.38 seconds
Started Dec 24 01:44:03 PM PST 23
Finished Dec 24 01:44:14 PM PST 23
Peak memory 214248 kb
Host smart-02da1791-00b4-47b1-a4bd-a48c0140d311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353830143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1353830143
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.1122452321
Short name T547
Test name
Test status
Simulation time 47643427 ps
CPU time 0.98 seconds
Started Dec 24 01:44:05 PM PST 23
Finished Dec 24 01:44:23 PM PST 23
Peak memory 205236 kb
Host smart-cc009f00-b39f-420c-bc64-f93181cd65f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122452321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.1122452321
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.937541829
Short name T500
Test name
Test status
Simulation time 42858692 ps
CPU time 1.38 seconds
Started Dec 24 01:44:03 PM PST 23
Finished Dec 24 01:44:15 PM PST 23
Peak memory 205380 kb
Host smart-5e16b0f2-8897-40e7-91c1-bfddb1d38d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937541829 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.937541829
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.3782944159
Short name T20
Test name
Test status
Simulation time 31509692 ps
CPU time 1 seconds
Started Dec 24 01:44:07 PM PST 23
Finished Dec 24 01:44:26 PM PST 23
Peak memory 205096 kb
Host smart-bd7d0f80-d433-49e8-a14c-57649849d520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782944159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.3782944159
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.3297694221
Short name T803
Test name
Test status
Simulation time 60184394 ps
CPU time 1 seconds
Started Dec 24 01:44:06 PM PST 23
Finished Dec 24 01:44:25 PM PST 23
Peak memory 205452 kb
Host smart-d33ebde1-0df7-4822-b7b9-269045e63f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297694221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.3297694221
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.1854204784
Short name T759
Test name
Test status
Simulation time 233108258 ps
CPU time 1.18 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:18 PM PST 23
Peak memory 214088 kb
Host smart-31b4a21c-6fa6-4369-8585-61f712e645ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854204784 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.1854204784
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.2200496722
Short name T16
Test name
Test status
Simulation time 53924302 ps
CPU time 0.91 seconds
Started Dec 24 01:42:47 PM PST 23
Finished Dec 24 01:43:06 PM PST 23
Peak memory 206000 kb
Host smart-6e9193ac-ed2d-49dd-b8d5-f02ddb6f741b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200496722 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.2200496722
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.3930352107
Short name T478
Test name
Test status
Simulation time 19477502 ps
CPU time 0.98 seconds
Started Dec 24 01:42:44 PM PST 23
Finished Dec 24 01:43:03 PM PST 23
Peak memory 204612 kb
Host smart-d92f683d-591b-43a3-a097-32731d452be8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930352107 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.3930352107
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.754757956
Short name T636
Test name
Test status
Simulation time 64983261 ps
CPU time 0.81 seconds
Started Dec 24 01:42:40 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 214228 kb
Host smart-e8596e87-b1b2-45b9-b520-568229168f67
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754757956 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.754757956
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_err.1556263789
Short name T133
Test name
Test status
Simulation time 19836739 ps
CPU time 1.03 seconds
Started Dec 24 01:42:45 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 215608 kb
Host smart-68dfaf3b-f1f1-42d1-9132-7b7c8edc00b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556263789 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.1556263789
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_intr.4232186723
Short name T512
Test name
Test status
Simulation time 23297133 ps
CPU time 0.99 seconds
Started Dec 24 01:42:47 PM PST 23
Finished Dec 24 01:43:07 PM PST 23
Peak memory 214076 kb
Host smart-be920e55-13f0-46da-af6f-bbf55145675a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232186723 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.4232186723
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.43170944
Short name T685
Test name
Test status
Simulation time 133905136 ps
CPU time 0.83 seconds
Started Dec 24 01:42:48 PM PST 23
Finished Dec 24 01:43:11 PM PST 23
Peak memory 204608 kb
Host smart-4a81153d-2460-495a-b441-68bde0223133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43170944 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.43170944
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.487222780
Short name T515
Test name
Test status
Simulation time 123024962 ps
CPU time 1.22 seconds
Started Dec 24 01:42:48 PM PST 23
Finished Dec 24 01:43:10 PM PST 23
Peak memory 205396 kb
Host smart-7a471292-5801-4fdb-b152-8ada45ba5344
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487222780 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.487222780
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.3498185061
Short name T490
Test name
Test status
Simulation time 31376302780 ps
CPU time 715.04 seconds
Started Dec 24 01:42:45 PM PST 23
Finished Dec 24 01:54:59 PM PST 23
Peak memory 214560 kb
Host smart-dbd3aadd-8e63-4fe0-be50-71a59136f6e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498185061 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.3498185061
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.3907024407
Short name T738
Test name
Test status
Simulation time 21791204 ps
CPU time 1.11 seconds
Started Dec 24 01:44:16 PM PST 23
Finished Dec 24 01:44:35 PM PST 23
Peak memory 214184 kb
Host smart-427befb5-54aa-4986-b1a5-909f99623d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907024407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.3907024407
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.1415768109
Short name T965
Test name
Test status
Simulation time 17298860 ps
CPU time 1 seconds
Started Dec 24 01:44:11 PM PST 23
Finished Dec 24 01:44:31 PM PST 23
Peak memory 205104 kb
Host smart-8b07ee74-52ac-402e-a032-6e1d54d86b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415768109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.1415768109
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.1330346869
Short name T302
Test name
Test status
Simulation time 60721309 ps
CPU time 0.93 seconds
Started Dec 24 01:44:02 PM PST 23
Finished Dec 24 01:44:10 PM PST 23
Peak memory 205060 kb
Host smart-f8b148fd-d0b9-42dc-a512-58411bbe32cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330346869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.1330346869
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.1603413215
Short name T681
Test name
Test status
Simulation time 132649139 ps
CPU time 1.47 seconds
Started Dec 24 01:44:02 PM PST 23
Finished Dec 24 01:44:10 PM PST 23
Peak memory 214096 kb
Host smart-88e18753-f37f-44f6-8a78-998d587e12c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603413215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.1603413215
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.2756394897
Short name T514
Test name
Test status
Simulation time 52738932 ps
CPU time 1.02 seconds
Started Dec 24 01:44:03 PM PST 23
Finished Dec 24 01:44:14 PM PST 23
Peak memory 205556 kb
Host smart-7b673c23-0feb-49d9-90a1-729678968a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756394897 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.2756394897
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.4114245739
Short name T301
Test name
Test status
Simulation time 104225588 ps
CPU time 1.63 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:19 PM PST 23
Peak memory 214272 kb
Host smart-6505ffd1-cab4-477d-9058-ed4089fce2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114245739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.4114245739
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.309577226
Short name T893
Test name
Test status
Simulation time 32364851 ps
CPU time 1.08 seconds
Started Dec 24 01:44:03 PM PST 23
Finished Dec 24 01:44:16 PM PST 23
Peak memory 205368 kb
Host smart-fb16f7b3-a9e4-4d68-bdf8-c3d4f2332a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309577226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.309577226
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.613189340
Short name T842
Test name
Test status
Simulation time 25272604 ps
CPU time 0.94 seconds
Started Dec 24 01:44:01 PM PST 23
Finished Dec 24 01:44:08 PM PST 23
Peak memory 205380 kb
Host smart-896c8e3e-2ff3-4fa6-9fa1-6a3f508421cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613189340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.613189340
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.2191919585
Short name T928
Test name
Test status
Simulation time 15412571 ps
CPU time 1.02 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:19 PM PST 23
Peak memory 205624 kb
Host smart-232db38c-fdd1-4200-bd3b-651a993982cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191919585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.2191919585
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.709244036
Short name T698
Test name
Test status
Simulation time 60170957 ps
CPU time 0.92 seconds
Started Dec 24 01:42:38 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 205112 kb
Host smart-c58fb5fc-f3c1-47e3-a44b-5a9b28bbe0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709244036 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.709244036
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.3374967936
Short name T670
Test name
Test status
Simulation time 15143468 ps
CPU time 0.86 seconds
Started Dec 24 01:42:41 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 204604 kb
Host smart-d1e6b864-86a8-4480-a69a-25b221336053
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374967936 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3374967936
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.2923684753
Short name T897
Test name
Test status
Simulation time 17835948 ps
CPU time 0.81 seconds
Started Dec 24 01:42:46 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 214348 kb
Host smart-68a3582c-0751-4696-ac12-ec14a565a0e5
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923684753 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.2923684753
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.2625523672
Short name T182
Test name
Test status
Simulation time 23269909 ps
CPU time 0.98 seconds
Started Dec 24 01:42:45 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 214444 kb
Host smart-195a5323-f8e3-4051-8b56-adf14853afb7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625523672 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.2625523672
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.67807967
Short name T214
Test name
Test status
Simulation time 22416013 ps
CPU time 0.99 seconds
Started Dec 24 01:42:37 PM PST 23
Finished Dec 24 01:42:44 PM PST 23
Peak memory 221780 kb
Host smart-1e17b0d7-31cc-4f3e-9a54-323c95664c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67807967 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.67807967
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.1805844393
Short name T830
Test name
Test status
Simulation time 36541349 ps
CPU time 1.03 seconds
Started Dec 24 01:42:39 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 205348 kb
Host smart-3c1a9c65-ee4a-41a4-a057-8cce89258abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805844393 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.1805844393
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.1572895314
Short name T875
Test name
Test status
Simulation time 42557295 ps
CPU time 0.86 seconds
Started Dec 24 01:42:40 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 214276 kb
Host smart-2c3befb5-7272-491e-bb7a-cf3c89e87dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572895314 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.1572895314
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.1057107968
Short name T917
Test name
Test status
Simulation time 36388410 ps
CPU time 0.82 seconds
Started Dec 24 01:42:38 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 204628 kb
Host smart-c0655a01-4714-42f3-a86e-c7659793a303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057107968 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.1057107968
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.1904168067
Short name T664
Test name
Test status
Simulation time 127118381 ps
CPU time 1.82 seconds
Started Dec 24 01:42:47 PM PST 23
Finished Dec 24 01:43:07 PM PST 23
Peak memory 205616 kb
Host smart-6ad3b664-716b-461f-bf93-472233e7f5d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904168067 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1904168067
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.18858810
Short name T579
Test name
Test status
Simulation time 92480850435 ps
CPU time 1114.14 seconds
Started Dec 24 01:42:40 PM PST 23
Finished Dec 24 02:01:26 PM PST 23
Peak memory 216480 kb
Host smart-c39910fb-4d60-4acf-9e31-f966aabee34e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18858810 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.18858810
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.3337189757
Short name T919
Test name
Test status
Simulation time 23295793 ps
CPU time 0.9 seconds
Started Dec 24 01:44:03 PM PST 23
Finished Dec 24 01:44:15 PM PST 23
Peak memory 205024 kb
Host smart-79d76934-6a95-4dbd-bd38-545a8d3a0d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337189757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.3337189757
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.2532911896
Short name T303
Test name
Test status
Simulation time 28157437 ps
CPU time 0.97 seconds
Started Dec 24 01:44:03 PM PST 23
Finished Dec 24 01:44:13 PM PST 23
Peak memory 204688 kb
Host smart-4cab63f3-f187-4fd2-9a8d-044903aad294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532911896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.2532911896
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.436121785
Short name T922
Test name
Test status
Simulation time 59627696 ps
CPU time 0.99 seconds
Started Dec 24 01:44:03 PM PST 23
Finished Dec 24 01:44:12 PM PST 23
Peak memory 205368 kb
Host smart-0707db57-c117-4aeb-b6c6-104f5411cf6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436121785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.436121785
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.3483406409
Short name T896
Test name
Test status
Simulation time 56952018 ps
CPU time 0.94 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:18 PM PST 23
Peak memory 205404 kb
Host smart-25038e2f-19b8-4f5d-ba3c-0d8eebd14dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483406409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.3483406409
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.1831990337
Short name T525
Test name
Test status
Simulation time 73989957 ps
CPU time 0.96 seconds
Started Dec 24 01:44:05 PM PST 23
Finished Dec 24 01:44:22 PM PST 23
Peak memory 204932 kb
Host smart-41b3b6cc-03ea-4698-9f64-79201b4e653b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831990337 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.1831990337
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.219799687
Short name T347
Test name
Test status
Simulation time 64441351 ps
CPU time 0.9 seconds
Started Dec 24 01:44:05 PM PST 23
Finished Dec 24 01:44:20 PM PST 23
Peak memory 205008 kb
Host smart-75e9e856-1e39-4f47-a625-c03ab2b4ed43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219799687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.219799687
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.817268091
Short name T676
Test name
Test status
Simulation time 34735202 ps
CPU time 1.14 seconds
Started Dec 24 01:44:01 PM PST 23
Finished Dec 24 01:44:08 PM PST 23
Peak memory 205200 kb
Host smart-5439137c-e7a4-4f51-8494-2bb53a6e9ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817268091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.817268091
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.207802954
Short name T587
Test name
Test status
Simulation time 35627072 ps
CPU time 0.98 seconds
Started Dec 24 01:42:38 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 205892 kb
Host smart-3f30120c-7e4f-4731-80a5-3cb3264b5be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207802954 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.207802954
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.1106128516
Short name T553
Test name
Test status
Simulation time 153539879 ps
CPU time 0.8 seconds
Started Dec 24 01:42:45 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 204296 kb
Host smart-5a286d72-39b4-49f9-9822-f4749e3e2948
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106128516 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.1106128516
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.1574334140
Short name T784
Test name
Test status
Simulation time 12286556 ps
CPU time 0.86 seconds
Started Dec 24 01:42:40 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 214520 kb
Host smart-dced02ce-cbf6-41a6-b13f-3d08322b8dd0
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574334140 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.1574334140
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.4041996439
Short name T871
Test name
Test status
Simulation time 24804191 ps
CPU time 0.96 seconds
Started Dec 24 01:42:44 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 214564 kb
Host smart-e6052db3-2607-44d1-a1b2-80604aeafe8b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041996439 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.4041996439
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.1660041027
Short name T531
Test name
Test status
Simulation time 30659571 ps
CPU time 0.88 seconds
Started Dec 24 01:42:40 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 215812 kb
Host smart-3486209f-9aa6-4560-a2b3-5955b5406f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660041027 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.1660041027
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.3304743148
Short name T264
Test name
Test status
Simulation time 56442471 ps
CPU time 1.09 seconds
Started Dec 24 01:42:44 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 205432 kb
Host smart-029db28e-603f-4aff-b1ea-7c3c3dbad3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304743148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.3304743148
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_smoke.4012836504
Short name T931
Test name
Test status
Simulation time 30049664 ps
CPU time 0.88 seconds
Started Dec 24 01:42:45 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 204536 kb
Host smart-e04352fb-f088-48e3-848e-96b81431c227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012836504 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.4012836504
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.1825953747
Short name T944
Test name
Test status
Simulation time 209218834 ps
CPU time 3.06 seconds
Started Dec 24 01:42:38 PM PST 23
Finished Dec 24 01:42:55 PM PST 23
Peak memory 205704 kb
Host smart-dd037dc7-8460-4639-a9b8-c5fe5986b6c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825953747 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1825953747
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.3772695155
Short name T96
Test name
Test status
Simulation time 371848673747 ps
CPU time 2512.82 seconds
Started Dec 24 01:42:38 PM PST 23
Finished Dec 24 02:24:40 PM PST 23
Peak memory 222872 kb
Host smart-9f9c6d4f-fc24-4b46-8842-b838a57e724e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772695155 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.3772695155
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.200052141
Short name T794
Test name
Test status
Simulation time 31605996 ps
CPU time 0.95 seconds
Started Dec 24 01:44:06 PM PST 23
Finished Dec 24 01:44:24 PM PST 23
Peak memory 205236 kb
Host smart-6dab109f-a883-48de-86d4-6660a1821a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200052141 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.200052141
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.1540737362
Short name T734
Test name
Test status
Simulation time 269227291 ps
CPU time 1.33 seconds
Started Dec 24 01:44:10 PM PST 23
Finished Dec 24 01:44:31 PM PST 23
Peak memory 214056 kb
Host smart-01eb716d-b0f8-4130-95c4-24a65a478c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540737362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.1540737362
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.115952896
Short name T627
Test name
Test status
Simulation time 16730930 ps
CPU time 1.02 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:19 PM PST 23
Peak memory 204876 kb
Host smart-e5217c3d-a059-4bfe-ac90-8bb519eb8399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115952896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.115952896
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.2085968859
Short name T308
Test name
Test status
Simulation time 31942966 ps
CPU time 1.43 seconds
Started Dec 24 01:44:05 PM PST 23
Finished Dec 24 01:44:20 PM PST 23
Peak memory 214108 kb
Host smart-fafd5c0c-4f96-4b61-93cd-af0000ebfbe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085968859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.2085968859
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.1094295114
Short name T285
Test name
Test status
Simulation time 16315835 ps
CPU time 0.97 seconds
Started Dec 24 01:44:06 PM PST 23
Finished Dec 24 01:44:24 PM PST 23
Peak memory 205220 kb
Host smart-30aea597-1b0c-4f5c-9471-0762651a7dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094295114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.1094295114
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.1665286946
Short name T655
Test name
Test status
Simulation time 175237996 ps
CPU time 1 seconds
Started Dec 24 01:44:06 PM PST 23
Finished Dec 24 01:44:25 PM PST 23
Peak memory 205156 kb
Host smart-e7666790-a8f2-4599-91c4-f575aeac9cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665286946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.1665286946
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.1509887455
Short name T10
Test name
Test status
Simulation time 72685044 ps
CPU time 1.12 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:19 PM PST 23
Peak memory 214060 kb
Host smart-ce13f5c0-575a-495f-826a-75089b7771b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509887455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.1509887455
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.4548499
Short name T332
Test name
Test status
Simulation time 18579245 ps
CPU time 1.05 seconds
Started Dec 24 01:44:06 PM PST 23
Finished Dec 24 01:44:24 PM PST 23
Peak memory 205416 kb
Host smart-833a04e7-11c0-463e-9e9e-a672021a2e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4548499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.4548499
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.2616509523
Short name T662
Test name
Test status
Simulation time 54788407 ps
CPU time 1.08 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:19 PM PST 23
Peak memory 205456 kb
Host smart-5afceb86-95bc-45f7-9282-3b106d5bad04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616509523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.2616509523
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.3962563906
Short name T460
Test name
Test status
Simulation time 22521195 ps
CPU time 0.91 seconds
Started Dec 24 01:44:07 PM PST 23
Finished Dec 24 01:44:25 PM PST 23
Peak memory 205584 kb
Host smart-574219ed-5b01-4a64-a16b-08e7bbd14100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962563906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.3962563906
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.1653155428
Short name T863
Test name
Test status
Simulation time 20751875 ps
CPU time 0.99 seconds
Started Dec 24 01:42:49 PM PST 23
Finished Dec 24 01:43:13 PM PST 23
Peak memory 206056 kb
Host smart-19ace736-a642-4003-bdfc-203d79cf1bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653155428 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.1653155428
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.687099455
Short name T486
Test name
Test status
Simulation time 40844757 ps
CPU time 0.86 seconds
Started Dec 24 01:42:47 PM PST 23
Finished Dec 24 01:43:06 PM PST 23
Peak memory 204948 kb
Host smart-d6f9da96-0240-403d-b6ce-3c6c92da2f66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687099455 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.687099455
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.1942277239
Short name T149
Test name
Test status
Simulation time 38744125 ps
CPU time 0.79 seconds
Started Dec 24 01:42:40 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 214148 kb
Host smart-a239786f-ac30-4b0b-9a6a-f4a4f5fadb64
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942277239 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.1942277239
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.937087964
Short name T642
Test name
Test status
Simulation time 47462295 ps
CPU time 0.94 seconds
Started Dec 24 01:42:41 PM PST 23
Finished Dec 24 01:42:54 PM PST 23
Peak memory 214480 kb
Host smart-1239c018-0144-477c-864a-dbae9fd43098
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937087964 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_di
sable_auto_req_mode.937087964
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.1792474943
Short name T610
Test name
Test status
Simulation time 21473464 ps
CPU time 1.04 seconds
Started Dec 24 01:42:40 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 215764 kb
Host smart-e11bb803-0387-49c4-a491-0abdf0310bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792474943 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.1792474943
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.3467642909
Short name T578
Test name
Test status
Simulation time 20585894 ps
CPU time 0.97 seconds
Started Dec 24 01:42:45 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 205392 kb
Host smart-f81ed07d-fc46-48a1-a318-98239f51fb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467642909 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.3467642909
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.1323409233
Short name T786
Test name
Test status
Simulation time 31415659 ps
CPU time 0.9 seconds
Started Dec 24 01:42:46 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 214340 kb
Host smart-53ae66d2-4ad5-4c89-be68-793e33219eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323409233 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.1323409233
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.573656851
Short name T502
Test name
Test status
Simulation time 23549194 ps
CPU time 0.85 seconds
Started Dec 24 01:42:47 PM PST 23
Finished Dec 24 01:43:06 PM PST 23
Peak memory 204488 kb
Host smart-e74b92be-4da7-45c8-8dff-afafe02e350b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573656851 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.573656851
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.172555029
Short name T291
Test name
Test status
Simulation time 26067501 ps
CPU time 1.21 seconds
Started Dec 24 01:42:46 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 205060 kb
Host smart-555563c2-865c-448f-ac0d-d71565b40243
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172555029 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.172555029
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.1103354652
Short name T586
Test name
Test status
Simulation time 392809683103 ps
CPU time 2620.4 seconds
Started Dec 24 01:42:38 PM PST 23
Finished Dec 24 02:26:33 PM PST 23
Peak memory 226608 kb
Host smart-674c46ac-e163-4397-b764-b96037d8f181
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103354652 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.1103354652
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.1735081692
Short name T59
Test name
Test status
Simulation time 83120280 ps
CPU time 0.91 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:18 PM PST 23
Peak memory 205564 kb
Host smart-811d0609-ea8b-40ae-9da1-abfe2f1ac9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735081692 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.1735081692
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.2408833672
Short name T628
Test name
Test status
Simulation time 27800322 ps
CPU time 0.97 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:19 PM PST 23
Peak memory 205200 kb
Host smart-9783c09b-a038-4f3b-a93a-29460cbb4625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408833672 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2408833672
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.4054806174
Short name T723
Test name
Test status
Simulation time 207725492 ps
CPU time 0.94 seconds
Started Dec 24 01:44:08 PM PST 23
Finished Dec 24 01:44:28 PM PST 23
Peak memory 205296 kb
Host smart-024e3a09-ba47-4b2b-bbe9-7d62974dbbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054806174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.4054806174
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.3800312390
Short name T83
Test name
Test status
Simulation time 15737661 ps
CPU time 1.04 seconds
Started Dec 24 01:44:07 PM PST 23
Finished Dec 24 01:44:27 PM PST 23
Peak memory 205604 kb
Host smart-cd79f704-9aaf-492d-ab17-6c58f07c9499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800312390 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.3800312390
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.3912007466
Short name T268
Test name
Test status
Simulation time 215938787 ps
CPU time 2.82 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:20 PM PST 23
Peak memory 214168 kb
Host smart-41867c2d-f464-4422-9dc3-56c1d282a785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912007466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.3912007466
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.2802209349
Short name T599
Test name
Test status
Simulation time 19328827 ps
CPU time 0.95 seconds
Started Dec 24 01:44:05 PM PST 23
Finished Dec 24 01:44:23 PM PST 23
Peak memory 205468 kb
Host smart-d66ef18e-1121-4939-abfa-b65ca2758cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802209349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.2802209349
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.1851218141
Short name T588
Test name
Test status
Simulation time 38474959 ps
CPU time 1.06 seconds
Started Dec 24 01:44:01 PM PST 23
Finished Dec 24 01:44:08 PM PST 23
Peak memory 205464 kb
Host smart-27e0d384-b2ce-4300-9949-d324ae75161a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851218141 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.1851218141
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.2040699856
Short name T527
Test name
Test status
Simulation time 35566794 ps
CPU time 0.99 seconds
Started Dec 24 01:44:03 PM PST 23
Finished Dec 24 01:44:13 PM PST 23
Peak memory 205544 kb
Host smart-a0a00029-92e4-45a3-acf9-fe3d98d6d294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040699856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.2040699856
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.2242992634
Short name T530
Test name
Test status
Simulation time 35493660 ps
CPU time 0.84 seconds
Started Dec 24 01:44:02 PM PST 23
Finished Dec 24 01:44:09 PM PST 23
Peak memory 204900 kb
Host smart-0bbd542b-f45d-4662-8c3e-cf56c333b11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242992634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.2242992634
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.4231824075
Short name T278
Test name
Test status
Simulation time 124396091 ps
CPU time 1.13 seconds
Started Dec 24 01:44:07 PM PST 23
Finished Dec 24 01:44:27 PM PST 23
Peak memory 214144 kb
Host smart-90fadff8-96a9-4038-97ae-3f0342884095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231824075 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.4231824075
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.2391197282
Short name T17
Test name
Test status
Simulation time 37341031 ps
CPU time 0.98 seconds
Started Dec 24 01:42:42 PM PST 23
Finished Dec 24 01:42:58 PM PST 23
Peak memory 205188 kb
Host smart-ce0e76fc-2c51-47ac-94ac-c96b64bdc052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391197282 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.2391197282
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.796403270
Short name T464
Test name
Test status
Simulation time 237895894 ps
CPU time 0.9 seconds
Started Dec 24 01:42:17 PM PST 23
Finished Dec 24 01:42:20 PM PST 23
Peak memory 205600 kb
Host smart-e1156a9c-9a97-428b-bb5b-08e0dd813481
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796403270 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.796403270
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.1916598163
Short name T929
Test name
Test status
Simulation time 17152206 ps
CPU time 0.99 seconds
Started Dec 24 01:42:02 PM PST 23
Finished Dec 24 01:42:07 PM PST 23
Peak memory 214212 kb
Host smart-5e068a92-b920-4a15-b730-e1f738890cfc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916598163 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.1916598163
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.2847022166
Short name T206
Test name
Test status
Simulation time 31658743 ps
CPU time 0.87 seconds
Started Dec 24 01:42:40 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 215472 kb
Host smart-63ca6763-bcf0-4b20-8d76-404340dbac03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847022166 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.2847022166
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.977065059
Short name T916
Test name
Test status
Simulation time 78857428 ps
CPU time 1.13 seconds
Started Dec 24 01:42:38 PM PST 23
Finished Dec 24 01:42:50 PM PST 23
Peak memory 214228 kb
Host smart-e108eea6-666a-499e-84b0-2b821f9409d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977065059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.977065059
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.2146382426
Short name T540
Test name
Test status
Simulation time 27321364 ps
CPU time 0.99 seconds
Started Dec 24 01:41:52 PM PST 23
Finished Dec 24 01:41:57 PM PST 23
Peak memory 221764 kb
Host smart-a0a67756-9bdf-4e9e-8c78-9667684a0b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146382426 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.2146382426
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_sec_cm.1456491797
Short name T45
Test name
Test status
Simulation time 650077166 ps
CPU time 3.31 seconds
Started Dec 24 01:42:44 PM PST 23
Finished Dec 24 01:43:07 PM PST 23
Peak memory 234004 kb
Host smart-ef7e1902-c7d4-41c7-9bc6-614a593db7e7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456491797 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.1456491797
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.121148912
Short name T569
Test name
Test status
Simulation time 36938585 ps
CPU time 0.82 seconds
Started Dec 24 01:41:54 PM PST 23
Finished Dec 24 01:42:01 PM PST 23
Peak memory 204324 kb
Host smart-0a61f67e-80c4-4ee3-9486-e3da395a8b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121148912 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.121148912
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.2062205736
Short name T792
Test name
Test status
Simulation time 140926283 ps
CPU time 2.08 seconds
Started Dec 24 01:41:57 PM PST 23
Finished Dec 24 01:42:05 PM PST 23
Peak memory 205912 kb
Host smart-6a4fd95c-8f9b-4475-828d-4f4f4498e892
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062205736 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.2062205736
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.1479386557
Short name T652
Test name
Test status
Simulation time 330607133960 ps
CPU time 2059.06 seconds
Started Dec 24 01:42:39 PM PST 23
Finished Dec 24 02:17:11 PM PST 23
Peak memory 223296 kb
Host smart-6b00837b-8c79-4c43-abb3-6737a09fa2e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479386557 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.1479386557
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert_test.1137864361
Short name T473
Test name
Test status
Simulation time 43474250 ps
CPU time 0.86 seconds
Started Dec 24 01:42:47 PM PST 23
Finished Dec 24 01:43:06 PM PST 23
Peak memory 204844 kb
Host smart-4545ee80-df16-466f-a059-53c3a24e33c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137864361 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.1137864361
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.2630994120
Short name T142
Test name
Test status
Simulation time 13678397 ps
CPU time 0.91 seconds
Started Dec 24 01:42:47 PM PST 23
Finished Dec 24 01:43:08 PM PST 23
Peak memory 214580 kb
Host smart-a42475a1-ce23-471a-b41f-b66947d7b1f8
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630994120 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.2630994120
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.3079708747
Short name T141
Test name
Test status
Simulation time 45007776 ps
CPU time 1.01 seconds
Started Dec 24 01:43:02 PM PST 23
Finished Dec 24 01:43:20 PM PST 23
Peak memory 205760 kb
Host smart-d127b4d7-dd80-4bb0-bedd-ad5181789e16
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079708747 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.3079708747
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.1500576008
Short name T740
Test name
Test status
Simulation time 19266297 ps
CPU time 1.17 seconds
Started Dec 24 01:42:52 PM PST 23
Finished Dec 24 01:43:15 PM PST 23
Peak memory 221676 kb
Host smart-0c00b4ea-8c82-4654-a8aa-d0e58a6ba0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500576008 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.1500576008
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.57907339
Short name T70
Test name
Test status
Simulation time 18355196 ps
CPU time 1.15 seconds
Started Dec 24 01:42:46 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 205500 kb
Host smart-bf8eaeb2-72c6-4e1e-95df-b37af12d4ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57907339 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.57907339
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.2781375275
Short name T21
Test name
Test status
Simulation time 26009718 ps
CPU time 0.89 seconds
Started Dec 24 01:42:47 PM PST 23
Finished Dec 24 01:43:07 PM PST 23
Peak memory 214504 kb
Host smart-32079751-dd25-4772-8c74-6a8627625f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781375275 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.2781375275
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.2752983878
Short name T453
Test name
Test status
Simulation time 14179137 ps
CPU time 0.93 seconds
Started Dec 24 01:42:48 PM PST 23
Finished Dec 24 01:43:09 PM PST 23
Peak memory 204860 kb
Host smart-2449037f-3632-4816-9de7-c0bb71b2eb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752983878 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.2752983878
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.3371459742
Short name T481
Test name
Test status
Simulation time 46651662 ps
CPU time 1.19 seconds
Started Dec 24 01:42:48 PM PST 23
Finished Dec 24 01:43:12 PM PST 23
Peak memory 205336 kb
Host smart-8bce4335-a66c-4781-88fd-3fa6f6ac8638
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371459742 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.3371459742
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.3887893219
Short name T631
Test name
Test status
Simulation time 24444814150 ps
CPU time 603.29 seconds
Started Dec 24 01:42:46 PM PST 23
Finished Dec 24 01:53:08 PM PST 23
Peak memory 215512 kb
Host smart-eda6e5dc-3e12-4746-be9d-0f8075c7208c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887893219 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.3887893219
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.3609442379
Short name T900
Test name
Test status
Simulation time 17873433 ps
CPU time 0.99 seconds
Started Dec 24 01:44:05 PM PST 23
Finished Dec 24 01:44:20 PM PST 23
Peak memory 205016 kb
Host smart-0a68a1c9-9636-463b-b387-5c99556425a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609442379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.3609442379
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.1539391637
Short name T915
Test name
Test status
Simulation time 64369842 ps
CPU time 0.96 seconds
Started Dec 24 01:44:03 PM PST 23
Finished Dec 24 01:44:15 PM PST 23
Peak memory 205220 kb
Host smart-c4fe7362-31af-41a2-a6bc-4a21ba1ad5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539391637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.1539391637
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.483515921
Short name T559
Test name
Test status
Simulation time 14564230 ps
CPU time 0.99 seconds
Started Dec 24 01:44:02 PM PST 23
Finished Dec 24 01:44:12 PM PST 23
Peak memory 204944 kb
Host smart-32b88015-b07b-4fde-ac36-f03837a6910d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483515921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.483515921
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.2021775135
Short name T267
Test name
Test status
Simulation time 120127344 ps
CPU time 2.75 seconds
Started Dec 24 01:44:05 PM PST 23
Finished Dec 24 01:44:24 PM PST 23
Peak memory 214012 kb
Host smart-2feb99bc-7e59-4c94-9b88-603065da4079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021775135 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2021775135
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.1198957628
Short name T680
Test name
Test status
Simulation time 51750919 ps
CPU time 0.87 seconds
Started Dec 24 01:44:06 PM PST 23
Finished Dec 24 01:44:23 PM PST 23
Peak memory 204856 kb
Host smart-0fd3ed0c-117d-4353-8d1f-38e498efbabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198957628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.1198957628
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.3892656583
Short name T624
Test name
Test status
Simulation time 14837187 ps
CPU time 0.95 seconds
Started Dec 24 01:44:05 PM PST 23
Finished Dec 24 01:44:21 PM PST 23
Peak memory 205072 kb
Host smart-fb715967-e65c-4b64-8c9c-e384533ce902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892656583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3892656583
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.4156887878
Short name T951
Test name
Test status
Simulation time 71840745 ps
CPU time 1.05 seconds
Started Dec 24 01:44:02 PM PST 23
Finished Dec 24 01:44:10 PM PST 23
Peak memory 205376 kb
Host smart-1a4df406-2cdd-455f-ad5f-de2e1402fb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156887878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.4156887878
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.1797710085
Short name T507
Test name
Test status
Simulation time 155268240 ps
CPU time 1.15 seconds
Started Dec 24 01:44:02 PM PST 23
Finished Dec 24 01:44:10 PM PST 23
Peak memory 205492 kb
Host smart-37b682b6-4f9f-4180-8a4f-d6c161519d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797710085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.1797710085
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.4198237396
Short name T590
Test name
Test status
Simulation time 23786165 ps
CPU time 0.98 seconds
Started Dec 24 01:44:02 PM PST 23
Finished Dec 24 01:44:10 PM PST 23
Peak memory 204936 kb
Host smart-bfca2f42-5008-421d-bd5a-3356d9536856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198237396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.4198237396
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.1843861097
Short name T702
Test name
Test status
Simulation time 15297126 ps
CPU time 0.91 seconds
Started Dec 24 01:44:02 PM PST 23
Finished Dec 24 01:44:10 PM PST 23
Peak memory 204848 kb
Host smart-b39a1daa-b821-4275-97cc-f743c0dac86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843861097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.1843861097
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.3350570511
Short name T886
Test name
Test status
Simulation time 41418111 ps
CPU time 0.96 seconds
Started Dec 24 01:42:42 PM PST 23
Finished Dec 24 01:42:56 PM PST 23
Peak memory 205892 kb
Host smart-afe0e77d-18e2-4fa8-a909-231a9fec516e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350570511 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3350570511
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.3330802430
Short name T602
Test name
Test status
Simulation time 40067287 ps
CPU time 1.04 seconds
Started Dec 24 01:42:48 PM PST 23
Finished Dec 24 01:43:10 PM PST 23
Peak memory 205516 kb
Host smart-871541e6-1a7f-4348-8ff6-794324a62bc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330802430 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.3330802430
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.1870010601
Short name T216
Test name
Test status
Simulation time 11322446 ps
CPU time 0.89 seconds
Started Dec 24 01:42:45 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 214252 kb
Host smart-3f369425-3471-4d06-826a-407b84519ca3
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870010601 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.1870010601
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.2687723635
Short name T840
Test name
Test status
Simulation time 26439387 ps
CPU time 1.01 seconds
Started Dec 24 01:42:46 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 214352 kb
Host smart-382a4baf-6b8d-4ffd-a95c-69c82359e807
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687723635 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.2687723635
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.4150981891
Short name T198
Test name
Test status
Simulation time 24559638 ps
CPU time 1.06 seconds
Started Dec 24 01:42:45 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 228476 kb
Host smart-bdd12f99-0719-48bf-9c17-687088dc93b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150981891 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.4150981891
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.1944355890
Short name T516
Test name
Test status
Simulation time 131593130 ps
CPU time 1.9 seconds
Started Dec 24 01:42:45 PM PST 23
Finished Dec 24 01:43:06 PM PST 23
Peak memory 214172 kb
Host smart-e6acc046-678f-4cd5-a390-27eaf870f0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944355890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.1944355890
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.3874219494
Short name T94
Test name
Test status
Simulation time 24743948 ps
CPU time 0.91 seconds
Started Dec 24 01:42:43 PM PST 23
Finished Dec 24 01:43:01 PM PST 23
Peak memory 214608 kb
Host smart-25dedf79-c292-4769-8f67-50755ea8eaf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874219494 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.3874219494
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.3648318796
Short name T459
Test name
Test status
Simulation time 55735843 ps
CPU time 0.83 seconds
Started Dec 24 01:42:51 PM PST 23
Finished Dec 24 01:43:15 PM PST 23
Peak memory 204404 kb
Host smart-2334fb9f-e39d-480c-8f08-2fcee3d012ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648318796 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.3648318796
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.2603956955
Short name T645
Test name
Test status
Simulation time 301119208 ps
CPU time 2.06 seconds
Started Dec 24 01:42:49 PM PST 23
Finished Dec 24 01:43:14 PM PST 23
Peak memory 205952 kb
Host smart-bb0cfd9a-f2e7-4db6-800c-52314dc04959
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603956955 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.2603956955
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.2463695624
Short name T778
Test name
Test status
Simulation time 43720210938 ps
CPU time 259.79 seconds
Started Dec 24 01:42:46 PM PST 23
Finished Dec 24 01:47:24 PM PST 23
Peak memory 215260 kb
Host smart-3c1c4e27-a6d2-4f39-ad7e-5f9cf6776a06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463695624 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.2463695624
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.429595922
Short name T619
Test name
Test status
Simulation time 33807586 ps
CPU time 1.18 seconds
Started Dec 24 01:44:06 PM PST 23
Finished Dec 24 01:44:25 PM PST 23
Peak memory 205228 kb
Host smart-5d4a12ab-41f9-4855-bf5f-ebe785894581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429595922 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.429595922
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.3054226966
Short name T703
Test name
Test status
Simulation time 65479215 ps
CPU time 1.02 seconds
Started Dec 24 01:44:03 PM PST 23
Finished Dec 24 01:44:15 PM PST 23
Peak memory 214188 kb
Host smart-491b5b2a-9025-4859-aca7-de2217b88c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054226966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.3054226966
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.1684470314
Short name T283
Test name
Test status
Simulation time 57914485 ps
CPU time 1.03 seconds
Started Dec 24 01:44:03 PM PST 23
Finished Dec 24 01:44:15 PM PST 23
Peak memory 214164 kb
Host smart-3ac8f104-33a4-4b22-b0c0-050f5d568f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684470314 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.1684470314
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.2579148162
Short name T650
Test name
Test status
Simulation time 16331810 ps
CPU time 0.92 seconds
Started Dec 24 01:44:01 PM PST 23
Finished Dec 24 01:44:08 PM PST 23
Peak memory 204872 kb
Host smart-80492a68-cfc9-471f-9e3d-53173fb60288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579148162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.2579148162
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.1387495046
Short name T346
Test name
Test status
Simulation time 17152931 ps
CPU time 1.05 seconds
Started Dec 24 01:44:02 PM PST 23
Finished Dec 24 01:44:10 PM PST 23
Peak memory 205048 kb
Host smart-10d4763d-4782-440d-9a15-7c3558952f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387495046 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.1387495046
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.973840454
Short name T644
Test name
Test status
Simulation time 32759735 ps
CPU time 1.67 seconds
Started Dec 24 01:44:01 PM PST 23
Finished Dec 24 01:44:10 PM PST 23
Peak memory 214180 kb
Host smart-e83f1fa6-1266-4655-9aaf-721f9168de39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973840454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.973840454
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.861109278
Short name T282
Test name
Test status
Simulation time 118700213 ps
CPU time 2.7 seconds
Started Dec 24 01:44:01 PM PST 23
Finished Dec 24 01:44:11 PM PST 23
Peak memory 214136 kb
Host smart-9fced7a9-3d0d-44ba-88b3-20b24664cc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861109278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.861109278
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.4152571084
Short name T467
Test name
Test status
Simulation time 17568099 ps
CPU time 0.96 seconds
Started Dec 24 01:44:02 PM PST 23
Finished Dec 24 01:44:10 PM PST 23
Peak memory 204800 kb
Host smart-c3cf764b-02ec-4479-a99e-9534f9b99732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152571084 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.4152571084
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.87221359
Short name T29
Test name
Test status
Simulation time 80316131 ps
CPU time 1.3 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:18 PM PST 23
Peak memory 205560 kb
Host smart-a18c5cc8-28ea-4353-a401-74e3545061bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87221359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.87221359
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.650237293
Short name T322
Test name
Test status
Simulation time 35479983 ps
CPU time 0.95 seconds
Started Dec 24 01:42:43 PM PST 23
Finished Dec 24 01:43:01 PM PST 23
Peak memory 205220 kb
Host smart-ba896e1b-f032-4146-b0f0-1405361d138d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650237293 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.650237293
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.49237938
Short name T689
Test name
Test status
Simulation time 15577768 ps
CPU time 0.78 seconds
Started Dec 24 01:42:48 PM PST 23
Finished Dec 24 01:43:10 PM PST 23
Peak memory 204256 kb
Host smart-62ca93b8-f275-49aa-912f-142479fbcda0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49237938 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.49237938
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.921705091
Short name T77
Test name
Test status
Simulation time 59978529 ps
CPU time 0.86 seconds
Started Dec 24 01:42:44 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 214324 kb
Host smart-426b88d2-46e8-4e8e-9786-2b3561b6588f
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921705091 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.921705091
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.3918297827
Short name T752
Test name
Test status
Simulation time 118110587 ps
CPU time 1.19 seconds
Started Dec 24 01:42:51 PM PST 23
Finished Dec 24 01:43:15 PM PST 23
Peak memory 214544 kb
Host smart-c9e52cc5-a117-417e-97b2-783d7b2d77e1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918297827 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.3918297827
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.2175460153
Short name T110
Test name
Test status
Simulation time 18897466 ps
CPU time 1.03 seconds
Started Dec 24 01:42:46 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 214552 kb
Host smart-265e0887-a2fa-4644-8297-001d5f034b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175460153 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.2175460153
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.1211077555
Short name T344
Test name
Test status
Simulation time 18843814 ps
CPU time 0.98 seconds
Started Dec 24 01:43:02 PM PST 23
Finished Dec 24 01:43:20 PM PST 23
Peak memory 205112 kb
Host smart-89d3feaf-e3dc-4fce-bd38-65d97e8acd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211077555 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.1211077555
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.4119641036
Short name T741
Test name
Test status
Simulation time 47788553 ps
CPU time 0.94 seconds
Started Dec 24 01:42:49 PM PST 23
Finished Dec 24 01:43:13 PM PST 23
Peak memory 221360 kb
Host smart-27e66916-3d78-433c-b972-51a0c1748f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119641036 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.4119641036
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.1956951306
Short name T847
Test name
Test status
Simulation time 34211207 ps
CPU time 0.86 seconds
Started Dec 24 01:43:02 PM PST 23
Finished Dec 24 01:43:20 PM PST 23
Peak memory 204180 kb
Host smart-3de3e4b6-371a-4d48-812d-1612dd8db426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956951306 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.1956951306
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.4008453173
Short name T265
Test name
Test status
Simulation time 289562218 ps
CPU time 1.92 seconds
Started Dec 24 01:42:44 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 205716 kb
Host smart-a323f3b2-68cc-48d5-adda-2a16742744b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008453173 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.4008453173
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.1397204338
Short name T699
Test name
Test status
Simulation time 377399993949 ps
CPU time 1988.99 seconds
Started Dec 24 01:42:45 PM PST 23
Finished Dec 24 02:16:13 PM PST 23
Peak memory 223112 kb
Host smart-f32d7315-86d9-405f-bebe-5ea432f2a288
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397204338 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.1397204338
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.684456892
Short name T582
Test name
Test status
Simulation time 18328126 ps
CPU time 0.97 seconds
Started Dec 24 01:44:02 PM PST 23
Finished Dec 24 01:44:09 PM PST 23
Peak memory 205356 kb
Host smart-a618eabd-b6b8-4f9b-aa72-60446fbc98bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684456892 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.684456892
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.4034613607
Short name T618
Test name
Test status
Simulation time 74100832 ps
CPU time 0.92 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:19 PM PST 23
Peak memory 204836 kb
Host smart-e1bb5be1-9383-4c5b-a0e8-daaab677d527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034613607 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.4034613607
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.1586106351
Short name T637
Test name
Test status
Simulation time 14783101 ps
CPU time 0.93 seconds
Started Dec 24 01:44:05 PM PST 23
Finished Dec 24 01:44:23 PM PST 23
Peak memory 205256 kb
Host smart-736dd581-3f26-48fd-972a-38c8b2860f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586106351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.1586106351
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.520945020
Short name T544
Test name
Test status
Simulation time 35755275 ps
CPU time 0.98 seconds
Started Dec 24 01:44:03 PM PST 23
Finished Dec 24 01:44:13 PM PST 23
Peak memory 204868 kb
Host smart-2f0a1a55-359a-4da8-bd3a-d848d76ff08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520945020 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.520945020
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.862687179
Short name T975
Test name
Test status
Simulation time 32423131 ps
CPU time 1.03 seconds
Started Dec 24 01:44:06 PM PST 23
Finished Dec 24 01:44:24 PM PST 23
Peak memory 214168 kb
Host smart-2c269f5d-a31b-4fd6-80f2-38c9baaec44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862687179 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.862687179
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.3725978886
Short name T815
Test name
Test status
Simulation time 60459733 ps
CPU time 2.53 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:20 PM PST 23
Peak memory 214276 kb
Host smart-df4f9b61-2f19-46cd-aa24-42905341b11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725978886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.3725978886
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.564368666
Short name T13
Test name
Test status
Simulation time 64759703 ps
CPU time 1.03 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:19 PM PST 23
Peak memory 214168 kb
Host smart-f4936f58-265e-4c96-b5d1-b62dd167c8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564368666 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.564368666
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.1933465738
Short name T836
Test name
Test status
Simulation time 62545202 ps
CPU time 0.97 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:19 PM PST 23
Peak memory 205320 kb
Host smart-f08d3132-9f04-423b-bcd6-6f086d555f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933465738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.1933465738
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.2474064598
Short name T493
Test name
Test status
Simulation time 16398677 ps
CPU time 0.95 seconds
Started Dec 24 01:44:09 PM PST 23
Finished Dec 24 01:44:30 PM PST 23
Peak memory 205072 kb
Host smart-ea5012f0-5533-47ad-a181-3010e36b3fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474064598 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.2474064598
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.2873047982
Short name T304
Test name
Test status
Simulation time 69993832 ps
CPU time 0.98 seconds
Started Dec 24 01:44:03 PM PST 23
Finished Dec 24 01:44:13 PM PST 23
Peak memory 205500 kb
Host smart-fffb9d43-dea7-4958-9735-6ba6cf0eb945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873047982 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.2873047982
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert_test.3559761043
Short name T831
Test name
Test status
Simulation time 104399172 ps
CPU time 0.88 seconds
Started Dec 24 01:42:46 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 205168 kb
Host smart-0c56a5b2-6ceb-4fe7-a9b3-b60b9fdcdfcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559761043 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.3559761043
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.3660007919
Short name T191
Test name
Test status
Simulation time 76730826 ps
CPU time 0.97 seconds
Started Dec 24 01:42:47 PM PST 23
Finished Dec 24 01:43:07 PM PST 23
Peak memory 214308 kb
Host smart-48a43c53-ae91-48e1-b52e-c5a77d122aa2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660007919 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.3660007919
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.2803747870
Short name T739
Test name
Test status
Simulation time 27625924 ps
CPU time 0.97 seconds
Started Dec 24 01:42:45 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 221244 kb
Host smart-33ad956d-7fb1-4006-be92-55a6bf6790a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803747870 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.2803747870
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.2889597793
Short name T649
Test name
Test status
Simulation time 18414991 ps
CPU time 0.97 seconds
Started Dec 24 01:43:02 PM PST 23
Finished Dec 24 01:43:20 PM PST 23
Peak memory 205224 kb
Host smart-c3b6655e-d724-4910-b00d-dc56da16f9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889597793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.2889597793
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.148907455
Short name T543
Test name
Test status
Simulation time 31131190 ps
CPU time 0.91 seconds
Started Dec 24 01:43:02 PM PST 23
Finished Dec 24 01:43:20 PM PST 23
Peak memory 213568 kb
Host smart-54a9a467-d378-4b80-929a-26917a34bc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148907455 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.148907455
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.3909119928
Short name T938
Test name
Test status
Simulation time 16897969 ps
CPU time 0.94 seconds
Started Dec 24 01:42:45 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 204812 kb
Host smart-75e9633e-634e-45f4-a320-03fef6df24fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909119928 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.3909119928
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.423008722
Short name T930
Test name
Test status
Simulation time 252612995 ps
CPU time 3.88 seconds
Started Dec 24 01:42:48 PM PST 23
Finished Dec 24 01:43:14 PM PST 23
Peak memory 205884 kb
Host smart-678fcec1-8a80-4018-97ad-88fd6355118b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423008722 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.423008722
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.594628347
Short name T136
Test name
Test status
Simulation time 441176714082 ps
CPU time 1179.54 seconds
Started Dec 24 01:42:52 PM PST 23
Finished Dec 24 02:02:54 PM PST 23
Peak memory 216504 kb
Host smart-2ccbf3c8-4260-4ae6-b4f4-f8069a1442a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594628347 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.594628347
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/231.edn_genbits.3603290693
Short name T711
Test name
Test status
Simulation time 48424637 ps
CPU time 0.94 seconds
Started Dec 24 01:44:07 PM PST 23
Finished Dec 24 01:44:25 PM PST 23
Peak memory 204672 kb
Host smart-9f8d7027-bf06-43cd-a024-b8884efbd17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603290693 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.3603290693
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.3013846625
Short name T335
Test name
Test status
Simulation time 13738775 ps
CPU time 0.91 seconds
Started Dec 24 01:44:02 PM PST 23
Finished Dec 24 01:44:11 PM PST 23
Peak memory 205156 kb
Host smart-7f4cfb91-8a1d-494e-99c1-1f467392bbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013846625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.3013846625
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.2755577978
Short name T336
Test name
Test status
Simulation time 29702839 ps
CPU time 0.97 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:19 PM PST 23
Peak memory 204888 kb
Host smart-c4dbb10a-6a1f-4139-9c9d-59c2d55bb400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755577978 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.2755577978
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.2616279942
Short name T907
Test name
Test status
Simulation time 19268710 ps
CPU time 0.98 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:18 PM PST 23
Peak memory 205056 kb
Host smart-9cccd830-0482-43c6-9b03-ec8c88cd74f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616279942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.2616279942
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.2822168611
Short name T833
Test name
Test status
Simulation time 148075888 ps
CPU time 1.79 seconds
Started Dec 24 01:44:03 PM PST 23
Finished Dec 24 01:44:14 PM PST 23
Peak memory 214160 kb
Host smart-7e13c013-5fe9-4430-a67f-9d088481125f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822168611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.2822168611
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.982558137
Short name T11
Test name
Test status
Simulation time 23765002 ps
CPU time 1.18 seconds
Started Dec 24 01:44:03 PM PST 23
Finished Dec 24 01:44:13 PM PST 23
Peak memory 214180 kb
Host smart-9da00f8b-5693-48ba-b46a-3c6a71f97773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982558137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.982558137
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.1087591225
Short name T555
Test name
Test status
Simulation time 13212110 ps
CPU time 0.98 seconds
Started Dec 24 01:44:03 PM PST 23
Finished Dec 24 01:44:13 PM PST 23
Peak memory 204816 kb
Host smart-b4190e13-24f0-40cd-bcf9-673d28a251b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087591225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.1087591225
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.2570125625
Short name T669
Test name
Test status
Simulation time 71305579 ps
CPU time 1.02 seconds
Started Dec 24 01:44:05 PM PST 23
Finished Dec 24 01:44:22 PM PST 23
Peak memory 205052 kb
Host smart-778b956d-a02f-439a-98e5-9306a0e59c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570125625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.2570125625
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.3625662721
Short name T340
Test name
Test status
Simulation time 18305096 ps
CPU time 1.04 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:17 PM PST 23
Peak memory 205328 kb
Host smart-327d6c39-b3f3-4dd8-83af-69e0846fa977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625662721 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.3625662721
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.4262627738
Short name T666
Test name
Test status
Simulation time 15096324 ps
CPU time 1.03 seconds
Started Dec 24 01:42:45 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 205248 kb
Host smart-b1a9a000-df57-4f8f-859d-044ac821edf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262627738 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.4262627738
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.3429618383
Short name T591
Test name
Test status
Simulation time 63080436 ps
CPU time 0.87 seconds
Started Dec 24 01:42:48 PM PST 23
Finished Dec 24 01:43:10 PM PST 23
Peak memory 204380 kb
Host smart-7191939e-dc16-4277-b0c7-044d870b293f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429618383 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.3429618383
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.724146570
Short name T138
Test name
Test status
Simulation time 79699453 ps
CPU time 0.85 seconds
Started Dec 24 01:42:44 PM PST 23
Finished Dec 24 01:43:04 PM PST 23
Peak memory 214336 kb
Host smart-96e24e43-c05f-456d-a9d1-f73b5b26f7fc
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724146570 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.724146570
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.2564145432
Short name T849
Test name
Test status
Simulation time 24910022 ps
CPU time 0.98 seconds
Started Dec 24 01:42:47 PM PST 23
Finished Dec 24 01:43:06 PM PST 23
Peak memory 215752 kb
Host smart-b4215271-314f-40f2-bf32-3822c1472d7b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564145432 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.2564145432
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.2953235245
Short name T197
Test name
Test status
Simulation time 25684139 ps
CPU time 1.26 seconds
Started Dec 24 01:42:51 PM PST 23
Finished Dec 24 01:43:15 PM PST 23
Peak memory 227504 kb
Host smart-63c5d496-332f-4ac8-b929-56155fff7283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953235245 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.2953235245
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.162092856
Short name T787
Test name
Test status
Simulation time 43987610 ps
CPU time 0.98 seconds
Started Dec 24 01:42:51 PM PST 23
Finished Dec 24 01:43:15 PM PST 23
Peak memory 205376 kb
Host smart-314c6d5e-3b60-4232-9e3d-9741d1235cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162092856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.162092856
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.3208113695
Short name T883
Test name
Test status
Simulation time 30293506 ps
CPU time 0.95 seconds
Started Dec 24 01:42:52 PM PST 23
Finished Dec 24 01:43:16 PM PST 23
Peak memory 221808 kb
Host smart-c81b91f9-5a87-4268-95a2-c5b622ade1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208113695 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.3208113695
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.1105167629
Short name T541
Test name
Test status
Simulation time 15491060 ps
CPU time 0.91 seconds
Started Dec 24 01:42:52 PM PST 23
Finished Dec 24 01:43:15 PM PST 23
Peak memory 204580 kb
Host smart-cb750144-c314-4e45-b56f-6d6f20cf2f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105167629 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.1105167629
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.906512521
Short name T943
Test name
Test status
Simulation time 847447628 ps
CPU time 2.09 seconds
Started Dec 24 01:42:45 PM PST 23
Finished Dec 24 01:43:06 PM PST 23
Peak memory 205896 kb
Host smart-c3fd1287-67dc-4c60-8ad0-209c9c0fea85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906512521 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.906512521
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.441318537
Short name T686
Test name
Test status
Simulation time 181056039509 ps
CPU time 1141.04 seconds
Started Dec 24 01:43:02 PM PST 23
Finished Dec 24 02:02:20 PM PST 23
Peak memory 218280 kb
Host smart-1250568a-f7f8-45f6-8f01-af8765859f3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441318537 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.441318537
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.1855839139
Short name T749
Test name
Test status
Simulation time 29825158 ps
CPU time 0.94 seconds
Started Dec 24 01:44:09 PM PST 23
Finished Dec 24 01:44:29 PM PST 23
Peak memory 205152 kb
Host smart-30afa454-c6e0-4118-b6da-ea7c32f8b663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855839139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.1855839139
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.1524926580
Short name T34
Test name
Test status
Simulation time 78352820 ps
CPU time 1.27 seconds
Started Dec 24 01:44:01 PM PST 23
Finished Dec 24 01:44:08 PM PST 23
Peak memory 205772 kb
Host smart-1a464991-f216-4625-804b-829545e4b8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524926580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.1524926580
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.1573719177
Short name T799
Test name
Test status
Simulation time 61859338 ps
CPU time 1.01 seconds
Started Dec 24 01:44:06 PM PST 23
Finished Dec 24 01:44:23 PM PST 23
Peak memory 205288 kb
Host smart-c16c8457-1bd4-4bcb-8c69-9e557a571db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573719177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1573719177
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.2887292008
Short name T485
Test name
Test status
Simulation time 17844734 ps
CPU time 1.2 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:19 PM PST 23
Peak memory 214152 kb
Host smart-ce939fd2-cea8-40ac-95be-6e9d115ce79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887292008 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.2887292008
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.2804882811
Short name T625
Test name
Test status
Simulation time 16702388 ps
CPU time 0.96 seconds
Started Dec 24 01:44:03 PM PST 23
Finished Dec 24 01:44:15 PM PST 23
Peak memory 204796 kb
Host smart-4d52b187-4654-468e-91ae-559d20e4ee0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804882811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.2804882811
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.2029563643
Short name T101
Test name
Test status
Simulation time 16570321 ps
CPU time 1.01 seconds
Started Dec 24 01:44:06 PM PST 23
Finished Dec 24 01:44:25 PM PST 23
Peak memory 205024 kb
Host smart-20dfdc3e-fcdc-43ca-a1bb-933d9ecfdfd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029563643 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.2029563643
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.4087155659
Short name T674
Test name
Test status
Simulation time 19843136 ps
CPU time 0.89 seconds
Started Dec 24 01:44:06 PM PST 23
Finished Dec 24 01:44:24 PM PST 23
Peak memory 205376 kb
Host smart-69f07330-b7fb-4e24-acdb-022b9273914b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087155659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.4087155659
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.1921692417
Short name T725
Test name
Test status
Simulation time 24728033 ps
CPU time 0.96 seconds
Started Dec 24 01:44:03 PM PST 23
Finished Dec 24 01:44:15 PM PST 23
Peak memory 204904 kb
Host smart-baf16fc3-d1a0-4425-a01d-95729a5c7189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921692417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.1921692417
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.262006268
Short name T880
Test name
Test status
Simulation time 155924868 ps
CPU time 1.1 seconds
Started Dec 24 01:44:11 PM PST 23
Finished Dec 24 01:44:32 PM PST 23
Peak memory 205476 kb
Host smart-68879c7a-92a4-44fb-979a-2b39e88f29ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262006268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.262006268
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.1268789682
Short name T513
Test name
Test status
Simulation time 64914761 ps
CPU time 2.48 seconds
Started Dec 24 01:44:06 PM PST 23
Finished Dec 24 01:44:24 PM PST 23
Peak memory 214056 kb
Host smart-1c696ba4-8b90-40b8-baf5-7aec7a136f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268789682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.1268789682
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.2737091652
Short name T50
Test name
Test status
Simulation time 41302165 ps
CPU time 0.96 seconds
Started Dec 24 01:42:47 PM PST 23
Finished Dec 24 01:43:07 PM PST 23
Peak memory 205268 kb
Host smart-a8432061-3273-48c0-84ac-cf451ef39b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737091652 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.2737091652
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.2399712278
Short name T829
Test name
Test status
Simulation time 17793528 ps
CPU time 0.95 seconds
Started Dec 24 01:42:48 PM PST 23
Finished Dec 24 01:43:09 PM PST 23
Peak memory 204936 kb
Host smart-dcfd0bed-8ec6-410f-9d0a-5d306acba6f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399712278 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.2399712278
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.3841169808
Short name T66
Test name
Test status
Simulation time 62586024 ps
CPU time 0.84 seconds
Started Dec 24 01:42:46 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 214312 kb
Host smart-91659c26-c989-49ec-817d-a1ebec925f76
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841169808 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.3841169808
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.3026259478
Short name T186
Test name
Test status
Simulation time 25238187 ps
CPU time 1.18 seconds
Started Dec 24 01:45:04 PM PST 23
Finished Dec 24 01:45:06 PM PST 23
Peak memory 214412 kb
Host smart-014ab226-3019-4f7a-a0e4-d12b0856deb5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026259478 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.3026259478
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.2753418160
Short name T120
Test name
Test status
Simulation time 29651313 ps
CPU time 1.21 seconds
Started Dec 24 01:42:47 PM PST 23
Finished Dec 24 01:43:07 PM PST 23
Peak memory 217136 kb
Host smart-20e8913b-d7ed-4bb1-84d7-d9513094d0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753418160 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.2753418160
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.3326482259
Short name T768
Test name
Test status
Simulation time 20182006 ps
CPU time 1.1 seconds
Started Dec 24 01:42:46 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 205464 kb
Host smart-f8b8aa2c-8b8a-46cf-81b8-19ff89ab8c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326482259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3326482259
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.2998877744
Short name T935
Test name
Test status
Simulation time 17711492 ps
CPU time 1.16 seconds
Started Dec 24 01:44:43 PM PST 23
Finished Dec 24 01:44:46 PM PST 23
Peak memory 211720 kb
Host smart-6e6bddb8-4f15-4d14-a141-4b6dfeadbb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998877744 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.2998877744
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.3542227261
Short name T522
Test name
Test status
Simulation time 17870358 ps
CPU time 0.91 seconds
Started Dec 24 01:42:48 PM PST 23
Finished Dec 24 01:43:10 PM PST 23
Peak memory 204716 kb
Host smart-b4f2529b-b5c1-4aaa-a1e8-e39c24055827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542227261 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.3542227261
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.4254701745
Short name T780
Test name
Test status
Simulation time 476928943 ps
CPU time 2.9 seconds
Started Dec 24 01:42:47 PM PST 23
Finished Dec 24 01:43:08 PM PST 23
Peak memory 205896 kb
Host smart-1fdde3e0-8aa0-4618-8043-c6ec5c607e3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254701745 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.4254701745
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/250.edn_genbits.2761764675
Short name T305
Test name
Test status
Simulation time 20143214 ps
CPU time 1.12 seconds
Started Dec 24 01:44:06 PM PST 23
Finished Dec 24 01:44:25 PM PST 23
Peak memory 214180 kb
Host smart-0378b319-e4f3-4fdb-83b6-39e3468d2fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761764675 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.2761764675
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.2663800372
Short name T562
Test name
Test status
Simulation time 41982284 ps
CPU time 0.88 seconds
Started Dec 24 01:44:18 PM PST 23
Finished Dec 24 01:44:36 PM PST 23
Peak memory 205388 kb
Host smart-4a65464a-9968-4175-8495-0bf7c538e0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663800372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.2663800372
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.1928779918
Short name T622
Test name
Test status
Simulation time 84087990 ps
CPU time 1.05 seconds
Started Dec 24 01:44:07 PM PST 23
Finished Dec 24 01:44:27 PM PST 23
Peak memory 214172 kb
Host smart-2807ce4c-8715-4297-ba9f-709d41ce3882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928779918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.1928779918
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.392633328
Short name T682
Test name
Test status
Simulation time 14043237 ps
CPU time 0.94 seconds
Started Dec 24 01:44:03 PM PST 23
Finished Dec 24 01:44:14 PM PST 23
Peak memory 205004 kb
Host smart-9233cb60-6e54-42c3-af84-b8caaea74b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392633328 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.392633328
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.2612744336
Short name T890
Test name
Test status
Simulation time 29043627 ps
CPU time 1.13 seconds
Started Dec 24 01:44:08 PM PST 23
Finished Dec 24 01:44:28 PM PST 23
Peak memory 205708 kb
Host smart-59460d0d-394b-4738-8116-0d8a27026b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612744336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.2612744336
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.3187373561
Short name T716
Test name
Test status
Simulation time 50676012 ps
CPU time 0.92 seconds
Started Dec 24 01:44:06 PM PST 23
Finished Dec 24 01:44:24 PM PST 23
Peak memory 205384 kb
Host smart-6e089deb-2562-4bb3-acb9-138dff282a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187373561 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.3187373561
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.3685298949
Short name T491
Test name
Test status
Simulation time 34231423 ps
CPU time 1.01 seconds
Started Dec 24 01:44:05 PM PST 23
Finished Dec 24 01:44:20 PM PST 23
Peak memory 205568 kb
Host smart-6a85ef24-58a1-43b4-b181-61de2dc0911b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685298949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.3685298949
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.2667222299
Short name T571
Test name
Test status
Simulation time 62502601 ps
CPU time 0.99 seconds
Started Dec 24 01:44:08 PM PST 23
Finished Dec 24 01:44:28 PM PST 23
Peak memory 204768 kb
Host smart-10d094c6-6a80-4a44-8378-c405daba805e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667222299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.2667222299
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.3802672976
Short name T827
Test name
Test status
Simulation time 63022343 ps
CPU time 1.1 seconds
Started Dec 24 01:44:09 PM PST 23
Finished Dec 24 01:44:30 PM PST 23
Peak memory 214152 kb
Host smart-798875fc-ecd2-47e3-9e4d-43abbe3a2f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802672976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.3802672976
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.2134450110
Short name T957
Test name
Test status
Simulation time 59239754 ps
CPU time 0.98 seconds
Started Dec 24 01:42:46 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 205116 kb
Host smart-72ec2087-c45d-4e9c-8459-4afb42fad29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134450110 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.2134450110
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.3436344329
Short name T688
Test name
Test status
Simulation time 34470290 ps
CPU time 0.78 seconds
Started Dec 24 01:45:04 PM PST 23
Finished Dec 24 01:45:06 PM PST 23
Peak memory 203956 kb
Host smart-9d4ee372-5a79-4212-ba77-4fbe7f98e01a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436344329 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.3436344329
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.1471056226
Short name T866
Test name
Test status
Simulation time 18874261 ps
CPU time 0.81 seconds
Started Dec 24 01:45:04 PM PST 23
Finished Dec 24 01:45:06 PM PST 23
Peak memory 214092 kb
Host smart-3c7735ed-1b30-4869-a97a-24fd34fd89ee
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471056226 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.1471056226
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_err.4170294860
Short name T112
Test name
Test status
Simulation time 21028182 ps
CPU time 1.15 seconds
Started Dec 24 01:44:43 PM PST 23
Finished Dec 24 01:44:45 PM PST 23
Peak memory 213444 kb
Host smart-454d71c0-df55-4e4e-acd1-74bd7071850b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170294860 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.4170294860
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.1526348029
Short name T306
Test name
Test status
Simulation time 20146381 ps
CPU time 1.02 seconds
Started Dec 24 01:42:47 PM PST 23
Finished Dec 24 01:43:07 PM PST 23
Peak memory 205648 kb
Host smart-ffef4344-686d-48b5-98a3-005fc84b01fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526348029 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.1526348029
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_smoke.2678981275
Short name T461
Test name
Test status
Simulation time 21050553 ps
CPU time 0.91 seconds
Started Dec 24 01:42:47 PM PST 23
Finished Dec 24 01:43:06 PM PST 23
Peak memory 204884 kb
Host smart-e1ad8539-1de1-45e9-921a-9e402de418b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678981275 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.2678981275
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.1410739456
Short name T474
Test name
Test status
Simulation time 115790299 ps
CPU time 2.01 seconds
Started Dec 24 01:42:46 PM PST 23
Finished Dec 24 01:43:06 PM PST 23
Peak memory 205856 kb
Host smart-f15ca8f5-8b9c-4b49-a8f3-1ac55a262182
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410739456 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.1410739456
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/260.edn_genbits.4118628266
Short name T950
Test name
Test status
Simulation time 59895855 ps
CPU time 0.94 seconds
Started Dec 24 01:44:07 PM PST 23
Finished Dec 24 01:44:27 PM PST 23
Peak memory 205628 kb
Host smart-03d307e7-69f4-47af-9935-cddbb7c27a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118628266 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.4118628266
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.2356950987
Short name T791
Test name
Test status
Simulation time 19982444 ps
CPU time 1.09 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:18 PM PST 23
Peak memory 205556 kb
Host smart-27401799-66c6-4c1c-976d-946f18fba6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356950987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.2356950987
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.2077995900
Short name T736
Test name
Test status
Simulation time 23778171 ps
CPU time 1.21 seconds
Started Dec 24 01:44:06 PM PST 23
Finished Dec 24 01:44:24 PM PST 23
Peak memory 214120 kb
Host smart-c090f711-ceb0-481a-a4ca-f7e34414d187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077995900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.2077995900
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.2061065438
Short name T269
Test name
Test status
Simulation time 29902629 ps
CPU time 1.03 seconds
Started Dec 24 01:44:09 PM PST 23
Finished Dec 24 01:44:30 PM PST 23
Peak memory 205216 kb
Host smart-e81e305b-f95b-4474-b895-004c45dae3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061065438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.2061065438
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.2464954478
Short name T601
Test name
Test status
Simulation time 20862199 ps
CPU time 1.04 seconds
Started Dec 24 01:44:03 PM PST 23
Finished Dec 24 01:44:16 PM PST 23
Peak memory 205060 kb
Host smart-f3379d8c-0b0f-44bd-ac0e-83208a438b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464954478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.2464954478
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.3306718738
Short name T598
Test name
Test status
Simulation time 16298469 ps
CPU time 1.04 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:17 PM PST 23
Peak memory 205688 kb
Host smart-4928baae-3322-4919-a266-e3899f11bd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306718738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.3306718738
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.1701931718
Short name T971
Test name
Test status
Simulation time 52234349 ps
CPU time 0.92 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:19 PM PST 23
Peak memory 204876 kb
Host smart-3afe85d8-e58b-4a23-80c1-0620a811ac90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701931718 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.1701931718
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.3331548931
Short name T945
Test name
Test status
Simulation time 46878125 ps
CPU time 0.87 seconds
Started Dec 24 01:44:03 PM PST 23
Finished Dec 24 01:44:12 PM PST 23
Peak memory 205104 kb
Host smart-0273cd9b-b19c-4ca5-85ed-1f1710effffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331548931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.3331548931
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.812060998
Short name T596
Test name
Test status
Simulation time 38021582 ps
CPU time 0.88 seconds
Started Dec 24 01:44:09 PM PST 23
Finished Dec 24 01:44:30 PM PST 23
Peak memory 205344 kb
Host smart-145acb5b-5595-4dd3-b839-f3594160afce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812060998 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.812060998
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.123878071
Short name T568
Test name
Test status
Simulation time 26261642 ps
CPU time 0.91 seconds
Started Dec 24 01:44:02 PM PST 23
Finished Dec 24 01:44:11 PM PST 23
Peak memory 205004 kb
Host smart-6f054dca-a67e-4fe0-8be3-0bb5e1ab713a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123878071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.123878071
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.37714652
Short name T61
Test name
Test status
Simulation time 193676886 ps
CPU time 0.97 seconds
Started Dec 24 01:42:48 PM PST 23
Finished Dec 24 01:43:12 PM PST 23
Peak memory 205980 kb
Host smart-d3a4bb4e-f47b-4114-aa9e-144f8f93a2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37714652 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.37714652
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.2972567127
Short name T468
Test name
Test status
Simulation time 52087468 ps
CPU time 0.86 seconds
Started Dec 24 01:42:51 PM PST 23
Finished Dec 24 01:43:14 PM PST 23
Peak memory 205344 kb
Host smart-79c31d57-2fb7-4346-8199-f3a57eb132dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972567127 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.2972567127
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.725564483
Short name T937
Test name
Test status
Simulation time 23077909 ps
CPU time 0.87 seconds
Started Dec 24 01:42:50 PM PST 23
Finished Dec 24 01:43:14 PM PST 23
Peak memory 214052 kb
Host smart-affcde08-ec58-4b60-8313-1b649042f404
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725564483 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.725564483
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_err.1358467005
Short name T215
Test name
Test status
Simulation time 28202276 ps
CPU time 0.94 seconds
Started Dec 24 01:42:50 PM PST 23
Finished Dec 24 01:43:14 PM PST 23
Peak memory 220864 kb
Host smart-2c0abd56-24f8-486f-8ac0-510dab0b61e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358467005 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.1358467005
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.1110832842
Short name T696
Test name
Test status
Simulation time 71053460 ps
CPU time 1.35 seconds
Started Dec 24 01:45:04 PM PST 23
Finished Dec 24 01:45:07 PM PST 23
Peak memory 204340 kb
Host smart-b629afcb-0dec-4702-8ce6-eacf011acdbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110832842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.1110832842
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.2783993359
Short name T585
Test name
Test status
Simulation time 35552004 ps
CPU time 0.98 seconds
Started Dec 24 01:42:49 PM PST 23
Finished Dec 24 01:43:13 PM PST 23
Peak memory 221640 kb
Host smart-365ebef8-9ab4-44b3-8436-3dc2f41085a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783993359 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.2783993359
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.3813904108
Short name T451
Test name
Test status
Simulation time 27401198 ps
CPU time 1.02 seconds
Started Dec 24 01:44:43 PM PST 23
Finished Dec 24 01:44:45 PM PST 23
Peak memory 202420 kb
Host smart-543f9068-2032-4769-a1d0-3d0828178144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813904108 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.3813904108
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.1582324882
Short name T661
Test name
Test status
Simulation time 128882509 ps
CPU time 2.83 seconds
Started Dec 24 01:44:43 PM PST 23
Finished Dec 24 01:44:47 PM PST 23
Peak memory 203324 kb
Host smart-88f1f326-9231-48a4-ba2b-a10463080527
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582324882 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.1582324882
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.383834598
Short name T771
Test name
Test status
Simulation time 382463837356 ps
CPU time 1845.38 seconds
Started Dec 24 01:42:48 PM PST 23
Finished Dec 24 02:13:55 PM PST 23
Peak memory 219960 kb
Host smart-df51984c-397e-4a89-8710-694f96bc1243
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383834598 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.383834598
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/271.edn_genbits.1935012365
Short name T629
Test name
Test status
Simulation time 15583034 ps
CPU time 1 seconds
Started Dec 24 01:44:05 PM PST 23
Finished Dec 24 01:44:21 PM PST 23
Peak memory 205132 kb
Host smart-baf3c016-aa20-49b4-b4a3-5078426731bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935012365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.1935012365
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.1340091719
Short name T635
Test name
Test status
Simulation time 16626193 ps
CPU time 0.97 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:18 PM PST 23
Peak memory 205408 kb
Host smart-e2eb1018-2a57-4aef-a926-985956ae6845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340091719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1340091719
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.85257633
Short name T471
Test name
Test status
Simulation time 29014132 ps
CPU time 0.93 seconds
Started Dec 24 01:44:01 PM PST 23
Finished Dec 24 01:44:09 PM PST 23
Peak memory 205180 kb
Host smart-100a0c0b-af57-4940-912f-580ed55fded5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85257633 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.85257633
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.100844563
Short name T309
Test name
Test status
Simulation time 33432348 ps
CPU time 1.19 seconds
Started Dec 24 01:44:05 PM PST 23
Finished Dec 24 01:44:21 PM PST 23
Peak memory 214160 kb
Host smart-7ee431c6-382a-456b-97fa-563c4ad2d842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100844563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.100844563
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.2736190499
Short name T772
Test name
Test status
Simulation time 51868906 ps
CPU time 0.98 seconds
Started Dec 24 01:44:03 PM PST 23
Finished Dec 24 01:44:14 PM PST 23
Peak memory 205472 kb
Host smart-89c8e34b-6411-4a16-8590-c220901c4dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736190499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.2736190499
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.1127953216
Short name T936
Test name
Test status
Simulation time 20137756 ps
CPU time 1.28 seconds
Started Dec 24 01:44:08 PM PST 23
Finished Dec 24 01:44:29 PM PST 23
Peak memory 205744 kb
Host smart-af979189-3f5f-4f1a-8e58-7481a9294194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127953216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.1127953216
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.2534317637
Short name T867
Test name
Test status
Simulation time 39844092 ps
CPU time 1.82 seconds
Started Dec 24 01:44:14 PM PST 23
Finished Dec 24 01:44:35 PM PST 23
Peak memory 214168 kb
Host smart-165aa648-3347-413a-9605-a31ff4859599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534317637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.2534317637
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.4231132806
Short name T526
Test name
Test status
Simulation time 90313884 ps
CPU time 1.27 seconds
Started Dec 24 01:44:12 PM PST 23
Finished Dec 24 01:44:33 PM PST 23
Peak memory 213928 kb
Host smart-374f5677-9bec-4af2-b9b3-8297e17b6f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231132806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.4231132806
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.615665600
Short name T504
Test name
Test status
Simulation time 239648978 ps
CPU time 0.98 seconds
Started Dec 24 01:45:04 PM PST 23
Finished Dec 24 01:45:06 PM PST 23
Peak memory 204492 kb
Host smart-4a6d5708-5abe-4d6b-b547-8b8b21e5cbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615665600 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.615665600
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.742044456
Short name T719
Test name
Test status
Simulation time 21339791 ps
CPU time 0.87 seconds
Started Dec 24 01:42:52 PM PST 23
Finished Dec 24 01:43:15 PM PST 23
Peak memory 205308 kb
Host smart-3a2251f2-816f-4981-b15a-01f1f3f7b103
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742044456 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.742044456
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.2949958680
Short name T65
Test name
Test status
Simulation time 10613891 ps
CPU time 0.85 seconds
Started Dec 24 01:42:52 PM PST 23
Finished Dec 24 01:43:15 PM PST 23
Peak memory 214276 kb
Host smart-daf3d175-a3ed-4981-bb51-eb56aee75dc6
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949958680 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.2949958680
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.3316113195
Short name T537
Test name
Test status
Simulation time 25786786 ps
CPU time 1.01 seconds
Started Dec 24 01:42:46 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 214428 kb
Host smart-c012a0e8-0ff0-4748-809c-e86967762dc5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316113195 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.3316113195
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.61839081
Short name T659
Test name
Test status
Simulation time 127816009 ps
CPU time 1.15 seconds
Started Dec 24 01:43:02 PM PST 23
Finished Dec 24 01:43:20 PM PST 23
Peak memory 213804 kb
Host smart-23ef18ea-3a6e-4912-a5f2-126b52fda9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61839081 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.61839081
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.2983998450
Short name T940
Test name
Test status
Simulation time 56229978 ps
CPU time 1.06 seconds
Started Dec 24 01:42:49 PM PST 23
Finished Dec 24 01:43:13 PM PST 23
Peak memory 205180 kb
Host smart-4b31fb3b-0555-40c9-9476-ab49d73946c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983998450 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.2983998450
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.727556302
Short name T535
Test name
Test status
Simulation time 29477728 ps
CPU time 0.97 seconds
Started Dec 24 01:44:43 PM PST 23
Finished Dec 24 01:44:45 PM PST 23
Peak memory 211836 kb
Host smart-a4955606-c610-470a-acd4-bbe7e25d78f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727556302 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.727556302
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.3958605642
Short name T456
Test name
Test status
Simulation time 30633990 ps
CPU time 0.85 seconds
Started Dec 24 01:42:48 PM PST 23
Finished Dec 24 01:43:12 PM PST 23
Peak memory 204848 kb
Host smart-b783f281-b079-4b58-8910-83fb5f6bf677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958605642 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.3958605642
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.4120180502
Short name T819
Test name
Test status
Simulation time 280730567 ps
CPU time 1.14 seconds
Started Dec 24 01:42:49 PM PST 23
Finished Dec 24 01:43:14 PM PST 23
Peak memory 205368 kb
Host smart-cc056779-57be-496c-a641-5f88e8e75748
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120180502 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.4120180502
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.1232115932
Short name T973
Test name
Test status
Simulation time 166901273609 ps
CPU time 878.83 seconds
Started Dec 24 01:44:43 PM PST 23
Finished Dec 24 01:59:23 PM PST 23
Peak memory 213148 kb
Host smart-a15c8f34-7b84-459e-b563-8010b5a30b1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232115932 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.1232115932
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.721805555
Short name T825
Test name
Test status
Simulation time 116559343 ps
CPU time 1.18 seconds
Started Dec 24 01:44:08 PM PST 23
Finished Dec 24 01:44:29 PM PST 23
Peak memory 214164 kb
Host smart-d9f537ba-bf6a-47a6-8c54-a020b535a9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721805555 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.721805555
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.106386890
Short name T746
Test name
Test status
Simulation time 85875440 ps
CPU time 0.9 seconds
Started Dec 24 01:44:15 PM PST 23
Finished Dec 24 01:44:35 PM PST 23
Peak memory 204852 kb
Host smart-e98d0899-26d5-4b97-8812-aa23f074e5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106386890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.106386890
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.2755650033
Short name T271
Test name
Test status
Simulation time 48985737 ps
CPU time 0.98 seconds
Started Dec 24 01:44:12 PM PST 23
Finished Dec 24 01:44:33 PM PST 23
Peak memory 213936 kb
Host smart-d62cf04e-7890-4b85-a4da-f1d463c54cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755650033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.2755650033
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.185350495
Short name T279
Test name
Test status
Simulation time 18599978 ps
CPU time 0.94 seconds
Started Dec 24 01:44:10 PM PST 23
Finished Dec 24 01:44:31 PM PST 23
Peak memory 205064 kb
Host smart-35b82e38-f69b-449c-b80d-34b8bbb6592e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185350495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.185350495
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.3989810736
Short name T837
Test name
Test status
Simulation time 60159131 ps
CPU time 1.13 seconds
Started Dec 24 01:44:11 PM PST 23
Finished Dec 24 01:44:32 PM PST 23
Peak memory 214156 kb
Host smart-22d5c338-9f11-49a4-98e2-f4771cd0a8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989810736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.3989810736
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.4098023437
Short name T46
Test name
Test status
Simulation time 33318856 ps
CPU time 0.96 seconds
Started Dec 24 01:44:14 PM PST 23
Finished Dec 24 01:44:34 PM PST 23
Peak memory 205004 kb
Host smart-9efbda41-4ac0-44ad-9faf-def22f829745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098023437 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.4098023437
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.3222498953
Short name T802
Test name
Test status
Simulation time 96679107 ps
CPU time 0.99 seconds
Started Dec 24 01:44:05 PM PST 23
Finished Dec 24 01:44:21 PM PST 23
Peak memory 214068 kb
Host smart-18714ef0-cdda-47a3-83a3-8bf152b3ded2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222498953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.3222498953
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.3101424868
Short name T339
Test name
Test status
Simulation time 57262350 ps
CPU time 0.95 seconds
Started Dec 24 01:44:08 PM PST 23
Finished Dec 24 01:44:29 PM PST 23
Peak memory 205388 kb
Host smart-0dbe0ffc-bd09-4a3a-bfe5-be61d6ca56df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101424868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3101424868
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.4023291039
Short name T528
Test name
Test status
Simulation time 20463998 ps
CPU time 1.13 seconds
Started Dec 24 01:44:18 PM PST 23
Finished Dec 24 01:44:37 PM PST 23
Peak memory 214048 kb
Host smart-6fbe31ce-e2bf-4e89-a262-b9bc186a57e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023291039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.4023291039
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.2432160101
Short name T846
Test name
Test status
Simulation time 55905243 ps
CPU time 0.95 seconds
Started Dec 24 01:42:46 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 205896 kb
Host smart-eb01917e-2e89-4f68-a7a5-233f2bf65b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432160101 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.2432160101
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.4227311176
Short name T861
Test name
Test status
Simulation time 50120613 ps
CPU time 0.87 seconds
Started Dec 24 01:42:53 PM PST 23
Finished Dec 24 01:43:16 PM PST 23
Peak memory 204520 kb
Host smart-8e7f90f7-58c3-49ea-a39b-0e784282cf80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227311176 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.4227311176
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.1514852827
Short name T147
Test name
Test status
Simulation time 17723458 ps
CPU time 0.85 seconds
Started Dec 24 01:42:46 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 214324 kb
Host smart-440c3e0c-baa4-4f84-a336-1671418fd01c
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514852827 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.1514852827
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.2304313028
Short name T906
Test name
Test status
Simulation time 20838687 ps
CPU time 0.99 seconds
Started Dec 24 01:42:50 PM PST 23
Finished Dec 24 01:43:14 PM PST 23
Peak memory 214436 kb
Host smart-0a0ece30-919c-4078-b750-ad993860cd3f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304313028 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.2304313028
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.2996705081
Short name T844
Test name
Test status
Simulation time 31383505 ps
CPU time 1.06 seconds
Started Dec 24 01:42:47 PM PST 23
Finished Dec 24 01:43:07 PM PST 23
Peak memory 215840 kb
Host smart-598141c0-44a6-42d2-a415-5d62b31eb9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996705081 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.2996705081
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.3383906355
Short name T275
Test name
Test status
Simulation time 15271149 ps
CPU time 1.08 seconds
Started Dec 24 01:42:46 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 205224 kb
Host smart-1c8f04cf-846b-4b44-859f-f865e6b164f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383906355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.3383906355
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.99842068
Short name T40
Test name
Test status
Simulation time 40828457 ps
CPU time 0.98 seconds
Started Dec 24 01:42:51 PM PST 23
Finished Dec 24 01:43:15 PM PST 23
Peak memory 221568 kb
Host smart-7d57a239-ae2b-442f-ab41-37a7b6ec4fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99842068 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.99842068
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.3762585966
Short name T939
Test name
Test status
Simulation time 45720167 ps
CPU time 0.86 seconds
Started Dec 24 01:42:46 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 204748 kb
Host smart-3cd3fcb9-79e0-4690-8fd4-fd3ffb606493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762585966 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.3762585966
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.3036363978
Short name T920
Test name
Test status
Simulation time 99515916 ps
CPU time 1.07 seconds
Started Dec 24 01:42:46 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 205084 kb
Host smart-1964c9d5-58c0-472a-946c-570bb94cb77e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036363978 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.3036363978
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.3928493710
Short name T905
Test name
Test status
Simulation time 193809651122 ps
CPU time 1256.81 seconds
Started Dec 24 01:42:47 PM PST 23
Finished Dec 24 02:04:01 PM PST 23
Peak memory 218756 kb
Host smart-24173c66-9153-4f68-a67f-682b187753b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928493710 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.3928493710
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/291.edn_genbits.1776258026
Short name T607
Test name
Test status
Simulation time 41821960 ps
CPU time 0.96 seconds
Started Dec 24 01:44:11 PM PST 23
Finished Dec 24 01:44:31 PM PST 23
Peak memory 205444 kb
Host smart-20452b3b-ea1b-4d0f-80e8-547c37f726b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776258026 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.1776258026
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.1396797214
Short name T506
Test name
Test status
Simulation time 139462653 ps
CPU time 3.05 seconds
Started Dec 24 01:44:12 PM PST 23
Finished Dec 24 01:44:35 PM PST 23
Peak memory 213980 kb
Host smart-9873b326-a35e-4f3f-8afa-4188de48a97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396797214 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.1396797214
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.1506131797
Short name T964
Test name
Test status
Simulation time 34038289 ps
CPU time 0.95 seconds
Started Dec 24 01:44:08 PM PST 23
Finished Dec 24 01:44:28 PM PST 23
Peak memory 205492 kb
Host smart-e1c9878a-a9a0-432f-8a8e-89763a711b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506131797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.1506131797
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.789185329
Short name T639
Test name
Test status
Simulation time 338802099 ps
CPU time 1.38 seconds
Started Dec 24 01:44:08 PM PST 23
Finished Dec 24 01:44:30 PM PST 23
Peak memory 214124 kb
Host smart-d4f77c76-21fd-4073-9154-dc6dda60a318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789185329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.789185329
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.3869625432
Short name T47
Test name
Test status
Simulation time 81160017 ps
CPU time 0.96 seconds
Started Dec 24 01:44:12 PM PST 23
Finished Dec 24 01:44:32 PM PST 23
Peak memory 204880 kb
Host smart-46a6c011-2578-4419-bad5-ce17971b8592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869625432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.3869625432
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.1438794331
Short name T710
Test name
Test status
Simulation time 234812529 ps
CPU time 0.95 seconds
Started Dec 24 01:44:14 PM PST 23
Finished Dec 24 01:44:34 PM PST 23
Peak memory 204976 kb
Host smart-992ebd38-a989-4d04-8073-f29be64eb0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438794331 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.1438794331
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.2728774067
Short name T554
Test name
Test status
Simulation time 21459006 ps
CPU time 0.98 seconds
Started Dec 24 01:44:08 PM PST 23
Finished Dec 24 01:44:28 PM PST 23
Peak memory 205156 kb
Host smart-d774720c-6e3c-4f35-a611-e14997a29e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728774067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.2728774067
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.1023309322
Short name T672
Test name
Test status
Simulation time 80354075 ps
CPU time 0.95 seconds
Started Dec 24 01:42:45 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 205028 kb
Host smart-1a637ee3-fd56-488f-a4d9-625f19026bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023309322 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.1023309322
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.3614448869
Short name T727
Test name
Test status
Simulation time 13846388 ps
CPU time 0.86 seconds
Started Dec 24 01:42:47 PM PST 23
Finished Dec 24 01:43:06 PM PST 23
Peak memory 204448 kb
Host smart-febcebae-4f42-488c-9ac2-15b8f107d030
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614448869 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.3614448869
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.1738457053
Short name T870
Test name
Test status
Simulation time 19021870 ps
CPU time 0.86 seconds
Started Dec 24 01:42:37 PM PST 23
Finished Dec 24 01:42:44 PM PST 23
Peak memory 214344 kb
Host smart-82a9c0d1-841a-413a-bd78-2ff65fcad686
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738457053 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.1738457053
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.3407490208
Short name T69
Test name
Test status
Simulation time 45385237 ps
CPU time 0.97 seconds
Started Dec 24 01:42:40 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 214416 kb
Host smart-9bad940c-160e-4ec3-af27-5b19d9b0d658
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407490208 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.3407490208
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.1826075466
Short name T213
Test name
Test status
Simulation time 28663303 ps
CPU time 0.83 seconds
Started Dec 24 01:42:42 PM PST 23
Finished Dec 24 01:42:54 PM PST 23
Peak memory 215232 kb
Host smart-d7a2affe-ba96-4ced-ba33-d285b2305541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826075466 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.1826075466
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.1395240976
Short name T574
Test name
Test status
Simulation time 328988067 ps
CPU time 3.06 seconds
Started Dec 24 01:42:42 PM PST 23
Finished Dec 24 01:43:01 PM PST 23
Peak memory 214172 kb
Host smart-8170960b-38a1-46d1-8524-0e49fb486298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395240976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.1395240976
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.2357208723
Short name T882
Test name
Test status
Simulation time 20195459 ps
CPU time 0.99 seconds
Started Dec 24 01:42:38 PM PST 23
Finished Dec 24 01:42:47 PM PST 23
Peak memory 214528 kb
Host smart-8d8c6877-0d8d-466c-a783-94b81b7ac283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357208723 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.2357208723
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_smoke.3074037842
Short name T475
Test name
Test status
Simulation time 16524980 ps
CPU time 0.92 seconds
Started Dec 24 01:42:43 PM PST 23
Finished Dec 24 01:43:00 PM PST 23
Peak memory 204936 kb
Host smart-b3521bf9-0c09-47aa-88c7-875340342ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074037842 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.3074037842
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.910492265
Short name T854
Test name
Test status
Simulation time 56294232 ps
CPU time 1.83 seconds
Started Dec 24 01:42:44 PM PST 23
Finished Dec 24 01:43:06 PM PST 23
Peak memory 205780 kb
Host smart-8af4916b-9e5a-4af7-a366-1b0cf0403501
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910492265 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.910492265
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3920398711
Short name T750
Test name
Test status
Simulation time 46555276040 ps
CPU time 678.98 seconds
Started Dec 24 01:42:31 PM PST 23
Finished Dec 24 01:53:52 PM PST 23
Peak memory 215624 kb
Host smart-8df56172-4e74-4c55-acbf-cad7c2303ba2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920398711 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3920398711
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.3986721349
Short name T577
Test name
Test status
Simulation time 240193462 ps
CPU time 0.97 seconds
Started Dec 24 01:42:51 PM PST 23
Finished Dec 24 01:43:14 PM PST 23
Peak memory 205164 kb
Host smart-329c66fe-f1fb-45a9-9de6-df466b815074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986721349 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.3986721349
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.1473689485
Short name T557
Test name
Test status
Simulation time 21261297 ps
CPU time 1.03 seconds
Started Dec 24 01:42:58 PM PST 23
Finished Dec 24 01:43:17 PM PST 23
Peak memory 205444 kb
Host smart-194d1615-29c4-4d6f-8cec-74f2b7214e19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473689485 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.1473689485
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.4123701276
Short name T902
Test name
Test status
Simulation time 149326869 ps
CPU time 1.04 seconds
Started Dec 24 01:42:53 PM PST 23
Finished Dec 24 01:43:17 PM PST 23
Peak memory 214500 kb
Host smart-2f0e1660-1acb-4f00-a779-62a9fb476fa6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123701276 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.4123701276
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.3446797824
Short name T967
Test name
Test status
Simulation time 135470643 ps
CPU time 0.96 seconds
Started Dec 24 01:42:51 PM PST 23
Finished Dec 24 01:43:14 PM PST 23
Peak memory 216684 kb
Host smart-b4f04066-a6a6-4ebf-b866-1cc3916f3e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446797824 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.3446797824
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.3135930658
Short name T349
Test name
Test status
Simulation time 60475840 ps
CPU time 1.12 seconds
Started Dec 24 01:42:58 PM PST 23
Finished Dec 24 01:43:18 PM PST 23
Peak memory 214184 kb
Host smart-13114b91-5a56-479b-a06c-265429e1cdb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135930658 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3135930658
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.660202355
Short name T974
Test name
Test status
Simulation time 17605378 ps
CPU time 1.04 seconds
Started Dec 24 01:43:00 PM PST 23
Finished Dec 24 01:43:18 PM PST 23
Peak memory 214524 kb
Host smart-d3aff5cb-ddca-4311-accc-89f4ddf51c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660202355 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.660202355
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.3548916234
Short name T457
Test name
Test status
Simulation time 26693851 ps
CPU time 0.87 seconds
Started Dec 24 01:42:51 PM PST 23
Finished Dec 24 01:43:14 PM PST 23
Peak memory 204632 kb
Host smart-94a56d13-47cb-4feb-8926-1de3b2678403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548916234 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.3548916234
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.899585474
Short name T529
Test name
Test status
Simulation time 424365506 ps
CPU time 2.78 seconds
Started Dec 24 01:42:51 PM PST 23
Finished Dec 24 01:43:17 PM PST 23
Peak memory 205652 kb
Host smart-64e23e24-6a0b-4ab1-9208-521e51d9e674
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899585474 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.899585474
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.1115202746
Short name T641
Test name
Test status
Simulation time 162516160954 ps
CPU time 858.27 seconds
Started Dec 24 01:42:52 PM PST 23
Finished Dec 24 01:57:33 PM PST 23
Peak memory 215136 kb
Host smart-81fc69fb-ac8e-4d6a-9596-e6131c3d49fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115202746 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.1115202746
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.596924011
Short name T954
Test name
Test status
Simulation time 57929299 ps
CPU time 0.93 seconds
Started Dec 24 01:43:04 PM PST 23
Finished Dec 24 01:43:21 PM PST 23
Peak memory 205996 kb
Host smart-23ee3ad6-2a9f-4df2-afc4-d10b2eb2f701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596924011 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.596924011
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.959085104
Short name T472
Test name
Test status
Simulation time 67129893 ps
CPU time 0.87 seconds
Started Dec 24 01:43:07 PM PST 23
Finished Dec 24 01:43:22 PM PST 23
Peak memory 205088 kb
Host smart-1e554e2c-1ae1-43ee-8892-a02f743fb750
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959085104 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.959085104
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.2947717762
Short name T140
Test name
Test status
Simulation time 60429140 ps
CPU time 0.86 seconds
Started Dec 24 01:42:58 PM PST 23
Finished Dec 24 01:43:17 PM PST 23
Peak memory 214288 kb
Host smart-d8dc8414-94b3-421d-81cf-afdeadb0a1e1
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947717762 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.2947717762
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.813906899
Short name T756
Test name
Test status
Simulation time 81601056 ps
CPU time 1.02 seconds
Started Dec 24 01:42:57 PM PST 23
Finished Dec 24 01:43:17 PM PST 23
Peak memory 214480 kb
Host smart-e79e7040-8cb2-4553-8281-6eb755ed4b22
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813906899 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_di
sable_auto_req_mode.813906899
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.2401221442
Short name T781
Test name
Test status
Simulation time 78095229 ps
CPU time 0.83 seconds
Started Dec 24 01:43:01 PM PST 23
Finished Dec 24 01:43:19 PM PST 23
Peak memory 215568 kb
Host smart-2cdab4ae-75e8-4651-8095-aa7f2f6301eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401221442 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.2401221442
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.1171571899
Short name T626
Test name
Test status
Simulation time 43544856 ps
CPU time 0.98 seconds
Started Dec 24 01:43:00 PM PST 23
Finished Dec 24 01:43:19 PM PST 23
Peak memory 205168 kb
Host smart-fdf55336-541b-49ae-a773-d463351064f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171571899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.1171571899
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.612116473
Short name T731
Test name
Test status
Simulation time 20321385 ps
CPU time 1.06 seconds
Started Dec 24 01:43:01 PM PST 23
Finished Dec 24 01:43:20 PM PST 23
Peak memory 214416 kb
Host smart-0dffad7b-a750-423f-bb5d-8448e5058c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612116473 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.612116473
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.2332410276
Short name T581
Test name
Test status
Simulation time 115879770 ps
CPU time 0.9 seconds
Started Dec 24 01:42:58 PM PST 23
Finished Dec 24 01:43:17 PM PST 23
Peak memory 204920 kb
Host smart-753b5569-dd3a-42b0-a052-0fa3994936f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332410276 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.2332410276
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.3099467798
Short name T54
Test name
Test status
Simulation time 328977100 ps
CPU time 2.32 seconds
Started Dec 24 01:42:53 PM PST 23
Finished Dec 24 01:43:17 PM PST 23
Peak memory 205848 kb
Host smart-bfa7a0f5-f179-4a34-a07d-97cafd23fef1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099467798 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.3099467798
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.2711284992
Short name T630
Test name
Test status
Simulation time 45093489749 ps
CPU time 1153.8 seconds
Started Dec 24 01:43:00 PM PST 23
Finished Dec 24 02:02:32 PM PST 23
Peak memory 215788 kb
Host smart-b074e120-dd76-49b7-83e2-d66b1abad5ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711284992 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.2711284992
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.1811923452
Short name T316
Test name
Test status
Simulation time 191956948 ps
CPU time 0.98 seconds
Started Dec 24 01:43:05 PM PST 23
Finished Dec 24 01:43:21 PM PST 23
Peak memory 205012 kb
Host smart-f7514c88-d57b-44b9-8e72-03aa8bd7d3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811923452 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.1811923452
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.1168049023
Short name T968
Test name
Test status
Simulation time 59383909 ps
CPU time 0.89 seconds
Started Dec 24 01:42:59 PM PST 23
Finished Dec 24 01:43:18 PM PST 23
Peak memory 204588 kb
Host smart-8db323ea-c2ef-4601-ab2d-1ecfc1a1ab3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168049023 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.1168049023
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.32035627
Short name T877
Test name
Test status
Simulation time 57281780 ps
CPU time 0.86 seconds
Started Dec 24 01:43:04 PM PST 23
Finished Dec 24 01:43:21 PM PST 23
Peak memory 214272 kb
Host smart-22788415-1b1b-4803-86af-d138f2dd1c6b
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32035627 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.32035627
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.671479024
Short name T966
Test name
Test status
Simulation time 28621613 ps
CPU time 1.05 seconds
Started Dec 24 01:43:12 PM PST 23
Finished Dec 24 01:43:23 PM PST 23
Peak memory 214580 kb
Host smart-a46a51f9-942a-4a0a-a6c6-a8a733a1ec29
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671479024 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_di
sable_auto_req_mode.671479024
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.567647412
Short name T187
Test name
Test status
Simulation time 23279560 ps
CPU time 1.27 seconds
Started Dec 24 01:43:05 PM PST 23
Finished Dec 24 01:43:22 PM PST 23
Peak memory 215760 kb
Host smart-124bedc1-6b79-4cc4-8165-1d2020bb9196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567647412 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.567647412
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.294177798
Short name T918
Test name
Test status
Simulation time 324324659 ps
CPU time 3.07 seconds
Started Dec 24 01:42:54 PM PST 23
Finished Dec 24 01:43:19 PM PST 23
Peak memory 214168 kb
Host smart-532a9aa3-ecbf-4a6c-8b3a-21d6bba8174d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294177798 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.294177798
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.2988417999
Short name T755
Test name
Test status
Simulation time 32629521 ps
CPU time 0.97 seconds
Started Dec 24 01:42:58 PM PST 23
Finished Dec 24 01:43:17 PM PST 23
Peak memory 221604 kb
Host smart-32a07d24-ac4d-46d9-b7a4-f64240d1d161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988417999 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.2988417999
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.2472649115
Short name T488
Test name
Test status
Simulation time 40426779 ps
CPU time 0.98 seconds
Started Dec 24 01:43:05 PM PST 23
Finished Dec 24 01:43:21 PM PST 23
Peak memory 204576 kb
Host smart-63ce1f9e-0153-49d5-94e4-a7711ac74727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472649115 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.2472649115
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.1874521883
Short name T695
Test name
Test status
Simulation time 126463595 ps
CPU time 1.91 seconds
Started Dec 24 01:42:58 PM PST 23
Finished Dec 24 01:43:18 PM PST 23
Peak memory 205592 kb
Host smart-78705fb6-a6cb-4904-bdfa-00b9494aae69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874521883 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.1874521883
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.2529839162
Short name T551
Test name
Test status
Simulation time 22388891822 ps
CPU time 269.06 seconds
Started Dec 24 01:42:53 PM PST 23
Finished Dec 24 01:47:45 PM PST 23
Peak memory 215428 kb
Host smart-6ed2b61e-fe2e-4842-a22d-fa28c0c5401f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529839162 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.2529839162
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.1365508553
Short name T250
Test name
Test status
Simulation time 22749947 ps
CPU time 1 seconds
Started Dec 24 01:43:08 PM PST 23
Finished Dec 24 01:43:22 PM PST 23
Peak memory 205388 kb
Host smart-d26c07f1-feba-47e7-b704-3d2b766f033a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365508553 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.1365508553
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.2219003588
Short name T104
Test name
Test status
Simulation time 45572269 ps
CPU time 1.22 seconds
Started Dec 24 01:43:07 PM PST 23
Finished Dec 24 01:43:22 PM PST 23
Peak memory 204692 kb
Host smart-10085bb5-1ccd-4fc9-ab70-74b020a7874f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219003588 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.2219003588
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.1633964389
Short name T600
Test name
Test status
Simulation time 46581097 ps
CPU time 0.81 seconds
Started Dec 24 01:43:03 PM PST 23
Finished Dec 24 01:43:20 PM PST 23
Peak memory 214308 kb
Host smart-22511ef6-fcd0-4028-8b47-e71c160eb12d
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633964389 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.1633964389
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.548314623
Short name T482
Test name
Test status
Simulation time 78216117 ps
CPU time 0.97 seconds
Started Dec 24 01:43:08 PM PST 23
Finished Dec 24 01:43:22 PM PST 23
Peak memory 214156 kb
Host smart-a566ab78-0d92-46dd-8885-7e551f402dd0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548314623 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_di
sable_auto_req_mode.548314623
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.2101849576
Short name T550
Test name
Test status
Simulation time 21164497 ps
CPU time 1.04 seconds
Started Dec 24 01:42:59 PM PST 23
Finished Dec 24 01:43:18 PM PST 23
Peak memory 215548 kb
Host smart-02d14e81-d822-4dae-a3a0-a58cc488a13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101849576 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.2101849576
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.557662996
Short name T949
Test name
Test status
Simulation time 31425909 ps
CPU time 0.93 seconds
Started Dec 24 01:42:56 PM PST 23
Finished Dec 24 01:43:17 PM PST 23
Peak memory 204880 kb
Host smart-bb505a81-a667-4afd-b948-6fd0a3ebe83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557662996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.557662996
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.2807029632
Short name T852
Test name
Test status
Simulation time 39011935 ps
CPU time 0.89 seconds
Started Dec 24 01:43:00 PM PST 23
Finished Dec 24 01:43:19 PM PST 23
Peak memory 214108 kb
Host smart-91a91607-1f90-4855-ac31-f3fb887f7af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807029632 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.2807029632
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.4043047996
Short name T969
Test name
Test status
Simulation time 15062697 ps
CPU time 0.89 seconds
Started Dec 24 01:42:59 PM PST 23
Finished Dec 24 01:43:18 PM PST 23
Peak memory 204872 kb
Host smart-ccd91ac7-eda6-42da-8c0c-bbc407ab53e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043047996 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.4043047996
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.3020151056
Short name T632
Test name
Test status
Simulation time 109302038 ps
CPU time 2.69 seconds
Started Dec 24 01:43:24 PM PST 23
Finished Dec 24 01:43:27 PM PST 23
Peak memory 205756 kb
Host smart-f88df2f3-7579-46f2-8306-7a67d4c52953
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020151056 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3020151056
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.3063859820
Short name T617
Test name
Test status
Simulation time 40787301650 ps
CPU time 903.71 seconds
Started Dec 24 01:43:00 PM PST 23
Finished Dec 24 01:58:21 PM PST 23
Peak memory 214868 kb
Host smart-bee0f144-3179-46ad-abb2-b6793535c6cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063859820 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.3063859820
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.150453642
Short name T247
Test name
Test status
Simulation time 28657606 ps
CPU time 0.97 seconds
Started Dec 24 01:43:06 PM PST 23
Finished Dec 24 01:43:22 PM PST 23
Peak memory 205316 kb
Host smart-2095bf85-5b31-4201-807f-fdcafe2f4517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150453642 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.150453642
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.2254994635
Short name T864
Test name
Test status
Simulation time 55404211 ps
CPU time 0.89 seconds
Started Dec 24 01:42:57 PM PST 23
Finished Dec 24 01:43:17 PM PST 23
Peak memory 204716 kb
Host smart-d8e83e53-174f-4321-84c1-d00651c2e190
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254994635 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.2254994635
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.1282752802
Short name T806
Test name
Test status
Simulation time 32233008 ps
CPU time 0.79 seconds
Started Dec 24 01:43:03 PM PST 23
Finished Dec 24 01:43:20 PM PST 23
Peak memory 214308 kb
Host smart-30473a97-4fc4-4d22-8b87-b632ec059cf5
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282752802 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.1282752802
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_err.54034133
Short name T201
Test name
Test status
Simulation time 22237674 ps
CPU time 1 seconds
Started Dec 24 01:42:57 PM PST 23
Finished Dec 24 01:43:17 PM PST 23
Peak memory 221740 kb
Host smart-e21863e9-13fd-4e98-94f6-efe7564852cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54034133 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.54034133
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.2868429053
Short name T888
Test name
Test status
Simulation time 25565607 ps
CPU time 1.02 seconds
Started Dec 24 01:43:08 PM PST 23
Finished Dec 24 01:43:22 PM PST 23
Peak memory 205404 kb
Host smart-c32f2f73-345e-4199-969e-3f2e20a76c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868429053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.2868429053
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.207117357
Short name T89
Test name
Test status
Simulation time 19540317 ps
CPU time 1.01 seconds
Started Dec 24 01:43:02 PM PST 23
Finished Dec 24 01:43:20 PM PST 23
Peak memory 214572 kb
Host smart-158b4593-2e12-4d61-9286-094af47814e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207117357 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.207117357
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.2157389389
Short name T621
Test name
Test status
Simulation time 36365465 ps
CPU time 0.83 seconds
Started Dec 24 01:43:03 PM PST 23
Finished Dec 24 01:43:20 PM PST 23
Peak memory 204680 kb
Host smart-23fee16f-9313-4e7e-a2fe-f48e9c413d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157389389 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.2157389389
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.2231742677
Short name T751
Test name
Test status
Simulation time 25476932 ps
CPU time 1.08 seconds
Started Dec 24 01:43:08 PM PST 23
Finished Dec 24 01:43:22 PM PST 23
Peak memory 204824 kb
Host smart-0e4ac872-d3f0-4472-917c-9bed152be7bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231742677 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.2231742677
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.3688357850
Short name T99
Test name
Test status
Simulation time 13778531956 ps
CPU time 346.89 seconds
Started Dec 24 01:43:02 PM PST 23
Finished Dec 24 01:49:06 PM PST 23
Peak memory 215100 kb
Host smart-68a12727-864e-47a3-ad9f-7176d36ab34b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688357850 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.3688357850
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.1969956810
Short name T972
Test name
Test status
Simulation time 64755642 ps
CPU time 0.95 seconds
Started Dec 24 01:43:06 PM PST 23
Finished Dec 24 01:43:22 PM PST 23
Peak memory 205172 kb
Host smart-02befb37-a26b-4686-8597-de970c8e3b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969956810 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.1969956810
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.205541249
Short name T501
Test name
Test status
Simulation time 46516274 ps
CPU time 0.92 seconds
Started Dec 24 01:42:56 PM PST 23
Finished Dec 24 01:43:17 PM PST 23
Peak memory 204732 kb
Host smart-5fad1c42-fd75-4759-ae7a-b4130799ba73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205541249 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.205541249
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.504345906
Short name T536
Test name
Test status
Simulation time 14714189 ps
CPU time 0.9 seconds
Started Dec 24 01:43:06 PM PST 23
Finished Dec 24 01:43:22 PM PST 23
Peak memory 214516 kb
Host smart-17ef3179-5b56-4081-a3d0-f1d6daf05813
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504345906 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.504345906
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.3218005931
Short name T826
Test name
Test status
Simulation time 33935175 ps
CPU time 1.09 seconds
Started Dec 24 01:43:12 PM PST 23
Finished Dec 24 01:43:23 PM PST 23
Peak memory 214388 kb
Host smart-1ef2407e-69d0-4065-8e8b-e1db9cb6b57b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218005931 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.3218005931
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.2762372248
Short name T773
Test name
Test status
Simulation time 18351215 ps
CPU time 0.99 seconds
Started Dec 24 01:43:03 PM PST 23
Finished Dec 24 01:43:20 PM PST 23
Peak memory 215636 kb
Host smart-b6ff459d-623e-4066-b748-0dbd6b4d9e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762372248 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.2762372248
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.781198452
Short name T660
Test name
Test status
Simulation time 37014100 ps
CPU time 1.02 seconds
Started Dec 24 01:43:15 PM PST 23
Finished Dec 24 01:43:24 PM PST 23
Peak memory 213964 kb
Host smart-0db1716a-e6e1-42e7-b866-e165729e6018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781198452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.781198452
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.714566076
Short name T93
Test name
Test status
Simulation time 29134896 ps
CPU time 0.85 seconds
Started Dec 24 01:43:03 PM PST 23
Finished Dec 24 01:43:20 PM PST 23
Peak memory 214312 kb
Host smart-239441ee-1df9-40cf-81ba-e99e10a95469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714566076 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.714566076
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.3450919934
Short name T620
Test name
Test status
Simulation time 50122688 ps
CPU time 0.86 seconds
Started Dec 24 01:42:57 PM PST 23
Finished Dec 24 01:43:17 PM PST 23
Peak memory 204764 kb
Host smart-5fa7604c-d737-465b-9b13-2c9c4d0d5f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450919934 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.3450919934
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.1976100653
Short name T55
Test name
Test status
Simulation time 356875153 ps
CPU time 1.37 seconds
Started Dec 24 01:42:57 PM PST 23
Finished Dec 24 01:43:18 PM PST 23
Peak memory 205620 kb
Host smart-9fdf9683-a2fb-4c02-928a-3c4e3dd52d82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976100653 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.1976100653
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.739918412
Short name T545
Test name
Test status
Simulation time 75121044418 ps
CPU time 1873.69 seconds
Started Dec 24 01:43:09 PM PST 23
Finished Dec 24 02:14:35 PM PST 23
Peak memory 221976 kb
Host smart-d44ef2dc-23c2-4a34-86f3-da0bf9d497a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739918412 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.739918412
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.2449524122
Short name T246
Test name
Test status
Simulation time 15847007 ps
CPU time 1 seconds
Started Dec 24 01:43:11 PM PST 23
Finished Dec 24 01:43:23 PM PST 23
Peak memory 205152 kb
Host smart-40ef7849-3c82-4b65-8ba5-819165059232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449524122 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.2449524122
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.1032609344
Short name T667
Test name
Test status
Simulation time 56479892 ps
CPU time 0.88 seconds
Started Dec 24 01:42:56 PM PST 23
Finished Dec 24 01:43:17 PM PST 23
Peak memory 204644 kb
Host smart-cab9ee0e-6510-424f-b7bc-a44020e9c981
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032609344 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.1032609344
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.2203370805
Short name T116
Test name
Test status
Simulation time 23668678 ps
CPU time 0.87 seconds
Started Dec 24 01:43:12 PM PST 23
Finished Dec 24 01:43:23 PM PST 23
Peak memory 214348 kb
Host smart-c362fa28-8d1c-40ec-8909-fe7327d35c82
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203370805 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.2203370805
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.2396237743
Short name T810
Test name
Test status
Simulation time 19048030 ps
CPU time 0.94 seconds
Started Dec 24 01:43:08 PM PST 23
Finished Dec 24 01:43:22 PM PST 23
Peak memory 214196 kb
Host smart-f21785d4-c0d0-4a13-a0ec-43b47a600d58
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396237743 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.2396237743
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.24472907
Short name T48
Test name
Test status
Simulation time 29637154 ps
CPU time 1.04 seconds
Started Dec 24 01:43:23 PM PST 23
Finished Dec 24 01:43:25 PM PST 23
Peak memory 229664 kb
Host smart-7f96dbd5-cc42-4462-bc70-8240e7f06a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24472907 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.24472907
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.4034829057
Short name T558
Test name
Test status
Simulation time 17361043 ps
CPU time 1.09 seconds
Started Dec 24 01:43:05 PM PST 23
Finished Dec 24 01:43:22 PM PST 23
Peak memory 205544 kb
Host smart-8e48fa35-7d8b-40c6-be2e-4ad4a0a6b4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034829057 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.4034829057
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.3518225085
Short name T834
Test name
Test status
Simulation time 85806602 ps
CPU time 0.95 seconds
Started Dec 24 01:43:13 PM PST 23
Finished Dec 24 01:43:23 PM PST 23
Peak memory 221584 kb
Host smart-92e06248-310f-4b0a-8932-a1bea7abbb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518225085 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.3518225085
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.2680992654
Short name T454
Test name
Test status
Simulation time 14731040 ps
CPU time 0.93 seconds
Started Dec 24 01:42:55 PM PST 23
Finished Dec 24 01:43:17 PM PST 23
Peak memory 205004 kb
Host smart-e2084247-f303-4314-9395-b3fd957a8cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680992654 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.2680992654
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.2385499138
Short name T480
Test name
Test status
Simulation time 79788874 ps
CPU time 1.01 seconds
Started Dec 24 01:42:57 PM PST 23
Finished Dec 24 01:43:17 PM PST 23
Peak memory 205068 kb
Host smart-1836a3e2-293b-435e-b391-96fefb27d4d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385499138 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.2385499138
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.3413927117
Short name T766
Test name
Test status
Simulation time 284656093828 ps
CPU time 599.34 seconds
Started Dec 24 01:42:57 PM PST 23
Finished Dec 24 01:53:16 PM PST 23
Peak memory 215468 kb
Host smart-03814b6e-b432-49ef-b480-b9d0aad9794e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413927117 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.3413927117
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.163592434
Short name T312
Test name
Test status
Simulation time 18933447 ps
CPU time 1 seconds
Started Dec 24 01:43:26 PM PST 23
Finished Dec 24 01:43:29 PM PST 23
Peak memory 205088 kb
Host smart-fe568de0-fb3a-40c3-b276-e98ece94b192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163592434 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.163592434
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.2267159457
Short name T462
Test name
Test status
Simulation time 13090778 ps
CPU time 0.83 seconds
Started Dec 24 01:43:03 PM PST 23
Finished Dec 24 01:43:20 PM PST 23
Peak memory 204256 kb
Host smart-eafc2992-68f3-4a87-9b85-861a2e1a99b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267159457 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.2267159457
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.2155287777
Short name T118
Test name
Test status
Simulation time 28614473 ps
CPU time 1.34 seconds
Started Dec 24 01:42:58 PM PST 23
Finished Dec 24 01:43:18 PM PST 23
Peak memory 214604 kb
Host smart-adac4715-30fd-49bd-914d-0f2450205b86
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155287777 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.2155287777
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.958386074
Short name T179
Test name
Test status
Simulation time 23163917 ps
CPU time 1.08 seconds
Started Dec 24 01:43:22 PM PST 23
Finished Dec 24 01:43:25 PM PST 23
Peak memory 228300 kb
Host smart-6a579c1b-6aef-46ce-aaf4-f47d0e287bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958386074 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.958386074
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.1132508478
Short name T796
Test name
Test status
Simulation time 78880360 ps
CPU time 1.1 seconds
Started Dec 24 01:42:58 PM PST 23
Finished Dec 24 01:43:18 PM PST 23
Peak memory 205564 kb
Host smart-5dbe9f15-fd62-4dff-8362-f3fce21234b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132508478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1132508478
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.2927649863
Short name T765
Test name
Test status
Simulation time 37436871 ps
CPU time 0.8 seconds
Started Dec 24 01:43:07 PM PST 23
Finished Dec 24 01:43:22 PM PST 23
Peak memory 213836 kb
Host smart-ca4ae4d0-c86e-4654-9f88-697d42f25bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927649863 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2927649863
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.348201074
Short name T812
Test name
Test status
Simulation time 30195920 ps
CPU time 0.87 seconds
Started Dec 24 01:43:07 PM PST 23
Finished Dec 24 01:43:22 PM PST 23
Peak memory 204600 kb
Host smart-caf6fb42-fa67-405b-9e09-73e3cb008104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348201074 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.348201074
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.3151663663
Short name T712
Test name
Test status
Simulation time 207527088 ps
CPU time 4.41 seconds
Started Dec 24 01:42:55 PM PST 23
Finished Dec 24 01:43:21 PM PST 23
Peak memory 205956 kb
Host smart-7580ce57-1f6b-403a-b837-c4da89c53fbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151663663 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.3151663663
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.70332930
Short name T521
Test name
Test status
Simulation time 175281639940 ps
CPU time 1120.32 seconds
Started Dec 24 01:43:06 PM PST 23
Finished Dec 24 02:02:01 PM PST 23
Peak memory 217296 kb
Host smart-3ab134f6-a504-43fb-a7f7-cfddcbc50938
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70332930 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.70332930
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert_test.3829093122
Short name T718
Test name
Test status
Simulation time 45425570 ps
CPU time 0.85 seconds
Started Dec 24 01:43:50 PM PST 23
Finished Dec 24 01:43:53 PM PST 23
Peak memory 204580 kb
Host smart-fef4de12-3a8f-4179-a94b-6b9d36bcb706
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829093122 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.3829093122
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.2755419352
Short name T128
Test name
Test status
Simulation time 40806340 ps
CPU time 0.84 seconds
Started Dec 24 01:43:30 PM PST 23
Finished Dec 24 01:43:34 PM PST 23
Peak memory 214208 kb
Host smart-df5c7ee7-2400-457e-ae52-436bc4efe702
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755419352 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.2755419352
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.339366835
Short name T499
Test name
Test status
Simulation time 54834140 ps
CPU time 1.14 seconds
Started Dec 24 01:43:32 PM PST 23
Finished Dec 24 01:43:38 PM PST 23
Peak memory 214544 kb
Host smart-d09796a5-1943-4624-8fcb-786384f10272
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339366835 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_di
sable_auto_req_mode.339366835
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.676572749
Short name T948
Test name
Test status
Simulation time 19521595 ps
CPU time 1.12 seconds
Started Dec 24 01:43:35 PM PST 23
Finished Dec 24 01:43:42 PM PST 23
Peak memory 214588 kb
Host smart-aa7884e5-9ab4-4b7c-8cbe-46b63ce0cb58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676572749 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.676572749
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.1375604063
Short name T286
Test name
Test status
Simulation time 48446200 ps
CPU time 0.96 seconds
Started Dec 24 01:42:57 PM PST 23
Finished Dec 24 01:43:17 PM PST 23
Peak memory 205688 kb
Host smart-58c8de57-c625-4276-82f6-baddee38b302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375604063 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.1375604063
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.1112802348
Short name T955
Test name
Test status
Simulation time 22146013 ps
CPU time 0.91 seconds
Started Dec 24 01:43:32 PM PST 23
Finished Dec 24 01:43:39 PM PST 23
Peak memory 214552 kb
Host smart-63c55dc5-70da-4a3e-bc3f-67472c2a2857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112802348 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1112802348
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.2878496322
Short name T496
Test name
Test status
Simulation time 42185446 ps
CPU time 0.94 seconds
Started Dec 24 01:43:43 PM PST 23
Finished Dec 24 01:43:45 PM PST 23
Peak memory 203488 kb
Host smart-93cf1c9b-d280-4821-b8c2-458fb5109139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878496322 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.2878496322
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.493355531
Short name T495
Test name
Test status
Simulation time 667880082 ps
CPU time 3.86 seconds
Started Dec 24 01:42:58 PM PST 23
Finished Dec 24 01:43:20 PM PST 23
Peak memory 205860 kb
Host smart-4de23ee9-cbfe-4276-91cc-946bf59782c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493355531 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.493355531
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_alert.1650015376
Short name T889
Test name
Test status
Simulation time 65158722 ps
CPU time 0.97 seconds
Started Dec 24 01:43:39 PM PST 23
Finished Dec 24 01:43:44 PM PST 23
Peak memory 205072 kb
Host smart-4cc5699f-287a-48f0-9fdd-f4df169937c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650015376 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.1650015376
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.1103371010
Short name T603
Test name
Test status
Simulation time 13686126 ps
CPU time 0.88 seconds
Started Dec 24 01:43:51 PM PST 23
Finished Dec 24 01:43:55 PM PST 23
Peak memory 204556 kb
Host smart-637422c4-a20f-4b1d-a0b7-b9f68edf0711
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103371010 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.1103371010
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.2212817326
Short name T127
Test name
Test status
Simulation time 20908167 ps
CPU time 0.95 seconds
Started Dec 24 01:43:43 PM PST 23
Finished Dec 24 01:43:45 PM PST 23
Peak memory 213164 kb
Host smart-30984cf6-436d-4f40-bd92-d4313a4927d9
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212817326 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2212817326
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.2413953919
Short name T185
Test name
Test status
Simulation time 30568978 ps
CPU time 0.92 seconds
Started Dec 24 01:43:30 PM PST 23
Finished Dec 24 01:43:34 PM PST 23
Peak memory 214448 kb
Host smart-9044843e-bb7e-479a-ba5e-ab24e80fcfe3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413953919 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.2413953919
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.3503845244
Short name T793
Test name
Test status
Simulation time 33129236 ps
CPU time 1.01 seconds
Started Dec 24 01:43:31 PM PST 23
Finished Dec 24 01:43:34 PM PST 23
Peak memory 215928 kb
Host smart-ef1de160-ee5e-4cef-99c2-a66f6a5344c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503845244 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.3503845244
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.3177608112
Short name T604
Test name
Test status
Simulation time 53297147 ps
CPU time 0.9 seconds
Started Dec 24 01:43:29 PM PST 23
Finished Dec 24 01:43:33 PM PST 23
Peak memory 204888 kb
Host smart-428d618f-551b-4e87-b3cd-d2da15334232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177608112 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.3177608112
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.1127185833
Short name T60
Test name
Test status
Simulation time 21235249 ps
CPU time 1.1 seconds
Started Dec 24 01:43:43 PM PST 23
Finished Dec 24 01:43:45 PM PST 23
Peak memory 213388 kb
Host smart-d2221439-1677-4582-9a65-1a86916681bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127185833 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.1127185833
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.1496430377
Short name T612
Test name
Test status
Simulation time 120676008 ps
CPU time 0.9 seconds
Started Dec 24 01:43:33 PM PST 23
Finished Dec 24 01:43:40 PM PST 23
Peak memory 204668 kb
Host smart-f9eaabd1-b37c-4d0a-bc62-dda621aa400f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496430377 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.1496430377
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.3609863206
Short name T894
Test name
Test status
Simulation time 301503140 ps
CPU time 3.37 seconds
Started Dec 24 01:43:27 PM PST 23
Finished Dec 24 01:43:31 PM PST 23
Peak memory 205920 kb
Host smart-d11e3570-1ec6-424a-ab8b-c1a5e14c9082
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609863206 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.3609863206
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.1346556538
Short name T298
Test name
Test status
Simulation time 17734863971 ps
CPU time 429.69 seconds
Started Dec 24 01:43:28 PM PST 23
Finished Dec 24 01:50:39 PM PST 23
Peak memory 216016 kb
Host smart-7c3cbdcb-e04d-4093-a1cb-4d53938deceb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346556538 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.1346556538
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.1935855889
Short name T798
Test name
Test status
Simulation time 62546622 ps
CPU time 0.97 seconds
Started Dec 24 01:42:16 PM PST 23
Finished Dec 24 01:42:20 PM PST 23
Peak memory 205844 kb
Host smart-3847cfdf-1b80-4c8c-a30e-cc4f7ed8ec00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935855889 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.1935855889
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.2418827213
Short name T509
Test name
Test status
Simulation time 19258543 ps
CPU time 0.85 seconds
Started Dec 24 01:42:44 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 204496 kb
Host smart-d8dd1ec3-dd0d-4b72-907a-947696609268
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418827213 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.2418827213
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.3969926061
Short name T747
Test name
Test status
Simulation time 13384745 ps
CPU time 0.92 seconds
Started Dec 24 01:42:42 PM PST 23
Finished Dec 24 01:42:54 PM PST 23
Peak memory 214536 kb
Host smart-2cb23cc1-7e87-41ff-a6d2-7f5078652af2
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969926061 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.3969926061
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.3102401539
Short name T838
Test name
Test status
Simulation time 29751191 ps
CPU time 1.2 seconds
Started Dec 24 01:42:43 PM PST 23
Finished Dec 24 01:43:02 PM PST 23
Peak memory 214556 kb
Host smart-e71265fd-2c37-4ddc-99dc-b1d0b5ef3710
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102401539 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.3102401539
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.2421570796
Short name T873
Test name
Test status
Simulation time 42162812 ps
CPU time 1.21 seconds
Started Dec 24 01:42:18 PM PST 23
Finished Dec 24 01:42:21 PM PST 23
Peak memory 227332 kb
Host smart-6b4f5fd5-cde8-4ffb-ae53-27b3adba3dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421570796 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.2421570796
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.1666129778
Short name T678
Test name
Test status
Simulation time 237000866 ps
CPU time 1.04 seconds
Started Dec 24 01:42:17 PM PST 23
Finished Dec 24 01:42:21 PM PST 23
Peak memory 205344 kb
Host smart-ead29147-a5a5-4e12-adce-a34dc719823e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666129778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1666129778
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.2770906285
Short name T42
Test name
Test status
Simulation time 35547305 ps
CPU time 0.98 seconds
Started Dec 24 01:42:41 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 221652 kb
Host smart-16890bc1-8769-4966-b955-e6ca0c36dcaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770906285 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.2770906285
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_sec_cm.60789053
Short name T23
Test name
Test status
Simulation time 324144042 ps
CPU time 5.78 seconds
Started Dec 24 01:41:57 PM PST 23
Finished Dec 24 01:42:09 PM PST 23
Peak memory 234568 kb
Host smart-ec9082a0-ac51-4a0e-8a6a-9558520ecaa9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60789053 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.60789053
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.3537376635
Short name T580
Test name
Test status
Simulation time 116042388 ps
CPU time 0.85 seconds
Started Dec 24 01:42:23 PM PST 23
Finished Dec 24 01:42:25 PM PST 23
Peak memory 204228 kb
Host smart-561018d9-72f0-4b54-821b-3c2624fe69f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537376635 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3537376635
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.51736612
Short name T572
Test name
Test status
Simulation time 342906021 ps
CPU time 3.71 seconds
Started Dec 24 01:42:44 PM PST 23
Finished Dec 24 01:43:08 PM PST 23
Peak memory 205804 kb
Host smart-2f5ceaf8-8095-4e85-863a-0facdc9c829e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51736612 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.51736612
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.3740195314
Short name T593
Test name
Test status
Simulation time 45734396329 ps
CPU time 926.14 seconds
Started Dec 24 01:42:16 PM PST 23
Finished Dec 24 01:57:44 PM PST 23
Peak memory 215592 kb
Host smart-0cc2ced5-b960-40f5-9454-39fb8c2a3eab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740195314 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.3740195314
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.2374193274
Short name T315
Test name
Test status
Simulation time 59557169 ps
CPU time 0.94 seconds
Started Dec 24 01:43:28 PM PST 23
Finished Dec 24 01:43:30 PM PST 23
Peak memory 205876 kb
Host smart-44bf9901-13e7-414a-af3d-8324cad7dce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374193274 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.2374193274
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.786347251
Short name T469
Test name
Test status
Simulation time 39129792 ps
CPU time 0.91 seconds
Started Dec 24 01:43:50 PM PST 23
Finished Dec 24 01:43:53 PM PST 23
Peak memory 204520 kb
Host smart-3604d852-65b7-417a-ac15-b1f57e329a74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786347251 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.786347251
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.1272617960
Short name T202
Test name
Test status
Simulation time 27435842 ps
CPU time 0.78 seconds
Started Dec 24 01:43:34 PM PST 23
Finished Dec 24 01:43:42 PM PST 23
Peak memory 214312 kb
Host smart-37abd43e-8cd7-4be0-a90e-1d51f5acaf94
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272617960 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.1272617960
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.582291605
Short name T952
Test name
Test status
Simulation time 24162132 ps
CPU time 1 seconds
Started Dec 24 01:43:31 PM PST 23
Finished Dec 24 01:43:35 PM PST 23
Peak memory 215588 kb
Host smart-cb9b84c1-2cfa-4361-bd9f-e7ed018659d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582291605 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_di
sable_auto_req_mode.582291605
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_genbits.390597421
Short name T848
Test name
Test status
Simulation time 139906849 ps
CPU time 1.85 seconds
Started Dec 24 01:43:30 PM PST 23
Finished Dec 24 01:43:34 PM PST 23
Peak memory 214108 kb
Host smart-b47112df-add8-49cf-9ef0-0f50da75084d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390597421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.390597421
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_smoke.2493606026
Short name T492
Test name
Test status
Simulation time 41172238 ps
CPU time 0.8 seconds
Started Dec 24 01:43:29 PM PST 23
Finished Dec 24 01:43:33 PM PST 23
Peak memory 204784 kb
Host smart-0e78e48b-48dd-4e97-a4f5-8d365a915d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493606026 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.2493606026
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.287697836
Short name T648
Test name
Test status
Simulation time 51950952 ps
CPU time 0.99 seconds
Started Dec 24 01:43:53 PM PST 23
Finished Dec 24 01:43:57 PM PST 23
Peak memory 204920 kb
Host smart-0a515df6-b777-4fb7-be4c-d97ec9982694
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287697836 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.287697836
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_alert.1666481125
Short name T76
Test name
Test status
Simulation time 132493862 ps
CPU time 0.99 seconds
Started Dec 24 01:43:31 PM PST 23
Finished Dec 24 01:43:34 PM PST 23
Peak memory 205976 kb
Host smart-7e1d4b4b-a195-4cf7-8afe-d02b5647c46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666481125 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.1666481125
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.1450704608
Short name T3
Test name
Test status
Simulation time 17466243 ps
CPU time 0.9 seconds
Started Dec 24 01:43:40 PM PST 23
Finished Dec 24 01:43:45 PM PST 23
Peak memory 205172 kb
Host smart-4bcdeb0e-c2d4-4f76-b640-d24007699f7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450704608 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.1450704608
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.3482295416
Short name T835
Test name
Test status
Simulation time 11764304 ps
CPU time 0.89 seconds
Started Dec 24 01:43:31 PM PST 23
Finished Dec 24 01:43:34 PM PST 23
Peak memory 214408 kb
Host smart-23ee0f25-7cd3-4c1d-88ca-de424ddba7a5
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482295416 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.3482295416
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.2168584506
Short name T745
Test name
Test status
Simulation time 17684498 ps
CPU time 1.02 seconds
Started Dec 24 01:43:43 PM PST 23
Finished Dec 24 01:43:45 PM PST 23
Peak memory 214232 kb
Host smart-d176c174-2c0f-4255-8ba1-56eda7d2abfe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168584506 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.2168584506
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.1131573576
Short name T518
Test name
Test status
Simulation time 54385007 ps
CPU time 0.91 seconds
Started Dec 24 01:43:33 PM PST 23
Finished Dec 24 01:43:39 PM PST 23
Peak memory 215496 kb
Host smart-90c40d98-2831-4231-a928-79ae3e12cae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131573576 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.1131573576
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.1012548729
Short name T913
Test name
Test status
Simulation time 56760691 ps
CPU time 1.74 seconds
Started Dec 24 01:43:35 PM PST 23
Finished Dec 24 01:43:43 PM PST 23
Peak memory 214196 kb
Host smart-0f957a7a-b83d-40f4-b3f3-94bf43a53fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012548729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.1012548729
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.2403969750
Short name T782
Test name
Test status
Simulation time 27983206 ps
CPU time 0.91 seconds
Started Dec 24 01:43:36 PM PST 23
Finished Dec 24 01:43:42 PM PST 23
Peak memory 214224 kb
Host smart-88e0e5ad-f72e-4ee1-b94a-00043a21fe6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403969750 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.2403969750
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.2811213032
Short name T814
Test name
Test status
Simulation time 15712042 ps
CPU time 0.85 seconds
Started Dec 24 01:43:30 PM PST 23
Finished Dec 24 01:43:33 PM PST 23
Peak memory 204604 kb
Host smart-cb2632bc-c7bc-46a6-8e45-c9ebc9a2c459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811213032 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.2811213032
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.3069125142
Short name T100
Test name
Test status
Simulation time 635908212 ps
CPU time 4.05 seconds
Started Dec 24 01:43:43 PM PST 23
Finished Dec 24 01:43:48 PM PST 23
Peak memory 205780 kb
Host smart-b8af70af-2a0c-464a-8775-dade117d13ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069125142 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.3069125142
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.3238998512
Short name T859
Test name
Test status
Simulation time 85924882862 ps
CPU time 533.29 seconds
Started Dec 24 01:43:27 PM PST 23
Finished Dec 24 01:52:21 PM PST 23
Peak memory 214612 kb
Host smart-f0a73f95-c303-4a1e-9ffe-d5af3644224a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238998512 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.3238998512
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.1595158342
Short name T729
Test name
Test status
Simulation time 21189424 ps
CPU time 1.06 seconds
Started Dec 24 01:43:38 PM PST 23
Finished Dec 24 01:43:42 PM PST 23
Peak memory 205956 kb
Host smart-22da1b22-66d8-475d-8dd8-7f81d1788cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595158342 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.1595158342
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.417821059
Short name T807
Test name
Test status
Simulation time 50855597 ps
CPU time 0.91 seconds
Started Dec 24 01:43:43 PM PST 23
Finished Dec 24 01:43:45 PM PST 23
Peak memory 204344 kb
Host smart-4ea46652-0279-4bf6-b2b4-2fd0ba4f96f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417821059 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.417821059
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.2479983043
Short name T81
Test name
Test status
Simulation time 15364157 ps
CPU time 0.87 seconds
Started Dec 24 01:43:31 PM PST 23
Finished Dec 24 01:43:34 PM PST 23
Peak memory 214492 kb
Host smart-9acd92d0-6c95-483b-a2be-8b291fffdb12
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479983043 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.2479983043
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.2598966606
Short name T853
Test name
Test status
Simulation time 41894564 ps
CPU time 1 seconds
Started Dec 24 01:43:31 PM PST 23
Finished Dec 24 01:43:34 PM PST 23
Peak memory 214540 kb
Host smart-2e0372d6-2909-4c1b-ad3b-eee61354d125
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598966606 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.2598966606
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.455304397
Short name T208
Test name
Test status
Simulation time 19525339 ps
CPU time 1.13 seconds
Started Dec 24 01:43:52 PM PST 23
Finished Dec 24 01:43:55 PM PST 23
Peak memory 221704 kb
Host smart-4180f227-ae3c-499e-998c-18228de8bbe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455304397 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.455304397
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.279217031
Short name T947
Test name
Test status
Simulation time 72404087 ps
CPU time 1.03 seconds
Started Dec 24 01:43:43 PM PST 23
Finished Dec 24 01:43:45 PM PST 23
Peak memory 203748 kb
Host smart-8ac3c22b-2373-40ba-a6a5-4d608ac82dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279217031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.279217031
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.1168715655
Short name T539
Test name
Test status
Simulation time 18993001 ps
CPU time 1.09 seconds
Started Dec 24 01:43:49 PM PST 23
Finished Dec 24 01:43:52 PM PST 23
Peak memory 214308 kb
Host smart-02b56a26-14f3-4162-abc9-84075a74eddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168715655 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.1168715655
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.3174527043
Short name T763
Test name
Test status
Simulation time 32290633 ps
CPU time 0.84 seconds
Started Dec 24 01:43:28 PM PST 23
Finished Dec 24 01:43:30 PM PST 23
Peak memory 204984 kb
Host smart-9da584ac-e115-4858-b3bb-5272106d77de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174527043 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.3174527043
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.1269823746
Short name T487
Test name
Test status
Simulation time 244609672 ps
CPU time 3.31 seconds
Started Dec 24 01:43:26 PM PST 23
Finished Dec 24 01:43:30 PM PST 23
Peak memory 214244 kb
Host smart-4cff7ecb-8dd1-4996-9ba5-eb0092d2a1db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269823746 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.1269823746
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.2109519051
Short name T901
Test name
Test status
Simulation time 28489943219 ps
CPU time 348.15 seconds
Started Dec 24 01:43:32 PM PST 23
Finished Dec 24 01:49:25 PM PST 23
Peak memory 215256 kb
Host smart-57d3c0aa-be83-46db-ba67-87d638230855
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109519051 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.2109519051
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.1721021602
Short name T328
Test name
Test status
Simulation time 68522683 ps
CPU time 0.98 seconds
Started Dec 24 01:43:50 PM PST 23
Finished Dec 24 01:43:52 PM PST 23
Peak memory 205136 kb
Host smart-9d65b4b7-d89d-43cd-bf30-1f1afdb553bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721021602 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.1721021602
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.3243203221
Short name T770
Test name
Test status
Simulation time 16325569 ps
CPU time 1.02 seconds
Started Dec 24 01:43:31 PM PST 23
Finished Dec 24 01:43:35 PM PST 23
Peak memory 204612 kb
Host smart-8e94cb30-2a52-4b1d-88a2-a36240753c93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243203221 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.3243203221
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.1761830738
Short name T30
Test name
Test status
Simulation time 13626289 ps
CPU time 0.89 seconds
Started Dec 24 01:43:28 PM PST 23
Finished Dec 24 01:43:30 PM PST 23
Peak memory 214440 kb
Host smart-7503c4aa-9531-4ed7-a216-3c6edb1bcf89
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761830738 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.1761830738
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.1623147119
Short name T106
Test name
Test status
Simulation time 24188565 ps
CPU time 1 seconds
Started Dec 24 01:43:59 PM PST 23
Finished Dec 24 01:44:03 PM PST 23
Peak memory 214476 kb
Host smart-50d8ee7a-3b7e-4768-bc71-91dbac9f9127
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623147119 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.1623147119
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.8031161
Short name T570
Test name
Test status
Simulation time 19981276 ps
CPU time 1.31 seconds
Started Dec 24 01:43:29 PM PST 23
Finished Dec 24 01:43:32 PM PST 23
Peak memory 221636 kb
Host smart-48b27ceb-3411-4fc8-836b-ff2095d9943e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8031161 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.8031161
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.3175736808
Short name T933
Test name
Test status
Simulation time 28064003 ps
CPU time 0.88 seconds
Started Dec 24 01:43:32 PM PST 23
Finished Dec 24 01:43:39 PM PST 23
Peak memory 205016 kb
Host smart-3f774091-92af-495c-8673-40e58434d3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175736808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.3175736808
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.3207695277
Short name T564
Test name
Test status
Simulation time 21798322 ps
CPU time 0.97 seconds
Started Dec 24 01:43:59 PM PST 23
Finished Dec 24 01:44:02 PM PST 23
Peak memory 214448 kb
Host smart-dae301d2-f629-4f94-bb69-03f0f8fa77bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207695277 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.3207695277
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.2604133016
Short name T653
Test name
Test status
Simulation time 39779943 ps
CPU time 0.86 seconds
Started Dec 24 01:43:29 PM PST 23
Finished Dec 24 01:43:32 PM PST 23
Peak memory 204584 kb
Host smart-e05ae516-da2d-4cc9-81a3-cc77434636cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604133016 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.2604133016
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.3186730083
Short name T71
Test name
Test status
Simulation time 44805882 ps
CPU time 1.42 seconds
Started Dec 24 01:43:31 PM PST 23
Finished Dec 24 01:43:35 PM PST 23
Peak memory 205292 kb
Host smart-fce9bcf9-8426-4a30-bc17-c792edeebd3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186730083 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.3186730083
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.708229507
Short name T643
Test name
Test status
Simulation time 47881608633 ps
CPU time 1077.59 seconds
Started Dec 24 01:43:34 PM PST 23
Finished Dec 24 02:01:38 PM PST 23
Peak memory 215532 kb
Host smart-cab951a1-cbb2-4ddc-bd32-601112da0dd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708229507 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.708229507
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.251566278
Short name T311
Test name
Test status
Simulation time 18923740 ps
CPU time 0.99 seconds
Started Dec 24 01:44:01 PM PST 23
Finished Dec 24 01:44:08 PM PST 23
Peak memory 205920 kb
Host smart-f389c0f0-542d-41ca-8084-1ac10f35e51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251566278 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.251566278
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.793489853
Short name T470
Test name
Test status
Simulation time 44716194 ps
CPU time 0.82 seconds
Started Dec 24 01:44:01 PM PST 23
Finished Dec 24 01:44:08 PM PST 23
Peak memory 204364 kb
Host smart-14af2275-72bd-43c6-9e5f-96e35fa3629d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793489853 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.793489853
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.1171551145
Short name T145
Test name
Test status
Simulation time 13255859 ps
CPU time 0.85 seconds
Started Dec 24 01:43:50 PM PST 23
Finished Dec 24 01:43:52 PM PST 23
Peak memory 214364 kb
Host smart-a3f4f865-4422-43ad-9a67-8c694e1639f2
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171551145 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.1171551145
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.1248654565
Short name T196
Test name
Test status
Simulation time 58465820 ps
CPU time 0.98 seconds
Started Dec 24 01:43:58 PM PST 23
Finished Dec 24 01:44:00 PM PST 23
Peak memory 214448 kb
Host smart-b151e031-0039-4642-93ed-fc8ee30e3892
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248654565 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.1248654565
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.490043880
Short name T753
Test name
Test status
Simulation time 18989641 ps
CPU time 1.05 seconds
Started Dec 24 01:43:59 PM PST 23
Finished Dec 24 01:44:03 PM PST 23
Peak memory 215988 kb
Host smart-ad6a0bb4-2465-4b19-b57b-556b6f9b7048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490043880 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.490043880
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.2914915350
Short name T820
Test name
Test status
Simulation time 35266227 ps
CPU time 1.15 seconds
Started Dec 24 01:43:53 PM PST 23
Finished Dec 24 01:43:57 PM PST 23
Peak memory 214156 kb
Host smart-70f04447-dbaf-4ef5-8838-703f556daac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914915350 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.2914915350
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.3813960055
Short name T498
Test name
Test status
Simulation time 19290795 ps
CPU time 1.06 seconds
Started Dec 24 01:43:49 PM PST 23
Finished Dec 24 01:43:52 PM PST 23
Peak memory 214268 kb
Host smart-15ce550b-31a1-453b-b3bb-4169f423e932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813960055 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.3813960055
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.2976826934
Short name T524
Test name
Test status
Simulation time 25830524 ps
CPU time 0.86 seconds
Started Dec 24 01:43:51 PM PST 23
Finished Dec 24 01:43:54 PM PST 23
Peak memory 204732 kb
Host smart-c96fbc0b-4d17-4440-9f04-4bfbf5d50737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976826934 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.2976826934
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.1137631079
Short name T296
Test name
Test status
Simulation time 106740305 ps
CPU time 2.72 seconds
Started Dec 24 01:44:00 PM PST 23
Finished Dec 24 01:44:08 PM PST 23
Peak memory 205916 kb
Host smart-f22146e5-def3-4a27-afdb-dd3c4868664c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137631079 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1137631079
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.2083110406
Short name T777
Test name
Test status
Simulation time 110967848529 ps
CPU time 1384.24 seconds
Started Dec 24 01:44:03 PM PST 23
Finished Dec 24 02:07:16 PM PST 23
Peak memory 219544 kb
Host smart-ddf28e1a-50f7-4b66-a662-cb16fea31558
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083110406 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.2083110406
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.3541807292
Short name T912
Test name
Test status
Simulation time 20800907 ps
CPU time 0.99 seconds
Started Dec 24 01:44:01 PM PST 23
Finished Dec 24 01:44:08 PM PST 23
Peak memory 205568 kb
Host smart-4c3575e9-3d66-4155-8b1b-968e7eff6edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541807292 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.3541807292
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.3982689529
Short name T914
Test name
Test status
Simulation time 24234926 ps
CPU time 0.97 seconds
Started Dec 24 01:43:58 PM PST 23
Finished Dec 24 01:44:00 PM PST 23
Peak memory 204544 kb
Host smart-e1498fd0-e806-49f3-9da6-4a262777a8a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982689529 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3982689529
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.4090741649
Short name T926
Test name
Test status
Simulation time 60660893 ps
CPU time 0.92 seconds
Started Dec 24 01:44:01 PM PST 23
Finished Dec 24 01:44:08 PM PST 23
Peak memory 214508 kb
Host smart-848b344c-ead9-4094-b27b-21d0433993a3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090741649 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.4090741649
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.599057745
Short name T872
Test name
Test status
Simulation time 32263104 ps
CPU time 0.94 seconds
Started Dec 24 01:44:02 PM PST 23
Finished Dec 24 01:44:10 PM PST 23
Peak memory 221588 kb
Host smart-1efeb0c9-0d16-46d1-b7b0-e6d7e7783ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599057745 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.599057745
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.1143613679
Short name T12
Test name
Test status
Simulation time 60818913 ps
CPU time 1.02 seconds
Started Dec 24 01:43:59 PM PST 23
Finished Dec 24 01:44:04 PM PST 23
Peak memory 214052 kb
Host smart-07a308dd-9458-4148-9545-e1d8bb157bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143613679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.1143613679
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.2102509873
Short name T690
Test name
Test status
Simulation time 27240603 ps
CPU time 0.9 seconds
Started Dec 24 01:43:59 PM PST 23
Finished Dec 24 01:44:04 PM PST 23
Peak memory 214312 kb
Host smart-dc47dad9-a225-42d2-9850-56f4f488e6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102509873 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.2102509873
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.1246444007
Short name T911
Test name
Test status
Simulation time 13741009 ps
CPU time 0.92 seconds
Started Dec 24 01:44:01 PM PST 23
Finished Dec 24 01:44:08 PM PST 23
Peak memory 204668 kb
Host smart-18bffe50-6797-4d4d-b7b2-d76837ee3215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246444007 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.1246444007
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.2355837644
Short name T697
Test name
Test status
Simulation time 283538656 ps
CPU time 3.49 seconds
Started Dec 24 01:43:59 PM PST 23
Finished Dec 24 01:44:05 PM PST 23
Peak memory 206032 kb
Host smart-c99a5440-333d-454e-93a9-3589224d3188
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355837644 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.2355837644
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.1965055513
Short name T97
Test name
Test status
Simulation time 123115180075 ps
CPU time 1318.51 seconds
Started Dec 24 01:43:59 PM PST 23
Finished Dec 24 02:06:01 PM PST 23
Peak memory 216276 kb
Host smart-11660bd8-7e00-4fe3-9e55-f61bd09d3f90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965055513 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.1965055513
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.3095822679
Short name T850
Test name
Test status
Simulation time 62912244 ps
CPU time 0.94 seconds
Started Dec 24 01:44:06 PM PST 23
Finished Dec 24 01:44:25 PM PST 23
Peak memory 205920 kb
Host smart-31fbe860-90ee-4920-99e1-5c19d131d774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095822679 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.3095822679
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.1631014474
Short name T594
Test name
Test status
Simulation time 71799389 ps
CPU time 0.99 seconds
Started Dec 24 01:43:59 PM PST 23
Finished Dec 24 01:44:04 PM PST 23
Peak memory 204632 kb
Host smart-ef03139b-9d94-47e0-9959-51d49d2426bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631014474 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.1631014474
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.3981972985
Short name T811
Test name
Test status
Simulation time 110987029 ps
CPU time 0.99 seconds
Started Dec 24 01:43:59 PM PST 23
Finished Dec 24 01:44:02 PM PST 23
Peak memory 214604 kb
Host smart-f4fbbaca-621a-4361-abc2-ccf02f8483d2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981972985 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.3981972985
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.2152734638
Short name T184
Test name
Test status
Simulation time 60247139 ps
CPU time 1.07 seconds
Started Dec 24 01:44:02 PM PST 23
Finished Dec 24 01:44:10 PM PST 23
Peak memory 228464 kb
Host smart-831fce8f-6565-4b8d-a727-448e32f2f524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152734638 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.2152734638
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.571105361
Short name T62
Test name
Test status
Simulation time 58999275 ps
CPU time 1.25 seconds
Started Dec 24 01:43:50 PM PST 23
Finished Dec 24 01:43:54 PM PST 23
Peak memory 214168 kb
Host smart-6abd984d-74dd-4a0c-8e85-de17825661c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571105361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.571105361
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.3335265509
Short name T548
Test name
Test status
Simulation time 25101072 ps
CPU time 0.92 seconds
Started Dec 24 01:43:52 PM PST 23
Finished Dec 24 01:43:56 PM PST 23
Peak memory 214328 kb
Host smart-6d91b977-4da8-4214-a16a-2cfc8255ecaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335265509 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.3335265509
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.3261830861
Short name T646
Test name
Test status
Simulation time 32785094 ps
CPU time 0.86 seconds
Started Dec 24 01:44:00 PM PST 23
Finished Dec 24 01:44:06 PM PST 23
Peak memory 204816 kb
Host smart-ddc77861-13dd-4839-99c5-387f1f4c6fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261830861 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.3261830861
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.1263348135
Short name T299
Test name
Test status
Simulation time 179906192985 ps
CPU time 1581 seconds
Started Dec 24 01:43:52 PM PST 23
Finished Dec 24 02:10:15 PM PST 23
Peak memory 217540 kb
Host smart-6d45aa64-ab0c-4bdc-bef6-99f3213a15e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263348135 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.1263348135
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.2459294544
Short name T730
Test name
Test status
Simulation time 30429856 ps
CPU time 0.92 seconds
Started Dec 24 01:43:59 PM PST 23
Finished Dec 24 01:44:04 PM PST 23
Peak memory 205868 kb
Host smart-d86c25f6-1d62-44af-b1c2-b676898e7077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459294544 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2459294544
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.3493511735
Short name T808
Test name
Test status
Simulation time 31347506 ps
CPU time 0.91 seconds
Started Dec 24 01:44:00 PM PST 23
Finished Dec 24 01:44:06 PM PST 23
Peak memory 204544 kb
Host smart-991bf271-e688-4a3c-8f38-ed2d44317386
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493511735 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.3493511735
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.1753041080
Short name T212
Test name
Test status
Simulation time 11774636 ps
CPU time 0.84 seconds
Started Dec 24 01:43:59 PM PST 23
Finished Dec 24 01:44:03 PM PST 23
Peak memory 214228 kb
Host smart-9b4215a2-6e0f-4a2b-8bc0-2efa3d7e30b0
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753041080 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.1753041080
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.565791617
Short name T181
Test name
Test status
Simulation time 25915688 ps
CPU time 1.02 seconds
Started Dec 24 01:44:01 PM PST 23
Finished Dec 24 01:44:08 PM PST 23
Peak memory 214568 kb
Host smart-8f813be3-3e21-4c66-91ea-514d9b242ae3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565791617 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_di
sable_auto_req_mode.565791617
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.2860959291
Short name T192
Test name
Test status
Simulation time 31115421 ps
CPU time 0.99 seconds
Started Dec 24 01:43:58 PM PST 23
Finished Dec 24 01:44:00 PM PST 23
Peak memory 214796 kb
Host smart-b9164b9c-8e72-4cda-b311-eada13485487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860959291 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.2860959291
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.1052529585
Short name T532
Test name
Test status
Simulation time 30267127 ps
CPU time 1.09 seconds
Started Dec 24 01:43:51 PM PST 23
Finished Dec 24 01:43:55 PM PST 23
Peak memory 214184 kb
Host smart-778cf8f5-6102-4510-8bb8-9868f827b1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052529585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.1052529585
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.1644024396
Short name T869
Test name
Test status
Simulation time 30871867 ps
CPU time 0.88 seconds
Started Dec 24 01:43:57 PM PST 23
Finished Dec 24 01:43:59 PM PST 23
Peak memory 214296 kb
Host smart-b20235f5-261d-4d3d-b680-d81aff56cf31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644024396 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1644024396
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.2772134974
Short name T483
Test name
Test status
Simulation time 26426215 ps
CPU time 0.87 seconds
Started Dec 24 01:43:51 PM PST 23
Finished Dec 24 01:43:54 PM PST 23
Peak memory 204680 kb
Host smart-d5f3a8c5-e79a-460d-9ce0-329a431d5dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772134974 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.2772134974
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.2388896548
Short name T904
Test name
Test status
Simulation time 576394010 ps
CPU time 4.17 seconds
Started Dec 24 01:43:49 PM PST 23
Finished Dec 24 01:43:54 PM PST 23
Peak memory 205736 kb
Host smart-2ab4ab78-42af-4fe0-864a-5e7519bb23d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388896548 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.2388896548
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.4107516819
Short name T762
Test name
Test status
Simulation time 23501136142 ps
CPU time 514.31 seconds
Started Dec 24 01:44:00 PM PST 23
Finished Dec 24 01:52:39 PM PST 23
Peak memory 215840 kb
Host smart-357aac8c-6953-4f42-ae04-9343b5d356e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107516819 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.4107516819
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.2937745225
Short name T319
Test name
Test status
Simulation time 61064988 ps
CPU time 0.96 seconds
Started Dec 24 01:44:02 PM PST 23
Finished Dec 24 01:44:10 PM PST 23
Peak memory 205864 kb
Host smart-5a3ac6ed-9a5f-4ac5-80ff-301bd8a5ab51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937745225 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.2937745225
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.3179115425
Short name T822
Test name
Test status
Simulation time 26062967 ps
CPU time 0.85 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:18 PM PST 23
Peak memory 204556 kb
Host smart-cf239bed-3a6c-4b2a-8fa1-1d864eaed02b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179115425 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.3179115425
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.3466377676
Short name T211
Test name
Test status
Simulation time 21740077 ps
CPU time 0.85 seconds
Started Dec 24 01:44:05 PM PST 23
Finished Dec 24 01:44:20 PM PST 23
Peak memory 214316 kb
Host smart-8ee2a57c-61fa-4ce4-adc7-9a71d6c9bf1f
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466377676 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.3466377676
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.451933839
Short name T115
Test name
Test status
Simulation time 19926173 ps
CPU time 1 seconds
Started Dec 24 01:44:12 PM PST 23
Finished Dec 24 01:44:33 PM PST 23
Peak memory 214620 kb
Host smart-b0276982-b5b9-4eed-a7dc-97044173dc21
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451933839 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_di
sable_auto_req_mode.451933839
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.244701977
Short name T119
Test name
Test status
Simulation time 30857963 ps
CPU time 0.94 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:18 PM PST 23
Peak memory 214636 kb
Host smart-1185566d-82fc-412d-8e13-12822c36e7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244701977 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.244701977
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.3223594690
Short name T19
Test name
Test status
Simulation time 45459305 ps
CPU time 0.95 seconds
Started Dec 24 01:44:02 PM PST 23
Finished Dec 24 01:44:10 PM PST 23
Peak memory 205012 kb
Host smart-1ba60879-7922-4674-9abd-5cc3b2fd3c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223594690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.3223594690
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.651458652
Short name T764
Test name
Test status
Simulation time 22695656 ps
CPU time 1 seconds
Started Dec 24 01:44:03 PM PST 23
Finished Dec 24 01:44:13 PM PST 23
Peak memory 221856 kb
Host smart-b7f42612-5d72-4ad6-80ac-fe50bd8ed0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651458652 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.651458652
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.3810147749
Short name T941
Test name
Test status
Simulation time 47781498 ps
CPU time 0.86 seconds
Started Dec 24 01:44:03 PM PST 23
Finished Dec 24 01:44:12 PM PST 23
Peak memory 204820 kb
Host smart-2c8a3c06-e2db-49d3-b962-5b690b69d2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810147749 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.3810147749
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.3468680899
Short name T523
Test name
Test status
Simulation time 107854814 ps
CPU time 1.49 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:20 PM PST 23
Peak memory 205520 kb
Host smart-841e093d-aa03-4cf0-b205-38f961a1755b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468680899 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.3468680899
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.869020554
Short name T789
Test name
Test status
Simulation time 355174637464 ps
CPU time 687.1 seconds
Started Dec 24 01:44:06 PM PST 23
Finished Dec 24 01:55:49 PM PST 23
Peak memory 217276 kb
Host smart-b91aba48-4127-4051-9d9f-97ad02f0dd10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869020554 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.869020554
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.503637267
Short name T248
Test name
Test status
Simulation time 192493285 ps
CPU time 0.91 seconds
Started Dec 24 01:44:06 PM PST 23
Finished Dec 24 01:44:25 PM PST 23
Peak memory 205976 kb
Host smart-6ad1eec1-ad5b-4894-bd7e-71e2ee4883fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503637267 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.503637267
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.3844135388
Short name T714
Test name
Test status
Simulation time 49987419 ps
CPU time 0.8 seconds
Started Dec 24 01:44:08 PM PST 23
Finished Dec 24 01:44:28 PM PST 23
Peak memory 204984 kb
Host smart-18501a3f-5398-4877-b97e-a0956d52b6b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844135388 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.3844135388
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.3076178189
Short name T701
Test name
Test status
Simulation time 31297478 ps
CPU time 0.8 seconds
Started Dec 24 01:44:08 PM PST 23
Finished Dec 24 01:44:28 PM PST 23
Peak memory 214308 kb
Host smart-296ac1c3-5a84-4ef6-aab1-4f226c15299b
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076178189 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.3076178189
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.3849082310
Short name T105
Test name
Test status
Simulation time 274312307 ps
CPU time 0.99 seconds
Started Dec 24 01:44:06 PM PST 23
Finished Dec 24 01:44:23 PM PST 23
Peak memory 214540 kb
Host smart-1caaba20-05a2-47f9-b654-e6954fcb124c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849082310 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.3849082310
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.3498056521
Short name T898
Test name
Test status
Simulation time 105539306 ps
CPU time 1.18 seconds
Started Dec 24 01:44:11 PM PST 23
Finished Dec 24 01:44:32 PM PST 23
Peak memory 214804 kb
Host smart-ae52bf3b-9961-4871-ab13-cfa0019e0dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498056521 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.3498056521
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.2880520453
Short name T331
Test name
Test status
Simulation time 212529721 ps
CPU time 2.42 seconds
Started Dec 24 01:44:05 PM PST 23
Finished Dec 24 01:44:21 PM PST 23
Peak memory 213640 kb
Host smart-8374932d-107d-4d8a-894b-757bf908536c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880520453 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.2880520453
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.238289955
Short name T735
Test name
Test status
Simulation time 20726200 ps
CPU time 0.9 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:19 PM PST 23
Peak memory 214424 kb
Host smart-d8c883f2-7110-4a91-aae4-f7d02df12def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238289955 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.238289955
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.1433269821
Short name T720
Test name
Test status
Simulation time 26446799 ps
CPU time 0.89 seconds
Started Dec 24 01:44:05 PM PST 23
Finished Dec 24 01:44:20 PM PST 23
Peak memory 204816 kb
Host smart-643997b7-ed2c-4fec-bc28-686d253d0bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433269821 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.1433269821
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.1339546987
Short name T489
Test name
Test status
Simulation time 123356249 ps
CPU time 3.02 seconds
Started Dec 24 01:44:06 PM PST 23
Finished Dec 24 01:44:26 PM PST 23
Peak memory 206072 kb
Host smart-2bdccf75-75fa-4785-b238-5aa9a5cbed27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339546987 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.1339546987
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1230769635
Short name T261
Test name
Test status
Simulation time 57901451941 ps
CPU time 584.55 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:54:02 PM PST 23
Peak memory 215776 kb
Host smart-c82625dd-d1cc-44d5-bc55-2c8e5791d2fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230769635 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1230769635
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.409859180
Short name T245
Test name
Test status
Simulation time 32234811 ps
CPU time 1.01 seconds
Started Dec 24 01:42:14 PM PST 23
Finished Dec 24 01:42:16 PM PST 23
Peak memory 205248 kb
Host smart-db8858b8-8b70-4734-a8af-eb137bd04fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409859180 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.409859180
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.3612790721
Short name T592
Test name
Test status
Simulation time 19245323 ps
CPU time 1.03 seconds
Started Dec 24 01:42:43 PM PST 23
Finished Dec 24 01:43:00 PM PST 23
Peak memory 204512 kb
Host smart-8975e56a-a914-4d31-b99f-4574907bab22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612790721 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.3612790721
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.1554686699
Short name T146
Test name
Test status
Simulation time 19529165 ps
CPU time 0.85 seconds
Started Dec 24 01:42:41 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 214072 kb
Host smart-c812379c-58ec-4160-a48c-883bbe5c4a4b
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554686699 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1554686699
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.178321738
Short name T79
Test name
Test status
Simulation time 32496669 ps
CPU time 0.98 seconds
Started Dec 24 01:42:43 PM PST 23
Finished Dec 24 01:43:00 PM PST 23
Peak memory 214564 kb
Host smart-9a0e7de3-bfc5-45f6-b1af-da0d988102bb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178321738 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_dis
able_auto_req_mode.178321738
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.1554954739
Short name T748
Test name
Test status
Simulation time 22373432 ps
CPU time 1.21 seconds
Started Dec 24 01:42:17 PM PST 23
Finished Dec 24 01:42:20 PM PST 23
Peak memory 215956 kb
Host smart-33d8360f-1fa3-48aa-b96f-0fd2c23a6e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554954739 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.1554954739
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.2347555094
Short name T851
Test name
Test status
Simulation time 54617530 ps
CPU time 1.04 seconds
Started Dec 24 01:42:45 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 205748 kb
Host smart-2b48e7cf-82f8-4082-8c8a-b688918fd42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347555094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.2347555094
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.1214326158
Short name T895
Test name
Test status
Simulation time 20856309 ps
CPU time 1.15 seconds
Started Dec 24 01:41:57 PM PST 23
Finished Dec 24 01:42:04 PM PST 23
Peak memory 221800 kb
Host smart-e1879132-8ce7-4a2b-b6f7-0f894b8bca83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214326158 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.1214326158
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.2278390714
Short name T253
Test name
Test status
Simulation time 49062322 ps
CPU time 0.86 seconds
Started Dec 24 01:42:15 PM PST 23
Finished Dec 24 01:42:16 PM PST 23
Peak memory 204688 kb
Host smart-e9d70e82-4e66-4e9f-8aec-c5f5fe850930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278390714 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.2278390714
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.777509136
Short name T721
Test name
Test status
Simulation time 19731983 ps
CPU time 0.85 seconds
Started Dec 24 01:42:43 PM PST 23
Finished Dec 24 01:43:01 PM PST 23
Peak memory 204532 kb
Host smart-6a674b43-5e13-4810-8f15-b9e9a126a885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777509136 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.777509136
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.1188724674
Short name T707
Test name
Test status
Simulation time 163242508 ps
CPU time 3.53 seconds
Started Dec 24 01:41:56 PM PST 23
Finished Dec 24 01:42:05 PM PST 23
Peak memory 205900 kb
Host smart-d2067dce-2684-4dc5-9b64-5c17ccb6a661
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188724674 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.1188724674
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.788731790
Short name T297
Test name
Test status
Simulation time 67029317778 ps
CPU time 806.8 seconds
Started Dec 24 01:42:15 PM PST 23
Finished Dec 24 01:55:44 PM PST 23
Peak memory 214476 kb
Host smart-823ef4bc-5204-4c82-8922-8b70eca39f8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788731790 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.788731790
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.2132939819
Short name T200
Test name
Test status
Simulation time 28183070 ps
CPU time 0.82 seconds
Started Dec 24 01:44:08 PM PST 23
Finished Dec 24 01:44:29 PM PST 23
Peak memory 215348 kb
Host smart-4ba2a7c6-1f44-48e0-8ed6-fb4fb7c7e886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132939819 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.2132939819
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.2929736651
Short name T726
Test name
Test status
Simulation time 41152065 ps
CPU time 1.36 seconds
Started Dec 24 01:44:15 PM PST 23
Finished Dec 24 01:44:35 PM PST 23
Peak memory 205952 kb
Host smart-83fa67b6-cdb7-4592-af89-dcfde5b4a63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929736651 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.2929736651
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.4220969995
Short name T177
Test name
Test status
Simulation time 33277818 ps
CPU time 1.15 seconds
Started Dec 24 01:44:21 PM PST 23
Finished Dec 24 01:44:37 PM PST 23
Peak memory 228500 kb
Host smart-99b42a50-8189-46d1-b490-656ffc461abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220969995 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.4220969995
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.2485731877
Short name T287
Test name
Test status
Simulation time 21205107 ps
CPU time 1.13 seconds
Started Dec 24 01:44:08 PM PST 23
Finished Dec 24 01:44:29 PM PST 23
Peak memory 205524 kb
Host smart-5078bc01-570b-4c18-8b87-77ab0ce2da9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485731877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.2485731877
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.1409835472
Short name T885
Test name
Test status
Simulation time 25865104 ps
CPU time 1.11 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:18 PM PST 23
Peak memory 228292 kb
Host smart-692ee5ba-ae97-440c-a629-d99ad12cd8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409835472 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.1409835472
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.2189508538
Short name T724
Test name
Test status
Simulation time 61096827 ps
CPU time 0.94 seconds
Started Dec 24 01:44:13 PM PST 23
Finished Dec 24 01:44:33 PM PST 23
Peak memory 204872 kb
Host smart-479ef55f-a1ea-4727-89e2-e4049cdb74ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189508538 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.2189508538
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.2692587334
Short name T776
Test name
Test status
Simulation time 47745364 ps
CPU time 0.96 seconds
Started Dec 24 01:44:09 PM PST 23
Finished Dec 24 01:44:30 PM PST 23
Peak memory 221788 kb
Host smart-3aa54718-548e-4332-acff-0de47da1072c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692587334 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.2692587334
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.2669601279
Short name T508
Test name
Test status
Simulation time 20876851 ps
CPU time 1.05 seconds
Started Dec 24 01:44:09 PM PST 23
Finished Dec 24 01:44:30 PM PST 23
Peak memory 205296 kb
Host smart-6ed4a998-1856-45e9-8e75-947640f5f7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669601279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.2669601279
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_genbits.1008834021
Short name T634
Test name
Test status
Simulation time 44600026 ps
CPU time 1.18 seconds
Started Dec 24 01:44:08 PM PST 23
Finished Dec 24 01:44:29 PM PST 23
Peak memory 205492 kb
Host smart-927cfc82-39ee-488c-a955-08b624972b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008834021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.1008834021
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.651440119
Short name T946
Test name
Test status
Simulation time 31138261 ps
CPU time 0.85 seconds
Started Dec 24 01:44:12 PM PST 23
Finished Dec 24 01:44:33 PM PST 23
Peak memory 215184 kb
Host smart-f7c625de-e688-44a2-9837-1a6e8c8b8e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651440119 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.651440119
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.2303534349
Short name T455
Test name
Test status
Simulation time 30895465 ps
CPU time 1 seconds
Started Dec 24 01:44:08 PM PST 23
Finished Dec 24 01:44:28 PM PST 23
Peak memory 204792 kb
Host smart-1e4a7fbb-e12b-4e7a-bbe8-8657c65a0050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303534349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.2303534349
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.1868089353
Short name T173
Test name
Test status
Simulation time 84070101 ps
CPU time 1.17 seconds
Started Dec 24 01:44:07 PM PST 23
Finished Dec 24 01:44:26 PM PST 23
Peak memory 214876 kb
Host smart-1e286304-7865-4c1e-85fb-b2aef3db9154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868089353 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.1868089353
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.1951253953
Short name T671
Test name
Test status
Simulation time 303040792 ps
CPU time 4.28 seconds
Started Dec 24 01:44:10 PM PST 23
Finished Dec 24 01:44:34 PM PST 23
Peak memory 214380 kb
Host smart-150374ff-2564-424a-ba9d-f513a0e0f337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951253953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.1951253953
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.990390770
Short name T2
Test name
Test status
Simulation time 25919691 ps
CPU time 0.95 seconds
Started Dec 24 01:43:59 PM PST 23
Finished Dec 24 01:44:04 PM PST 23
Peak memory 221200 kb
Host smart-4c6d7cdf-4c32-42d5-948c-351d7a6a241c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990390770 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.990390770
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.3801530414
Short name T561
Test name
Test status
Simulation time 65129221 ps
CPU time 0.99 seconds
Started Dec 24 01:44:09 PM PST 23
Finished Dec 24 01:44:30 PM PST 23
Peak memory 205160 kb
Host smart-af54fb2e-3265-43f8-8c3f-85c06314a569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801530414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.3801530414
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.826992325
Short name T743
Test name
Test status
Simulation time 25179577 ps
CPU time 0.91 seconds
Started Dec 24 01:43:58 PM PST 23
Finished Dec 24 01:44:01 PM PST 23
Peak memory 215828 kb
Host smart-71ab2d22-21d1-48d6-a33d-03c4c3bc1bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826992325 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.826992325
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.3767960635
Short name T693
Test name
Test status
Simulation time 32055178 ps
CPU time 1 seconds
Started Dec 24 01:43:59 PM PST 23
Finished Dec 24 01:44:04 PM PST 23
Peak memory 205440 kb
Host smart-cbfceb0c-a54e-420a-946a-82d40fb55e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767960635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.3767960635
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.3522797420
Short name T111
Test name
Test status
Simulation time 44804029 ps
CPU time 1 seconds
Started Dec 24 01:43:57 PM PST 23
Finished Dec 24 01:43:59 PM PST 23
Peak memory 214604 kb
Host smart-ad679644-1eab-42b2-81c1-4a036f668a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522797420 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.3522797420
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.2163090313
Short name T704
Test name
Test status
Simulation time 24110804 ps
CPU time 0.98 seconds
Started Dec 24 01:43:57 PM PST 23
Finished Dec 24 01:43:59 PM PST 23
Peak memory 205392 kb
Host smart-d272df8b-3f24-4131-bdcc-abf1c4359831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163090313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.2163090313
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.2161529565
Short name T317
Test name
Test status
Simulation time 72252563 ps
CPU time 1.03 seconds
Started Dec 24 01:42:14 PM PST 23
Finished Dec 24 01:42:16 PM PST 23
Peak memory 205964 kb
Host smart-1d481929-7e90-411e-954f-d6d0f86c6a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161529565 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.2161529565
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.2347321117
Short name T609
Test name
Test status
Simulation time 11986741 ps
CPU time 0.82 seconds
Started Dec 24 01:41:57 PM PST 23
Finished Dec 24 01:42:04 PM PST 23
Peak memory 204336 kb
Host smart-f7037e5a-6435-4ea9-b168-aae304a8995d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347321117 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.2347321117
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.2883134335
Short name T190
Test name
Test status
Simulation time 290004808 ps
CPU time 1.23 seconds
Started Dec 24 01:42:44 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 213852 kb
Host smart-ff112c78-4574-4833-976b-a59f250801ad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883134335 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.2883134335
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.2137741348
Short name T86
Test name
Test status
Simulation time 58920407 ps
CPU time 0.96 seconds
Started Dec 24 01:42:42 PM PST 23
Finished Dec 24 01:42:58 PM PST 23
Peak memory 214616 kb
Host smart-11d6e329-f211-42b5-a235-0c802a87ef49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137741348 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.2137741348
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.3005468693
Short name T465
Test name
Test status
Simulation time 30215574 ps
CPU time 1 seconds
Started Dec 24 01:41:56 PM PST 23
Finished Dec 24 01:42:03 PM PST 23
Peak memory 205380 kb
Host smart-c43324e2-d506-4408-a925-3f2540c70188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005468693 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.3005468693
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.2964633146
Short name T942
Test name
Test status
Simulation time 27951942 ps
CPU time 0.91 seconds
Started Dec 24 01:42:45 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 214292 kb
Host smart-5751d133-110e-4e34-9496-26c6dc6b9b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964633146 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.2964633146
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.1543967896
Short name T329
Test name
Test status
Simulation time 36286707 ps
CPU time 0.83 seconds
Started Dec 24 01:42:19 PM PST 23
Finished Dec 24 01:42:22 PM PST 23
Peak memory 204620 kb
Host smart-8262cdae-c584-4abc-93f2-652060736c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543967896 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.1543967896
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.576306228
Short name T533
Test name
Test status
Simulation time 23255138 ps
CPU time 0.88 seconds
Started Dec 24 01:42:43 PM PST 23
Finished Dec 24 01:43:03 PM PST 23
Peak memory 204632 kb
Host smart-deb1808f-c9d0-48cb-b472-027c53c1fd4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576306228 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.576306228
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.346009176
Short name T98
Test name
Test status
Simulation time 450798544 ps
CPU time 3.95 seconds
Started Dec 24 01:42:17 PM PST 23
Finished Dec 24 01:42:23 PM PST 23
Peak memory 205888 kb
Host smart-d105fe77-1b7f-4805-8fa5-a1ee3583213c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346009176 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.346009176
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.630858393
Short name T300
Test name
Test status
Simulation time 626651135876 ps
CPU time 3139.89 seconds
Started Dec 24 01:42:16 PM PST 23
Finished Dec 24 02:34:37 PM PST 23
Peak memory 228176 kb
Host smart-79621caa-6a24-4b0a-91b6-0747d568b8f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630858393 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.630858393
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.1877716316
Short name T832
Test name
Test status
Simulation time 33266981 ps
CPU time 1.28 seconds
Started Dec 24 01:43:59 PM PST 23
Finished Dec 24 01:44:03 PM PST 23
Peak memory 214868 kb
Host smart-a1df50ca-2041-4003-83cc-18478a01539d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877716316 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.1877716316
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.233355000
Short name T334
Test name
Test status
Simulation time 27278133 ps
CPU time 0.9 seconds
Started Dec 24 01:44:00 PM PST 23
Finished Dec 24 01:44:06 PM PST 23
Peak memory 205012 kb
Host smart-3fbb0f80-1219-41ac-834a-6a868c178647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233355000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.233355000
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.4179689203
Short name T43
Test name
Test status
Simulation time 18206194 ps
CPU time 1.43 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:17 PM PST 23
Peak memory 221704 kb
Host smart-f696804a-5510-41d5-a1c2-04ca12759b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179689203 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.4179689203
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.2297624036
Short name T505
Test name
Test status
Simulation time 15570172 ps
CPU time 0.97 seconds
Started Dec 24 01:44:00 PM PST 23
Finished Dec 24 01:44:06 PM PST 23
Peak memory 205076 kb
Host smart-3c1331af-dac4-4fc4-a138-01cfd5491883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297624036 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.2297624036
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.3406041995
Short name T188
Test name
Test status
Simulation time 28963449 ps
CPU time 1.05 seconds
Started Dec 24 01:44:06 PM PST 23
Finished Dec 24 01:44:25 PM PST 23
Peak memory 215620 kb
Host smart-0a000100-e8d7-404e-a705-02e09a7927df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406041995 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.3406041995
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.451623878
Short name T813
Test name
Test status
Simulation time 62100900 ps
CPU time 1.15 seconds
Started Dec 24 01:44:01 PM PST 23
Finished Dec 24 01:44:09 PM PST 23
Peak memory 205816 kb
Host smart-0c2e07b3-6345-4d55-8350-55ec66e93190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451623878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.451623878
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.103630519
Short name T126
Test name
Test status
Simulation time 29083237 ps
CPU time 0.84 seconds
Started Dec 24 01:44:03 PM PST 23
Finished Dec 24 01:44:12 PM PST 23
Peak memory 215496 kb
Host smart-de39d634-38fa-430d-98c1-e907258d5f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103630519 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.103630519
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.1452302924
Short name T903
Test name
Test status
Simulation time 230237624 ps
CPU time 3.26 seconds
Started Dec 24 01:43:51 PM PST 23
Finished Dec 24 01:43:56 PM PST 23
Peak memory 214168 kb
Host smart-c4629bad-47a0-45cd-a912-c7952e7a0a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452302924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.1452302924
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.1029596820
Short name T6
Test name
Test status
Simulation time 21005683 ps
CPU time 0.97 seconds
Started Dec 24 01:44:03 PM PST 23
Finished Dec 24 01:44:13 PM PST 23
Peak memory 214444 kb
Host smart-6169fdec-e8a3-4722-b68c-f7cbae6f0ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029596820 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.1029596820
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.2310014428
Short name T757
Test name
Test status
Simulation time 20593762 ps
CPU time 1.01 seconds
Started Dec 24 01:44:02 PM PST 23
Finished Dec 24 01:44:11 PM PST 23
Peak memory 205208 kb
Host smart-683c6bc4-32ed-49ba-a0bb-b6a5604e1844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310014428 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2310014428
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.2577357148
Short name T565
Test name
Test status
Simulation time 31860395 ps
CPU time 0.81 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:18 PM PST 23
Peak memory 215568 kb
Host smart-92e1a5fd-c231-4244-8aa2-62110a2dd306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577357148 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.2577357148
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.2614651892
Short name T715
Test name
Test status
Simulation time 24470314 ps
CPU time 0.95 seconds
Started Dec 24 01:44:11 PM PST 23
Finished Dec 24 01:44:32 PM PST 23
Peak memory 205060 kb
Host smart-66ee9813-5971-40e2-8419-88bbeeb5181e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614651892 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.2614651892
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.1296017574
Short name T732
Test name
Test status
Simulation time 32416194 ps
CPU time 0.84 seconds
Started Dec 24 01:44:00 PM PST 23
Finished Dec 24 01:44:06 PM PST 23
Peak memory 215460 kb
Host smart-9031b9d4-e68b-48a0-8436-6ddaf7fb9b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296017574 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.1296017574
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.1870522181
Short name T818
Test name
Test status
Simulation time 17949147 ps
CPU time 1.09 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:17 PM PST 23
Peak memory 205516 kb
Host smart-979c9174-0e41-4b70-bb09-c40078cf8641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870522181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.1870522181
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.987004764
Short name T130
Test name
Test status
Simulation time 20418438 ps
CPU time 1.08 seconds
Started Dec 24 01:44:12 PM PST 23
Finished Dec 24 01:44:33 PM PST 23
Peak memory 214700 kb
Host smart-f3a0314d-4634-4098-9b73-02152c871276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987004764 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.987004764
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.789568141
Short name T663
Test name
Test status
Simulation time 33169686 ps
CPU time 0.98 seconds
Started Dec 24 01:44:07 PM PST 23
Finished Dec 24 01:44:26 PM PST 23
Peak memory 214128 kb
Host smart-ec20a411-4498-4c22-9177-e36c7286905e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789568141 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.789568141
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.2359110645
Short name T909
Test name
Test status
Simulation time 87331627 ps
CPU time 1.15 seconds
Started Dec 24 01:44:12 PM PST 23
Finished Dec 24 01:44:33 PM PST 23
Peak memory 221796 kb
Host smart-3ea7f2af-e6ee-4c27-b99e-e869052c829b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359110645 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.2359110645
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.2034418055
Short name T56
Test name
Test status
Simulation time 49632340 ps
CPU time 0.99 seconds
Started Dec 24 01:44:12 PM PST 23
Finished Dec 24 01:44:33 PM PST 23
Peak memory 205248 kb
Host smart-8e56e27f-9512-47b2-85d7-2336193a02c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034418055 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.2034418055
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.420533971
Short name T511
Test name
Test status
Simulation time 18669179 ps
CPU time 1.17 seconds
Started Dec 24 01:44:12 PM PST 23
Finished Dec 24 01:44:33 PM PST 23
Peak memory 215556 kb
Host smart-a3f392a6-5de3-45ab-b688-a346280833d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420533971 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.420533971
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.3723481038
Short name T728
Test name
Test status
Simulation time 26952676 ps
CPU time 1.03 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:18 PM PST 23
Peak memory 205656 kb
Host smart-9ceeb861-2eb9-4b39-ba6f-10fe78a335a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723481038 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.3723481038
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.2650168823
Short name T962
Test name
Test status
Simulation time 53740131 ps
CPU time 0.94 seconds
Started Dec 24 01:42:17 PM PST 23
Finished Dec 24 01:42:20 PM PST 23
Peak memory 205888 kb
Host smart-f8e91cea-ab7b-495a-9be4-37d49195f42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650168823 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.2650168823
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.3092884555
Short name T684
Test name
Test status
Simulation time 107601521 ps
CPU time 0.87 seconds
Started Dec 24 01:42:15 PM PST 23
Finished Dec 24 01:42:17 PM PST 23
Peak memory 205432 kb
Host smart-cccff18e-e800-4b46-bd36-33dc2cd0dc42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092884555 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.3092884555
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.1218984651
Short name T856
Test name
Test status
Simulation time 13755636 ps
CPU time 0.91 seconds
Started Dec 24 01:42:22 PM PST 23
Finished Dec 24 01:42:24 PM PST 23
Peak memory 214508 kb
Host smart-6487dbb7-19ba-4bd1-b4a5-692748b5aad3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218984651 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.1218984651
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.1116300958
Short name T783
Test name
Test status
Simulation time 18835604 ps
CPU time 1.08 seconds
Started Dec 24 01:42:43 PM PST 23
Finished Dec 24 01:43:00 PM PST 23
Peak memory 215916 kb
Host smart-bd5b039c-3f4c-4efa-ad4d-6730912c99e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116300958 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.1116300958
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.992700853
Short name T683
Test name
Test status
Simulation time 99535798 ps
CPU time 1.18 seconds
Started Dec 24 01:41:58 PM PST 23
Finished Dec 24 01:42:05 PM PST 23
Peak memory 205468 kb
Host smart-c5e0f230-a07f-47aa-9c9b-950b33eea98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992700853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.992700853
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.1168709367
Short name T49
Test name
Test status
Simulation time 19249081 ps
CPU time 1.1 seconds
Started Dec 24 01:42:43 PM PST 23
Finished Dec 24 01:43:03 PM PST 23
Peak memory 214536 kb
Host smart-06fc1b0d-78b0-4a83-aff4-e6de5298b19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168709367 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.1168709367
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.3617252459
Short name T321
Test name
Test status
Simulation time 21874224 ps
CPU time 0.84 seconds
Started Dec 24 01:42:16 PM PST 23
Finished Dec 24 01:42:18 PM PST 23
Peak memory 204832 kb
Host smart-38304049-9665-4b64-997b-8666ca046743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617252459 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.3617252459
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.2766884519
Short name T57
Test name
Test status
Simulation time 87199162 ps
CPU time 0.83 seconds
Started Dec 24 01:41:56 PM PST 23
Finished Dec 24 01:42:02 PM PST 23
Peak memory 204664 kb
Host smart-3e1d2b3c-7815-4d7d-a4c6-f2fd0184be29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766884519 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.2766884519
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.44967469
Short name T458
Test name
Test status
Simulation time 171154464 ps
CPU time 2.97 seconds
Started Dec 24 01:42:44 PM PST 23
Finished Dec 24 01:43:06 PM PST 23
Peak memory 205804 kb
Host smart-ca2d4e8d-6721-45e9-bb66-74b773194ffb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44967469 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.44967469
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.3838722760
Short name T566
Test name
Test status
Simulation time 87129512708 ps
CPU time 1967.25 seconds
Started Dec 24 01:42:43 PM PST 23
Finished Dec 24 02:15:48 PM PST 23
Peak memory 220600 kb
Host smart-d9130f32-0ad9-476e-a9b2-7ab2c8a4b8eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838722760 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.3838722760
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.3195084225
Short name T774
Test name
Test status
Simulation time 18497782 ps
CPU time 1.38 seconds
Started Dec 24 01:44:05 PM PST 23
Finished Dec 24 01:44:22 PM PST 23
Peak memory 221800 kb
Host smart-97f685b5-64a2-48b9-9940-308243f16e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195084225 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.3195084225
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.2944974291
Short name T805
Test name
Test status
Simulation time 20077208 ps
CPU time 1.05 seconds
Started Dec 24 01:44:05 PM PST 23
Finished Dec 24 01:44:20 PM PST 23
Peak memory 214136 kb
Host smart-45dee0f7-6b77-4f5f-85a7-fa048b1af0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944974291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.2944974291
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.2120885083
Short name T7
Test name
Test status
Simulation time 20983686 ps
CPU time 1.22 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:18 PM PST 23
Peak memory 214492 kb
Host smart-e10735dd-afad-4ae9-a288-045ea7d868ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120885083 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.2120885083
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.2846556244
Short name T927
Test name
Test status
Simulation time 37801142 ps
CPU time 1.04 seconds
Started Dec 24 01:44:06 PM PST 23
Finished Dec 24 01:44:24 PM PST 23
Peak memory 205184 kb
Host smart-c3c87930-9296-4609-91da-371418da734e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846556244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.2846556244
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.2791137541
Short name T194
Test name
Test status
Simulation time 39153037 ps
CPU time 1.25 seconds
Started Dec 24 01:44:02 PM PST 23
Finished Dec 24 01:44:10 PM PST 23
Peak memory 228084 kb
Host smart-b2d2f90c-1c5e-44e1-acc0-be3b2a8c0da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791137541 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.2791137541
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.2256110924
Short name T556
Test name
Test status
Simulation time 18124156 ps
CPU time 1.01 seconds
Started Dec 24 01:44:02 PM PST 23
Finished Dec 24 01:44:11 PM PST 23
Peak memory 204948 kb
Host smart-8b63bc82-cc14-451d-970a-20a242045c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256110924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.2256110924
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.2145726005
Short name T899
Test name
Test status
Simulation time 30378942 ps
CPU time 0.97 seconds
Started Dec 24 01:44:00 PM PST 23
Finished Dec 24 01:44:06 PM PST 23
Peak memory 228396 kb
Host smart-5d7cab4f-4a1e-47e4-bec6-d91e7f253764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145726005 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.2145726005
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.267862314
Short name T658
Test name
Test status
Simulation time 71388792 ps
CPU time 1.23 seconds
Started Dec 24 01:44:02 PM PST 23
Finished Dec 24 01:44:11 PM PST 23
Peak memory 205852 kb
Host smart-41531458-896f-4e96-a2eb-4a1c92822e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267862314 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.267862314
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.267210529
Short name T816
Test name
Test status
Simulation time 47234231 ps
CPU time 1.08 seconds
Started Dec 24 01:43:58 PM PST 23
Finished Dec 24 01:44:00 PM PST 23
Peak memory 221764 kb
Host smart-b31ab9fe-e4f8-4324-ae09-cca20f5bbcdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267210529 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.267210529
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.4228342819
Short name T281
Test name
Test status
Simulation time 65091255 ps
CPU time 1.06 seconds
Started Dec 24 01:43:59 PM PST 23
Finished Dec 24 01:44:02 PM PST 23
Peak memory 205488 kb
Host smart-c28460bc-b8f9-49b5-ab84-528291f58f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228342819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.4228342819
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.3524798732
Short name T934
Test name
Test status
Simulation time 21272297 ps
CPU time 1.07 seconds
Started Dec 24 01:43:58 PM PST 23
Finished Dec 24 01:44:01 PM PST 23
Peak memory 216044 kb
Host smart-5e169a7d-def5-4229-905c-aae8e6f04427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524798732 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.3524798732
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.1285824681
Short name T758
Test name
Test status
Simulation time 16456824 ps
CPU time 1.04 seconds
Started Dec 24 01:43:58 PM PST 23
Finished Dec 24 01:44:01 PM PST 23
Peak memory 214120 kb
Host smart-40540539-2574-4907-a735-660bb4d3abd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285824681 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.1285824681
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.2025897474
Short name T651
Test name
Test status
Simulation time 38108876 ps
CPU time 1.37 seconds
Started Dec 24 01:43:59 PM PST 23
Finished Dec 24 01:44:04 PM PST 23
Peak memory 227652 kb
Host smart-077d49af-45df-4a0d-9f7e-622532f5a047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025897474 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.2025897474
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.3057941876
Short name T700
Test name
Test status
Simulation time 78723440 ps
CPU time 1.13 seconds
Started Dec 24 01:44:00 PM PST 23
Finished Dec 24 01:44:06 PM PST 23
Peak memory 205408 kb
Host smart-348dc38d-9544-405a-9309-afcb5970fbf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057941876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.3057941876
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.1308726731
Short name T657
Test name
Test status
Simulation time 70773477 ps
CPU time 1.02 seconds
Started Dec 24 01:44:01 PM PST 23
Finished Dec 24 01:44:09 PM PST 23
Peak memory 216756 kb
Host smart-816a873c-cf5e-40d5-be8e-bc9321585193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308726731 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.1308726731
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.2951289904
Short name T797
Test name
Test status
Simulation time 20828037 ps
CPU time 0.98 seconds
Started Dec 24 01:44:02 PM PST 23
Finished Dec 24 01:44:09 PM PST 23
Peak memory 205440 kb
Host smart-2d7063fa-bd44-4011-9bac-d7eb9751503b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951289904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.2951289904
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.1223171461
Short name T38
Test name
Test status
Simulation time 57338270 ps
CPU time 0.96 seconds
Started Dec 24 01:43:59 PM PST 23
Finished Dec 24 01:44:02 PM PST 23
Peak memory 221372 kb
Host smart-2e15b13c-a02b-4a13-a497-88e69551e1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223171461 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.1223171461
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.3022337519
Short name T589
Test name
Test status
Simulation time 12397691 ps
CPU time 0.92 seconds
Started Dec 24 01:43:58 PM PST 23
Finished Dec 24 01:44:01 PM PST 23
Peak memory 205064 kb
Host smart-d3b8da77-f1d1-46ea-b9a9-bd84e0b49b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022337519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.3022337519
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.2585673408
Short name T207
Test name
Test status
Simulation time 22416676 ps
CPU time 1.01 seconds
Started Dec 24 01:43:59 PM PST 23
Finished Dec 24 01:44:03 PM PST 23
Peak memory 221776 kb
Host smart-ad0b5742-53e0-4b1d-b929-282a8556b62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585673408 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.2585673408
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.1938040938
Short name T573
Test name
Test status
Simulation time 16215781 ps
CPU time 0.95 seconds
Started Dec 24 01:44:03 PM PST 23
Finished Dec 24 01:44:14 PM PST 23
Peak memory 205212 kb
Host smart-410db745-4899-488a-9fda-6c85d43f88c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938040938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.1938040938
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.1638273369
Short name T326
Test name
Test status
Simulation time 42973909 ps
CPU time 0.92 seconds
Started Dec 24 01:42:43 PM PST 23
Finished Dec 24 01:43:01 PM PST 23
Peak memory 205140 kb
Host smart-2a081091-e71a-4b1c-ad21-6c8cfc086d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638273369 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.1638273369
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.2219484869
Short name T679
Test name
Test status
Simulation time 35983256 ps
CPU time 0.82 seconds
Started Dec 24 01:42:43 PM PST 23
Finished Dec 24 01:43:00 PM PST 23
Peak memory 204360 kb
Host smart-2e05d5df-2b44-44b8-bd12-cbef59b9dc27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219484869 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.2219484869
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_err.922491621
Short name T210
Test name
Test status
Simulation time 31939074 ps
CPU time 0.89 seconds
Started Dec 24 01:42:15 PM PST 23
Finished Dec 24 01:42:17 PM PST 23
Peak memory 221044 kb
Host smart-1df3cdd4-f991-4a9c-864e-ae7dd54abe56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922491621 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.922491621
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.1985649765
Short name T615
Test name
Test status
Simulation time 577078333 ps
CPU time 4.91 seconds
Started Dec 24 01:42:42 PM PST 23
Finished Dec 24 01:42:58 PM PST 23
Peak memory 214184 kb
Host smart-f1d5f7e7-8d6e-475b-96a0-24f1cb5fd6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985649765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.1985649765
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.2946016933
Short name T95
Test name
Test status
Simulation time 52051441 ps
CPU time 0.78 seconds
Started Dec 24 01:42:19 PM PST 23
Finished Dec 24 01:42:22 PM PST 23
Peak memory 214184 kb
Host smart-3183cbd1-1a8e-46dc-837c-ac6537a53391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946016933 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.2946016933
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.60071576
Short name T323
Test name
Test status
Simulation time 15671878 ps
CPU time 0.95 seconds
Started Dec 24 01:42:16 PM PST 23
Finished Dec 24 01:42:19 PM PST 23
Peak memory 204836 kb
Host smart-591f59f6-74ff-48d1-9da3-ea449e6c08ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60071576 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.60071576
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.2711791253
Short name T519
Test name
Test status
Simulation time 38792585 ps
CPU time 0.81 seconds
Started Dec 24 01:42:41 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 204836 kb
Host smart-e8ad92d1-1888-4bc6-bdb6-deefe8005d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711791253 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.2711791253
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.2284756693
Short name T510
Test name
Test status
Simulation time 92496988 ps
CPU time 1.1 seconds
Started Dec 24 01:42:42 PM PST 23
Finished Dec 24 01:42:59 PM PST 23
Peak memory 205232 kb
Host smart-3c9f898e-bbb6-4c0e-b759-e6398f0e6ae1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284756693 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.2284756693
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.1867747213
Short name T923
Test name
Test status
Simulation time 98494948218 ps
CPU time 2206.4 seconds
Started Dec 24 01:42:15 PM PST 23
Finished Dec 24 02:19:02 PM PST 23
Peak memory 221168 kb
Host smart-517a19c0-6f2e-438f-83d0-6300aa7e64c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867747213 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.1867747213
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.4161461190
Short name T124
Test name
Test status
Simulation time 29275435 ps
CPU time 1.22 seconds
Started Dec 24 01:43:58 PM PST 23
Finished Dec 24 01:44:01 PM PST 23
Peak memory 217144 kb
Host smart-07904827-a1a2-49db-911c-5f0f1617cedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161461190 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.4161461190
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.4066675510
Short name T552
Test name
Test status
Simulation time 20584012 ps
CPU time 0.92 seconds
Started Dec 24 01:43:58 PM PST 23
Finished Dec 24 01:44:01 PM PST 23
Peak memory 205152 kb
Host smart-0db54b54-05fd-4121-b11b-a6745d1a27f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066675510 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.4066675510
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.3507555482
Short name T178
Test name
Test status
Simulation time 64961415 ps
CPU time 1.07 seconds
Started Dec 24 01:44:00 PM PST 23
Finished Dec 24 01:44:07 PM PST 23
Peak memory 214652 kb
Host smart-6fb7c218-d0d3-4141-9efa-98b071f732b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507555482 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.3507555482
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.3336288845
Short name T879
Test name
Test status
Simulation time 63716331 ps
CPU time 0.99 seconds
Started Dec 24 01:43:59 PM PST 23
Finished Dec 24 01:44:03 PM PST 23
Peak memory 205392 kb
Host smart-2e91c8b6-c90c-4d1b-ada3-bb58f2cc8fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336288845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.3336288845
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.1967078269
Short name T970
Test name
Test status
Simulation time 24754818 ps
CPU time 1.06 seconds
Started Dec 24 01:44:00 PM PST 23
Finished Dec 24 01:44:06 PM PST 23
Peak memory 221692 kb
Host smart-bdef4bf6-e5b1-48a7-9eef-77840c28952c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967078269 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.1967078269
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.1826174042
Short name T767
Test name
Test status
Simulation time 19598710 ps
CPU time 1.02 seconds
Started Dec 24 01:44:01 PM PST 23
Finished Dec 24 01:44:07 PM PST 23
Peak memory 205064 kb
Host smart-f89f9777-2971-435b-b234-c037f65df23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826174042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.1826174042
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.3735677274
Short name T88
Test name
Test status
Simulation time 63214354 ps
CPU time 0.99 seconds
Started Dec 24 01:43:58 PM PST 23
Finished Dec 24 01:44:00 PM PST 23
Peak memory 216052 kb
Host smart-30c22719-cbb6-48e1-977d-017283f43fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735677274 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.3735677274
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/84.edn_err.2296019648
Short name T174
Test name
Test status
Simulation time 46778864 ps
CPU time 1.15 seconds
Started Dec 24 01:44:03 PM PST 23
Finished Dec 24 01:44:15 PM PST 23
Peak memory 221196 kb
Host smart-c1841dfc-46c9-4f74-9586-2d1d5ffa7cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296019648 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.2296019648
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.3651444955
Short name T479
Test name
Test status
Simulation time 58255731 ps
CPU time 1 seconds
Started Dec 24 01:44:01 PM PST 23
Finished Dec 24 01:44:08 PM PST 23
Peak memory 205440 kb
Host smart-bbd8df97-4196-4cab-975a-51b2c4183caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651444955 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.3651444955
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.3649482956
Short name T785
Test name
Test status
Simulation time 21307975 ps
CPU time 1.08 seconds
Started Dec 24 01:44:05 PM PST 23
Finished Dec 24 01:44:20 PM PST 23
Peak memory 214280 kb
Host smart-31cafaf9-9d42-4ccd-9850-64a8ecd7432b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649482956 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.3649482956
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.2024122766
Short name T273
Test name
Test status
Simulation time 55677115 ps
CPU time 0.98 seconds
Started Dec 24 01:44:01 PM PST 23
Finished Dec 24 01:44:08 PM PST 23
Peak memory 205232 kb
Host smart-a5c880be-52bb-4f06-988e-83d6d86a2ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024122766 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.2024122766
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.2689001905
Short name T139
Test name
Test status
Simulation time 41577226 ps
CPU time 1.05 seconds
Started Dec 24 01:44:06 PM PST 23
Finished Dec 24 01:44:24 PM PST 23
Peak memory 217088 kb
Host smart-fa889aa6-5408-46d9-a886-16c0af7f0c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689001905 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.2689001905
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.3002851929
Short name T694
Test name
Test status
Simulation time 14692922 ps
CPU time 0.97 seconds
Started Dec 24 01:43:57 PM PST 23
Finished Dec 24 01:43:59 PM PST 23
Peak memory 204836 kb
Host smart-04b9cb27-ccc0-47fa-8767-1db27c237ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002851929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.3002851929
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.3790105771
Short name T129
Test name
Test status
Simulation time 29075017 ps
CPU time 1.12 seconds
Started Dec 24 01:44:02 PM PST 23
Finished Dec 24 01:44:10 PM PST 23
Peak memory 228776 kb
Host smart-36c7cb3c-35cf-4a7e-b269-c962fc6433a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790105771 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.3790105771
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.839638947
Short name T925
Test name
Test status
Simulation time 129262699 ps
CPU time 1 seconds
Started Dec 24 01:43:57 PM PST 23
Finished Dec 24 01:43:59 PM PST 23
Peak memory 205320 kb
Host smart-5f1db2ee-e1f4-45b2-92d0-3e8ec9a58873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839638947 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.839638947
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.3448590291
Short name T823
Test name
Test status
Simulation time 22465943 ps
CPU time 1.06 seconds
Started Dec 24 01:44:00 PM PST 23
Finished Dec 24 01:44:06 PM PST 23
Peak memory 221688 kb
Host smart-9ac8f8d6-54c1-470d-aa48-a1c68a8f86d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448590291 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.3448590291
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.2156056883
Short name T102
Test name
Test status
Simulation time 22657719 ps
CPU time 1.04 seconds
Started Dec 24 01:43:59 PM PST 23
Finished Dec 24 01:44:04 PM PST 23
Peak memory 214076 kb
Host smart-e71103a8-9ca0-455f-aff4-3f4b6db758d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156056883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.2156056883
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.3664763054
Short name T39
Test name
Test status
Simulation time 41262951 ps
CPU time 0.9 seconds
Started Dec 24 01:44:00 PM PST 23
Finished Dec 24 01:44:05 PM PST 23
Peak memory 221504 kb
Host smart-774a66f4-cd0a-45db-9577-d76a9c931d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664763054 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.3664763054
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.363228369
Short name T959
Test name
Test status
Simulation time 51423627 ps
CPU time 0.94 seconds
Started Dec 24 01:43:56 PM PST 23
Finished Dec 24 01:43:59 PM PST 23
Peak memory 205756 kb
Host smart-5fbb0fb3-e280-4db1-b621-e5ef4b78ce74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363228369 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.363228369
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.26393069
Short name T874
Test name
Test status
Simulation time 51629495 ps
CPU time 0.93 seconds
Started Dec 24 01:42:45 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 205868 kb
Host smart-f0663458-236e-4f13-80b4-415fbb739b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26393069 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.26393069
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.1743785877
Short name T606
Test name
Test status
Simulation time 52889774 ps
CPU time 0.89 seconds
Started Dec 24 01:42:43 PM PST 23
Finished Dec 24 01:43:00 PM PST 23
Peak memory 204568 kb
Host smart-22e0d647-7714-41dd-8888-e7d585a84312
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743785877 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.1743785877
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.901370508
Short name T884
Test name
Test status
Simulation time 11255022 ps
CPU time 0.88 seconds
Started Dec 24 01:42:30 PM PST 23
Finished Dec 24 01:42:32 PM PST 23
Peak memory 214296 kb
Host smart-0689224a-16e0-4c6c-b279-88ec8d2c8a5f
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901370508 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.901370508
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.2477342341
Short name T80
Test name
Test status
Simulation time 88558733 ps
CPU time 1.12 seconds
Started Dec 24 01:42:32 PM PST 23
Finished Dec 24 01:42:34 PM PST 23
Peak memory 214436 kb
Host smart-ee044d6c-4f08-41dc-93c8-ad86dff22325
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477342341 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.2477342341
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.2457546330
Short name T131
Test name
Test status
Simulation time 42966958 ps
CPU time 0.82 seconds
Started Dec 24 01:42:32 PM PST 23
Finished Dec 24 01:42:34 PM PST 23
Peak memory 215356 kb
Host smart-3a75734b-e75f-453d-99b8-518671958e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457546330 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.2457546330
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.3736164145
Short name T274
Test name
Test status
Simulation time 102755808 ps
CPU time 0.98 seconds
Started Dec 24 01:42:16 PM PST 23
Finished Dec 24 01:42:19 PM PST 23
Peak memory 205348 kb
Host smart-1a06389c-dfaf-40f5-a6c2-2882c6120067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736164145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.3736164145
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.2922736795
Short name T91
Test name
Test status
Simulation time 31368641 ps
CPU time 0.96 seconds
Started Dec 24 01:42:32 PM PST 23
Finished Dec 24 01:42:34 PM PST 23
Peak memory 225480 kb
Host smart-7e4a208a-a537-4fe7-a742-b9033847b416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922736795 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.2922736795
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.3213112070
Short name T251
Test name
Test status
Simulation time 16140096 ps
CPU time 0.94 seconds
Started Dec 24 01:42:15 PM PST 23
Finished Dec 24 01:42:18 PM PST 23
Peak memory 205012 kb
Host smart-522f27e5-2221-4cc5-b22b-cc1c2848cbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213112070 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.3213112070
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.2722433371
Short name T583
Test name
Test status
Simulation time 67160235 ps
CPU time 0.85 seconds
Started Dec 24 01:42:21 PM PST 23
Finished Dec 24 01:42:22 PM PST 23
Peak memory 204532 kb
Host smart-a61a7f36-10c4-4d1b-a3d1-70fe10b19299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722433371 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.2722433371
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.2782298678
Short name T761
Test name
Test status
Simulation time 188200879 ps
CPU time 4.02 seconds
Started Dec 24 01:42:17 PM PST 23
Finished Dec 24 01:42:24 PM PST 23
Peak memory 205928 kb
Host smart-2e5684fe-83d5-47e3-99e5-4d17b3299e1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782298678 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.2782298678
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.3314253985
Short name T708
Test name
Test status
Simulation time 62621317112 ps
CPU time 1563.19 seconds
Started Dec 24 01:42:29 PM PST 23
Finished Dec 24 02:08:34 PM PST 23
Peak memory 219192 kb
Host smart-1efc28e7-c4f9-41cc-bbce-5a5c31a843e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314253985 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.3314253985
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.824126454
Short name T41
Test name
Test status
Simulation time 18939284 ps
CPU time 1.05 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:18 PM PST 23
Peak memory 221652 kb
Host smart-fb2bbf13-19da-4ca0-b12b-6e1c7b78c73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824126454 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.824126454
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.1523168743
Short name T788
Test name
Test status
Simulation time 97365473 ps
CPU time 2.3 seconds
Started Dec 24 01:44:02 PM PST 23
Finished Dec 24 01:44:11 PM PST 23
Peak memory 214088 kb
Host smart-b9b7e009-342d-45cb-ae32-14d78f6e6700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523168743 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.1523168743
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.1341926557
Short name T121
Test name
Test status
Simulation time 34635377 ps
CPU time 0.99 seconds
Started Dec 24 01:44:00 PM PST 23
Finished Dec 24 01:44:06 PM PST 23
Peak memory 228452 kb
Host smart-b0c6c52b-bf5b-4692-8f0b-d224cd170b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341926557 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.1341926557
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.1767501054
Short name T821
Test name
Test status
Simulation time 53558275 ps
CPU time 1.54 seconds
Started Dec 24 01:44:03 PM PST 23
Finished Dec 24 01:44:14 PM PST 23
Peak memory 214084 kb
Host smart-e7b81cf7-1d31-498f-b02a-77cd62cc9062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767501054 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.1767501054
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.471634217
Short name T113
Test name
Test status
Simulation time 62161551 ps
CPU time 0.83 seconds
Started Dec 24 01:44:03 PM PST 23
Finished Dec 24 01:44:14 PM PST 23
Peak memory 215864 kb
Host smart-8b77011c-f51f-4c6e-8489-f3a6c930d735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471634217 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.471634217
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.2242597991
Short name T924
Test name
Test status
Simulation time 62523200 ps
CPU time 0.88 seconds
Started Dec 24 01:44:05 PM PST 23
Finished Dec 24 01:44:20 PM PST 23
Peak memory 205020 kb
Host smart-2696e4af-f7cc-412d-a743-1615d0359cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242597991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.2242597991
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.3600680268
Short name T647
Test name
Test status
Simulation time 29189915 ps
CPU time 1.23 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:19 PM PST 23
Peak memory 229936 kb
Host smart-1c2251f7-3a4c-407b-a0c2-70221775ac8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600680268 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.3600680268
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.2519934664
Short name T687
Test name
Test status
Simulation time 35246315 ps
CPU time 1.14 seconds
Started Dec 24 01:44:05 PM PST 23
Finished Dec 24 01:44:21 PM PST 23
Peak memory 214000 kb
Host smart-d9597210-c6ed-4bc3-a7af-ff22f9e0e65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519934664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.2519934664
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.4097468202
Short name T858
Test name
Test status
Simulation time 23660172 ps
CPU time 1.23 seconds
Started Dec 24 01:44:05 PM PST 23
Finished Dec 24 01:44:22 PM PST 23
Peak memory 215956 kb
Host smart-e8763bfc-9a02-43f1-942a-38b8cb0d2bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097468202 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.4097468202
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.1914741191
Short name T722
Test name
Test status
Simulation time 244678290 ps
CPU time 1.27 seconds
Started Dec 24 01:44:03 PM PST 23
Finished Dec 24 01:44:13 PM PST 23
Peak memory 214172 kb
Host smart-00034f95-ca06-490c-be18-fa1a304aa0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914741191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.1914741191
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.2792654271
Short name T176
Test name
Test status
Simulation time 34518283 ps
CPU time 0.9 seconds
Started Dec 24 01:44:06 PM PST 23
Finished Dec 24 01:44:24 PM PST 23
Peak memory 214520 kb
Host smart-8ea70310-b0d1-4e92-9b24-57a2b9586e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792654271 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.2792654271
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.2471496359
Short name T800
Test name
Test status
Simulation time 32288409 ps
CPU time 1.01 seconds
Started Dec 24 01:44:11 PM PST 23
Finished Dec 24 01:44:31 PM PST 23
Peak memory 205284 kb
Host smart-0f3e996f-bde0-4c21-a66e-7192b2a2d619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471496359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.2471496359
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.4154982703
Short name T4
Test name
Test status
Simulation time 19286841 ps
CPU time 1.16 seconds
Started Dec 24 01:44:11 PM PST 23
Finished Dec 24 01:44:32 PM PST 23
Peak memory 215552 kb
Host smart-57efda82-47ed-4ee9-aad0-6bedb5698407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154982703 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.4154982703
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.4008373392
Short name T348
Test name
Test status
Simulation time 17661521 ps
CPU time 0.91 seconds
Started Dec 24 01:44:04 PM PST 23
Finished Dec 24 01:44:19 PM PST 23
Peak memory 204960 kb
Host smart-1e6d0d4c-1a7e-4702-be44-29a9a1e47cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008373392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.4008373392
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.3004483718
Short name T125
Test name
Test status
Simulation time 38167923 ps
CPU time 1.03 seconds
Started Dec 24 01:44:08 PM PST 23
Finished Dec 24 01:44:29 PM PST 23
Peak memory 221544 kb
Host smart-fad5f1de-9dac-4096-91d9-704ad30afc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004483718 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.3004483718
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.479771916
Short name T58
Test name
Test status
Simulation time 34081445 ps
CPU time 1.06 seconds
Started Dec 24 01:44:06 PM PST 23
Finished Dec 24 01:44:26 PM PST 23
Peak memory 214172 kb
Host smart-c884552d-5cdb-4fb3-a32c-82ed377b971b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479771916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.479771916
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.3829843171
Short name T175
Test name
Test status
Simulation time 55160981 ps
CPU time 1.05 seconds
Started Dec 24 01:44:06 PM PST 23
Finished Dec 24 01:44:23 PM PST 23
Peak memory 228484 kb
Host smart-51595d15-09d3-4e79-a773-141a1b629789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829843171 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.3829843171
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.896335697
Short name T595
Test name
Test status
Simulation time 49187263 ps
CPU time 1.05 seconds
Started Dec 24 01:44:05 PM PST 23
Finished Dec 24 01:44:21 PM PST 23
Peak memory 205572 kb
Host smart-440f85e4-83c8-40d8-8359-a9f0b1b301d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896335697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.896335697
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.2682114523
Short name T183
Test name
Test status
Simulation time 39138048 ps
CPU time 1.21 seconds
Started Dec 24 01:44:08 PM PST 23
Finished Dec 24 01:44:28 PM PST 23
Peak memory 228536 kb
Host smart-a246b091-4108-436c-9602-01de460b39dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682114523 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.2682114523
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.3517548234
Short name T613
Test name
Test status
Simulation time 18567054 ps
CPU time 1.09 seconds
Started Dec 24 01:44:06 PM PST 23
Finished Dec 24 01:44:25 PM PST 23
Peak memory 205340 kb
Host smart-baea6690-8cdd-4c2a-a4e4-18d8603e1d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517548234 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.3517548234
Directory /workspace/99.edn_genbits/latest
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