Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 8 0 8 100.00


Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr_pin 2 0 2 100.00 100 1 1 0
cp_intr_pin_value 4 0 4 100.00 100 1 1 0


Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_intr_pins_all_values 8 0 8 100.00 100 1 1 0


Summary for Variable cp_intr_pin

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_intr_pin

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_pins[0] 111336 1 T1 166 T3 26 T7 1
all_pins[1] 111336 1 T1 166 T3 26 T7 1



Summary for Variable cp_intr_pin_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_intr_pin_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 212996 1 T1 332 T3 52 T7 2
values[0x1] 9676 1 T5 204 T41 1 T184 1
transitions[0x0=>0x1] 8913 1 T5 178 T41 1 T184 1
transitions[0x1=>0x0] 8928 1 T5 178 T41 1 T184 1



Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 0 8 100.00


Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins
cp_intr_pincp_intr_pin_valueCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_pins[0] values[0x0] 103271 1 T1 166 T3 26 T7 1
all_pins[0] values[0x1] 8065 1 T5 164 T41 1 T42 2
all_pins[0] transitions[0x0=>0x1] 7661 1 T5 151 T41 1 T186 1
all_pins[0] transitions[0x1=>0x0] 1207 1 T5 27 T184 1 T186 2
all_pins[1] values[0x0] 109725 1 T1 166 T3 26 T7 1
all_pins[1] values[0x1] 1611 1 T5 40 T184 1 T42 2
all_pins[1] transitions[0x0=>0x1] 1252 1 T5 27 T184 1 T42 1
all_pins[1] transitions[0x1=>0x0] 7721 1 T5 151 T41 1 T42 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%