Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.13 99.02 92.26 96.79 94.08 98.62 99.77 99.40


Total test records in report: 977
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T778 /workspace/coverage/default/23.edn_stress_all.2537332362 Dec 27 12:58:10 PM PST 23 Dec 27 12:58:21 PM PST 23 75407023 ps
T353 /workspace/coverage/default/101.edn_genbits.4084673180 Dec 27 12:59:06 PM PST 23 Dec 27 12:59:17 PM PST 23 29658915 ps
T779 /workspace/coverage/default/13.edn_intr.1859058571 Dec 27 12:58:03 PM PST 23 Dec 27 12:58:12 PM PST 23 25093053 ps
T780 /workspace/coverage/default/23.edn_genbits.79891391 Dec 27 12:58:14 PM PST 23 Dec 27 12:58:24 PM PST 23 64926806 ps
T781 /workspace/coverage/default/23.edn_err.1671877802 Dec 27 12:58:05 PM PST 23 Dec 27 12:58:13 PM PST 23 30892200 ps
T782 /workspace/coverage/default/257.edn_genbits.3001864708 Dec 27 12:58:59 PM PST 23 Dec 27 12:59:07 PM PST 23 17088294 ps
T783 /workspace/coverage/default/26.edn_smoke.2922860857 Dec 27 12:58:15 PM PST 23 Dec 27 12:58:26 PM PST 23 47724290 ps
T784 /workspace/coverage/default/38.edn_disable_auto_req_mode.2917531589 Dec 27 12:58:17 PM PST 23 Dec 27 12:58:27 PM PST 23 80764154 ps
T785 /workspace/coverage/default/152.edn_genbits.2367304679 Dec 27 12:59:11 PM PST 23 Dec 27 12:59:23 PM PST 23 29385887 ps
T786 /workspace/coverage/default/25.edn_genbits.365682562 Dec 27 12:58:14 PM PST 23 Dec 27 12:58:26 PM PST 23 172342836 ps
T787 /workspace/coverage/default/2.edn_stress_all.1806636200 Dec 27 12:57:23 PM PST 23 Dec 27 12:57:31 PM PST 23 193104067 ps
T788 /workspace/coverage/default/15.edn_alert_test.3672534774 Dec 27 12:57:59 PM PST 23 Dec 27 12:58:03 PM PST 23 23759176 ps
T789 /workspace/coverage/default/15.edn_err.443672050 Dec 27 12:58:05 PM PST 23 Dec 27 12:58:13 PM PST 23 118802785 ps
T790 /workspace/coverage/default/23.edn_stress_all_with_rand_reset.4161897723 Dec 27 12:58:42 PM PST 23 Dec 27 01:12:39 PM PST 23 73781473301 ps
T791 /workspace/coverage/default/82.edn_err.2761626314 Dec 27 12:58:51 PM PST 23 Dec 27 12:58:59 PM PST 23 71542317 ps
T792 /workspace/coverage/default/72.edn_genbits.1440172550 Dec 27 12:58:48 PM PST 23 Dec 27 12:58:59 PM PST 23 68698977 ps
T290 /workspace/coverage/default/28.edn_alert.3326621079 Dec 27 12:58:43 PM PST 23 Dec 27 12:58:52 PM PST 23 20044500 ps
T793 /workspace/coverage/default/16.edn_disable.2246348190 Dec 27 12:58:01 PM PST 23 Dec 27 12:58:08 PM PST 23 14307799 ps
T794 /workspace/coverage/default/4.edn_stress_all.1383216829 Dec 27 12:57:46 PM PST 23 Dec 27 12:57:49 PM PST 23 48682608 ps
T795 /workspace/coverage/default/15.edn_stress_all.1210930312 Dec 27 12:57:49 PM PST 23 Dec 27 12:57:52 PM PST 23 81101958 ps
T796 /workspace/coverage/default/8.edn_smoke.3144240651 Dec 27 12:57:55 PM PST 23 Dec 27 12:57:57 PM PST 23 34009241 ps
T797 /workspace/coverage/default/132.edn_genbits.1567804116 Dec 27 12:59:18 PM PST 23 Dec 27 12:59:30 PM PST 23 18195385 ps
T798 /workspace/coverage/default/31.edn_intr.1891957991 Dec 27 12:58:29 PM PST 23 Dec 27 12:58:40 PM PST 23 21590885 ps
T799 /workspace/coverage/default/34.edn_err.1932288674 Dec 27 12:58:40 PM PST 23 Dec 27 12:58:50 PM PST 23 48586888 ps
T800 /workspace/coverage/default/30.edn_disable.1997857137 Dec 27 12:58:37 PM PST 23 Dec 27 12:58:48 PM PST 23 11938609 ps
T801 /workspace/coverage/default/31.edn_disable_auto_req_mode.58014411 Dec 27 12:58:39 PM PST 23 Dec 27 12:58:48 PM PST 23 200473369 ps
T802 /workspace/coverage/default/1.edn_genbits.4189807335 Dec 27 12:57:57 PM PST 23 Dec 27 12:58:07 PM PST 23 24821610 ps
T803 /workspace/coverage/default/29.edn_stress_all_with_rand_reset.2603422806 Dec 27 12:58:14 PM PST 23 Dec 27 01:38:29 PM PST 23 159166519819 ps
T804 /workspace/coverage/default/119.edn_genbits.3548192073 Dec 27 12:59:07 PM PST 23 Dec 27 12:59:19 PM PST 23 36223052 ps
T114 /workspace/coverage/default/14.edn_disable.3677401582 Dec 27 12:58:12 PM PST 23 Dec 27 12:58:22 PM PST 23 70157750 ps
T805 /workspace/coverage/default/38.edn_alert.3914192900 Dec 27 12:58:37 PM PST 23 Dec 27 12:58:47 PM PST 23 20258688 ps
T157 /workspace/coverage/default/7.edn_disable.904808132 Dec 27 12:57:42 PM PST 23 Dec 27 12:57:50 PM PST 23 43988890 ps
T806 /workspace/coverage/default/245.edn_genbits.677933712 Dec 27 12:58:53 PM PST 23 Dec 27 12:59:10 PM PST 23 1215050848 ps
T807 /workspace/coverage/default/18.edn_stress_all_with_rand_reset.154830106 Dec 27 12:58:04 PM PST 23 Dec 27 01:24:53 PM PST 23 444231710948 ps
T808 /workspace/coverage/default/125.edn_genbits.3737136319 Dec 27 12:59:12 PM PST 23 Dec 27 12:59:23 PM PST 23 41652340 ps
T809 /workspace/coverage/default/86.edn_err.3124798560 Dec 27 12:58:53 PM PST 23 Dec 27 12:59:01 PM PST 23 20024070 ps
T810 /workspace/coverage/default/22.edn_genbits.2565762106 Dec 27 12:58:01 PM PST 23 Dec 27 12:58:10 PM PST 23 207469871 ps
T811 /workspace/coverage/default/36.edn_alert.3420194118 Dec 27 12:58:34 PM PST 23 Dec 27 12:58:45 PM PST 23 20380730 ps
T357 /workspace/coverage/default/51.edn_genbits.213707545 Dec 27 12:58:45 PM PST 23 Dec 27 12:58:54 PM PST 23 24534050 ps
T255 /workspace/coverage/default/45.edn_disable_auto_req_mode.4292134407 Dec 27 12:58:55 PM PST 23 Dec 27 12:59:03 PM PST 23 26558123 ps
T812 /workspace/coverage/default/42.edn_intr.985608325 Dec 27 12:58:48 PM PST 23 Dec 27 12:58:58 PM PST 23 19837698 ps
T813 /workspace/coverage/default/11.edn_genbits.1476253039 Dec 27 12:57:48 PM PST 23 Dec 27 12:57:50 PM PST 23 43480177 ps
T54 /workspace/coverage/default/0.edn_sec_cm.3559881146 Dec 27 12:57:54 PM PST 23 Dec 27 12:57:59 PM PST 23 177396809 ps
T112 /workspace/coverage/default/24.edn_disable.388446972 Dec 27 12:58:21 PM PST 23 Dec 27 12:58:35 PM PST 23 33881240 ps
T301 /workspace/coverage/default/5.edn_alert.893978696 Dec 27 12:57:43 PM PST 23 Dec 27 12:57:46 PM PST 23 18932655 ps
T814 /workspace/coverage/default/20.edn_intr.3044190131 Dec 27 12:58:41 PM PST 23 Dec 27 12:58:50 PM PST 23 20791289 ps
T815 /workspace/coverage/default/86.edn_genbits.25422248 Dec 27 12:59:12 PM PST 23 Dec 27 12:59:25 PM PST 23 157685248 ps
T816 /workspace/coverage/default/38.edn_stress_all.3712824188 Dec 27 12:58:32 PM PST 23 Dec 27 12:58:43 PM PST 23 112720319 ps
T150 /workspace/coverage/default/6.edn_err.1080451167 Dec 27 12:57:38 PM PST 23 Dec 27 12:57:42 PM PST 23 27411968 ps
T817 /workspace/coverage/default/30.edn_intr.2312829529 Dec 27 12:58:15 PM PST 23 Dec 27 12:58:26 PM PST 23 69994011 ps
T818 /workspace/coverage/default/58.edn_genbits.3960883106 Dec 27 12:58:22 PM PST 23 Dec 27 12:58:37 PM PST 23 44144635 ps
T819 /workspace/coverage/default/7.edn_smoke.2300514953 Dec 27 12:57:45 PM PST 23 Dec 27 12:57:48 PM PST 23 45129327 ps
T324 /workspace/coverage/default/218.edn_genbits.1074012225 Dec 27 12:59:05 PM PST 23 Dec 27 12:59:15 PM PST 23 15798771 ps
T820 /workspace/coverage/default/68.edn_err.1351468733 Dec 27 12:58:37 PM PST 23 Dec 27 12:58:48 PM PST 23 104210568 ps
T821 /workspace/coverage/default/38.edn_err.3986011589 Dec 27 12:58:23 PM PST 23 Dec 27 12:58:37 PM PST 23 42001769 ps
T822 /workspace/coverage/default/214.edn_genbits.2990907183 Dec 27 12:59:06 PM PST 23 Dec 27 12:59:18 PM PST 23 85984053 ps
T823 /workspace/coverage/default/193.edn_genbits.2141691854 Dec 27 12:59:08 PM PST 23 Dec 27 12:59:19 PM PST 23 31823338 ps
T824 /workspace/coverage/default/26.edn_genbits.3826316719 Dec 27 12:58:26 PM PST 23 Dec 27 12:58:40 PM PST 23 56983226 ps
T825 /workspace/coverage/default/89.edn_err.488435465 Dec 27 12:59:06 PM PST 23 Dec 27 12:59:22 PM PST 23 28973119 ps
T826 /workspace/coverage/default/251.edn_genbits.2854583861 Dec 27 12:59:11 PM PST 23 Dec 27 12:59:23 PM PST 23 28372910 ps
T827 /workspace/coverage/default/39.edn_intr.463423300 Dec 27 12:58:30 PM PST 23 Dec 27 12:58:40 PM PST 23 18944426 ps
T828 /workspace/coverage/default/76.edn_genbits.3762310835 Dec 27 12:58:38 PM PST 23 Dec 27 12:58:49 PM PST 23 92862007 ps
T829 /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1597803067 Dec 27 12:59:03 PM PST 23 Dec 27 01:20:03 PM PST 23 101750699602 ps
T830 /workspace/coverage/default/29.edn_disable_auto_req_mode.1262097357 Dec 27 12:58:13 PM PST 23 Dec 27 12:58:24 PM PST 23 37993213 ps
T831 /workspace/coverage/default/14.edn_stress_all_with_rand_reset.3217569407 Dec 27 12:58:00 PM PST 23 Dec 27 01:19:47 PM PST 23 248197655789 ps
T832 /workspace/coverage/default/3.edn_err.1817009280 Dec 27 12:57:36 PM PST 23 Dec 27 12:57:41 PM PST 23 20720071 ps
T833 /workspace/coverage/default/1.edn_stress_all_with_rand_reset.2658589221 Dec 27 12:58:03 PM PST 23 Dec 27 01:19:00 PM PST 23 114640210624 ps
T834 /workspace/coverage/default/43.edn_alert_test.4245746091 Dec 27 12:58:30 PM PST 23 Dec 27 12:58:40 PM PST 23 19830929 ps
T835 /workspace/coverage/default/110.edn_genbits.3359279851 Dec 27 12:59:10 PM PST 23 Dec 27 12:59:22 PM PST 23 59147007 ps
T836 /workspace/coverage/default/118.edn_genbits.1350463001 Dec 27 12:59:07 PM PST 23 Dec 27 12:59:18 PM PST 23 72162053 ps
T837 /workspace/coverage/default/35.edn_genbits.4276911495 Dec 27 12:58:24 PM PST 23 Dec 27 12:58:37 PM PST 23 31180134 ps
T838 /workspace/coverage/default/54.edn_genbits.271092198 Dec 27 12:58:22 PM PST 23 Dec 27 12:58:37 PM PST 23 26208632 ps
T839 /workspace/coverage/default/43.edn_genbits.2494183374 Dec 27 12:59:02 PM PST 23 Dec 27 12:59:11 PM PST 23 15839542 ps
T840 /workspace/coverage/default/29.edn_smoke.3383479141 Dec 27 12:58:25 PM PST 23 Dec 27 12:58:38 PM PST 23 45287280 ps
T841 /workspace/coverage/default/46.edn_intr.3312087527 Dec 27 12:59:13 PM PST 23 Dec 27 12:59:25 PM PST 23 19852175 ps
T842 /workspace/coverage/default/2.edn_intr.3750496708 Dec 27 12:57:44 PM PST 23 Dec 27 12:57:47 PM PST 23 31159781 ps
T843 /workspace/coverage/default/50.edn_genbits.1105679779 Dec 27 12:58:11 PM PST 23 Dec 27 12:58:22 PM PST 23 17644493 ps
T297 /workspace/coverage/default/34.edn_alert.3832857137 Dec 27 12:58:12 PM PST 23 Dec 27 12:58:27 PM PST 23 35496888 ps
T844 /workspace/coverage/default/49.edn_alert.1637201851 Dec 27 12:58:54 PM PST 23 Dec 27 12:59:02 PM PST 23 18266163 ps
T845 /workspace/coverage/default/25.edn_stress_all.590711771 Dec 27 12:58:10 PM PST 23 Dec 27 12:58:24 PM PST 23 1023381889 ps
T846 /workspace/coverage/default/188.edn_genbits.2726752122 Dec 27 12:59:46 PM PST 23 Dec 27 12:59:50 PM PST 23 25735889 ps
T847 /workspace/coverage/default/19.edn_disable_auto_req_mode.1015447706 Dec 27 12:58:12 PM PST 23 Dec 27 12:58:22 PM PST 23 26236594 ps
T848 /workspace/coverage/default/67.edn_genbits.2007214344 Dec 27 12:58:57 PM PST 23 Dec 27 12:59:05 PM PST 23 44925827 ps
T849 /workspace/coverage/default/37.edn_genbits.399587758 Dec 27 12:58:43 PM PST 23 Dec 27 12:58:52 PM PST 23 34878210 ps
T850 /workspace/coverage/default/47.edn_stress_all.108937134 Dec 27 12:58:52 PM PST 23 Dec 27 12:59:01 PM PST 23 71639265 ps
T851 /workspace/coverage/default/47.edn_stress_all_with_rand_reset.1027001806 Dec 27 12:58:31 PM PST 23 Dec 27 01:25:58 PM PST 23 738041142232 ps
T852 /workspace/coverage/default/31.edn_err.3096459639 Dec 27 12:58:11 PM PST 23 Dec 27 12:58:22 PM PST 23 39686559 ps
T853 /workspace/coverage/default/49.edn_genbits.1811358554 Dec 27 12:58:48 PM PST 23 Dec 27 12:58:58 PM PST 23 58524527 ps
T854 /workspace/coverage/default/153.edn_genbits.3148442147 Dec 27 12:59:10 PM PST 23 Dec 27 12:59:22 PM PST 23 21665888 ps
T855 /workspace/coverage/default/1.edn_intr.2362065493 Dec 27 12:57:59 PM PST 23 Dec 27 12:58:03 PM PST 23 22721865 ps
T249 /workspace/coverage/default/99.edn_err.218012634 Dec 27 12:59:11 PM PST 23 Dec 27 12:59:22 PM PST 23 42558110 ps
T336 /workspace/coverage/default/73.edn_genbits.1076614249 Dec 27 12:58:53 PM PST 23 Dec 27 12:59:01 PM PST 23 17953041 ps
T257 /workspace/coverage/default/55.edn_err.951815549 Dec 27 12:58:44 PM PST 23 Dec 27 12:58:52 PM PST 23 81083633 ps
T119 /workspace/coverage/default/43.edn_disable.3892750259 Dec 27 12:58:36 PM PST 23 Dec 27 12:58:46 PM PST 23 27787762 ps
T856 /workspace/coverage/default/114.edn_genbits.2302197450 Dec 27 12:59:02 PM PST 23 Dec 27 12:59:10 PM PST 23 282128464 ps
T857 /workspace/coverage/default/171.edn_genbits.1688919709 Dec 27 12:59:06 PM PST 23 Dec 27 12:59:16 PM PST 23 74259640 ps
T858 /workspace/coverage/default/43.edn_alert.2324204862 Dec 27 12:58:57 PM PST 23 Dec 27 12:59:05 PM PST 23 145414525 ps
T243 /workspace/coverage/default/1.edn_disable.1527485004 Dec 27 12:57:54 PM PST 23 Dec 27 12:57:56 PM PST 23 39270689 ps
T859 /workspace/coverage/default/87.edn_err.3365867972 Dec 27 12:59:19 PM PST 23 Dec 27 12:59:31 PM PST 23 22257852 ps
T860 /workspace/coverage/default/6.edn_smoke.2476099475 Dec 27 12:57:54 PM PST 23 Dec 27 12:57:56 PM PST 23 29816978 ps
T325 /workspace/coverage/default/254.edn_genbits.3099266931 Dec 27 12:59:08 PM PST 23 Dec 27 12:59:21 PM PST 23 13864531 ps
T861 /workspace/coverage/default/69.edn_genbits.228136504 Dec 27 12:58:40 PM PST 23 Dec 27 12:58:50 PM PST 23 16131953 ps
T862 /workspace/coverage/default/226.edn_genbits.733128726 Dec 27 12:59:20 PM PST 23 Dec 27 12:59:32 PM PST 23 17332857 ps
T863 /workspace/coverage/default/252.edn_genbits.3098392283 Dec 27 12:59:05 PM PST 23 Dec 27 12:59:15 PM PST 23 33847346 ps
T864 /workspace/coverage/default/35.edn_alert.254236203 Dec 27 12:58:14 PM PST 23 Dec 27 12:58:25 PM PST 23 67356078 ps
T865 /workspace/coverage/default/15.edn_intr.2319744621 Dec 27 12:57:49 PM PST 23 Dec 27 12:57:52 PM PST 23 18194374 ps
T256 /workspace/coverage/default/43.edn_disable_auto_req_mode.4038703579 Dec 27 12:58:46 PM PST 23 Dec 27 12:58:56 PM PST 23 27099691 ps
T866 /workspace/coverage/default/6.edn_genbits.2328219834 Dec 27 12:57:40 PM PST 23 Dec 27 12:57:43 PM PST 23 30516471 ps
T867 /workspace/coverage/default/232.edn_genbits.1646554140 Dec 27 12:59:06 PM PST 23 Dec 27 12:59:19 PM PST 23 418580916 ps
T868 /workspace/coverage/default/109.edn_genbits.1756452482 Dec 27 12:59:09 PM PST 23 Dec 27 12:59:21 PM PST 23 14380207 ps
T869 /workspace/coverage/default/1.edn_disable_auto_req_mode.1943581159 Dec 27 12:58:03 PM PST 23 Dec 27 12:58:12 PM PST 23 27685987 ps
T870 /workspace/coverage/default/237.edn_genbits.813858252 Dec 27 12:58:51 PM PST 23 Dec 27 12:58:59 PM PST 23 18855816 ps
T117 /workspace/coverage/default/25.edn_disable.3663027480 Dec 27 12:58:44 PM PST 23 Dec 27 12:58:52 PM PST 23 10582188 ps
T871 /workspace/coverage/default/189.edn_genbits.3530239801 Dec 27 12:59:03 PM PST 23 Dec 27 12:59:12 PM PST 23 32244498 ps
T872 /workspace/coverage/default/42.edn_stress_all.443598850 Dec 27 12:58:14 PM PST 23 Dec 27 12:58:27 PM PST 23 679762171 ps
T248 /workspace/coverage/default/8.edn_disable_auto_req_mode.2640542317 Dec 27 12:57:53 PM PST 23 Dec 27 12:57:55 PM PST 23 74818841 ps
T873 /workspace/coverage/default/10.edn_genbits.103797138 Dec 27 12:58:03 PM PST 23 Dec 27 12:58:12 PM PST 23 44007546 ps
T874 /workspace/coverage/default/12.edn_stress_all.40596727 Dec 27 12:58:12 PM PST 23 Dec 27 12:58:25 PM PST 23 322801127 ps
T875 /workspace/coverage/default/19.edn_intr.911264604 Dec 27 12:58:05 PM PST 23 Dec 27 12:58:13 PM PST 23 27275291 ps
T876 /workspace/coverage/default/211.edn_genbits.3494903683 Dec 27 12:59:16 PM PST 23 Dec 27 12:59:29 PM PST 23 16849378 ps
T341 /workspace/coverage/default/108.edn_genbits.3091903980 Dec 27 12:59:04 PM PST 23 Dec 27 12:59:13 PM PST 23 63885666 ps
T877 /workspace/coverage/default/173.edn_genbits.3734416434 Dec 27 12:59:12 PM PST 23 Dec 27 12:59:23 PM PST 23 150425556 ps
T878 /workspace/coverage/default/7.edn_err.3151955047 Dec 27 12:58:10 PM PST 23 Dec 27 12:58:25 PM PST 23 71359197 ps
T879 /workspace/coverage/default/15.edn_genbits.2503056791 Dec 27 12:57:48 PM PST 23 Dec 27 12:57:50 PM PST 23 62509937 ps
T880 /workspace/coverage/default/3.edn_smoke.2896867609 Dec 27 12:57:33 PM PST 23 Dec 27 12:57:39 PM PST 23 13197096 ps
T881 /workspace/coverage/default/142.edn_genbits.4112850067 Dec 27 12:59:10 PM PST 23 Dec 27 12:59:22 PM PST 23 21818974 ps
T882 /workspace/coverage/default/59.edn_err.2357038319 Dec 27 12:58:21 PM PST 23 Dec 27 12:58:36 PM PST 23 40024114 ps
T883 /workspace/coverage/default/104.edn_genbits.3764245904 Dec 27 12:59:08 PM PST 23 Dec 27 12:59:19 PM PST 23 75122385 ps
T884 /workspace/coverage/default/34.edn_smoke.515665061 Dec 27 12:58:47 PM PST 23 Dec 27 12:58:56 PM PST 23 40924240 ps
T885 /workspace/coverage/default/137.edn_genbits.1301224678 Dec 27 12:59:23 PM PST 23 Dec 27 12:59:34 PM PST 23 15554306 ps
T886 /workspace/coverage/default/1.edn_regwen.1112099271 Dec 27 12:58:05 PM PST 23 Dec 27 12:58:13 PM PST 23 43480054 ps
T887 /workspace/coverage/default/80.edn_err.3894861799 Dec 27 12:58:48 PM PST 23 Dec 27 12:58:58 PM PST 23 113677576 ps
T888 /workspace/coverage/default/11.edn_err.998619503 Dec 27 12:58:07 PM PST 23 Dec 27 12:58:13 PM PST 23 52407035 ps
T889 /workspace/coverage/default/79.edn_err.1536330673 Dec 27 12:58:35 PM PST 23 Dec 27 12:58:46 PM PST 23 18947896 ps
T890 /workspace/coverage/default/37.edn_disable.1337485069 Dec 27 12:58:47 PM PST 23 Dec 27 12:58:56 PM PST 23 15982252 ps
T891 /workspace/coverage/default/31.edn_disable.2779232091 Dec 27 12:58:08 PM PST 23 Dec 27 12:58:15 PM PST 23 11059774 ps
T892 /workspace/coverage/default/112.edn_genbits.763491985 Dec 27 12:59:18 PM PST 23 Dec 27 12:59:30 PM PST 23 99876758 ps
T893 /workspace/coverage/default/48.edn_alert.3550265974 Dec 27 12:58:58 PM PST 23 Dec 27 12:59:06 PM PST 23 53050512 ps
T894 /workspace/coverage/default/31.edn_alert.2459595401 Dec 27 12:58:12 PM PST 23 Dec 27 12:58:22 PM PST 23 25962069 ps
T895 /workspace/coverage/default/4.edn_stress_all_with_rand_reset.2906693523 Dec 27 12:57:47 PM PST 23 Dec 27 01:21:21 PM PST 23 64825275877 ps
T896 /workspace/coverage/default/40.edn_disable_auto_req_mode.3283765417 Dec 27 12:58:40 PM PST 23 Dec 27 12:58:49 PM PST 23 57939661 ps
T897 /workspace/coverage/default/220.edn_genbits.1878916494 Dec 27 12:59:00 PM PST 23 Dec 27 12:59:08 PM PST 23 71615942 ps
T898 /workspace/coverage/default/11.edn_stress_all_with_rand_reset.3210453506 Dec 27 12:58:06 PM PST 23 Dec 27 01:04:52 PM PST 23 18564575527 ps
T899 /workspace/coverage/default/90.edn_genbits.2873994614 Dec 27 12:59:01 PM PST 23 Dec 27 12:59:09 PM PST 23 25311749 ps
T900 /workspace/coverage/default/113.edn_genbits.2461286779 Dec 27 12:59:05 PM PST 23 Dec 27 12:59:14 PM PST 23 18548402 ps
T901 /workspace/coverage/default/2.edn_disable_auto_req_mode.174749365 Dec 27 12:57:30 PM PST 23 Dec 27 12:57:37 PM PST 23 150165231 ps
T902 /workspace/coverage/default/84.edn_err.1764883174 Dec 27 12:58:58 PM PST 23 Dec 27 12:59:06 PM PST 23 33615060 ps
T903 /workspace/coverage/default/203.edn_genbits.3846849390 Dec 27 12:59:13 PM PST 23 Dec 27 12:59:25 PM PST 23 23853607 ps
T904 /workspace/coverage/default/39.edn_stress_all_with_rand_reset.4134251282 Dec 27 12:58:25 PM PST 23 Dec 27 01:07:36 PM PST 23 20864667701 ps
T905 /workspace/coverage/default/130.edn_genbits.1623897268 Dec 27 12:59:05 PM PST 23 Dec 27 12:59:15 PM PST 23 97980108 ps
T906 /workspace/coverage/default/53.edn_genbits.2643140749 Dec 27 12:58:39 PM PST 23 Dec 27 12:58:49 PM PST 23 17252819 ps
T907 /workspace/coverage/default/47.edn_intr.126003246 Dec 27 12:58:57 PM PST 23 Dec 27 12:59:04 PM PST 23 20337142 ps
T908 /workspace/coverage/default/41.edn_disable_auto_req_mode.2635808457 Dec 27 12:58:35 PM PST 23 Dec 27 12:58:46 PM PST 23 27778604 ps
T909 /workspace/coverage/default/6.edn_stress_all.1776153225 Dec 27 12:57:34 PM PST 23 Dec 27 12:57:41 PM PST 23 201905198 ps
T910 /workspace/coverage/default/94.edn_genbits.1081438234 Dec 27 12:59:16 PM PST 23 Dec 27 12:59:28 PM PST 23 56340236 ps
T911 /workspace/coverage/default/31.edn_stress_all_with_rand_reset.2029456504 Dec 27 12:58:20 PM PST 23 Dec 27 01:29:01 PM PST 23 182858181776 ps
T912 /workspace/coverage/default/221.edn_genbits.300667945 Dec 27 12:59:15 PM PST 23 Dec 27 12:59:28 PM PST 23 17413757 ps
T913 /workspace/coverage/default/49.edn_disable.3795572289 Dec 27 12:58:42 PM PST 23 Dec 27 12:58:50 PM PST 23 42393286 ps
T914 /workspace/coverage/default/172.edn_genbits.2826027121 Dec 27 12:59:09 PM PST 23 Dec 27 12:59:21 PM PST 23 84826666 ps
T915 /workspace/coverage/default/234.edn_genbits.1198940619 Dec 27 12:59:05 PM PST 23 Dec 27 12:59:14 PM PST 23 112336746 ps
T916 /workspace/coverage/default/16.edn_alert.1224407952 Dec 27 12:58:10 PM PST 23 Dec 27 12:58:20 PM PST 23 17733140 ps
T917 /workspace/coverage/default/3.edn_genbits.2288583567 Dec 27 12:57:58 PM PST 23 Dec 27 12:58:01 PM PST 23 21967600 ps
T918 /workspace/coverage/default/95.edn_genbits.4117332009 Dec 27 12:58:53 PM PST 23 Dec 27 12:59:01 PM PST 23 16729456 ps
T919 /workspace/coverage/default/16.edn_intr.625747478 Dec 27 12:58:02 PM PST 23 Dec 27 12:58:10 PM PST 23 19038615 ps
T920 /workspace/coverage/default/61.edn_genbits.2248162138 Dec 27 12:58:55 PM PST 23 Dec 27 12:59:02 PM PST 23 106741112 ps
T921 /workspace/coverage/default/255.edn_genbits.1797717599 Dec 27 12:59:09 PM PST 23 Dec 27 12:59:21 PM PST 23 190748340 ps
T922 /workspace/coverage/default/81.edn_err.1525300066 Dec 27 12:58:30 PM PST 23 Dec 27 12:58:40 PM PST 23 44146814 ps
T923 /workspace/coverage/default/10.edn_smoke.3388950270 Dec 27 12:57:55 PM PST 23 Dec 27 12:57:58 PM PST 23 122814166 ps
T924 /workspace/coverage/default/32.edn_stress_all.1036698488 Dec 27 12:58:23 PM PST 23 Dec 27 12:58:37 PM PST 23 30116879 ps
T925 /workspace/coverage/default/37.edn_alert_test.2653794675 Dec 27 12:58:42 PM PST 23 Dec 27 12:58:51 PM PST 23 32720764 ps
T926 /workspace/coverage/default/144.edn_genbits.3109030297 Dec 27 12:58:58 PM PST 23 Dec 27 12:59:06 PM PST 23 20641974 ps
T927 /workspace/coverage/default/247.edn_genbits.1042728391 Dec 27 12:58:58 PM PST 23 Dec 27 12:59:06 PM PST 23 34406000 ps
T928 /workspace/coverage/default/3.edn_alert_test.3076609786 Dec 27 12:58:01 PM PST 23 Dec 27 12:58:08 PM PST 23 18385995 ps
T355 /workspace/coverage/default/222.edn_genbits.3619159297 Dec 27 12:59:13 PM PST 23 Dec 27 12:59:25 PM PST 23 65132241 ps
T929 /workspace/coverage/default/91.edn_genbits.3815334352 Dec 27 12:58:59 PM PST 23 Dec 27 12:59:08 PM PST 23 16103646 ps
T930 /workspace/coverage/default/85.edn_genbits.3593700742 Dec 27 12:59:05 PM PST 23 Dec 27 12:59:15 PM PST 23 17240383 ps
T931 /workspace/coverage/default/31.edn_smoke.1526588606 Dec 27 12:58:46 PM PST 23 Dec 27 12:58:55 PM PST 23 12820243 ps
T932 /workspace/coverage/default/227.edn_genbits.1865189703 Dec 27 12:59:06 PM PST 23 Dec 27 12:59:16 PM PST 23 38617774 ps
T298 /workspace/coverage/default/8.edn_alert.1029596634 Dec 27 12:57:55 PM PST 23 Dec 27 12:57:57 PM PST 23 19564000 ps
T933 /workspace/coverage/default/11.edn_alert.690381596 Dec 27 12:58:00 PM PST 23 Dec 27 12:58:04 PM PST 23 20324022 ps
T934 /workspace/coverage/default/47.edn_alert_test.4097734172 Dec 27 12:58:37 PM PST 23 Dec 27 12:58:48 PM PST 23 13138081 ps
T935 /workspace/coverage/default/17.edn_intr.497343409 Dec 27 12:58:17 PM PST 23 Dec 27 12:58:27 PM PST 23 18240811 ps
T936 /workspace/coverage/default/294.edn_genbits.1985190387 Dec 27 12:59:04 PM PST 23 Dec 27 12:59:15 PM PST 23 45715625 ps
T293 /workspace/coverage/default/47.edn_alert.3426350788 Dec 27 12:58:46 PM PST 23 Dec 27 12:58:55 PM PST 23 32151312 ps
T937 /workspace/coverage/default/16.edn_stress_all.2100738567 Dec 27 12:58:01 PM PST 23 Dec 27 12:58:08 PM PST 23 270265141 ps
T938 /workspace/coverage/default/7.edn_intr.2865237454 Dec 27 12:58:03 PM PST 23 Dec 27 12:58:11 PM PST 23 22807640 ps
T939 /workspace/coverage/default/26.edn_stress_all_with_rand_reset.986733957 Dec 27 12:58:11 PM PST 23 Dec 27 01:19:05 PM PST 23 314114926109 ps
T940 /workspace/coverage/default/39.edn_stress_all.674210190 Dec 27 12:58:19 PM PST 23 Dec 27 12:58:35 PM PST 23 186678269 ps
T251 /workspace/coverage/default/56.edn_err.718327353 Dec 27 12:58:26 PM PST 23 Dec 27 12:58:39 PM PST 23 23109131 ps
T941 /workspace/coverage/default/45.edn_stress_all.1193492879 Dec 27 12:58:51 PM PST 23 Dec 27 12:59:02 PM PST 23 315142789 ps
T942 /workspace/coverage/default/23.edn_disable_auto_req_mode.1882750914 Dec 27 12:58:15 PM PST 23 Dec 27 12:58:26 PM PST 23 49851062 ps
T146 /workspace/coverage/default/46.edn_disable_auto_req_mode.564431016 Dec 27 12:58:41 PM PST 23 Dec 27 12:58:50 PM PST 23 38695883 ps
T943 /workspace/coverage/default/6.edn_disable_auto_req_mode.4122369422 Dec 27 12:57:51 PM PST 23 Dec 27 12:57:54 PM PST 23 38224917 ps
T944 /workspace/coverage/default/298.edn_genbits.2292972827 Dec 27 12:58:59 PM PST 23 Dec 27 12:59:07 PM PST 23 52341887 ps
T945 /workspace/coverage/default/195.edn_genbits.3052182466 Dec 27 12:59:04 PM PST 23 Dec 27 12:59:13 PM PST 23 17633162 ps
T946 /workspace/coverage/default/8.edn_stress_all.1711279140 Dec 27 12:57:46 PM PST 23 Dec 27 12:57:50 PM PST 23 195239584 ps
T947 /workspace/coverage/default/133.edn_genbits.3627919640 Dec 27 12:59:05 PM PST 23 Dec 27 12:59:15 PM PST 23 37288667 ps
T948 /workspace/coverage/default/19.edn_stress_all_with_rand_reset.886683012 Dec 27 12:58:06 PM PST 23 Dec 27 01:16:53 PM PST 23 84345946307 ps
T949 /workspace/coverage/default/24.edn_stress_all.663459155 Dec 27 12:58:13 PM PST 23 Dec 27 12:58:27 PM PST 23 1448580981 ps
T950 /workspace/coverage/default/24.edn_alert.380184280 Dec 27 12:58:10 PM PST 23 Dec 27 12:58:21 PM PST 23 48874491 ps
T951 /workspace/coverage/default/47.edn_err.2822407797 Dec 27 12:58:31 PM PST 23 Dec 27 12:58:41 PM PST 23 54508626 ps
T952 /workspace/coverage/default/45.edn_err.3878460562 Dec 27 12:58:40 PM PST 23 Dec 27 12:58:50 PM PST 23 20587073 ps
T953 /workspace/coverage/default/129.edn_genbits.3063342680 Dec 27 12:59:15 PM PST 23 Dec 27 12:59:28 PM PST 23 26999109 ps
T954 /workspace/coverage/default/48.edn_err.2537980718 Dec 27 12:58:36 PM PST 23 Dec 27 12:58:46 PM PST 23 23166541 ps
T955 /workspace/coverage/default/35.edn_disable.981688342 Dec 27 12:58:42 PM PST 23 Dec 27 12:58:50 PM PST 23 21527818 ps
T956 /workspace/coverage/default/186.edn_genbits.3335176737 Dec 27 12:58:58 PM PST 23 Dec 27 12:59:06 PM PST 23 85762921 ps
T957 /workspace/coverage/default/24.edn_genbits.1094396519 Dec 27 12:58:10 PM PST 23 Dec 27 12:58:21 PM PST 23 18872484 ps
T958 /workspace/coverage/default/46.edn_disable.1084331743 Dec 27 12:58:46 PM PST 23 Dec 27 12:58:56 PM PST 23 15755294 ps
T959 /workspace/coverage/default/51.edn_err.1913798345 Dec 27 12:58:21 PM PST 23 Dec 27 12:58:36 PM PST 23 66258492 ps
T960 /workspace/coverage/default/27.edn_smoke.2887190687 Dec 27 12:58:41 PM PST 23 Dec 27 12:58:50 PM PST 23 43446208 ps
T961 /workspace/coverage/default/8.edn_intr.1091986653 Dec 27 12:57:43 PM PST 23 Dec 27 12:57:46 PM PST 23 19024164 ps
T962 /workspace/coverage/default/22.edn_disable_auto_req_mode.4028236390 Dec 27 12:58:12 PM PST 23 Dec 27 12:58:22 PM PST 23 21911316 ps
T963 /workspace/coverage/default/23.edn_alert_test.783105108 Dec 27 12:58:12 PM PST 23 Dec 27 12:58:23 PM PST 23 14630529 ps
T964 /workspace/coverage/default/28.edn_disable_auto_req_mode.1330632926 Dec 27 12:58:36 PM PST 23 Dec 27 12:58:46 PM PST 23 38200666 ps
T965 /workspace/coverage/default/17.edn_err.2336623810 Dec 27 12:58:42 PM PST 23 Dec 27 12:58:51 PM PST 23 18333725 ps
T966 /workspace/coverage/default/75.edn_genbits.3492620504 Dec 27 12:58:40 PM PST 23 Dec 27 12:58:49 PM PST 23 25263506 ps
T967 /workspace/coverage/default/140.edn_genbits.3823769124 Dec 27 12:59:13 PM PST 23 Dec 27 12:59:25 PM PST 23 14996781 ps
T968 /workspace/coverage/default/20.edn_smoke.1600390398 Dec 27 12:58:05 PM PST 23 Dec 27 12:58:13 PM PST 23 28214609 ps
T969 /workspace/coverage/default/35.edn_intr.786923460 Dec 27 12:58:44 PM PST 23 Dec 27 12:58:53 PM PST 23 31701352 ps
T970 /workspace/coverage/default/42.edn_disable.1251240303 Dec 27 12:58:30 PM PST 23 Dec 27 12:58:46 PM PST 23 16397803 ps
T971 /workspace/coverage/default/22.edn_stress_all.2971933523 Dec 27 12:58:30 PM PST 23 Dec 27 12:58:42 PM PST 23 389254988 ps
T972 /workspace/coverage/default/42.edn_genbits.483107492 Dec 27 12:58:28 PM PST 23 Dec 27 12:58:48 PM PST 23 1253548186 ps
T973 /workspace/coverage/default/26.edn_alert_test.1474344281 Dec 27 12:58:42 PM PST 23 Dec 27 12:58:51 PM PST 23 22336762 ps
T974 /workspace/coverage/default/18.edn_stress_all.1593000083 Dec 27 12:58:04 PM PST 23 Dec 27 12:58:14 PM PST 23 65276417 ps
T975 /workspace/coverage/default/100.edn_genbits.2525320095 Dec 27 12:59:43 PM PST 23 Dec 27 12:59:47 PM PST 23 18385496 ps
T976 /workspace/coverage/default/10.edn_stress_all_with_rand_reset.159713270 Dec 27 12:58:04 PM PST 23 Dec 27 01:14:46 PM PST 23 93621711397 ps
T977 /workspace/coverage/default/25.edn_alert_test.2961752761 Dec 27 12:58:21 PM PST 23 Dec 27 12:58:35 PM PST 23 37526595 ps

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.3990541965
Short name T5
Test name
Test status
Simulation time 40476495994 ps
CPU time 1035.73 seconds
Started Dec 27 12:58:01 PM PST 23
Finished Dec 27 01:15:22 PM PST 23
Peak memory 216864 kb
Host smart-e1ecee57-328c-4519-923f-6fb22e0de49d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990541965 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.3990541965
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/145.edn_genbits.4262608040
Short name T11
Test name
Test status
Simulation time 25102242 ps
CPU time 1.18 seconds
Started Dec 27 12:58:59 PM PST 23
Finished Dec 27 12:59:07 PM PST 23
Peak memory 214140 kb
Host smart-f6ffeca9-6632-4d6d-9f9b-4f97a217f97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262608040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.4262608040
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.3645441014
Short name T15
Test name
Test status
Simulation time 28858760 ps
CPU time 1.26 seconds
Started Dec 27 12:58:51 PM PST 23
Finished Dec 27 12:59:00 PM PST 23
Peak memory 221736 kb
Host smart-2554f59a-5ddc-4749-a28e-315afeb8f920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645441014 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.3645441014
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/2.edn_sec_cm.3793255269
Short name T22
Test name
Test status
Simulation time 390310054 ps
CPU time 6.26 seconds
Started Dec 27 12:57:39 PM PST 23
Finished Dec 27 12:57:48 PM PST 23
Peak memory 234608 kb
Host smart-382495c1-250f-4081-aa3a-046b2408682d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793255269 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.3793255269
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.1996344878
Short name T29
Test name
Test status
Simulation time 285774025 ps
CPU time 1.17 seconds
Started Dec 27 12:57:54 PM PST 23
Finished Dec 27 12:57:57 PM PST 23
Peak memory 214472 kb
Host smart-5df8be2f-710d-4fc0-8e81-3171a743e7fb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996344878 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.1996344878
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1572119662
Short name T121
Test name
Test status
Simulation time 139345657 ps
CPU time 2.46 seconds
Started Dec 27 12:38:08 PM PST 23
Finished Dec 27 12:38:23 PM PST 23
Peak memory 205984 kb
Host smart-0f4d0ca2-2ef4-4519-9cd2-6a708d0e5d5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572119662 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1572119662
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/default/15.edn_disable.183978600
Short name T161
Test name
Test status
Simulation time 12429642 ps
CPU time 0.86 seconds
Started Dec 27 12:57:42 PM PST 23
Finished Dec 27 12:57:45 PM PST 23
Peak memory 214208 kb
Host smart-8c67c9ea-d7b2-4e4e-864a-b49d0aa1f7df
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183978600 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.183978600
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/32.edn_err.2576074707
Short name T85
Test name
Test status
Simulation time 88863309 ps
CPU time 0.95 seconds
Started Dec 27 12:58:14 PM PST 23
Finished Dec 27 12:58:25 PM PST 23
Peak memory 214720 kb
Host smart-aafeec74-589a-464a-822f-a393cbe470f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576074707 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.2576074707
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/22.edn_alert.2886209785
Short name T17
Test name
Test status
Simulation time 32094138 ps
CPU time 0.97 seconds
Started Dec 27 12:58:14 PM PST 23
Finished Dec 27 12:58:33 PM PST 23
Peak memory 205896 kb
Host smart-79f819b9-d112-4266-a753-07cccd6f963f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886209785 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.2886209785
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/34.edn_disable.3133181490
Short name T73
Test name
Test status
Simulation time 12195545 ps
CPU time 0.85 seconds
Started Dec 27 12:58:59 PM PST 23
Finished Dec 27 12:59:07 PM PST 23
Peak memory 214340 kb
Host smart-ae80cc8a-86c3-4a2f-822d-7a4ce2962a1b
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133181490 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.3133181490
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_intr.2003198585
Short name T4
Test name
Test status
Simulation time 27796123 ps
CPU time 0.86 seconds
Started Dec 27 12:58:14 PM PST 23
Finished Dec 27 12:58:25 PM PST 23
Peak memory 214328 kb
Host smart-c73d457c-db26-4c88-9710-aeaec068af37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003198585 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.2003198585
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.1322582878
Short name T126
Test name
Test status
Simulation time 59500542 ps
CPU time 1.04 seconds
Started Dec 27 12:57:42 PM PST 23
Finished Dec 27 12:57:45 PM PST 23
Peak memory 214532 kb
Host smart-ea105979-d7bc-470a-af48-a7c7c033a953
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322582878 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.1322582878
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.4243675490
Short name T203
Test name
Test status
Simulation time 78169551 ps
CPU time 0.79 seconds
Started Dec 27 12:37:01 PM PST 23
Finished Dec 27 12:37:27 PM PST 23
Peak memory 205764 kb
Host smart-bc243562-fe23-40ea-b8d6-f347fe5bf025
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243675490 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.4243675490
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.1776007812
Short name T113
Test name
Test status
Simulation time 23138394 ps
CPU time 1 seconds
Started Dec 27 12:58:45 PM PST 23
Finished Dec 27 12:58:54 PM PST 23
Peak memory 206372 kb
Host smart-c2b996dc-24aa-4b18-a8b2-89e1eb53c543
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776007812 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.1776007812
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_disable.1527485004
Short name T243
Test name
Test status
Simulation time 39270689 ps
CPU time 0.87 seconds
Started Dec 27 12:57:54 PM PST 23
Finished Dec 27 12:57:56 PM PST 23
Peak memory 214264 kb
Host smart-3821fabd-d130-4cdf-8d00-034dee0c43d9
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527485004 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.1527485004
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable.3557830764
Short name T80
Test name
Test status
Simulation time 13935286 ps
CPU time 0.96 seconds
Started Dec 27 12:58:23 PM PST 23
Finished Dec 27 12:58:37 PM PST 23
Peak memory 214452 kb
Host smart-b888b0d0-e888-4151-a107-5279e8ee36e4
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557830764 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.3557830764
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/146.edn_genbits.1058996787
Short name T27
Test name
Test status
Simulation time 40002415 ps
CPU time 1.38 seconds
Started Dec 27 12:59:05 PM PST 23
Finished Dec 27 12:59:15 PM PST 23
Peak memory 205804 kb
Host smart-bbe4d0f7-fd44-4e15-92c2-726132b31660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058996787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.1058996787
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_regwen.1112099271
Short name T886
Test name
Test status
Simulation time 43480054 ps
CPU time 0.9 seconds
Started Dec 27 12:58:05 PM PST 23
Finished Dec 27 12:58:13 PM PST 23
Peak memory 204640 kb
Host smart-b552d117-9a11-428d-968e-2dd524694204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112099271 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.1112099271
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_disable.1090575527
Short name T247
Test name
Test status
Simulation time 15933283 ps
CPU time 0.86 seconds
Started Dec 27 12:57:50 PM PST 23
Finished Dec 27 12:57:52 PM PST 23
Peak memory 214352 kb
Host smart-a8f7eed5-05a4-4422-a995-bb3313c18c4e
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090575527 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.1090575527
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable.539079103
Short name T148
Test name
Test status
Simulation time 98009880 ps
CPU time 0.83 seconds
Started Dec 27 12:58:05 PM PST 23
Finished Dec 27 12:58:13 PM PST 23
Peak memory 214320 kb
Host smart-c445bbbc-3e2c-483e-a25e-4d127d653c84
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539079103 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.539079103
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/167.edn_genbits.3721928127
Short name T318
Test name
Test status
Simulation time 17649094 ps
CPU time 1.05 seconds
Started Dec 27 12:59:08 PM PST 23
Finished Dec 27 12:59:19 PM PST 23
Peak memory 204804 kb
Host smart-ce65ba03-cb73-4bba-81cc-3e7126109ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721928127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.3721928127
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.603478704
Short name T178
Test name
Test status
Simulation time 343819399 ps
CPU time 3.67 seconds
Started Dec 27 12:36:25 PM PST 23
Finished Dec 27 12:36:51 PM PST 23
Peak memory 214244 kb
Host smart-7ca2ca9c-0c37-408d-8695-f709de695382
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603478704 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.603478704
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.1972574286
Short name T39
Test name
Test status
Simulation time 81516099 ps
CPU time 1.06 seconds
Started Dec 27 12:58:11 PM PST 23
Finished Dec 27 12:58:25 PM PST 23
Peak memory 214500 kb
Host smart-1125f5cd-27d3-4e93-8e71-2e5415f1ee46
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972574286 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.1972574286
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/192.edn_genbits.1293999307
Short name T287
Test name
Test status
Simulation time 17414870 ps
CPU time 1.09 seconds
Started Dec 27 12:59:00 PM PST 23
Finished Dec 27 12:59:09 PM PST 23
Peak memory 205736 kb
Host smart-82af89ab-7862-4608-be36-a3760cba56b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293999307 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.1293999307
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/280.edn_genbits.3405228239
Short name T316
Test name
Test status
Simulation time 106767833 ps
CPU time 1.52 seconds
Started Dec 27 12:59:33 PM PST 23
Finished Dec 27 12:59:41 PM PST 23
Peak memory 214188 kb
Host smart-fa50c7d1-8c93-4b0a-bddf-28dc52b58f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405228239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.3405228239
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_disable.3663027480
Short name T117
Test name
Test status
Simulation time 10582188 ps
CPU time 0.84 seconds
Started Dec 27 12:58:44 PM PST 23
Finished Dec 27 12:58:52 PM PST 23
Peak memory 214236 kb
Host smart-666e5102-6f23-4a3e-a838-b19161807702
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663027480 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.3663027480
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable.2163509983
Short name T118
Test name
Test status
Simulation time 29792161 ps
CPU time 0.81 seconds
Started Dec 27 12:59:01 PM PST 23
Finished Dec 27 12:59:09 PM PST 23
Peak memory 214320 kb
Host smart-36e5073e-c59e-45c6-a428-ade7585ba516
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163509983 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.2163509983
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.183361320
Short name T104
Test name
Test status
Simulation time 29913761 ps
CPU time 0.95 seconds
Started Dec 27 12:58:45 PM PST 23
Finished Dec 27 12:58:55 PM PST 23
Peak memory 206224 kb
Host smart-464bc56f-612c-43f3-95bd-cd36e65f61d7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183361320 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_di
sable_auto_req_mode.183361320
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_disable.1047157611
Short name T155
Test name
Test status
Simulation time 13488560 ps
CPU time 0.89 seconds
Started Dec 27 12:58:00 PM PST 23
Finished Dec 27 12:58:04 PM PST 23
Peak memory 214496 kb
Host smart-d7d92dda-1221-494a-b25a-61cd9cb9b77f
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047157611 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.1047157611
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.3216574578
Short name T137
Test name
Test status
Simulation time 46824654 ps
CPU time 1.03 seconds
Started Dec 27 12:58:08 PM PST 23
Finished Dec 27 12:58:15 PM PST 23
Peak memory 214600 kb
Host smart-f79b47f0-4a2b-4f92-b9a6-ec8a6e85d8c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216574578 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.3216574578
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.2761659289
Short name T37
Test name
Test status
Simulation time 66469755 ps
CPU time 1.06 seconds
Started Dec 27 12:57:47 PM PST 23
Finished Dec 27 12:57:50 PM PST 23
Peak memory 214556 kb
Host smart-d9a98391-be4a-4abc-981b-f9efde7ef9b8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761659289 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.2761659289
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.4038703579
Short name T256
Test name
Test status
Simulation time 27099691 ps
CPU time 1.05 seconds
Started Dec 27 12:58:46 PM PST 23
Finished Dec 27 12:58:56 PM PST 23
Peak memory 214520 kb
Host smart-d1971d68-6144-426a-acc1-3925c9cadaa3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038703579 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.4038703579
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_disable.3266209986
Short name T115
Test name
Test status
Simulation time 40366766 ps
CPU time 0.85 seconds
Started Dec 27 12:57:50 PM PST 23
Finished Dec 27 12:57:52 PM PST 23
Peak memory 214312 kb
Host smart-eff5eccc-49b6-40e1-80fc-b9ea4b6e44bc
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266209986 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.3266209986
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.820746911
Short name T521
Test name
Test status
Simulation time 130558009463 ps
CPU time 1234.73 seconds
Started Dec 27 12:57:40 PM PST 23
Finished Dec 27 01:18:17 PM PST 23
Peak memory 217308 kb
Host smart-aed60996-61ae-4600-abf5-f518d047aa47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820746911 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.820746911
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.edn_regwen.2328095756
Short name T49
Test name
Test status
Simulation time 35099785 ps
CPU time 0.81 seconds
Started Dec 27 12:57:45 PM PST 23
Finished Dec 27 12:57:47 PM PST 23
Peak memory 204828 kb
Host smart-14a67c77-c43b-422d-844b-ad9ba1e554a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328095756 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.2328095756
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/19.edn_intr.911264604
Short name T875
Test name
Test status
Simulation time 27275291 ps
CPU time 0.87 seconds
Started Dec 27 12:58:05 PM PST 23
Finished Dec 27 12:58:13 PM PST 23
Peak memory 214236 kb
Host smart-38062898-89fe-4ac3-95e1-5491706eb53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911264604 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.911264604
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/14.edn_err.3079712409
Short name T81
Test name
Test status
Simulation time 129854642 ps
CPU time 1.21 seconds
Started Dec 27 12:58:13 PM PST 23
Finished Dec 27 12:58:24 PM PST 23
Peak memory 214624 kb
Host smart-0c018c2e-2e89-4812-a6b9-8c2cd4ef8531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079712409 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.3079712409
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/0.edn_alert.3698378592
Short name T294
Test name
Test status
Simulation time 18479915 ps
CPU time 0.98 seconds
Started Dec 27 12:57:57 PM PST 23
Finished Dec 27 12:58:00 PM PST 23
Peak memory 205212 kb
Host smart-53bb08d0-c330-4d85-b53f-6ca4bb4b1b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698378592 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.3698378592
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert.3815645571
Short name T308
Test name
Test status
Simulation time 35387213 ps
CPU time 0.98 seconds
Started Dec 27 12:57:41 PM PST 23
Finished Dec 27 12:57:45 PM PST 23
Peak memory 205116 kb
Host smart-510ca5be-06f7-423b-a0d2-8c5f23455b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815645571 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.3815645571
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert.177996989
Short name T260
Test name
Test status
Simulation time 19445058 ps
CPU time 1.02 seconds
Started Dec 27 12:57:38 PM PST 23
Finished Dec 27 12:57:42 PM PST 23
Peak memory 205256 kb
Host smart-a3179156-f775-4eed-b1e0-cd46243563d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177996989 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.177996989
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_genbits.999424879
Short name T286
Test name
Test status
Simulation time 49121145 ps
CPU time 1.32 seconds
Started Dec 27 12:58:03 PM PST 23
Finished Dec 27 12:58:11 PM PST 23
Peak memory 214188 kb
Host smart-c1ab91bd-b17a-4bf2-ab1e-bf1ef2353423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999424879 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.999424879
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.3228595800
Short name T335
Test name
Test status
Simulation time 40708152 ps
CPU time 1.11 seconds
Started Dec 27 12:59:03 PM PST 23
Finished Dec 27 12:59:12 PM PST 23
Peak memory 205592 kb
Host smart-31a4f37b-a726-4ec7-bb47-6b59afadf0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228595800 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.3228595800
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1669822007
Short name T200
Test name
Test status
Simulation time 50807720 ps
CPU time 1.58 seconds
Started Dec 27 12:36:38 PM PST 23
Finished Dec 27 12:37:08 PM PST 23
Peak memory 205908 kb
Host smart-f38decd8-2703-4fdf-99be-eaa478f06093
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669822007 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.1669822007
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/default/101.edn_genbits.4084673180
Short name T353
Test name
Test status
Simulation time 29658915 ps
CPU time 0.9 seconds
Started Dec 27 12:59:06 PM PST 23
Finished Dec 27 12:59:17 PM PST 23
Peak memory 204984 kb
Host smart-14ceef1d-42f7-4a18-848b-b56aa31cde60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084673180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.4084673180
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.2764547517
Short name T62
Test name
Test status
Simulation time 19379286 ps
CPU time 1.01 seconds
Started Dec 27 12:59:06 PM PST 23
Finished Dec 27 12:59:16 PM PST 23
Peak memory 205128 kb
Host smart-ad592d7c-ada8-4bfb-a2de-dbc1225e513e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764547517 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.2764547517
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.3091903980
Short name T341
Test name
Test status
Simulation time 63885666 ps
CPU time 0.97 seconds
Started Dec 27 12:59:04 PM PST 23
Finished Dec 27 12:59:13 PM PST 23
Peak memory 205568 kb
Host smart-e5778ef3-666f-4606-9113-917cf20757f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091903980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.3091903980
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.1116905776
Short name T350
Test name
Test status
Simulation time 27875506 ps
CPU time 0.9 seconds
Started Dec 27 12:59:14 PM PST 23
Finished Dec 27 12:59:25 PM PST 23
Peak memory 204916 kb
Host smart-30065a6c-3ff7-4916-824e-e44f0089bef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116905776 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.1116905776
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.3979161312
Short name T561
Test name
Test status
Simulation time 67925443 ps
CPU time 0.99 seconds
Started Dec 27 12:59:07 PM PST 23
Finished Dec 27 12:59:18 PM PST 23
Peak memory 205644 kb
Host smart-0d26b07c-8c7c-4f66-afc2-07efa0e48613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979161312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.3979161312
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_regwen.3251889648
Short name T302
Test name
Test status
Simulation time 114779729 ps
CPU time 0.79 seconds
Started Dec 27 12:58:09 PM PST 23
Finished Dec 27 12:58:19 PM PST 23
Peak memory 204712 kb
Host smart-639c39ad-1bbb-46dd-9599-e170667c3694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251889648 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.3251889648
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/219.edn_genbits.4105965194
Short name T333
Test name
Test status
Simulation time 73587297 ps
CPU time 2.82 seconds
Started Dec 27 12:58:59 PM PST 23
Finished Dec 27 12:59:10 PM PST 23
Peak memory 214184 kb
Host smart-4366d72c-4c85-4c22-99eb-48de304a2a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105965194 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.4105965194
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_genbits.1686171709
Short name T326
Test name
Test status
Simulation time 52138433 ps
CPU time 2.13 seconds
Started Dec 27 12:58:20 PM PST 23
Finished Dec 27 12:58:35 PM PST 23
Peak memory 214100 kb
Host smart-8b9bcc85-dc79-46e9-a487-5fbd5b5ca346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686171709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.1686171709
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.1419096429
Short name T346
Test name
Test status
Simulation time 17244195 ps
CPU time 0.94 seconds
Started Dec 27 12:58:55 PM PST 23
Finished Dec 27 12:59:02 PM PST 23
Peak memory 204932 kb
Host smart-46bb3248-04ea-498e-b602-0a0759db31cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419096429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.1419096429
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2764433362
Short name T494
Test name
Test status
Simulation time 65440429078 ps
CPU time 1215.84 seconds
Started Dec 27 12:58:20 PM PST 23
Finished Dec 27 01:18:49 PM PST 23
Peak memory 215908 kb
Host smart-d8e0a17f-428f-47fc-96ee-1be920c210a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764433362 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.2764433362
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.edn_regwen.1383217935
Short name T292
Test name
Test status
Simulation time 49920251 ps
CPU time 0.88 seconds
Started Dec 27 12:57:25 PM PST 23
Finished Dec 27 12:57:32 PM PST 23
Peak memory 204968 kb
Host smart-dccee75f-68b5-4fb0-af93-9099e799e9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383217935 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.1383217935
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_alert_test.1773913577
Short name T460
Test name
Test status
Simulation time 73482610 ps
CPU time 0.92 seconds
Started Dec 27 12:57:48 PM PST 23
Finished Dec 27 12:57:50 PM PST 23
Peak memory 204648 kb
Host smart-dca8d1e4-7b18-4927-af61-81e19ad3c4df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773913577 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.1773913577
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1836228155
Short name T210
Test name
Test status
Simulation time 33285916 ps
CPU time 1.94 seconds
Started Dec 27 12:36:47 PM PST 23
Finished Dec 27 12:37:17 PM PST 23
Peak memory 205912 kb
Host smart-074e63a7-3c80-48a3-a56f-1422557438ac
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836228155 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.1836228155
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/default/0.edn_intr.2063510874
Short name T547
Test name
Test status
Simulation time 17428824 ps
CPU time 1.01 seconds
Started Dec 27 12:58:00 PM PST 23
Finished Dec 27 12:58:03 PM PST 23
Peak memory 214496 kb
Host smart-54fbfe0f-f36c-42c6-b28b-6ee1161d3d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063510874 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.2063510874
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3349328460
Short name T269
Test name
Test status
Simulation time 81335598 ps
CPU time 2.21 seconds
Started Dec 27 12:37:14 PM PST 23
Finished Dec 27 12:37:41 PM PST 23
Peak memory 205996 kb
Host smart-61133877-19c7-459d-b281-1c056cb1e3f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349328460 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.3349328460
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/default/10.edn_stress_all.308757359
Short name T653
Test name
Test status
Simulation time 31672405 ps
CPU time 1.22 seconds
Started Dec 27 12:58:08 PM PST 23
Finished Dec 27 12:58:16 PM PST 23
Peak memory 204964 kb
Host smart-1c4f1f2c-685c-4aad-84d5-9ba67dcdcf59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308757359 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.308757359
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/104.edn_genbits.3764245904
Short name T883
Test name
Test status
Simulation time 75122385 ps
CPU time 1.09 seconds
Started Dec 27 12:59:08 PM PST 23
Finished Dec 27 12:59:19 PM PST 23
Peak memory 205364 kb
Host smart-e07f6a9d-c9c7-4fa0-b030-aba76a2d0799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764245904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.3764245904
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.3087689589
Short name T694
Test name
Test status
Simulation time 64517910 ps
CPU time 0.97 seconds
Started Dec 27 12:59:22 PM PST 23
Finished Dec 27 12:59:33 PM PST 23
Peak memory 205000 kb
Host smart-fd48915a-edc5-4213-94b0-7c0c4db9d483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087689589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.3087689589
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.883438580
Short name T330
Test name
Test status
Simulation time 59442764 ps
CPU time 0.98 seconds
Started Dec 27 12:59:03 PM PST 23
Finished Dec 27 12:59:13 PM PST 23
Peak memory 205588 kb
Host smart-9b40817d-a7af-4b44-bdb6-d7c5ce3c7a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883438580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.883438580
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.1434301401
Short name T477
Test name
Test status
Simulation time 252143123 ps
CPU time 3.68 seconds
Started Dec 27 12:59:12 PM PST 23
Finished Dec 27 12:59:26 PM PST 23
Peak memory 214180 kb
Host smart-9d7471a4-c317-4157-9c27-304511e2affd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434301401 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.1434301401
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.2583281774
Short name T323
Test name
Test status
Simulation time 15440220 ps
CPU time 0.94 seconds
Started Dec 27 12:59:09 PM PST 23
Finished Dec 27 12:59:21 PM PST 23
Peak memory 205044 kb
Host smart-b4d4445b-76f7-4d62-bf1c-d48750592070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583281774 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.2583281774
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.2612018092
Short name T67
Test name
Test status
Simulation time 257819350 ps
CPU time 3.84 seconds
Started Dec 27 12:59:00 PM PST 23
Finished Dec 27 12:59:12 PM PST 23
Peak memory 214068 kb
Host smart-dadbb87f-f551-4988-88f3-e8282fe85505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612018092 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.2612018092
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.3619159297
Short name T355
Test name
Test status
Simulation time 65132241 ps
CPU time 0.9 seconds
Started Dec 27 12:59:13 PM PST 23
Finished Dec 27 12:59:25 PM PST 23
Peak memory 205072 kb
Host smart-10a97c09-17e2-42e9-8bef-9e2be68e99d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619159297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.3619159297
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_regwen.882778562
Short name T267
Test name
Test status
Simulation time 25654466 ps
CPU time 0.91 seconds
Started Dec 27 12:57:49 PM PST 23
Finished Dec 27 12:57:52 PM PST 23
Peak memory 204868 kb
Host smart-f11d1147-b9f8-4959-9963-928f019864ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882778562 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.882778562
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/259.edn_genbits.2043982171
Short name T74
Test name
Test status
Simulation time 26345491 ps
CPU time 1.37 seconds
Started Dec 27 12:58:54 PM PST 23
Finished Dec 27 12:59:02 PM PST 23
Peak memory 214148 kb
Host smart-97c385f9-9870-4f5e-8ed4-38fb0f182acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043982171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.2043982171
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_disable.3059860160
Short name T109
Test name
Test status
Simulation time 68373442 ps
CPU time 0.84 seconds
Started Dec 27 12:58:25 PM PST 23
Finished Dec 27 12:58:38 PM PST 23
Peak memory 214300 kb
Host smart-d071717b-194f-42e7-85ec-4c7354fd9b80
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059860160 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.3059860160
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable.3681091162
Short name T68
Test name
Test status
Simulation time 28677362 ps
CPU time 0.81 seconds
Started Dec 27 12:58:32 PM PST 23
Finished Dec 27 12:58:41 PM PST 23
Peak memory 214232 kb
Host smart-9fb1d6f5-b85c-4721-9399-ec35b0bf034d
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681091162 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.3681091162
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.616209653
Short name T211
Test name
Test status
Simulation time 254119240 ps
CPU time 1.42 seconds
Started Dec 27 12:36:41 PM PST 23
Finished Dec 27 12:37:12 PM PST 23
Peak memory 205948 kb
Host smart-844b160b-fe75-492e-8f65-0e13dbb87571
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616209653 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.616209653
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.5401947
Short name T403
Test name
Test status
Simulation time 506979605 ps
CPU time 6.12 seconds
Started Dec 27 12:36:25 PM PST 23
Finished Dec 27 12:36:53 PM PST 23
Peak memory 205868 kb
Host smart-5fff3a46-4cea-4190-bad1-2fe722868b37
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5401947 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.5401947
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3572504569
Short name T227
Test name
Test status
Simulation time 55045755 ps
CPU time 0.92 seconds
Started Dec 27 12:36:42 PM PST 23
Finished Dec 27 12:37:12 PM PST 23
Peak memory 205996 kb
Host smart-2dc784a1-08e3-4e66-ad4b-67e50a7fbb3c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572504569 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.3572504569
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2770991206
Short name T190
Test name
Test status
Simulation time 32405901 ps
CPU time 1.06 seconds
Started Dec 27 12:36:29 PM PST 23
Finished Dec 27 12:36:54 PM PST 23
Peak memory 215872 kb
Host smart-a5db0e3c-36d0-4f5c-9322-c0d828c417c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770991206 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.2770991206
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.4050424818
Short name T407
Test name
Test status
Simulation time 25765378 ps
CPU time 0.84 seconds
Started Dec 27 12:36:36 PM PST 23
Finished Dec 27 12:37:06 PM PST 23
Peak memory 205904 kb
Host smart-3f2392c5-7b70-4d9a-84e4-6c86bd2bbeeb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050424818 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.4050424818
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.268494888
Short name T216
Test name
Test status
Simulation time 32946186 ps
CPU time 0.76 seconds
Started Dec 27 12:36:25 PM PST 23
Finished Dec 27 12:36:47 PM PST 23
Peak memory 205832 kb
Host smart-9210fef7-9e82-4fd6-b101-7268de4a4245
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268494888 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.268494888
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2613063495
Short name T229
Test name
Test status
Simulation time 20589107 ps
CPU time 0.95 seconds
Started Dec 27 12:36:39 PM PST 23
Finished Dec 27 12:37:10 PM PST 23
Peak memory 205940 kb
Host smart-ba76d3cb-f8c4-480a-9192-0e2c23e6abda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613063495 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.2613063495
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.3892755833
Short name T366
Test name
Test status
Simulation time 69478287 ps
CPU time 2.37 seconds
Started Dec 27 12:36:30 PM PST 23
Finished Dec 27 12:36:58 PM PST 23
Peak memory 214052 kb
Host smart-36e71dc5-d5e8-4e03-90da-a690113b8855
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892755833 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3892755833
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2410010602
Short name T204
Test name
Test status
Simulation time 280235686 ps
CPU time 1.32 seconds
Started Dec 27 12:37:24 PM PST 23
Finished Dec 27 12:37:43 PM PST 23
Peak memory 205916 kb
Host smart-22f965f6-3f29-41f6-9f5e-33794032f72c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410010602 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.2410010602
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3184646687
Short name T384
Test name
Test status
Simulation time 52328962 ps
CPU time 0.88 seconds
Started Dec 27 12:36:25 PM PST 23
Finished Dec 27 12:36:48 PM PST 23
Peak memory 205912 kb
Host smart-24ea999c-9852-4586-852c-aed9062caeef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184646687 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.3184646687
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1055099005
Short name T390
Test name
Test status
Simulation time 128743640 ps
CPU time 1.34 seconds
Started Dec 27 12:36:55 PM PST 23
Finished Dec 27 12:37:22 PM PST 23
Peak memory 214248 kb
Host smart-9348db91-f588-444a-850e-8d8a2999d29c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055099005 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.1055099005
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.2262369823
Short name T379
Test name
Test status
Simulation time 13881384 ps
CPU time 0.84 seconds
Started Dec 27 12:36:46 PM PST 23
Finished Dec 27 12:37:15 PM PST 23
Peak memory 205936 kb
Host smart-8b3c1573-9f36-430e-b803-d518a3b6c41e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262369823 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.2262369823
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.1799753951
Short name T417
Test name
Test status
Simulation time 33564965 ps
CPU time 0.73 seconds
Started Dec 27 12:36:44 PM PST 23
Finished Dec 27 12:37:14 PM PST 23
Peak memory 205824 kb
Host smart-a951a0bd-9e7f-4268-82e7-3a3cd85b526e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799753951 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.1799753951
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.106241994
Short name T392
Test name
Test status
Simulation time 48732596 ps
CPU time 0.96 seconds
Started Dec 27 12:36:43 PM PST 23
Finished Dec 27 12:37:14 PM PST 23
Peak memory 205948 kb
Host smart-7ae53d64-37cb-4194-a14c-d0d67b3bf845
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106241994 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_out
standing.106241994
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.2075387104
Short name T172
Test name
Test status
Simulation time 225780037 ps
CPU time 2.52 seconds
Started Dec 27 12:36:36 PM PST 23
Finished Dec 27 12:37:07 PM PST 23
Peak memory 214316 kb
Host smart-b960e491-2214-4f46-8bfb-27c7ae14d55f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075387104 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.2075387104
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.4025148363
Short name T398
Test name
Test status
Simulation time 53855218 ps
CPU time 1.52 seconds
Started Dec 27 12:39:08 PM PST 23
Finished Dec 27 12:39:31 PM PST 23
Peak memory 205808 kb
Host smart-3ed1f27c-df2f-4687-a6d6-5cc4811f49cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025148363 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.4025148363
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1015721204
Short name T180
Test name
Test status
Simulation time 61999609 ps
CPU time 0.98 seconds
Started Dec 27 12:36:54 PM PST 23
Finished Dec 27 12:37:21 PM PST 23
Peak memory 214124 kb
Host smart-65dd3b57-3a7b-4246-abd9-a26669162a82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015721204 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.1015721204
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.543038997
Short name T231
Test name
Test status
Simulation time 25242314 ps
CPU time 0.85 seconds
Started Dec 27 12:37:00 PM PST 23
Finished Dec 27 12:37:27 PM PST 23
Peak memory 205984 kb
Host smart-562da08a-f6ca-4c6f-b375-886cae5a19b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543038997 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.543038997
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.2697430122
Short name T449
Test name
Test status
Simulation time 47406223 ps
CPU time 0.83 seconds
Started Dec 27 12:36:46 PM PST 23
Finished Dec 27 12:37:15 PM PST 23
Peak memory 205924 kb
Host smart-51e38759-19ab-4b53-a77c-841fc7546aa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697430122 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2697430122
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1518044366
Short name T201
Test name
Test status
Simulation time 62231672 ps
CPU time 1.09 seconds
Started Dec 27 12:36:59 PM PST 23
Finished Dec 27 12:37:25 PM PST 23
Peak memory 205992 kb
Host smart-b0e01d7a-c542-4a8b-8914-06349a04ecf3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518044366 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.1518044366
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.4246393062
Short name T445
Test name
Test status
Simulation time 18552087 ps
CPU time 1.4 seconds
Started Dec 27 12:36:39 PM PST 23
Finished Dec 27 12:37:10 PM PST 23
Peak memory 214224 kb
Host smart-a2d1229a-69b7-4d7f-a181-aa03ef223371
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246393062 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.4246393062
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1432409018
Short name T435
Test name
Test status
Simulation time 78723239 ps
CPU time 2.24 seconds
Started Dec 27 12:36:26 PM PST 23
Finished Dec 27 12:36:51 PM PST 23
Peak memory 205932 kb
Host smart-ff627d99-a92b-4d3c-8f6f-bacb1a3fc249
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432409018 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.1432409018
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3431640479
Short name T413
Test name
Test status
Simulation time 28632394 ps
CPU time 0.96 seconds
Started Dec 27 12:37:00 PM PST 23
Finished Dec 27 12:37:26 PM PST 23
Peak memory 205972 kb
Host smart-8bb055c5-44ad-4e69-9e0e-bff0eb47558d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431640479 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3431640479
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.837740803
Short name T208
Test name
Test status
Simulation time 18282174 ps
CPU time 0.96 seconds
Started Dec 27 12:36:29 PM PST 23
Finished Dec 27 12:36:53 PM PST 23
Peak memory 205916 kb
Host smart-49fd4758-a75f-497f-b23b-ed0b652e786d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837740803 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.837740803
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.694571171
Short name T441
Test name
Test status
Simulation time 44725383 ps
CPU time 0.81 seconds
Started Dec 27 12:36:51 PM PST 23
Finished Dec 27 12:37:18 PM PST 23
Peak memory 205880 kb
Host smart-b90d4d07-c6d9-4dc8-90f5-9a1c7320489c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694571171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.694571171
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1466475730
Short name T202
Test name
Test status
Simulation time 27693911 ps
CPU time 1.07 seconds
Started Dec 27 12:37:02 PM PST 23
Finished Dec 27 12:37:28 PM PST 23
Peak memory 205892 kb
Host smart-91019b36-3d4a-4d88-92d3-98f3fe6ab114
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466475730 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.1466475730
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.3238297851
Short name T438
Test name
Test status
Simulation time 2011964712 ps
CPU time 4.79 seconds
Started Dec 27 12:36:37 PM PST 23
Finished Dec 27 12:37:10 PM PST 23
Peak memory 214100 kb
Host smart-252d26a9-8d3a-4717-a118-a2d30ae6242f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238297851 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.3238297851
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2136602108
Short name T386
Test name
Test status
Simulation time 56263412 ps
CPU time 1.72 seconds
Started Dec 27 12:36:37 PM PST 23
Finished Dec 27 12:37:08 PM PST 23
Peak memory 205964 kb
Host smart-66bf00ab-8f7b-4261-a445-7b702557f7c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136602108 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.2136602108
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2092256586
Short name T181
Test name
Test status
Simulation time 19963292 ps
CPU time 0.94 seconds
Started Dec 27 12:37:18 PM PST 23
Finished Dec 27 12:37:39 PM PST 23
Peak memory 205952 kb
Host smart-8641871a-5ff4-4d4e-842e-3c38256e93dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092256586 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.2092256586
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.2108940137
Short name T430
Test name
Test status
Simulation time 42606726 ps
CPU time 0.81 seconds
Started Dec 27 12:36:56 PM PST 23
Finished Dec 27 12:37:22 PM PST 23
Peak memory 205728 kb
Host smart-47a300dc-ee2d-4e4b-87fe-1e0006fa89fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108940137 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.2108940137
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.1063017332
Short name T225
Test name
Test status
Simulation time 124234771 ps
CPU time 0.81 seconds
Started Dec 27 12:36:55 PM PST 23
Finished Dec 27 12:37:21 PM PST 23
Peak memory 205904 kb
Host smart-a1e463fe-87a7-442d-bc26-5688eef7c804
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063017332 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.1063017332
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.777022743
Short name T415
Test name
Test status
Simulation time 108957936 ps
CPU time 1.28 seconds
Started Dec 27 12:37:51 PM PST 23
Finished Dec 27 12:37:56 PM PST 23
Peak memory 205996 kb
Host smart-afd5a55d-d79d-4a03-a43e-1d6e47283187
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777022743 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_ou
tstanding.777022743
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1956864817
Short name T427
Test name
Test status
Simulation time 307134826 ps
CPU time 1.59 seconds
Started Dec 27 12:36:58 PM PST 23
Finished Dec 27 12:37:24 PM PST 23
Peak memory 206048 kb
Host smart-c258ba3e-ed7d-46a8-b25f-bb5ddd53bd67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956864817 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.1956864817
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1548064984
Short name T24
Test name
Test status
Simulation time 60189960 ps
CPU time 1.03 seconds
Started Dec 27 12:38:07 PM PST 23
Finished Dec 27 12:38:14 PM PST 23
Peak memory 206124 kb
Host smart-cc44bfc9-91a8-4840-8c1b-711f15da69a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548064984 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.1548064984
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.2519694538
Short name T410
Test name
Test status
Simulation time 14802131 ps
CPU time 0.92 seconds
Started Dec 27 12:36:36 PM PST 23
Finished Dec 27 12:37:06 PM PST 23
Peak memory 205980 kb
Host smart-9f54394d-80a2-43bb-9024-72a2dd365631
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519694538 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.2519694538
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.3017806950
Short name T422
Test name
Test status
Simulation time 18968299 ps
CPU time 0.83 seconds
Started Dec 27 12:37:16 PM PST 23
Finished Dec 27 12:37:37 PM PST 23
Peak memory 205892 kb
Host smart-7558647c-e6de-4c14-8626-218d8b308206
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017806950 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.3017806950
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.1002654783
Short name T232
Test name
Test status
Simulation time 158813370 ps
CPU time 0.92 seconds
Started Dec 27 12:37:13 PM PST 23
Finished Dec 27 12:37:36 PM PST 23
Peak memory 205916 kb
Host smart-54e59f72-8b94-43c9-9013-2b1ff2a12aa9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002654783 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.1002654783
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.3760866227
Short name T169
Test name
Test status
Simulation time 22362720 ps
CPU time 1.45 seconds
Started Dec 27 12:36:28 PM PST 23
Finished Dec 27 12:36:52 PM PST 23
Peak memory 216512 kb
Host smart-0101ba00-d0c8-4c0b-886c-060e6a0d8c62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760866227 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.3760866227
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1768113932
Short name T401
Test name
Test status
Simulation time 95446068 ps
CPU time 1.65 seconds
Started Dec 27 12:37:11 PM PST 23
Finished Dec 27 12:37:35 PM PST 23
Peak memory 205904 kb
Host smart-fc597a46-dc63-4eb8-aab0-2520c38e01d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768113932 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1768113932
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.522798128
Short name T183
Test name
Test status
Simulation time 16378780 ps
CPU time 0.93 seconds
Started Dec 27 12:37:13 PM PST 23
Finished Dec 27 12:37:36 PM PST 23
Peak memory 206040 kb
Host smart-a18225d4-e8bd-4da2-bf2d-eb57fbc1ad19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522798128 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.522798128
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.4200531513
Short name T214
Test name
Test status
Simulation time 13218233 ps
CPU time 0.86 seconds
Started Dec 27 12:36:45 PM PST 23
Finished Dec 27 12:37:15 PM PST 23
Peak memory 205844 kb
Host smart-608d0c1d-a2ee-4c0e-ba57-e0acb524afc2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200531513 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.4200531513
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.398078327
Short name T452
Test name
Test status
Simulation time 12581417 ps
CPU time 0.89 seconds
Started Dec 27 12:37:23 PM PST 23
Finished Dec 27 12:37:42 PM PST 23
Peak memory 205992 kb
Host smart-6e782e09-aec8-4d33-a105-7b8e9638e104
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398078327 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.398078327
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.952947621
Short name T400
Test name
Test status
Simulation time 14719140 ps
CPU time 0.95 seconds
Started Dec 27 12:37:16 PM PST 23
Finished Dec 27 12:37:37 PM PST 23
Peak memory 205888 kb
Host smart-76795092-9c13-418a-9c64-947f062fa57a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952947621 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_ou
tstanding.952947621
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.2654342389
Short name T198
Test name
Test status
Simulation time 118319655 ps
CPU time 4.14 seconds
Started Dec 27 12:37:32 PM PST 23
Finished Dec 27 12:37:51 PM PST 23
Peak memory 214188 kb
Host smart-79d99150-0198-4a5c-a7e3-1a292cb15c25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654342389 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.2654342389
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.4033911758
Short name T372
Test name
Test status
Simulation time 67962792 ps
CPU time 1.33 seconds
Started Dec 27 12:36:52 PM PST 23
Finished Dec 27 12:37:20 PM PST 23
Peak memory 214260 kb
Host smart-d3168a90-9deb-4c84-9e95-7c5db4b50915
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033911758 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.4033911758
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.1914492820
Short name T233
Test name
Test status
Simulation time 11623956 ps
CPU time 0.81 seconds
Started Dec 27 12:36:46 PM PST 23
Finished Dec 27 12:37:15 PM PST 23
Peak memory 205920 kb
Host smart-bb9d4f09-ec86-450e-92d6-e80372788fd2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914492820 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.1914492820
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.1907119379
Short name T388
Test name
Test status
Simulation time 21560020 ps
CPU time 0.86 seconds
Started Dec 27 12:36:51 PM PST 23
Finished Dec 27 12:37:18 PM PST 23
Peak memory 205900 kb
Host smart-2cda7743-eed5-4fa0-9033-9bd2a19bc242
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907119379 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.1907119379
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1534490403
Short name T439
Test name
Test status
Simulation time 19023922 ps
CPU time 1.1 seconds
Started Dec 27 12:37:26 PM PST 23
Finished Dec 27 12:37:43 PM PST 23
Peak memory 206004 kb
Host smart-148eb6bc-65ea-4521-8fa4-780912c02bb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534490403 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.1534490403
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.2121530734
Short name T375
Test name
Test status
Simulation time 103013501 ps
CPU time 3.66 seconds
Started Dec 27 12:37:14 PM PST 23
Finished Dec 27 12:37:42 PM PST 23
Peak memory 214244 kb
Host smart-e8f140ac-d444-4c76-9e79-fedffc76ff25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121530734 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.2121530734
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1338873414
Short name T268
Test name
Test status
Simulation time 96164212 ps
CPU time 2.43 seconds
Started Dec 27 12:37:09 PM PST 23
Finished Dec 27 12:37:34 PM PST 23
Peak memory 205988 kb
Host smart-72a77cbe-ac86-45a8-bdf1-4f4f90eb64ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338873414 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.1338873414
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1972594623
Short name T396
Test name
Test status
Simulation time 69006203 ps
CPU time 1.31 seconds
Started Dec 27 12:36:59 PM PST 23
Finished Dec 27 12:37:25 PM PST 23
Peak memory 214148 kb
Host smart-11aeda56-72e6-4cad-b784-708a68287369
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972594623 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.1972594623
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.4052693543
Short name T41
Test name
Test status
Simulation time 111473927 ps
CPU time 0.79 seconds
Started Dec 27 12:37:46 PM PST 23
Finished Dec 27 12:37:53 PM PST 23
Peak memory 205876 kb
Host smart-8b8b080e-98bc-45ff-ae1d-aa55dfa19abc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052693543 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.4052693543
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3319089660
Short name T416
Test name
Test status
Simulation time 31188567 ps
CPU time 1.29 seconds
Started Dec 27 12:36:36 PM PST 23
Finished Dec 27 12:37:06 PM PST 23
Peak memory 205872 kb
Host smart-26b89147-a6f6-4754-acde-0f0b69d70020
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319089660 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.3319089660
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.2117134196
Short name T176
Test name
Test status
Simulation time 107094765 ps
CPU time 3.43 seconds
Started Dec 27 12:36:41 PM PST 23
Finished Dec 27 12:37:14 PM PST 23
Peak memory 214332 kb
Host smart-bcd91d6f-1eb4-49fa-9b80-7b8204a5b3d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117134196 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.2117134196
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2825558279
Short name T192
Test name
Test status
Simulation time 108057483 ps
CPU time 2.36 seconds
Started Dec 27 12:37:10 PM PST 23
Finished Dec 27 12:37:35 PM PST 23
Peak memory 205964 kb
Host smart-307f3547-a9a1-487f-a7ea-d57ada080d3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825558279 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.2825558279
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1407875244
Short name T414
Test name
Test status
Simulation time 72710391 ps
CPU time 1.02 seconds
Started Dec 27 12:37:18 PM PST 23
Finished Dec 27 12:37:39 PM PST 23
Peak memory 214180 kb
Host smart-55cb7374-0921-4d4a-89f6-ae3201ccd5e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407875244 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.1407875244
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.3178441620
Short name T429
Test name
Test status
Simulation time 11893743 ps
CPU time 0.84 seconds
Started Dec 27 12:37:07 PM PST 23
Finished Dec 27 12:37:31 PM PST 23
Peak memory 205988 kb
Host smart-29dc155b-5853-4a11-b5f0-4c268349d1cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178441620 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.3178441620
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.2910302078
Short name T437
Test name
Test status
Simulation time 13117494 ps
CPU time 0.83 seconds
Started Dec 27 12:37:01 PM PST 23
Finished Dec 27 12:37:27 PM PST 23
Peak memory 205864 kb
Host smart-1fbb54d1-c5b6-46d3-8f1a-c8fe004b5ef4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910302078 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.2910302078
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2703853443
Short name T399
Test name
Test status
Simulation time 301692206 ps
CPU time 1.02 seconds
Started Dec 27 12:36:28 PM PST 23
Finished Dec 27 12:36:52 PM PST 23
Peak memory 206004 kb
Host smart-3613e7c8-96ac-448c-8603-431e407fbb44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703853443 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.2703853443
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.538096136
Short name T432
Test name
Test status
Simulation time 120950400 ps
CPU time 1.97 seconds
Started Dec 27 12:36:55 PM PST 23
Finished Dec 27 12:37:22 PM PST 23
Peak memory 214272 kb
Host smart-45af865b-d2d6-4214-99ea-553b216b35fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538096136 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.538096136
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.393035612
Short name T394
Test name
Test status
Simulation time 414970971 ps
CPU time 2.53 seconds
Started Dec 27 12:37:25 PM PST 23
Finished Dec 27 12:37:44 PM PST 23
Peak memory 205892 kb
Host smart-25592720-2ccf-4881-a399-295116d12a02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393035612 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.393035612
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.4066515614
Short name T424
Test name
Test status
Simulation time 47307095 ps
CPU time 1.22 seconds
Started Dec 27 12:37:29 PM PST 23
Finished Dec 27 12:37:45 PM PST 23
Peak memory 214156 kb
Host smart-a20051f5-91ce-4c69-9626-6252591326ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066515614 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.4066515614
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.2631712369
Short name T434
Test name
Test status
Simulation time 23948511 ps
CPU time 0.8 seconds
Started Dec 27 12:37:08 PM PST 23
Finished Dec 27 12:37:32 PM PST 23
Peak memory 205808 kb
Host smart-57299055-082d-4992-ab5c-c33feb6a7a54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631712369 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.2631712369
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.1679992383
Short name T411
Test name
Test status
Simulation time 38984287 ps
CPU time 0.78 seconds
Started Dec 27 12:37:11 PM PST 23
Finished Dec 27 12:37:34 PM PST 23
Peak memory 205692 kb
Host smart-59a79318-d3f4-4af7-b936-4e1610ed1812
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679992383 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.1679992383
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2954059340
Short name T378
Test name
Test status
Simulation time 18396482 ps
CPU time 1 seconds
Started Dec 27 12:38:15 PM PST 23
Finished Dec 27 12:38:23 PM PST 23
Peak memory 205104 kb
Host smart-33171be6-7f52-405c-86eb-59ea849d0890
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954059340 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.2954059340
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.3181794798
Short name T404
Test name
Test status
Simulation time 26185520 ps
CPU time 1.57 seconds
Started Dec 27 12:36:58 PM PST 23
Finished Dec 27 12:37:25 PM PST 23
Peak memory 214248 kb
Host smart-15e39dbd-d2c3-4c55-b7dc-52ffb01e585a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181794798 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3181794798
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1439486325
Short name T219
Test name
Test status
Simulation time 73979686 ps
CPU time 1.41 seconds
Started Dec 27 12:36:54 PM PST 23
Finished Dec 27 12:37:21 PM PST 23
Peak memory 205988 kb
Host smart-6cc0db7c-198b-49a6-bf84-5d67d6541869
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439486325 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1439486325
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.639806749
Short name T369
Test name
Test status
Simulation time 17561917 ps
CPU time 1.18 seconds
Started Dec 27 12:36:46 PM PST 23
Finished Dec 27 12:37:15 PM PST 23
Peak memory 214128 kb
Host smart-2ce4b719-05ef-4303-9f4c-49775bcc733d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639806749 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.639806749
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.165742165
Short name T364
Test name
Test status
Simulation time 16250480 ps
CPU time 0.89 seconds
Started Dec 27 12:37:06 PM PST 23
Finished Dec 27 12:37:31 PM PST 23
Peak memory 205928 kb
Host smart-33d9f384-6280-436c-83b9-97cac089858b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165742165 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.165742165
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.724192380
Short name T187
Test name
Test status
Simulation time 13499560 ps
CPU time 0.78 seconds
Started Dec 27 12:37:20 PM PST 23
Finished Dec 27 12:37:40 PM PST 23
Peak memory 205728 kb
Host smart-76e92617-d0ad-4217-ba4b-40f05008af0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724192380 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.724192380
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3927286593
Short name T370
Test name
Test status
Simulation time 21700363 ps
CPU time 1.04 seconds
Started Dec 27 12:37:18 PM PST 23
Finished Dec 27 12:37:39 PM PST 23
Peak memory 205940 kb
Host smart-eaa79f56-e40d-4330-aa5a-df9e0ca203bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927286593 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.3927286593
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.1953901583
Short name T179
Test name
Test status
Simulation time 158941434 ps
CPU time 4.37 seconds
Started Dec 27 12:36:35 PM PST 23
Finished Dec 27 12:37:08 PM PST 23
Peak memory 214144 kb
Host smart-09aada09-f565-497a-821e-891d4770b230
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953901583 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1953901583
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3339059164
Short name T442
Test name
Test status
Simulation time 53917506 ps
CPU time 0.95 seconds
Started Dec 27 12:36:48 PM PST 23
Finished Dec 27 12:37:17 PM PST 23
Peak memory 206004 kb
Host smart-28163838-9d76-430d-a527-e147e7fe9681
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339059164 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.3339059164
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.847780288
Short name T193
Test name
Test status
Simulation time 144901932 ps
CPU time 3.18 seconds
Started Dec 27 12:36:56 PM PST 23
Finished Dec 27 12:37:29 PM PST 23
Peak memory 205936 kb
Host smart-d7a1dcda-1190-492f-85f8-0be7c65db1b5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847780288 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.847780288
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.339184826
Short name T436
Test name
Test status
Simulation time 30973691 ps
CPU time 0.92 seconds
Started Dec 27 12:36:28 PM PST 23
Finished Dec 27 12:36:52 PM PST 23
Peak memory 206012 kb
Host smart-3af070fa-f57c-4c4f-bd53-f4ea6ab97207
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339184826 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.339184826
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3127982576
Short name T224
Test name
Test status
Simulation time 14983882 ps
CPU time 0.91 seconds
Started Dec 27 12:36:52 PM PST 23
Finished Dec 27 12:37:19 PM PST 23
Peak memory 205960 kb
Host smart-0d9c30d0-3631-48cf-9c7c-8cbd355e8a31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127982576 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.3127982576
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.3050720427
Short name T391
Test name
Test status
Simulation time 139532548 ps
CPU time 0.81 seconds
Started Dec 27 12:37:45 PM PST 23
Finished Dec 27 12:37:53 PM PST 23
Peak memory 205792 kb
Host smart-a4868d6b-57a4-4067-80f2-5ce7620ea238
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050720427 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.3050720427
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.807645403
Short name T409
Test name
Test status
Simulation time 32898582 ps
CPU time 0.74 seconds
Started Dec 27 12:36:40 PM PST 23
Finished Dec 27 12:37:10 PM PST 23
Peak memory 205716 kb
Host smart-099fa5ba-3da1-4f07-afa1-543badaee53c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807645403 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.807645403
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3107905114
Short name T215
Test name
Test status
Simulation time 19757864 ps
CPU time 1.09 seconds
Started Dec 27 12:36:34 PM PST 23
Finished Dec 27 12:37:03 PM PST 23
Peak memory 205908 kb
Host smart-24b96293-5334-4e56-be27-65baa261bb23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107905114 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.3107905114
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.1307374284
Short name T377
Test name
Test status
Simulation time 69834973 ps
CPU time 2.33 seconds
Started Dec 27 12:36:46 PM PST 23
Finished Dec 27 12:37:17 PM PST 23
Peak memory 214264 kb
Host smart-dd88c739-52c7-46ad-ae02-2b3b16bbeb0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307374284 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.1307374284
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.615699372
Short name T444
Test name
Test status
Simulation time 97072172 ps
CPU time 1.59 seconds
Started Dec 27 12:36:51 PM PST 23
Finished Dec 27 12:37:20 PM PST 23
Peak memory 205880 kb
Host smart-85affd3e-1c21-40e7-80c7-70e6b4a114ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615699372 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.615699372
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.718836150
Short name T380
Test name
Test status
Simulation time 17596465 ps
CPU time 0.75 seconds
Started Dec 27 12:36:58 PM PST 23
Finished Dec 27 12:37:24 PM PST 23
Peak memory 205692 kb
Host smart-ce00f18f-e92f-4ced-96f2-458e20f81f68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718836150 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.718836150
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.632117454
Short name T433
Test name
Test status
Simulation time 19925981 ps
CPU time 0.82 seconds
Started Dec 27 12:37:15 PM PST 23
Finished Dec 27 12:37:37 PM PST 23
Peak memory 205920 kb
Host smart-20fa5d46-3dab-4303-9a03-88e34e5eae53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632117454 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.632117454
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.1501846101
Short name T217
Test name
Test status
Simulation time 28672672 ps
CPU time 0.74 seconds
Started Dec 27 12:36:52 PM PST 23
Finished Dec 27 12:37:19 PM PST 23
Peak memory 205796 kb
Host smart-18414d7e-e367-4fbc-8ae5-3f96de3792cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501846101 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.1501846101
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.3456470288
Short name T213
Test name
Test status
Simulation time 19089560 ps
CPU time 0.81 seconds
Started Dec 27 12:36:58 PM PST 23
Finished Dec 27 12:37:24 PM PST 23
Peak memory 205864 kb
Host smart-884b0a58-ec30-4a96-8d41-8cad2f44a42c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456470288 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3456470288
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.1127285729
Short name T186
Test name
Test status
Simulation time 31359549 ps
CPU time 0.78 seconds
Started Dec 27 12:37:12 PM PST 23
Finished Dec 27 12:37:35 PM PST 23
Peak memory 205880 kb
Host smart-8c2386e9-c1de-4b50-aca1-d57b266f5b66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127285729 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.1127285729
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.1396359204
Short name T374
Test name
Test status
Simulation time 47164947 ps
CPU time 0.77 seconds
Started Dec 27 12:37:44 PM PST 23
Finished Dec 27 12:37:52 PM PST 23
Peak memory 205672 kb
Host smart-690facf5-5d76-4d2d-9f17-c4cf4a80e564
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396359204 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.1396359204
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.720313213
Short name T221
Test name
Test status
Simulation time 30494015 ps
CPU time 0.79 seconds
Started Dec 27 12:37:31 PM PST 23
Finished Dec 27 12:37:46 PM PST 23
Peak memory 206016 kb
Host smart-f95c46da-3cce-4c3c-8622-9f0e804d7126
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720313213 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.720313213
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.2735078034
Short name T389
Test name
Test status
Simulation time 134637139 ps
CPU time 0.81 seconds
Started Dec 27 12:37:53 PM PST 23
Finished Dec 27 12:37:58 PM PST 23
Peak memory 205880 kb
Host smart-4a2c3131-6b1c-47b3-ae4b-36ce4ef6a9c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735078034 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.2735078034
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.2528157555
Short name T223
Test name
Test status
Simulation time 13303190 ps
CPU time 0.86 seconds
Started Dec 27 12:37:19 PM PST 23
Finished Dec 27 12:37:39 PM PST 23
Peak memory 205908 kb
Host smart-639a6e84-9724-4168-8776-5f4a05dc02d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528157555 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2528157555
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.1563280612
Short name T402
Test name
Test status
Simulation time 30274954 ps
CPU time 0.78 seconds
Started Dec 27 12:36:51 PM PST 23
Finished Dec 27 12:37:18 PM PST 23
Peak memory 205744 kb
Host smart-2af6109d-b2e8-4324-b88b-1d903745bdaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563280612 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.1563280612
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.231374572
Short name T206
Test name
Test status
Simulation time 52121689 ps
CPU time 0.96 seconds
Started Dec 27 12:36:39 PM PST 23
Finished Dec 27 12:37:10 PM PST 23
Peak memory 206068 kb
Host smart-fa456b05-9cdc-48f5-bdd8-a6aa1129a5a1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231374572 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.231374572
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3685994001
Short name T446
Test name
Test status
Simulation time 110106343 ps
CPU time 3.24 seconds
Started Dec 27 12:36:27 PM PST 23
Finished Dec 27 12:36:52 PM PST 23
Peak memory 206004 kb
Host smart-3b545f29-e2eb-4257-ab7b-60b726659d91
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685994001 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.3685994001
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.1772490336
Short name T412
Test name
Test status
Simulation time 26744160 ps
CPU time 0.87 seconds
Started Dec 27 12:36:32 PM PST 23
Finished Dec 27 12:36:59 PM PST 23
Peak memory 206004 kb
Host smart-e91e73ee-174f-4d20-9ec3-47b61c79f4de
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772490336 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.1772490336
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.738633260
Short name T440
Test name
Test status
Simulation time 17702345 ps
CPU time 0.99 seconds
Started Dec 27 12:36:45 PM PST 23
Finished Dec 27 12:37:15 PM PST 23
Peak memory 205960 kb
Host smart-cfb18966-692f-4f59-9e95-24e2b406f6d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738633260 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.738633260
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.1848862365
Short name T173
Test name
Test status
Simulation time 45994354 ps
CPU time 0.83 seconds
Started Dec 27 12:37:04 PM PST 23
Finished Dec 27 12:37:29 PM PST 23
Peak memory 205872 kb
Host smart-89d95549-e7be-4899-9ea7-8a62c1db4aa4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848862365 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.1848862365
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.183454711
Short name T387
Test name
Test status
Simulation time 62316325 ps
CPU time 0.82 seconds
Started Dec 27 12:36:28 PM PST 23
Finished Dec 27 12:36:51 PM PST 23
Peak memory 205728 kb
Host smart-4ecd4bd6-f0e4-4e69-ba9d-f47a9e08880d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183454711 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.183454711
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1494353751
Short name T222
Test name
Test status
Simulation time 30754414 ps
CPU time 1.23 seconds
Started Dec 27 12:37:09 PM PST 23
Finished Dec 27 12:37:33 PM PST 23
Peak memory 206012 kb
Host smart-fd13e166-5575-4a1d-a8b8-6b1ae97694b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494353751 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.1494353751
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.2509297734
Short name T122
Test name
Test status
Simulation time 265097506 ps
CPU time 2.65 seconds
Started Dec 27 12:36:30 PM PST 23
Finished Dec 27 12:36:58 PM PST 23
Peak memory 214216 kb
Host smart-8a7a662b-ca2e-4b11-8e84-61d79b36806d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509297734 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.2509297734
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.736107169
Short name T419
Test name
Test status
Simulation time 346742607 ps
CPU time 1.53 seconds
Started Dec 27 12:37:04 PM PST 23
Finished Dec 27 12:37:30 PM PST 23
Peak memory 205928 kb
Host smart-f8c09602-5f82-4cbb-99ed-1155961d03cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736107169 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.736107169
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.2846486300
Short name T42
Test name
Test status
Simulation time 88640591 ps
CPU time 0.78 seconds
Started Dec 27 12:37:35 PM PST 23
Finished Dec 27 12:37:48 PM PST 23
Peak memory 205668 kb
Host smart-ec28dd69-62d8-409f-8a78-9c3c7ee3484b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846486300 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2846486300
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.1308011097
Short name T371
Test name
Test status
Simulation time 13994765 ps
CPU time 0.86 seconds
Started Dec 27 12:37:16 PM PST 23
Finished Dec 27 12:37:37 PM PST 23
Peak memory 205864 kb
Host smart-b95db4d3-82cd-49a7-abc4-ba1be5b7ccdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308011097 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.1308011097
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.2506141733
Short name T373
Test name
Test status
Simulation time 13953626 ps
CPU time 0.82 seconds
Started Dec 27 12:37:36 PM PST 23
Finished Dec 27 12:37:50 PM PST 23
Peak memory 205924 kb
Host smart-844326fd-27ad-4f75-8a27-2ee598be1d54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506141733 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2506141733
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.2579220776
Short name T196
Test name
Test status
Simulation time 28733451 ps
CPU time 0.82 seconds
Started Dec 27 12:37:08 PM PST 23
Finished Dec 27 12:37:32 PM PST 23
Peak memory 205984 kb
Host smart-5d7f93c0-1418-4f67-a590-0bed79170207
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579220776 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.2579220776
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.3478564986
Short name T408
Test name
Test status
Simulation time 25270736 ps
CPU time 0.85 seconds
Started Dec 27 12:37:02 PM PST 23
Finished Dec 27 12:37:27 PM PST 23
Peak memory 205912 kb
Host smart-7ba596bf-4ab4-481b-8b2a-87da79d71191
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478564986 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.3478564986
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.1723302665
Short name T450
Test name
Test status
Simulation time 29630236 ps
CPU time 0.78 seconds
Started Dec 27 12:37:13 PM PST 23
Finished Dec 27 12:37:35 PM PST 23
Peak memory 205664 kb
Host smart-b9e9f8dd-803a-4d46-be54-6c1a3c547ff3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723302665 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1723302665
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.3549743753
Short name T431
Test name
Test status
Simulation time 20324313 ps
CPU time 0.78 seconds
Started Dec 27 12:37:14 PM PST 23
Finished Dec 27 12:37:36 PM PST 23
Peak memory 205712 kb
Host smart-aa997d5c-3ab2-493a-8069-774c9be1bee6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549743753 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3549743753
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.2197180059
Short name T367
Test name
Test status
Simulation time 66754786 ps
CPU time 0.82 seconds
Started Dec 27 12:36:33 PM PST 23
Finished Dec 27 12:37:00 PM PST 23
Peak memory 205912 kb
Host smart-fb714522-c6a8-496e-ab38-2aa678a60cbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197180059 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.2197180059
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.1302319892
Short name T428
Test name
Test status
Simulation time 51963361 ps
CPU time 0.82 seconds
Started Dec 27 12:36:52 PM PST 23
Finished Dec 27 12:37:19 PM PST 23
Peak memory 205872 kb
Host smart-1201aecf-234a-45a4-a318-dbad199254d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302319892 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.1302319892
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.3942580765
Short name T383
Test name
Test status
Simulation time 39854023 ps
CPU time 0.79 seconds
Started Dec 27 12:37:24 PM PST 23
Finished Dec 27 12:37:43 PM PST 23
Peak memory 205796 kb
Host smart-6329446f-0a0e-45b1-a577-01e9aea61baf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942580765 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3942580765
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.556073970
Short name T212
Test name
Test status
Simulation time 62772645 ps
CPU time 1.11 seconds
Started Dec 27 12:37:12 PM PST 23
Finished Dec 27 12:37:37 PM PST 23
Peak memory 206072 kb
Host smart-d07b6b6a-cc67-49ea-a945-29635f1394dc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556073970 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.556073970
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.1880923591
Short name T220
Test name
Test status
Simulation time 65862231 ps
CPU time 1.98 seconds
Started Dec 27 12:37:53 PM PST 23
Finished Dec 27 12:37:59 PM PST 23
Peak memory 205968 kb
Host smart-1905f6e9-789c-4fb4-bf0a-a5004c6f3691
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880923591 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.1880923591
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1300998262
Short name T174
Test name
Test status
Simulation time 65276510 ps
CPU time 0.77 seconds
Started Dec 27 12:37:11 PM PST 23
Finished Dec 27 12:37:34 PM PST 23
Peak memory 205752 kb
Host smart-52481ab6-dca9-4f1e-a3ba-edcb60a6a2e5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300998262 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.1300998262
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1308699049
Short name T171
Test name
Test status
Simulation time 24726547 ps
CPU time 1.22 seconds
Started Dec 27 12:37:16 PM PST 23
Finished Dec 27 12:37:38 PM PST 23
Peak memory 214120 kb
Host smart-64a76f91-2578-4bae-8ed1-4cf7beb17d41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308699049 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.1308699049
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.3400807145
Short name T382
Test name
Test status
Simulation time 14455851 ps
CPU time 0.9 seconds
Started Dec 27 12:37:52 PM PST 23
Finished Dec 27 12:37:57 PM PST 23
Peak memory 205904 kb
Host smart-50ff7867-d71e-43fb-99f9-1cea7d16108e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400807145 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.3400807145
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.2298533794
Short name T194
Test name
Test status
Simulation time 44131167 ps
CPU time 0.8 seconds
Started Dec 27 12:36:50 PM PST 23
Finished Dec 27 12:37:21 PM PST 23
Peak memory 205816 kb
Host smart-d6604fb0-e1e1-4bd6-8913-34d52f5c7191
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298533794 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.2298533794
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1874985551
Short name T426
Test name
Test status
Simulation time 68737521 ps
CPU time 1.32 seconds
Started Dec 27 12:36:48 PM PST 23
Finished Dec 27 12:37:17 PM PST 23
Peak memory 205912 kb
Host smart-f7c65030-be32-4020-9fb6-7468cb18a4da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874985551 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.1874985551
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.2546449117
Short name T199
Test name
Test status
Simulation time 76350461 ps
CPU time 1.61 seconds
Started Dec 27 12:36:57 PM PST 23
Finished Dec 27 12:37:23 PM PST 23
Peak memory 214108 kb
Host smart-27099428-be66-4ffc-83e6-360decd80cb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546449117 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.2546449117
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3141734977
Short name T405
Test name
Test status
Simulation time 559909212 ps
CPU time 1.61 seconds
Started Dec 27 12:36:37 PM PST 23
Finished Dec 27 12:37:07 PM PST 23
Peak memory 205948 kb
Host smart-6f614cd7-df3c-448f-ac57-40c90f4d461c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141734977 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.3141734977
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.1262500597
Short name T368
Test name
Test status
Simulation time 52542996 ps
CPU time 0.87 seconds
Started Dec 27 12:36:36 PM PST 23
Finished Dec 27 12:37:06 PM PST 23
Peak memory 205996 kb
Host smart-894ab342-12ea-48d2-89b7-662e8ddffabc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262500597 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.1262500597
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.2224938169
Short name T184
Test name
Test status
Simulation time 13212302 ps
CPU time 0.84 seconds
Started Dec 27 12:36:56 PM PST 23
Finished Dec 27 12:37:22 PM PST 23
Peak memory 205996 kb
Host smart-3cc6a8cd-ab74-4040-b996-523a9cbf8cdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224938169 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.2224938169
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.3356045064
Short name T443
Test name
Test status
Simulation time 20906823 ps
CPU time 0.8 seconds
Started Dec 27 12:38:06 PM PST 23
Finished Dec 27 12:38:14 PM PST 23
Peak memory 204636 kb
Host smart-eb88aa68-9a64-4549-984d-298ec895037b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356045064 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.3356045064
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.2428915624
Short name T189
Test name
Test status
Simulation time 14909786 ps
CPU time 0.79 seconds
Started Dec 27 12:36:58 PM PST 23
Finished Dec 27 12:37:23 PM PST 23
Peak memory 205892 kb
Host smart-ecbb3307-4b35-43c2-b182-2b16a930c610
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428915624 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.2428915624
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.1575112959
Short name T423
Test name
Test status
Simulation time 23078210 ps
CPU time 0.83 seconds
Started Dec 27 12:37:15 PM PST 23
Finished Dec 27 12:37:36 PM PST 23
Peak memory 206016 kb
Host smart-1f41728b-a1e1-4607-982c-6187a7560038
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575112959 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.1575112959
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.4084774669
Short name T385
Test name
Test status
Simulation time 23622760 ps
CPU time 0.81 seconds
Started Dec 27 12:37:01 PM PST 23
Finished Dec 27 12:37:31 PM PST 23
Peak memory 205936 kb
Host smart-5998a1fb-962e-48a7-a860-5588e790e9a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084774669 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.4084774669
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.1326692605
Short name T418
Test name
Test status
Simulation time 24828607 ps
CPU time 0.86 seconds
Started Dec 27 12:36:57 PM PST 23
Finished Dec 27 12:37:23 PM PST 23
Peak memory 205872 kb
Host smart-b5cfa0fb-bc88-4f97-b17a-470b645f9925
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326692605 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1326692605
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.1653022702
Short name T228
Test name
Test status
Simulation time 12590680 ps
CPU time 0.8 seconds
Started Dec 27 12:37:34 PM PST 23
Finished Dec 27 12:37:48 PM PST 23
Peak memory 205888 kb
Host smart-8366fde7-94e4-400c-a401-7c7ce8f45e63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653022702 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.1653022702
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.2165218379
Short name T226
Test name
Test status
Simulation time 46595205 ps
CPU time 0.74 seconds
Started Dec 27 12:36:47 PM PST 23
Finished Dec 27 12:37:15 PM PST 23
Peak memory 205820 kb
Host smart-367cc9bf-2342-4a9f-bef8-0a38b8810dc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165218379 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.2165218379
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.194499405
Short name T376
Test name
Test status
Simulation time 12630179 ps
CPU time 0.82 seconds
Started Dec 27 12:36:50 PM PST 23
Finished Dec 27 12:37:18 PM PST 23
Peak memory 205976 kb
Host smart-de255922-f072-4cfd-a678-7f9f233818e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194499405 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.194499405
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2929324343
Short name T177
Test name
Test status
Simulation time 21961121 ps
CPU time 1.17 seconds
Started Dec 27 12:36:49 PM PST 23
Finished Dec 27 12:37:17 PM PST 23
Peak memory 214316 kb
Host smart-f153dba7-7fa3-4100-a8e9-994dadda56c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929324343 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.2929324343
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.1410813294
Short name T397
Test name
Test status
Simulation time 19852618 ps
CPU time 0.84 seconds
Started Dec 27 12:37:49 PM PST 23
Finished Dec 27 12:37:54 PM PST 23
Peak memory 205784 kb
Host smart-6bf5d4df-df9d-4517-9b57-6eca1b8b6994
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410813294 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.1410813294
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.738406144
Short name T406
Test name
Test status
Simulation time 18002169 ps
CPU time 0.79 seconds
Started Dec 27 12:36:59 PM PST 23
Finished Dec 27 12:37:25 PM PST 23
Peak memory 205920 kb
Host smart-d5e2e3b5-e125-4c33-b9be-2d99dc5a1601
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738406144 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.738406144
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.23879000
Short name T421
Test name
Test status
Simulation time 16500847 ps
CPU time 1.05 seconds
Started Dec 27 12:36:32 PM PST 23
Finished Dec 27 12:37:00 PM PST 23
Peak memory 205896 kb
Host smart-c89edc6b-56e3-43a7-bad4-e68d50787cfc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23879000 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_outs
tanding.23879000
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.4182640487
Short name T365
Test name
Test status
Simulation time 82732901 ps
CPU time 1.77 seconds
Started Dec 27 12:36:52 PM PST 23
Finished Dec 27 12:37:20 PM PST 23
Peak memory 214200 kb
Host smart-9e0db325-ada1-40b2-a817-cb056b139ad0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182640487 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.4182640487
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.4006847971
Short name T195
Test name
Test status
Simulation time 161818675 ps
CPU time 1.45 seconds
Started Dec 27 12:38:46 PM PST 23
Finished Dec 27 12:38:58 PM PST 23
Peak memory 205052 kb
Host smart-915c1805-ef7c-4353-8a0a-c41092f3c91c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006847971 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.4006847971
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2741079635
Short name T25
Test name
Test status
Simulation time 90195021 ps
CPU time 0.88 seconds
Started Dec 27 12:37:17 PM PST 23
Finished Dec 27 12:37:38 PM PST 23
Peak memory 205988 kb
Host smart-ca29d9cd-1394-4da0-9852-83fd64387b11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741079635 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.2741079635
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.2201869915
Short name T207
Test name
Test status
Simulation time 121803187 ps
CPU time 0.88 seconds
Started Dec 27 12:36:23 PM PST 23
Finished Dec 27 12:36:46 PM PST 23
Peak memory 205920 kb
Host smart-b41ccdd6-25a7-4b0b-995c-092029af46b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201869915 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.2201869915
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.2579029541
Short name T218
Test name
Test status
Simulation time 24078910 ps
CPU time 0.83 seconds
Started Dec 27 12:36:54 PM PST 23
Finished Dec 27 12:37:21 PM PST 23
Peak memory 205880 kb
Host smart-7edf8929-c363-4c93-8663-25a433822ebc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579029541 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.2579029541
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.34047526
Short name T175
Test name
Test status
Simulation time 70262037 ps
CPU time 0.98 seconds
Started Dec 27 12:37:02 PM PST 23
Finished Dec 27 12:37:28 PM PST 23
Peak memory 205944 kb
Host smart-01edb062-a2c2-46e4-a077-b798834f0186
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34047526 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_outs
tanding.34047526
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.1530300183
Short name T170
Test name
Test status
Simulation time 449282547 ps
CPU time 3.55 seconds
Started Dec 27 12:36:56 PM PST 23
Finished Dec 27 12:37:24 PM PST 23
Peak memory 214252 kb
Host smart-0df6bcee-8f76-449e-a11e-dbb98abc96f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530300183 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.1530300183
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.4222931571
Short name T420
Test name
Test status
Simulation time 169845094 ps
CPU time 1.46 seconds
Started Dec 27 12:37:07 PM PST 23
Finished Dec 27 12:37:32 PM PST 23
Peak memory 205904 kb
Host smart-ea9fc583-e0e4-4f84-b03e-ea3abe48fe09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222931571 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.4222931571
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2705048405
Short name T182
Test name
Test status
Simulation time 106481119 ps
CPU time 1.34 seconds
Started Dec 27 12:37:24 PM PST 23
Finished Dec 27 12:37:44 PM PST 23
Peak memory 214156 kb
Host smart-ffbf313e-beee-4fdc-b34d-5839ec339d34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705048405 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2705048405
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.3361293321
Short name T205
Test name
Test status
Simulation time 16468002 ps
CPU time 0.9 seconds
Started Dec 27 12:36:25 PM PST 23
Finished Dec 27 12:36:48 PM PST 23
Peak memory 205992 kb
Host smart-1e34bb6b-9cde-46ac-9230-dd2e109f0d70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361293321 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.3361293321
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.429853116
Short name T395
Test name
Test status
Simulation time 13984154 ps
CPU time 0.96 seconds
Started Dec 27 12:36:36 PM PST 23
Finished Dec 27 12:37:05 PM PST 23
Peak memory 206004 kb
Host smart-44d4bbf1-95d9-47ec-972f-7f2939c70525
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429853116 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.429853116
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3951124043
Short name T230
Test name
Test status
Simulation time 74737609 ps
CPU time 0.99 seconds
Started Dec 27 12:36:58 PM PST 23
Finished Dec 27 12:37:23 PM PST 23
Peak memory 205956 kb
Host smart-95828e2f-67fa-4aed-a937-270d65dd937d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951124043 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.3951124043
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.1022742679
Short name T451
Test name
Test status
Simulation time 55787655 ps
CPU time 1.7 seconds
Started Dec 27 12:37:56 PM PST 23
Finished Dec 27 12:38:07 PM PST 23
Peak memory 214212 kb
Host smart-198cc647-b0d2-478e-83e1-9df3d00cace4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022742679 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.1022742679
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2134607131
Short name T197
Test name
Test status
Simulation time 109982609 ps
CPU time 2.39 seconds
Started Dec 27 12:37:31 PM PST 23
Finished Dec 27 12:37:51 PM PST 23
Peak memory 205912 kb
Host smart-90d8b5d4-0159-4603-aba0-03d02fb3f0be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134607131 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.2134607131
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2322406292
Short name T381
Test name
Test status
Simulation time 18856956 ps
CPU time 1.02 seconds
Started Dec 27 12:36:31 PM PST 23
Finished Dec 27 12:36:58 PM PST 23
Peak memory 214152 kb
Host smart-5daac7fc-97d1-4eb1-b73d-ce143852aea3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322406292 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.2322406292
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.4247627755
Short name T209
Test name
Test status
Simulation time 19588362 ps
CPU time 0.92 seconds
Started Dec 27 12:36:42 PM PST 23
Finished Dec 27 12:37:12 PM PST 23
Peak memory 205864 kb
Host smart-cf7c5c93-ccf3-4821-9efa-eaa4417bb9eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247627755 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.4247627755
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.1577962107
Short name T188
Test name
Test status
Simulation time 13174960 ps
CPU time 0.83 seconds
Started Dec 27 12:36:53 PM PST 23
Finished Dec 27 12:37:20 PM PST 23
Peak memory 206000 kb
Host smart-42c9c5b2-e485-4131-9267-05ead967353c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577962107 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1577962107
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3080619796
Short name T185
Test name
Test status
Simulation time 51650211 ps
CPU time 1.01 seconds
Started Dec 27 12:36:35 PM PST 23
Finished Dec 27 12:37:04 PM PST 23
Peak memory 205916 kb
Host smart-c5a783b5-658c-475e-8237-858416891e63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080619796 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.3080619796
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.508753728
Short name T120
Test name
Test status
Simulation time 102913575 ps
CPU time 3.66 seconds
Started Dec 27 12:37:01 PM PST 23
Finished Dec 27 12:37:30 PM PST 23
Peak memory 214408 kb
Host smart-99eddfde-e7e1-4240-ad40-c29a44fb8a32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508753728 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.508753728
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1671169545
Short name T191
Test name
Test status
Simulation time 631157142 ps
CPU time 2.25 seconds
Started Dec 27 12:36:44 PM PST 23
Finished Dec 27 12:37:15 PM PST 23
Peak memory 205988 kb
Host smart-28da2325-6b3f-468a-85ad-d4308c9e9ec6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671169545 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.1671169545
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.4192813069
Short name T447
Test name
Test status
Simulation time 186085765 ps
CPU time 1.11 seconds
Started Dec 27 12:36:26 PM PST 23
Finished Dec 27 12:36:59 PM PST 23
Peak memory 214300 kb
Host smart-1c56e6fc-c019-4d70-8c90-cd181e3e7907
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192813069 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.4192813069
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.477368895
Short name T40
Test name
Test status
Simulation time 94094133 ps
CPU time 0.84 seconds
Started Dec 27 12:36:37 PM PST 23
Finished Dec 27 12:37:07 PM PST 23
Peak memory 205876 kb
Host smart-e0ede1e8-46d0-4e53-a71a-707835e8d009
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477368895 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.477368895
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.2679624436
Short name T393
Test name
Test status
Simulation time 50962517 ps
CPU time 0.83 seconds
Started Dec 27 12:37:01 PM PST 23
Finished Dec 27 12:37:27 PM PST 23
Peak memory 205868 kb
Host smart-1efdafe5-3f4d-48d8-b28a-8b7df90cf26e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679624436 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.2679624436
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1712928055
Short name T448
Test name
Test status
Simulation time 19966278 ps
CPU time 1 seconds
Started Dec 27 12:36:28 PM PST 23
Finished Dec 27 12:36:52 PM PST 23
Peak memory 205988 kb
Host smart-8baabbed-5fde-4cb4-8662-1056d62ebd51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712928055 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.1712928055
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.1536259705
Short name T425
Test name
Test status
Simulation time 22484833 ps
CPU time 1.43 seconds
Started Dec 27 12:37:01 PM PST 23
Finished Dec 27 12:37:28 PM PST 23
Peak memory 214296 kb
Host smart-549966f4-7c3f-4ae1-9531-55a288e9dc9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536259705 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.1536259705
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1344325777
Short name T270
Test name
Test status
Simulation time 706422747 ps
CPU time 1.85 seconds
Started Dec 27 12:36:48 PM PST 23
Finished Dec 27 12:37:22 PM PST 23
Peak memory 205864 kb
Host smart-a686e8ce-9de7-4b52-81af-6089c4532605
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344325777 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.1344325777
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.4275434512
Short name T724
Test name
Test status
Simulation time 39800829 ps
CPU time 1.07 seconds
Started Dec 27 12:57:51 PM PST 23
Finished Dec 27 12:57:53 PM PST 23
Peak memory 214500 kb
Host smart-d0774510-5e5f-4525-ac28-8ebcd92acd01
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275434512 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.4275434512
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.2302051067
Short name T624
Test name
Test status
Simulation time 57381192 ps
CPU time 0.82 seconds
Started Dec 27 12:57:50 PM PST 23
Finished Dec 27 12:57:53 PM PST 23
Peak memory 215448 kb
Host smart-88354f4c-fc20-400e-b299-df872058e6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302051067 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.2302051067
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.2294303963
Short name T511
Test name
Test status
Simulation time 60920664 ps
CPU time 2.3 seconds
Started Dec 27 12:58:01 PM PST 23
Finished Dec 27 12:58:10 PM PST 23
Peak memory 214192 kb
Host smart-73b2829c-8872-4409-8a96-5f8b6b9b2cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294303963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2294303963
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_regwen.3364375267
Short name T291
Test name
Test status
Simulation time 79415972 ps
CPU time 0.9 seconds
Started Dec 27 12:58:07 PM PST 23
Finished Dec 27 12:58:14 PM PST 23
Peak memory 204656 kb
Host smart-3b7c55f8-f27f-425b-bd6d-24a1de21348a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364375267 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.3364375267
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.3559881146
Short name T54
Test name
Test status
Simulation time 177396809 ps
CPU time 3.44 seconds
Started Dec 27 12:57:54 PM PST 23
Finished Dec 27 12:57:59 PM PST 23
Peak memory 231812 kb
Host smart-acd7bde8-b4ce-4dae-b1c5-5bfda7ea0d41
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559881146 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.3559881146
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.323685489
Short name T572
Test name
Test status
Simulation time 16838503 ps
CPU time 0.89 seconds
Started Dec 27 12:57:35 PM PST 23
Finished Dec 27 12:57:40 PM PST 23
Peak memory 205020 kb
Host smart-f4f0fb83-0444-47bd-9866-64b2eef5dda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323685489 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.323685489
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.1892711564
Short name T542
Test name
Test status
Simulation time 214213760 ps
CPU time 1.82 seconds
Started Dec 27 12:57:49 PM PST 23
Finished Dec 27 12:57:52 PM PST 23
Peak memory 205808 kb
Host smart-c7ca6b8a-bc8a-4968-ad1f-6856edaf83dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892711564 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.1892711564
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.3798863860
Short name T485
Test name
Test status
Simulation time 51972942762 ps
CPU time 1170.82 seconds
Started Dec 27 12:58:01 PM PST 23
Finished Dec 27 01:17:37 PM PST 23
Peak memory 215024 kb
Host smart-b272c2f7-bdce-405b-8a65-7a8eebfe4af9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798863860 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.3798863860
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.1497840419
Short name T265
Test name
Test status
Simulation time 36039170 ps
CPU time 1.06 seconds
Started Dec 27 12:58:06 PM PST 23
Finished Dec 27 12:58:13 PM PST 23
Peak memory 205180 kb
Host smart-33ff349c-1981-449d-8c95-a959eb55310b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497840419 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1497840419
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.1191911732
Short name T698
Test name
Test status
Simulation time 25110618 ps
CPU time 0.84 seconds
Started Dec 27 12:57:51 PM PST 23
Finished Dec 27 12:57:53 PM PST 23
Peak memory 204488 kb
Host smart-bbd05c13-b1ae-4f7c-8546-65ee35a190b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191911732 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1191911732
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.1943581159
Short name T869
Test name
Test status
Simulation time 27685987 ps
CPU time 0.93 seconds
Started Dec 27 12:58:03 PM PST 23
Finished Dec 27 12:58:12 PM PST 23
Peak memory 214372 kb
Host smart-a05fb68b-4d37-476a-a822-077634a47725
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943581159 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.1943581159
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.392902302
Short name T132
Test name
Test status
Simulation time 43571956 ps
CPU time 0.93 seconds
Started Dec 27 12:57:51 PM PST 23
Finished Dec 27 12:57:54 PM PST 23
Peak memory 214556 kb
Host smart-87db3e50-1418-4149-9381-1313208882c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392902302 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.392902302
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.4189807335
Short name T802
Test name
Test status
Simulation time 24821610 ps
CPU time 1.02 seconds
Started Dec 27 12:57:57 PM PST 23
Finished Dec 27 12:58:07 PM PST 23
Peak memory 214176 kb
Host smart-c03069a4-5690-4698-a4c3-98ca220b8fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189807335 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.4189807335
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.2362065493
Short name T855
Test name
Test status
Simulation time 22721865 ps
CPU time 0.96 seconds
Started Dec 27 12:57:59 PM PST 23
Finished Dec 27 12:58:03 PM PST 23
Peak memory 214552 kb
Host smart-aaa74139-efe9-40f6-a201-6a887f7acae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362065493 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.2362065493
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_sec_cm.2139774111
Short name T53
Test name
Test status
Simulation time 358603504 ps
CPU time 6.23 seconds
Started Dec 27 12:58:09 PM PST 23
Finished Dec 27 12:58:24 PM PST 23
Peak memory 235320 kb
Host smart-6e214d43-2240-4b2f-b277-a0652dd78ae7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139774111 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.2139774111
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.939852454
Short name T457
Test name
Test status
Simulation time 24167497 ps
CPU time 0.84 seconds
Started Dec 27 12:57:56 PM PST 23
Finished Dec 27 12:57:58 PM PST 23
Peak memory 204856 kb
Host smart-8a658f45-fb20-4a4c-becb-db49946e74e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939852454 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.939852454
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.2400919497
Short name T548
Test name
Test status
Simulation time 267942264 ps
CPU time 2.38 seconds
Started Dec 27 12:57:45 PM PST 23
Finished Dec 27 12:57:48 PM PST 23
Peak memory 205876 kb
Host smart-f6b29d29-42e6-4fbb-a056-77f5bb82bca9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400919497 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.2400919497
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.2658589221
Short name T833
Test name
Test status
Simulation time 114640210624 ps
CPU time 1250.16 seconds
Started Dec 27 12:58:03 PM PST 23
Finished Dec 27 01:19:00 PM PST 23
Peak memory 216636 kb
Host smart-cdf49873-7a38-46d1-bf94-f5c0d98d8392
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658589221 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.2658589221
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert_test.1780831843
Short name T607
Test name
Test status
Simulation time 16917792 ps
CPU time 0.95 seconds
Started Dec 27 12:57:56 PM PST 23
Finished Dec 27 12:57:59 PM PST 23
Peak memory 204460 kb
Host smart-d5fc2b45-37da-460a-af87-74d035e4c190
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780831843 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.1780831843
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_err.3732332275
Short name T254
Test name
Test status
Simulation time 44938265 ps
CPU time 0.89 seconds
Started Dec 27 12:58:10 PM PST 23
Finished Dec 27 12:58:20 PM PST 23
Peak memory 214724 kb
Host smart-b95934d0-c5cf-4920-bb97-76aec5f66f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732332275 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.3732332275
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.103797138
Short name T873
Test name
Test status
Simulation time 44007546 ps
CPU time 0.88 seconds
Started Dec 27 12:58:03 PM PST 23
Finished Dec 27 12:58:12 PM PST 23
Peak memory 205204 kb
Host smart-e806b905-dbb6-474b-ac11-b588245e7331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103797138 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.103797138
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.2819459453
Short name T610
Test name
Test status
Simulation time 19929897 ps
CPU time 1.04 seconds
Started Dec 27 12:58:21 PM PST 23
Finished Dec 27 12:58:36 PM PST 23
Peak memory 214300 kb
Host smart-28dddd11-87b5-44c2-ba93-1115ce01a9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819459453 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.2819459453
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.3388950270
Short name T923
Test name
Test status
Simulation time 122814166 ps
CPU time 0.87 seconds
Started Dec 27 12:57:55 PM PST 23
Finished Dec 27 12:57:58 PM PST 23
Peak memory 204836 kb
Host smart-aa3cd17a-9ba2-4cc5-a2e0-034553ab64e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388950270 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.3388950270
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.159713270
Short name T976
Test name
Test status
Simulation time 93621711397 ps
CPU time 994.25 seconds
Started Dec 27 12:58:04 PM PST 23
Finished Dec 27 01:14:46 PM PST 23
Peak memory 216432 kb
Host smart-68f20768-82d2-4b82-aaee-72b6382351be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159713270 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.159713270
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.2525320095
Short name T975
Test name
Test status
Simulation time 18385496 ps
CPU time 1.03 seconds
Started Dec 27 12:59:43 PM PST 23
Finished Dec 27 12:59:47 PM PST 23
Peak memory 205620 kb
Host smart-a4ecc94a-c58b-462a-b40e-ea259f17fba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525320095 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.2525320095
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.1567535910
Short name T493
Test name
Test status
Simulation time 22090999 ps
CPU time 0.93 seconds
Started Dec 27 12:58:45 PM PST 23
Finished Dec 27 12:58:54 PM PST 23
Peak memory 205456 kb
Host smart-aa579d49-fbe3-454e-8da5-9a09019b3bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567535910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.1567535910
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.3105551097
Short name T319
Test name
Test status
Simulation time 74247408 ps
CPU time 0.87 seconds
Started Dec 27 12:59:02 PM PST 23
Finished Dec 27 12:59:12 PM PST 23
Peak memory 204976 kb
Host smart-5bb1ad8a-6cc4-4b70-92b4-f227bd33b7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105551097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.3105551097
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.1615798260
Short name T741
Test name
Test status
Simulation time 19695761 ps
CPU time 1.24 seconds
Started Dec 27 12:59:05 PM PST 23
Finished Dec 27 12:59:15 PM PST 23
Peak memory 205652 kb
Host smart-9daa5c7e-3ed6-46f6-b4d2-8dd17539e881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615798260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.1615798260
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.1493985910
Short name T635
Test name
Test status
Simulation time 15648733 ps
CPU time 1.03 seconds
Started Dec 27 12:59:13 PM PST 23
Finished Dec 27 12:59:25 PM PST 23
Peak memory 205948 kb
Host smart-16e8066d-70c4-46af-887b-57ae37874817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493985910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1493985910
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.1756452482
Short name T868
Test name
Test status
Simulation time 14380207 ps
CPU time 0.94 seconds
Started Dec 27 12:59:09 PM PST 23
Finished Dec 27 12:59:21 PM PST 23
Peak memory 205128 kb
Host smart-f571100a-0ddf-4d1b-b8f7-6fe69d84e567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756452482 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.1756452482
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.690381596
Short name T933
Test name
Test status
Simulation time 20324022 ps
CPU time 1.01 seconds
Started Dec 27 12:58:00 PM PST 23
Finished Dec 27 12:58:04 PM PST 23
Peak memory 205988 kb
Host smart-b5ac9d18-c611-4064-ad7d-35e748b2048e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690381596 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.690381596
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.242382666
Short name T2
Test name
Test status
Simulation time 11926707 ps
CPU time 0.9 seconds
Started Dec 27 12:57:51 PM PST 23
Finished Dec 27 12:57:53 PM PST 23
Peak memory 204480 kb
Host smart-4cdf0232-9dc2-4334-8842-476df3b7fd2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242382666 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.242382666
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.978945824
Short name T28
Test name
Test status
Simulation time 15097817 ps
CPU time 0.86 seconds
Started Dec 27 12:58:16 PM PST 23
Finished Dec 27 12:58:26 PM PST 23
Peak memory 214176 kb
Host smart-90d53871-48ac-46f5-86fd-51314d21c7ec
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978945824 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.978945824
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.4038639024
Short name T495
Test name
Test status
Simulation time 63884012 ps
CPU time 0.99 seconds
Started Dec 27 12:58:09 PM PST 23
Finished Dec 27 12:58:19 PM PST 23
Peak memory 214560 kb
Host smart-4e21d758-e5a8-4cbc-a984-043290d98368
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038639024 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.4038639024
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.998619503
Short name T888
Test name
Test status
Simulation time 52407035 ps
CPU time 1.16 seconds
Started Dec 27 12:58:07 PM PST 23
Finished Dec 27 12:58:13 PM PST 23
Peak memory 214612 kb
Host smart-33643766-e83e-414f-8933-52441bd7418e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998619503 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.998619503
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.1476253039
Short name T813
Test name
Test status
Simulation time 43480177 ps
CPU time 1.1 seconds
Started Dec 27 12:57:48 PM PST 23
Finished Dec 27 12:57:50 PM PST 23
Peak memory 214132 kb
Host smart-d645c4e7-01bc-4059-8acb-2e0f00483d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476253039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1476253039
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.1164977335
Short name T674
Test name
Test status
Simulation time 36419106 ps
CPU time 0.95 seconds
Started Dec 27 12:57:57 PM PST 23
Finished Dec 27 12:58:00 PM PST 23
Peak memory 221160 kb
Host smart-caa513ba-24d5-4902-bafb-531fb5305359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164977335 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.1164977335
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.3339844919
Short name T464
Test name
Test status
Simulation time 25881059 ps
CPU time 0.85 seconds
Started Dec 27 12:58:06 PM PST 23
Finished Dec 27 12:58:13 PM PST 23
Peak memory 204948 kb
Host smart-6c8cd3b5-142c-46cb-ace6-f58896a7f39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339844919 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.3339844919
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.2142049559
Short name T504
Test name
Test status
Simulation time 66175829 ps
CPU time 1.66 seconds
Started Dec 27 12:57:38 PM PST 23
Finished Dec 27 12:57:42 PM PST 23
Peak memory 206004 kb
Host smart-eff7124a-34fb-42d9-b5ff-d6841f0496ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142049559 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.2142049559
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.3210453506
Short name T898
Test name
Test status
Simulation time 18564575527 ps
CPU time 399.67 seconds
Started Dec 27 12:58:06 PM PST 23
Finished Dec 27 01:04:52 PM PST 23
Peak memory 214448 kb
Host smart-8f715c17-d310-4045-aa38-c82e001430b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210453506 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.3210453506
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.3359279851
Short name T835
Test name
Test status
Simulation time 59147007 ps
CPU time 1.07 seconds
Started Dec 27 12:59:10 PM PST 23
Finished Dec 27 12:59:22 PM PST 23
Peak memory 205452 kb
Host smart-bffc47cc-88a8-4ae7-a9fd-b9616ffde843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359279851 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.3359279851
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.763491985
Short name T892
Test name
Test status
Simulation time 99876758 ps
CPU time 1.01 seconds
Started Dec 27 12:59:18 PM PST 23
Finished Dec 27 12:59:30 PM PST 23
Peak memory 205452 kb
Host smart-1be4e966-5699-40f1-a6c0-b89f665123d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763491985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.763491985
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.2461286779
Short name T900
Test name
Test status
Simulation time 18548402 ps
CPU time 1.09 seconds
Started Dec 27 12:59:05 PM PST 23
Finished Dec 27 12:59:14 PM PST 23
Peak memory 205420 kb
Host smart-e644afe6-4d32-4de7-a09f-4416dc48c9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461286779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.2461286779
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.2302197450
Short name T856
Test name
Test status
Simulation time 282128464 ps
CPU time 1.13 seconds
Started Dec 27 12:59:02 PM PST 23
Finished Dec 27 12:59:10 PM PST 23
Peak memory 205200 kb
Host smart-d845de4b-1ead-4462-afa5-2f6f0e7d622c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302197450 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.2302197450
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.3517150216
Short name T648
Test name
Test status
Simulation time 169202869 ps
CPU time 1.3 seconds
Started Dec 27 12:59:09 PM PST 23
Finished Dec 27 12:59:21 PM PST 23
Peak memory 214176 kb
Host smart-39116615-e7ba-4cb0-bca8-8b3c65df1df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517150216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.3517150216
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.3878437549
Short name T705
Test name
Test status
Simulation time 31732405 ps
CPU time 1 seconds
Started Dec 27 12:59:08 PM PST 23
Finished Dec 27 12:59:19 PM PST 23
Peak memory 205036 kb
Host smart-88c8e623-339b-4cf0-a9bf-34239bc9ee7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878437549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.3878437549
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.4093331617
Short name T71
Test name
Test status
Simulation time 198380962 ps
CPU time 0.97 seconds
Started Dec 27 12:59:15 PM PST 23
Finished Dec 27 12:59:27 PM PST 23
Peak memory 205096 kb
Host smart-6cdd2bcf-f485-4429-897e-29a33678d864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093331617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.4093331617
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.1350463001
Short name T836
Test name
Test status
Simulation time 72162053 ps
CPU time 1.1 seconds
Started Dec 27 12:59:07 PM PST 23
Finished Dec 27 12:59:18 PM PST 23
Peak memory 205640 kb
Host smart-d6edd4d3-e525-41ff-8ce8-7d1305850edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350463001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.1350463001
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.3548192073
Short name T804
Test name
Test status
Simulation time 36223052 ps
CPU time 1.09 seconds
Started Dec 27 12:59:07 PM PST 23
Finished Dec 27 12:59:19 PM PST 23
Peak memory 214128 kb
Host smart-3cd0a33c-cddc-43ca-bf1c-a04ab1e1cef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548192073 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3548192073
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert_test.2267828153
Short name T727
Test name
Test status
Simulation time 119010178 ps
CPU time 0.93 seconds
Started Dec 27 12:57:46 PM PST 23
Finished Dec 27 12:57:48 PM PST 23
Peak memory 204584 kb
Host smart-73708d60-05ab-4e01-8fb5-82172ce8b75a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267828153 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2267828153
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.4077611221
Short name T156
Test name
Test status
Simulation time 11091729 ps
CPU time 0.85 seconds
Started Dec 27 12:57:43 PM PST 23
Finished Dec 27 12:57:46 PM PST 23
Peak memory 214316 kb
Host smart-108c5d4e-869f-4c7a-b528-22d971c61580
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077611221 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.4077611221
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.3997288155
Short name T718
Test name
Test status
Simulation time 57961535 ps
CPU time 0.95 seconds
Started Dec 27 12:57:49 PM PST 23
Finished Dec 27 12:57:51 PM PST 23
Peak memory 214576 kb
Host smart-e7c5f162-c41d-42c6-8a41-1e373e9e1b69
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997288155 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.3997288155
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.3418024413
Short name T533
Test name
Test status
Simulation time 32482811 ps
CPU time 0.89 seconds
Started Dec 27 12:57:57 PM PST 23
Finished Dec 27 12:57:59 PM PST 23
Peak memory 215560 kb
Host smart-f55242db-1ae9-47be-b728-1af405716382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418024413 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.3418024413
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_intr.2652163465
Short name T91
Test name
Test status
Simulation time 28082923 ps
CPU time 1.11 seconds
Started Dec 27 12:58:03 PM PST 23
Finished Dec 27 12:58:11 PM PST 23
Peak memory 214500 kb
Host smart-77677655-7668-4195-bf9e-7f9b71f77e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652163465 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.2652163465
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.3032121584
Short name T61
Test name
Test status
Simulation time 16986166 ps
CPU time 0.92 seconds
Started Dec 27 12:57:44 PM PST 23
Finished Dec 27 12:57:47 PM PST 23
Peak memory 204764 kb
Host smart-03df473d-2b59-440f-ba1a-5333d2f457ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032121584 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.3032121584
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.40596727
Short name T874
Test name
Test status
Simulation time 322801127 ps
CPU time 3.78 seconds
Started Dec 27 12:58:12 PM PST 23
Finished Dec 27 12:58:25 PM PST 23
Peak memory 206008 kb
Host smart-a22983cf-8eb2-4f53-8f9e-6c600e1139fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40596727 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.40596727
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.2869562666
Short name T774
Test name
Test status
Simulation time 30016138695 ps
CPU time 675.03 seconds
Started Dec 27 12:57:58 PM PST 23
Finished Dec 27 01:09:16 PM PST 23
Peak memory 214448 kb
Host smart-8ef3acb3-971e-4e8e-8c59-2b7e4ae9cabe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869562666 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.2869562666
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.1637886843
Short name T527
Test name
Test status
Simulation time 17450688 ps
CPU time 1.07 seconds
Started Dec 27 12:59:07 PM PST 23
Finished Dec 27 12:59:18 PM PST 23
Peak memory 214176 kb
Host smart-981e1dac-855f-4cbc-95a1-b06f2b9abdee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637886843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.1637886843
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.1474291151
Short name T59
Test name
Test status
Simulation time 154843024 ps
CPU time 0.99 seconds
Started Dec 27 12:59:05 PM PST 23
Finished Dec 27 12:59:15 PM PST 23
Peak memory 205608 kb
Host smart-69f5ef6d-5e57-4319-9676-30b1a3c798b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474291151 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.1474291151
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.1068028080
Short name T482
Test name
Test status
Simulation time 77877158 ps
CPU time 1.02 seconds
Started Dec 27 12:59:17 PM PST 23
Finished Dec 27 12:59:29 PM PST 23
Peak memory 204984 kb
Host smart-6f240a66-91bd-45fd-99b3-4c4cbdad437c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068028080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.1068028080
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.2169669274
Short name T631
Test name
Test status
Simulation time 43466831 ps
CPU time 1.94 seconds
Started Dec 27 12:59:04 PM PST 23
Finished Dec 27 12:59:14 PM PST 23
Peak memory 214232 kb
Host smart-f79c0f4d-0cff-4718-bab2-e36ff441466c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169669274 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.2169669274
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.3540585713
Short name T539
Test name
Test status
Simulation time 1332560667 ps
CPU time 9.73 seconds
Started Dec 27 12:59:05 PM PST 23
Finished Dec 27 12:59:23 PM PST 23
Peak memory 214108 kb
Host smart-22aa3300-4b6e-4a0a-b22f-6a4f115aaf95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540585713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.3540585713
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.3737136319
Short name T808
Test name
Test status
Simulation time 41652340 ps
CPU time 0.96 seconds
Started Dec 27 12:59:12 PM PST 23
Finished Dec 27 12:59:23 PM PST 23
Peak memory 205716 kb
Host smart-3a7b95ea-0ab3-44b3-a757-d5af3d077133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737136319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.3737136319
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.2821541874
Short name T659
Test name
Test status
Simulation time 18547334 ps
CPU time 0.97 seconds
Started Dec 27 12:59:19 PM PST 23
Finished Dec 27 12:59:31 PM PST 23
Peak memory 204872 kb
Host smart-cd147ea3-ea73-4956-9146-e06b8a8829ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821541874 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.2821541874
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.972539530
Short name T557
Test name
Test status
Simulation time 18956598 ps
CPU time 1.1 seconds
Started Dec 27 12:59:06 PM PST 23
Finished Dec 27 12:59:16 PM PST 23
Peak memory 214152 kb
Host smart-fc50436c-67cd-48c6-954c-e518241bba03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972539530 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.972539530
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.3063342680
Short name T953
Test name
Test status
Simulation time 26999109 ps
CPU time 0.94 seconds
Started Dec 27 12:59:15 PM PST 23
Finished Dec 27 12:59:28 PM PST 23
Peak memory 205032 kb
Host smart-899178ff-fb9b-4677-ad99-d50eaf12b23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063342680 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.3063342680
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.836659800
Short name T761
Test name
Test status
Simulation time 21681462 ps
CPU time 1.04 seconds
Started Dec 27 12:58:01 PM PST 23
Finished Dec 27 12:58:08 PM PST 23
Peak memory 205800 kb
Host smart-cd9239ca-96c5-4d3b-a601-cf99e1a64230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836659800 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.836659800
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.3546997387
Short name T621
Test name
Test status
Simulation time 16135453 ps
CPU time 0.95 seconds
Started Dec 27 12:57:50 PM PST 23
Finished Dec 27 12:57:52 PM PST 23
Peak memory 205092 kb
Host smart-89e539e7-9b3d-4652-886b-de4c4e4d6c8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546997387 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3546997387
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.3193572123
Short name T154
Test name
Test status
Simulation time 22557675 ps
CPU time 0.87 seconds
Started Dec 27 12:57:59 PM PST 23
Finished Dec 27 12:58:03 PM PST 23
Peak memory 214184 kb
Host smart-c86df4de-cccb-499c-8226-95cc282443b3
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193572123 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.3193572123
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_err.2332647042
Short name T730
Test name
Test status
Simulation time 21160686 ps
CPU time 1.16 seconds
Started Dec 27 12:58:00 PM PST 23
Finished Dec 27 12:58:05 PM PST 23
Peak memory 221724 kb
Host smart-482434bc-4a2e-46ab-a7b4-f6b8fc8724a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332647042 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.2332647042
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.4289400340
Short name T69
Test name
Test status
Simulation time 54185411 ps
CPU time 1.66 seconds
Started Dec 27 12:57:59 PM PST 23
Finished Dec 27 12:58:04 PM PST 23
Peak memory 214164 kb
Host smart-a90c096c-c0de-4d47-8956-781c31eaa052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289400340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.4289400340
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.1859058571
Short name T779
Test name
Test status
Simulation time 25093053 ps
CPU time 0.87 seconds
Started Dec 27 12:58:03 PM PST 23
Finished Dec 27 12:58:12 PM PST 23
Peak memory 214472 kb
Host smart-1230d2a1-e703-4b0b-9bd4-b9e7376c2987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859058571 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.1859058571
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.4114113314
Short name T602
Test name
Test status
Simulation time 11946604 ps
CPU time 0.88 seconds
Started Dec 27 12:58:28 PM PST 23
Finished Dec 27 12:58:40 PM PST 23
Peak memory 204680 kb
Host smart-50be479a-af10-4aea-a9f8-daec67cdaa6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114113314 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.4114113314
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.656027547
Short name T522
Test name
Test status
Simulation time 393985504 ps
CPU time 4.15 seconds
Started Dec 27 12:58:25 PM PST 23
Finished Dec 27 12:58:41 PM PST 23
Peak memory 206052 kb
Host smart-915041a3-bd52-476c-b7d4-91a9395bbafa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656027547 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.656027547
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/130.edn_genbits.1623897268
Short name T905
Test name
Test status
Simulation time 97980108 ps
CPU time 0.93 seconds
Started Dec 27 12:59:05 PM PST 23
Finished Dec 27 12:59:15 PM PST 23
Peak memory 205364 kb
Host smart-edb82d0c-07c5-4738-8b3b-d77f65449049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623897268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1623897268
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.1825039147
Short name T536
Test name
Test status
Simulation time 73750638 ps
CPU time 2.13 seconds
Started Dec 27 12:59:03 PM PST 23
Finished Dec 27 12:59:13 PM PST 23
Peak memory 214104 kb
Host smart-6f5edff3-fc15-431b-bc25-691794b1a0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825039147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.1825039147
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.1567804116
Short name T797
Test name
Test status
Simulation time 18195385 ps
CPU time 1.09 seconds
Started Dec 27 12:59:18 PM PST 23
Finished Dec 27 12:59:30 PM PST 23
Peak memory 205692 kb
Host smart-338e54cb-f761-4531-82c4-6fb7efcc4427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567804116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.1567804116
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.3627919640
Short name T947
Test name
Test status
Simulation time 37288667 ps
CPU time 1.63 seconds
Started Dec 27 12:59:05 PM PST 23
Finished Dec 27 12:59:15 PM PST 23
Peak memory 214220 kb
Host smart-e97be0b3-429c-4279-b55b-fecd38536003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627919640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.3627919640
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.2631707340
Short name T314
Test name
Test status
Simulation time 69302373 ps
CPU time 1.02 seconds
Started Dec 27 12:59:20 PM PST 23
Finished Dec 27 12:59:32 PM PST 23
Peak memory 205360 kb
Host smart-8c7db464-e1bf-4032-8341-c31ab8075974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631707340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.2631707340
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.842210255
Short name T352
Test name
Test status
Simulation time 16478023 ps
CPU time 0.94 seconds
Started Dec 27 12:59:01 PM PST 23
Finished Dec 27 12:59:09 PM PST 23
Peak memory 205000 kb
Host smart-748efc26-ef47-47e6-ae40-b29ef0097dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842210255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.842210255
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.3573871712
Short name T510
Test name
Test status
Simulation time 49736074 ps
CPU time 1.03 seconds
Started Dec 27 12:58:52 PM PST 23
Finished Dec 27 12:59:00 PM PST 23
Peak memory 214064 kb
Host smart-b1fc6183-27a9-4a29-9f29-f76016830374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573871712 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.3573871712
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.1301224678
Short name T885
Test name
Test status
Simulation time 15554306 ps
CPU time 0.95 seconds
Started Dec 27 12:59:23 PM PST 23
Finished Dec 27 12:59:34 PM PST 23
Peak memory 204912 kb
Host smart-5e61544d-8403-4cf0-91c6-546ef28a26d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301224678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1301224678
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.947799688
Short name T582
Test name
Test status
Simulation time 13557940 ps
CPU time 0.94 seconds
Started Dec 27 12:59:16 PM PST 23
Finished Dec 27 12:59:28 PM PST 23
Peak memory 205424 kb
Host smart-5204e1d3-4861-4fd2-bc8d-2a0da75c629b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947799688 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.947799688
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.1539521446
Short name T295
Test name
Test status
Simulation time 51734761 ps
CPU time 0.93 seconds
Started Dec 27 12:58:03 PM PST 23
Finished Dec 27 12:58:11 PM PST 23
Peak memory 205940 kb
Host smart-0a137620-e3c5-437c-8c8b-892f1c8f4229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539521446 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.1539521446
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.3487440124
Short name T723
Test name
Test status
Simulation time 93374753 ps
CPU time 0.86 seconds
Started Dec 27 12:58:01 PM PST 23
Finished Dec 27 12:58:08 PM PST 23
Peak memory 205476 kb
Host smart-f6b43af0-5ebf-4a98-8fdb-4d8774b60f4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487440124 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3487440124
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.3677401582
Short name T114
Test name
Test status
Simulation time 70157750 ps
CPU time 0.83 seconds
Started Dec 27 12:58:12 PM PST 23
Finished Dec 27 12:58:22 PM PST 23
Peak memory 214336 kb
Host smart-1a4d7085-a083-4c8a-b8ce-dcdc5c6ec0a5
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677401582 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.3677401582
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.3352645374
Short name T508
Test name
Test status
Simulation time 86539837 ps
CPU time 0.98 seconds
Started Dec 27 12:57:53 PM PST 23
Finished Dec 27 12:57:55 PM PST 23
Peak memory 214356 kb
Host smart-ba0547a2-35ea-4545-a3ef-1e0a620c16f4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352645374 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.3352645374
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_genbits.4150084397
Short name T571
Test name
Test status
Simulation time 70748004 ps
CPU time 1.12 seconds
Started Dec 27 12:58:04 PM PST 23
Finished Dec 27 12:58:13 PM PST 23
Peak memory 214176 kb
Host smart-ede5a999-87ae-446b-ade2-bccdcdfbe5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150084397 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.4150084397
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.1859461304
Short name T562
Test name
Test status
Simulation time 19312324 ps
CPU time 1.16 seconds
Started Dec 27 12:58:02 PM PST 23
Finished Dec 27 12:58:09 PM PST 23
Peak memory 221864 kb
Host smart-498ebb83-adaa-4fa5-bd61-8a30529cf168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859461304 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.1859461304
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.2714335310
Short name T544
Test name
Test status
Simulation time 14993139 ps
CPU time 0.92 seconds
Started Dec 27 12:57:56 PM PST 23
Finished Dec 27 12:57:58 PM PST 23
Peak memory 204608 kb
Host smart-b996c64f-a92e-43d7-a926-b0396531bf53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714335310 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.2714335310
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.1563905524
Short name T311
Test name
Test status
Simulation time 559696479 ps
CPU time 1.6 seconds
Started Dec 27 12:57:37 PM PST 23
Finished Dec 27 12:57:42 PM PST 23
Peak memory 205688 kb
Host smart-485d791d-410b-41ab-9bae-694b0fce260f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563905524 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.1563905524
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.3217569407
Short name T831
Test name
Test status
Simulation time 248197655789 ps
CPU time 1303.19 seconds
Started Dec 27 12:58:00 PM PST 23
Finished Dec 27 01:19:47 PM PST 23
Peak memory 219604 kb
Host smart-4d3ee738-f77f-4225-8b9d-e1b48ddbc890
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217569407 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.3217569407
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.3823769124
Short name T967
Test name
Test status
Simulation time 14996781 ps
CPU time 1.05 seconds
Started Dec 27 12:59:13 PM PST 23
Finished Dec 27 12:59:25 PM PST 23
Peak memory 205440 kb
Host smart-132f8a0b-6882-4833-878b-5a4d73744102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823769124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.3823769124
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.4112850067
Short name T881
Test name
Test status
Simulation time 21818974 ps
CPU time 1.21 seconds
Started Dec 27 12:59:10 PM PST 23
Finished Dec 27 12:59:22 PM PST 23
Peak memory 214036 kb
Host smart-767a34b4-64ab-43d7-8862-c075814675eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112850067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.4112850067
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.4002998989
Short name T750
Test name
Test status
Simulation time 17545795 ps
CPU time 1.06 seconds
Started Dec 27 12:58:57 PM PST 23
Finished Dec 27 12:59:05 PM PST 23
Peak memory 205596 kb
Host smart-63cf15a9-be33-405c-bf95-22ea043f382e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002998989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.4002998989
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.3109030297
Short name T926
Test name
Test status
Simulation time 20641974 ps
CPU time 1.1 seconds
Started Dec 27 12:58:58 PM PST 23
Finished Dec 27 12:59:06 PM PST 23
Peak memory 214176 kb
Host smart-ceb341ff-fb75-4951-9485-24fdb145253e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109030297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.3109030297
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.1697877501
Short name T76
Test name
Test status
Simulation time 54424998 ps
CPU time 0.91 seconds
Started Dec 27 12:58:52 PM PST 23
Finished Dec 27 12:59:00 PM PST 23
Peak memory 205420 kb
Host smart-0e92bbca-b49e-4bf3-a280-e98d1f3c0791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697877501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.1697877501
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.2634037693
Short name T489
Test name
Test status
Simulation time 50202868 ps
CPU time 1.81 seconds
Started Dec 27 12:59:00 PM PST 23
Finished Dec 27 12:59:10 PM PST 23
Peak memory 214228 kb
Host smart-61b4a91b-89eb-4c9f-9550-91628f8d1403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634037693 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.2634037693
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.3787037553
Short name T708
Test name
Test status
Simulation time 20331389 ps
CPU time 1.07 seconds
Started Dec 27 12:58:59 PM PST 23
Finished Dec 27 12:59:08 PM PST 23
Peak memory 205256 kb
Host smart-963549dd-cf00-483c-80ec-c364b3b3bc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787037553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.3787037553
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.219566190
Short name T734
Test name
Test status
Simulation time 20192071 ps
CPU time 1.03 seconds
Started Dec 27 12:58:04 PM PST 23
Finished Dec 27 12:58:13 PM PST 23
Peak memory 205256 kb
Host smart-81b0cf5a-6b2c-4df1-9a6b-7209a0b8ed32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219566190 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.219566190
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.3672534774
Short name T788
Test name
Test status
Simulation time 23759176 ps
CPU time 0.85 seconds
Started Dec 27 12:57:59 PM PST 23
Finished Dec 27 12:58:03 PM PST 23
Peak memory 204604 kb
Host smart-8a791aa7-1f9a-4601-9fd6-8d6e832bceb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672534774 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.3672534774
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_err.443672050
Short name T789
Test name
Test status
Simulation time 118802785 ps
CPU time 1.06 seconds
Started Dec 27 12:58:05 PM PST 23
Finished Dec 27 12:58:13 PM PST 23
Peak memory 221720 kb
Host smart-f7cb97f3-ab38-4ff0-81a8-89124a527ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443672050 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.443672050
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.2503056791
Short name T879
Test name
Test status
Simulation time 62509937 ps
CPU time 1 seconds
Started Dec 27 12:57:48 PM PST 23
Finished Dec 27 12:57:50 PM PST 23
Peak memory 205348 kb
Host smart-520eacd1-baad-49d0-8fe6-29969dd162e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503056791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.2503056791
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.2319744621
Short name T865
Test name
Test status
Simulation time 18194374 ps
CPU time 1.08 seconds
Started Dec 27 12:57:49 PM PST 23
Finished Dec 27 12:57:52 PM PST 23
Peak memory 214504 kb
Host smart-d5096c4b-99ba-4cc4-b3a5-4ad9489b878f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319744621 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.2319744621
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.577815144
Short name T559
Test name
Test status
Simulation time 39777658 ps
CPU time 0.82 seconds
Started Dec 27 12:57:47 PM PST 23
Finished Dec 27 12:57:49 PM PST 23
Peak memory 204644 kb
Host smart-2ee87ff1-111c-4497-9f2e-d36cb44625df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577815144 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.577815144
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.1210930312
Short name T795
Test name
Test status
Simulation time 81101958 ps
CPU time 1.47 seconds
Started Dec 27 12:57:49 PM PST 23
Finished Dec 27 12:57:52 PM PST 23
Peak memory 205716 kb
Host smart-c0708f19-6009-4f42-9b13-ca7c790006a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210930312 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.1210930312
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.2083129252
Short name T613
Test name
Test status
Simulation time 45709535065 ps
CPU time 999.39 seconds
Started Dec 27 12:58:08 PM PST 23
Finished Dec 27 01:14:55 PM PST 23
Peak memory 214496 kb
Host smart-d7916e9f-85ba-442c-898e-8fdca1605f2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083129252 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.2083129252
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.1159061349
Short name T677
Test name
Test status
Simulation time 46500255 ps
CPU time 0.9 seconds
Started Dec 27 12:59:03 PM PST 23
Finished Dec 27 12:59:12 PM PST 23
Peak memory 205080 kb
Host smart-1c115d6c-b732-43a9-bf64-e67cc3788e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159061349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.1159061349
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.3896248823
Short name T282
Test name
Test status
Simulation time 41548611 ps
CPU time 0.99 seconds
Started Dec 27 12:59:13 PM PST 23
Finished Dec 27 12:59:25 PM PST 23
Peak memory 205244 kb
Host smart-67b98875-8f15-44ba-9f3b-8489b61bbb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896248823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.3896248823
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.2367304679
Short name T785
Test name
Test status
Simulation time 29385887 ps
CPU time 1.34 seconds
Started Dec 27 12:59:11 PM PST 23
Finished Dec 27 12:59:23 PM PST 23
Peak memory 214196 kb
Host smart-e259038c-bb34-4bac-903f-cf20537cfaa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367304679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.2367304679
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.3148442147
Short name T854
Test name
Test status
Simulation time 21665888 ps
CPU time 0.96 seconds
Started Dec 27 12:59:10 PM PST 23
Finished Dec 27 12:59:22 PM PST 23
Peak memory 205036 kb
Host smart-88112e45-ca75-4a89-ae7b-99e44e9c0acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148442147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.3148442147
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.1041752976
Short name T742
Test name
Test status
Simulation time 28696601 ps
CPU time 0.95 seconds
Started Dec 27 12:59:13 PM PST 23
Finished Dec 27 12:59:24 PM PST 23
Peak memory 205004 kb
Host smart-90e1fd94-1dcf-48cc-9c5c-5fa30051ad9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041752976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1041752976
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.2650440751
Short name T51
Test name
Test status
Simulation time 50430581 ps
CPU time 0.9 seconds
Started Dec 27 12:59:30 PM PST 23
Finished Dec 27 12:59:38 PM PST 23
Peak memory 205112 kb
Host smart-e665f573-71b0-46b3-9135-24cc23d55df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650440751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.2650440751
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.4217075083
Short name T530
Test name
Test status
Simulation time 43374172 ps
CPU time 1.35 seconds
Started Dec 27 12:59:28 PM PST 23
Finished Dec 27 12:59:37 PM PST 23
Peak memory 205628 kb
Host smart-24acc587-58cd-4e48-bec4-23e3f40c1c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217075083 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.4217075083
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.1015945265
Short name T747
Test name
Test status
Simulation time 19435009 ps
CPU time 1.22 seconds
Started Dec 27 12:59:18 PM PST 23
Finished Dec 27 12:59:30 PM PST 23
Peak memory 205816 kb
Host smart-476461f8-dcfc-4aa6-9266-ac07b91ee415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015945265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.1015945265
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.2860345310
Short name T343
Test name
Test status
Simulation time 22236458 ps
CPU time 1.08 seconds
Started Dec 27 12:59:07 PM PST 23
Finished Dec 27 12:59:19 PM PST 23
Peak memory 214036 kb
Host smart-b644879a-f383-4f2b-a06d-7688642aed4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860345310 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.2860345310
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.4017596823
Short name T507
Test name
Test status
Simulation time 16942026 ps
CPU time 1.02 seconds
Started Dec 27 12:59:18 PM PST 23
Finished Dec 27 12:59:30 PM PST 23
Peak memory 205376 kb
Host smart-1760543a-4f3d-4ee2-9184-12c397e093e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017596823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.4017596823
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.1224407952
Short name T916
Test name
Test status
Simulation time 17733140 ps
CPU time 1.02 seconds
Started Dec 27 12:58:10 PM PST 23
Finished Dec 27 12:58:20 PM PST 23
Peak memory 205944 kb
Host smart-c0ba1d97-62b0-4bc4-be6c-64fa89bba95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224407952 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.1224407952
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.1997639094
Short name T577
Test name
Test status
Simulation time 22211919 ps
CPU time 0.81 seconds
Started Dec 27 12:58:01 PM PST 23
Finished Dec 27 12:58:09 PM PST 23
Peak memory 204320 kb
Host smart-dbb2ce6c-0650-458d-8d3e-87e987bfd99e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997639094 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.1997639094
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.2246348190
Short name T793
Test name
Test status
Simulation time 14307799 ps
CPU time 0.87 seconds
Started Dec 27 12:58:01 PM PST 23
Finished Dec 27 12:58:08 PM PST 23
Peak memory 214428 kb
Host smart-158e7d5c-b7e4-428e-ae44-0d2ae129bbfc
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246348190 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2246348190
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.552439732
Short name T497
Test name
Test status
Simulation time 16409017 ps
CPU time 0.93 seconds
Started Dec 27 12:57:58 PM PST 23
Finished Dec 27 12:58:02 PM PST 23
Peak memory 214392 kb
Host smart-091063e1-34ee-4d7c-8b2a-b2a5e7c66898
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552439732 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_di
sable_auto_req_mode.552439732
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.1236454840
Short name T64
Test name
Test status
Simulation time 19998414 ps
CPU time 0.88 seconds
Started Dec 27 12:57:59 PM PST 23
Finished Dec 27 12:58:03 PM PST 23
Peak memory 215464 kb
Host smart-b1a87172-1e29-42fe-b012-cf416e59c864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236454840 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.1236454840
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.33268967
Short name T642
Test name
Test status
Simulation time 61356787 ps
CPU time 0.94 seconds
Started Dec 27 12:58:07 PM PST 23
Finished Dec 27 12:58:14 PM PST 23
Peak memory 205496 kb
Host smart-5946ea00-2f44-4796-a853-65474405a469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33268967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.33268967
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.625747478
Short name T919
Test name
Test status
Simulation time 19038615 ps
CPU time 1.05 seconds
Started Dec 27 12:58:02 PM PST 23
Finished Dec 27 12:58:10 PM PST 23
Peak memory 214316 kb
Host smart-5a9f7696-fb85-472f-bae1-1f0448e6fe2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625747478 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.625747478
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.1332229785
Short name T591
Test name
Test status
Simulation time 13639411 ps
CPU time 0.93 seconds
Started Dec 27 12:57:52 PM PST 23
Finished Dec 27 12:57:55 PM PST 23
Peak memory 204808 kb
Host smart-4c8b25fa-4c70-4184-91a7-59f5664bc91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332229785 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.1332229785
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.2100738567
Short name T937
Test name
Test status
Simulation time 270265141 ps
CPU time 1.96 seconds
Started Dec 27 12:58:01 PM PST 23
Finished Dec 27 12:58:08 PM PST 23
Peak memory 205680 kb
Host smart-ad656b36-fd19-44d2-a41d-af6e2f4e7771
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100738567 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2100738567
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/160.edn_genbits.3358357475
Short name T33
Test name
Test status
Simulation time 23747612 ps
CPU time 1.05 seconds
Started Dec 27 12:59:23 PM PST 23
Finished Dec 27 12:59:34 PM PST 23
Peak memory 205624 kb
Host smart-6e1a743b-2382-456e-846c-82216ebc729b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358357475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.3358357475
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.620219583
Short name T744
Test name
Test status
Simulation time 16474397 ps
CPU time 0.94 seconds
Started Dec 27 12:59:12 PM PST 23
Finished Dec 27 12:59:23 PM PST 23
Peak memory 205052 kb
Host smart-1834afce-d162-4f2b-bd9c-85b249f9e018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620219583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.620219583
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.3147438067
Short name T563
Test name
Test status
Simulation time 44530304 ps
CPU time 1.05 seconds
Started Dec 27 12:59:28 PM PST 23
Finished Dec 27 12:59:37 PM PST 23
Peak memory 205376 kb
Host smart-e4011a2b-aac3-4ea7-90a8-e56ed5b6f09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147438067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.3147438067
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.2650868502
Short name T629
Test name
Test status
Simulation time 17837090 ps
CPU time 0.96 seconds
Started Dec 27 12:59:11 PM PST 23
Finished Dec 27 12:59:23 PM PST 23
Peak memory 204796 kb
Host smart-dc44414f-a351-405e-a782-a2074f1a8e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650868502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.2650868502
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.3276895801
Short name T514
Test name
Test status
Simulation time 48905578 ps
CPU time 2.2 seconds
Started Dec 27 12:59:11 PM PST 23
Finished Dec 27 12:59:23 PM PST 23
Peak memory 214184 kb
Host smart-aa1645d5-c7c3-4161-b43a-0a7f7c9935a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276895801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3276895801
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.4142192869
Short name T317
Test name
Test status
Simulation time 19301804 ps
CPU time 1.01 seconds
Started Dec 27 12:59:39 PM PST 23
Finished Dec 27 12:59:45 PM PST 23
Peak memory 205360 kb
Host smart-5305f067-a7d7-402f-9b43-ed2b202a4d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142192869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.4142192869
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.3874483681
Short name T666
Test name
Test status
Simulation time 78408752 ps
CPU time 0.93 seconds
Started Dec 27 12:59:18 PM PST 23
Finished Dec 27 12:59:30 PM PST 23
Peak memory 205060 kb
Host smart-264141ae-5c80-44d2-8d0a-64ac72122aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874483681 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.3874483681
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.3502804948
Short name T18
Test name
Test status
Simulation time 97883150 ps
CPU time 1.01 seconds
Started Dec 27 12:58:16 PM PST 23
Finished Dec 27 12:58:26 PM PST 23
Peak memory 205832 kb
Host smart-300da6ba-80b9-416d-b2ab-ae0de796d6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502804948 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.3502804948
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.1758053539
Short name T500
Test name
Test status
Simulation time 39450373 ps
CPU time 0.82 seconds
Started Dec 27 12:58:00 PM PST 23
Finished Dec 27 12:58:04 PM PST 23
Peak memory 204316 kb
Host smart-5c319919-9681-4635-aa04-e46043363827
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758053539 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.1758053539
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.3083429449
Short name T634
Test name
Test status
Simulation time 43011784 ps
CPU time 1.04 seconds
Started Dec 27 12:58:07 PM PST 23
Finished Dec 27 12:58:14 PM PST 23
Peak memory 214464 kb
Host smart-87cb2d2e-e5ef-4dec-9803-e091dd63e6ea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083429449 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.3083429449
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.2336623810
Short name T965
Test name
Test status
Simulation time 18333725 ps
CPU time 1.27 seconds
Started Dec 27 12:58:42 PM PST 23
Finished Dec 27 12:58:51 PM PST 23
Peak memory 216000 kb
Host smart-5719cbf1-9ea0-4920-8701-e8049f82dd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336623810 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.2336623810
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.1195987979
Short name T628
Test name
Test status
Simulation time 31351116 ps
CPU time 1.08 seconds
Started Dec 27 12:58:07 PM PST 23
Finished Dec 27 12:58:13 PM PST 23
Peak memory 214128 kb
Host smart-f68a54a4-f679-4a34-9e64-0238a6ef3615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195987979 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.1195987979
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.497343409
Short name T935
Test name
Test status
Simulation time 18240811 ps
CPU time 0.98 seconds
Started Dec 27 12:58:17 PM PST 23
Finished Dec 27 12:58:27 PM PST 23
Peak memory 214508 kb
Host smart-9485fc1f-08c6-4352-aebd-3dccce10b0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497343409 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.497343409
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.2664811766
Short name T637
Test name
Test status
Simulation time 13453708 ps
CPU time 0.89 seconds
Started Dec 27 12:58:15 PM PST 23
Finished Dec 27 12:58:26 PM PST 23
Peak memory 204960 kb
Host smart-6ed8a8a4-8b7a-4ade-ba2f-aeb412691752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664811766 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.2664811766
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.403227424
Short name T360
Test name
Test status
Simulation time 348646993 ps
CPU time 4.06 seconds
Started Dec 27 12:57:45 PM PST 23
Finished Dec 27 12:57:50 PM PST 23
Peak memory 206040 kb
Host smart-64af3237-731d-409a-a921-b5b06ac93605
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403227424 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.403227424
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.2198336199
Short name T576
Test name
Test status
Simulation time 29565254536 ps
CPU time 774.69 seconds
Started Dec 27 12:58:13 PM PST 23
Finished Dec 27 01:11:17 PM PST 23
Peak memory 215460 kb
Host smart-836fb8bd-4524-4367-b594-46ef6efc21f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198336199 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.2198336199
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.1155615824
Short name T554
Test name
Test status
Simulation time 35589466 ps
CPU time 0.88 seconds
Started Dec 27 12:59:05 PM PST 23
Finished Dec 27 12:59:14 PM PST 23
Peak memory 205000 kb
Host smart-2faac3ab-35aa-491f-bd1c-045988eec046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155615824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.1155615824
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.1688919709
Short name T857
Test name
Test status
Simulation time 74259640 ps
CPU time 1.25 seconds
Started Dec 27 12:59:06 PM PST 23
Finished Dec 27 12:59:16 PM PST 23
Peak memory 205712 kb
Host smart-5dce3161-5258-4ce7-b28b-34f80fe2783e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688919709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.1688919709
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.2826027121
Short name T914
Test name
Test status
Simulation time 84826666 ps
CPU time 1.01 seconds
Started Dec 27 12:59:09 PM PST 23
Finished Dec 27 12:59:21 PM PST 23
Peak memory 205084 kb
Host smart-8cd93ce0-6a46-4d09-b3ba-cb8814f7d2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826027121 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.2826027121
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.3734416434
Short name T877
Test name
Test status
Simulation time 150425556 ps
CPU time 1.08 seconds
Started Dec 27 12:59:12 PM PST 23
Finished Dec 27 12:59:23 PM PST 23
Peak memory 205844 kb
Host smart-61779cda-0b48-4dae-9bb2-426058f2fc1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734416434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.3734416434
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.4189145482
Short name T329
Test name
Test status
Simulation time 28618277 ps
CPU time 0.93 seconds
Started Dec 27 12:59:07 PM PST 23
Finished Dec 27 12:59:18 PM PST 23
Peak memory 205156 kb
Host smart-9243dceb-47f3-42e7-bc87-c5b18537ba6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189145482 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.4189145482
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.3845024866
Short name T534
Test name
Test status
Simulation time 30697245 ps
CPU time 1.18 seconds
Started Dec 27 12:59:04 PM PST 23
Finished Dec 27 12:59:13 PM PST 23
Peak memory 205516 kb
Host smart-0a21fd60-f055-4420-90da-2834a442cf2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845024866 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.3845024866
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.1058175764
Short name T283
Test name
Test status
Simulation time 27388751 ps
CPU time 0.93 seconds
Started Dec 27 12:59:12 PM PST 23
Finished Dec 27 12:59:23 PM PST 23
Peak memory 205276 kb
Host smart-9d57e881-2525-4825-bfb7-239a242cbc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058175764 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.1058175764
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.2072074048
Short name T32
Test name
Test status
Simulation time 53894893 ps
CPU time 1.07 seconds
Started Dec 27 12:58:56 PM PST 23
Finished Dec 27 12:59:03 PM PST 23
Peak memory 205436 kb
Host smart-78b8692c-f0aa-4507-adc8-374c012b70ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072074048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.2072074048
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.4128306136
Short name T501
Test name
Test status
Simulation time 45297930 ps
CPU time 1.94 seconds
Started Dec 27 12:59:03 PM PST 23
Finished Dec 27 12:59:13 PM PST 23
Peak memory 214180 kb
Host smart-fc216b8a-1b84-40c4-9460-fe9ca183371c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128306136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.4128306136
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.43794370
Short name T1
Test name
Test status
Simulation time 35246144 ps
CPU time 1.02 seconds
Started Dec 27 12:58:54 PM PST 23
Finished Dec 27 12:59:01 PM PST 23
Peak memory 205608 kb
Host smart-d58e044c-9066-436d-b485-94006954b2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43794370 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.43794370
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.3967726771
Short name T704
Test name
Test status
Simulation time 67285746 ps
CPU time 0.92 seconds
Started Dec 27 12:58:08 PM PST 23
Finished Dec 27 12:58:16 PM PST 23
Peak memory 205212 kb
Host smart-9229043c-0280-4e8c-8ae7-8d4d1ce42d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967726771 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.3967726771
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.1067417660
Short name T458
Test name
Test status
Simulation time 30651206 ps
CPU time 0.92 seconds
Started Dec 27 12:58:02 PM PST 23
Finished Dec 27 12:58:10 PM PST 23
Peak memory 204448 kb
Host smart-026d3e87-1d37-4445-b171-2c2ebbf37a5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067417660 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.1067417660
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.358144127
Short name T160
Test name
Test status
Simulation time 23577358 ps
CPU time 0.85 seconds
Started Dec 27 12:58:13 PM PST 23
Finished Dec 27 12:58:24 PM PST 23
Peak memory 214280 kb
Host smart-e03ee511-36cd-4419-b6a7-b0668305c214
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358144127 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.358144127
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.3476710249
Short name T103
Test name
Test status
Simulation time 52400213 ps
CPU time 1.08 seconds
Started Dec 27 12:58:12 PM PST 23
Finished Dec 27 12:58:22 PM PST 23
Peak memory 214532 kb
Host smart-43a6ab1a-0358-4ae9-81cd-f08b9f791ca9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476710249 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.3476710249
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.1657909992
Short name T136
Test name
Test status
Simulation time 34400445 ps
CPU time 1.16 seconds
Started Dec 27 12:58:06 PM PST 23
Finished Dec 27 12:58:13 PM PST 23
Peak memory 221664 kb
Host smart-6e6e510f-df82-4906-97fc-82780e396454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657909992 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.1657909992
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.2876020933
Short name T755
Test name
Test status
Simulation time 224299564 ps
CPU time 2.91 seconds
Started Dec 27 12:58:20 PM PST 23
Finished Dec 27 12:58:35 PM PST 23
Peak memory 214200 kb
Host smart-049d75d5-92c6-462e-9f99-4d49cc18420d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876020933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.2876020933
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.2431927998
Short name T740
Test name
Test status
Simulation time 19914748 ps
CPU time 0.98 seconds
Started Dec 27 12:58:08 PM PST 23
Finished Dec 27 12:58:16 PM PST 23
Peak memory 214436 kb
Host smart-72d32717-312c-4f30-a7dc-ecdb753cf2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431927998 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.2431927998
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.4172624705
Short name T465
Test name
Test status
Simulation time 120634945 ps
CPU time 0.89 seconds
Started Dec 27 12:58:11 PM PST 23
Finished Dec 27 12:58:22 PM PST 23
Peak memory 204880 kb
Host smart-104225d3-857b-47b8-b6c3-b8b73a6e5a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172624705 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.4172624705
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.1593000083
Short name T974
Test name
Test status
Simulation time 65276417 ps
CPU time 1.92 seconds
Started Dec 27 12:58:04 PM PST 23
Finished Dec 27 12:58:14 PM PST 23
Peak memory 205860 kb
Host smart-28ff00b6-d826-4e5d-a4af-fa122330828d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593000083 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1593000083
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.154830106
Short name T807
Test name
Test status
Simulation time 444231710948 ps
CPU time 1600.89 seconds
Started Dec 27 12:58:04 PM PST 23
Finished Dec 27 01:24:53 PM PST 23
Peak memory 217884 kb
Host smart-b782229d-fd88-405e-878c-b4c79db50860
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154830106 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.154830106
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.347431485
Short name T701
Test name
Test status
Simulation time 60982227 ps
CPU time 0.99 seconds
Started Dec 27 12:59:02 PM PST 23
Finished Dec 27 12:59:11 PM PST 23
Peak memory 205468 kb
Host smart-38631859-942a-499c-a232-3c511e23395f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347431485 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.347431485
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.3396390609
Short name T30
Test name
Test status
Simulation time 39283617 ps
CPU time 1.39 seconds
Started Dec 27 12:59:09 PM PST 23
Finished Dec 27 12:59:27 PM PST 23
Peak memory 205856 kb
Host smart-9f618a4c-0263-44e9-8233-a0ba1988606d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396390609 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.3396390609
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.4225926095
Short name T79
Test name
Test status
Simulation time 20506257 ps
CPU time 1.04 seconds
Started Dec 27 12:58:54 PM PST 23
Finished Dec 27 12:59:02 PM PST 23
Peak memory 205160 kb
Host smart-1fd27051-b210-48be-a4d2-3fcb6d3a169a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225926095 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.4225926095
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.3673663299
Short name T627
Test name
Test status
Simulation time 47537883 ps
CPU time 1.28 seconds
Started Dec 27 12:59:03 PM PST 23
Finished Dec 27 12:59:13 PM PST 23
Peak memory 214112 kb
Host smart-471d357f-ca52-4b01-9f1d-4c297606ed54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673663299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.3673663299
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.1101780519
Short name T274
Test name
Test status
Simulation time 14576007 ps
CPU time 0.96 seconds
Started Dec 27 12:58:48 PM PST 23
Finished Dec 27 12:58:58 PM PST 23
Peak memory 205000 kb
Host smart-6764cafa-5314-4ee9-b67d-032c80af81b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101780519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.1101780519
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.3239540099
Short name T362
Test name
Test status
Simulation time 51078884 ps
CPU time 1.1 seconds
Started Dec 27 12:58:52 PM PST 23
Finished Dec 27 12:59:00 PM PST 23
Peak memory 214080 kb
Host smart-6fa9e47a-834a-49c5-80c0-d5949ab3a928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239540099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.3239540099
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.3335176737
Short name T956
Test name
Test status
Simulation time 85762921 ps
CPU time 1.07 seconds
Started Dec 27 12:58:58 PM PST 23
Finished Dec 27 12:59:06 PM PST 23
Peak memory 214092 kb
Host smart-4b72216d-5b53-4b80-812f-93db02b6c85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335176737 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.3335176737
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.3363624796
Short name T328
Test name
Test status
Simulation time 93394842 ps
CPU time 2.24 seconds
Started Dec 27 12:59:07 PM PST 23
Finished Dec 27 12:59:27 PM PST 23
Peak memory 214108 kb
Host smart-d2721c42-0352-4c31-b0fe-ae7b37ecd5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363624796 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.3363624796
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.2726752122
Short name T846
Test name
Test status
Simulation time 25735889 ps
CPU time 0.97 seconds
Started Dec 27 12:59:46 PM PST 23
Finished Dec 27 12:59:50 PM PST 23
Peak memory 205464 kb
Host smart-25f1deb6-e42f-41cc-ad69-ff3381b72d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726752122 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.2726752122
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.3530239801
Short name T871
Test name
Test status
Simulation time 32244498 ps
CPU time 1 seconds
Started Dec 27 12:59:03 PM PST 23
Finished Dec 27 12:59:12 PM PST 23
Peak memory 205340 kb
Host smart-d023d8ac-f900-464d-abbf-d8d48426c8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530239801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.3530239801
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.794774099
Short name T309
Test name
Test status
Simulation time 16249624 ps
CPU time 0.94 seconds
Started Dec 27 12:58:09 PM PST 23
Finished Dec 27 12:58:18 PM PST 23
Peak memory 205968 kb
Host smart-85a7380b-c31d-4634-9ee9-424c11386467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794774099 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.794774099
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.3357766295
Short name T583
Test name
Test status
Simulation time 33082415 ps
CPU time 0.97 seconds
Started Dec 27 12:58:34 PM PST 23
Finished Dec 27 12:58:45 PM PST 23
Peak memory 204616 kb
Host smart-a47e4257-8033-4c86-8101-5a4a0550d385
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357766295 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.3357766295
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.1667302772
Short name T685
Test name
Test status
Simulation time 12395829 ps
CPU time 0.89 seconds
Started Dec 27 12:58:08 PM PST 23
Finished Dec 27 12:58:14 PM PST 23
Peak memory 214484 kb
Host smart-037cc27d-b6f4-4240-990f-ec4aadcfa4e9
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667302772 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.1667302772
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.1015447706
Short name T847
Test name
Test status
Simulation time 26236594 ps
CPU time 0.97 seconds
Started Dec 27 12:58:12 PM PST 23
Finished Dec 27 12:58:22 PM PST 23
Peak memory 214512 kb
Host smart-4c85f1bd-a05a-4b7b-a3fb-47b34bb6f39b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015447706 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.1015447706
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.1506858138
Short name T737
Test name
Test status
Simulation time 40369442 ps
CPU time 1.21 seconds
Started Dec 27 12:58:02 PM PST 23
Finished Dec 27 12:58:10 PM PST 23
Peak memory 214876 kb
Host smart-c0a51d46-cb2a-4e37-b35c-b36ecb7deb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506858138 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.1506858138
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.2399074183
Short name T625
Test name
Test status
Simulation time 69772124 ps
CPU time 1.12 seconds
Started Dec 27 12:58:15 PM PST 23
Finished Dec 27 12:58:26 PM PST 23
Peak memory 205564 kb
Host smart-81b0a76c-38f0-489a-bc66-94e7999fab66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399074183 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.2399074183
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_smoke.909096262
Short name T529
Test name
Test status
Simulation time 22438268 ps
CPU time 0.84 seconds
Started Dec 27 12:58:04 PM PST 23
Finished Dec 27 12:58:13 PM PST 23
Peak memory 204564 kb
Host smart-00b9b897-ad46-4185-9f62-5ac75a591011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909096262 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.909096262
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.437468961
Short name T729
Test name
Test status
Simulation time 177961053 ps
CPU time 3.86 seconds
Started Dec 27 12:57:59 PM PST 23
Finished Dec 27 12:58:06 PM PST 23
Peak memory 214204 kb
Host smart-3d42570e-49ab-4319-a702-dc695d13ebb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437468961 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.437468961
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.886683012
Short name T948
Test name
Test status
Simulation time 84345946307 ps
CPU time 1120.96 seconds
Started Dec 27 12:58:06 PM PST 23
Finished Dec 27 01:16:53 PM PST 23
Peak memory 217880 kb
Host smart-d689cfe2-165e-489e-8497-737a374b5219
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886683012 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.886683012
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.2258281721
Short name T636
Test name
Test status
Simulation time 16878162 ps
CPU time 1.01 seconds
Started Dec 27 12:58:53 PM PST 23
Finished Dec 27 12:59:00 PM PST 23
Peak memory 204908 kb
Host smart-ed785d60-7131-454f-9382-f83e88344c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258281721 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.2258281721
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.2402277002
Short name T751
Test name
Test status
Simulation time 26832903 ps
CPU time 1.26 seconds
Started Dec 27 12:58:55 PM PST 23
Finished Dec 27 12:59:03 PM PST 23
Peak memory 205824 kb
Host smart-c8da0d1b-9bf1-4797-aa50-d9c649903771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402277002 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2402277002
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.2141691854
Short name T823
Test name
Test status
Simulation time 31823338 ps
CPU time 1 seconds
Started Dec 27 12:59:08 PM PST 23
Finished Dec 27 12:59:19 PM PST 23
Peak memory 205488 kb
Host smart-0f516f0f-39bd-46b6-86d0-718a8e94903e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141691854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.2141691854
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.1549607152
Short name T714
Test name
Test status
Simulation time 62282472 ps
CPU time 1.04 seconds
Started Dec 27 12:59:05 PM PST 23
Finished Dec 27 12:59:15 PM PST 23
Peak memory 205300 kb
Host smart-aafeaee2-480f-466d-a15d-359ac5b389e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549607152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.1549607152
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.3052182466
Short name T945
Test name
Test status
Simulation time 17633162 ps
CPU time 0.96 seconds
Started Dec 27 12:59:04 PM PST 23
Finished Dec 27 12:59:13 PM PST 23
Peak memory 204888 kb
Host smart-05f013b3-5f43-48fc-8da4-2e45d4243255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052182466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.3052182466
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.4182029318
Short name T288
Test name
Test status
Simulation time 19655918 ps
CPU time 1.06 seconds
Started Dec 27 12:59:07 PM PST 23
Finished Dec 27 12:59:19 PM PST 23
Peak memory 205544 kb
Host smart-f95206d8-5c1b-4657-9dce-32002cc569ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182029318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.4182029318
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.2679249735
Short name T605
Test name
Test status
Simulation time 15469366 ps
CPU time 0.95 seconds
Started Dec 27 12:59:05 PM PST 23
Finished Dec 27 12:59:15 PM PST 23
Peak memory 204912 kb
Host smart-37cc761b-60eb-48e7-862c-d26375fb8ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679249735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.2679249735
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.1054366817
Short name T344
Test name
Test status
Simulation time 19289828 ps
CPU time 1.07 seconds
Started Dec 27 12:58:55 PM PST 23
Finished Dec 27 12:59:03 PM PST 23
Peak memory 205420 kb
Host smart-50ea705c-51e0-4f0c-8c9c-03c9ac665046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054366817 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.1054366817
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.2784730442
Short name T70
Test name
Test status
Simulation time 162250886 ps
CPU time 1.1 seconds
Started Dec 27 12:59:17 PM PST 23
Finished Dec 27 12:59:29 PM PST 23
Peak memory 205580 kb
Host smart-6a4d6ca6-285a-4394-833e-a47cb453e1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784730442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.2784730442
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.2544575113
Short name T57
Test name
Test status
Simulation time 16689272 ps
CPU time 0.96 seconds
Started Dec 27 12:57:42 PM PST 23
Finished Dec 27 12:57:45 PM PST 23
Peak memory 205300 kb
Host smart-8aa9b5a3-5473-4b9e-a2dd-6ef9773c22d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544575113 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.2544575113
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.1613918873
Short name T710
Test name
Test status
Simulation time 41667545 ps
CPU time 0.9 seconds
Started Dec 27 12:57:42 PM PST 23
Finished Dec 27 12:57:45 PM PST 23
Peak memory 204524 kb
Host smart-3a575df5-f63b-4ce8-b842-8b1126aedafd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613918873 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.1613918873
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.3186464041
Short name T149
Test name
Test status
Simulation time 24067555 ps
CPU time 0.88 seconds
Started Dec 27 12:57:39 PM PST 23
Finished Dec 27 12:57:42 PM PST 23
Peak memory 214264 kb
Host smart-a6d3bc01-234f-4446-a3d5-bbe0af580d77
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186464041 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.3186464041
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.174749365
Short name T901
Test name
Test status
Simulation time 150165231 ps
CPU time 1.04 seconds
Started Dec 27 12:57:30 PM PST 23
Finished Dec 27 12:57:37 PM PST 23
Peak memory 214472 kb
Host smart-f55b0f5b-1fbd-4a83-aa63-1debb3987353
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174749365 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_dis
able_auto_req_mode.174749365
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.3454170687
Short name T558
Test name
Test status
Simulation time 19622974 ps
CPU time 1.23 seconds
Started Dec 27 12:57:41 PM PST 23
Finished Dec 27 12:57:44 PM PST 23
Peak memory 221696 kb
Host smart-d09ab7b8-14c1-47cd-9522-95669c560fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454170687 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.3454170687
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.1796482303
Short name T345
Test name
Test status
Simulation time 40600972 ps
CPU time 1.06 seconds
Started Dec 27 12:57:39 PM PST 23
Finished Dec 27 12:57:43 PM PST 23
Peak memory 205332 kb
Host smart-c91f7d95-6fc0-444f-8973-134646508f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796482303 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.1796482303
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.3750496708
Short name T842
Test name
Test status
Simulation time 31159781 ps
CPU time 0.85 seconds
Started Dec 27 12:57:44 PM PST 23
Finished Dec 27 12:57:47 PM PST 23
Peak memory 214284 kb
Host smart-fab48f8c-ae5b-4a1d-a058-34bacd0e6225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750496708 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.3750496708
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_smoke.1762066596
Short name T616
Test name
Test status
Simulation time 12782269 ps
CPU time 0.85 seconds
Started Dec 27 12:58:01 PM PST 23
Finished Dec 27 12:58:08 PM PST 23
Peak memory 204676 kb
Host smart-f3d6190f-5a01-4ea4-9091-097427663e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762066596 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.1762066596
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.1806636200
Short name T787
Test name
Test status
Simulation time 193104067 ps
CPU time 1.71 seconds
Started Dec 27 12:57:23 PM PST 23
Finished Dec 27 12:57:31 PM PST 23
Peak memory 206004 kb
Host smart-3ee296ec-c6be-48d9-8b6a-97196d0ccc99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806636200 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.1806636200
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.3096171589
Short name T706
Test name
Test status
Simulation time 49127398348 ps
CPU time 978.98 seconds
Started Dec 27 12:57:50 PM PST 23
Finished Dec 27 01:14:10 PM PST 23
Peak memory 214436 kb
Host smart-fc8cfdac-ab37-4d28-b97d-5faeb0408f8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096171589 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.3096171589
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.4012222662
Short name T641
Test name
Test status
Simulation time 36067988 ps
CPU time 0.94 seconds
Started Dec 27 12:58:09 PM PST 23
Finished Dec 27 12:58:19 PM PST 23
Peak memory 206004 kb
Host smart-0a9061aa-3031-46cb-a71f-7a1dc9d8400e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012222662 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.4012222662
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.3474084247
Short name T752
Test name
Test status
Simulation time 14042403 ps
CPU time 0.86 seconds
Started Dec 27 12:58:07 PM PST 23
Finished Dec 27 12:58:21 PM PST 23
Peak memory 205160 kb
Host smart-34df4e1f-a833-4271-bdc6-9c4686594739
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474084247 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.3474084247
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.624350402
Short name T235
Test name
Test status
Simulation time 17631700 ps
CPU time 0.82 seconds
Started Dec 27 12:58:20 PM PST 23
Finished Dec 27 12:58:34 PM PST 23
Peak memory 214236 kb
Host smart-d09a8392-71b9-4ea4-9727-666224fb3ca7
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624350402 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.624350402
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.2403170119
Short name T131
Test name
Test status
Simulation time 79260170 ps
CPU time 0.96 seconds
Started Dec 27 12:58:44 PM PST 23
Finished Dec 27 12:58:53 PM PST 23
Peak memory 214532 kb
Host smart-f10615f8-3462-4860-8379-1aedf3308b87
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403170119 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.2403170119
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.3546327160
Short name T58
Test name
Test status
Simulation time 29182932 ps
CPU time 1.18 seconds
Started Dec 27 12:58:19 PM PST 23
Finished Dec 27 12:58:33 PM PST 23
Peak memory 216976 kb
Host smart-3b358652-c50e-4983-bf97-7996ff47e6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546327160 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.3546327160
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.3228404472
Short name T34
Test name
Test status
Simulation time 45751045 ps
CPU time 1.07 seconds
Started Dec 27 12:58:07 PM PST 23
Finished Dec 27 12:58:14 PM PST 23
Peak memory 205400 kb
Host smart-42b14e9c-9b6e-4f6d-9dc7-14cc0944fd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228404472 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.3228404472
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.3044190131
Short name T814
Test name
Test status
Simulation time 20791289 ps
CPU time 1.01 seconds
Started Dec 27 12:58:41 PM PST 23
Finished Dec 27 12:58:50 PM PST 23
Peak memory 214276 kb
Host smart-d7eb1681-a9c4-4425-95b5-6d7619161d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044190131 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.3044190131
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.1600390398
Short name T968
Test name
Test status
Simulation time 28214609 ps
CPU time 0.94 seconds
Started Dec 27 12:58:05 PM PST 23
Finished Dec 27 12:58:13 PM PST 23
Peak memory 204620 kb
Host smart-258e4e18-e3b9-4591-b303-9d2243b9ebce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600390398 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.1600390398
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.1842973955
Short name T688
Test name
Test status
Simulation time 135038297 ps
CPU time 1.23 seconds
Started Dec 27 12:58:09 PM PST 23
Finished Dec 27 12:58:19 PM PST 23
Peak memory 205088 kb
Host smart-a69a2c50-8edd-4cc7-a884-c079dd763499
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842973955 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.1842973955
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.4078849322
Short name T735
Test name
Test status
Simulation time 103252266784 ps
CPU time 1703.04 seconds
Started Dec 27 12:58:14 PM PST 23
Finished Dec 27 01:26:48 PM PST 23
Peak memory 219228 kb
Host smart-5ab4a981-667a-4efa-9373-e962dc2f18d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078849322 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.4078849322
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.1330341943
Short name T598
Test name
Test status
Simulation time 22038325 ps
CPU time 1.37 seconds
Started Dec 27 12:59:08 PM PST 23
Finished Dec 27 12:59:20 PM PST 23
Peak memory 205536 kb
Host smart-fae3718d-5913-4921-b49c-5af693f67b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330341943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.1330341943
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.3103281417
Short name T619
Test name
Test status
Simulation time 422342110 ps
CPU time 1.6 seconds
Started Dec 27 12:59:06 PM PST 23
Finished Dec 27 12:59:17 PM PST 23
Peak memory 214152 kb
Host smart-2dd75e1f-b275-4e57-b973-c20d676d4fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103281417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.3103281417
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.2504547011
Short name T281
Test name
Test status
Simulation time 16887255 ps
CPU time 0.96 seconds
Started Dec 27 12:59:08 PM PST 23
Finished Dec 27 12:59:20 PM PST 23
Peak memory 205892 kb
Host smart-bad440e4-bfe6-42ef-8ade-273d6547720f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504547011 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.2504547011
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.3846849390
Short name T903
Test name
Test status
Simulation time 23853607 ps
CPU time 1.28 seconds
Started Dec 27 12:59:13 PM PST 23
Finished Dec 27 12:59:25 PM PST 23
Peak memory 214092 kb
Host smart-d13df401-6e26-468e-817b-4d55c038b977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846849390 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.3846849390
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.603525428
Short name T574
Test name
Test status
Simulation time 16910318 ps
CPU time 0.99 seconds
Started Dec 27 12:59:00 PM PST 23
Finished Dec 27 12:59:09 PM PST 23
Peak memory 204928 kb
Host smart-78a7d95f-c901-4670-a10a-81be13339b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603525428 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.603525428
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.3999506354
Short name T97
Test name
Test status
Simulation time 13441639 ps
CPU time 1 seconds
Started Dec 27 12:59:04 PM PST 23
Finished Dec 27 12:59:13 PM PST 23
Peak memory 205632 kb
Host smart-8873473a-bd7e-4e8a-90c3-08f5ef71f013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999506354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3999506354
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.464141241
Short name T623
Test name
Test status
Simulation time 30359544 ps
CPU time 0.99 seconds
Started Dec 27 12:59:00 PM PST 23
Finished Dec 27 12:59:09 PM PST 23
Peak memory 205344 kb
Host smart-a4bc13a4-9c8d-4201-886c-6a1995647128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464141241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.464141241
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.573211096
Short name T515
Test name
Test status
Simulation time 17006761 ps
CPU time 1.05 seconds
Started Dec 27 12:59:04 PM PST 23
Finished Dec 27 12:59:13 PM PST 23
Peak memory 205976 kb
Host smart-841d4d12-19b3-4c17-bf1c-82e5de05103a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573211096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.573211096
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.2348775388
Short name T643
Test name
Test status
Simulation time 148409595 ps
CPU time 0.99 seconds
Started Dec 27 12:59:24 PM PST 23
Finished Dec 27 12:59:35 PM PST 23
Peak memory 205556 kb
Host smart-17c97681-36e4-4864-90c6-368f80ad6252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348775388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.2348775388
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.3812786533
Short name T19
Test name
Test status
Simulation time 162214132 ps
CPU time 0.98 seconds
Started Dec 27 12:58:06 PM PST 23
Finished Dec 27 12:58:13 PM PST 23
Peak memory 205144 kb
Host smart-0a1e34e3-e2d6-4b3d-b777-6a4eb1817686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812786533 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3812786533
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.108456120
Short name T463
Test name
Test status
Simulation time 29910203 ps
CPU time 0.95 seconds
Started Dec 27 12:58:15 PM PST 23
Finished Dec 27 12:58:26 PM PST 23
Peak memory 205172 kb
Host smart-b849df4d-fbe4-4e1b-95ee-b2df2a89ae3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108456120 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.108456120
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.3862065893
Short name T111
Test name
Test status
Simulation time 37978058 ps
CPU time 0.84 seconds
Started Dec 27 12:57:51 PM PST 23
Finished Dec 27 12:57:53 PM PST 23
Peak memory 214248 kb
Host smart-6037db11-df8e-4e6a-88ce-864648c4acfd
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862065893 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.3862065893
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_err.2354758001
Short name T241
Test name
Test status
Simulation time 20462488 ps
CPU time 1.11 seconds
Started Dec 27 12:58:31 PM PST 23
Finished Dec 27 12:58:41 PM PST 23
Peak memory 214504 kb
Host smart-e96f8dbd-854b-4084-a433-4f1076549369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354758001 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.2354758001
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.472018720
Short name T273
Test name
Test status
Simulation time 33327298 ps
CPU time 0.82 seconds
Started Dec 27 12:58:11 PM PST 23
Finished Dec 27 12:58:22 PM PST 23
Peak memory 204964 kb
Host smart-e37ebeb3-3981-42d9-9ad4-471eb9dc3568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472018720 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.472018720
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.2712600828
Short name T738
Test name
Test status
Simulation time 39136858 ps
CPU time 0.91 seconds
Started Dec 27 12:58:04 PM PST 23
Finished Dec 27 12:58:13 PM PST 23
Peak memory 214052 kb
Host smart-02571b7f-1b87-4863-a98c-2f464ddcfc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712600828 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.2712600828
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.1211477881
Short name T453
Test name
Test status
Simulation time 17545118 ps
CPU time 0.88 seconds
Started Dec 27 12:58:06 PM PST 23
Finished Dec 27 12:58:13 PM PST 23
Peak memory 204564 kb
Host smart-cb825f7b-428c-4280-b644-2bb81b90e789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211477881 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.1211477881
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.3668271365
Short name T717
Test name
Test status
Simulation time 323279535 ps
CPU time 3.78 seconds
Started Dec 27 12:57:57 PM PST 23
Finished Dec 27 12:58:02 PM PST 23
Peak memory 205872 kb
Host smart-3d8b2aac-c62b-4121-a6a2-ad1d12beb2ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668271365 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.3668271365
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.137040470
Short name T745
Test name
Test status
Simulation time 43258523338 ps
CPU time 546.14 seconds
Started Dec 27 12:58:22 PM PST 23
Finished Dec 27 01:07:42 PM PST 23
Peak memory 214748 kb
Host smart-50e5de95-7587-42d4-a9a5-d0afc48f3303
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137040470 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.137040470
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.724275058
Short name T20
Test name
Test status
Simulation time 28255734 ps
CPU time 1.08 seconds
Started Dec 27 12:59:10 PM PST 23
Finished Dec 27 12:59:22 PM PST 23
Peak memory 205260 kb
Host smart-4f0021c9-605c-4dbe-9dea-6aee9abb3ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724275058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.724275058
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.3494903683
Short name T876
Test name
Test status
Simulation time 16849378 ps
CPU time 0.95 seconds
Started Dec 27 12:59:16 PM PST 23
Finished Dec 27 12:59:29 PM PST 23
Peak memory 204972 kb
Host smart-45933367-ca89-4a12-9a26-40533194e466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494903683 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.3494903683
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.567973795
Short name T483
Test name
Test status
Simulation time 185523978 ps
CPU time 2.54 seconds
Started Dec 27 12:58:54 PM PST 23
Finished Dec 27 12:59:03 PM PST 23
Peak memory 214140 kb
Host smart-b186e748-1546-46df-a6e2-097767be4e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567973795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.567973795
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.2344975863
Short name T618
Test name
Test status
Simulation time 120074085 ps
CPU time 1.33 seconds
Started Dec 27 12:59:06 PM PST 23
Finished Dec 27 12:59:17 PM PST 23
Peak memory 213992 kb
Host smart-691f407b-9682-4df1-97c2-930a4b02bd0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344975863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.2344975863
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.2990907183
Short name T822
Test name
Test status
Simulation time 85984053 ps
CPU time 2.08 seconds
Started Dec 27 12:59:06 PM PST 23
Finished Dec 27 12:59:18 PM PST 23
Peak memory 214208 kb
Host smart-6110177b-15c9-47c9-b8c7-19415dffaa7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990907183 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.2990907183
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.3063399929
Short name T13
Test name
Test status
Simulation time 54800232 ps
CPU time 0.98 seconds
Started Dec 27 12:59:02 PM PST 23
Finished Dec 27 12:59:11 PM PST 23
Peak memory 214164 kb
Host smart-4aadf076-6cd3-4e85-95ef-84837efbaeea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063399929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.3063399929
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.1021454334
Short name T340
Test name
Test status
Simulation time 82311287 ps
CPU time 1.38 seconds
Started Dec 27 12:59:07 PM PST 23
Finished Dec 27 12:59:18 PM PST 23
Peak memory 205544 kb
Host smart-0fa7c9be-3865-4bb5-bc94-050ae235fe27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021454334 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.1021454334
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.2354735960
Short name T528
Test name
Test status
Simulation time 52255126 ps
CPU time 0.97 seconds
Started Dec 27 12:59:04 PM PST 23
Finished Dec 27 12:59:13 PM PST 23
Peak memory 205124 kb
Host smart-5a23a08a-ee82-4362-a518-e528ef7737f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354735960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.2354735960
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.1074012225
Short name T324
Test name
Test status
Simulation time 15798771 ps
CPU time 0.93 seconds
Started Dec 27 12:59:05 PM PST 23
Finished Dec 27 12:59:15 PM PST 23
Peak memory 205392 kb
Host smart-a9255fb7-dd7c-4b02-9b73-142292772f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074012225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.1074012225
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert_test.3706468879
Short name T461
Test name
Test status
Simulation time 24785539 ps
CPU time 0.9 seconds
Started Dec 27 12:58:08 PM PST 23
Finished Dec 27 12:58:16 PM PST 23
Peak memory 204584 kb
Host smart-d7114ea6-1cd9-4bdc-b67b-24709735e6d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706468879 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.3706468879
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.600083746
Short name T239
Test name
Test status
Simulation time 38730745 ps
CPU time 0.86 seconds
Started Dec 27 12:58:19 PM PST 23
Finished Dec 27 12:58:33 PM PST 23
Peak memory 214356 kb
Host smart-baa6bd82-4beb-4b19-ab16-dd7ee0e803af
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600083746 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.600083746
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.4028236390
Short name T962
Test name
Test status
Simulation time 21911316 ps
CPU time 0.93 seconds
Started Dec 27 12:58:12 PM PST 23
Finished Dec 27 12:58:22 PM PST 23
Peak memory 214504 kb
Host smart-2f292b1a-7216-4f2d-b38d-2c317ae0b0c5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028236390 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.4028236390
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.670995722
Short name T555
Test name
Test status
Simulation time 22112450 ps
CPU time 0.98 seconds
Started Dec 27 12:58:12 PM PST 23
Finished Dec 27 12:58:23 PM PST 23
Peak memory 221076 kb
Host smart-e79014b2-415d-4faa-9351-3198a7e50bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670995722 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.670995722
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.2565762106
Short name T810
Test name
Test status
Simulation time 207469871 ps
CPU time 2.98 seconds
Started Dec 27 12:58:01 PM PST 23
Finished Dec 27 12:58:10 PM PST 23
Peak memory 214120 kb
Host smart-d9cafba2-fb12-48a8-b7e2-2f8bc9c2e7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565762106 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.2565762106
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.3891858529
Short name T611
Test name
Test status
Simulation time 117389362 ps
CPU time 0.96 seconds
Started Dec 27 12:58:17 PM PST 23
Finished Dec 27 12:58:27 PM PST 23
Peak memory 221556 kb
Host smart-f256f270-d598-4c38-a9a9-6380a401e49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891858529 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.3891858529
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.1943464455
Short name T731
Test name
Test status
Simulation time 18455994 ps
CPU time 0.88 seconds
Started Dec 27 12:58:09 PM PST 23
Finished Dec 27 12:58:19 PM PST 23
Peak memory 204672 kb
Host smart-e5e694d9-16e0-44c0-a8e9-c2fe45ee9683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943464455 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.1943464455
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.2971933523
Short name T971
Test name
Test status
Simulation time 389254988 ps
CPU time 2.39 seconds
Started Dec 27 12:58:30 PM PST 23
Finished Dec 27 12:58:42 PM PST 23
Peak memory 205996 kb
Host smart-9b66c01e-ee18-4a17-9399-1aff1d419445
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971933523 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.2971933523
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.1836143605
Short name T767
Test name
Test status
Simulation time 257640739829 ps
CPU time 1471.58 seconds
Started Dec 27 12:58:06 PM PST 23
Finished Dec 27 01:22:44 PM PST 23
Peak memory 219952 kb
Host smart-0c1983d5-3fa5-44a1-893e-46196531d823
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836143605 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.1836143605
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.1878916494
Short name T897
Test name
Test status
Simulation time 71615942 ps
CPU time 0.93 seconds
Started Dec 27 12:59:00 PM PST 23
Finished Dec 27 12:59:08 PM PST 23
Peak memory 205200 kb
Host smart-74435115-b1b4-45bd-9cfd-ec63118dce9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878916494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.1878916494
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.300667945
Short name T912
Test name
Test status
Simulation time 17413757 ps
CPU time 1.14 seconds
Started Dec 27 12:59:15 PM PST 23
Finished Dec 27 12:59:28 PM PST 23
Peak memory 205620 kb
Host smart-15d46884-b78d-4bc1-b25b-72d99c2155bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300667945 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.300667945
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.301684978
Short name T713
Test name
Test status
Simulation time 22533642 ps
CPU time 0.96 seconds
Started Dec 27 12:58:53 PM PST 23
Finished Dec 27 12:59:01 PM PST 23
Peak memory 205584 kb
Host smart-39460b6a-9067-4bf3-9557-8880dc539e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301684978 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.301684978
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.2717915376
Short name T770
Test name
Test status
Simulation time 199843424 ps
CPU time 2.64 seconds
Started Dec 27 12:59:05 PM PST 23
Finished Dec 27 12:59:17 PM PST 23
Peak memory 214160 kb
Host smart-5bfe8722-fd1b-4264-8464-2bef183ac528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717915376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.2717915376
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.3933703639
Short name T579
Test name
Test status
Simulation time 140657220 ps
CPU time 1.3 seconds
Started Dec 27 12:58:59 PM PST 23
Finished Dec 27 12:59:08 PM PST 23
Peak memory 214172 kb
Host smart-691a338e-6e0a-4ba6-8dcb-678e5a75b97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933703639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.3933703639
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.733128726
Short name T862
Test name
Test status
Simulation time 17332857 ps
CPU time 1 seconds
Started Dec 27 12:59:20 PM PST 23
Finished Dec 27 12:59:32 PM PST 23
Peak memory 205492 kb
Host smart-1207717b-b6cc-448c-83a5-3510453246fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733128726 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.733128726
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.1865189703
Short name T932
Test name
Test status
Simulation time 38617774 ps
CPU time 1.14 seconds
Started Dec 27 12:59:06 PM PST 23
Finished Dec 27 12:59:16 PM PST 23
Peak memory 214152 kb
Host smart-34acdaa1-cac4-4f2b-8039-c00ffc61bee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865189703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.1865189703
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.3609703768
Short name T315
Test name
Test status
Simulation time 15776937 ps
CPU time 1.01 seconds
Started Dec 27 12:59:02 PM PST 23
Finished Dec 27 12:59:12 PM PST 23
Peak memory 205504 kb
Host smart-b24b60d7-333e-4d71-9e08-a9bc9183111c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609703768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.3609703768
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.3567124891
Short name T593
Test name
Test status
Simulation time 31981293 ps
CPU time 0.98 seconds
Started Dec 27 12:59:05 PM PST 23
Finished Dec 27 12:59:15 PM PST 23
Peak memory 204864 kb
Host smart-75a76261-4237-40dc-99b7-1ac2ce4a895e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567124891 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.3567124891
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.1727059476
Short name T262
Test name
Test status
Simulation time 18314567 ps
CPU time 1.02 seconds
Started Dec 27 12:58:10 PM PST 23
Finished Dec 27 12:58:21 PM PST 23
Peak memory 205904 kb
Host smart-b70e7b3e-f433-4ef3-8ab8-70ca2ef6f47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727059476 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.1727059476
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.783105108
Short name T963
Test name
Test status
Simulation time 14630529 ps
CPU time 0.87 seconds
Started Dec 27 12:58:12 PM PST 23
Finished Dec 27 12:58:23 PM PST 23
Peak memory 204604 kb
Host smart-7e079d4e-fb36-40ef-afd1-818ee59dbcea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783105108 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.783105108
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.1882750914
Short name T942
Test name
Test status
Simulation time 49851062 ps
CPU time 0.9 seconds
Started Dec 27 12:58:15 PM PST 23
Finished Dec 27 12:58:26 PM PST 23
Peak memory 214504 kb
Host smart-7938a384-58f8-49b9-a233-8f722b410e27
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882750914 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.1882750914
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.1671877802
Short name T781
Test name
Test status
Simulation time 30892200 ps
CPU time 1.32 seconds
Started Dec 27 12:58:05 PM PST 23
Finished Dec 27 12:58:13 PM PST 23
Peak memory 227272 kb
Host smart-5fadd760-849c-47d7-8413-0db78d6f1508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671877802 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.1671877802
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.79891391
Short name T780
Test name
Test status
Simulation time 64926806 ps
CPU time 0.9 seconds
Started Dec 27 12:58:14 PM PST 23
Finished Dec 27 12:58:24 PM PST 23
Peak memory 204688 kb
Host smart-03355af3-6886-4d5f-9f0f-f228ddb9b91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79891391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.79891391
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.1794847719
Short name T105
Test name
Test status
Simulation time 23986345 ps
CPU time 0.92 seconds
Started Dec 27 12:58:40 PM PST 23
Finished Dec 27 12:58:50 PM PST 23
Peak memory 214428 kb
Host smart-4f1d2bb4-e4e2-428b-ba95-cd1107fdfe52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794847719 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.1794847719
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.1907057003
Short name T771
Test name
Test status
Simulation time 14701407 ps
CPU time 0.91 seconds
Started Dec 27 12:58:11 PM PST 23
Finished Dec 27 12:58:22 PM PST 23
Peak memory 204560 kb
Host smart-aadac920-62fb-4f60-a977-0c58dcfedb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907057003 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.1907057003
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.2537332362
Short name T778
Test name
Test status
Simulation time 75407023 ps
CPU time 1.94 seconds
Started Dec 27 12:58:10 PM PST 23
Finished Dec 27 12:58:21 PM PST 23
Peak memory 205388 kb
Host smart-07e4309c-92d6-4d33-b1a5-5d2dae90f956
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537332362 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.2537332362
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.4161897723
Short name T790
Test name
Test status
Simulation time 73781473301 ps
CPU time 829.14 seconds
Started Dec 27 12:58:42 PM PST 23
Finished Dec 27 01:12:39 PM PST 23
Peak memory 215368 kb
Host smart-0bd4589b-bffa-41e4-a347-3eaebd6c14e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161897723 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.4161897723
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.2271717488
Short name T725
Test name
Test status
Simulation time 23277240 ps
CPU time 1.15 seconds
Started Dec 27 12:59:20 PM PST 23
Finished Dec 27 12:59:32 PM PST 23
Peak memory 214172 kb
Host smart-1d19183d-a864-47e4-a589-184d4d2cd20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271717488 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.2271717488
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.2710931804
Short name T662
Test name
Test status
Simulation time 25658745 ps
CPU time 0.97 seconds
Started Dec 27 12:59:03 PM PST 23
Finished Dec 27 12:59:12 PM PST 23
Peak memory 205292 kb
Host smart-c8149252-b10e-402b-98b7-9679b395a9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710931804 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.2710931804
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.1646554140
Short name T867
Test name
Test status
Simulation time 418580916 ps
CPU time 4.04 seconds
Started Dec 27 12:59:06 PM PST 23
Finished Dec 27 12:59:19 PM PST 23
Peak memory 214080 kb
Host smart-8fd03fd8-f9a8-47e3-85c5-6a63d25bfdb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646554140 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.1646554140
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.2933895666
Short name T481
Test name
Test status
Simulation time 18833896 ps
CPU time 1.14 seconds
Started Dec 27 12:58:55 PM PST 23
Finished Dec 27 12:59:02 PM PST 23
Peak memory 205252 kb
Host smart-b8bd71aa-9a08-44ca-b310-4ee946c37d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933895666 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.2933895666
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.1198940619
Short name T915
Test name
Test status
Simulation time 112336746 ps
CPU time 1.21 seconds
Started Dec 27 12:59:05 PM PST 23
Finished Dec 27 12:59:14 PM PST 23
Peak memory 214176 kb
Host smart-605b8549-a81a-46ed-8f31-88e5a1a471a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198940619 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.1198940619
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.1272644569
Short name T38
Test name
Test status
Simulation time 20809638 ps
CPU time 1.13 seconds
Started Dec 27 12:59:14 PM PST 23
Finished Dec 27 12:59:26 PM PST 23
Peak memory 205532 kb
Host smart-a3255136-da0b-4516-a2c2-371e0fa6c392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272644569 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.1272644569
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.1380358747
Short name T320
Test name
Test status
Simulation time 43299370 ps
CPU time 1 seconds
Started Dec 27 12:59:32 PM PST 23
Finished Dec 27 12:59:39 PM PST 23
Peak memory 205532 kb
Host smart-be7ef015-8f5d-4a66-8610-734541673c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380358747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.1380358747
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.813858252
Short name T870
Test name
Test status
Simulation time 18855816 ps
CPU time 1.07 seconds
Started Dec 27 12:58:51 PM PST 23
Finished Dec 27 12:58:59 PM PST 23
Peak memory 214168 kb
Host smart-3d6b3dd9-8ade-4493-887c-bea2f88acc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813858252 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.813858252
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.2975290510
Short name T526
Test name
Test status
Simulation time 27611099 ps
CPU time 0.99 seconds
Started Dec 27 12:58:58 PM PST 23
Finished Dec 27 12:59:06 PM PST 23
Peak memory 205232 kb
Host smart-0ec54b04-8b20-44c6-a4d2-d8f8d847e262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975290510 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.2975290510
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.4171330635
Short name T537
Test name
Test status
Simulation time 33758112 ps
CPU time 1.2 seconds
Started Dec 27 12:59:01 PM PST 23
Finished Dec 27 12:59:10 PM PST 23
Peak memory 205308 kb
Host smart-cc4c5999-2c26-45a3-a73c-525f4d1a43d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171330635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.4171330635
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.380184280
Short name T950
Test name
Test status
Simulation time 48874491 ps
CPU time 0.9 seconds
Started Dec 27 12:58:10 PM PST 23
Finished Dec 27 12:58:21 PM PST 23
Peak memory 205208 kb
Host smart-31d24cb5-88d7-4009-8813-efb0003a8a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380184280 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.380184280
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.2383791833
Short name T645
Test name
Test status
Simulation time 13366776 ps
CPU time 0.86 seconds
Started Dec 27 12:58:20 PM PST 23
Finished Dec 27 12:58:34 PM PST 23
Peak memory 204436 kb
Host smart-2e1775b9-1bf6-44af-83a0-b2e11b7ddc05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383791833 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.2383791833
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.388446972
Short name T112
Test name
Test status
Simulation time 33881240 ps
CPU time 0.8 seconds
Started Dec 27 12:58:21 PM PST 23
Finished Dec 27 12:58:35 PM PST 23
Peak memory 214352 kb
Host smart-a2e5ca0a-c67c-4d8c-a225-53da5dd5bfb6
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388446972 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.388446972
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.1520485209
Short name T139
Test name
Test status
Simulation time 114146353 ps
CPU time 0.96 seconds
Started Dec 27 12:58:30 PM PST 23
Finished Dec 27 12:58:40 PM PST 23
Peak memory 214504 kb
Host smart-a2322584-b682-4b2a-b3b2-82688cdc49bd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520485209 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.1520485209
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.3650362129
Short name T580
Test name
Test status
Simulation time 32282844 ps
CPU time 1.26 seconds
Started Dec 27 12:58:17 PM PST 23
Finished Dec 27 12:58:28 PM PST 23
Peak memory 214808 kb
Host smart-777926c6-d333-4b09-9b52-6b98f1ec2efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650362129 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.3650362129
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.1094396519
Short name T957
Test name
Test status
Simulation time 18872484 ps
CPU time 1.05 seconds
Started Dec 27 12:58:10 PM PST 23
Finished Dec 27 12:58:21 PM PST 23
Peak memory 205296 kb
Host smart-57c554da-1814-4a0a-bd76-44b3073b941d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094396519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1094396519
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.2615927910
Short name T83
Test name
Test status
Simulation time 21477147 ps
CPU time 0.89 seconds
Started Dec 27 12:58:10 PM PST 23
Finished Dec 27 12:58:20 PM PST 23
Peak memory 214428 kb
Host smart-814f5d1c-533b-4208-9bc5-e58b24b5e5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615927910 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.2615927910
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.808501661
Short name T573
Test name
Test status
Simulation time 49774905 ps
CPU time 0.87 seconds
Started Dec 27 12:58:21 PM PST 23
Finished Dec 27 12:58:35 PM PST 23
Peak memory 204680 kb
Host smart-9d4c51ed-5a5a-4f59-91a6-033cab8adf86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808501661 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.808501661
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.663459155
Short name T949
Test name
Test status
Simulation time 1448580981 ps
CPU time 4.42 seconds
Started Dec 27 12:58:13 PM PST 23
Finished Dec 27 12:58:27 PM PST 23
Peak memory 205832 kb
Host smart-130bd6ac-2ca5-467f-9e98-a53116471482
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663459155 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.663459155
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.2967504173
Short name T590
Test name
Test status
Simulation time 51282460545 ps
CPU time 307.25 seconds
Started Dec 27 12:58:36 PM PST 23
Finished Dec 27 01:03:53 PM PST 23
Peak memory 214920 kb
Host smart-f1c0b7c6-554e-47fa-be5c-f543ae29c106
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967504173 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.2967504173
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.2055618950
Short name T689
Test name
Test status
Simulation time 49864810 ps
CPU time 1.98 seconds
Started Dec 27 12:59:06 PM PST 23
Finished Dec 27 12:59:17 PM PST 23
Peak memory 214064 kb
Host smart-2deea869-0e61-4419-849f-353a1425f664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055618950 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.2055618950
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.2406763425
Short name T72
Test name
Test status
Simulation time 41168155 ps
CPU time 1.03 seconds
Started Dec 27 12:59:08 PM PST 23
Finished Dec 27 12:59:20 PM PST 23
Peak memory 205228 kb
Host smart-9604c73c-d627-4929-bee2-31dbb049e4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406763425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.2406763425
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.1429525297
Short name T78
Test name
Test status
Simulation time 16108772 ps
CPU time 1.07 seconds
Started Dec 27 12:59:04 PM PST 23
Finished Dec 27 12:59:14 PM PST 23
Peak memory 205428 kb
Host smart-2d0a41ef-ca87-44ef-8bbf-340971f04ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429525297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1429525297
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.3522010696
Short name T285
Test name
Test status
Simulation time 101155318 ps
CPU time 0.94 seconds
Started Dec 27 12:58:56 PM PST 23
Finished Dec 27 12:59:04 PM PST 23
Peak memory 205348 kb
Host smart-ebb8946f-eebc-4c7b-88d5-e3a8c2d88a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522010696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.3522010696
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.288930966
Short name T652
Test name
Test status
Simulation time 32952093 ps
CPU time 1.05 seconds
Started Dec 27 12:59:13 PM PST 23
Finished Dec 27 12:59:24 PM PST 23
Peak memory 205900 kb
Host smart-90f2bb1c-d91d-425e-a0dc-8305a7b51884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288930966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.288930966
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.677933712
Short name T806
Test name
Test status
Simulation time 1215050848 ps
CPU time 10.13 seconds
Started Dec 27 12:58:53 PM PST 23
Finished Dec 27 12:59:10 PM PST 23
Peak memory 214164 kb
Host smart-8ed53c39-0e47-474b-b102-dd5f7e24c897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677933712 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.677933712
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.3447184349
Short name T488
Test name
Test status
Simulation time 25248811 ps
CPU time 0.92 seconds
Started Dec 27 12:59:01 PM PST 23
Finished Dec 27 12:59:10 PM PST 23
Peak memory 205080 kb
Host smart-418db295-52a4-472f-8332-5467236cbf55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447184349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.3447184349
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.1042728391
Short name T927
Test name
Test status
Simulation time 34406000 ps
CPU time 1.55 seconds
Started Dec 27 12:58:58 PM PST 23
Finished Dec 27 12:59:06 PM PST 23
Peak memory 214156 kb
Host smart-8d952e29-fdef-40e4-a147-bf60410ce89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042728391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.1042728391
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.1133499090
Short name T545
Test name
Test status
Simulation time 56774816 ps
CPU time 0.94 seconds
Started Dec 27 12:59:03 PM PST 23
Finished Dec 27 12:59:12 PM PST 23
Peak memory 205616 kb
Host smart-7c3b0b52-b0d0-444f-992c-3db1339cdff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133499090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.1133499090
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.1479190201
Short name T338
Test name
Test status
Simulation time 15422934 ps
CPU time 1.06 seconds
Started Dec 27 12:59:09 PM PST 23
Finished Dec 27 12:59:21 PM PST 23
Peak memory 205288 kb
Host smart-a861e250-e947-4154-a2c5-9d351d39beaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479190201 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.1479190201
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.63690172
Short name T261
Test name
Test status
Simulation time 53638522 ps
CPU time 0.99 seconds
Started Dec 27 12:58:47 PM PST 23
Finished Dec 27 12:58:57 PM PST 23
Peak memory 205952 kb
Host smart-e88bddbc-1f69-48a4-a37e-fa978efb5e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63690172 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.63690172
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.2961752761
Short name T977
Test name
Test status
Simulation time 37526595 ps
CPU time 0.8 seconds
Started Dec 27 12:58:21 PM PST 23
Finished Dec 27 12:58:35 PM PST 23
Peak memory 204284 kb
Host smart-cb9de303-a744-4ddd-832c-6bb99d956eef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961752761 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.2961752761
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.2802373202
Short name T679
Test name
Test status
Simulation time 24375357 ps
CPU time 0.98 seconds
Started Dec 27 12:58:32 PM PST 23
Finished Dec 27 12:58:44 PM PST 23
Peak memory 214584 kb
Host smart-66dc7e23-cdcc-4c1a-a8ab-c8cb30e8ec17
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802373202 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.2802373202
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.3179762217
Short name T43
Test name
Test status
Simulation time 29541381 ps
CPU time 1.02 seconds
Started Dec 27 12:58:14 PM PST 23
Finished Dec 27 12:58:33 PM PST 23
Peak memory 228776 kb
Host smart-be562fc9-36f6-4916-8e82-a341ca49cbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179762217 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.3179762217
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.365682562
Short name T786
Test name
Test status
Simulation time 172342836 ps
CPU time 1.98 seconds
Started Dec 27 12:58:14 PM PST 23
Finished Dec 27 12:58:26 PM PST 23
Peak memory 214176 kb
Host smart-33323919-ac56-4a53-b466-a003fb3bd667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365682562 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.365682562
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.1646142643
Short name T87
Test name
Test status
Simulation time 53024676 ps
CPU time 0.87 seconds
Started Dec 27 12:58:58 PM PST 23
Finished Dec 27 12:59:06 PM PST 23
Peak memory 214312 kb
Host smart-6a2ff37b-d1b0-4561-8f67-ba10dd7710ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646142643 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.1646142643
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.1060994084
Short name T614
Test name
Test status
Simulation time 14029047 ps
CPU time 0.93 seconds
Started Dec 27 12:58:19 PM PST 23
Finished Dec 27 12:58:33 PM PST 23
Peak memory 204728 kb
Host smart-58b108b4-ff7e-4f3e-b78c-13d5dbe1f8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060994084 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.1060994084
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.590711771
Short name T845
Test name
Test status
Simulation time 1023381889 ps
CPU time 3.51 seconds
Started Dec 27 12:58:10 PM PST 23
Finished Dec 27 12:58:24 PM PST 23
Peak memory 205960 kb
Host smart-b14dbde3-ef50-43d7-b5a9-9b3164979dbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590711771 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.590711771
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.3896617764
Short name T754
Test name
Test status
Simulation time 55904123263 ps
CPU time 1302.25 seconds
Started Dec 27 12:58:11 PM PST 23
Finished Dec 27 01:20:03 PM PST 23
Peak memory 216568 kb
Host smart-1cee9a92-8604-4165-be64-6f1ca6b093aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896617764 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.3896617764
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.2854529261
Short name T630
Test name
Test status
Simulation time 69700106 ps
CPU time 1.03 seconds
Started Dec 27 12:59:07 PM PST 23
Finished Dec 27 12:59:18 PM PST 23
Peak memory 214144 kb
Host smart-5fe421f9-ab08-424a-b09d-27084a75e226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854529261 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.2854529261
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.2854583861
Short name T826
Test name
Test status
Simulation time 28372910 ps
CPU time 1.07 seconds
Started Dec 27 12:59:11 PM PST 23
Finished Dec 27 12:59:23 PM PST 23
Peak memory 205616 kb
Host smart-68dd72ce-eb13-4178-a737-e1189c166b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854583861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.2854583861
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.3098392283
Short name T863
Test name
Test status
Simulation time 33847346 ps
CPU time 0.96 seconds
Started Dec 27 12:59:05 PM PST 23
Finished Dec 27 12:59:15 PM PST 23
Peak memory 205176 kb
Host smart-34b97ada-b026-4c02-b3a6-42bd72048a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098392283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.3098392283
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.2022070104
Short name T525
Test name
Test status
Simulation time 234024885 ps
CPU time 2.76 seconds
Started Dec 27 12:58:54 PM PST 23
Finished Dec 27 12:59:10 PM PST 23
Peak memory 214120 kb
Host smart-93810d13-ee98-455c-9232-d9e3dfc3b76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022070104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.2022070104
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.3099266931
Short name T325
Test name
Test status
Simulation time 13864531 ps
CPU time 0.97 seconds
Started Dec 27 12:59:08 PM PST 23
Finished Dec 27 12:59:21 PM PST 23
Peak memory 205568 kb
Host smart-7469abaf-c7ac-4455-82b4-60e3c8f8d8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099266931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.3099266931
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.1797717599
Short name T921
Test name
Test status
Simulation time 190748340 ps
CPU time 0.9 seconds
Started Dec 27 12:59:09 PM PST 23
Finished Dec 27 12:59:21 PM PST 23
Peak memory 204872 kb
Host smart-39af6cd3-6edb-45ef-a33b-605cb2a94623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797717599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.1797717599
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.2148706186
Short name T518
Test name
Test status
Simulation time 46316570 ps
CPU time 1.94 seconds
Started Dec 27 12:59:14 PM PST 23
Finished Dec 27 12:59:27 PM PST 23
Peak memory 214084 kb
Host smart-99ed06e2-a8de-4dff-a4e4-2cd0fa12600d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148706186 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.2148706186
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.3001864708
Short name T782
Test name
Test status
Simulation time 17088294 ps
CPU time 1.06 seconds
Started Dec 27 12:58:59 PM PST 23
Finished Dec 27 12:59:07 PM PST 23
Peak memory 205584 kb
Host smart-18f0e67b-695b-4564-965f-35bc229f602b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001864708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.3001864708
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.781791869
Short name T726
Test name
Test status
Simulation time 62738446 ps
CPU time 1.01 seconds
Started Dec 27 12:59:00 PM PST 23
Finished Dec 27 12:59:08 PM PST 23
Peak memory 205220 kb
Host smart-8b96393c-e60d-4ec0-a5f3-5b4ec584f285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781791869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.781791869
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.1581717805
Short name T617
Test name
Test status
Simulation time 54573369 ps
CPU time 0.92 seconds
Started Dec 27 12:58:37 PM PST 23
Finished Dec 27 12:58:48 PM PST 23
Peak memory 205224 kb
Host smart-88d38da0-b0eb-4fb6-9170-ebac53e0e201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581717805 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.1581717805
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.1474344281
Short name T973
Test name
Test status
Simulation time 22336762 ps
CPU time 0.79 seconds
Started Dec 27 12:58:42 PM PST 23
Finished Dec 27 12:58:51 PM PST 23
Peak memory 204248 kb
Host smart-1fb7fb4e-6744-449d-bcff-3d2f367722cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474344281 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.1474344281
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.947416923
Short name T245
Test name
Test status
Simulation time 43404053 ps
CPU time 0.9 seconds
Started Dec 27 12:58:12 PM PST 23
Finished Dec 27 12:58:22 PM PST 23
Peak memory 214280 kb
Host smart-b1201637-cc0d-404d-97fd-4f3b3d72db7e
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947416923 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.947416923
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_err.1811736231
Short name T107
Test name
Test status
Simulation time 47470421 ps
CPU time 0.97 seconds
Started Dec 27 12:58:13 PM PST 23
Finished Dec 27 12:58:23 PM PST 23
Peak memory 214856 kb
Host smart-d839d7e5-46af-46ff-81d6-970962e8318b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811736231 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.1811736231
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.3826316719
Short name T824
Test name
Test status
Simulation time 56983226 ps
CPU time 2.27 seconds
Started Dec 27 12:58:26 PM PST 23
Finished Dec 27 12:58:40 PM PST 23
Peak memory 214088 kb
Host smart-53cae8dc-7ce1-43d8-99d4-4deb762c3974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826316719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.3826316719
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.2587559726
Short name T762
Test name
Test status
Simulation time 36292767 ps
CPU time 0.82 seconds
Started Dec 27 12:58:13 PM PST 23
Finished Dec 27 12:58:24 PM PST 23
Peak memory 214260 kb
Host smart-e10f5b49-5c25-45a5-bce4-644b69dae1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587559726 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.2587559726
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.2922860857
Short name T783
Test name
Test status
Simulation time 47724290 ps
CPU time 0.85 seconds
Started Dec 27 12:58:15 PM PST 23
Finished Dec 27 12:58:26 PM PST 23
Peak memory 204624 kb
Host smart-53aff82d-b92f-493a-b2cb-81cde678dfba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922860857 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.2922860857
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.2946133415
Short name T608
Test name
Test status
Simulation time 186225425 ps
CPU time 1.4 seconds
Started Dec 27 12:58:19 PM PST 23
Finished Dec 27 12:58:33 PM PST 23
Peak memory 205564 kb
Host smart-ecb5321c-7a0b-467d-80a9-cff2e1dac06d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946133415 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.2946133415
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.986733957
Short name T939
Test name
Test status
Simulation time 314114926109 ps
CPU time 1244.06 seconds
Started Dec 27 12:58:11 PM PST 23
Finished Dec 27 01:19:05 PM PST 23
Peak memory 217248 kb
Host smart-673ce9f2-a371-4a35-9ee8-e8a3fbf6a8c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986733957 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.986733957
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.2395404439
Short name T775
Test name
Test status
Simulation time 365797857 ps
CPU time 4.44 seconds
Started Dec 27 12:59:04 PM PST 23
Finished Dec 27 12:59:17 PM PST 23
Peak memory 214096 kb
Host smart-66fbc413-1446-4ced-9a66-4cfa834fadda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395404439 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.2395404439
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.3329274871
Short name T772
Test name
Test status
Simulation time 51390308 ps
CPU time 0.92 seconds
Started Dec 27 12:59:07 PM PST 23
Finished Dec 27 12:59:18 PM PST 23
Peak memory 204976 kb
Host smart-06780085-2b08-4cb5-8501-c8cb9d5e3dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329274871 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.3329274871
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.1827975718
Short name T499
Test name
Test status
Simulation time 32368188 ps
CPU time 0.91 seconds
Started Dec 27 12:59:07 PM PST 23
Finished Dec 27 12:59:18 PM PST 23
Peak memory 205072 kb
Host smart-91a501f0-9069-496d-9d47-e61476b65337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827975718 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.1827975718
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.3444478225
Short name T695
Test name
Test status
Simulation time 24387027 ps
CPU time 0.98 seconds
Started Dec 27 12:58:57 PM PST 23
Finished Dec 27 12:59:05 PM PST 23
Peak memory 213988 kb
Host smart-cc7680c4-65f5-4060-8307-51e03b0c1152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444478225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.3444478225
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.2814882837
Short name T347
Test name
Test status
Simulation time 16462884 ps
CPU time 1.02 seconds
Started Dec 27 12:58:56 PM PST 23
Finished Dec 27 12:59:03 PM PST 23
Peak memory 205412 kb
Host smart-68401990-e567-4616-94f4-b9bdb6d31308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814882837 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.2814882837
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.3769062292
Short name T711
Test name
Test status
Simulation time 20819778 ps
CPU time 1.08 seconds
Started Dec 27 12:59:08 PM PST 23
Finished Dec 27 12:59:19 PM PST 23
Peak memory 214156 kb
Host smart-eb8097c4-5840-4fb9-bcb2-c862586be788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769062292 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.3769062292
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.2506103435
Short name T321
Test name
Test status
Simulation time 176886013 ps
CPU time 2.85 seconds
Started Dec 27 12:58:55 PM PST 23
Finished Dec 27 12:59:04 PM PST 23
Peak memory 214152 kb
Host smart-ed332994-b712-49ba-aff8-0a3851b90e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506103435 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.2506103435
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.1666887628
Short name T640
Test name
Test status
Simulation time 195762043 ps
CPU time 2.91 seconds
Started Dec 27 12:59:23 PM PST 23
Finished Dec 27 12:59:36 PM PST 23
Peak memory 214124 kb
Host smart-ff90504f-234d-479d-acef-d91d78f75b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666887628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.1666887628
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.3114981150
Short name T639
Test name
Test status
Simulation time 93919452 ps
CPU time 0.89 seconds
Started Dec 27 12:58:58 PM PST 23
Finished Dec 27 12:59:06 PM PST 23
Peak memory 205024 kb
Host smart-49c56ed6-28da-4e70-ae4d-c69237cb11f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114981150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.3114981150
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.19187813
Short name T585
Test name
Test status
Simulation time 22303619 ps
CPU time 1.09 seconds
Started Dec 27 12:59:08 PM PST 23
Finished Dec 27 12:59:20 PM PST 23
Peak memory 205324 kb
Host smart-7471fa64-10c1-4cf6-af12-2eb85d6ee802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19187813 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.19187813
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.3996968640
Short name T560
Test name
Test status
Simulation time 52116305 ps
CPU time 0.91 seconds
Started Dec 27 12:58:16 PM PST 23
Finished Dec 27 12:58:26 PM PST 23
Peak memory 205212 kb
Host smart-9eeb8b90-de35-4bed-9e3b-53e5f2fe1ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996968640 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.3996968640
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.4267018388
Short name T748
Test name
Test status
Simulation time 37842028 ps
CPU time 0.95 seconds
Started Dec 27 12:58:09 PM PST 23
Finished Dec 27 12:58:19 PM PST 23
Peak memory 205052 kb
Host smart-f536873e-6ae0-48d4-968e-78d5df907e9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267018388 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.4267018388
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.20654607
Short name T244
Test name
Test status
Simulation time 39710865 ps
CPU time 0.86 seconds
Started Dec 27 12:58:19 PM PST 23
Finished Dec 27 12:58:37 PM PST 23
Peak memory 214140 kb
Host smart-0e27b3af-0806-4e19-a858-7798b840691f
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20654607 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.20654607
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.2383644788
Short name T134
Test name
Test status
Simulation time 48642188 ps
CPU time 1.09 seconds
Started Dec 27 12:58:47 PM PST 23
Finished Dec 27 12:58:56 PM PST 23
Peak memory 214568 kb
Host smart-17cb1a2b-059e-491a-9eb2-553bfc0b84c4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383644788 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.2383644788
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.3058605044
Short name T237
Test name
Test status
Simulation time 115354453 ps
CPU time 0.94 seconds
Started Dec 27 12:58:19 PM PST 23
Finished Dec 27 12:58:33 PM PST 23
Peak memory 215872 kb
Host smart-09ada1f2-1802-4c55-acab-9acc4892baf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058605044 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.3058605044
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_intr.1633285183
Short name T756
Test name
Test status
Simulation time 30808336 ps
CPU time 0.87 seconds
Started Dec 27 12:58:54 PM PST 23
Finished Dec 27 12:59:02 PM PST 23
Peak memory 214420 kb
Host smart-28ddac6f-aa86-4c1c-a4b0-6d444aa9cd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633285183 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.1633285183
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.2887190687
Short name T960
Test name
Test status
Simulation time 43446208 ps
CPU time 0.84 seconds
Started Dec 27 12:58:41 PM PST 23
Finished Dec 27 12:58:50 PM PST 23
Peak memory 204780 kb
Host smart-ad143d88-ed33-4082-aadf-5f0258921f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887190687 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.2887190687
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.821168624
Short name T703
Test name
Test status
Simulation time 42727670 ps
CPU time 1.34 seconds
Started Dec 27 12:58:10 PM PST 23
Finished Dec 27 12:58:21 PM PST 23
Peak memory 205684 kb
Host smart-0d5a9421-fae3-4409-88b9-7806fdc7ce38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821168624 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.821168624
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.3290745589
Short name T272
Test name
Test status
Simulation time 130674469748 ps
CPU time 399.2 seconds
Started Dec 27 12:58:48 PM PST 23
Finished Dec 27 01:05:36 PM PST 23
Peak memory 216128 kb
Host smart-02ca88c4-fe3e-42d1-9755-b2fde4305af2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290745589 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.3290745589
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.4032190058
Short name T769
Test name
Test status
Simulation time 76660410 ps
CPU time 2.23 seconds
Started Dec 27 12:59:02 PM PST 23
Finished Dec 27 12:59:12 PM PST 23
Peak memory 214128 kb
Host smart-42ad0d0c-c149-4336-9d73-8b6d8ae975bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032190058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.4032190058
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.1489749140
Short name T35
Test name
Test status
Simulation time 175669702 ps
CPU time 2.71 seconds
Started Dec 27 12:58:56 PM PST 23
Finished Dec 27 12:59:05 PM PST 23
Peak memory 214160 kb
Host smart-a5d9d876-b63a-4462-8e64-c3775cbeec4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489749140 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.1489749140
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.1704140777
Short name T31
Test name
Test status
Simulation time 35864831 ps
CPU time 1.6 seconds
Started Dec 27 12:59:00 PM PST 23
Finished Dec 27 12:59:09 PM PST 23
Peak memory 214048 kb
Host smart-800378f9-f395-4f27-8d10-8bbc4f222a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704140777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1704140777
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.3673155886
Short name T277
Test name
Test status
Simulation time 18547393 ps
CPU time 1.05 seconds
Started Dec 27 12:59:10 PM PST 23
Finished Dec 27 12:59:22 PM PST 23
Peak memory 205140 kb
Host smart-84e77e26-86d7-4d3e-8a6f-acef7f728f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673155886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.3673155886
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2365167516
Short name T681
Test name
Test status
Simulation time 308922969 ps
CPU time 4.19 seconds
Started Dec 27 12:59:00 PM PST 23
Finished Dec 27 12:59:12 PM PST 23
Peak memory 214104 kb
Host smart-47860328-884a-441d-aaef-7730ec614bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365167516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2365167516
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.1436144519
Short name T496
Test name
Test status
Simulation time 46536321 ps
CPU time 0.95 seconds
Started Dec 27 12:59:05 PM PST 23
Finished Dec 27 12:59:14 PM PST 23
Peak memory 205480 kb
Host smart-50b30256-8616-4c52-8551-3e2bd129658f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436144519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.1436144519
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.2134499452
Short name T36
Test name
Test status
Simulation time 17866690 ps
CPU time 1.15 seconds
Started Dec 27 12:59:08 PM PST 23
Finished Dec 27 12:59:19 PM PST 23
Peak memory 205236 kb
Host smart-aa25ea7e-4eab-496a-b1b5-acc22f4d32ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134499452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.2134499452
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.2620219818
Short name T351
Test name
Test status
Simulation time 33887779 ps
CPU time 0.93 seconds
Started Dec 27 12:59:12 PM PST 23
Finished Dec 27 12:59:23 PM PST 23
Peak memory 205672 kb
Host smart-2426a878-9569-447c-b8a1-0294a8c72816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620219818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.2620219818
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.3678662987
Short name T356
Test name
Test status
Simulation time 37422228 ps
CPU time 1.06 seconds
Started Dec 27 12:59:11 PM PST 23
Finished Dec 27 12:59:22 PM PST 23
Peak memory 205344 kb
Host smart-280ab816-cde6-4d18-9797-910d3ed30e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678662987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.3678662987
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.3326621079
Short name T290
Test name
Test status
Simulation time 20044500 ps
CPU time 1.06 seconds
Started Dec 27 12:58:43 PM PST 23
Finished Dec 27 12:58:52 PM PST 23
Peak memory 205840 kb
Host smart-072dc7a7-72dc-4d59-bfb6-4f8cf6ce121c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326621079 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.3326621079
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.1207961865
Short name T99
Test name
Test status
Simulation time 19211751 ps
CPU time 0.86 seconds
Started Dec 27 12:58:22 PM PST 23
Finished Dec 27 12:58:37 PM PST 23
Peak memory 204636 kb
Host smart-cdc71849-1334-4f07-80d3-67a48b503588
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207961865 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.1207961865
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.1330632926
Short name T964
Test name
Test status
Simulation time 38200666 ps
CPU time 1.01 seconds
Started Dec 27 12:58:36 PM PST 23
Finished Dec 27 12:58:46 PM PST 23
Peak memory 214384 kb
Host smart-bf0e7f87-200b-437f-8277-54061ee4b22f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330632926 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.1330632926
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.717859066
Short name T691
Test name
Test status
Simulation time 28005036 ps
CPU time 1.02 seconds
Started Dec 27 12:58:35 PM PST 23
Finished Dec 27 12:58:46 PM PST 23
Peak memory 221488 kb
Host smart-96325ac2-5a77-46fc-92f9-f352b4eeeb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717859066 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.717859066
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.3604057943
Short name T568
Test name
Test status
Simulation time 23538802 ps
CPU time 1.01 seconds
Started Dec 27 12:58:06 PM PST 23
Finished Dec 27 12:58:13 PM PST 23
Peak memory 205384 kb
Host smart-9a0f69c5-27ba-4679-8c95-55cadc1bbe1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604057943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.3604057943
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.3506548978
Short name T549
Test name
Test status
Simulation time 26728084 ps
CPU time 0.92 seconds
Started Dec 27 12:58:19 PM PST 23
Finished Dec 27 12:58:33 PM PST 23
Peak memory 214412 kb
Host smart-517f96ae-9a11-46b0-8462-af5b71cff773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506548978 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.3506548978
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.4070637752
Short name T612
Test name
Test status
Simulation time 12141158 ps
CPU time 0.87 seconds
Started Dec 27 12:58:14 PM PST 23
Finished Dec 27 12:58:25 PM PST 23
Peak memory 204612 kb
Host smart-786a5a39-8a2d-44e9-b342-32ebb57fe2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070637752 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.4070637752
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.2813088644
Short name T476
Test name
Test status
Simulation time 362531650 ps
CPU time 2.29 seconds
Started Dec 27 12:58:19 PM PST 23
Finished Dec 27 12:58:34 PM PST 23
Peak memory 205724 kb
Host smart-2eea7953-0bf8-46eb-a279-ade469f6e5ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813088644 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.2813088644
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.660619731
Short name T94
Test name
Test status
Simulation time 33445779212 ps
CPU time 857.32 seconds
Started Dec 27 12:58:13 PM PST 23
Finished Dec 27 01:12:41 PM PST 23
Peak memory 215916 kb
Host smart-206c65a3-a638-41aa-b5b4-c75fdbd0bbb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660619731 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.660619731
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/281.edn_genbits.1409283213
Short name T26
Test name
Test status
Simulation time 55431834 ps
CPU time 2.1 seconds
Started Dec 27 12:59:09 PM PST 23
Finished Dec 27 12:59:22 PM PST 23
Peak memory 214120 kb
Host smart-7f717fbb-3390-46ba-aaf5-482e167447c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409283213 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.1409283213
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.3635699738
Short name T668
Test name
Test status
Simulation time 47903651 ps
CPU time 0.88 seconds
Started Dec 27 12:59:06 PM PST 23
Finished Dec 27 12:59:17 PM PST 23
Peak memory 204964 kb
Host smart-dafba2e4-cf90-4fd5-bceb-b5b996f7afc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635699738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.3635699738
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.4082606164
Short name T354
Test name
Test status
Simulation time 32634856 ps
CPU time 1 seconds
Started Dec 27 12:59:02 PM PST 23
Finished Dec 27 12:59:11 PM PST 23
Peak memory 205404 kb
Host smart-e522ff24-ebc6-4ed3-9f79-1b40df4a43a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082606164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.4082606164
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.2097711339
Short name T327
Test name
Test status
Simulation time 124679659 ps
CPU time 3.09 seconds
Started Dec 27 12:59:02 PM PST 23
Finished Dec 27 12:59:14 PM PST 23
Peak memory 214164 kb
Host smart-cb3c119e-09c8-44c0-9995-c0a977758bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097711339 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.2097711339
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.966134927
Short name T280
Test name
Test status
Simulation time 62293817 ps
CPU time 1 seconds
Started Dec 27 12:59:04 PM PST 23
Finished Dec 27 12:59:13 PM PST 23
Peak memory 205256 kb
Host smart-98c6e847-4d24-4448-975d-c713a31bf0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966134927 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.966134927
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.2483713927
Short name T342
Test name
Test status
Simulation time 36396611 ps
CPU time 1.07 seconds
Started Dec 27 12:59:01 PM PST 23
Finished Dec 27 12:59:09 PM PST 23
Peak memory 214180 kb
Host smart-a274c089-7b78-464d-a193-7c2bc398cc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483713927 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.2483713927
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.2502000938
Short name T503
Test name
Test status
Simulation time 78291353 ps
CPU time 2.66 seconds
Started Dec 27 12:59:00 PM PST 23
Finished Dec 27 12:59:10 PM PST 23
Peak memory 214172 kb
Host smart-3e85d081-746a-4b0f-966f-b7be5bef7578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502000938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.2502000938
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.2323982534
Short name T680
Test name
Test status
Simulation time 70556071 ps
CPU time 0.96 seconds
Started Dec 27 12:58:56 PM PST 23
Finished Dec 27 12:59:04 PM PST 23
Peak memory 204928 kb
Host smart-ad126b68-6bb1-463f-9012-83e600c4b134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323982534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.2323982534
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.2212694809
Short name T517
Test name
Test status
Simulation time 58660445 ps
CPU time 1.13 seconds
Started Dec 27 12:58:54 PM PST 23
Finished Dec 27 12:59:02 PM PST 23
Peak memory 205648 kb
Host smart-f524926b-e203-443f-b5d8-f0f3dd3b91c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212694809 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.2212694809
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.2400191785
Short name T759
Test name
Test status
Simulation time 53280206 ps
CPU time 0.94 seconds
Started Dec 27 12:58:17 PM PST 23
Finished Dec 27 12:58:27 PM PST 23
Peak memory 205304 kb
Host smart-6a511cd0-1ff5-4ad1-8ddc-3fd658fa557b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400191785 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.2400191785
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.3653672384
Short name T620
Test name
Test status
Simulation time 45726200 ps
CPU time 0.88 seconds
Started Dec 27 12:58:23 PM PST 23
Finished Dec 27 12:58:37 PM PST 23
Peak memory 205088 kb
Host smart-2bf9e9b6-5416-4ae7-96fd-0caf1b8cc6fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653672384 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.3653672384
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.1161222474
Short name T242
Test name
Test status
Simulation time 11236464 ps
CPU time 0.84 seconds
Started Dec 27 12:58:19 PM PST 23
Finished Dec 27 12:58:33 PM PST 23
Peak memory 214248 kb
Host smart-606c4ee8-3aa1-4627-9a5f-a573ea1c08f9
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161222474 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.1161222474
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.1262097357
Short name T830
Test name
Test status
Simulation time 37993213 ps
CPU time 1 seconds
Started Dec 27 12:58:13 PM PST 23
Finished Dec 27 12:58:24 PM PST 23
Peak memory 214552 kb
Host smart-ca9ba54e-df4a-414b-be78-8cc5087dbf85
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262097357 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.1262097357
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.829865158
Short name T158
Test name
Test status
Simulation time 34136459 ps
CPU time 0.8 seconds
Started Dec 27 12:58:11 PM PST 23
Finished Dec 27 12:58:22 PM PST 23
Peak memory 215256 kb
Host smart-9f0464d2-e06a-4eb0-aa30-680c03bbd319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829865158 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.829865158
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.1358172202
Short name T12
Test name
Test status
Simulation time 31714649 ps
CPU time 1.05 seconds
Started Dec 27 12:58:41 PM PST 23
Finished Dec 27 12:58:50 PM PST 23
Peak memory 214160 kb
Host smart-373b48ec-412c-4b33-93cc-da0221b5468e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358172202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.1358172202
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.636440543
Short name T82
Test name
Test status
Simulation time 33536993 ps
CPU time 0.87 seconds
Started Dec 27 12:58:02 PM PST 23
Finished Dec 27 12:58:09 PM PST 23
Peak memory 214228 kb
Host smart-a9424178-39e7-46d6-bb63-19a20ddfc702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636440543 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.636440543
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.3383479141
Short name T840
Test name
Test status
Simulation time 45287280 ps
CPU time 0.89 seconds
Started Dec 27 12:58:25 PM PST 23
Finished Dec 27 12:58:38 PM PST 23
Peak memory 204644 kb
Host smart-2b6f534b-8fe2-4f0d-958d-8057ae3fdc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383479141 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.3383479141
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.1981824761
Short name T599
Test name
Test status
Simulation time 206993789 ps
CPU time 4.5 seconds
Started Dec 27 12:58:06 PM PST 23
Finished Dec 27 12:58:17 PM PST 23
Peak memory 205896 kb
Host smart-c54bb82c-a315-43d8-8a12-b89fba322d35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981824761 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1981824761
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.2603422806
Short name T803
Test name
Test status
Simulation time 159166519819 ps
CPU time 2405.12 seconds
Started Dec 27 12:58:14 PM PST 23
Finished Dec 27 01:38:29 PM PST 23
Peak memory 223160 kb
Host smart-2a594a63-682e-44e3-942c-4a7edeecb977
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603422806 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.2603422806
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.257865114
Short name T600
Test name
Test status
Simulation time 55648280 ps
CPU time 0.96 seconds
Started Dec 27 12:59:18 PM PST 23
Finished Dec 27 12:59:30 PM PST 23
Peak memory 205068 kb
Host smart-00af4d45-5987-4b3b-b255-f7f60122b116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257865114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.257865114
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.3283282012
Short name T760
Test name
Test status
Simulation time 18858237 ps
CPU time 1.16 seconds
Started Dec 27 12:59:05 PM PST 23
Finished Dec 27 12:59:15 PM PST 23
Peak memory 205816 kb
Host smart-146d7fa4-0c48-4673-bd88-6ecc85c1e285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283282012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.3283282012
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.1993864279
Short name T14
Test name
Test status
Simulation time 32232898 ps
CPU time 1.1 seconds
Started Dec 27 12:58:58 PM PST 23
Finished Dec 27 12:59:07 PM PST 23
Peak memory 214216 kb
Host smart-3495b2fc-ac30-41d5-8efc-bbe57ab3df79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993864279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.1993864279
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.1093697499
Short name T646
Test name
Test status
Simulation time 55508438 ps
CPU time 1.02 seconds
Started Dec 27 12:59:03 PM PST 23
Finished Dec 27 12:59:12 PM PST 23
Peak memory 205120 kb
Host smart-89d5b3f8-0ddd-44d3-a50c-3636eea45c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093697499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.1093697499
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.1985190387
Short name T936
Test name
Test status
Simulation time 45715625 ps
CPU time 2 seconds
Started Dec 27 12:59:04 PM PST 23
Finished Dec 27 12:59:15 PM PST 23
Peak memory 214156 kb
Host smart-7d86e2b7-649b-4122-b9cd-c106708b7232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985190387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.1985190387
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.3682847297
Short name T546
Test name
Test status
Simulation time 58645882 ps
CPU time 1.39 seconds
Started Dec 27 12:59:04 PM PST 23
Finished Dec 27 12:59:13 PM PST 23
Peak memory 214152 kb
Host smart-3d2a15c8-2b0b-47b4-97cb-23cfb389a85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682847297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.3682847297
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.2427425998
Short name T480
Test name
Test status
Simulation time 69752967 ps
CPU time 0.98 seconds
Started Dec 27 12:59:15 PM PST 23
Finished Dec 27 12:59:27 PM PST 23
Peak memory 214052 kb
Host smart-3c934401-eb66-479d-9975-25f7df8dfa58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427425998 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.2427425998
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.2292972827
Short name T944
Test name
Test status
Simulation time 52341887 ps
CPU time 0.88 seconds
Started Dec 27 12:58:59 PM PST 23
Finished Dec 27 12:59:07 PM PST 23
Peak memory 204784 kb
Host smart-c6fa79ed-436f-492c-b4c3-3ff81342b1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292972827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.2292972827
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.3931868478
Short name T313
Test name
Test status
Simulation time 53595979 ps
CPU time 0.88 seconds
Started Dec 27 12:59:12 PM PST 23
Finished Dec 27 12:59:24 PM PST 23
Peak memory 204976 kb
Host smart-5934d421-a2b6-4813-b7b6-8e7483b31017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931868478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.3931868478
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.3467264398
Short name T682
Test name
Test status
Simulation time 22673371 ps
CPU time 0.94 seconds
Started Dec 27 12:57:31 PM PST 23
Finished Dec 27 12:57:38 PM PST 23
Peak memory 205184 kb
Host smart-5e4be168-85fc-4d0c-836d-f659353275fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467264398 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.3467264398
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.3076609786
Short name T928
Test name
Test status
Simulation time 18385995 ps
CPU time 0.81 seconds
Started Dec 27 12:58:01 PM PST 23
Finished Dec 27 12:58:08 PM PST 23
Peak memory 204256 kb
Host smart-b285c3f9-abe3-417e-bc78-bf4a1d2de51b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076609786 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.3076609786
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.2924728919
Short name T108
Test name
Test status
Simulation time 11577536 ps
CPU time 0.86 seconds
Started Dec 27 12:57:41 PM PST 23
Finished Dec 27 12:57:44 PM PST 23
Peak memory 214148 kb
Host smart-c1825e0e-14ed-4d51-84aa-baf16085f472
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924728919 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.2924728919
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.526471630
Short name T719
Test name
Test status
Simulation time 65324695 ps
CPU time 0.95 seconds
Started Dec 27 12:57:43 PM PST 23
Finished Dec 27 12:57:45 PM PST 23
Peak memory 214556 kb
Host smart-098ba475-a412-4237-93a6-b69a8a421c84
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526471630 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_dis
able_auto_req_mode.526471630
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.1817009280
Short name T832
Test name
Test status
Simulation time 20720071 ps
CPU time 1.07 seconds
Started Dec 27 12:57:36 PM PST 23
Finished Dec 27 12:57:41 PM PST 23
Peak memory 215716 kb
Host smart-95ba1ee7-d30e-4309-8b35-7e5806212cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817009280 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.1817009280
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.2288583567
Short name T917
Test name
Test status
Simulation time 21967600 ps
CPU time 1.13 seconds
Started Dec 27 12:57:58 PM PST 23
Finished Dec 27 12:58:01 PM PST 23
Peak memory 205548 kb
Host smart-60f510e0-c43b-4375-93c7-16901d2e83a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288583567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.2288583567
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.1839485687
Short name T89
Test name
Test status
Simulation time 24879872 ps
CPU time 0.94 seconds
Started Dec 27 12:57:40 PM PST 23
Finished Dec 27 12:57:43 PM PST 23
Peak memory 214488 kb
Host smart-2e271c20-f7a8-4f33-9fa7-2fbd7a7e6208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839485687 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.1839485687
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.202804380
Short name T266
Test name
Test status
Simulation time 16895090 ps
CPU time 0.92 seconds
Started Dec 27 12:57:31 PM PST 23
Finished Dec 27 12:57:37 PM PST 23
Peak memory 204676 kb
Host smart-ca6efa75-6336-44b6-87b9-ad26f782e698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202804380 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.202804380
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.644621827
Short name T23
Test name
Test status
Simulation time 1253433973 ps
CPU time 5.62 seconds
Started Dec 27 12:57:28 PM PST 23
Finished Dec 27 12:57:41 PM PST 23
Peak memory 233920 kb
Host smart-6c345118-5875-49e8-a492-e0a74c094595
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644621827 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.644621827
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.2896867609
Short name T880
Test name
Test status
Simulation time 13197096 ps
CPU time 0.9 seconds
Started Dec 27 12:57:33 PM PST 23
Finished Dec 27 12:57:39 PM PST 23
Peak memory 204740 kb
Host smart-99e2690a-c3a7-4c78-9f6d-73430a976c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896867609 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.2896867609
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.3145279292
Short name T236
Test name
Test status
Simulation time 28742096 ps
CPU time 1.13 seconds
Started Dec 27 12:57:34 PM PST 23
Finished Dec 27 12:57:40 PM PST 23
Peak memory 205280 kb
Host smart-990f353a-9d18-49e5-9ca0-3c7b0cc6bfb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145279292 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.3145279292
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.4037651351
Short name T657
Test name
Test status
Simulation time 268689465515 ps
CPU time 891.24 seconds
Started Dec 27 12:57:40 PM PST 23
Finished Dec 27 01:12:34 PM PST 23
Peak memory 215920 kb
Host smart-3059c192-44cf-47c5-a2ab-4ffc6a4bd017
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037651351 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.4037651351
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.410463438
Short name T264
Test name
Test status
Simulation time 19702637 ps
CPU time 1.02 seconds
Started Dec 27 12:58:11 PM PST 23
Finished Dec 27 12:58:22 PM PST 23
Peak memory 205064 kb
Host smart-48ad637c-ef17-4a18-a214-0fe60b0e85bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410463438 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.410463438
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.3467862270
Short name T661
Test name
Test status
Simulation time 24435714 ps
CPU time 0.75 seconds
Started Dec 27 12:58:32 PM PST 23
Finished Dec 27 12:58:43 PM PST 23
Peak memory 203952 kb
Host smart-b858c3af-aaca-4f5c-9d21-4163ce7841b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467862270 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3467862270
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.1997857137
Short name T800
Test name
Test status
Simulation time 11938609 ps
CPU time 0.86 seconds
Started Dec 27 12:58:37 PM PST 23
Finished Dec 27 12:58:48 PM PST 23
Peak memory 214296 kb
Host smart-3fdd1fd9-8af6-47cb-99dc-d2a570a28a4d
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997857137 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1997857137
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.1231197616
Short name T125
Test name
Test status
Simulation time 43737147 ps
CPU time 1 seconds
Started Dec 27 12:58:11 PM PST 23
Finished Dec 27 12:58:22 PM PST 23
Peak memory 214584 kb
Host smart-eb6920ed-3ab2-4437-b5ff-330a3e62db5f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231197616 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.1231197616
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.4291385926
Short name T234
Test name
Test status
Simulation time 24867200 ps
CPU time 0.9 seconds
Started Dec 27 12:58:24 PM PST 23
Finished Dec 27 12:58:37 PM PST 23
Peak memory 214764 kb
Host smart-3bb058d2-ccfd-4735-815f-8eff8fddae64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291385926 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.4291385926
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.3828968148
Short name T60
Test name
Test status
Simulation time 27579955 ps
CPU time 0.92 seconds
Started Dec 27 12:58:21 PM PST 23
Finished Dec 27 12:58:36 PM PST 23
Peak memory 205424 kb
Host smart-aa28413f-ee07-41c6-ab55-e59a5f6042d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828968148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3828968148
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.2312829529
Short name T817
Test name
Test status
Simulation time 69994011 ps
CPU time 0.94 seconds
Started Dec 27 12:58:15 PM PST 23
Finished Dec 27 12:58:26 PM PST 23
Peak memory 221656 kb
Host smart-de560187-f08b-4569-b94a-99b244ff26da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312829529 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.2312829529
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.540452635
Short name T687
Test name
Test status
Simulation time 46235294 ps
CPU time 0.85 seconds
Started Dec 27 12:58:21 PM PST 23
Finished Dec 27 12:58:35 PM PST 23
Peak memory 204820 kb
Host smart-accfbda8-8aaa-4265-8b04-5def1a394de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540452635 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.540452635
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.1965791312
Short name T588
Test name
Test status
Simulation time 220690682 ps
CPU time 1.75 seconds
Started Dec 27 12:58:36 PM PST 23
Finished Dec 27 12:58:47 PM PST 23
Peak memory 205888 kb
Host smart-4c8a54e6-d8be-4d4f-8fe3-d0d0820ead35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965791312 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.1965791312
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_alert.2459595401
Short name T894
Test name
Test status
Simulation time 25962069 ps
CPU time 0.94 seconds
Started Dec 27 12:58:12 PM PST 23
Finished Dec 27 12:58:22 PM PST 23
Peak memory 205316 kb
Host smart-608b54f4-ea6b-4fe5-8913-191adbe79cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459595401 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.2459595401
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.947906980
Short name T77
Test name
Test status
Simulation time 37185966 ps
CPU time 0.83 seconds
Started Dec 27 12:58:35 PM PST 23
Finished Dec 27 12:58:46 PM PST 23
Peak memory 204968 kb
Host smart-8de36b43-4219-452a-860f-3a532fdbf2dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947906980 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.947906980
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.2779232091
Short name T891
Test name
Test status
Simulation time 11059774 ps
CPU time 0.82 seconds
Started Dec 27 12:58:08 PM PST 23
Finished Dec 27 12:58:15 PM PST 23
Peak memory 214344 kb
Host smart-79494124-0d9b-4da4-959b-63de8348b5f0
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779232091 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.2779232091
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.58014411
Short name T801
Test name
Test status
Simulation time 200473369 ps
CPU time 0.95 seconds
Started Dec 27 12:58:39 PM PST 23
Finished Dec 27 12:58:48 PM PST 23
Peak memory 214528 kb
Host smart-8e8769ea-c1d7-4dd9-aacb-d49560dbfe90
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58014411 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_dis
able_auto_req_mode.58014411
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.3096459639
Short name T852
Test name
Test status
Simulation time 39686559 ps
CPU time 0.92 seconds
Started Dec 27 12:58:11 PM PST 23
Finished Dec 27 12:58:22 PM PST 23
Peak memory 215564 kb
Host smart-a4775355-894a-4597-9d14-44914897918a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096459639 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.3096459639
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.3995434433
Short name T626
Test name
Test status
Simulation time 53469563 ps
CPU time 0.9 seconds
Started Dec 27 12:58:12 PM PST 23
Finished Dec 27 12:58:22 PM PST 23
Peak memory 205040 kb
Host smart-15414656-6774-4c40-b999-d8600cf51ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995434433 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.3995434433
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.1891957991
Short name T798
Test name
Test status
Simulation time 21590885 ps
CPU time 0.88 seconds
Started Dec 27 12:58:29 PM PST 23
Finished Dec 27 12:58:40 PM PST 23
Peak memory 214528 kb
Host smart-3ee6992f-4960-46ac-a28d-19c856ac341e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891957991 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.1891957991
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.1526588606
Short name T931
Test name
Test status
Simulation time 12820243 ps
CPU time 0.85 seconds
Started Dec 27 12:58:46 PM PST 23
Finished Dec 27 12:58:55 PM PST 23
Peak memory 204576 kb
Host smart-e0dd5c2a-16ba-47fe-82e8-3b9e678c871b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526588606 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.1526588606
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.2715176754
Short name T606
Test name
Test status
Simulation time 174174015 ps
CPU time 1.74 seconds
Started Dec 27 12:58:35 PM PST 23
Finished Dec 27 12:58:46 PM PST 23
Peak memory 205936 kb
Host smart-4509422d-e842-4fb5-9ea5-89747fbe5842
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715176754 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.2715176754
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.2029456504
Short name T911
Test name
Test status
Simulation time 182858181776 ps
CPU time 1828.38 seconds
Started Dec 27 12:58:20 PM PST 23
Finished Dec 27 01:29:01 PM PST 23
Peak memory 222256 kb
Host smart-a0c7f655-a9a9-4127-9d67-6d4dbb13d07a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029456504 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.2029456504
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.141044410
Short name T307
Test name
Test status
Simulation time 71196922 ps
CPU time 0.98 seconds
Started Dec 27 12:58:03 PM PST 23
Finished Dec 27 12:58:12 PM PST 23
Peak memory 205180 kb
Host smart-603bcbbc-6daf-4741-8811-6a60ac472da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141044410 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.141044410
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.1742217639
Short name T671
Test name
Test status
Simulation time 40108515 ps
CPU time 0.92 seconds
Started Dec 27 12:58:21 PM PST 23
Finished Dec 27 12:58:35 PM PST 23
Peak memory 204676 kb
Host smart-c274cf1d-a426-4079-9d03-db4329ca64df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742217639 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.1742217639
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.3006591323
Short name T145
Test name
Test status
Simulation time 109711492 ps
CPU time 1.12 seconds
Started Dec 27 12:58:21 PM PST 23
Finished Dec 27 12:58:35 PM PST 23
Peak memory 214536 kb
Host smart-4c2ed13d-180d-470a-9013-00a069603b65
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006591323 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.3006591323
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_genbits.582954794
Short name T663
Test name
Test status
Simulation time 21208162 ps
CPU time 1.08 seconds
Started Dec 27 12:58:08 PM PST 23
Finished Dec 27 12:58:21 PM PST 23
Peak memory 205224 kb
Host smart-b94cfd9a-4f72-41fa-a87b-48794fe06588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582954794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.582954794
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.1724206492
Short name T702
Test name
Test status
Simulation time 30282916 ps
CPU time 1 seconds
Started Dec 27 12:58:12 PM PST 23
Finished Dec 27 12:58:23 PM PST 23
Peak memory 221776 kb
Host smart-7ae52666-df4e-48e3-b32e-fc201d33a528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724206492 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.1724206492
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.2162118201
Short name T469
Test name
Test status
Simulation time 33786297 ps
CPU time 0.78 seconds
Started Dec 27 12:58:08 PM PST 23
Finished Dec 27 12:58:16 PM PST 23
Peak memory 204644 kb
Host smart-b65154cb-e427-4654-a2cd-8ba1b14ae502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162118201 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.2162118201
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.1036698488
Short name T924
Test name
Test status
Simulation time 30116879 ps
CPU time 0.89 seconds
Started Dec 27 12:58:23 PM PST 23
Finished Dec 27 12:58:37 PM PST 23
Peak memory 204452 kb
Host smart-ff7872e2-5c44-48c1-955b-e9922da60139
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036698488 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.1036698488
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.3534292923
Short name T739
Test name
Test status
Simulation time 109393037139 ps
CPU time 602.09 seconds
Started Dec 27 12:58:28 PM PST 23
Finished Dec 27 01:08:41 PM PST 23
Peak memory 215368 kb
Host smart-db3ae680-f139-4210-a504-ccc9704bd592
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534292923 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.3534292923
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.3389727211
Short name T304
Test name
Test status
Simulation time 31481592 ps
CPU time 0.99 seconds
Started Dec 27 12:58:10 PM PST 23
Finished Dec 27 12:58:20 PM PST 23
Peak memory 205140 kb
Host smart-6dc4b7df-46c2-49c9-b5f0-91cf49ecd34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389727211 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.3389727211
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.3288218512
Short name T492
Test name
Test status
Simulation time 15329094 ps
CPU time 0.9 seconds
Started Dec 27 12:58:19 PM PST 23
Finished Dec 27 12:58:33 PM PST 23
Peak memory 204592 kb
Host smart-282243ca-0ae5-4dda-ad6f-e3b7acd29cc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288218512 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.3288218512
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.3064533259
Short name T102
Test name
Test status
Simulation time 116235936 ps
CPU time 1.15 seconds
Started Dec 27 12:58:34 PM PST 23
Finished Dec 27 12:58:45 PM PST 23
Peak memory 214512 kb
Host smart-76bb4715-3f1f-4ce5-8dc8-2415bb63888d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064533259 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.3064533259
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.3779055857
Short name T473
Test name
Test status
Simulation time 38938761 ps
CPU time 0.81 seconds
Started Dec 27 12:58:34 PM PST 23
Finished Dec 27 12:58:45 PM PST 23
Peak memory 215336 kb
Host smart-e18cc030-d0e4-4902-9855-29377644b62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779055857 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.3779055857
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.724167334
Short name T75
Test name
Test status
Simulation time 48566624 ps
CPU time 0.88 seconds
Started Dec 27 12:58:29 PM PST 23
Finished Dec 27 12:58:40 PM PST 23
Peak memory 205080 kb
Host smart-965ebecb-d601-4dc7-b270-874f1b349642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724167334 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.724167334
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.3939304484
Short name T90
Test name
Test status
Simulation time 17668193 ps
CPU time 0.98 seconds
Started Dec 27 12:58:14 PM PST 23
Finished Dec 27 12:58:25 PM PST 23
Peak memory 214528 kb
Host smart-4636cced-4ab8-4639-8384-bc231a68146f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939304484 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.3939304484
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.3045235509
Short name T454
Test name
Test status
Simulation time 68702668 ps
CPU time 0.89 seconds
Started Dec 27 12:58:13 PM PST 23
Finished Dec 27 12:58:23 PM PST 23
Peak memory 204968 kb
Host smart-4b65797f-3a11-4968-9983-7e8e7ac558fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045235509 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.3045235509
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.2079825044
Short name T763
Test name
Test status
Simulation time 473299168 ps
CPU time 1.73 seconds
Started Dec 27 12:58:03 PM PST 23
Finished Dec 27 12:58:12 PM PST 23
Peak memory 205996 kb
Host smart-e9ff5e8f-5d4f-4577-9070-5b53054ae83d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079825044 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.2079825044
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.2380990803
Short name T278
Test name
Test status
Simulation time 68196898855 ps
CPU time 1726.42 seconds
Started Dec 27 12:58:32 PM PST 23
Finished Dec 27 01:27:27 PM PST 23
Peak memory 221152 kb
Host smart-e0310893-80fd-4177-bc6e-438d15910075
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380990803 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.2380990803
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.3832857137
Short name T297
Test name
Test status
Simulation time 35496888 ps
CPU time 0.94 seconds
Started Dec 27 12:58:12 PM PST 23
Finished Dec 27 12:58:27 PM PST 23
Peak memory 205212 kb
Host smart-086cdc1d-a38d-476c-b191-46c5815cf540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832857137 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.3832857137
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.483808478
Short name T56
Test name
Test status
Simulation time 48378679 ps
CPU time 0.85 seconds
Started Dec 27 12:58:16 PM PST 23
Finished Dec 27 12:58:26 PM PST 23
Peak memory 205100 kb
Host smart-fbfcf864-40fb-4d40-8933-066c2d54c8f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483808478 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.483808478
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.4116319827
Short name T601
Test name
Test status
Simulation time 17671276 ps
CPU time 0.87 seconds
Started Dec 27 12:58:42 PM PST 23
Finished Dec 27 12:58:51 PM PST 23
Peak memory 214440 kb
Host smart-380f27cf-38e6-4f7b-ad0b-4c2005c04fa4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116319827 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.4116319827
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.1932288674
Short name T799
Test name
Test status
Simulation time 48586888 ps
CPU time 0.92 seconds
Started Dec 27 12:58:40 PM PST 23
Finished Dec 27 12:58:50 PM PST 23
Peak memory 220892 kb
Host smart-403f0c16-27ec-4964-9a35-d31f5065da02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932288674 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.1932288674
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.320537361
Short name T349
Test name
Test status
Simulation time 33656948 ps
CPU time 0.96 seconds
Started Dec 27 12:58:23 PM PST 23
Finished Dec 27 12:58:37 PM PST 23
Peak memory 205684 kb
Host smart-eceb4ef4-e8a5-4ccf-91f8-721a796aba55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320537361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.320537361
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_smoke.515665061
Short name T884
Test name
Test status
Simulation time 40924240 ps
CPU time 0.89 seconds
Started Dec 27 12:58:47 PM PST 23
Finished Dec 27 12:58:56 PM PST 23
Peak memory 204712 kb
Host smart-a188c119-1670-4162-85a1-2621f180f563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515665061 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.515665061
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.705183962
Short name T334
Test name
Test status
Simulation time 21142558 ps
CPU time 0.97 seconds
Started Dec 27 12:58:11 PM PST 23
Finished Dec 27 12:58:35 PM PST 23
Peak memory 204720 kb
Host smart-d0178eeb-7fc5-40dd-a241-68d210687c9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705183962 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.705183962
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.4034611751
Short name T673
Test name
Test status
Simulation time 156946137189 ps
CPU time 843.03 seconds
Started Dec 27 12:58:13 PM PST 23
Finished Dec 27 01:12:26 PM PST 23
Peak memory 215580 kb
Host smart-22bd444c-3314-4823-928d-058165d1a21f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034611751 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.4034611751
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.254236203
Short name T864
Test name
Test status
Simulation time 67356078 ps
CPU time 0.92 seconds
Started Dec 27 12:58:14 PM PST 23
Finished Dec 27 12:58:25 PM PST 23
Peak memory 205876 kb
Host smart-a6ce8abc-5ce9-4bcb-9d1c-5cdd273a9306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254236203 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.254236203
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.1499979471
Short name T524
Test name
Test status
Simulation time 32283769 ps
CPU time 0.91 seconds
Started Dec 27 12:58:19 PM PST 23
Finished Dec 27 12:58:33 PM PST 23
Peak memory 204552 kb
Host smart-27aaed5f-3dad-4903-b038-b805e0545e37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499979471 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1499979471
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.981688342
Short name T955
Test name
Test status
Simulation time 21527818 ps
CPU time 0.86 seconds
Started Dec 27 12:58:42 PM PST 23
Finished Dec 27 12:58:50 PM PST 23
Peak memory 214256 kb
Host smart-02893ea4-66c8-4338-aab7-43464d52399a
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981688342 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.981688342
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.3161130631
Short name T130
Test name
Test status
Simulation time 77369831 ps
CPU time 0.9 seconds
Started Dec 27 12:58:04 PM PST 23
Finished Dec 27 12:58:13 PM PST 23
Peak memory 214360 kb
Host smart-6453f57e-99be-47bd-bccc-74102546d073
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161130631 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.3161130631
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.2612517536
Short name T135
Test name
Test status
Simulation time 52794581 ps
CPU time 1.12 seconds
Started Dec 27 12:58:40 PM PST 23
Finished Dec 27 12:58:50 PM PST 23
Peak memory 221740 kb
Host smart-fbf54f6f-1420-4130-8788-422239d4b272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612517536 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.2612517536
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.4276911495
Short name T837
Test name
Test status
Simulation time 31180134 ps
CPU time 1.03 seconds
Started Dec 27 12:58:24 PM PST 23
Finished Dec 27 12:58:37 PM PST 23
Peak memory 214124 kb
Host smart-2ae7f784-0c41-48c7-b725-fab55102e6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276911495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.4276911495
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.786923460
Short name T969
Test name
Test status
Simulation time 31701352 ps
CPU time 0.84 seconds
Started Dec 27 12:58:44 PM PST 23
Finished Dec 27 12:58:53 PM PST 23
Peak memory 214236 kb
Host smart-f5ceb54f-33d2-473a-a7e6-4d5f48abe94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786923460 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.786923460
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.1567689028
Short name T675
Test name
Test status
Simulation time 18864513 ps
CPU time 0.89 seconds
Started Dec 27 12:58:22 PM PST 23
Finished Dec 27 12:58:36 PM PST 23
Peak memory 204936 kb
Host smart-67a191bf-6970-43b7-92f5-6c8cb9412672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567689028 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.1567689028
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.930129759
Short name T478
Test name
Test status
Simulation time 100270287 ps
CPU time 2.3 seconds
Started Dec 27 12:58:19 PM PST 23
Finished Dec 27 12:58:34 PM PST 23
Peak memory 205680 kb
Host smart-42f13ef2-b943-4cc3-bdac-2bada863c176
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930129759 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.930129759
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.3325470974
Short name T596
Test name
Test status
Simulation time 24093255422 ps
CPU time 138.33 seconds
Started Dec 27 12:58:34 PM PST 23
Finished Dec 27 01:01:03 PM PST 23
Peak memory 215776 kb
Host smart-cf2ae2f1-dc82-410d-b49b-679ea39ee7ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325470974 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.3325470974
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.3420194118
Short name T811
Test name
Test status
Simulation time 20380730 ps
CPU time 1.02 seconds
Started Dec 27 12:58:34 PM PST 23
Finished Dec 27 12:58:45 PM PST 23
Peak memory 205956 kb
Host smart-1544a6ce-8a2c-469d-b649-8e295ff566c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420194118 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.3420194118
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.3571869115
Short name T649
Test name
Test status
Simulation time 15784356 ps
CPU time 0.92 seconds
Started Dec 27 12:58:52 PM PST 23
Finished Dec 27 12:59:00 PM PST 23
Peak memory 204488 kb
Host smart-6c997ac2-ad5c-4df4-881a-26003d6f78bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571869115 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.3571869115
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.1416429422
Short name T100
Test name
Test status
Simulation time 13530316 ps
CPU time 0.9 seconds
Started Dec 27 12:58:52 PM PST 23
Finished Dec 27 12:59:00 PM PST 23
Peak memory 214532 kb
Host smart-9087b13f-fcb7-4fc8-8342-f81df302b736
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416429422 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.1416429422
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.349414098
Short name T777
Test name
Test status
Simulation time 20415297 ps
CPU time 0.92 seconds
Started Dec 27 12:58:42 PM PST 23
Finished Dec 27 12:58:51 PM PST 23
Peak memory 214456 kb
Host smart-676ca6f2-6ba1-4ae9-acad-3a170fcbdff5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349414098 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_di
sable_auto_req_mode.349414098
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.2562206075
Short name T615
Test name
Test status
Simulation time 23741378 ps
CPU time 0.9 seconds
Started Dec 27 12:58:43 PM PST 23
Finished Dec 27 12:58:51 PM PST 23
Peak memory 215696 kb
Host smart-f402a60a-7a9a-467a-8100-a9e65b793a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562206075 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.2562206075
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.2782549851
Short name T766
Test name
Test status
Simulation time 14775481 ps
CPU time 0.89 seconds
Started Dec 27 12:58:12 PM PST 23
Finished Dec 27 12:58:23 PM PST 23
Peak memory 204780 kb
Host smart-df02bb7f-ff3a-408f-9939-d2f533d159f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782549851 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.2782549851
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.1233443965
Short name T167
Test name
Test status
Simulation time 35085080 ps
CPU time 0.88 seconds
Started Dec 27 12:58:23 PM PST 23
Finished Dec 27 12:58:37 PM PST 23
Peak memory 214100 kb
Host smart-903dc1c1-6c7f-4c4e-a004-57e92eccfdca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233443965 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.1233443965
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.1301580807
Short name T581
Test name
Test status
Simulation time 16210116 ps
CPU time 0.92 seconds
Started Dec 27 12:58:46 PM PST 23
Finished Dec 27 12:58:55 PM PST 23
Peak memory 204736 kb
Host smart-d8649e05-2633-491c-9d66-6bdbd9e0f490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301580807 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.1301580807
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.1015700479
Short name T707
Test name
Test status
Simulation time 1669324597 ps
CPU time 3.12 seconds
Started Dec 27 12:58:32 PM PST 23
Finished Dec 27 12:58:44 PM PST 23
Peak memory 205812 kb
Host smart-3989fe40-4fdd-4ed3-9e12-e2fe0c88a4c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015700479 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.1015700479
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.3329595924
Short name T540
Test name
Test status
Simulation time 156035819376 ps
CPU time 884.98 seconds
Started Dec 27 12:58:40 PM PST 23
Finished Dec 27 01:13:34 PM PST 23
Peak memory 215904 kb
Host smart-3c920dba-6726-4a41-b6b4-71340803d449
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329595924 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.3329595924
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.3840222085
Short name T259
Test name
Test status
Simulation time 17664783 ps
CPU time 0.96 seconds
Started Dec 27 12:58:47 PM PST 23
Finished Dec 27 12:58:56 PM PST 23
Peak memory 205256 kb
Host smart-386b37ab-e223-4c47-a670-7cc809ca71f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840222085 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.3840222085
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.2653794675
Short name T925
Test name
Test status
Simulation time 32720764 ps
CPU time 0.95 seconds
Started Dec 27 12:58:42 PM PST 23
Finished Dec 27 12:58:51 PM PST 23
Peak memory 205160 kb
Host smart-03057cf8-0643-4009-b2ff-002bfbdd6428
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653794675 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.2653794675
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.1337485069
Short name T890
Test name
Test status
Simulation time 15982252 ps
CPU time 0.87 seconds
Started Dec 27 12:58:47 PM PST 23
Finished Dec 27 12:58:56 PM PST 23
Peak memory 214360 kb
Host smart-961d0ab2-0f57-412f-a1c8-6a20eae9b22d
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337485069 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1337485069
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.2743888416
Short name T638
Test name
Test status
Simulation time 70449748 ps
CPU time 0.93 seconds
Started Dec 27 12:58:32 PM PST 23
Finished Dec 27 12:58:43 PM PST 23
Peak memory 214500 kb
Host smart-8a2006c2-7f03-4a14-b794-9d6b44691a79
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743888416 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.2743888416
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.2473243314
Short name T147
Test name
Test status
Simulation time 40433279 ps
CPU time 0.83 seconds
Started Dec 27 12:58:28 PM PST 23
Finished Dec 27 12:58:39 PM PST 23
Peak memory 215508 kb
Host smart-4b091d2d-2518-46f4-a5cb-fad17bc98d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473243314 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.2473243314
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.399587758
Short name T849
Test name
Test status
Simulation time 34878210 ps
CPU time 1.05 seconds
Started Dec 27 12:58:43 PM PST 23
Finished Dec 27 12:58:52 PM PST 23
Peak memory 205392 kb
Host smart-ec99b6d0-b7c3-43d8-ae24-1e66a78c0f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399587758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.399587758
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.2034020774
Short name T468
Test name
Test status
Simulation time 26094670 ps
CPU time 0.96 seconds
Started Dec 27 12:58:36 PM PST 23
Finished Dec 27 12:58:46 PM PST 23
Peak memory 214328 kb
Host smart-36cc39af-328f-4353-8ce9-e7ccbe4b1f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034020774 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2034020774
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.3743130202
Short name T584
Test name
Test status
Simulation time 23245389 ps
CPU time 0.91 seconds
Started Dec 27 12:58:56 PM PST 23
Finished Dec 27 12:59:04 PM PST 23
Peak memory 204664 kb
Host smart-da3608c6-67cd-4e0c-b299-e46daa9e33a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743130202 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.3743130202
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.1605759027
Short name T720
Test name
Test status
Simulation time 115714328 ps
CPU time 2.85 seconds
Started Dec 27 12:58:42 PM PST 23
Finished Dec 27 12:58:53 PM PST 23
Peak memory 205984 kb
Host smart-c55518f2-0383-482b-9d6a-9b20b1a2790a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605759027 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.1605759027
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.1231555471
Short name T768
Test name
Test status
Simulation time 39342094027 ps
CPU time 475.55 seconds
Started Dec 27 12:58:38 PM PST 23
Finished Dec 27 01:06:43 PM PST 23
Peak memory 214440 kb
Host smart-435dac16-1341-4d6d-aadc-0a9fc741987b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231555471 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.1231555471
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.3914192900
Short name T805
Test name
Test status
Simulation time 20258688 ps
CPU time 0.94 seconds
Started Dec 27 12:58:37 PM PST 23
Finished Dec 27 12:58:47 PM PST 23
Peak memory 205892 kb
Host smart-bd17e2b4-ab47-485d-b7d2-6922b995cfd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914192900 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.3914192900
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.2295744425
Short name T509
Test name
Test status
Simulation time 21173291 ps
CPU time 1.02 seconds
Started Dec 27 12:58:44 PM PST 23
Finished Dec 27 12:58:53 PM PST 23
Peak memory 204560 kb
Host smart-c6bda828-7c65-4433-913c-ebd96b3e347c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295744425 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.2295744425
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.340276368
Short name T578
Test name
Test status
Simulation time 17709608 ps
CPU time 0.8 seconds
Started Dec 27 12:58:29 PM PST 23
Finished Dec 27 12:58:40 PM PST 23
Peak memory 214328 kb
Host smart-5ac7f853-2a52-45e6-9a3b-4bbe89737b3f
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340276368 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.340276368
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.2917531589
Short name T784
Test name
Test status
Simulation time 80764154 ps
CPU time 0.97 seconds
Started Dec 27 12:58:17 PM PST 23
Finished Dec 27 12:58:27 PM PST 23
Peak memory 214504 kb
Host smart-987f197a-8445-4495-90c8-326986e9dc43
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917531589 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.2917531589
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.3986011589
Short name T821
Test name
Test status
Simulation time 42001769 ps
CPU time 0.84 seconds
Started Dec 27 12:58:23 PM PST 23
Finished Dec 27 12:58:37 PM PST 23
Peak memory 215524 kb
Host smart-6ade951c-f967-4d56-a1c4-5a0fe9cf6548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986011589 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.3986011589
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.2638556133
Short name T331
Test name
Test status
Simulation time 77667242 ps
CPU time 1.07 seconds
Started Dec 27 12:58:41 PM PST 23
Finished Dec 27 12:58:50 PM PST 23
Peak memory 214172 kb
Host smart-8f43a89c-f65c-428d-8010-4347fcaf5d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638556133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.2638556133
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.995293509
Short name T168
Test name
Test status
Simulation time 25507732 ps
CPU time 0.94 seconds
Started Dec 27 12:58:39 PM PST 23
Finished Dec 27 12:58:48 PM PST 23
Peak memory 214248 kb
Host smart-faf4e224-8efa-4c1d-b0d5-50eb52ba1603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995293509 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.995293509
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.1303184180
Short name T456
Test name
Test status
Simulation time 14539508 ps
CPU time 0.88 seconds
Started Dec 27 12:58:50 PM PST 23
Finished Dec 27 12:58:59 PM PST 23
Peak memory 204556 kb
Host smart-e76884ff-a04e-44fa-b185-69943ea0db33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303184180 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.1303184180
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.3712824188
Short name T816
Test name
Test status
Simulation time 112720319 ps
CPU time 2.6 seconds
Started Dec 27 12:58:32 PM PST 23
Finished Dec 27 12:58:43 PM PST 23
Peak memory 205980 kb
Host smart-a5d4f685-09bc-4ec5-9f57-bafb6bc332db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712824188 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.3712824188
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.1799331134
Short name T98
Test name
Test status
Simulation time 19926568019 ps
CPU time 424.15 seconds
Started Dec 27 12:58:54 PM PST 23
Finished Dec 27 01:06:05 PM PST 23
Peak memory 214448 kb
Host smart-2298384c-d771-4578-a644-b4d45e15330f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799331134 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.1799331134
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.2575779783
Short name T289
Test name
Test status
Simulation time 44081776 ps
CPU time 1 seconds
Started Dec 27 12:58:40 PM PST 23
Finished Dec 27 12:58:50 PM PST 23
Peak memory 205928 kb
Host smart-2a9523fe-48ec-4ac9-8869-02bf2311ec2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575779783 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2575779783
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.928896560
Short name T669
Test name
Test status
Simulation time 164272071 ps
CPU time 0.91 seconds
Started Dec 27 12:58:58 PM PST 23
Finished Dec 27 12:59:06 PM PST 23
Peak memory 204536 kb
Host smart-eca96ffd-304d-485e-8328-45131cee9598
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928896560 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.928896560
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.923719935
Short name T672
Test name
Test status
Simulation time 37257935 ps
CPU time 0.84 seconds
Started Dec 27 12:58:47 PM PST 23
Finished Dec 27 12:58:56 PM PST 23
Peak memory 214336 kb
Host smart-a866bbb3-019c-4699-948a-fd18065b9e2c
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923719935 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.923719935
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.3486141677
Short name T101
Test name
Test status
Simulation time 44257352 ps
CPU time 1.07 seconds
Started Dec 27 12:58:35 PM PST 23
Finished Dec 27 12:58:46 PM PST 23
Peak memory 214500 kb
Host smart-1135b876-df60-45f7-af71-3e06b59e5d0d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486141677 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.3486141677
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.4188161710
Short name T159
Test name
Test status
Simulation time 18610027 ps
CPU time 1 seconds
Started Dec 27 12:58:26 PM PST 23
Finished Dec 27 12:58:39 PM PST 23
Peak memory 215644 kb
Host smart-c48e1ebd-505f-420b-98b8-b8fee9174086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188161710 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.4188161710
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.1613972643
Short name T736
Test name
Test status
Simulation time 15051465 ps
CPU time 0.93 seconds
Started Dec 27 12:58:35 PM PST 23
Finished Dec 27 12:58:45 PM PST 23
Peak memory 205480 kb
Host smart-53f97161-22ba-45da-918a-34e366e3f601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613972643 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.1613972643
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.463423300
Short name T827
Test name
Test status
Simulation time 18944426 ps
CPU time 1.04 seconds
Started Dec 27 12:58:30 PM PST 23
Finished Dec 27 12:58:40 PM PST 23
Peak memory 214304 kb
Host smart-cf28855c-9150-4902-8f23-8127c8132749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463423300 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.463423300
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.3417712190
Short name T491
Test name
Test status
Simulation time 13751799 ps
CPU time 0.89 seconds
Started Dec 27 12:58:23 PM PST 23
Finished Dec 27 12:58:37 PM PST 23
Peak memory 204572 kb
Host smart-a417698a-f53b-4dda-8bb2-d53e1067a339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417712190 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.3417712190
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.674210190
Short name T940
Test name
Test status
Simulation time 186678269 ps
CPU time 3.02 seconds
Started Dec 27 12:58:19 PM PST 23
Finished Dec 27 12:58:35 PM PST 23
Peak memory 205816 kb
Host smart-a6de2bc6-857b-4733-8a93-883d11fbdb67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674210190 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.674210190
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.4134251282
Short name T904
Test name
Test status
Simulation time 20864667701 ps
CPU time 538.85 seconds
Started Dec 27 12:58:25 PM PST 23
Finished Dec 27 01:07:36 PM PST 23
Peak memory 215532 kb
Host smart-d79155bd-d051-4036-8207-8b4449684250
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134251282 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.4134251282
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.3371930475
Short name T728
Test name
Test status
Simulation time 44093116 ps
CPU time 0.91 seconds
Started Dec 27 12:57:36 PM PST 23
Finished Dec 27 12:57:41 PM PST 23
Peak memory 205940 kb
Host smart-c4f040c3-6ff8-4aa0-b72f-2c2c0ef08fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371930475 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.3371930475
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.3674862593
Short name T541
Test name
Test status
Simulation time 51455104 ps
CPU time 0.97 seconds
Started Dec 27 12:58:05 PM PST 23
Finished Dec 27 12:58:13 PM PST 23
Peak memory 204512 kb
Host smart-2b7d0f75-e433-4117-8413-69549e3310a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674862593 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.3674862593
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.2322556132
Short name T162
Test name
Test status
Simulation time 20551395 ps
CPU time 0.84 seconds
Started Dec 27 12:57:45 PM PST 23
Finished Dec 27 12:57:47 PM PST 23
Peak memory 214208 kb
Host smart-51db6034-6404-4aa0-bf85-c035056c54ea
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322556132 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.2322556132
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.2633306850
Short name T133
Test name
Test status
Simulation time 25189988 ps
CPU time 0.95 seconds
Started Dec 27 12:58:08 PM PST 23
Finished Dec 27 12:58:16 PM PST 23
Peak memory 214548 kb
Host smart-18af9075-8ae3-48a2-a5b2-d01fc00f668f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633306850 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.2633306850
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.2937993647
Short name T152
Test name
Test status
Simulation time 18385085 ps
CPU time 1.07 seconds
Started Dec 27 12:57:39 PM PST 23
Finished Dec 27 12:57:43 PM PST 23
Peak memory 221784 kb
Host smart-14ddfd19-f34e-46fb-a785-57b1a0b2b963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937993647 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.2937993647
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.1933743546
Short name T693
Test name
Test status
Simulation time 61991248 ps
CPU time 0.9 seconds
Started Dec 27 12:57:54 PM PST 23
Finished Dec 27 12:57:56 PM PST 23
Peak memory 205036 kb
Host smart-4b9b0ce5-c642-46fa-a2a9-a5d246cb645a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933743546 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1933743546
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.3863949416
Short name T86
Test name
Test status
Simulation time 32697118 ps
CPU time 0.85 seconds
Started Dec 27 12:57:51 PM PST 23
Finished Dec 27 12:57:53 PM PST 23
Peak memory 214316 kb
Host smart-8eb5addf-dbe7-4b22-8df8-5eac4ccdbcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863949416 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.3863949416
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.555389036
Short name T300
Test name
Test status
Simulation time 18680107 ps
CPU time 0.84 seconds
Started Dec 27 12:57:45 PM PST 23
Finished Dec 27 12:57:47 PM PST 23
Peak memory 204740 kb
Host smart-1240858d-6072-4fc1-90b0-f59e134661b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555389036 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.555389036
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.1498910283
Short name T21
Test name
Test status
Simulation time 436421332 ps
CPU time 6.87 seconds
Started Dec 27 12:57:56 PM PST 23
Finished Dec 27 12:58:04 PM PST 23
Peak memory 232956 kb
Host smart-d7e94aa4-641d-425a-91ca-126b264592c5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498910283 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.1498910283
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.1047088972
Short name T552
Test name
Test status
Simulation time 16200186 ps
CPU time 0.93 seconds
Started Dec 27 12:58:12 PM PST 23
Finished Dec 27 12:58:23 PM PST 23
Peak memory 204876 kb
Host smart-db00cbc6-c392-439b-a3bf-4f6d350fcb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047088972 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.1047088972
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.1383216829
Short name T794
Test name
Test status
Simulation time 48682608 ps
CPU time 1.1 seconds
Started Dec 27 12:57:46 PM PST 23
Finished Dec 27 12:57:49 PM PST 23
Peak memory 204296 kb
Host smart-b4a82dd7-84f6-47e1-8614-a485e4298207
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383216829 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1383216829
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.2906693523
Short name T895
Test name
Test status
Simulation time 64825275877 ps
CPU time 1411.94 seconds
Started Dec 27 12:57:47 PM PST 23
Finished Dec 27 01:21:21 PM PST 23
Peak memory 217320 kb
Host smart-7f6197a0-8abf-49a5-9e07-11937e21ef35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906693523 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.2906693523
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.4013522297
Short name T622
Test name
Test status
Simulation time 113664868 ps
CPU time 0.94 seconds
Started Dec 27 12:58:27 PM PST 23
Finished Dec 27 12:58:40 PM PST 23
Peak memory 205312 kb
Host smart-97e4b650-f4c5-4293-bdbb-a009beebdb7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013522297 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.4013522297
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.1305519365
Short name T531
Test name
Test status
Simulation time 59214396 ps
CPU time 1.49 seconds
Started Dec 27 12:58:25 PM PST 23
Finished Dec 27 12:58:39 PM PST 23
Peak memory 204724 kb
Host smart-2fdd194a-b8e5-44ab-888e-81fee1b5d87a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305519365 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.1305519365
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.1313133863
Short name T535
Test name
Test status
Simulation time 44329872 ps
CPU time 0.84 seconds
Started Dec 27 12:58:44 PM PST 23
Finished Dec 27 12:58:53 PM PST 23
Peak memory 214228 kb
Host smart-44eef7ae-d372-4625-be0b-d73399de8164
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313133863 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.1313133863
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.3283765417
Short name T896
Test name
Test status
Simulation time 57939661 ps
CPU time 1 seconds
Started Dec 27 12:58:40 PM PST 23
Finished Dec 27 12:58:49 PM PST 23
Peak memory 214516 kb
Host smart-72079987-5a9c-4a78-a253-1cf5a6291fff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283765417 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.3283765417
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.207179836
Short name T246
Test name
Test status
Simulation time 72417184 ps
CPU time 1.02 seconds
Started Dec 27 12:58:29 PM PST 23
Finished Dec 27 12:58:40 PM PST 23
Peak memory 216960 kb
Host smart-cb335e50-321f-42a0-8a81-fd1f2f577176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207179836 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.207179836
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.2616207041
Short name T587
Test name
Test status
Simulation time 19382769 ps
CPU time 0.97 seconds
Started Dec 27 12:58:39 PM PST 23
Finished Dec 27 12:58:48 PM PST 23
Peak memory 204956 kb
Host smart-31ecfb63-38f6-48a2-b6fd-6396155406e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616207041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.2616207041
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.1204168681
Short name T106
Test name
Test status
Simulation time 84486573 ps
CPU time 0.78 seconds
Started Dec 27 12:58:47 PM PST 23
Finished Dec 27 12:58:57 PM PST 23
Peak memory 214340 kb
Host smart-b27ff1ce-3f7c-4bce-b3a7-40a8c3d943d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204168681 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.1204168681
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.1715335271
Short name T683
Test name
Test status
Simulation time 49343292 ps
CPU time 0.87 seconds
Started Dec 27 12:58:45 PM PST 23
Finished Dec 27 12:58:54 PM PST 23
Peak memory 204836 kb
Host smart-f20aaec0-0892-429c-940c-69a5bd5faf8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715335271 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.1715335271
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.2979307194
Short name T565
Test name
Test status
Simulation time 58551679 ps
CPU time 1.18 seconds
Started Dec 27 12:58:46 PM PST 23
Finished Dec 27 12:58:55 PM PST 23
Peak memory 205280 kb
Host smart-77611fda-7f90-45de-bcc5-9f0cc28feddc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979307194 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.2979307194
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.1050062733
Short name T733
Test name
Test status
Simulation time 55090014371 ps
CPU time 854.35 seconds
Started Dec 27 12:58:44 PM PST 23
Finished Dec 27 01:13:06 PM PST 23
Peak memory 215520 kb
Host smart-6eb7e1c0-5b5b-4928-bb3d-5373e7650f30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050062733 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.1050062733
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.4088722605
Short name T305
Test name
Test status
Simulation time 36129040 ps
CPU time 0.94 seconds
Started Dec 27 12:58:48 PM PST 23
Finished Dec 27 12:58:58 PM PST 23
Peak memory 205236 kb
Host smart-f905790e-a199-4fe7-a22a-265aead5c671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088722605 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.4088722605
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.3114575908
Short name T532
Test name
Test status
Simulation time 30787806 ps
CPU time 0.93 seconds
Started Dec 27 12:58:31 PM PST 23
Finished Dec 27 12:58:41 PM PST 23
Peak memory 205076 kb
Host smart-9b0a0f27-2e1a-4769-8f50-c5789f9dbec5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114575908 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.3114575908
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.2635808457
Short name T908
Test name
Test status
Simulation time 27778604 ps
CPU time 1 seconds
Started Dec 27 12:58:35 PM PST 23
Finished Dec 27 12:58:46 PM PST 23
Peak memory 214544 kb
Host smart-43e1e3cd-3396-4f35-9094-aa563609ba08
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635808457 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.2635808457
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.2639253250
Short name T455
Test name
Test status
Simulation time 44246583 ps
CPU time 1.05 seconds
Started Dec 27 12:58:47 PM PST 23
Finished Dec 27 12:58:57 PM PST 23
Peak memory 214788 kb
Host smart-348b218e-8519-4d1e-b816-8c8d0de9f4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639253250 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2639253250
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.2751445201
Short name T746
Test name
Test status
Simulation time 21730763 ps
CPU time 1.1 seconds
Started Dec 27 12:58:55 PM PST 23
Finished Dec 27 12:59:03 PM PST 23
Peak memory 205096 kb
Host smart-fe436d40-43ea-4575-9c1b-05e76b31d1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751445201 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.2751445201
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.2556893419
Short name T765
Test name
Test status
Simulation time 32456402 ps
CPU time 0.96 seconds
Started Dec 27 12:58:33 PM PST 23
Finished Dec 27 12:58:44 PM PST 23
Peak memory 221764 kb
Host smart-42773d95-570e-49d5-9c24-b884686529e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556893419 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.2556893419
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.483958318
Short name T655
Test name
Test status
Simulation time 36704344 ps
CPU time 0.81 seconds
Started Dec 27 12:58:45 PM PST 23
Finished Dec 27 12:58:53 PM PST 23
Peak memory 204788 kb
Host smart-a7ecf40f-4202-42f8-8ace-58c953a9e98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483958318 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.483958318
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.765501179
Short name T592
Test name
Test status
Simulation time 232474956 ps
CPU time 2.16 seconds
Started Dec 27 12:58:50 PM PST 23
Finished Dec 27 12:59:00 PM PST 23
Peak memory 205416 kb
Host smart-426f8520-a62f-4cc5-aca2-fff7dc629db5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765501179 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.765501179
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.3237515613
Short name T647
Test name
Test status
Simulation time 48182658162 ps
CPU time 1060.27 seconds
Started Dec 27 12:59:04 PM PST 23
Finished Dec 27 01:16:53 PM PST 23
Peak memory 215464 kb
Host smart-efd0b179-6676-41d4-8956-4ba7288814be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237515613 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.3237515613
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.1869947022
Short name T310
Test name
Test status
Simulation time 31695567 ps
CPU time 0.94 seconds
Started Dec 27 12:58:47 PM PST 23
Finished Dec 27 12:59:00 PM PST 23
Peak memory 205572 kb
Host smart-e0eb7b42-dcbb-4d8e-b4c9-4c10a1faa11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869947022 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.1869947022
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.621627766
Short name T519
Test name
Test status
Simulation time 15441615 ps
CPU time 0.91 seconds
Started Dec 27 12:58:21 PM PST 23
Finished Dec 27 12:58:35 PM PST 23
Peak memory 205092 kb
Host smart-fb482566-d74b-4b87-8b70-3048912e99fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621627766 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.621627766
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.1251240303
Short name T970
Test name
Test status
Simulation time 16397803 ps
CPU time 0.9 seconds
Started Dec 27 12:58:30 PM PST 23
Finished Dec 27 12:58:46 PM PST 23
Peak memory 214532 kb
Host smart-15c186c0-0b2d-4050-a8b0-b944fee8ff79
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251240303 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.1251240303
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.4269706236
Short name T138
Test name
Test status
Simulation time 26474375 ps
CPU time 1.03 seconds
Started Dec 27 12:58:42 PM PST 23
Finished Dec 27 12:58:51 PM PST 23
Peak memory 214552 kb
Host smart-2fc5f84e-2e29-4a77-982e-f63b0271dc68
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269706236 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.4269706236
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.2406901149
Short name T153
Test name
Test status
Simulation time 22089945 ps
CPU time 0.9 seconds
Started Dec 27 12:58:43 PM PST 23
Finished Dec 27 12:58:51 PM PST 23
Peak memory 215452 kb
Host smart-c2c1981e-8f16-4ef9-a7ce-dd3c41264d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406901149 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.2406901149
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.483107492
Short name T972
Test name
Test status
Simulation time 1253548186 ps
CPU time 9.28 seconds
Started Dec 27 12:58:28 PM PST 23
Finished Dec 27 12:58:48 PM PST 23
Peak memory 214172 kb
Host smart-1183bae6-03c6-41be-8fa1-88c65af0eb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483107492 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.483107492
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.985608325
Short name T812
Test name
Test status
Simulation time 19837698 ps
CPU time 0.99 seconds
Started Dec 27 12:58:48 PM PST 23
Finished Dec 27 12:58:58 PM PST 23
Peak memory 214384 kb
Host smart-89bce1a1-01cc-4323-97fb-de208b5cea71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985608325 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.985608325
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.4094620728
Short name T699
Test name
Test status
Simulation time 18312246 ps
CPU time 0.93 seconds
Started Dec 27 12:58:34 PM PST 23
Finished Dec 27 12:58:45 PM PST 23
Peak memory 204780 kb
Host smart-29326bcc-f60f-4650-bdb5-1256a3f45972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094620728 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.4094620728
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.443598850
Short name T872
Test name
Test status
Simulation time 679762171 ps
CPU time 3.83 seconds
Started Dec 27 12:58:14 PM PST 23
Finished Dec 27 12:58:27 PM PST 23
Peak memory 205856 kb
Host smart-9597fdd1-619b-40ff-942b-337aad1606f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443598850 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.443598850
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.1882611950
Short name T275
Test name
Test status
Simulation time 1077446934050 ps
CPU time 1876.8 seconds
Started Dec 27 12:58:37 PM PST 23
Finished Dec 27 01:30:03 PM PST 23
Peak memory 217448 kb
Host smart-d45ed454-7f81-43d2-bd17-4feb55ae1cc8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882611950 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.1882611950
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.2324204862
Short name T858
Test name
Test status
Simulation time 145414525 ps
CPU time 0.96 seconds
Started Dec 27 12:58:57 PM PST 23
Finished Dec 27 12:59:05 PM PST 23
Peak memory 205872 kb
Host smart-c4f35bc7-3a73-4819-9854-e72e66a43584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324204862 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2324204862
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.4245746091
Short name T834
Test name
Test status
Simulation time 19830929 ps
CPU time 0.97 seconds
Started Dec 27 12:58:30 PM PST 23
Finished Dec 27 12:58:40 PM PST 23
Peak memory 204604 kb
Host smart-661a6bcf-3ec8-4996-b8ab-a52b618b680d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245746091 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.4245746091
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.3892750259
Short name T119
Test name
Test status
Simulation time 27787762 ps
CPU time 0.86 seconds
Started Dec 27 12:58:36 PM PST 23
Finished Dec 27 12:58:46 PM PST 23
Peak memory 214288 kb
Host smart-e31ea277-677b-4a30-ac09-93e6beba5af8
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892750259 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.3892750259
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_err.3300147221
Short name T665
Test name
Test status
Simulation time 19744208 ps
CPU time 1.2 seconds
Started Dec 27 12:58:19 PM PST 23
Finished Dec 27 12:58:33 PM PST 23
Peak memory 221652 kb
Host smart-3379e332-c6a0-47c1-a6d5-c0e490b17f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300147221 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.3300147221
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.2494183374
Short name T839
Test name
Test status
Simulation time 15839542 ps
CPU time 1 seconds
Started Dec 27 12:59:02 PM PST 23
Finished Dec 27 12:59:11 PM PST 23
Peak memory 204924 kb
Host smart-3b012137-8e97-47b3-b796-b21306e10880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494183374 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.2494183374
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.1758975161
Short name T520
Test name
Test status
Simulation time 39557191 ps
CPU time 0.85 seconds
Started Dec 27 12:58:33 PM PST 23
Finished Dec 27 12:58:45 PM PST 23
Peak memory 214240 kb
Host smart-39750a3c-1040-4cd6-b047-cb8db593f371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758975161 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.1758975161
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.4171590517
Short name T564
Test name
Test status
Simulation time 17792413 ps
CPU time 0.84 seconds
Started Dec 27 12:58:20 PM PST 23
Finished Dec 27 12:58:33 PM PST 23
Peak memory 204764 kb
Host smart-13827dc3-9a73-45f7-b204-8a74ad52ad23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171590517 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.4171590517
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.1415032614
Short name T50
Test name
Test status
Simulation time 174847134 ps
CPU time 2.37 seconds
Started Dec 27 12:58:23 PM PST 23
Finished Dec 27 12:58:39 PM PST 23
Peak memory 205744 kb
Host smart-eb919239-5544-461b-b624-39e85409906c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415032614 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1415032614
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.3422851962
Short name T678
Test name
Test status
Simulation time 566758880869 ps
CPU time 3428.96 seconds
Started Dec 27 12:58:42 PM PST 23
Finished Dec 27 01:55:59 PM PST 23
Peak memory 229952 kb
Host smart-c595ca4f-6c61-4e0d-acce-6d5310f99181
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422851962 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.3422851962
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.4225066822
Short name T303
Test name
Test status
Simulation time 22783620 ps
CPU time 1.07 seconds
Started Dec 27 12:58:12 PM PST 23
Finished Dec 27 12:58:23 PM PST 23
Peak memory 205932 kb
Host smart-4b0e614d-7d63-4e04-9bd2-8ec62706e92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225066822 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.4225066822
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.3634329585
Short name T686
Test name
Test status
Simulation time 69740893 ps
CPU time 0.85 seconds
Started Dec 27 12:58:31 PM PST 23
Finished Dec 27 12:58:41 PM PST 23
Peak memory 204480 kb
Host smart-014fcd32-acc4-4116-a9e7-98f3555db40e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634329585 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.3634329585
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.4003900943
Short name T110
Test name
Test status
Simulation time 41584863 ps
CPU time 0.84 seconds
Started Dec 27 12:58:29 PM PST 23
Finished Dec 27 12:58:39 PM PST 23
Peak memory 214304 kb
Host smart-0520f3f7-e662-4a4c-b4e9-5542cff4c8bd
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003900943 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.4003900943
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_err.413086462
Short name T151
Test name
Test status
Simulation time 23591834 ps
CPU time 0.9 seconds
Started Dec 27 12:58:54 PM PST 23
Finished Dec 27 12:59:02 PM PST 23
Peak memory 215552 kb
Host smart-559c5069-a83e-4c7c-afb3-f53aee149333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413086462 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.413086462
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.3584910833
Short name T63
Test name
Test status
Simulation time 20753083 ps
CPU time 1.08 seconds
Started Dec 27 12:58:48 PM PST 23
Finished Dec 27 12:58:58 PM PST 23
Peak memory 205568 kb
Host smart-e6dd36b8-3050-4656-8d9e-83e75327341e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584910833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.3584910833
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.1956955107
Short name T88
Test name
Test status
Simulation time 23659326 ps
CPU time 0.87 seconds
Started Dec 27 12:59:03 PM PST 23
Finished Dec 27 12:59:12 PM PST 23
Peak memory 214528 kb
Host smart-686618e3-61d5-44e5-9cae-a1755c46ba2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956955107 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.1956955107
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.3047984773
Short name T604
Test name
Test status
Simulation time 43134149 ps
CPU time 0.93 seconds
Started Dec 27 12:58:23 PM PST 23
Finished Dec 27 12:58:37 PM PST 23
Peak memory 204788 kb
Host smart-843ab278-f835-459f-a5de-cee560b16e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047984773 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.3047984773
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.3142292022
Short name T569
Test name
Test status
Simulation time 363147917 ps
CPU time 2.29 seconds
Started Dec 27 12:58:30 PM PST 23
Finished Dec 27 12:58:47 PM PST 23
Peak memory 205896 kb
Host smart-5f881dfe-16ea-4a9a-bbef-65a65f9f6fc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142292022 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.3142292022
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.3127918302
Short name T644
Test name
Test status
Simulation time 211697435601 ps
CPU time 2607.51 seconds
Started Dec 27 12:58:45 PM PST 23
Finished Dec 27 01:42:21 PM PST 23
Peak memory 226464 kb
Host smart-d732dc97-834c-40b3-ac13-23e3e275a702
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127918302 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.3127918302
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.177080649
Short name T263
Test name
Test status
Simulation time 18817703 ps
CPU time 0.97 seconds
Started Dec 27 12:58:56 PM PST 23
Finished Dec 27 12:59:03 PM PST 23
Peak memory 205068 kb
Host smart-3d23c520-48e9-4e31-bb34-e88ab9891835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177080649 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.177080649
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.334528204
Short name T459
Test name
Test status
Simulation time 27665696 ps
CPU time 0.93 seconds
Started Dec 27 12:58:30 PM PST 23
Finished Dec 27 12:58:40 PM PST 23
Peak memory 204624 kb
Host smart-2f17e9ce-29bc-4041-85d3-27741473ee3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334528204 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.334528204
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.864850897
Short name T116
Test name
Test status
Simulation time 16770055 ps
CPU time 0.79 seconds
Started Dec 27 12:58:28 PM PST 23
Finished Dec 27 12:58:39 PM PST 23
Peak memory 214264 kb
Host smart-7ca076ec-b84b-405c-a70e-168ac2d969b8
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864850897 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.864850897
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.4292134407
Short name T255
Test name
Test status
Simulation time 26558123 ps
CPU time 1.04 seconds
Started Dec 27 12:58:55 PM PST 23
Finished Dec 27 12:59:03 PM PST 23
Peak memory 214540 kb
Host smart-712ad4fc-71a2-4bca-a5a2-18f3f88ad7a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292134407 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.4292134407
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.3878460562
Short name T952
Test name
Test status
Simulation time 20587073 ps
CPU time 1.2 seconds
Started Dec 27 12:58:40 PM PST 23
Finished Dec 27 12:58:50 PM PST 23
Peak memory 221920 kb
Host smart-d4196d8b-710f-4277-b10f-68e96b871c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878460562 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.3878460562
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.2788815590
Short name T472
Test name
Test status
Simulation time 59523258 ps
CPU time 0.94 seconds
Started Dec 27 12:58:37 PM PST 23
Finished Dec 27 12:58:47 PM PST 23
Peak memory 205056 kb
Host smart-2f13d9f9-a633-4d3a-8464-6b45f4a96d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788815590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.2788815590
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.505406914
Short name T52
Test name
Test status
Simulation time 51270379 ps
CPU time 0.81 seconds
Started Dec 27 12:58:21 PM PST 23
Finished Dec 27 12:58:35 PM PST 23
Peak memory 214360 kb
Host smart-e43aae11-e5d1-45b3-99f9-6d739140aed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505406914 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.505406914
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.367568901
Short name T676
Test name
Test status
Simulation time 12399933 ps
CPU time 0.9 seconds
Started Dec 27 12:58:40 PM PST 23
Finished Dec 27 12:58:49 PM PST 23
Peak memory 204556 kb
Host smart-8838c899-569b-4977-8821-1a3059e80249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367568901 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.367568901
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.1193492879
Short name T941
Test name
Test status
Simulation time 315142789 ps
CPU time 3.94 seconds
Started Dec 27 12:58:51 PM PST 23
Finished Dec 27 12:59:02 PM PST 23
Peak memory 205924 kb
Host smart-bf90e13e-8e69-4ba6-ac56-a54c2151d407
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193492879 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1193492879
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.1563118027
Short name T96
Test name
Test status
Simulation time 6525965861 ps
CPU time 137.18 seconds
Started Dec 27 12:58:32 PM PST 23
Finished Dec 27 01:00:59 PM PST 23
Peak memory 214524 kb
Host smart-52c81f5f-e645-4eaa-af70-3ce2ad4ca5de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563118027 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.1563118027
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.2649467631
Short name T258
Test name
Test status
Simulation time 33659143 ps
CPU time 0.97 seconds
Started Dec 27 12:58:45 PM PST 23
Finished Dec 27 12:58:54 PM PST 23
Peak memory 205848 kb
Host smart-3257b2b0-cf0f-445f-bc54-227d9525277d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649467631 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.2649467631
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.596827027
Short name T498
Test name
Test status
Simulation time 41816920 ps
CPU time 0.84 seconds
Started Dec 27 12:58:56 PM PST 23
Finished Dec 27 12:59:03 PM PST 23
Peak memory 205096 kb
Host smart-6302892e-11b2-4b5d-a4a6-9206fdb80325
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596827027 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.596827027
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.1084331743
Short name T958
Test name
Test status
Simulation time 15755294 ps
CPU time 0.87 seconds
Started Dec 27 12:58:46 PM PST 23
Finished Dec 27 12:58:56 PM PST 23
Peak memory 214260 kb
Host smart-8ae878d6-5211-4e20-b523-3a7c9cd4f0ae
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084331743 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.1084331743
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.564431016
Short name T146
Test name
Test status
Simulation time 38695883 ps
CPU time 1 seconds
Started Dec 27 12:58:41 PM PST 23
Finished Dec 27 12:58:50 PM PST 23
Peak memory 214544 kb
Host smart-a1239568-84d3-4f47-9ef4-cac7f1ef666a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564431016 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_di
sable_auto_req_mode.564431016
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.2998066825
Short name T45
Test name
Test status
Simulation time 31016794 ps
CPU time 1 seconds
Started Dec 27 12:58:57 PM PST 23
Finished Dec 27 12:59:04 PM PST 23
Peak memory 221796 kb
Host smart-0f449041-5ab6-493e-a0de-142da9e84821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998066825 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.2998066825
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.3239498473
Short name T722
Test name
Test status
Simulation time 21153443 ps
CPU time 0.9 seconds
Started Dec 27 12:58:23 PM PST 23
Finished Dec 27 12:58:37 PM PST 23
Peak memory 205352 kb
Host smart-895ab189-c109-4dea-9eba-71dd63225198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239498473 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.3239498473
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.3312087527
Short name T841
Test name
Test status
Simulation time 19852175 ps
CPU time 1.01 seconds
Started Dec 27 12:59:13 PM PST 23
Finished Dec 27 12:59:25 PM PST 23
Peak memory 214436 kb
Host smart-7f5cb745-5454-4d4e-b0fb-86a5dab5a5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312087527 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.3312087527
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.740868077
Short name T594
Test name
Test status
Simulation time 32209760 ps
CPU time 0.83 seconds
Started Dec 27 12:58:45 PM PST 23
Finished Dec 27 12:58:54 PM PST 23
Peak memory 204780 kb
Host smart-67b35473-afeb-404f-867d-4a1e9549930d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740868077 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.740868077
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.1384184318
Short name T656
Test name
Test status
Simulation time 251737301 ps
CPU time 2.88 seconds
Started Dec 27 12:58:15 PM PST 23
Finished Dec 27 12:58:28 PM PST 23
Peak memory 205884 kb
Host smart-fbff8081-3491-49bb-af79-4236ebab576e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384184318 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.1384184318
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.3898884730
Short name T670
Test name
Test status
Simulation time 63038276986 ps
CPU time 1425.95 seconds
Started Dec 27 12:58:46 PM PST 23
Finished Dec 27 01:22:40 PM PST 23
Peak memory 215256 kb
Host smart-5a9997dc-4287-45af-aeb8-95bd411930e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898884730 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.3898884730
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.3426350788
Short name T293
Test name
Test status
Simulation time 32151312 ps
CPU time 0.94 seconds
Started Dec 27 12:58:46 PM PST 23
Finished Dec 27 12:58:55 PM PST 23
Peak memory 205868 kb
Host smart-54939edf-f053-44b2-8e39-b56cf02a28eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426350788 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.3426350788
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.4097734172
Short name T934
Test name
Test status
Simulation time 13138081 ps
CPU time 0.86 seconds
Started Dec 27 12:58:37 PM PST 23
Finished Dec 27 12:58:48 PM PST 23
Peak memory 204508 kb
Host smart-ac20e44c-9945-4995-aa12-ae4073368296
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097734172 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.4097734172
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.3679947696
Short name T165
Test name
Test status
Simulation time 48224101 ps
CPU time 0.93 seconds
Started Dec 27 12:58:45 PM PST 23
Finished Dec 27 12:58:55 PM PST 23
Peak memory 214204 kb
Host smart-398860be-1e45-4bc6-aa54-160699060ed0
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679947696 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.3679947696
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.1713929188
Short name T697
Test name
Test status
Simulation time 51722134 ps
CPU time 1.05 seconds
Started Dec 27 12:58:35 PM PST 23
Finished Dec 27 12:58:46 PM PST 23
Peak memory 214548 kb
Host smart-ddb36f87-3b87-4460-9fbd-caa48fbbd2e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713929188 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.1713929188
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.2822407797
Short name T951
Test name
Test status
Simulation time 54508626 ps
CPU time 1.62 seconds
Started Dec 27 12:58:31 PM PST 23
Finished Dec 27 12:58:41 PM PST 23
Peak memory 227576 kb
Host smart-13687f9a-f11b-4f15-8c00-e1c0f321a3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822407797 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.2822407797
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.1532202150
Short name T276
Test name
Test status
Simulation time 475455277 ps
CPU time 3.64 seconds
Started Dec 27 12:58:43 PM PST 23
Finished Dec 27 12:58:55 PM PST 23
Peak memory 214172 kb
Host smart-b696ee71-0ce9-4406-8c70-df0683b96f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532202150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.1532202150
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.126003246
Short name T907
Test name
Test status
Simulation time 20337142 ps
CPU time 0.92 seconds
Started Dec 27 12:58:57 PM PST 23
Finished Dec 27 12:59:04 PM PST 23
Peak memory 214528 kb
Host smart-f3943aca-19e6-4f35-97c8-df266247bb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126003246 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.126003246
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.700555664
Short name T3
Test name
Test status
Simulation time 100394402 ps
CPU time 0.8 seconds
Started Dec 27 12:58:49 PM PST 23
Finished Dec 27 12:58:58 PM PST 23
Peak memory 204628 kb
Host smart-d7776cd9-e59f-439b-a637-f6859251dd71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700555664 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.700555664
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.108937134
Short name T850
Test name
Test status
Simulation time 71639265 ps
CPU time 1.96 seconds
Started Dec 27 12:58:52 PM PST 23
Finished Dec 27 12:59:01 PM PST 23
Peak memory 205716 kb
Host smart-648e0d2b-2fca-4b29-988f-aa935322c735
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108937134 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.108937134
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.1027001806
Short name T851
Test name
Test status
Simulation time 738041142232 ps
CPU time 1638.16 seconds
Started Dec 27 12:58:31 PM PST 23
Finished Dec 27 01:25:58 PM PST 23
Peak memory 217420 kb
Host smart-8f592975-41dc-4749-9f08-535ec816908a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027001806 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.1027001806
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.3550265974
Short name T893
Test name
Test status
Simulation time 53050512 ps
CPU time 0.9 seconds
Started Dec 27 12:58:58 PM PST 23
Finished Dec 27 12:59:06 PM PST 23
Peak memory 205040 kb
Host smart-d2777fd0-9f8d-4c2d-95f9-aafab3a6a2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550265974 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.3550265974
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.2678526372
Short name T474
Test name
Test status
Simulation time 46053168 ps
CPU time 0.89 seconds
Started Dec 27 12:58:28 PM PST 23
Finished Dec 27 12:58:40 PM PST 23
Peak memory 205128 kb
Host smart-6ee57bf1-4075-4003-b2c4-85caed6ca92a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678526372 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.2678526372
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.4131774247
Short name T166
Test name
Test status
Simulation time 31456630 ps
CPU time 0.78 seconds
Started Dec 27 12:58:13 PM PST 23
Finished Dec 27 12:58:23 PM PST 23
Peak memory 214212 kb
Host smart-6fe0ab3c-1f75-4429-a13f-32e687dcf135
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131774247 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.4131774247
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.2392832646
Short name T143
Test name
Test status
Simulation time 126892051 ps
CPU time 1.06 seconds
Started Dec 27 12:58:39 PM PST 23
Finished Dec 27 12:58:48 PM PST 23
Peak memory 214400 kb
Host smart-619452be-8005-446d-8979-140e5db67afc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392832646 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.2392832646
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.2537980718
Short name T954
Test name
Test status
Simulation time 23166541 ps
CPU time 0.93 seconds
Started Dec 27 12:58:36 PM PST 23
Finished Dec 27 12:58:46 PM PST 23
Peak memory 215812 kb
Host smart-22c8da67-25cd-417b-8fbe-bf3beb3a7253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537980718 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.2537980718
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.2260381857
Short name T716
Test name
Test status
Simulation time 1007503672 ps
CPU time 6.74 seconds
Started Dec 27 12:58:47 PM PST 23
Finished Dec 27 12:59:02 PM PST 23
Peak memory 214012 kb
Host smart-0ef122b8-6bc5-4a4e-a1ad-d475ae55a31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260381857 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.2260381857
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.615361319
Short name T55
Test name
Test status
Simulation time 42801032 ps
CPU time 0.8 seconds
Started Dec 27 12:58:38 PM PST 23
Finished Dec 27 12:58:48 PM PST 23
Peak memory 214028 kb
Host smart-7f4717f1-0267-4a4c-ba50-1a41d55533d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615361319 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.615361319
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.3720335126
Short name T776
Test name
Test status
Simulation time 20825166 ps
CPU time 0.92 seconds
Started Dec 27 12:58:48 PM PST 23
Finished Dec 27 12:58:58 PM PST 23
Peak memory 204856 kb
Host smart-94280c9d-f998-47c5-8a10-eb3a28797fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720335126 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.3720335126
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.3546882216
Short name T516
Test name
Test status
Simulation time 164510369 ps
CPU time 2.8 seconds
Started Dec 27 12:58:21 PM PST 23
Finished Dec 27 12:58:37 PM PST 23
Peak memory 205944 kb
Host smart-cee055d5-36bb-4508-9b60-f3b0311f72d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546882216 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.3546882216
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.1132225999
Short name T743
Test name
Test status
Simulation time 41470872393 ps
CPU time 937.55 seconds
Started Dec 27 12:58:25 PM PST 23
Finished Dec 27 01:14:15 PM PST 23
Peak memory 215472 kb
Host smart-805ec4f9-f41d-4d32-b67d-854dc4061616
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132225999 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.1132225999
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.1637201851
Short name T844
Test name
Test status
Simulation time 18266163 ps
CPU time 0.96 seconds
Started Dec 27 12:58:54 PM PST 23
Finished Dec 27 12:59:02 PM PST 23
Peak memory 205128 kb
Host smart-a79494d0-2768-4416-9aa0-8234688b9ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637201851 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.1637201851
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.2305697961
Short name T757
Test name
Test status
Simulation time 64291923 ps
CPU time 0.9 seconds
Started Dec 27 12:58:29 PM PST 23
Finished Dec 27 12:58:40 PM PST 23
Peak memory 204628 kb
Host smart-6e6b5bba-3b3f-412f-ae7d-18c54f2feed1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305697961 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.2305697961
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.3795572289
Short name T913
Test name
Test status
Simulation time 42393286 ps
CPU time 0.85 seconds
Started Dec 27 12:58:42 PM PST 23
Finished Dec 27 12:58:50 PM PST 23
Peak memory 214356 kb
Host smart-648561e2-1da7-4535-be71-a88074232ab9
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795572289 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.3795572289
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.1949100475
Short name T660
Test name
Test status
Simulation time 119646173 ps
CPU time 0.97 seconds
Started Dec 27 12:58:14 PM PST 23
Finished Dec 27 12:58:25 PM PST 23
Peak memory 214500 kb
Host smart-85afb280-5687-4574-adae-5e352bdd2e83
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949100475 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.1949100475
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.2558356980
Short name T667
Test name
Test status
Simulation time 27526537 ps
CPU time 0.93 seconds
Started Dec 27 12:58:21 PM PST 23
Finished Dec 27 12:58:35 PM PST 23
Peak memory 215636 kb
Host smart-4b873621-ff46-47d3-9491-3ca3f9df1b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558356980 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.2558356980
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.1811358554
Short name T853
Test name
Test status
Simulation time 58524527 ps
CPU time 0.97 seconds
Started Dec 27 12:58:48 PM PST 23
Finished Dec 27 12:58:58 PM PST 23
Peak memory 204888 kb
Host smart-7fefab80-fedb-4a4e-a5d9-e2a3473c8c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811358554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.1811358554
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.3381214087
Short name T486
Test name
Test status
Simulation time 19928229 ps
CPU time 1.06 seconds
Started Dec 27 12:58:19 PM PST 23
Finished Dec 27 12:58:33 PM PST 23
Peak memory 214360 kb
Host smart-d07d2eff-31f7-4bb3-832e-e4f9cb332a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381214087 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.3381214087
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.261617563
Short name T487
Test name
Test status
Simulation time 15458024 ps
CPU time 0.93 seconds
Started Dec 27 12:58:56 PM PST 23
Finished Dec 27 12:59:04 PM PST 23
Peak memory 204800 kb
Host smart-aad571b9-1878-4d39-be30-75bdb1d94642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261617563 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.261617563
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.610294071
Short name T93
Test name
Test status
Simulation time 168684528 ps
CPU time 4.09 seconds
Started Dec 27 12:58:32 PM PST 23
Finished Dec 27 12:58:44 PM PST 23
Peak memory 205688 kb
Host smart-f1fea6dc-0cf9-4402-b6a3-2c6638b26c77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610294071 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.610294071
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1597803067
Short name T829
Test name
Test status
Simulation time 101750699602 ps
CPU time 1251.36 seconds
Started Dec 27 12:59:03 PM PST 23
Finished Dec 27 01:20:03 PM PST 23
Peak memory 219260 kb
Host smart-c200c67c-e0b5-4a89-a1d0-b54894f28dfd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597803067 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1597803067
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.893978696
Short name T301
Test name
Test status
Simulation time 18932655 ps
CPU time 0.97 seconds
Started Dec 27 12:57:43 PM PST 23
Finished Dec 27 12:57:46 PM PST 23
Peak memory 205104 kb
Host smart-8840ada2-d202-4289-8dcd-7f28c6118ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893978696 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.893978696
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.728801760
Short name T651
Test name
Test status
Simulation time 48188990 ps
CPU time 1.06 seconds
Started Dec 27 12:57:41 PM PST 23
Finished Dec 27 12:57:45 PM PST 23
Peak memory 205184 kb
Host smart-ca109bd7-7eeb-4086-8e98-af9f5fd97fd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728801760 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.728801760
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.3449680004
Short name T127
Test name
Test status
Simulation time 108931604 ps
CPU time 1.15 seconds
Started Dec 27 12:57:58 PM PST 23
Finished Dec 27 12:58:02 PM PST 23
Peak memory 214524 kb
Host smart-14b45fde-144f-453c-8e7b-0f8d03e3aaef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449680004 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.3449680004
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.3544868692
Short name T484
Test name
Test status
Simulation time 22351446 ps
CPU time 1.04 seconds
Started Dec 27 12:58:06 PM PST 23
Finished Dec 27 12:58:13 PM PST 23
Peak memory 215852 kb
Host smart-9d36a70d-c7eb-4df9-8d62-7f46872afe52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544868692 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.3544868692
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.396103300
Short name T712
Test name
Test status
Simulation time 21585680 ps
CPU time 0.92 seconds
Started Dec 27 12:57:57 PM PST 23
Finished Dec 27 12:58:00 PM PST 23
Peak memory 205456 kb
Host smart-ef4c4023-bbc8-415f-b2c7-31112b0a356a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396103300 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.396103300
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.1734340524
Short name T609
Test name
Test status
Simulation time 45695581 ps
CPU time 0.82 seconds
Started Dec 27 12:57:57 PM PST 23
Finished Dec 27 12:58:00 PM PST 23
Peak memory 214324 kb
Host smart-44f0a583-8fa2-435d-aede-d27ddd6ec114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734340524 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.1734340524
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.2163918620
Short name T299
Test name
Test status
Simulation time 15395358 ps
CPU time 0.89 seconds
Started Dec 27 12:57:55 PM PST 23
Finished Dec 27 12:57:58 PM PST 23
Peak memory 204756 kb
Host smart-8ffe2dd9-d156-4c13-b5f0-1d9fab8e4d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163918620 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.2163918620
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.1848678957
Short name T470
Test name
Test status
Simulation time 13289621 ps
CPU time 0.88 seconds
Started Dec 27 12:57:59 PM PST 23
Finished Dec 27 12:58:03 PM PST 23
Peak memory 204624 kb
Host smart-c068fc6a-70bc-4fc0-b2c2-d514c6e1de9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848678957 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.1848678957
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.2279159632
Short name T271
Test name
Test status
Simulation time 335762836 ps
CPU time 3.84 seconds
Started Dec 27 12:58:05 PM PST 23
Finished Dec 27 12:58:16 PM PST 23
Peak memory 205724 kb
Host smart-0bbaee93-b593-43c4-9f27-d557ba1c78b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279159632 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.2279159632
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.1315316781
Short name T603
Test name
Test status
Simulation time 64178649788 ps
CPU time 551.97 seconds
Started Dec 27 12:57:44 PM PST 23
Finished Dec 27 01:06:57 PM PST 23
Peak memory 215320 kb
Host smart-03f7e232-af31-4c7d-9ebc-5d3546d20589
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315316781 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.1315316781
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.3867169325
Short name T753
Test name
Test status
Simulation time 34528237 ps
CPU time 1.09 seconds
Started Dec 27 12:59:03 PM PST 23
Finished Dec 27 12:59:12 PM PST 23
Peak memory 215832 kb
Host smart-7968d731-c93d-4104-a9fb-c560861aafb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867169325 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.3867169325
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.1105679779
Short name T843
Test name
Test status
Simulation time 17644493 ps
CPU time 1.1 seconds
Started Dec 27 12:58:11 PM PST 23
Finished Dec 27 12:58:22 PM PST 23
Peak memory 205116 kb
Host smart-f22283da-3cd8-4a6b-b4dc-2cfcb9587550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105679779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.1105679779
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.1913798345
Short name T959
Test name
Test status
Simulation time 66258492 ps
CPU time 1.02 seconds
Started Dec 27 12:58:21 PM PST 23
Finished Dec 27 12:58:36 PM PST 23
Peak memory 216904 kb
Host smart-5fef4f9b-211b-4aa6-8a63-c7c77476ee72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913798345 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.1913798345
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.213707545
Short name T357
Test name
Test status
Simulation time 24534050 ps
CPU time 0.96 seconds
Started Dec 27 12:58:45 PM PST 23
Finished Dec 27 12:58:54 PM PST 23
Peak memory 205532 kb
Host smart-10134200-7fd1-4339-ac23-2b2e2384629b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213707545 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.213707545
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.4167253112
Short name T566
Test name
Test status
Simulation time 67125210 ps
CPU time 1.06 seconds
Started Dec 27 12:58:50 PM PST 23
Finished Dec 27 12:58:59 PM PST 23
Peak memory 214704 kb
Host smart-6a52821f-ad30-48e5-858f-effb85d3f954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167253112 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.4167253112
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.3225105691
Short name T715
Test name
Test status
Simulation time 151711963 ps
CPU time 0.92 seconds
Started Dec 27 12:58:21 PM PST 23
Finished Dec 27 12:58:35 PM PST 23
Peak memory 205052 kb
Host smart-74528246-9db2-4016-ae92-75aad04fff11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225105691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3225105691
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_genbits.2643140749
Short name T906
Test name
Test status
Simulation time 17252819 ps
CPU time 1.03 seconds
Started Dec 27 12:58:39 PM PST 23
Finished Dec 27 12:58:49 PM PST 23
Peak memory 214184 kb
Host smart-bbc0e433-78f5-4f7c-a705-0e2bf2463e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643140749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.2643140749
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.327725746
Short name T144
Test name
Test status
Simulation time 19996860 ps
CPU time 1.09 seconds
Started Dec 27 12:58:42 PM PST 23
Finished Dec 27 12:58:51 PM PST 23
Peak memory 214472 kb
Host smart-793d722f-54f5-40b6-a6d8-af9c75976f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327725746 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.327725746
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.271092198
Short name T838
Test name
Test status
Simulation time 26208632 ps
CPU time 1.41 seconds
Started Dec 27 12:58:22 PM PST 23
Finished Dec 27 12:58:37 PM PST 23
Peak memory 214104 kb
Host smart-6d358825-28dd-4609-9989-af054e47e4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271092198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.271092198
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.951815549
Short name T257
Test name
Test status
Simulation time 81083633 ps
CPU time 0.8 seconds
Started Dec 27 12:58:44 PM PST 23
Finished Dec 27 12:58:52 PM PST 23
Peak memory 215500 kb
Host smart-3bad3abb-5bf4-400a-8dba-92e0fa2d0c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951815549 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.951815549
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.826211
Short name T312
Test name
Test status
Simulation time 327210417 ps
CPU time 3.97 seconds
Started Dec 27 12:58:55 PM PST 23
Finished Dec 27 12:59:05 PM PST 23
Peak memory 213944 kb
Host smart-de757924-2262-4fcf-b5e0-577b3a7d9ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.826211
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.718327353
Short name T251
Test name
Test status
Simulation time 23109131 ps
CPU time 1.04 seconds
Started Dec 27 12:58:26 PM PST 23
Finished Dec 27 12:58:39 PM PST 23
Peak memory 228092 kb
Host smart-bae9ba23-2a32-4de2-9f4b-0f6895e989de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718327353 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.718327353
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.2807728563
Short name T10
Test name
Test status
Simulation time 158185491 ps
CPU time 2.56 seconds
Started Dec 27 12:58:34 PM PST 23
Finished Dec 27 12:58:47 PM PST 23
Peak memory 214180 kb
Host smart-b1994258-9de7-46f7-b7ee-702716a2ab48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807728563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.2807728563
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.3229188555
Short name T253
Test name
Test status
Simulation time 26012987 ps
CPU time 0.96 seconds
Started Dec 27 12:58:48 PM PST 23
Finished Dec 27 12:58:58 PM PST 23
Peak memory 214404 kb
Host smart-f53234a6-6dd4-4673-903f-1d40638e0bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229188555 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.3229188555
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.3293087301
Short name T339
Test name
Test status
Simulation time 17855214 ps
CPU time 1.11 seconds
Started Dec 27 12:58:37 PM PST 23
Finished Dec 27 12:58:48 PM PST 23
Peak memory 205176 kb
Host smart-5eb4f9d8-294e-4c25-b3bf-9829a3b3d805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293087301 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.3293087301
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.613151461
Short name T567
Test name
Test status
Simulation time 29714738 ps
CPU time 1.2 seconds
Started Dec 27 12:58:28 PM PST 23
Finished Dec 27 12:58:40 PM PST 23
Peak memory 214476 kb
Host smart-bbce17d1-5e73-4b26-95cd-2e29de464112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613151461 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.613151461
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.3960883106
Short name T818
Test name
Test status
Simulation time 44144635 ps
CPU time 0.92 seconds
Started Dec 27 12:58:22 PM PST 23
Finished Dec 27 12:58:37 PM PST 23
Peak memory 205496 kb
Host smart-09d37a3d-556c-4304-ae92-9374d1718edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960883106 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.3960883106
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.2357038319
Short name T882
Test name
Test status
Simulation time 40024114 ps
CPU time 1.04 seconds
Started Dec 27 12:58:21 PM PST 23
Finished Dec 27 12:58:36 PM PST 23
Peak memory 216100 kb
Host smart-24507a42-523e-4200-953e-17bcba8de900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357038319 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.2357038319
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.2112968573
Short name T506
Test name
Test status
Simulation time 18843341 ps
CPU time 0.97 seconds
Started Dec 27 12:58:42 PM PST 23
Finished Dec 27 12:58:51 PM PST 23
Peak memory 205540 kb
Host smart-47709c01-615c-46ff-bb2c-824982a45b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112968573 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.2112968573
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.685675489
Short name T690
Test name
Test status
Simulation time 35387331 ps
CPU time 0.97 seconds
Started Dec 27 12:57:45 PM PST 23
Finished Dec 27 12:57:47 PM PST 23
Peak memory 205164 kb
Host smart-38eaa945-b9e0-402f-ae13-46686fb76c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685675489 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.685675489
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.2459813630
Short name T538
Test name
Test status
Simulation time 35589633 ps
CPU time 0.98 seconds
Started Dec 27 12:57:52 PM PST 23
Finished Dec 27 12:57:54 PM PST 23
Peak memory 204552 kb
Host smart-d0423b0a-b0df-454f-b1cc-1e8924ec6510
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459813630 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.2459813630
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.3339199250
Short name T523
Test name
Test status
Simulation time 35401302 ps
CPU time 0.82 seconds
Started Dec 27 12:57:36 PM PST 23
Finished Dec 27 12:57:40 PM PST 23
Peak memory 214264 kb
Host smart-cea26f6b-1708-4a74-806c-14e8678354bd
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339199250 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.3339199250
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.4122369422
Short name T943
Test name
Test status
Simulation time 38224917 ps
CPU time 0.95 seconds
Started Dec 27 12:57:51 PM PST 23
Finished Dec 27 12:57:54 PM PST 23
Peak memory 214512 kb
Host smart-ae3e9bb8-b57d-4fbc-a33b-8be555997a7a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122369422 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.4122369422
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.1080451167
Short name T150
Test name
Test status
Simulation time 27411968 ps
CPU time 1 seconds
Started Dec 27 12:57:38 PM PST 23
Finished Dec 27 12:57:42 PM PST 23
Peak memory 221556 kb
Host smart-3a661136-a08e-4d3f-9735-85d2b1aa989b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080451167 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.1080451167
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.2328219834
Short name T866
Test name
Test status
Simulation time 30516471 ps
CPU time 0.88 seconds
Started Dec 27 12:57:40 PM PST 23
Finished Dec 27 12:57:43 PM PST 23
Peak memory 204936 kb
Host smart-0463a3b2-bd5a-4fe7-9bd0-33f56d7b713f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328219834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.2328219834
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.627164565
Short name T654
Test name
Test status
Simulation time 19582060 ps
CPU time 1.06 seconds
Started Dec 27 12:57:32 PM PST 23
Finished Dec 27 12:57:39 PM PST 23
Peak memory 214468 kb
Host smart-16e7064d-fdff-426f-9b20-ae85c214dc02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627164565 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.627164565
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_smoke.2476099475
Short name T860
Test name
Test status
Simulation time 29816978 ps
CPU time 0.89 seconds
Started Dec 27 12:57:54 PM PST 23
Finished Dec 27 12:57:56 PM PST 23
Peak memory 204884 kb
Host smart-895904f0-e45d-41f1-b419-8442de9a404f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476099475 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.2476099475
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.1776153225
Short name T909
Test name
Test status
Simulation time 201905198 ps
CPU time 2.46 seconds
Started Dec 27 12:57:34 PM PST 23
Finished Dec 27 12:57:41 PM PST 23
Peak memory 205476 kb
Host smart-2957aed5-b3d1-472e-9fbe-37521c50f09a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776153225 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.1776153225
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/60.edn_err.2181972873
Short name T632
Test name
Test status
Simulation time 32792059 ps
CPU time 0.88 seconds
Started Dec 27 12:58:59 PM PST 23
Finished Dec 27 12:59:08 PM PST 23
Peak memory 215552 kb
Host smart-7e677270-4fe9-4c20-9645-30635762dc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181972873 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.2181972873
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.3553710668
Short name T589
Test name
Test status
Simulation time 16440368 ps
CPU time 1 seconds
Started Dec 27 12:58:55 PM PST 23
Finished Dec 27 12:59:02 PM PST 23
Peak memory 205176 kb
Host smart-5ee2ab36-5755-45eb-8c4c-895ca70530d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553710668 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3553710668
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.2493289960
Short name T240
Test name
Test status
Simulation time 67818182 ps
CPU time 1.07 seconds
Started Dec 27 12:58:37 PM PST 23
Finished Dec 27 12:58:47 PM PST 23
Peak memory 217036 kb
Host smart-bb8d62e4-81af-484f-b9ad-4bfe6ef191cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493289960 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.2493289960
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.2248162138
Short name T920
Test name
Test status
Simulation time 106741112 ps
CPU time 0.92 seconds
Started Dec 27 12:58:55 PM PST 23
Finished Dec 27 12:59:02 PM PST 23
Peak memory 204860 kb
Host smart-09b7d90d-a161-43f6-bae4-90fee0f7efe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248162138 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.2248162138
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.1313884501
Short name T140
Test name
Test status
Simulation time 23561079 ps
CPU time 1.14 seconds
Started Dec 27 12:58:37 PM PST 23
Finished Dec 27 12:58:48 PM PST 23
Peak memory 214512 kb
Host smart-4d82a197-4df4-4ff2-adc7-a5ca16a3f43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313884501 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.1313884501
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.3006663504
Short name T595
Test name
Test status
Simulation time 62728620 ps
CPU time 1 seconds
Started Dec 27 12:58:27 PM PST 23
Finished Dec 27 12:58:40 PM PST 23
Peak memory 205412 kb
Host smart-8515d154-a288-4f27-aa4d-5bcecca2d92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006663504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.3006663504
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.1240681374
Short name T128
Test name
Test status
Simulation time 20583907 ps
CPU time 1.09 seconds
Started Dec 27 12:58:56 PM PST 23
Finished Dec 27 12:59:03 PM PST 23
Peak memory 214600 kb
Host smart-593901fc-25c7-4fc8-b6c4-c76898febb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240681374 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.1240681374
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.1320609255
Short name T348
Test name
Test status
Simulation time 28444248 ps
CPU time 0.93 seconds
Started Dec 27 12:58:46 PM PST 23
Finished Dec 27 12:58:55 PM PST 23
Peak memory 205520 kb
Host smart-b3aa83b5-a168-44a9-ba27-d94fcac4501d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320609255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.1320609255
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.2541337828
Short name T664
Test name
Test status
Simulation time 21873396 ps
CPU time 1 seconds
Started Dec 27 12:58:49 PM PST 23
Finished Dec 27 12:58:58 PM PST 23
Peak memory 221668 kb
Host smart-305187cd-f23b-4d8d-a200-3a4214c2d103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541337828 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.2541337828
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.814004281
Short name T284
Test name
Test status
Simulation time 40270699 ps
CPU time 1.15 seconds
Started Dec 27 12:58:43 PM PST 23
Finished Dec 27 12:58:52 PM PST 23
Peak memory 213984 kb
Host smart-4cb9cb70-eff6-42e5-9d77-f7a7c1d459ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814004281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.814004281
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.1103494507
Short name T252
Test name
Test status
Simulation time 72243151 ps
CPU time 1.03 seconds
Started Dec 27 12:58:48 PM PST 23
Finished Dec 27 12:58:58 PM PST 23
Peak memory 217048 kb
Host smart-eb4ee411-ee45-4bbe-843f-0fd8b5f6d4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103494507 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.1103494507
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.3595606446
Short name T337
Test name
Test status
Simulation time 31692113 ps
CPU time 1.11 seconds
Started Dec 27 12:58:33 PM PST 23
Finished Dec 27 12:58:44 PM PST 23
Peak memory 214044 kb
Host smart-60b51f4d-3b67-4a1c-b926-bf0325416904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595606446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.3595606446
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.549066365
Short name T467
Test name
Test status
Simulation time 28605031 ps
CPU time 1.22 seconds
Started Dec 27 12:59:05 PM PST 23
Finished Dec 27 12:59:15 PM PST 23
Peak memory 217024 kb
Host smart-6e09347e-64b2-49eb-9e70-c6cb1c0b4c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549066365 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.549066365
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.3607233128
Short name T359
Test name
Test status
Simulation time 133966931 ps
CPU time 0.97 seconds
Started Dec 27 12:58:40 PM PST 23
Finished Dec 27 12:58:49 PM PST 23
Peak memory 205616 kb
Host smart-ac6ff574-9966-4f91-9ea8-3bd68d99f8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607233128 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.3607233128
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.1491104450
Short name T44
Test name
Test status
Simulation time 19767233 ps
CPU time 1.14 seconds
Started Dec 27 12:58:54 PM PST 23
Finished Dec 27 12:59:02 PM PST 23
Peak memory 221760 kb
Host smart-50868640-6e59-4d4f-972a-c8bc142841a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491104450 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1491104450
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.2007214344
Short name T848
Test name
Test status
Simulation time 44925827 ps
CPU time 0.95 seconds
Started Dec 27 12:58:57 PM PST 23
Finished Dec 27 12:59:05 PM PST 23
Peak memory 204896 kb
Host smart-82ccaf14-aa07-43f2-aa41-89c5b0288038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007214344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.2007214344
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.1351468733
Short name T820
Test name
Test status
Simulation time 104210568 ps
CPU time 1.02 seconds
Started Dec 27 12:58:37 PM PST 23
Finished Dec 27 12:58:48 PM PST 23
Peak memory 216988 kb
Host smart-cc6303a8-321c-4336-8894-2fc0ed165061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351468733 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.1351468733
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.373794133
Short name T658
Test name
Test status
Simulation time 21399712 ps
CPU time 0.91 seconds
Started Dec 27 12:59:02 PM PST 23
Finished Dec 27 12:59:11 PM PST 23
Peak memory 214172 kb
Host smart-5e0cfcb9-6dc6-45ae-a441-40bfca251298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373794133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.373794133
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.3932956505
Short name T123
Test name
Test status
Simulation time 74504347 ps
CPU time 1.16 seconds
Started Dec 27 12:58:51 PM PST 23
Finished Dec 27 12:58:59 PM PST 23
Peak memory 227688 kb
Host smart-7a92623a-a41c-43d1-a2ad-7e4b194ae965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932956505 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.3932956505
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.228136504
Short name T861
Test name
Test status
Simulation time 16131953 ps
CPU time 0.98 seconds
Started Dec 27 12:58:40 PM PST 23
Finished Dec 27 12:58:50 PM PST 23
Peak memory 205532 kb
Host smart-0b33c7de-5639-49d1-84ac-16742da50990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228136504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.228136504
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.3266628126
Short name T513
Test name
Test status
Simulation time 32939771 ps
CPU time 0.98 seconds
Started Dec 27 12:58:04 PM PST 23
Finished Dec 27 12:58:13 PM PST 23
Peak memory 205092 kb
Host smart-5815a1ba-a6b8-45c3-aa9a-b3389d95fea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266628126 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.3266628126
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.131266027
Short name T553
Test name
Test status
Simulation time 43091787 ps
CPU time 0.86 seconds
Started Dec 27 12:58:09 PM PST 23
Finished Dec 27 12:58:18 PM PST 23
Peak memory 204512 kb
Host smart-ac31586d-b199-41dd-a165-59d2628b2810
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131266027 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.131266027
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.904808132
Short name T157
Test name
Test status
Simulation time 43988890 ps
CPU time 0.88 seconds
Started Dec 27 12:57:42 PM PST 23
Finished Dec 27 12:57:50 PM PST 23
Peak memory 214240 kb
Host smart-a1acc192-64c4-430f-95dd-9c768b864e24
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904808132 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.904808132
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.3684573407
Short name T142
Test name
Test status
Simulation time 216018064 ps
CPU time 1.09 seconds
Started Dec 27 12:58:08 PM PST 23
Finished Dec 27 12:58:16 PM PST 23
Peak memory 214500 kb
Host smart-d6d6a0f2-4007-4c22-b2ee-da0f1037371e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684573407 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.3684573407
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.3151955047
Short name T878
Test name
Test status
Simulation time 71359197 ps
CPU time 1.12 seconds
Started Dec 27 12:58:10 PM PST 23
Finished Dec 27 12:58:25 PM PST 23
Peak memory 221560 kb
Host smart-ea88a549-23a2-46a0-a917-1c725ff49cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151955047 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.3151955047
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.3892793107
Short name T758
Test name
Test status
Simulation time 171674687 ps
CPU time 0.91 seconds
Started Dec 27 12:57:56 PM PST 23
Finished Dec 27 12:57:59 PM PST 23
Peak memory 204840 kb
Host smart-4e86fd07-9fb1-4fa8-a219-5d17ef0c1f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892793107 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.3892793107
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.2865237454
Short name T938
Test name
Test status
Simulation time 22807640 ps
CPU time 0.92 seconds
Started Dec 27 12:58:03 PM PST 23
Finished Dec 27 12:58:11 PM PST 23
Peak memory 214528 kb
Host smart-de0d80f6-81ba-476f-b23a-51f9441d8d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865237454 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.2865237454
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.498427731
Short name T306
Test name
Test status
Simulation time 45101928 ps
CPU time 0.85 seconds
Started Dec 27 12:58:00 PM PST 23
Finished Dec 27 12:58:04 PM PST 23
Peak memory 204924 kb
Host smart-e09049f1-5de1-44cb-a5b9-409f2d38320e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498427731 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.498427731
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.2300514953
Short name T819
Test name
Test status
Simulation time 45129327 ps
CPU time 0.86 seconds
Started Dec 27 12:57:45 PM PST 23
Finished Dec 27 12:57:48 PM PST 23
Peak memory 204616 kb
Host smart-c53f0780-27fb-4fc1-b279-f1aebf70d8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300514953 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.2300514953
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.3379564024
Short name T505
Test name
Test status
Simulation time 179567478 ps
CPU time 3.82 seconds
Started Dec 27 12:57:48 PM PST 23
Finished Dec 27 12:57:53 PM PST 23
Peak memory 205956 kb
Host smart-8eada586-5f06-497f-974a-b58cecf1fff6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379564024 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.3379564024
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.3331746151
Short name T773
Test name
Test status
Simulation time 219839828354 ps
CPU time 1289.36 seconds
Started Dec 27 12:57:40 PM PST 23
Finished Dec 27 01:19:12 PM PST 23
Peak memory 216276 kb
Host smart-142b996c-aa58-4291-8c5f-ae11bcbaeb3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331746151 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.3331746151
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.880153859
Short name T551
Test name
Test status
Simulation time 46836192 ps
CPU time 0.94 seconds
Started Dec 27 12:58:42 PM PST 23
Finished Dec 27 12:58:50 PM PST 23
Peak memory 221588 kb
Host smart-d79ea504-66e0-45e1-af2f-3dba176cbb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880153859 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.880153859
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.1723583979
Short name T358
Test name
Test status
Simulation time 39562414 ps
CPU time 0.89 seconds
Started Dec 27 12:58:38 PM PST 23
Finished Dec 27 12:58:48 PM PST 23
Peak memory 205336 kb
Host smart-33577cc9-cba5-435e-9765-6e9c335fa9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723583979 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.1723583979
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.1315211165
Short name T633
Test name
Test status
Simulation time 153870908 ps
CPU time 1.11 seconds
Started Dec 27 12:58:37 PM PST 23
Finished Dec 27 12:58:48 PM PST 23
Peak memory 214648 kb
Host smart-e6bb1a39-a007-4c58-86a6-d48952b315cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315211165 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.1315211165
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.3441697167
Short name T502
Test name
Test status
Simulation time 56906749 ps
CPU time 0.91 seconds
Started Dec 27 12:58:55 PM PST 23
Finished Dec 27 12:59:02 PM PST 23
Peak memory 205024 kb
Host smart-aa2b5444-0598-412d-b3ae-4521bcce2072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441697167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.3441697167
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.392829351
Short name T141
Test name
Test status
Simulation time 138660051 ps
CPU time 1.05 seconds
Started Dec 27 12:59:07 PM PST 23
Finished Dec 27 12:59:18 PM PST 23
Peak memory 228500 kb
Host smart-7c30e7a9-f1a4-427d-9bf0-248955cdaa10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392829351 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.392829351
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.1440172550
Short name T792
Test name
Test status
Simulation time 68698977 ps
CPU time 2.31 seconds
Started Dec 27 12:58:48 PM PST 23
Finished Dec 27 12:58:59 PM PST 23
Peak memory 214088 kb
Host smart-b9c5dd75-38b0-414e-8dcc-744471cbbd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440172550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.1440172550
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.4103507632
Short name T66
Test name
Test status
Simulation time 31346015 ps
CPU time 1.01 seconds
Started Dec 27 12:59:05 PM PST 23
Finished Dec 27 12:59:15 PM PST 23
Peak memory 215652 kb
Host smart-f348e616-d2ec-4d10-bad5-7e801c7bb7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103507632 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.4103507632
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.1076614249
Short name T336
Test name
Test status
Simulation time 17953041 ps
CPU time 1.12 seconds
Started Dec 27 12:58:53 PM PST 23
Finished Dec 27 12:59:01 PM PST 23
Peak memory 205184 kb
Host smart-f54f7999-264d-4b2b-b51f-29d94ef4a8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076614249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1076614249
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.3304912184
Short name T764
Test name
Test status
Simulation time 21648416 ps
CPU time 1.08 seconds
Started Dec 27 12:58:47 PM PST 23
Finished Dec 27 12:58:56 PM PST 23
Peak memory 214936 kb
Host smart-c13f640f-90a1-46da-a526-dc3ef10de11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304912184 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.3304912184
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.3211640039
Short name T48
Test name
Test status
Simulation time 318216447 ps
CPU time 2.77 seconds
Started Dec 27 12:58:25 PM PST 23
Finished Dec 27 12:58:40 PM PST 23
Peak memory 214172 kb
Host smart-b29ea7cd-980c-47f6-b6a0-84eaac6e5b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211640039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.3211640039
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.4082819639
Short name T124
Test name
Test status
Simulation time 24222374 ps
CPU time 1.01 seconds
Started Dec 27 12:58:58 PM PST 23
Finished Dec 27 12:59:07 PM PST 23
Peak memory 228460 kb
Host smart-149356f6-6170-4fe6-8431-544f114e84ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082819639 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.4082819639
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.3492620504
Short name T966
Test name
Test status
Simulation time 25263506 ps
CPU time 0.95 seconds
Started Dec 27 12:58:40 PM PST 23
Finished Dec 27 12:58:49 PM PST 23
Peak memory 205240 kb
Host smart-fa68ab94-59b9-407b-a25b-ef7d221a4fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492620504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.3492620504
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.2005207123
Short name T479
Test name
Test status
Simulation time 24672495 ps
CPU time 0.92 seconds
Started Dec 27 12:58:56 PM PST 23
Finished Dec 27 12:59:09 PM PST 23
Peak memory 214472 kb
Host smart-562ecc6f-1e4c-41c1-9221-01d010045dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005207123 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.2005207123
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.3762310835
Short name T828
Test name
Test status
Simulation time 92862007 ps
CPU time 2.19 seconds
Started Dec 27 12:58:38 PM PST 23
Finished Dec 27 12:58:49 PM PST 23
Peak memory 214164 kb
Host smart-630a1705-ab9c-43c5-a4d1-52ace9a0bb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762310835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.3762310835
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.175428729
Short name T238
Test name
Test status
Simulation time 73543206 ps
CPU time 1.01 seconds
Started Dec 27 12:58:45 PM PST 23
Finished Dec 27 12:58:54 PM PST 23
Peak memory 216860 kb
Host smart-41a5e7e8-4fce-4fc2-9874-250a1a684eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175428729 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.175428729
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.465314870
Short name T462
Test name
Test status
Simulation time 35759847 ps
CPU time 1.06 seconds
Started Dec 27 12:58:45 PM PST 23
Finished Dec 27 12:58:54 PM PST 23
Peak memory 205228 kb
Host smart-a41fed45-1da9-4d35-9198-9c6cbc571750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465314870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.465314870
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.2219865902
Short name T164
Test name
Test status
Simulation time 19118473 ps
CPU time 1.07 seconds
Started Dec 27 12:58:47 PM PST 23
Finished Dec 27 12:58:57 PM PST 23
Peak memory 215744 kb
Host smart-3e392242-d8b3-425c-a047-07c0ce92abac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219865902 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.2219865902
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.4020347078
Short name T279
Test name
Test status
Simulation time 30891881 ps
CPU time 1.04 seconds
Started Dec 27 12:59:00 PM PST 23
Finished Dec 27 12:59:08 PM PST 23
Peak memory 214152 kb
Host smart-e3536929-701d-46c2-923d-926e47280f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020347078 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.4020347078
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.1536330673
Short name T889
Test name
Test status
Simulation time 18947896 ps
CPU time 1.22 seconds
Started Dec 27 12:58:35 PM PST 23
Finished Dec 27 12:58:46 PM PST 23
Peak memory 221632 kb
Host smart-2db458bd-8e28-4c74-adf3-631076c37193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536330673 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.1536330673
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.3338850210
Short name T550
Test name
Test status
Simulation time 58266632 ps
CPU time 1.6 seconds
Started Dec 27 12:59:04 PM PST 23
Finished Dec 27 12:59:14 PM PST 23
Peak memory 213976 kb
Host smart-ea2726a9-8c71-42ad-bd6b-6d2fc1061b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338850210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.3338850210
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.1029596634
Short name T298
Test name
Test status
Simulation time 19564000 ps
CPU time 0.99 seconds
Started Dec 27 12:57:55 PM PST 23
Finished Dec 27 12:57:57 PM PST 23
Peak memory 205532 kb
Host smart-53b5b182-cceb-4855-b8ef-ad88b2cb64d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029596634 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.1029596634
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.3891771108
Short name T732
Test name
Test status
Simulation time 15335624 ps
CPU time 0.85 seconds
Started Dec 27 12:58:08 PM PST 23
Finished Dec 27 12:58:16 PM PST 23
Peak memory 204560 kb
Host smart-73752fb7-f2b8-4897-9026-3538e9776a11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891771108 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.3891771108
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.2640542317
Short name T248
Test name
Test status
Simulation time 74818841 ps
CPU time 1.09 seconds
Started Dec 27 12:57:53 PM PST 23
Finished Dec 27 12:57:55 PM PST 23
Peak memory 214572 kb
Host smart-c353fa60-1847-4089-9daf-e1ed4c7e06e2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640542317 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.2640542317
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.733588392
Short name T512
Test name
Test status
Simulation time 23768387 ps
CPU time 0.95 seconds
Started Dec 27 12:58:12 PM PST 23
Finished Dec 27 12:58:22 PM PST 23
Peak memory 214476 kb
Host smart-c276c451-c338-44a6-a7c0-d74a6ade6b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733588392 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.733588392
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.1364130618
Short name T471
Test name
Test status
Simulation time 38403383 ps
CPU time 1.69 seconds
Started Dec 27 12:57:57 PM PST 23
Finished Dec 27 12:58:00 PM PST 23
Peak memory 214156 kb
Host smart-18426758-1de5-449d-9dec-10de919174a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364130618 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.1364130618
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.1091986653
Short name T961
Test name
Test status
Simulation time 19024164 ps
CPU time 1.13 seconds
Started Dec 27 12:57:43 PM PST 23
Finished Dec 27 12:57:46 PM PST 23
Peak memory 221836 kb
Host smart-9cf95225-9e8f-42f6-8981-5ed9186eddef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091986653 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.1091986653
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_smoke.3144240651
Short name T796
Test name
Test status
Simulation time 34009241 ps
CPU time 0.81 seconds
Started Dec 27 12:57:55 PM PST 23
Finished Dec 27 12:57:57 PM PST 23
Peak memory 204736 kb
Host smart-6b1a2ec9-bd88-4f4e-be49-9eac26479c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144240651 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.3144240651
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.1711279140
Short name T946
Test name
Test status
Simulation time 195239584 ps
CPU time 1.95 seconds
Started Dec 27 12:57:46 PM PST 23
Finished Dec 27 12:57:50 PM PST 23
Peak memory 205684 kb
Host smart-4587e2c4-4f3b-4abe-9f4b-c615582987d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711279140 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.1711279140
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.2943081528
Short name T92
Test name
Test status
Simulation time 18508968458 ps
CPU time 413.11 seconds
Started Dec 27 12:58:05 PM PST 23
Finished Dec 27 01:05:05 PM PST 23
Peak memory 214368 kb
Host smart-f2b83830-d362-4083-9ef6-d09526b4d4c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943081528 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.2943081528
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.3894861799
Short name T887
Test name
Test status
Simulation time 113677576 ps
CPU time 1.18 seconds
Started Dec 27 12:58:48 PM PST 23
Finished Dec 27 12:58:58 PM PST 23
Peak memory 227580 kb
Host smart-49cf7a01-86f0-4961-8482-0e11fe06d8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894861799 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.3894861799
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.3857915477
Short name T95
Test name
Test status
Simulation time 212916932 ps
CPU time 1.06 seconds
Started Dec 27 12:59:10 PM PST 23
Finished Dec 27 12:59:22 PM PST 23
Peak memory 205580 kb
Host smart-2105b4a8-76b8-4fed-9ab5-39ff74189e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857915477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.3857915477
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.1525300066
Short name T922
Test name
Test status
Simulation time 44146814 ps
CPU time 1.04 seconds
Started Dec 27 12:58:30 PM PST 23
Finished Dec 27 12:58:40 PM PST 23
Peak memory 217008 kb
Host smart-a9e4deb0-c97d-4f2b-832f-2364c2cca412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525300066 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.1525300066
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.3363721530
Short name T475
Test name
Test status
Simulation time 24641173 ps
CPU time 0.87 seconds
Started Dec 27 12:58:38 PM PST 23
Finished Dec 27 12:58:48 PM PST 23
Peak memory 205004 kb
Host smart-982de3cf-9120-49eb-9488-fadbf5e50bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363721530 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.3363721530
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.2761626314
Short name T791
Test name
Test status
Simulation time 71542317 ps
CPU time 1.14 seconds
Started Dec 27 12:58:51 PM PST 23
Finished Dec 27 12:58:59 PM PST 23
Peak memory 221732 kb
Host smart-add3140f-cc15-4741-af6e-34378833f98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761626314 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.2761626314
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.2634672041
Short name T575
Test name
Test status
Simulation time 76645251 ps
CPU time 1.09 seconds
Started Dec 27 12:58:47 PM PST 23
Finished Dec 27 12:58:57 PM PST 23
Peak memory 206016 kb
Host smart-2f7d4984-8d4a-4b50-b7d4-66a55b8d9b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634672041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.2634672041
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.4174364688
Short name T65
Test name
Test status
Simulation time 22473316 ps
CPU time 0.9 seconds
Started Dec 27 12:58:54 PM PST 23
Finished Dec 27 12:59:02 PM PST 23
Peak memory 215084 kb
Host smart-6b6a0ad9-a9fa-4c0c-920a-bb301c73aeef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174364688 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.4174364688
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.131909665
Short name T363
Test name
Test status
Simulation time 114931169 ps
CPU time 1.38 seconds
Started Dec 27 12:58:58 PM PST 23
Finished Dec 27 12:59:06 PM PST 23
Peak memory 214100 kb
Host smart-c252f8da-79aa-4c04-939c-c4b4adb2b4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131909665 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.131909665
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.1764883174
Short name T902
Test name
Test status
Simulation time 33615060 ps
CPU time 1.07 seconds
Started Dec 27 12:58:58 PM PST 23
Finished Dec 27 12:59:06 PM PST 23
Peak memory 221864 kb
Host smart-6003a7c2-3487-4680-b14a-981dd4a9de6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764883174 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.1764883174
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.3022894771
Short name T700
Test name
Test status
Simulation time 16919790 ps
CPU time 0.99 seconds
Started Dec 27 12:58:58 PM PST 23
Finished Dec 27 12:59:06 PM PST 23
Peak memory 205316 kb
Host smart-9c714b34-43fc-47ee-b0e2-93e172a515bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022894771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.3022894771
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.1549813095
Short name T9
Test name
Test status
Simulation time 69356968 ps
CPU time 0.98 seconds
Started Dec 27 12:59:11 PM PST 23
Finished Dec 27 12:59:22 PM PST 23
Peak memory 215948 kb
Host smart-c3c6cd9c-71b3-48c7-8f63-017f5fcc1dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549813095 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.1549813095
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.3593700742
Short name T930
Test name
Test status
Simulation time 17240383 ps
CPU time 0.97 seconds
Started Dec 27 12:59:05 PM PST 23
Finished Dec 27 12:59:15 PM PST 23
Peak memory 204936 kb
Host smart-3045bd93-4f79-47ba-91cc-2e05d3956ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593700742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.3593700742
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.3124798560
Short name T809
Test name
Test status
Simulation time 20024070 ps
CPU time 1.14 seconds
Started Dec 27 12:58:53 PM PST 23
Finished Dec 27 12:59:01 PM PST 23
Peak memory 228116 kb
Host smart-bb4f17f1-5073-4389-a3b3-4491056fb180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124798560 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.3124798560
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.25422248
Short name T815
Test name
Test status
Simulation time 157685248 ps
CPU time 2.68 seconds
Started Dec 27 12:59:12 PM PST 23
Finished Dec 27 12:59:25 PM PST 23
Peak memory 214192 kb
Host smart-76083d62-4965-4eb8-a46e-4be295ff8526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25422248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.25422248
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.3365867972
Short name T859
Test name
Test status
Simulation time 22257852 ps
CPU time 1.15 seconds
Started Dec 27 12:59:19 PM PST 23
Finished Dec 27 12:59:31 PM PST 23
Peak memory 221588 kb
Host smart-05058c0f-b5bb-437f-b4de-d6db9f669418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365867972 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.3365867972
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.139051443
Short name T684
Test name
Test status
Simulation time 26328020 ps
CPU time 0.99 seconds
Started Dec 27 12:59:14 PM PST 23
Finished Dec 27 12:59:25 PM PST 23
Peak memory 205232 kb
Host smart-f268cde6-2bff-4585-b71d-86013e025d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139051443 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.139051443
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.3418478178
Short name T570
Test name
Test status
Simulation time 22920945 ps
CPU time 0.94 seconds
Started Dec 27 12:58:55 PM PST 23
Finished Dec 27 12:59:02 PM PST 23
Peak memory 216020 kb
Host smart-82af1e87-7e20-407a-ae54-850e47e9e351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418478178 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.3418478178
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.2865639651
Short name T597
Test name
Test status
Simulation time 64280833 ps
CPU time 0.96 seconds
Started Dec 27 12:58:59 PM PST 23
Finished Dec 27 12:59:07 PM PST 23
Peak memory 204792 kb
Host smart-06fb2d21-f368-470d-bf43-4d19a75cfe96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865639651 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.2865639651
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.488435465
Short name T825
Test name
Test status
Simulation time 28973119 ps
CPU time 1.19 seconds
Started Dec 27 12:59:06 PM PST 23
Finished Dec 27 12:59:22 PM PST 23
Peak memory 216908 kb
Host smart-7e59c128-a1c6-4a72-a391-245a8d767a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488435465 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.488435465
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.3973625687
Short name T332
Test name
Test status
Simulation time 21877906 ps
CPU time 1.13 seconds
Started Dec 27 12:58:57 PM PST 23
Finished Dec 27 12:59:05 PM PST 23
Peak memory 214076 kb
Host smart-d007a747-157d-4cdb-9773-52931373a120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973625687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.3973625687
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.3962354073
Short name T296
Test name
Test status
Simulation time 21725288 ps
CPU time 0.97 seconds
Started Dec 27 12:58:01 PM PST 23
Finished Dec 27 12:58:07 PM PST 23
Peak memory 205108 kb
Host smart-bc42a31a-bac8-4550-bd29-f2a4a6a57cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962354073 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.3962354073
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.389787713
Short name T692
Test name
Test status
Simulation time 21276145 ps
CPU time 1 seconds
Started Dec 27 12:57:48 PM PST 23
Finished Dec 27 12:57:50 PM PST 23
Peak memory 204688 kb
Host smart-f9e5c4a0-06cc-4904-81a6-2014272fbb7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389787713 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.389787713
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.1065573849
Short name T7
Test name
Test status
Simulation time 83599356 ps
CPU time 0.87 seconds
Started Dec 27 12:57:38 PM PST 23
Finished Dec 27 12:57:42 PM PST 23
Peak memory 214368 kb
Host smart-7a1070e4-83e8-426b-957c-247d18769811
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065573849 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.1065573849
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_err.2258047278
Short name T46
Test name
Test status
Simulation time 36713616 ps
CPU time 0.9 seconds
Started Dec 27 12:57:40 PM PST 23
Finished Dec 27 12:57:44 PM PST 23
Peak memory 221000 kb
Host smart-89c8f2b3-6fd5-4744-bfc2-1d181f6066d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258047278 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.2258047278
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.2630512765
Short name T749
Test name
Test status
Simulation time 74505443 ps
CPU time 0.93 seconds
Started Dec 27 12:57:43 PM PST 23
Finished Dec 27 12:57:46 PM PST 23
Peak memory 205016 kb
Host smart-b9c5df98-bd57-42c2-ac8e-d37f951d3dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630512765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.2630512765
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.983728655
Short name T84
Test name
Test status
Simulation time 58022613 ps
CPU time 0.79 seconds
Started Dec 27 12:58:02 PM PST 23
Finished Dec 27 12:58:10 PM PST 23
Peak memory 214340 kb
Host smart-10e2d26c-7d56-4f68-8498-3c28c1f1d31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983728655 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.983728655
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_smoke.1604592484
Short name T490
Test name
Test status
Simulation time 15148850 ps
CPU time 0.94 seconds
Started Dec 27 12:57:38 PM PST 23
Finished Dec 27 12:57:42 PM PST 23
Peak memory 204852 kb
Host smart-242979b3-ab3a-4834-bf8c-8d1579d42a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604592484 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.1604592484
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.2378954119
Short name T556
Test name
Test status
Simulation time 32044987 ps
CPU time 1.14 seconds
Started Dec 27 12:57:55 PM PST 23
Finished Dec 27 12:57:58 PM PST 23
Peak memory 204912 kb
Host smart-acc4615a-910a-40f8-bcac-e33250a8d7ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378954119 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.2378954119
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.658743500
Short name T586
Test name
Test status
Simulation time 72127253230 ps
CPU time 1597.94 seconds
Started Dec 27 12:58:04 PM PST 23
Finished Dec 27 01:24:50 PM PST 23
Peak memory 218400 kb
Host smart-c6588c22-548e-47be-9dd4-b23c0f3e8b96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658743500 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.658743500
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.2090427104
Short name T16
Test name
Test status
Simulation time 32531886 ps
CPU time 0.95 seconds
Started Dec 27 12:58:59 PM PST 23
Finished Dec 27 12:59:07 PM PST 23
Peak memory 221580 kb
Host smart-f11a152d-2226-4e40-9031-8d50124808e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090427104 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.2090427104
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.2873994614
Short name T899
Test name
Test status
Simulation time 25311749 ps
CPU time 1.12 seconds
Started Dec 27 12:59:01 PM PST 23
Finished Dec 27 12:59:09 PM PST 23
Peak memory 205304 kb
Host smart-c5f325d6-c13c-4105-b5b4-5f9cedc39de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873994614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.2873994614
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.2183976163
Short name T47
Test name
Test status
Simulation time 29953466 ps
CPU time 1.29 seconds
Started Dec 27 12:58:57 PM PST 23
Finished Dec 27 12:59:05 PM PST 23
Peak memory 221724 kb
Host smart-8290d86b-4344-4075-b86f-7a1cfc536c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183976163 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.2183976163
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.3815334352
Short name T929
Test name
Test status
Simulation time 16103646 ps
CPU time 0.93 seconds
Started Dec 27 12:58:59 PM PST 23
Finished Dec 27 12:59:08 PM PST 23
Peak memory 204996 kb
Host smart-cee227c6-6bb7-459c-a881-73d4e68499d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815334352 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.3815334352
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.3123469334
Short name T163
Test name
Test status
Simulation time 19116516 ps
CPU time 1.1 seconds
Started Dec 27 12:58:54 PM PST 23
Finished Dec 27 12:59:01 PM PST 23
Peak memory 221792 kb
Host smart-762ba26c-38da-41e1-9699-68308b8642b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123469334 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.3123469334
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.2865094903
Short name T650
Test name
Test status
Simulation time 94316837 ps
CPU time 2.88 seconds
Started Dec 27 12:58:54 PM PST 23
Finished Dec 27 12:59:04 PM PST 23
Peak memory 213908 kb
Host smart-448f1469-e090-4f25-9ef3-fb49eeb37a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865094903 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.2865094903
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.2117472085
Short name T696
Test name
Test status
Simulation time 28396211 ps
CPU time 0.94 seconds
Started Dec 27 12:59:02 PM PST 23
Finished Dec 27 12:59:12 PM PST 23
Peak memory 216008 kb
Host smart-bcbd825e-4199-4e84-9b9f-eb319c1ac740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117472085 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.2117472085
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.2687899997
Short name T543
Test name
Test status
Simulation time 20103920 ps
CPU time 1.04 seconds
Started Dec 27 12:59:01 PM PST 23
Finished Dec 27 12:59:10 PM PST 23
Peak memory 205164 kb
Host smart-55192cc8-9259-4f5d-afe3-10c94b541d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687899997 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.2687899997
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.1979823123
Short name T250
Test name
Test status
Simulation time 37227681 ps
CPU time 0.96 seconds
Started Dec 27 12:59:00 PM PST 23
Finished Dec 27 12:59:08 PM PST 23
Peak memory 227880 kb
Host smart-43bd7d08-c4ce-4fdc-ba18-a1d3fb382a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979823123 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.1979823123
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.1081438234
Short name T910
Test name
Test status
Simulation time 56340236 ps
CPU time 1.08 seconds
Started Dec 27 12:59:16 PM PST 23
Finished Dec 27 12:59:28 PM PST 23
Peak memory 205516 kb
Host smart-6cedf126-df2f-4fc3-82d1-9c2f8d8dd0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081438234 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.1081438234
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.2998563080
Short name T721
Test name
Test status
Simulation time 23430487 ps
CPU time 1.05 seconds
Started Dec 27 12:59:03 PM PST 23
Finished Dec 27 12:59:12 PM PST 23
Peak memory 221676 kb
Host smart-8ea8d9c8-315d-493a-81ea-d5c34c39b472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998563080 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.2998563080
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.4117332009
Short name T918
Test name
Test status
Simulation time 16729456 ps
CPU time 1.16 seconds
Started Dec 27 12:58:53 PM PST 23
Finished Dec 27 12:59:01 PM PST 23
Peak memory 205132 kb
Host smart-ea2b2d24-8c0b-4f94-a3f7-7ec11436b756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117332009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.4117332009
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.3132521552
Short name T6
Test name
Test status
Simulation time 23620575 ps
CPU time 1.4 seconds
Started Dec 27 12:58:56 PM PST 23
Finished Dec 27 12:59:03 PM PST 23
Peak memory 215904 kb
Host smart-9f0f4bc6-bc3f-4a8f-aea6-2b04f3f98a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132521552 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.3132521552
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.2899744265
Short name T322
Test name
Test status
Simulation time 73269700 ps
CPU time 0.96 seconds
Started Dec 27 12:58:50 PM PST 23
Finished Dec 27 12:58:59 PM PST 23
Peak memory 205056 kb
Host smart-e626a6b4-c07d-4dde-b79c-983bb7b98279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899744265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.2899744265
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.686319483
Short name T129
Test name
Test status
Simulation time 42318466 ps
CPU time 0.96 seconds
Started Dec 27 12:58:56 PM PST 23
Finished Dec 27 12:59:03 PM PST 23
Peak memory 214588 kb
Host smart-f856e606-c1a0-4dc3-9d20-afac94e4d992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686319483 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.686319483
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.3087261896
Short name T361
Test name
Test status
Simulation time 51961303 ps
CPU time 0.89 seconds
Started Dec 27 12:59:07 PM PST 23
Finished Dec 27 12:59:18 PM PST 23
Peak memory 204928 kb
Host smart-b535dd6f-2867-41fc-852a-1c98733afdde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087261896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.3087261896
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.1886417498
Short name T8
Test name
Test status
Simulation time 24530708 ps
CPU time 1.22 seconds
Started Dec 27 12:59:13 PM PST 23
Finished Dec 27 12:59:25 PM PST 23
Peak memory 228388 kb
Host smart-cff4e787-729e-4759-8074-3645b3714c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886417498 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.1886417498
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.1584228540
Short name T709
Test name
Test status
Simulation time 46851147 ps
CPU time 0.9 seconds
Started Dec 27 12:59:12 PM PST 23
Finished Dec 27 12:59:23 PM PST 23
Peak memory 204696 kb
Host smart-4147deae-1835-46a1-8311-ac9286df92b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584228540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.1584228540
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.218012634
Short name T249
Test name
Test status
Simulation time 42558110 ps
CPU time 1.11 seconds
Started Dec 27 12:59:11 PM PST 23
Finished Dec 27 12:59:22 PM PST 23
Peak memory 217076 kb
Host smart-df1ec133-0c26-4ff1-9094-6ead7f46f9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218012634 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.218012634
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.1913725856
Short name T466
Test name
Test status
Simulation time 38702866 ps
CPU time 0.95 seconds
Started Dec 27 12:59:00 PM PST 23
Finished Dec 27 12:59:09 PM PST 23
Peak memory 205072 kb
Host smart-fac24cc5-e8d4-4620-b962-8d4eb4db5bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913725856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.1913725856
Directory /workspace/99.edn_genbits/latest
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