Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.09 99.02 92.32 96.84 94.08 98.62 99.77 99.00


Total test records in report: 975
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T773 /workspace/coverage/default/19.edn_alert.4172932012 Dec 31 12:52:53 PM PST 23 Dec 31 12:52:55 PM PST 23 20267693 ps
T268 /workspace/coverage/default/42.edn_err.1339722661 Dec 31 12:53:33 PM PST 23 Dec 31 12:53:46 PM PST 23 20097005 ps
T774 /workspace/coverage/default/4.edn_disable.2789087705 Dec 31 12:52:10 PM PST 23 Dec 31 12:52:26 PM PST 23 18269080 ps
T775 /workspace/coverage/default/255.edn_genbits.477028330 Dec 31 12:54:52 PM PST 23 Dec 31 12:54:58 PM PST 23 72177203 ps
T776 /workspace/coverage/default/11.edn_alert.1421833710 Dec 31 12:52:15 PM PST 23 Dec 31 12:52:30 PM PST 23 21093036 ps
T777 /workspace/coverage/default/68.edn_genbits.1411474489 Dec 31 12:53:41 PM PST 23 Dec 31 12:53:53 PM PST 23 24068838 ps
T778 /workspace/coverage/default/2.edn_disable_auto_req_mode.2841757441 Dec 31 12:52:07 PM PST 23 Dec 31 12:52:20 PM PST 23 154195040 ps
T193 /workspace/coverage/default/34.edn_disable_auto_req_mode.1403951691 Dec 31 12:53:46 PM PST 23 Dec 31 12:54:00 PM PST 23 96817961 ps
T779 /workspace/coverage/default/11.edn_stress_all.1326040295 Dec 31 12:52:21 PM PST 23 Dec 31 12:52:35 PM PST 23 172381248 ps
T780 /workspace/coverage/default/251.edn_genbits.3248466426 Dec 31 12:54:37 PM PST 23 Dec 31 12:54:41 PM PST 23 57129921 ps
T781 /workspace/coverage/default/6.edn_smoke.1515593296 Dec 31 12:52:19 PM PST 23 Dec 31 12:52:34 PM PST 23 44940463 ps
T65 /workspace/coverage/default/3.edn_sec_cm.618725901 Dec 31 12:52:06 PM PST 23 Dec 31 12:52:23 PM PST 23 2178380243 ps
T782 /workspace/coverage/default/43.edn_err.2701671108 Dec 31 12:53:33 PM PST 23 Dec 31 12:53:46 PM PST 23 27275309 ps
T783 /workspace/coverage/default/110.edn_genbits.963295682 Dec 31 12:53:59 PM PST 23 Dec 31 12:54:10 PM PST 23 22231320 ps
T784 /workspace/coverage/default/14.edn_stress_all.2424695136 Dec 31 12:52:28 PM PST 23 Dec 31 12:52:41 PM PST 23 553235529 ps
T785 /workspace/coverage/default/27.edn_stress_all.3112347838 Dec 31 12:53:09 PM PST 23 Dec 31 12:53:21 PM PST 23 269987605 ps
T786 /workspace/coverage/default/38.edn_disable_auto_req_mode.969305519 Dec 31 12:53:33 PM PST 23 Dec 31 12:53:46 PM PST 23 111798771 ps
T787 /workspace/coverage/default/160.edn_genbits.1942663499 Dec 31 12:54:36 PM PST 23 Dec 31 12:54:38 PM PST 23 64456080 ps
T788 /workspace/coverage/default/45.edn_alert_test.2471176978 Dec 31 12:53:33 PM PST 23 Dec 31 12:53:46 PM PST 23 17947042 ps
T129 /workspace/coverage/default/22.edn_disable.4097598628 Dec 31 12:52:59 PM PST 23 Dec 31 12:53:03 PM PST 23 12584563 ps
T134 /workspace/coverage/default/27.edn_disable.2194923520 Dec 31 12:53:23 PM PST 23 Dec 31 12:53:37 PM PST 23 29539797 ps
T789 /workspace/coverage/default/204.edn_genbits.3060897943 Dec 31 12:54:29 PM PST 23 Dec 31 12:54:32 PM PST 23 58628877 ps
T790 /workspace/coverage/default/6.edn_err.1013214330 Dec 31 12:52:06 PM PST 23 Dec 31 12:52:20 PM PST 23 18119709 ps
T791 /workspace/coverage/default/167.edn_genbits.2396255924 Dec 31 12:54:54 PM PST 23 Dec 31 12:55:00 PM PST 23 35444553 ps
T792 /workspace/coverage/default/112.edn_genbits.273284255 Dec 31 12:53:49 PM PST 23 Dec 31 12:54:02 PM PST 23 29843319 ps
T793 /workspace/coverage/default/15.edn_disable_auto_req_mode.2979440421 Dec 31 12:52:33 PM PST 23 Dec 31 12:52:42 PM PST 23 71250613 ps
T794 /workspace/coverage/default/5.edn_err.489947005 Dec 31 12:52:12 PM PST 23 Dec 31 12:52:29 PM PST 23 170879704 ps
T226 /workspace/coverage/default/0.edn_err.2229242000 Dec 31 12:52:01 PM PST 23 Dec 31 12:52:10 PM PST 23 20211869 ps
T795 /workspace/coverage/default/22.edn_stress_all.1926576967 Dec 31 12:53:20 PM PST 23 Dec 31 12:53:38 PM PST 23 131598260 ps
T213 /workspace/coverage/default/55.edn_err.3586721528 Dec 31 12:54:32 PM PST 23 Dec 31 12:54:34 PM PST 23 19485893 ps
T796 /workspace/coverage/default/14.edn_err.2955826506 Dec 31 12:52:29 PM PST 23 Dec 31 12:52:40 PM PST 23 31614026 ps
T797 /workspace/coverage/default/21.edn_err.481214205 Dec 31 12:53:10 PM PST 23 Dec 31 12:53:21 PM PST 23 115397548 ps
T798 /workspace/coverage/default/132.edn_genbits.1448169718 Dec 31 12:55:07 PM PST 23 Dec 31 12:55:13 PM PST 23 13782327 ps
T342 /workspace/coverage/default/0.edn_regwen.2571497095 Dec 31 12:52:08 PM PST 23 Dec 31 12:52:23 PM PST 23 15443579 ps
T799 /workspace/coverage/default/2.edn_smoke.3591823010 Dec 31 12:52:10 PM PST 23 Dec 31 12:52:26 PM PST 23 15149071 ps
T800 /workspace/coverage/default/121.edn_genbits.692714747 Dec 31 12:54:43 PM PST 23 Dec 31 12:54:46 PM PST 23 68562800 ps
T801 /workspace/coverage/default/27.edn_genbits.3650515403 Dec 31 12:53:08 PM PST 23 Dec 31 12:53:19 PM PST 23 82708422 ps
T802 /workspace/coverage/default/13.edn_alert.1404634323 Dec 31 12:52:30 PM PST 23 Dec 31 12:52:40 PM PST 23 58939366 ps
T803 /workspace/coverage/default/35.edn_stress_all.820401773 Dec 31 12:53:36 PM PST 23 Dec 31 12:53:51 PM PST 23 67095776 ps
T804 /workspace/coverage/default/37.edn_err.2722877761 Dec 31 12:54:24 PM PST 23 Dec 31 12:54:26 PM PST 23 36743580 ps
T805 /workspace/coverage/default/138.edn_genbits.2433460230 Dec 31 12:54:20 PM PST 23 Dec 31 12:54:25 PM PST 23 276355914 ps
T806 /workspace/coverage/default/13.edn_disable.555091765 Dec 31 12:52:23 PM PST 23 Dec 31 12:52:35 PM PST 23 32846313 ps
T371 /workspace/coverage/default/150.edn_genbits.1758454577 Dec 31 12:54:45 PM PST 23 Dec 31 12:54:48 PM PST 23 39367820 ps
T807 /workspace/coverage/default/25.edn_smoke.2739101423 Dec 31 12:52:58 PM PST 23 Dec 31 12:53:02 PM PST 23 41951625 ps
T210 /workspace/coverage/default/9.edn_err.1637735014 Dec 31 12:52:19 PM PST 23 Dec 31 12:52:34 PM PST 23 28488062 ps
T808 /workspace/coverage/default/174.edn_genbits.2017415249 Dec 31 12:54:44 PM PST 23 Dec 31 12:54:47 PM PST 23 69292586 ps
T809 /workspace/coverage/default/202.edn_genbits.978857798 Dec 31 12:54:35 PM PST 23 Dec 31 12:54:38 PM PST 23 18343550 ps
T810 /workspace/coverage/default/73.edn_genbits.524157811 Dec 31 12:53:53 PM PST 23 Dec 31 12:54:05 PM PST 23 19332095 ps
T811 /workspace/coverage/default/297.edn_genbits.2424820806 Dec 31 12:54:35 PM PST 23 Dec 31 12:54:38 PM PST 23 25614537 ps
T812 /workspace/coverage/default/211.edn_genbits.225656379 Dec 31 12:54:30 PM PST 23 Dec 31 12:54:33 PM PST 23 106811723 ps
T813 /workspace/coverage/default/12.edn_genbits.3210702488 Dec 31 12:52:19 PM PST 23 Dec 31 12:52:33 PM PST 23 41511954 ps
T266 /workspace/coverage/default/79.edn_err.3212322284 Dec 31 12:54:21 PM PST 23 Dec 31 12:54:23 PM PST 23 21705378 ps
T814 /workspace/coverage/default/56.edn_err.2943459999 Dec 31 12:54:52 PM PST 23 Dec 31 12:54:58 PM PST 23 28262462 ps
T815 /workspace/coverage/default/6.edn_alert_test.445711838 Dec 31 12:52:10 PM PST 23 Dec 31 12:52:26 PM PST 23 90093185 ps
T346 /workspace/coverage/default/12.edn_alert.3599899794 Dec 31 12:52:31 PM PST 23 Dec 31 12:52:41 PM PST 23 37196077 ps
T816 /workspace/coverage/default/8.edn_regwen.424541647 Dec 31 12:52:11 PM PST 23 Dec 31 12:52:26 PM PST 23 11589992 ps
T817 /workspace/coverage/default/25.edn_disable.1035860586 Dec 31 12:53:40 PM PST 23 Dec 31 12:53:53 PM PST 23 34862100 ps
T818 /workspace/coverage/default/99.edn_genbits.3089700485 Dec 31 12:53:54 PM PST 23 Dec 31 12:54:06 PM PST 23 16499930 ps
T819 /workspace/coverage/default/10.edn_stress_all.1891555405 Dec 31 12:52:09 PM PST 23 Dec 31 12:52:25 PM PST 23 155306870 ps
T820 /workspace/coverage/default/28.edn_stress_all_with_rand_reset.138149221 Dec 31 12:53:05 PM PST 23 Dec 31 01:05:44 PM PST 23 31278199747 ps
T821 /workspace/coverage/default/90.edn_err.3082354563 Dec 31 12:54:27 PM PST 23 Dec 31 12:54:29 PM PST 23 56262022 ps
T822 /workspace/coverage/default/63.edn_genbits.3169335157 Dec 31 12:53:57 PM PST 23 Dec 31 12:54:08 PM PST 23 17945403 ps
T823 /workspace/coverage/default/264.edn_genbits.680375480 Dec 31 12:54:47 PM PST 23 Dec 31 12:54:53 PM PST 23 68154941 ps
T824 /workspace/coverage/default/18.edn_stress_all.585172765 Dec 31 12:52:30 PM PST 23 Dec 31 12:52:43 PM PST 23 322422147 ps
T825 /workspace/coverage/default/257.edn_genbits.1210475071 Dec 31 12:54:56 PM PST 23 Dec 31 12:55:04 PM PST 23 410143812 ps
T826 /workspace/coverage/default/4.edn_alert_test.1836165780 Dec 31 12:52:18 PM PST 23 Dec 31 12:52:32 PM PST 23 11451767 ps
T827 /workspace/coverage/default/32.edn_stress_all.2452580796 Dec 31 12:53:40 PM PST 23 Dec 31 12:53:55 PM PST 23 120363181 ps
T828 /workspace/coverage/default/73.edn_err.2723949539 Dec 31 12:53:48 PM PST 23 Dec 31 12:54:01 PM PST 23 67986724 ps
T829 /workspace/coverage/default/43.edn_intr.2684382943 Dec 31 12:53:58 PM PST 23 Dec 31 12:54:08 PM PST 23 48035395 ps
T830 /workspace/coverage/default/7.edn_disable.3568413867 Dec 31 12:52:12 PM PST 23 Dec 31 12:52:28 PM PST 23 12346347 ps
T831 /workspace/coverage/default/10.edn_smoke.1500415651 Dec 31 12:52:10 PM PST 23 Dec 31 12:52:26 PM PST 23 12558758 ps
T299 /workspace/coverage/default/258.edn_genbits.1928136246 Dec 31 12:54:53 PM PST 23 Dec 31 12:54:58 PM PST 23 53810748 ps
T832 /workspace/coverage/default/26.edn_smoke.3695558859 Dec 31 12:53:32 PM PST 23 Dec 31 12:53:45 PM PST 23 45811685 ps
T833 /workspace/coverage/default/41.edn_stress_all_with_rand_reset.1871854689 Dec 31 12:53:43 PM PST 23 Dec 31 01:26:30 PM PST 23 154900505761 ps
T98 /workspace/coverage/default/32.edn_intr.3730195478 Dec 31 12:53:28 PM PST 23 Dec 31 12:53:41 PM PST 23 32752694 ps
T834 /workspace/coverage/default/123.edn_genbits.601124356 Dec 31 12:53:49 PM PST 23 Dec 31 12:54:02 PM PST 23 29400699 ps
T835 /workspace/coverage/default/0.edn_intr.750355769 Dec 31 12:52:12 PM PST 23 Dec 31 12:52:28 PM PST 23 17405560 ps
T836 /workspace/coverage/default/111.edn_genbits.3102491045 Dec 31 12:54:03 PM PST 23 Dec 31 12:54:12 PM PST 23 11911850 ps
T344 /workspace/coverage/default/10.edn_alert.1728332229 Dec 31 12:52:13 PM PST 23 Dec 31 12:52:29 PM PST 23 62391633 ps
T837 /workspace/coverage/default/291.edn_genbits.4112588009 Dec 31 12:54:34 PM PST 23 Dec 31 12:54:37 PM PST 23 51659224 ps
T838 /workspace/coverage/default/55.edn_genbits.4221685539 Dec 31 12:54:09 PM PST 23 Dec 31 12:54:15 PM PST 23 15739800 ps
T839 /workspace/coverage/default/18.edn_err.961017207 Dec 31 12:53:05 PM PST 23 Dec 31 12:53:19 PM PST 23 140954331 ps
T840 /workspace/coverage/default/4.edn_smoke.3419942576 Dec 31 12:52:07 PM PST 23 Dec 31 12:52:22 PM PST 23 15068742 ps
T841 /workspace/coverage/default/46.edn_genbits.1660188243 Dec 31 12:53:45 PM PST 23 Dec 31 12:53:59 PM PST 23 77779547 ps
T842 /workspace/coverage/default/4.edn_disable_auto_req_mode.336760097 Dec 31 12:52:10 PM PST 23 Dec 31 12:52:26 PM PST 23 24687948 ps
T190 /workspace/coverage/default/44.edn_err.3400611472 Dec 31 12:53:44 PM PST 23 Dec 31 12:53:58 PM PST 23 29916982 ps
T843 /workspace/coverage/default/256.edn_genbits.1194211506 Dec 31 12:54:25 PM PST 23 Dec 31 12:54:28 PM PST 23 18298748 ps
T844 /workspace/coverage/default/97.edn_err.1842114792 Dec 31 12:54:18 PM PST 23 Dec 31 12:54:21 PM PST 23 41369809 ps
T845 /workspace/coverage/default/26.edn_alert_test.3853286155 Dec 31 12:53:47 PM PST 23 Dec 31 12:54:00 PM PST 23 27637531 ps
T846 /workspace/coverage/default/29.edn_alert_test.2901209325 Dec 31 12:53:14 PM PST 23 Dec 31 12:53:33 PM PST 23 16291676 ps
T847 /workspace/coverage/default/2.edn_stress_all_with_rand_reset.3802603093 Dec 31 12:52:10 PM PST 23 Dec 31 01:13:20 PM PST 23 57500784790 ps
T848 /workspace/coverage/default/31.edn_stress_all.2764420183 Dec 31 12:53:14 PM PST 23 Dec 31 12:53:34 PM PST 23 2613292118 ps
T849 /workspace/coverage/default/22.edn_err.739569528 Dec 31 12:53:08 PM PST 23 Dec 31 12:53:19 PM PST 23 61591582 ps
T850 /workspace/coverage/default/25.edn_stress_all.1595628268 Dec 31 12:53:15 PM PST 23 Dec 31 12:53:34 PM PST 23 499395366 ps
T851 /workspace/coverage/default/17.edn_intr.1885876595 Dec 31 12:52:39 PM PST 23 Dec 31 12:52:46 PM PST 23 81523472 ps
T852 /workspace/coverage/default/4.edn_stress_all.678065368 Dec 31 12:52:10 PM PST 23 Dec 31 12:52:26 PM PST 23 284923136 ps
T853 /workspace/coverage/default/7.edn_smoke.1582064851 Dec 31 12:52:08 PM PST 23 Dec 31 12:52:22 PM PST 23 23719444 ps
T854 /workspace/coverage/default/25.edn_alert_test.37646574 Dec 31 12:53:26 PM PST 23 Dec 31 12:53:40 PM PST 23 56308457 ps
T855 /workspace/coverage/default/46.edn_err.589055527 Dec 31 12:53:57 PM PST 23 Dec 31 12:54:08 PM PST 23 30732876 ps
T856 /workspace/coverage/default/18.edn_stress_all_with_rand_reset.3638614831 Dec 31 12:52:28 PM PST 23 Dec 31 01:05:16 PM PST 23 45131662081 ps
T857 /workspace/coverage/default/64.edn_genbits.1575968999 Dec 31 12:53:44 PM PST 23 Dec 31 12:53:57 PM PST 23 47220809 ps
T858 /workspace/coverage/default/33.edn_err.3676140156 Dec 31 12:53:39 PM PST 23 Dec 31 12:53:52 PM PST 23 35693315 ps
T859 /workspace/coverage/default/90.edn_genbits.1700731382 Dec 31 12:54:45 PM PST 23 Dec 31 12:54:51 PM PST 23 240462754 ps
T860 /workspace/coverage/default/25.edn_alert.793485897 Dec 31 12:53:11 PM PST 23 Dec 31 12:53:32 PM PST 23 119218688 ps
T861 /workspace/coverage/default/10.edn_alert_test.3528627924 Dec 31 12:52:30 PM PST 23 Dec 31 12:52:40 PM PST 23 14176869 ps
T862 /workspace/coverage/default/14.edn_alert_test.1781548293 Dec 31 12:52:26 PM PST 23 Dec 31 12:52:37 PM PST 23 18340859 ps
T863 /workspace/coverage/default/87.edn_genbits.3836618808 Dec 31 12:53:45 PM PST 23 Dec 31 12:53:59 PM PST 23 47720103 ps
T864 /workspace/coverage/default/45.edn_stress_all.435397083 Dec 31 12:53:45 PM PST 23 Dec 31 12:54:02 PM PST 23 400546741 ps
T865 /workspace/coverage/default/3.edn_intr.627298734 Dec 31 12:52:10 PM PST 23 Dec 31 12:52:26 PM PST 23 23093636 ps
T866 /workspace/coverage/default/224.edn_genbits.2112383321 Dec 31 12:54:11 PM PST 23 Dec 31 12:54:16 PM PST 23 67391504 ps
T867 /workspace/coverage/default/34.edn_alert_test.215607646 Dec 31 12:53:43 PM PST 23 Dec 31 12:53:57 PM PST 23 14097741 ps
T868 /workspace/coverage/default/7.edn_disable_auto_req_mode.306581371 Dec 31 12:52:09 PM PST 23 Dec 31 12:52:24 PM PST 23 59893438 ps
T869 /workspace/coverage/default/8.edn_genbits.827696899 Dec 31 12:52:12 PM PST 23 Dec 31 12:52:28 PM PST 23 32037841 ps
T870 /workspace/coverage/default/31.edn_disable_auto_req_mode.2434813377 Dec 31 12:53:29 PM PST 23 Dec 31 12:53:42 PM PST 23 217336198 ps
T871 /workspace/coverage/default/136.edn_genbits.3980490052 Dec 31 12:54:27 PM PST 23 Dec 31 12:54:30 PM PST 23 19449228 ps
T872 /workspace/coverage/default/219.edn_genbits.2396491367 Dec 31 12:54:41 PM PST 23 Dec 31 12:54:44 PM PST 23 33352046 ps
T873 /workspace/coverage/default/23.edn_smoke.1444986235 Dec 31 12:53:12 PM PST 23 Dec 31 12:53:28 PM PST 23 137590540 ps
T874 /workspace/coverage/default/65.edn_genbits.3953545629 Dec 31 12:53:42 PM PST 23 Dec 31 12:53:55 PM PST 23 39948802 ps
T875 /workspace/coverage/default/196.edn_genbits.1581111350 Dec 31 12:54:10 PM PST 23 Dec 31 12:54:15 PM PST 23 127715402 ps
T876 /workspace/coverage/default/42.edn_disable.4193312139 Dec 31 12:54:13 PM PST 23 Dec 31 12:54:17 PM PST 23 16098135 ps
T877 /workspace/coverage/default/5.edn_intr.1463064212 Dec 31 12:52:19 PM PST 23 Dec 31 12:52:34 PM PST 23 36246191 ps
T878 /workspace/coverage/default/181.edn_genbits.1854910407 Dec 31 12:54:45 PM PST 23 Dec 31 12:54:49 PM PST 23 114523874 ps
T879 /workspace/coverage/default/170.edn_genbits.3754760705 Dec 31 12:54:00 PM PST 23 Dec 31 12:54:11 PM PST 23 72613727 ps
T880 /workspace/coverage/default/180.edn_genbits.1883963486 Dec 31 12:53:51 PM PST 23 Dec 31 12:54:03 PM PST 23 47142518 ps
T881 /workspace/coverage/default/209.edn_genbits.2246777624 Dec 31 12:54:12 PM PST 23 Dec 31 12:54:16 PM PST 23 16055582 ps
T882 /workspace/coverage/default/25.edn_intr.922621346 Dec 31 12:53:13 PM PST 23 Dec 31 12:53:31 PM PST 23 28935744 ps
T883 /workspace/coverage/default/33.edn_disable_auto_req_mode.415753840 Dec 31 12:53:17 PM PST 23 Dec 31 12:53:35 PM PST 23 98944743 ps
T884 /workspace/coverage/default/273.edn_genbits.1393379154 Dec 31 12:54:40 PM PST 23 Dec 31 12:54:43 PM PST 23 26314930 ps
T885 /workspace/coverage/default/250.edn_genbits.380713539 Dec 31 12:54:47 PM PST 23 Dec 31 12:54:52 PM PST 23 58619817 ps
T886 /workspace/coverage/default/11.edn_intr.241742108 Dec 31 12:52:13 PM PST 23 Dec 31 12:52:29 PM PST 23 26036410 ps
T887 /workspace/coverage/default/12.edn_disable_auto_req_mode.1536780805 Dec 31 12:52:24 PM PST 23 Dec 31 12:52:36 PM PST 23 51874836 ps
T888 /workspace/coverage/default/65.edn_err.2714428935 Dec 31 12:53:42 PM PST 23 Dec 31 12:53:54 PM PST 23 18450091 ps
T889 /workspace/coverage/default/40.edn_intr.78744626 Dec 31 12:53:37 PM PST 23 Dec 31 12:53:51 PM PST 23 38630012 ps
T890 /workspace/coverage/default/46.edn_disable.421348496 Dec 31 12:53:37 PM PST 23 Dec 31 12:53:51 PM PST 23 42077764 ps
T891 /workspace/coverage/default/21.edn_smoke.1322685184 Dec 31 12:52:53 PM PST 23 Dec 31 12:52:56 PM PST 23 41014893 ps
T892 /workspace/coverage/default/62.edn_genbits.2003588154 Dec 31 12:54:12 PM PST 23 Dec 31 12:54:16 PM PST 23 87692003 ps
T198 /workspace/coverage/default/74.edn_err.769722876 Dec 31 12:53:56 PM PST 23 Dec 31 12:54:07 PM PST 23 34555240 ps
T893 /workspace/coverage/default/24.edn_alert_test.2855748988 Dec 31 12:53:06 PM PST 23 Dec 31 12:53:18 PM PST 23 11039082 ps
T894 /workspace/coverage/default/220.edn_genbits.3431123228 Dec 31 12:54:10 PM PST 23 Dec 31 12:54:15 PM PST 23 41422009 ps
T895 /workspace/coverage/default/36.edn_stress_all_with_rand_reset.1766037726 Dec 31 12:53:48 PM PST 23 Dec 31 01:12:31 PM PST 23 497098545294 ps
T896 /workspace/coverage/default/189.edn_genbits.2964008143 Dec 31 12:54:29 PM PST 23 Dec 31 12:54:32 PM PST 23 21260513 ps
T897 /workspace/coverage/default/254.edn_genbits.1510659482 Dec 31 12:54:08 PM PST 23 Dec 31 12:54:14 PM PST 23 18765513 ps
T179 /workspace/coverage/default/81.edn_err.1797105578 Dec 31 12:53:55 PM PST 23 Dec 31 12:54:07 PM PST 23 21489304 ps
T898 /workspace/coverage/default/9.edn_regwen.380460025 Dec 31 12:52:10 PM PST 23 Dec 31 12:52:25 PM PST 23 13098738 ps
T899 /workspace/coverage/default/29.edn_stress_all_with_rand_reset.2778765867 Dec 31 12:53:38 PM PST 23 Dec 31 01:06:28 PM PST 23 136569679009 ps
T900 /workspace/coverage/default/45.edn_disable_auto_req_mode.3215524026 Dec 31 12:53:36 PM PST 23 Dec 31 12:53:50 PM PST 23 59718304 ps
T901 /workspace/coverage/default/44.edn_stress_all.3488235796 Dec 31 12:53:50 PM PST 23 Dec 31 12:54:06 PM PST 23 686833167 ps
T902 /workspace/coverage/default/13.edn_disable_auto_req_mode.718375760 Dec 31 12:52:33 PM PST 23 Dec 31 12:52:43 PM PST 23 17646671 ps
T903 /workspace/coverage/default/22.edn_alert_test.3834689841 Dec 31 12:53:02 PM PST 23 Dec 31 12:53:15 PM PST 23 15630551 ps
T351 /workspace/coverage/default/42.edn_alert.3318799314 Dec 31 12:53:22 PM PST 23 Dec 31 12:53:37 PM PST 23 18846833 ps
T904 /workspace/coverage/default/18.edn_intr.3099457041 Dec 31 12:52:31 PM PST 23 Dec 31 12:52:41 PM PST 23 18486979 ps
T905 /workspace/coverage/default/5.edn_smoke.319157778 Dec 31 12:52:15 PM PST 23 Dec 31 12:52:31 PM PST 23 56343769 ps
T906 /workspace/coverage/default/20.edn_alert.2019517370 Dec 31 12:53:05 PM PST 23 Dec 31 12:53:18 PM PST 23 18616297 ps
T907 /workspace/coverage/default/133.edn_genbits.2472471974 Dec 31 12:53:48 PM PST 23 Dec 31 12:54:01 PM PST 23 36214705 ps
T307 /workspace/coverage/default/231.edn_genbits.1458324253 Dec 31 12:54:09 PM PST 23 Dec 31 12:54:15 PM PST 23 37599451 ps
T908 /workspace/coverage/default/47.edn_disable.2265394770 Dec 31 12:54:09 PM PST 23 Dec 31 12:54:15 PM PST 23 13247982 ps
T909 /workspace/coverage/default/49.edn_genbits.1867236182 Dec 31 12:54:01 PM PST 23 Dec 31 12:54:12 PM PST 23 21170809 ps
T910 /workspace/coverage/default/44.edn_stress_all_with_rand_reset.1053071946 Dec 31 12:53:34 PM PST 23 Dec 31 01:18:23 PM PST 23 61056233726 ps
T911 /workspace/coverage/default/28.edn_disable.3183600453 Dec 31 12:53:20 PM PST 23 Dec 31 12:53:36 PM PST 23 17782484 ps
T912 /workspace/coverage/default/62.edn_err.2599412795 Dec 31 12:53:46 PM PST 23 Dec 31 12:54:00 PM PST 23 18267769 ps
T913 /workspace/coverage/default/15.edn_stress_all_with_rand_reset.2071716641 Dec 31 12:52:27 PM PST 23 Dec 31 01:03:52 PM PST 23 124415176658 ps
T914 /workspace/coverage/default/24.edn_alert.3145310012 Dec 31 12:53:11 PM PST 23 Dec 31 12:53:22 PM PST 23 21976560 ps
T915 /workspace/coverage/default/36.edn_smoke.899093832 Dec 31 12:53:57 PM PST 23 Dec 31 12:54:08 PM PST 23 14910619 ps
T916 /workspace/coverage/default/39.edn_genbits.678949156 Dec 31 12:53:47 PM PST 23 Dec 31 12:54:01 PM PST 23 12327249 ps
T917 /workspace/coverage/default/9.edn_stress_all.814040785 Dec 31 12:52:13 PM PST 23 Dec 31 12:52:31 PM PST 23 325300211 ps
T918 /workspace/coverage/default/154.edn_genbits.4045432164 Dec 31 12:53:51 PM PST 23 Dec 31 12:54:04 PM PST 23 17482702 ps
T919 /workspace/coverage/default/103.edn_genbits.1331894009 Dec 31 12:53:35 PM PST 23 Dec 31 12:53:49 PM PST 23 66522383 ps
T920 /workspace/coverage/default/35.edn_alert_test.3804322883 Dec 31 12:53:38 PM PST 23 Dec 31 12:53:51 PM PST 23 39293345 ps
T921 /workspace/coverage/default/40.edn_stress_all.3594942658 Dec 31 12:53:41 PM PST 23 Dec 31 12:53:57 PM PST 23 267441529 ps
T922 /workspace/coverage/default/46.edn_stress_all_with_rand_reset.3875755119 Dec 31 12:54:03 PM PST 23 Dec 31 01:24:41 PM PST 23 1164844027845 ps
T923 /workspace/coverage/default/7.edn_alert_test.3389810454 Dec 31 12:52:14 PM PST 23 Dec 31 12:52:29 PM PST 23 39337393 ps
T924 /workspace/coverage/default/157.edn_genbits.3107481357 Dec 31 12:54:41 PM PST 23 Dec 31 12:54:44 PM PST 23 28056450 ps
T925 /workspace/coverage/default/6.edn_stress_all.1531223040 Dec 31 12:52:07 PM PST 23 Dec 31 12:52:25 PM PST 23 644215795 ps
T926 /workspace/coverage/default/49.edn_alert_test.1118269788 Dec 31 12:53:33 PM PST 23 Dec 31 12:53:46 PM PST 23 24406380 ps
T927 /workspace/coverage/default/217.edn_genbits.2459814880 Dec 31 12:54:27 PM PST 23 Dec 31 12:54:30 PM PST 23 62932878 ps
T343 /workspace/coverage/default/1.edn_regwen.1750930954 Dec 31 12:52:07 PM PST 23 Dec 31 12:52:22 PM PST 23 13633904 ps
T928 /workspace/coverage/default/4.edn_intr.1736215252 Dec 31 12:52:13 PM PST 23 Dec 31 12:52:29 PM PST 23 19441073 ps
T929 /workspace/coverage/default/126.edn_genbits.3077544540 Dec 31 12:54:43 PM PST 23 Dec 31 12:54:49 PM PST 23 131078227 ps
T930 /workspace/coverage/default/39.edn_disable_auto_req_mode.135354006 Dec 31 12:53:52 PM PST 23 Dec 31 12:54:04 PM PST 23 296149277 ps
T931 /workspace/coverage/default/194.edn_genbits.1381667981 Dec 31 12:54:31 PM PST 23 Dec 31 12:54:34 PM PST 23 59544565 ps
T932 /workspace/coverage/default/5.edn_disable.2564435940 Dec 31 12:52:11 PM PST 23 Dec 31 12:52:27 PM PST 23 50970873 ps
T933 /workspace/coverage/default/159.edn_genbits.1090619866 Dec 31 12:54:00 PM PST 23 Dec 31 12:54:13 PM PST 23 136476106 ps
T934 /workspace/coverage/default/172.edn_genbits.3946208649 Dec 31 12:54:24 PM PST 23 Dec 31 12:54:31 PM PST 23 64119618 ps
T935 /workspace/coverage/default/23.edn_alert_test.1258346362 Dec 31 12:53:21 PM PST 23 Dec 31 12:53:36 PM PST 23 15917518 ps
T936 /workspace/coverage/default/185.edn_genbits.3042160162 Dec 31 12:53:53 PM PST 23 Dec 31 12:54:04 PM PST 23 88660917 ps
T937 /workspace/coverage/default/43.edn_alert.2660386540 Dec 31 12:53:48 PM PST 23 Dec 31 12:54:02 PM PST 23 19453374 ps
T938 /workspace/coverage/default/35.edn_genbits.3192195484 Dec 31 12:53:43 PM PST 23 Dec 31 12:53:55 PM PST 23 22978800 ps
T939 /workspace/coverage/default/11.edn_genbits.3454625634 Dec 31 12:52:23 PM PST 23 Dec 31 12:52:36 PM PST 23 36481655 ps
T940 /workspace/coverage/default/86.edn_err.2151139986 Dec 31 12:53:48 PM PST 23 Dec 31 12:54:01 PM PST 23 22936962 ps
T941 /workspace/coverage/default/38.edn_alert_test.3508972816 Dec 31 12:54:00 PM PST 23 Dec 31 12:54:13 PM PST 23 137793173 ps
T942 /workspace/coverage/default/188.edn_genbits.3403235142 Dec 31 12:54:09 PM PST 23 Dec 31 12:54:15 PM PST 23 43121209 ps
T943 /workspace/coverage/default/16.edn_disable_auto_req_mode.2031614570 Dec 31 12:52:35 PM PST 23 Dec 31 12:52:44 PM PST 23 46460796 ps
T944 /workspace/coverage/default/7.edn_err.3733292651 Dec 31 12:52:09 PM PST 23 Dec 31 12:52:24 PM PST 23 68351475 ps
T945 /workspace/coverage/default/75.edn_err.2880144081 Dec 31 12:54:05 PM PST 23 Dec 31 12:54:13 PM PST 23 23302786 ps
T946 /workspace/coverage/default/16.edn_disable.850000981 Dec 31 12:52:35 PM PST 23 Dec 31 12:52:44 PM PST 23 17421807 ps
T947 /workspace/coverage/default/119.edn_genbits.2684838044 Dec 31 12:54:44 PM PST 23 Dec 31 12:54:49 PM PST 23 150018233 ps
T948 /workspace/coverage/default/271.edn_genbits.1340121708 Dec 31 12:55:00 PM PST 23 Dec 31 12:55:07 PM PST 23 19592356 ps
T949 /workspace/coverage/default/197.edn_genbits.4233787995 Dec 31 12:54:12 PM PST 23 Dec 31 12:54:17 PM PST 23 73625234 ps
T950 /workspace/coverage/default/60.edn_genbits.2446413903 Dec 31 12:54:34 PM PST 23 Dec 31 12:54:37 PM PST 23 22037942 ps
T951 /workspace/coverage/default/15.edn_smoke.736327128 Dec 31 12:52:23 PM PST 23 Dec 31 12:52:36 PM PST 23 39851479 ps
T952 /workspace/coverage/default/16.edn_genbits.1486900931 Dec 31 12:52:34 PM PST 23 Dec 31 12:52:43 PM PST 23 52488224 ps
T953 /workspace/coverage/default/22.edn_genbits.2714378501 Dec 31 12:53:07 PM PST 23 Dec 31 12:53:18 PM PST 23 42036804 ps
T954 /workspace/coverage/default/156.edn_genbits.2398730661 Dec 31 12:53:58 PM PST 23 Dec 31 12:54:09 PM PST 23 89844043 ps
T955 /workspace/coverage/default/26.edn_genbits.1305140013 Dec 31 12:53:43 PM PST 23 Dec 31 12:53:56 PM PST 23 18522228 ps
T956 /workspace/coverage/default/215.edn_genbits.3273760612 Dec 31 12:54:17 PM PST 23 Dec 31 12:54:20 PM PST 23 90083892 ps
T957 /workspace/coverage/default/245.edn_genbits.1482009710 Dec 31 12:54:39 PM PST 23 Dec 31 12:54:42 PM PST 23 28211582 ps
T958 /workspace/coverage/default/32.edn_disable_auto_req_mode.4200717964 Dec 31 12:53:36 PM PST 23 Dec 31 12:53:50 PM PST 23 43711348 ps
T959 /workspace/coverage/default/45.edn_err.844697860 Dec 31 12:53:35 PM PST 23 Dec 31 12:53:49 PM PST 23 36710324 ps
T960 /workspace/coverage/default/295.edn_genbits.748054440 Dec 31 12:54:45 PM PST 23 Dec 31 12:54:49 PM PST 23 18320043 ps
T961 /workspace/coverage/default/97.edn_genbits.1490765959 Dec 31 12:54:14 PM PST 23 Dec 31 12:54:18 PM PST 23 20258087 ps
T962 /workspace/coverage/default/17.edn_alert_test.1421064460 Dec 31 12:52:28 PM PST 23 Dec 31 12:52:38 PM PST 23 38621865 ps
T963 /workspace/coverage/default/77.edn_genbits.1870324479 Dec 31 12:53:45 PM PST 23 Dec 31 12:53:58 PM PST 23 15387418 ps
T964 /workspace/coverage/default/37.edn_intr.521092431 Dec 31 12:53:58 PM PST 23 Dec 31 12:54:09 PM PST 23 23367865 ps
T965 /workspace/coverage/default/24.edn_disable_auto_req_mode.2341719812 Dec 31 12:53:05 PM PST 23 Dec 31 12:53:19 PM PST 23 116843126 ps
T966 /workspace/coverage/default/130.edn_genbits.3587309499 Dec 31 12:53:38 PM PST 23 Dec 31 12:53:53 PM PST 23 277526398 ps
T967 /workspace/coverage/default/265.edn_genbits.3136246577 Dec 31 12:55:04 PM PST 23 Dec 31 12:55:10 PM PST 23 17115288 ps
T968 /workspace/coverage/default/173.edn_genbits.1763568355 Dec 31 12:53:54 PM PST 23 Dec 31 12:54:05 PM PST 23 24808239 ps
T969 /workspace/coverage/default/21.edn_stress_all.808886088 Dec 31 12:52:59 PM PST 23 Dec 31 12:53:07 PM PST 23 759799650 ps
T970 /workspace/coverage/default/4.edn_genbits.1382231560 Dec 31 12:52:12 PM PST 23 Dec 31 12:52:28 PM PST 23 65774991 ps
T971 /workspace/coverage/default/33.edn_stress_all_with_rand_reset.2697934322 Dec 31 12:53:37 PM PST 23 Dec 31 01:04:46 PM PST 23 58942443748 ps
T972 /workspace/coverage/default/101.edn_genbits.988383947 Dec 31 12:53:46 PM PST 23 Dec 31 12:54:00 PM PST 23 36562178 ps
T973 /workspace/coverage/default/8.edn_stress_all.1110525066 Dec 31 12:52:19 PM PST 23 Dec 31 12:52:34 PM PST 23 110429918 ps
T258 /workspace/coverage/default/18.edn_disable_auto_req_mode.3106223730 Dec 31 12:53:07 PM PST 23 Dec 31 12:53:19 PM PST 23 18300044 ps
T974 /workspace/coverage/default/78.edn_err.2442922880 Dec 31 12:53:34 PM PST 23 Dec 31 12:53:47 PM PST 23 24005898 ps
T975 /workspace/coverage/default/12.edn_stress_all.3277041235 Dec 31 12:52:12 PM PST 23 Dec 31 12:52:28 PM PST 23 57899271 ps

Test location /workspace/coverage/default/10.edn_genbits.683760270
Short name T1
Test name
Test status
Simulation time 126283110 ps
CPU time 2.68 seconds
Started Dec 31 12:52:21 PM PST 23
Finished Dec 31 12:52:36 PM PST 23
Peak memory 214088 kb
Host smart-780b48a7-d4bd-4275-9c34-4b7aaf378a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683760270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.683760270
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.313507495
Short name T40
Test name
Test status
Simulation time 209320918 ps
CPU time 1.01 seconds
Started Dec 31 12:54:33 PM PST 23
Finished Dec 31 12:54:35 PM PST 23
Peak memory 205616 kb
Host smart-3cd9a179-e182-400c-9da9-4c0e5c97cb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313507495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.313507495
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.3898892746
Short name T46
Test name
Test status
Simulation time 316363834 ps
CPU time 3.49 seconds
Started Dec 31 12:55:30 PM PST 23
Finished Dec 31 12:55:37 PM PST 23
Peak memory 205952 kb
Host smart-eaf78c5d-1e51-4a9c-a0fd-3e3310dcd141
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898892746 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.3898892746
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/default/26.edn_err.372851196
Short name T82
Test name
Test status
Simulation time 32945147 ps
CPU time 1.22 seconds
Started Dec 31 12:53:41 PM PST 23
Finished Dec 31 12:53:54 PM PST 23
Peak memory 216872 kb
Host smart-c03b8204-45d0-4924-9ec6-b22ef9d89acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372851196 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.372851196
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.3729142584
Short name T36
Test name
Test status
Simulation time 95194212272 ps
CPU time 1397.57 seconds
Started Dec 31 12:53:46 PM PST 23
Finished Dec 31 01:17:17 PM PST 23
Peak memory 218252 kb
Host smart-e30676a5-61f8-4326-8d47-189888bab2a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729142584 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.3729142584
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.edn_sec_cm.198860
Short name T24
Test name
Test status
Simulation time 6504053264 ps
CPU time 7.52 seconds
Started Dec 31 12:52:01 PM PST 23
Finished Dec 31 12:52:17 PM PST 23
Peak memory 234784 kb
Host smart-00ba817e-c178-4870-b575-285d29a0e0b5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198860 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.198860
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.1215985594
Short name T176
Test name
Test status
Simulation time 93045521 ps
CPU time 0.95 seconds
Started Dec 31 12:53:51 PM PST 23
Finished Dec 31 12:54:04 PM PST 23
Peak memory 214520 kb
Host smart-5d157392-db62-4b21-b586-38e42c6a11cf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215985594 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.1215985594
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.3765375822
Short name T27
Test name
Test status
Simulation time 140015114 ps
CPU time 2.75 seconds
Started Dec 31 12:55:03 PM PST 23
Finished Dec 31 12:55:11 PM PST 23
Peak memory 214320 kb
Host smart-1a926e22-ba7c-4467-aba9-000a95589b15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765375822 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3765375822
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/default/52.edn_err.587521673
Short name T13
Test name
Test status
Simulation time 21850111 ps
CPU time 1.21 seconds
Started Dec 31 12:54:18 PM PST 23
Finished Dec 31 12:54:21 PM PST 23
Peak memory 221736 kb
Host smart-0af3adb3-67ab-42cd-8c9f-b313ca27c9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587521673 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.587521673
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/0.edn_disable.3736002041
Short name T219
Test name
Test status
Simulation time 30223128 ps
CPU time 0.82 seconds
Started Dec 31 12:52:07 PM PST 23
Finished Dec 31 12:52:22 PM PST 23
Peak memory 214240 kb
Host smart-90dfc6d5-6cad-4b87-829e-a7454a5edc46
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736002041 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.3736002041
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.3299307112
Short name T315
Test name
Test status
Simulation time 48151902 ps
CPU time 0.85 seconds
Started Dec 31 12:55:27 PM PST 23
Finished Dec 31 12:55:32 PM PST 23
Peak memory 205920 kb
Host smart-dd6b439b-db66-4f6a-9870-710971d7bb8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299307112 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3299307112
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/default/82.edn_err.2334125249
Short name T8
Test name
Test status
Simulation time 104459424 ps
CPU time 0.98 seconds
Started Dec 31 12:53:27 PM PST 23
Finished Dec 31 12:53:40 PM PST 23
Peak memory 216008 kb
Host smart-43178e3e-3956-41a5-8679-a976f751e924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334125249 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.2334125249
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/45.edn_alert.2787961861
Short name T17
Test name
Test status
Simulation time 17512145 ps
CPU time 0.98 seconds
Started Dec 31 12:54:05 PM PST 23
Finished Dec 31 12:54:13 PM PST 23
Peak memory 205892 kb
Host smart-c8e627f2-1a8f-48ac-9e2d-0f138b450c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787961861 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.2787961861
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/20.edn_disable.327494617
Short name T88
Test name
Test status
Simulation time 14333531 ps
CPU time 0.89 seconds
Started Dec 31 12:52:59 PM PST 23
Finished Dec 31 12:53:03 PM PST 23
Peak memory 214508 kb
Host smart-112ec9db-5734-4c89-9aba-330a107c2204
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327494617 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.327494617
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/226.edn_genbits.724085996
Short name T31
Test name
Test status
Simulation time 37845741 ps
CPU time 0.94 seconds
Started Dec 31 12:54:09 PM PST 23
Finished Dec 31 12:54:15 PM PST 23
Peak memory 205428 kb
Host smart-06fe1954-610d-43fd-a2cc-c9943ac30d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724085996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.724085996
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.1159810182
Short name T159
Test name
Test status
Simulation time 29077490 ps
CPU time 0.95 seconds
Started Dec 31 12:55:46 PM PST 23
Finished Dec 31 12:55:49 PM PST 23
Peak memory 206096 kb
Host smart-da54e4f6-8d3a-4939-b813-5d5f029a18a8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159810182 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.1159810182
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.2450447406
Short name T108
Test name
Test status
Simulation time 40853757063 ps
CPU time 1036.66 seconds
Started Dec 31 12:53:44 PM PST 23
Finished Dec 31 01:11:13 PM PST 23
Peak memory 215664 kb
Host smart-b086df54-d40e-4522-849e-ad34a0840687
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450447406 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.2450447406
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.2427499368
Short name T195
Test name
Test status
Simulation time 84595163 ps
CPU time 1.13 seconds
Started Dec 31 12:53:08 PM PST 23
Finished Dec 31 12:53:19 PM PST 23
Peak memory 214448 kb
Host smart-269e10fc-f0d3-42f1-aa5d-11bed928f6be
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427499368 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.2427499368
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_disable.4097598628
Short name T129
Test name
Test status
Simulation time 12584563 ps
CPU time 0.88 seconds
Started Dec 31 12:52:59 PM PST 23
Finished Dec 31 12:53:03 PM PST 23
Peak memory 214512 kb
Host smart-3c7d7eb4-bd7d-4e2e-846f-c8f38ccd52ad
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097598628 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.4097598628
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable.2194923520
Short name T134
Test name
Test status
Simulation time 29539797 ps
CPU time 0.78 seconds
Started Dec 31 12:53:23 PM PST 23
Finished Dec 31 12:53:37 PM PST 23
Peak memory 214228 kb
Host smart-c9607bf9-fe9d-4f90-a1ad-c4281cbfbbbd
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194923520 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.2194923520
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/5.edn_regwen.3056010487
Short name T277
Test name
Test status
Simulation time 50157160 ps
CPU time 0.87 seconds
Started Dec 31 12:52:12 PM PST 23
Finished Dec 31 12:52:28 PM PST 23
Peak memory 204832 kb
Host smart-f2b14ab4-c37c-499c-8660-7a68d5f82bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056010487 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.3056010487
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/28.edn_intr.4212169067
Short name T95
Test name
Test status
Simulation time 18689678 ps
CPU time 0.99 seconds
Started Dec 31 12:53:14 PM PST 23
Finished Dec 31 12:53:33 PM PST 23
Peak memory 214428 kb
Host smart-036b4f16-5fab-45bc-88a3-ef4db3f58e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212169067 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.4212169067
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/29.edn_disable.1416410314
Short name T228
Test name
Test status
Simulation time 50272009 ps
CPU time 0.84 seconds
Started Dec 31 12:53:37 PM PST 23
Finished Dec 31 12:53:51 PM PST 23
Peak memory 214344 kb
Host smart-52e34bfd-cd06-4078-9db7-df8d19582bac
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416410314 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.1416410314
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable.2154499615
Short name T261
Test name
Test status
Simulation time 12812577 ps
CPU time 0.89 seconds
Started Dec 31 12:54:03 PM PST 23
Finished Dec 31 12:54:12 PM PST 23
Peak memory 214292 kb
Host smart-08c4a810-fab7-4f77-a9a1-03b1a0c4b1ca
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154499615 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2154499615
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/234.edn_genbits.3861062502
Short name T87
Test name
Test status
Simulation time 24313177 ps
CPU time 1.12 seconds
Started Dec 31 12:54:42 PM PST 23
Finished Dec 31 12:54:45 PM PST 23
Peak memory 214156 kb
Host smart-233bf3e5-81fa-45e0-945a-5717c42d5cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861062502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.3861062502
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3836591387
Short name T143
Test name
Test status
Simulation time 43303315 ps
CPU time 1.49 seconds
Started Dec 31 12:55:20 PM PST 23
Finished Dec 31 12:55:26 PM PST 23
Peak memory 206004 kb
Host smart-29a51a40-a3fd-4ebc-a995-351fa15cffed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836591387 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.3836591387
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.1669875777
Short name T47
Test name
Test status
Simulation time 132515419 ps
CPU time 0.75 seconds
Started Dec 31 12:54:57 PM PST 23
Finished Dec 31 12:55:14 PM PST 23
Peak memory 205820 kb
Host smart-6fc90b6a-eb48-4fe0-a604-536a8de50c7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669875777 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.1669875777
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/default/14.edn_disable.3788384395
Short name T130
Test name
Test status
Simulation time 16444050 ps
CPU time 0.8 seconds
Started Dec 31 12:52:25 PM PST 23
Finished Dec 31 12:52:36 PM PST 23
Peak memory 205900 kb
Host smart-4ca54144-57ff-40a9-9c85-06eaac3e94d8
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788384395 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.3788384395
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.3937586765
Short name T199
Test name
Test status
Simulation time 28140900 ps
CPU time 0.98 seconds
Started Dec 31 12:53:29 PM PST 23
Finished Dec 31 12:53:42 PM PST 23
Peak memory 214484 kb
Host smart-8df1cad8-cfab-4f3d-a743-58e783490a5d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937586765 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.3937586765
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.39688522
Short name T377
Test name
Test status
Simulation time 22288003 ps
CPU time 1.59 seconds
Started Dec 31 12:55:17 PM PST 23
Finished Dec 31 12:55:24 PM PST 23
Peak memory 214376 kb
Host smart-23e63858-7645-4c15-a5ca-bf62b209c687
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39688522 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.39688522
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/205.edn_genbits.1609003613
Short name T296
Test name
Test status
Simulation time 27780491 ps
CPU time 0.94 seconds
Started Dec 31 12:55:09 PM PST 23
Finished Dec 31 12:55:16 PM PST 23
Peak memory 205008 kb
Host smart-4c2a489d-30ed-4b47-b76a-02e47a6c40f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609003613 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.1609003613
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.1736215252
Short name T928
Test name
Test status
Simulation time 19441073 ps
CPU time 1.13 seconds
Started Dec 31 12:52:13 PM PST 23
Finished Dec 31 12:52:29 PM PST 23
Peak memory 225788 kb
Host smart-13530938-f82f-4481-a97b-e0aeaa8f1152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736215252 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.1736215252
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.2037243762
Short name T191
Test name
Test status
Simulation time 83233262 ps
CPU time 0.98 seconds
Started Dec 31 12:52:09 PM PST 23
Finished Dec 31 12:52:24 PM PST 23
Peak memory 214580 kb
Host smart-b75966b2-01a5-4f58-933b-b426af3db8ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037243762 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.2037243762
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_disable.860821494
Short name T214
Test name
Test status
Simulation time 11015872 ps
CPU time 0.82 seconds
Started Dec 31 12:52:28 PM PST 23
Finished Dec 31 12:52:38 PM PST 23
Peak memory 214252 kb
Host smart-f9219c1c-3340-4c4d-b57a-54df3f939c24
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860821494 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.860821494
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.533784409
Short name T181
Test name
Test status
Simulation time 215192486 ps
CPU time 1.11 seconds
Started Dec 31 12:52:28 PM PST 23
Finished Dec 31 12:52:38 PM PST 23
Peak memory 214632 kb
Host smart-f7d5787f-898a-474f-ac9c-b8eba0419280
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533784409 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_di
sable_auto_req_mode.533784409
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.2979440421
Short name T793
Test name
Test status
Simulation time 71250613 ps
CPU time 1.07 seconds
Started Dec 31 12:52:33 PM PST 23
Finished Dec 31 12:52:42 PM PST 23
Peak memory 214484 kb
Host smart-9b467ffc-2a31-42db-b764-5818ad309322
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979440421 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.2979440421
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.3106223730
Short name T258
Test name
Test status
Simulation time 18300044 ps
CPU time 0.98 seconds
Started Dec 31 12:53:07 PM PST 23
Finished Dec 31 12:53:19 PM PST 23
Peak memory 214584 kb
Host smart-aa996fe1-6230-4af3-a500-6bc1ab3c0f1d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106223730 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.3106223730
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_disable.1855753145
Short name T223
Test name
Test status
Simulation time 68021939 ps
CPU time 1 seconds
Started Dec 31 12:53:51 PM PST 23
Finished Dec 31 12:54:04 PM PST 23
Peak memory 214280 kb
Host smart-7c662ce9-b965-43dd-80b7-e5d975995e50
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855753145 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.1855753145
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.3505988606
Short name T58
Test name
Test status
Simulation time 25752642843 ps
CPU time 555.27 seconds
Started Dec 31 12:53:36 PM PST 23
Finished Dec 31 01:03:04 PM PST 23
Peak memory 215896 kb
Host smart-5204c982-289e-4faf-8085-5dd4802bdfe6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505988606 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.3505988606
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/146.edn_genbits.3975969509
Short name T289
Test name
Test status
Simulation time 62777699 ps
CPU time 0.95 seconds
Started Dec 31 12:54:09 PM PST 23
Finished Dec 31 12:54:15 PM PST 23
Peak memory 205448 kb
Host smart-fe375a42-c5ee-47d9-8ae4-7f02751f6140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975969509 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.3975969509
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.4140373373
Short name T304
Test name
Test status
Simulation time 73870862 ps
CPU time 0.94 seconds
Started Dec 31 12:54:53 PM PST 23
Finished Dec 31 12:54:59 PM PST 23
Peak memory 205064 kb
Host smart-9aaf68b2-53ea-4ecc-a6e6-014e659a39bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140373373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.4140373373
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_regwen.3383523374
Short name T278
Test name
Test status
Simulation time 32717317 ps
CPU time 0.81 seconds
Started Dec 31 12:52:22 PM PST 23
Finished Dec 31 12:52:35 PM PST 23
Peak memory 204852 kb
Host smart-59e10834-d639-4b65-b6f6-ea76c96ca224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383523374 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.3383523374
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/18.edn_alert.1481806538
Short name T271
Test name
Test status
Simulation time 32851818 ps
CPU time 1 seconds
Started Dec 31 12:52:29 PM PST 23
Finished Dec 31 12:52:40 PM PST 23
Peak memory 205948 kb
Host smart-6e9b9b9c-0ec8-41c0-a591-a630b2b99ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481806538 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.1481806538
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/42.edn_genbits.2416896325
Short name T11
Test name
Test status
Simulation time 21898743 ps
CPU time 1.14 seconds
Started Dec 31 12:53:35 PM PST 23
Finished Dec 31 12:53:49 PM PST 23
Peak memory 214188 kb
Host smart-5f5565e6-7d2e-49d7-830a-1c3f37c39f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416896325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.2416896325
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.3599899794
Short name T346
Test name
Test status
Simulation time 37196077 ps
CPU time 0.92 seconds
Started Dec 31 12:52:31 PM PST 23
Finished Dec 31 12:52:41 PM PST 23
Peak memory 205628 kb
Host smart-39171efc-bd5f-443b-a453-04b8160b99f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599899794 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.3599899794
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert.3069812335
Short name T272
Test name
Test status
Simulation time 39882155 ps
CPU time 0.94 seconds
Started Dec 31 12:52:30 PM PST 23
Finished Dec 31 12:52:40 PM PST 23
Peak memory 205540 kb
Host smart-ff06827e-52e2-4528-b01b-00fc59540466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069812335 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.3069812335
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/80.edn_genbits.2722023495
Short name T30
Test name
Test status
Simulation time 49496158 ps
CPU time 1.04 seconds
Started Dec 31 12:53:55 PM PST 23
Finished Dec 31 12:54:07 PM PST 23
Peak memory 205500 kb
Host smart-c4cd9163-b6d4-4469-8476-24898b6ce328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722023495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.2722023495
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.3736846039
Short name T298
Test name
Test status
Simulation time 54530284 ps
CPU time 2.19 seconds
Started Dec 31 12:54:36 PM PST 23
Finished Dec 31 12:54:40 PM PST 23
Peak memory 214080 kb
Host smart-bea27349-9347-4fa9-b53c-94d29fe47bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736846039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3736846039
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_regwen.2151233536
Short name T337
Test name
Test status
Simulation time 26937805 ps
CPU time 0.83 seconds
Started Dec 31 12:52:02 PM PST 23
Finished Dec 31 12:52:11 PM PST 23
Peak memory 204656 kb
Host smart-486266f0-b383-4165-8f0b-9798f0734b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151233536 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.2151233536
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/208.edn_genbits.3890883511
Short name T284
Test name
Test status
Simulation time 63449752 ps
CPU time 0.98 seconds
Started Dec 31 12:54:42 PM PST 23
Finished Dec 31 12:54:44 PM PST 23
Peak memory 205596 kb
Host smart-bb7ae9cf-5422-4521-944b-dd8139381392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890883511 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.3890883511
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.436875808
Short name T321
Test name
Test status
Simulation time 432847450096 ps
CPU time 2417.18 seconds
Started Dec 31 12:53:03 PM PST 23
Finished Dec 31 01:33:35 PM PST 23
Peak memory 222148 kb
Host smart-2390ae65-ac4a-40fc-8f06-63c4e453c537
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436875808 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.436875808
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/233.edn_genbits.3361597273
Short name T332
Test name
Test status
Simulation time 28631628 ps
CPU time 1.1 seconds
Started Dec 31 12:54:10 PM PST 23
Finished Dec 31 12:54:20 PM PST 23
Peak memory 205728 kb
Host smart-6956d37c-6621-4daf-851b-b520ff66c352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361597273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.3361597273
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.1556423329
Short name T335
Test name
Test status
Simulation time 34824422 ps
CPU time 1.05 seconds
Started Dec 31 12:54:51 PM PST 23
Finished Dec 31 12:54:56 PM PST 23
Peak memory 205472 kb
Host smart-c1c7d7d7-3b47-4cb6-9370-1e4ce96815c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556423329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.1556423329
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_alert_test.3321160909
Short name T59
Test name
Test status
Simulation time 28015013 ps
CPU time 0.93 seconds
Started Dec 31 12:52:12 PM PST 23
Finished Dec 31 12:52:28 PM PST 23
Peak memory 204604 kb
Host smart-668efa49-1dbf-4e9f-ac70-957f69e20474
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321160909 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.3321160909
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/68.edn_err.1156569720
Short name T53
Test name
Test status
Simulation time 19146783 ps
CPU time 1.17 seconds
Started Dec 31 12:53:57 PM PST 23
Finished Dec 31 12:54:08 PM PST 23
Peak memory 228536 kb
Host smart-7ac9feb1-7fae-4ec4-b9a2-12514cf4ae61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156569720 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.1156569720
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/232.edn_genbits.3797218881
Short name T508
Test name
Test status
Simulation time 25498265 ps
CPU time 0.92 seconds
Started Dec 31 12:54:32 PM PST 23
Finished Dec 31 12:54:34 PM PST 23
Peak memory 204780 kb
Host smart-cdc938f1-8971-4376-ab5a-9742abf1407e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797218881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.3797218881
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.997765278
Short name T244
Test name
Test status
Simulation time 70300166 ps
CPU time 0.89 seconds
Started Dec 31 12:55:17 PM PST 23
Finished Dec 31 12:55:23 PM PST 23
Peak memory 205964 kb
Host smart-8f78f638-a549-43b4-8acd-805c3e34110c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997765278 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.997765278
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/default/12.edn_intr.2459116665
Short name T97
Test name
Test status
Simulation time 28728684 ps
CPU time 0.82 seconds
Started Dec 31 12:52:25 PM PST 23
Finished Dec 31 12:52:36 PM PST 23
Peak memory 214460 kb
Host smart-db052a4a-247a-4a68-adf9-fed922ba398e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459116665 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.2459116665
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.4043777058
Short name T154
Test name
Test status
Simulation time 85653746 ps
CPU time 2.03 seconds
Started Dec 31 12:54:52 PM PST 23
Finished Dec 31 12:54:59 PM PST 23
Peak memory 206012 kb
Host smart-1d6b3d46-06eb-4e93-927c-8c5561c84741
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043777058 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.4043777058
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.3256549761
Short name T384
Test name
Test status
Simulation time 22177289 ps
CPU time 0.85 seconds
Started Dec 31 12:55:24 PM PST 23
Finished Dec 31 12:55:30 PM PST 23
Peak memory 205964 kb
Host smart-8e55fd81-8a95-4fb3-9c69-b8f377f04f15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256549761 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.3256549761
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.4260203911
Short name T280
Test name
Test status
Simulation time 48240438 ps
CPU time 1.54 seconds
Started Dec 31 12:55:36 PM PST 23
Finished Dec 31 12:55:42 PM PST 23
Peak memory 206000 kb
Host smart-66291cda-7c0e-4495-9358-033af645d3d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260203911 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.4260203911
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.207160653
Short name T303
Test name
Test status
Simulation time 109956620209 ps
CPU time 386.48 seconds
Started Dec 31 12:52:08 PM PST 23
Finished Dec 31 12:58:49 PM PST 23
Peak memory 215032 kb
Host smart-07173dc8-ff7f-40e2-a4e7-6e8b8ecbfea8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207160653 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.207160653
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.2378052457
Short name T476
Test name
Test status
Simulation time 54558990 ps
CPU time 1.02 seconds
Started Dec 31 12:53:55 PM PST 23
Finished Dec 31 12:54:06 PM PST 23
Peak memory 214132 kb
Host smart-e2b41baf-e20c-4b13-8b8e-12f8cf731525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378052457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.2378052457
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.415288765
Short name T372
Test name
Test status
Simulation time 27842886 ps
CPU time 0.92 seconds
Started Dec 31 12:53:59 PM PST 23
Finished Dec 31 12:54:09 PM PST 23
Peak memory 205156 kb
Host smart-3d1920aa-2c1b-4c7c-9d38-46fa0cfed37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415288765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.415288765
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.3676275564
Short name T369
Test name
Test status
Simulation time 30655469 ps
CPU time 0.95 seconds
Started Dec 31 12:54:43 PM PST 23
Finished Dec 31 12:54:47 PM PST 23
Peak memory 205600 kb
Host smart-bdf404c5-134b-45f1-bd9e-66619a2f7ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676275564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.3676275564
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.4099728601
Short name T301
Test name
Test status
Simulation time 77374791 ps
CPU time 1.15 seconds
Started Dec 31 12:54:39 PM PST 23
Finished Dec 31 12:54:42 PM PST 23
Peak memory 214100 kb
Host smart-02a002f5-ae34-4c24-aadd-692b9df4c0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099728601 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.4099728601
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.2071716641
Short name T913
Test name
Test status
Simulation time 124415176658 ps
CPU time 675.53 seconds
Started Dec 31 12:52:27 PM PST 23
Finished Dec 31 01:03:52 PM PST 23
Peak memory 214512 kb
Host smart-b1ad3ee8-9002-4ddf-98a6-c2dddb4bf06a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071716641 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.2071716641
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.2019517370
Short name T906
Test name
Test status
Simulation time 18616297 ps
CPU time 0.99 seconds
Started Dec 31 12:53:05 PM PST 23
Finished Dec 31 12:53:18 PM PST 23
Peak memory 205940 kb
Host smart-47c8b898-fab1-42bd-a615-a5fae47c0189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019517370 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.2019517370
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/231.edn_genbits.1458324253
Short name T307
Test name
Test status
Simulation time 37599451 ps
CPU time 1.63 seconds
Started Dec 31 12:54:09 PM PST 23
Finished Dec 31 12:54:15 PM PST 23
Peak memory 214268 kb
Host smart-5d528969-9c71-450c-a5fb-4a12103eae4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458324253 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.1458324253
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.3915340028
Short name T273
Test name
Test status
Simulation time 19012604 ps
CPU time 0.98 seconds
Started Dec 31 12:52:08 PM PST 23
Finished Dec 31 12:52:22 PM PST 23
Peak memory 205888 kb
Host smart-2b77b550-e41d-4aaa-932c-1281a7a61b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915340028 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.3915340028
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/0.edn_intr.750355769
Short name T835
Test name
Test status
Simulation time 17405560 ps
CPU time 1.01 seconds
Started Dec 31 12:52:12 PM PST 23
Finished Dec 31 12:52:28 PM PST 23
Peak memory 214524 kb
Host smart-a2762d2c-de76-41fa-a219-8bcc18ea58c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750355769 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.750355769
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/192.edn_genbits.367046324
Short name T499
Test name
Test status
Simulation time 130307452 ps
CPU time 1.32 seconds
Started Dec 31 12:54:48 PM PST 23
Finished Dec 31 12:54:54 PM PST 23
Peak memory 214092 kb
Host smart-c979d2bf-485d-4635-ba8a-1303cf06b6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367046324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.367046324
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.3771599953
Short name T148
Test name
Test status
Simulation time 432722858 ps
CPU time 2.14 seconds
Started Dec 31 12:55:03 PM PST 23
Finished Dec 31 12:55:10 PM PST 23
Peak memory 214268 kb
Host smart-356fdd4e-4b51-4cd2-b936-f5acc32eafdf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771599953 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3771599953
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/default/11.edn_disable.460814862
Short name T126
Test name
Test status
Simulation time 12867206 ps
CPU time 0.85 seconds
Started Dec 31 12:52:23 PM PST 23
Finished Dec 31 12:52:36 PM PST 23
Peak memory 214312 kb
Host smart-70f03b88-ea8d-4bac-b3a1-38e6335c1f6c
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460814862 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.460814862
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.718375760
Short name T902
Test name
Test status
Simulation time 17646671 ps
CPU time 1.34 seconds
Started Dec 31 12:52:33 PM PST 23
Finished Dec 31 12:52:43 PM PST 23
Peak memory 214504 kb
Host smart-714f4aa5-d4ed-45bf-92b8-f5c4e070c1fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718375760 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_di
sable_auto_req_mode.718375760
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_disable.1140325750
Short name T123
Test name
Test status
Simulation time 16451813 ps
CPU time 0.82 seconds
Started Dec 31 12:53:03 PM PST 23
Finished Dec 31 12:53:18 PM PST 23
Peak memory 214312 kb
Host smart-9a61f2c2-86e5-4577-8877-71d5f0d3c277
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140325750 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1140325750
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable.308217548
Short name T135
Test name
Test status
Simulation time 12437233 ps
CPU time 0.86 seconds
Started Dec 31 12:53:38 PM PST 23
Finished Dec 31 12:53:51 PM PST 23
Peak memory 214520 kb
Host smart-19a6d7ab-626c-40a9-aadc-25e176d2c8eb
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308217548 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.308217548
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/279.edn_genbits.2109536690
Short name T696
Test name
Test status
Simulation time 48967845 ps
CPU time 1.32 seconds
Started Dec 31 12:54:13 PM PST 23
Finished Dec 31 12:54:17 PM PST 23
Peak memory 214180 kb
Host smart-0bf985bd-3675-4409-a1a9-83d7ac725861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109536690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.2109536690
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3017520327
Short name T440
Test name
Test status
Simulation time 348141608 ps
CPU time 1.11 seconds
Started Dec 31 12:54:49 PM PST 23
Finished Dec 31 12:54:54 PM PST 23
Peak memory 205976 kb
Host smart-964f4d2e-1e10-4fc6-979c-18fe0e6d0a98
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017520327 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.3017520327
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3985418433
Short name T378
Test name
Test status
Simulation time 489105049 ps
CPU time 2.96 seconds
Started Dec 31 12:55:00 PM PST 23
Finished Dec 31 12:55:09 PM PST 23
Peak memory 206032 kb
Host smart-3d21d8ed-6092-4d86-8942-6ec7493c63c9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985418433 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.3985418433
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.334673294
Short name T385
Test name
Test status
Simulation time 68133149 ps
CPU time 0.82 seconds
Started Dec 31 12:54:46 PM PST 23
Finished Dec 31 12:54:51 PM PST 23
Peak memory 205856 kb
Host smart-56decd27-4fb9-4820-838d-1e2a6e499bc7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334673294 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.334673294
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.320523431
Short name T138
Test name
Test status
Simulation time 19391279 ps
CPU time 1.07 seconds
Started Dec 31 12:54:57 PM PST 23
Finished Dec 31 12:55:03 PM PST 23
Peak memory 214224 kb
Host smart-13848689-1e65-44fb-a7f7-05996a46c194
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320523431 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.320523431
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.3616928714
Short name T235
Test name
Test status
Simulation time 15575308 ps
CPU time 0.87 seconds
Started Dec 31 12:54:51 PM PST 23
Finished Dec 31 12:54:56 PM PST 23
Peak memory 205960 kb
Host smart-0a2781da-92e1-4d9d-88dd-33665cd6a59e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616928714 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.3616928714
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.1615455733
Short name T386
Test name
Test status
Simulation time 18792287 ps
CPU time 0.89 seconds
Started Dec 31 12:55:02 PM PST 23
Finished Dec 31 12:55:09 PM PST 23
Peak memory 206032 kb
Host smart-bb110d85-900c-4837-8426-e5ff2d9bb5b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615455733 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1615455733
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3291705822
Short name T422
Test name
Test status
Simulation time 15507657 ps
CPU time 1.04 seconds
Started Dec 31 12:55:10 PM PST 23
Finished Dec 31 12:55:17 PM PST 23
Peak memory 206088 kb
Host smart-8f9c9aa2-a01c-4256-9448-5941ef218e0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291705822 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.3291705822
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2958158813
Short name T392
Test name
Test status
Simulation time 89833314 ps
CPU time 2.39 seconds
Started Dec 31 12:55:24 PM PST 23
Finished Dec 31 12:55:31 PM PST 23
Peak memory 206072 kb
Host smart-1da7a802-f0bd-4375-9487-54dd946ed20f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958158813 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.2958158813
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3385777028
Short name T443
Test name
Test status
Simulation time 104456280 ps
CPU time 0.91 seconds
Started Dec 31 12:55:30 PM PST 23
Finished Dec 31 12:55:34 PM PST 23
Peak memory 206120 kb
Host smart-fd22306c-98d2-4639-a52e-503d97718b1e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385777028 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.3385777028
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3172458631
Short name T439
Test name
Test status
Simulation time 823152287 ps
CPU time 2.81 seconds
Started Dec 31 12:55:20 PM PST 23
Finished Dec 31 12:55:28 PM PST 23
Peak memory 206024 kb
Host smart-0fdf88b3-0594-41a9-a605-6468c74d0c70
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172458631 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.3172458631
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.369227502
Short name T249
Test name
Test status
Simulation time 51882435 ps
CPU time 0.9 seconds
Started Dec 31 12:55:11 PM PST 23
Finished Dec 31 12:55:18 PM PST 23
Peak memory 206032 kb
Host smart-a7910649-46f3-4aac-b9ee-f4d177c08bb3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369227502 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.369227502
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.628884170
Short name T137
Test name
Test status
Simulation time 51329289 ps
CPU time 1.38 seconds
Started Dec 31 12:55:05 PM PST 23
Finished Dec 31 12:55:12 PM PST 23
Peak memory 214348 kb
Host smart-9e04cdb9-1862-44fe-ab0c-24455cee28e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628884170 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.628884170
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.841247402
Short name T419
Test name
Test status
Simulation time 14289900 ps
CPU time 0.85 seconds
Started Dec 31 12:55:03 PM PST 23
Finished Dec 31 12:55:09 PM PST 23
Peak memory 205964 kb
Host smart-4fbd33f7-f9ec-4604-b4a3-f2ccc53c635d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841247402 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.841247402
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.1196934978
Short name T448
Test name
Test status
Simulation time 45289162 ps
CPU time 0.85 seconds
Started Dec 31 12:54:56 PM PST 23
Finished Dec 31 12:55:02 PM PST 23
Peak memory 205912 kb
Host smart-3416cadd-15d2-4183-a3d9-61e094947460
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196934978 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.1196934978
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2299839368
Short name T233
Test name
Test status
Simulation time 50258584 ps
CPU time 0.9 seconds
Started Dec 31 12:55:05 PM PST 23
Finished Dec 31 12:55:11 PM PST 23
Peak memory 205968 kb
Host smart-83dd5429-99d0-49f4-ab4f-3eb158343d7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299839368 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.2299839368
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.1358796331
Short name T165
Test name
Test status
Simulation time 52791900 ps
CPU time 2.01 seconds
Started Dec 31 12:54:57 PM PST 23
Finished Dec 31 12:55:05 PM PST 23
Peak memory 214444 kb
Host smart-968e80f6-ae73-436d-a79e-5e12cd5e9a31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358796331 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.1358796331
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1288563401
Short name T462
Test name
Test status
Simulation time 22899464 ps
CPU time 1.54 seconds
Started Dec 31 12:55:21 PM PST 23
Finished Dec 31 12:55:28 PM PST 23
Peak memory 214260 kb
Host smart-0f6855ab-78ec-4e47-bfd4-e70e299e65dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288563401 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.1288563401
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.2902141259
Short name T166
Test name
Test status
Simulation time 16620645 ps
CPU time 0.94 seconds
Started Dec 31 12:55:16 PM PST 23
Finished Dec 31 12:55:23 PM PST 23
Peak memory 205880 kb
Host smart-abf3a7da-cd57-422f-bf61-b47cc54ede5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902141259 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2902141259
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3154243109
Short name T436
Test name
Test status
Simulation time 20913911 ps
CPU time 1.09 seconds
Started Dec 31 12:55:00 PM PST 23
Finished Dec 31 12:55:07 PM PST 23
Peak memory 206036 kb
Host smart-a89aeee2-d1d5-45e0-9929-cd4c1d6bc7d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154243109 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.3154243109
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.1543510863
Short name T407
Test name
Test status
Simulation time 360207872 ps
CPU time 3.65 seconds
Started Dec 31 12:55:08 PM PST 23
Finished Dec 31 12:55:18 PM PST 23
Peak memory 214364 kb
Host smart-3e80c0a1-87af-497a-9bbd-199d74af756b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543510863 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.1543510863
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3645628574
Short name T413
Test name
Test status
Simulation time 358009473 ps
CPU time 2.12 seconds
Started Dec 31 12:55:23 PM PST 23
Finished Dec 31 12:55:30 PM PST 23
Peak memory 205968 kb
Host smart-7349cb3c-3300-4357-b498-e3ca17f10514
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645628574 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.3645628574
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.2437132023
Short name T430
Test name
Test status
Simulation time 12212616 ps
CPU time 0.87 seconds
Started Dec 31 12:55:13 PM PST 23
Finished Dec 31 12:55:20 PM PST 23
Peak memory 206004 kb
Host smart-1c25b228-08ad-4f6e-8c55-2cdc31b61f77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437132023 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.2437132023
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.1331803150
Short name T412
Test name
Test status
Simulation time 17589825 ps
CPU time 0.85 seconds
Started Dec 31 12:55:11 PM PST 23
Finished Dec 31 12:55:18 PM PST 23
Peak memory 205960 kb
Host smart-9fbdfd1d-f066-402a-891c-8be8d8590118
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331803150 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.1331803150
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.917914197
Short name T142
Test name
Test status
Simulation time 16074764 ps
CPU time 0.98 seconds
Started Dec 31 12:55:18 PM PST 23
Finished Dec 31 12:55:24 PM PST 23
Peak memory 206044 kb
Host smart-0318cd8a-6391-418b-9391-f379b3d3a97f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917914197 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_ou
tstanding.917914197
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.1635099521
Short name T387
Test name
Test status
Simulation time 80842178 ps
CPU time 2.9 seconds
Started Dec 31 12:55:37 PM PST 23
Finished Dec 31 12:55:45 PM PST 23
Peak memory 214268 kb
Host smart-f4978763-3687-46a9-86cd-7fb35baa862a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635099521 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.1635099521
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.468889076
Short name T171
Test name
Test status
Simulation time 111147145 ps
CPU time 1.64 seconds
Started Dec 31 12:55:15 PM PST 23
Finished Dec 31 12:55:23 PM PST 23
Peak memory 205972 kb
Host smart-98e738e5-4e2b-4630-94d5-097a0949d9c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468889076 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.468889076
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3606079702
Short name T147
Test name
Test status
Simulation time 21214926 ps
CPU time 0.88 seconds
Started Dec 31 12:54:54 PM PST 23
Finished Dec 31 12:55:00 PM PST 23
Peak memory 206020 kb
Host smart-15fe1b32-1630-4f82-8fad-ddc0eaee903a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606079702 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.3606079702
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.1370395597
Short name T250
Test name
Test status
Simulation time 79007866 ps
CPU time 0.87 seconds
Started Dec 31 12:55:00 PM PST 23
Finished Dec 31 12:55:07 PM PST 23
Peak memory 206032 kb
Host smart-0600d8b2-1b4b-4f8e-97be-7357a76fdd87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370395597 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.1370395597
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.3548486012
Short name T432
Test name
Test status
Simulation time 47884001 ps
CPU time 0.9 seconds
Started Dec 31 12:54:59 PM PST 23
Finished Dec 31 12:55:06 PM PST 23
Peak memory 206020 kb
Host smart-8d53410d-d6f8-4bb3-b466-f215f008a300
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548486012 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.3548486012
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.2526377077
Short name T410
Test name
Test status
Simulation time 31439234 ps
CPU time 1.31 seconds
Started Dec 31 12:55:11 PM PST 23
Finished Dec 31 12:55:18 PM PST 23
Peak memory 205900 kb
Host smart-73fc9e9f-f32f-4f20-af57-6028afe83fcd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526377077 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.2526377077
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.1926376542
Short name T139
Test name
Test status
Simulation time 188050189 ps
CPU time 2.44 seconds
Started Dec 31 12:55:47 PM PST 23
Finished Dec 31 12:55:51 PM PST 23
Peak memory 222480 kb
Host smart-59788061-ad35-4fef-8681-fe020c80bbb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926376542 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.1926376542
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3068504900
Short name T283
Test name
Test status
Simulation time 298116578 ps
CPU time 2.23 seconds
Started Dec 31 12:54:56 PM PST 23
Finished Dec 31 12:55:03 PM PST 23
Peak memory 206044 kb
Host smart-33c1507e-f8b5-4b00-9860-8cd2c640b8a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068504900 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.3068504900
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.406564679
Short name T416
Test name
Test status
Simulation time 36282986 ps
CPU time 1.13 seconds
Started Dec 31 12:55:12 PM PST 23
Finished Dec 31 12:55:19 PM PST 23
Peak memory 222520 kb
Host smart-805f3160-e246-4294-bb35-34c537336d53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406564679 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.406564679
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.1184865854
Short name T408
Test name
Test status
Simulation time 12992219 ps
CPU time 0.81 seconds
Started Dec 31 12:54:53 PM PST 23
Finished Dec 31 12:54:59 PM PST 23
Peak memory 205996 kb
Host smart-ddaabab8-9c02-489b-a135-f9541c833681
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184865854 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.1184865854
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.2193840129
Short name T409
Test name
Test status
Simulation time 159954219 ps
CPU time 0.77 seconds
Started Dec 31 12:55:04 PM PST 23
Finished Dec 31 12:55:10 PM PST 23
Peak memory 205800 kb
Host smart-0f04f84c-0083-489f-8eaa-802b83a803b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193840129 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.2193840129
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.796413665
Short name T151
Test name
Test status
Simulation time 194644586 ps
CPU time 1.02 seconds
Started Dec 31 12:55:11 PM PST 23
Finished Dec 31 12:55:18 PM PST 23
Peak memory 206020 kb
Host smart-b863d0e2-7bc1-41bb-969e-ef0184f1ad63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796413665 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_ou
tstanding.796413665
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.1327414945
Short name T400
Test name
Test status
Simulation time 143833977 ps
CPU time 2.39 seconds
Started Dec 31 12:55:28 PM PST 23
Finished Dec 31 12:55:34 PM PST 23
Peak memory 214328 kb
Host smart-61f079da-f2b2-4e69-b2c2-0566af3f1148
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327414945 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.1327414945
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.674132672
Short name T161
Test name
Test status
Simulation time 251073376 ps
CPU time 2.04 seconds
Started Dec 31 12:55:27 PM PST 23
Finished Dec 31 12:55:33 PM PST 23
Peak memory 206052 kb
Host smart-58cccfb2-0d9c-4456-9440-1c039e8f2d90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674132672 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.674132672
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2877854265
Short name T157
Test name
Test status
Simulation time 21087338 ps
CPU time 1.19 seconds
Started Dec 31 12:55:09 PM PST 23
Finished Dec 31 12:55:16 PM PST 23
Peak memory 214304 kb
Host smart-cdca4284-732f-4a75-ad13-10acdd92b845
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877854265 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2877854265
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.2885991615
Short name T162
Test name
Test status
Simulation time 82003586 ps
CPU time 0.74 seconds
Started Dec 31 12:54:58 PM PST 23
Finished Dec 31 12:55:04 PM PST 23
Peak memory 205784 kb
Host smart-dc2f4bcc-a8d4-4c59-8c4b-885dac78ae61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885991615 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.2885991615
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.1760421265
Short name T421
Test name
Test status
Simulation time 109665466 ps
CPU time 3.75 seconds
Started Dec 31 12:55:23 PM PST 23
Finished Dec 31 12:55:32 PM PST 23
Peak memory 214180 kb
Host smart-079a781f-253b-414f-9963-9f84265f1581
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760421265 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.1760421265
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2258577572
Short name T414
Test name
Test status
Simulation time 57711206 ps
CPU time 1.69 seconds
Started Dec 31 12:55:21 PM PST 23
Finished Dec 31 12:55:28 PM PST 23
Peak memory 205956 kb
Host smart-a90db7c6-fed9-490a-ae97-c92f013de03f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258577572 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.2258577572
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2391893727
Short name T236
Test name
Test status
Simulation time 20028069 ps
CPU time 1.1 seconds
Started Dec 31 12:54:56 PM PST 23
Finished Dec 31 12:55:02 PM PST 23
Peak memory 214256 kb
Host smart-3dc00932-3aee-4161-971d-459f3f4dfe17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391893727 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.2391893727
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.1137047815
Short name T398
Test name
Test status
Simulation time 20693194 ps
CPU time 0.81 seconds
Started Dec 31 12:55:21 PM PST 23
Finished Dec 31 12:55:27 PM PST 23
Peak memory 205940 kb
Host smart-88d27a03-bfb9-4846-8c2e-f1de96745071
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137047815 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.1137047815
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.3326557575
Short name T457
Test name
Test status
Simulation time 24123885 ps
CPU time 0.83 seconds
Started Dec 31 12:55:16 PM PST 23
Finished Dec 31 12:55:23 PM PST 23
Peak memory 205924 kb
Host smart-5e51c013-0580-4c5c-8781-5d764301beb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326557575 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3326557575
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3294826689
Short name T232
Test name
Test status
Simulation time 18508747 ps
CPU time 1.1 seconds
Started Dec 31 12:55:13 PM PST 23
Finished Dec 31 12:55:21 PM PST 23
Peak memory 205976 kb
Host smart-594da623-9887-4636-8ed8-381ebf1d6043
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294826689 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.3294826689
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.3549817875
Short name T140
Test name
Test status
Simulation time 43440458 ps
CPU time 1.67 seconds
Started Dec 31 12:55:16 PM PST 23
Finished Dec 31 12:55:24 PM PST 23
Peak memory 214300 kb
Host smart-34fd6188-dd0d-4249-8490-930d1c53b66b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549817875 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.3549817875
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.830591232
Short name T149
Test name
Test status
Simulation time 90465121 ps
CPU time 1.28 seconds
Started Dec 31 12:55:05 PM PST 23
Finished Dec 31 12:55:11 PM PST 23
Peak memory 214216 kb
Host smart-e1cab08e-f1a2-4484-854c-750016d16a7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830591232 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.830591232
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.895657575
Short name T247
Test name
Test status
Simulation time 55351587 ps
CPU time 0.96 seconds
Started Dec 31 12:55:27 PM PST 23
Finished Dec 31 12:55:32 PM PST 23
Peak memory 205940 kb
Host smart-3f6833df-5c2e-4522-af75-4d693a647d9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895657575 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.895657575
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3775391928
Short name T167
Test name
Test status
Simulation time 128525742 ps
CPU time 0.83 seconds
Started Dec 31 12:55:19 PM PST 23
Finished Dec 31 12:55:25 PM PST 23
Peak memory 205940 kb
Host smart-d6aa1d22-fa84-400c-8d23-60e5f57a8e8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775391928 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3775391928
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2983911615
Short name T160
Test name
Test status
Simulation time 38372987 ps
CPU time 1.18 seconds
Started Dec 31 12:55:11 PM PST 23
Finished Dec 31 12:55:19 PM PST 23
Peak memory 206072 kb
Host smart-7dca6605-9595-47c3-a8a4-63807da0cf04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983911615 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.2983911615
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.1053830258
Short name T146
Test name
Test status
Simulation time 506851282 ps
CPU time 4.27 seconds
Started Dec 31 12:55:10 PM PST 23
Finished Dec 31 12:55:20 PM PST 23
Peak memory 217708 kb
Host smart-a6d6d22a-33ee-48b9-b4fb-3398ca2055d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053830258 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.1053830258
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1476533492
Short name T282
Test name
Test status
Simulation time 124631310 ps
CPU time 2.02 seconds
Started Dec 31 12:55:00 PM PST 23
Finished Dec 31 12:55:07 PM PST 23
Peak memory 205968 kb
Host smart-5bc29fa4-c9b5-4ab4-950d-4b5b6afb705a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476533492 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.1476533492
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2520458303
Short name T459
Test name
Test status
Simulation time 59806641 ps
CPU time 1.26 seconds
Started Dec 31 12:55:36 PM PST 23
Finished Dec 31 12:55:41 PM PST 23
Peak memory 214264 kb
Host smart-91d9f6d0-4b79-4cad-aa7a-ded74732dcf4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520458303 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2520458303
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.1254252647
Short name T451
Test name
Test status
Simulation time 17558492 ps
CPU time 0.9 seconds
Started Dec 31 12:54:57 PM PST 23
Finished Dec 31 12:55:03 PM PST 23
Peak memory 206016 kb
Host smart-f890ff72-a8ae-4e49-bbe1-5677414d12d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254252647 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.1254252647
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.3258706089
Short name T396
Test name
Test status
Simulation time 17518581 ps
CPU time 0.79 seconds
Started Dec 31 12:55:23 PM PST 23
Finished Dec 31 12:55:29 PM PST 23
Peak memory 206012 kb
Host smart-04593161-da07-47aa-a9bf-eb8e47bfd767
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258706089 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.3258706089
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3542127163
Short name T426
Test name
Test status
Simulation time 63224011 ps
CPU time 0.97 seconds
Started Dec 31 12:55:25 PM PST 23
Finished Dec 31 12:55:30 PM PST 23
Peak memory 206000 kb
Host smart-f6afc333-ec71-4b4c-a8c1-95af4a54d6ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542127163 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.3542127163
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.2377922769
Short name T158
Test name
Test status
Simulation time 285168604 ps
CPU time 2.61 seconds
Started Dec 31 12:55:29 PM PST 23
Finished Dec 31 12:55:35 PM PST 23
Peak memory 214260 kb
Host smart-f50ccf2b-6a68-4b18-8ea2-f1ea33460e5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377922769 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.2377922769
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3687899004
Short name T141
Test name
Test status
Simulation time 161764226 ps
CPU time 1.47 seconds
Started Dec 31 12:55:20 PM PST 23
Finished Dec 31 12:55:26 PM PST 23
Peak memory 206068 kb
Host smart-0622cf04-92a8-4aae-bb45-cceebc588939
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687899004 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3687899004
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1579560994
Short name T383
Test name
Test status
Simulation time 24818968 ps
CPU time 1.32 seconds
Started Dec 31 12:54:58 PM PST 23
Finished Dec 31 12:55:05 PM PST 23
Peak memory 214352 kb
Host smart-e9c1f2e1-4b5a-4fcc-b163-89a94a0104aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579560994 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.1579560994
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.147641078
Short name T241
Test name
Test status
Simulation time 43868443 ps
CPU time 0.79 seconds
Started Dec 31 12:55:30 PM PST 23
Finished Dec 31 12:55:34 PM PST 23
Peak memory 205844 kb
Host smart-b25ed0a9-f4ab-423a-aaf6-40a4055663cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147641078 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.147641078
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.42327223
Short name T455
Test name
Test status
Simulation time 11970685 ps
CPU time 0.82 seconds
Started Dec 31 12:54:59 PM PST 23
Finished Dec 31 12:55:06 PM PST 23
Peak memory 205956 kb
Host smart-426f3eab-6466-4ca8-a273-0c462725307c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42327223 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.42327223
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2779222900
Short name T45
Test name
Test status
Simulation time 35426484 ps
CPU time 1.1 seconds
Started Dec 31 12:55:00 PM PST 23
Finished Dec 31 12:55:06 PM PST 23
Peak memory 206004 kb
Host smart-019411a5-4be9-4a30-81c1-c4ddd0f25e97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779222900 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.2779222900
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.3832348829
Short name T463
Test name
Test status
Simulation time 196154772 ps
CPU time 1.94 seconds
Started Dec 31 12:54:45 PM PST 23
Finished Dec 31 12:54:50 PM PST 23
Peak memory 214200 kb
Host smart-9a53cde5-66d3-4b77-b3c3-6e52fe914e19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832348829 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3832348829
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3409290625
Short name T399
Test name
Test status
Simulation time 17169285 ps
CPU time 1.05 seconds
Started Dec 31 12:55:09 PM PST 23
Finished Dec 31 12:55:16 PM PST 23
Peak memory 214276 kb
Host smart-ccbd86f4-1f8c-4b5e-a01d-4ec70716b84f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409290625 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3409290625
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.682458738
Short name T411
Test name
Test status
Simulation time 14564138 ps
CPU time 0.92 seconds
Started Dec 31 12:55:34 PM PST 23
Finished Dec 31 12:55:38 PM PST 23
Peak memory 205984 kb
Host smart-8824a45e-73c6-4850-8f09-b463c6d1457c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682458738 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.682458738
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.3916427002
Short name T310
Test name
Test status
Simulation time 101586817 ps
CPU time 0.74 seconds
Started Dec 31 12:54:53 PM PST 23
Finished Dec 31 12:54:58 PM PST 23
Peak memory 205772 kb
Host smart-962460be-a0f6-4501-8956-f18ac848f558
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916427002 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.3916427002
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.141097252
Short name T145
Test name
Test status
Simulation time 36530240 ps
CPU time 1.45 seconds
Started Dec 31 12:55:17 PM PST 23
Finished Dec 31 12:55:24 PM PST 23
Peak memory 206004 kb
Host smart-32b3c71c-b9eb-4765-a42b-d58e7ccddf6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141097252 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_ou
tstanding.141097252
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.2339195324
Short name T28
Test name
Test status
Simulation time 113904915 ps
CPU time 3.42 seconds
Started Dec 31 12:55:05 PM PST 23
Finished Dec 31 12:55:13 PM PST 23
Peak memory 214288 kb
Host smart-ebfb46d9-c550-48b1-ba76-921c08d76d8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339195324 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.2339195324
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.142047973
Short name T437
Test name
Test status
Simulation time 72849470 ps
CPU time 2.1 seconds
Started Dec 31 12:55:51 PM PST 23
Finished Dec 31 12:55:54 PM PST 23
Peak memory 206068 kb
Host smart-5ea33857-d6d4-401d-b590-2b4e920d4c2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142047973 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.142047973
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3027663142
Short name T246
Test name
Test status
Simulation time 23099062 ps
CPU time 1.1 seconds
Started Dec 31 12:55:12 PM PST 23
Finished Dec 31 12:55:19 PM PST 23
Peak memory 205940 kb
Host smart-cd056ce3-957f-4ebc-9b23-7f8533028c47
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027663142 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.3027663142
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3532409481
Short name T239
Test name
Test status
Simulation time 73257998 ps
CPU time 1.97 seconds
Started Dec 31 12:55:11 PM PST 23
Finished Dec 31 12:55:20 PM PST 23
Peak memory 206024 kb
Host smart-27255584-2456-4fcf-8dfd-bad1f4e4cd53
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532409481 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.3532409481
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2492540882
Short name T424
Test name
Test status
Simulation time 17140306 ps
CPU time 0.94 seconds
Started Dec 31 12:55:26 PM PST 23
Finished Dec 31 12:55:31 PM PST 23
Peak memory 206056 kb
Host smart-e6162131-aed1-49e4-b005-697b5a0e2fe3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492540882 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.2492540882
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.708732147
Short name T136
Test name
Test status
Simulation time 32846528 ps
CPU time 1.09 seconds
Started Dec 31 12:55:02 PM PST 23
Finished Dec 31 12:55:08 PM PST 23
Peak memory 214428 kb
Host smart-774e0acd-164a-46d2-8185-73146380628b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708732147 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.708732147
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.1822204788
Short name T238
Test name
Test status
Simulation time 32870790 ps
CPU time 0.79 seconds
Started Dec 31 12:55:15 PM PST 23
Finished Dec 31 12:55:22 PM PST 23
Peak memory 205808 kb
Host smart-97acadaf-a076-4361-afc5-ca5e6e48d23d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822204788 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.1822204788
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.694402710
Short name T237
Test name
Test status
Simulation time 35931970 ps
CPU time 0.78 seconds
Started Dec 31 12:55:12 PM PST 23
Finished Dec 31 12:55:19 PM PST 23
Peak memory 205792 kb
Host smart-19745db0-57d3-428d-b3e6-fe99d440417e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694402710 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.694402710
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2162284404
Short name T446
Test name
Test status
Simulation time 29265764 ps
CPU time 1.27 seconds
Started Dec 31 12:55:07 PM PST 23
Finished Dec 31 12:55:14 PM PST 23
Peak memory 205996 kb
Host smart-3073e190-a72e-47cb-8475-68e52c5d011b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162284404 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.2162284404
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.1764677093
Short name T458
Test name
Test status
Simulation time 73130049 ps
CPU time 2.58 seconds
Started Dec 31 12:55:05 PM PST 23
Finished Dec 31 12:55:13 PM PST 23
Peak memory 214312 kb
Host smart-d79c0021-4215-4307-a8a0-e529ce5139bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764677093 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.1764677093
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1246511074
Short name T442
Test name
Test status
Simulation time 539395103 ps
CPU time 2.13 seconds
Started Dec 31 12:55:25 PM PST 23
Finished Dec 31 12:55:35 PM PST 23
Peak memory 206020 kb
Host smart-7c8fa344-1148-4f38-b434-0d3ba17d827e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246511074 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.1246511074
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.2776487410
Short name T397
Test name
Test status
Simulation time 41589997 ps
CPU time 0.86 seconds
Started Dec 31 12:55:01 PM PST 23
Finished Dec 31 12:55:13 PM PST 23
Peak memory 205972 kb
Host smart-e56f0794-1159-40b7-aec4-5881d4dc9c7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776487410 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.2776487410
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.1071708468
Short name T394
Test name
Test status
Simulation time 15179174 ps
CPU time 0.78 seconds
Started Dec 31 12:55:00 PM PST 23
Finished Dec 31 12:55:06 PM PST 23
Peak memory 206032 kb
Host smart-d698f33d-45eb-4048-a3e2-9f7d4b386b01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071708468 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.1071708468
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.1735588786
Short name T311
Test name
Test status
Simulation time 36937987 ps
CPU time 0.8 seconds
Started Dec 31 12:55:38 PM PST 23
Finished Dec 31 12:55:43 PM PST 23
Peak memory 205984 kb
Host smart-1e2394be-d0a3-4f5f-b915-05ed9a4235c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735588786 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.1735588786
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.1918555691
Short name T466
Test name
Test status
Simulation time 48059773 ps
CPU time 0.84 seconds
Started Dec 31 12:55:51 PM PST 23
Finished Dec 31 12:55:53 PM PST 23
Peak memory 205948 kb
Host smart-a60b784b-6fe3-4db6-91aa-e6c01edd7244
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918555691 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.1918555691
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.2839249465
Short name T444
Test name
Test status
Simulation time 37348405 ps
CPU time 0.78 seconds
Started Dec 31 12:55:34 PM PST 23
Finished Dec 31 12:55:39 PM PST 23
Peak memory 206008 kb
Host smart-73f0f7df-5bec-49ac-9158-780149fb8db5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839249465 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.2839249465
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.3860444921
Short name T391
Test name
Test status
Simulation time 15685075 ps
CPU time 0.88 seconds
Started Dec 31 12:55:26 PM PST 23
Finished Dec 31 12:55:31 PM PST 23
Peak memory 206004 kb
Host smart-39205e1c-a593-4813-a3eb-02a9f3a9ffbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860444921 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3860444921
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.2476486686
Short name T433
Test name
Test status
Simulation time 10959915 ps
CPU time 0.79 seconds
Started Dec 31 12:55:24 PM PST 23
Finished Dec 31 12:55:29 PM PST 23
Peak memory 206016 kb
Host smart-59b6e733-cc6c-43c5-a4cb-298ab3f2ff99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476486686 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.2476486686
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.3531894593
Short name T382
Test name
Test status
Simulation time 53465050 ps
CPU time 0.81 seconds
Started Dec 31 12:55:38 PM PST 23
Finished Dec 31 12:55:43 PM PST 23
Peak memory 205780 kb
Host smart-60cd6029-4935-497f-8190-4d72eb3f3473
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531894593 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3531894593
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.2827204475
Short name T312
Test name
Test status
Simulation time 13651862 ps
CPU time 0.9 seconds
Started Dec 31 12:55:25 PM PST 23
Finished Dec 31 12:55:30 PM PST 23
Peak memory 205996 kb
Host smart-3dc98900-85a0-4a12-b0df-a048257cecbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827204475 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2827204475
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.2703962775
Short name T169
Test name
Test status
Simulation time 18289400 ps
CPU time 0.9 seconds
Started Dec 31 12:56:23 PM PST 23
Finished Dec 31 12:56:33 PM PST 23
Peak memory 205932 kb
Host smart-2552c48f-a98b-4209-856c-3f607200b2cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703962775 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.2703962775
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.151729132
Short name T164
Test name
Test status
Simulation time 59584066 ps
CPU time 1.14 seconds
Started Dec 31 12:55:10 PM PST 23
Finished Dec 31 12:55:17 PM PST 23
Peak memory 206032 kb
Host smart-7b624785-860a-48eb-bd3e-32dc7c59ee95
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151729132 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.151729132
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1655170802
Short name T464
Test name
Test status
Simulation time 436096149 ps
CPU time 5.39 seconds
Started Dec 31 12:55:05 PM PST 23
Finished Dec 31 12:55:16 PM PST 23
Peak memory 205944 kb
Host smart-c5e2718e-2aae-420b-881e-5e27b85970c9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655170802 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.1655170802
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.142211105
Short name T401
Test name
Test status
Simulation time 22418160 ps
CPU time 0.86 seconds
Started Dec 31 12:55:17 PM PST 23
Finished Dec 31 12:55:23 PM PST 23
Peak memory 205932 kb
Host smart-a1db1d9d-c195-4d23-b074-7125628eba9e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142211105 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.142211105
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.110924041
Short name T465
Test name
Test status
Simulation time 19256670 ps
CPU time 1.1 seconds
Started Dec 31 12:54:54 PM PST 23
Finished Dec 31 12:55:00 PM PST 23
Peak memory 214580 kb
Host smart-5208b685-4c65-410f-9737-d6789dbdc70f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110924041 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.110924041
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.4278265816
Short name T389
Test name
Test status
Simulation time 19717976 ps
CPU time 0.88 seconds
Started Dec 31 12:54:57 PM PST 23
Finished Dec 31 12:55:03 PM PST 23
Peak memory 205892 kb
Host smart-01fa0b72-8267-4f4e-9cdc-59a2bcd103af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278265816 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.4278265816
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.4167599202
Short name T438
Test name
Test status
Simulation time 32884989 ps
CPU time 1.11 seconds
Started Dec 31 12:55:15 PM PST 23
Finished Dec 31 12:55:23 PM PST 23
Peak memory 206104 kb
Host smart-e958d3cd-5bec-4df5-89c8-23048995435a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167599202 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.4167599202
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.3770904793
Short name T156
Test name
Test status
Simulation time 22271662 ps
CPU time 1.5 seconds
Started Dec 31 12:55:17 PM PST 23
Finished Dec 31 12:55:24 PM PST 23
Peak memory 222404 kb
Host smart-75adf315-4093-4f03-bf73-515bcdc30232
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770904793 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.3770904793
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.732059945
Short name T163
Test name
Test status
Simulation time 316101451 ps
CPU time 2.22 seconds
Started Dec 31 12:55:15 PM PST 23
Finished Dec 31 12:55:23 PM PST 23
Peak memory 206068 kb
Host smart-4a59e647-6f89-422b-8ec6-d00bf338d682
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732059945 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.732059945
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.2174794376
Short name T423
Test name
Test status
Simulation time 19324967 ps
CPU time 0.85 seconds
Started Dec 31 12:55:34 PM PST 23
Finished Dec 31 12:55:38 PM PST 23
Peak memory 205932 kb
Host smart-25dada83-3faa-4d0a-a450-f32692752559
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174794376 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2174794376
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.3302611103
Short name T381
Test name
Test status
Simulation time 16597656 ps
CPU time 0.9 seconds
Started Dec 31 12:55:52 PM PST 23
Finished Dec 31 12:55:56 PM PST 23
Peak memory 205988 kb
Host smart-b3ffd352-1aa3-4e88-8474-2ff6aee340c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302611103 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.3302611103
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.2638024775
Short name T395
Test name
Test status
Simulation time 135105479 ps
CPU time 0.78 seconds
Started Dec 31 12:56:17 PM PST 23
Finished Dec 31 12:56:28 PM PST 23
Peak memory 205832 kb
Host smart-58adefd4-e6ce-4d56-a341-f42f8d4861b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638024775 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2638024775
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.1475872437
Short name T417
Test name
Test status
Simulation time 39413254 ps
CPU time 0.78 seconds
Started Dec 31 12:55:33 PM PST 23
Finished Dec 31 12:55:37 PM PST 23
Peak memory 205712 kb
Host smart-94890561-043f-464f-a8f8-1a50d7a43610
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475872437 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.1475872437
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.3287038037
Short name T404
Test name
Test status
Simulation time 14442824 ps
CPU time 0.85 seconds
Started Dec 31 12:55:09 PM PST 23
Finished Dec 31 12:55:16 PM PST 23
Peak memory 205948 kb
Host smart-c7dc9af6-fa90-44da-bd11-44fc7b14d45a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287038037 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.3287038037
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.2854883730
Short name T427
Test name
Test status
Simulation time 13078280 ps
CPU time 0.87 seconds
Started Dec 31 12:55:52 PM PST 23
Finished Dec 31 12:55:56 PM PST 23
Peak memory 206000 kb
Host smart-4c09ecb6-9fd8-4a18-9957-9466d39dcf91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854883730 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.2854883730
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.2488920474
Short name T314
Test name
Test status
Simulation time 12087718 ps
CPU time 0.84 seconds
Started Dec 31 12:55:29 PM PST 23
Finished Dec 31 12:55:34 PM PST 23
Peak memory 205932 kb
Host smart-893823c7-3b0f-489a-a4aa-711e56fa6a57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488920474 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.2488920474
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.906545603
Short name T415
Test name
Test status
Simulation time 19099002 ps
CPU time 0.77 seconds
Started Dec 31 12:55:25 PM PST 23
Finished Dec 31 12:55:30 PM PST 23
Peak memory 205948 kb
Host smart-d3ae1805-8f73-4f48-ac01-a58bfe354107
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906545603 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.906545603
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.1242961747
Short name T380
Test name
Test status
Simulation time 21497162 ps
CPU time 0.85 seconds
Started Dec 31 12:55:20 PM PST 23
Finished Dec 31 12:55:26 PM PST 23
Peak memory 205900 kb
Host smart-a4f4c5e1-ab91-4d9b-9a22-a3611f7bd915
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242961747 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.1242961747
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3957437509
Short name T243
Test name
Test status
Simulation time 160992320 ps
CPU time 3.11 seconds
Started Dec 31 12:54:54 PM PST 23
Finished Dec 31 12:55:01 PM PST 23
Peak memory 206032 kb
Host smart-65b5ca6b-f6ce-4de4-9dd1-cbd42efb216a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957437509 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.3957437509
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3810755527
Short name T240
Test name
Test status
Simulation time 36408791 ps
CPU time 0.86 seconds
Started Dec 31 12:55:09 PM PST 23
Finished Dec 31 12:55:16 PM PST 23
Peak memory 205836 kb
Host smart-373510c1-7055-4ab0-a9ed-0b2857a166b5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810755527 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3810755527
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3309754395
Short name T390
Test name
Test status
Simulation time 60457547 ps
CPU time 1.08 seconds
Started Dec 31 12:55:07 PM PST 23
Finished Dec 31 12:55:13 PM PST 23
Peak memory 214268 kb
Host smart-9230c038-9195-4548-acdf-2058788bb547
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309754395 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.3309754395
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.2733202300
Short name T242
Test name
Test status
Simulation time 30187235 ps
CPU time 0.78 seconds
Started Dec 31 12:55:02 PM PST 23
Finished Dec 31 12:55:08 PM PST 23
Peak memory 205832 kb
Host smart-4ab92141-7ee5-4361-b40f-309e65672d9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733202300 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2733202300
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.461935593
Short name T48
Test name
Test status
Simulation time 41211012 ps
CPU time 0.83 seconds
Started Dec 31 12:55:11 PM PST 23
Finished Dec 31 12:55:18 PM PST 23
Peak memory 206048 kb
Host smart-b273e3b8-f76b-41f6-957d-4810c56744b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461935593 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.461935593
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1350170288
Short name T152
Test name
Test status
Simulation time 118246888 ps
CPU time 1.05 seconds
Started Dec 31 12:54:59 PM PST 23
Finished Dec 31 12:55:06 PM PST 23
Peak memory 205972 kb
Host smart-b3dd86fe-d845-488f-9807-c368fb6a7ac4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350170288 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.1350170288
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.740510486
Short name T435
Test name
Test status
Simulation time 78231295 ps
CPU time 2.83 seconds
Started Dec 31 12:54:55 PM PST 23
Finished Dec 31 12:55:03 PM PST 23
Peak memory 214224 kb
Host smart-b5da7f65-4145-4200-af67-482a4a278987
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740510486 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.740510486
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3230084224
Short name T447
Test name
Test status
Simulation time 650726699 ps
CPU time 1.97 seconds
Started Dec 31 12:54:51 PM PST 23
Finished Dec 31 12:54:58 PM PST 23
Peak memory 206016 kb
Host smart-608e4cf8-e381-432c-bc9f-1d496279240f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230084224 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.3230084224
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.255020582
Short name T313
Test name
Test status
Simulation time 20131095 ps
CPU time 0.78 seconds
Started Dec 31 12:55:38 PM PST 23
Finished Dec 31 12:55:43 PM PST 23
Peak memory 205804 kb
Host smart-a41371c9-bc9c-4ed5-87bb-af40bad0fb56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255020582 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.255020582
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.2677168114
Short name T316
Test name
Test status
Simulation time 12743908 ps
CPU time 0.81 seconds
Started Dec 31 12:55:24 PM PST 23
Finished Dec 31 12:55:29 PM PST 23
Peak memory 206000 kb
Host smart-4c065e18-2da1-4b99-8b51-3fd35d5b3f04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677168114 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.2677168114
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.2551224935
Short name T428
Test name
Test status
Simulation time 28030949 ps
CPU time 0.77 seconds
Started Dec 31 12:55:30 PM PST 23
Finished Dec 31 12:55:34 PM PST 23
Peak memory 205836 kb
Host smart-58101fcb-080e-4054-a3da-754dc1d77063
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551224935 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.2551224935
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.3668502717
Short name T168
Test name
Test status
Simulation time 25066275 ps
CPU time 0.81 seconds
Started Dec 31 12:55:36 PM PST 23
Finished Dec 31 12:55:44 PM PST 23
Peak memory 205892 kb
Host smart-823cb0f3-ebb8-4b87-b6c0-8b159244fb92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668502717 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.3668502717
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.356078558
Short name T460
Test name
Test status
Simulation time 43138828 ps
CPU time 0.8 seconds
Started Dec 31 12:55:34 PM PST 23
Finished Dec 31 12:55:39 PM PST 23
Peak memory 205972 kb
Host smart-5ef0d774-c283-4e6a-b910-f6aa281d26e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356078558 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.356078558
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.539378738
Short name T429
Test name
Test status
Simulation time 11468583 ps
CPU time 0.79 seconds
Started Dec 31 12:55:39 PM PST 23
Finished Dec 31 12:55:43 PM PST 23
Peak memory 205956 kb
Host smart-9e974e73-52e8-4f0c-b97d-72c3cf570f72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539378738 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.539378738
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.207306165
Short name T434
Test name
Test status
Simulation time 82951613 ps
CPU time 0.78 seconds
Started Dec 31 12:55:10 PM PST 23
Finished Dec 31 12:55:17 PM PST 23
Peak memory 205740 kb
Host smart-0d70d75d-c719-41ef-b1e7-0d6ffb648212
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207306165 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.207306165
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.3327686089
Short name T153
Test name
Test status
Simulation time 36202308 ps
CPU time 0.81 seconds
Started Dec 31 12:55:38 PM PST 23
Finished Dec 31 12:55:43 PM PST 23
Peak memory 206032 kb
Host smart-494f8112-802d-4ae4-9192-6d0e7456a0ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327686089 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.3327686089
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.3557290098
Short name T454
Test name
Test status
Simulation time 67713709 ps
CPU time 0.84 seconds
Started Dec 31 12:55:37 PM PST 23
Finished Dec 31 12:55:43 PM PST 23
Peak memory 206036 kb
Host smart-21038542-c7e6-4d9b-9434-320ce965a208
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557290098 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.3557290098
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.3972754870
Short name T393
Test name
Test status
Simulation time 17989216 ps
CPU time 0.82 seconds
Started Dec 31 12:55:21 PM PST 23
Finished Dec 31 12:55:27 PM PST 23
Peak memory 206044 kb
Host smart-fa1f5204-d614-4925-b5fd-bb6deab82f03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972754870 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.3972754870
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3644484229
Short name T453
Test name
Test status
Simulation time 21484626 ps
CPU time 1.44 seconds
Started Dec 31 12:55:12 PM PST 23
Finished Dec 31 12:55:20 PM PST 23
Peak memory 214252 kb
Host smart-38f8332d-36ab-4037-8c6c-d210a23cda09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644484229 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.3644484229
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.3526426931
Short name T234
Test name
Test status
Simulation time 22095076 ps
CPU time 0.85 seconds
Started Dec 31 12:54:50 PM PST 23
Finished Dec 31 12:54:55 PM PST 23
Peak memory 206096 kb
Host smart-a44fc943-d831-4da3-b4bf-e5591d2112ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526426931 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.3526426931
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.2097462787
Short name T388
Test name
Test status
Simulation time 24398549 ps
CPU time 0.88 seconds
Started Dec 31 12:55:09 PM PST 23
Finished Dec 31 12:55:16 PM PST 23
Peak memory 205844 kb
Host smart-534805a1-3aa0-4c77-9782-b0403e2bd1a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097462787 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.2097462787
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3992801045
Short name T150
Test name
Test status
Simulation time 21292391 ps
CPU time 1.01 seconds
Started Dec 31 12:55:09 PM PST 23
Finished Dec 31 12:55:16 PM PST 23
Peak memory 205928 kb
Host smart-bb3782c9-f592-4199-9a06-1b8729cf218a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992801045 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.3992801045
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.1441812574
Short name T461
Test name
Test status
Simulation time 121636843 ps
CPU time 3.91 seconds
Started Dec 31 12:55:12 PM PST 23
Finished Dec 31 12:55:23 PM PST 23
Peak memory 214228 kb
Host smart-c264a337-bfcf-465f-815d-df7fe49655e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441812574 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.1441812574
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.450462467
Short name T445
Test name
Test status
Simulation time 92516840 ps
CPU time 1.44 seconds
Started Dec 31 12:55:12 PM PST 23
Finished Dec 31 12:55:20 PM PST 23
Peak memory 205940 kb
Host smart-51278f36-e50d-4e46-9dbc-7b9d9c0a8b28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450462467 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.450462467
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.29255586
Short name T29
Test name
Test status
Simulation time 35034733 ps
CPU time 1.08 seconds
Started Dec 31 12:55:18 PM PST 23
Finished Dec 31 12:55:24 PM PST 23
Peak memory 214252 kb
Host smart-61650726-f27f-4da9-a9bb-e4042fd11573
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29255586 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.29255586
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.2162979251
Short name T248
Test name
Test status
Simulation time 173084173 ps
CPU time 0.87 seconds
Started Dec 31 12:55:16 PM PST 23
Finished Dec 31 12:55:27 PM PST 23
Peak memory 205916 kb
Host smart-95612a8f-bef2-454c-8c70-8162190eabcf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162979251 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.2162979251
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3736013002
Short name T49
Test name
Test status
Simulation time 28061509 ps
CPU time 0.87 seconds
Started Dec 31 12:55:03 PM PST 23
Finished Dec 31 12:55:09 PM PST 23
Peak memory 205988 kb
Host smart-f85bc21f-9787-496b-bd80-7633cb6f1652
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736013002 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3736013002
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.3717870840
Short name T449
Test name
Test status
Simulation time 29326386 ps
CPU time 1.07 seconds
Started Dec 31 12:55:21 PM PST 23
Finished Dec 31 12:55:27 PM PST 23
Peak memory 205992 kb
Host smart-86dffe6e-f6ad-4a9e-b620-4175ca1dd694
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717870840 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.3717870840
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2140938938
Short name T245
Test name
Test status
Simulation time 115024888 ps
CPU time 2.62 seconds
Started Dec 31 12:55:12 PM PST 23
Finished Dec 31 12:55:21 PM PST 23
Peak memory 205976 kb
Host smart-9fe6da7f-4668-4bef-9b31-94f5ef77b07b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140938938 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.2140938938
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1404640911
Short name T418
Test name
Test status
Simulation time 12556452 ps
CPU time 0.97 seconds
Started Dec 31 12:54:50 PM PST 23
Finished Dec 31 12:54:55 PM PST 23
Peak memory 206076 kb
Host smart-1a27da7a-e805-44c8-b432-e0a03f6b8a01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404640911 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.1404640911
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.2433584612
Short name T379
Test name
Test status
Simulation time 36942875 ps
CPU time 0.87 seconds
Started Dec 31 12:55:05 PM PST 23
Finished Dec 31 12:55:17 PM PST 23
Peak memory 205996 kb
Host smart-6df2b017-0f36-4c8d-a602-1013be713e1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433584612 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.2433584612
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.1030978236
Short name T406
Test name
Test status
Simulation time 20997038 ps
CPU time 0.8 seconds
Started Dec 31 12:54:58 PM PST 23
Finished Dec 31 12:55:04 PM PST 23
Peak memory 206028 kb
Host smart-3a76ec94-4654-4e69-8421-8c04f346a621
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030978236 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.1030978236
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3896307259
Short name T403
Test name
Test status
Simulation time 16121786 ps
CPU time 0.98 seconds
Started Dec 31 12:55:31 PM PST 23
Finished Dec 31 12:55:35 PM PST 23
Peak memory 206008 kb
Host smart-ce3884a3-d5f3-4427-808a-7e9f3f5727a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896307259 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.3896307259
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.222390666
Short name T155
Test name
Test status
Simulation time 59830685 ps
CPU time 2.26 seconds
Started Dec 31 12:55:13 PM PST 23
Finished Dec 31 12:55:22 PM PST 23
Peak memory 214552 kb
Host smart-a927263f-f3ae-4f0c-9c62-7c03bf64bc46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222390666 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.222390666
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1674346642
Short name T441
Test name
Test status
Simulation time 154647718 ps
CPU time 1.97 seconds
Started Dec 31 12:55:09 PM PST 23
Finished Dec 31 12:55:17 PM PST 23
Peak memory 205996 kb
Host smart-60c4b5d7-ae40-401c-a4d6-5d48ff35c1b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674346642 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.1674346642
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2387145668
Short name T402
Test name
Test status
Simulation time 153902704 ps
CPU time 1.28 seconds
Started Dec 31 12:55:00 PM PST 23
Finished Dec 31 12:55:11 PM PST 23
Peak memory 214232 kb
Host smart-72f7b41c-2fda-4cfc-985c-6e5b0e4bd5ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387145668 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.2387145668
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.3993760770
Short name T456
Test name
Test status
Simulation time 24694305 ps
CPU time 0.83 seconds
Started Dec 31 12:55:13 PM PST 23
Finished Dec 31 12:55:21 PM PST 23
Peak memory 205984 kb
Host smart-317f850f-f168-49c9-b2c6-7b80ebe3f219
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993760770 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.3993760770
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.1738655393
Short name T452
Test name
Test status
Simulation time 15061759 ps
CPU time 0.85 seconds
Started Dec 31 12:55:01 PM PST 23
Finished Dec 31 12:55:08 PM PST 23
Peak memory 205936 kb
Host smart-b7b932ac-da24-4d8c-b72a-f8094bc148be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738655393 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1738655393
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2899149724
Short name T144
Test name
Test status
Simulation time 25448602 ps
CPU time 1.13 seconds
Started Dec 31 12:55:11 PM PST 23
Finished Dec 31 12:55:19 PM PST 23
Peak memory 206052 kb
Host smart-3810e7d3-249e-482c-8bbd-e8b0081c5b95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899149724 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.2899149724
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.996411542
Short name T431
Test name
Test status
Simulation time 107456622 ps
CPU time 2.63 seconds
Started Dec 31 12:55:14 PM PST 23
Finished Dec 31 12:55:24 PM PST 23
Peak memory 214356 kb
Host smart-bd9174cd-c1bb-42e8-93e0-25a24020baf2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996411542 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.996411542
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2187303275
Short name T281
Test name
Test status
Simulation time 638828049 ps
CPU time 2.47 seconds
Started Dec 31 12:55:10 PM PST 23
Finished Dec 31 12:55:19 PM PST 23
Peak memory 206024 kb
Host smart-ccf86dc9-0417-4f6f-bfd5-1de59feff60d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187303275 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.2187303275
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1026631933
Short name T425
Test name
Test status
Simulation time 240976261 ps
CPU time 1.1 seconds
Started Dec 31 12:55:10 PM PST 23
Finished Dec 31 12:55:17 PM PST 23
Peak memory 214228 kb
Host smart-ffeb0fc4-7cc0-4627-b280-f8949f672376
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026631933 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.1026631933
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.3602301167
Short name T170
Test name
Test status
Simulation time 15828930 ps
CPU time 0.91 seconds
Started Dec 31 12:55:15 PM PST 23
Finished Dec 31 12:55:22 PM PST 23
Peak memory 205948 kb
Host smart-5d241ee2-b835-461c-94de-f09c6e0abcb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602301167 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3602301167
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.8576855
Short name T405
Test name
Test status
Simulation time 53045740 ps
CPU time 0.89 seconds
Started Dec 31 12:55:05 PM PST 23
Finished Dec 31 12:55:11 PM PST 23
Peak memory 205980 kb
Host smart-077b6589-8256-4ddf-879f-389285ed738a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8576855 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.8576855
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2831826930
Short name T450
Test name
Test status
Simulation time 36813493 ps
CPU time 1.02 seconds
Started Dec 31 12:55:04 PM PST 23
Finished Dec 31 12:55:10 PM PST 23
Peak memory 206004 kb
Host smart-0e4e0e7c-7626-4edf-8b0f-435c170f825c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831826930 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.2831826930
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.3725986473
Short name T231
Test name
Test status
Simulation time 252370347 ps
CPU time 2.49 seconds
Started Dec 31 12:54:56 PM PST 23
Finished Dec 31 12:55:04 PM PST 23
Peak memory 214228 kb
Host smart-262819a5-4af0-46da-982f-68232b22e81d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725986473 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.3725986473
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3264985781
Short name T420
Test name
Test status
Simulation time 123111983 ps
CPU time 2.07 seconds
Started Dec 31 12:55:21 PM PST 23
Finished Dec 31 12:55:32 PM PST 23
Peak memory 206060 kb
Host smart-5293bf65-79c4-4e8c-915c-e80ea6f2efb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264985781 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.3264985781
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.4006766800
Short name T707
Test name
Test status
Simulation time 31633442 ps
CPU time 0.93 seconds
Started Dec 31 12:52:07 PM PST 23
Finished Dec 31 12:52:21 PM PST 23
Peak memory 205944 kb
Host smart-55de3e49-06be-4691-a4c6-b85d3b7ea406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006766800 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.4006766800
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_err.2229242000
Short name T226
Test name
Test status
Simulation time 20211869 ps
CPU time 0.99 seconds
Started Dec 31 12:52:01 PM PST 23
Finished Dec 31 12:52:10 PM PST 23
Peak memory 215392 kb
Host smart-0430c3d8-da0c-464e-ae6a-2832ebb3068c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229242000 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.2229242000
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.1461990542
Short name T558
Test name
Test status
Simulation time 56852642 ps
CPU time 0.93 seconds
Started Dec 31 12:52:03 PM PST 23
Finished Dec 31 12:52:11 PM PST 23
Peak memory 204968 kb
Host smart-eb4de57e-8569-4acb-86f3-b48ced5c7b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461990542 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.1461990542
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_regwen.2571497095
Short name T342
Test name
Test status
Simulation time 15443579 ps
CPU time 0.93 seconds
Started Dec 31 12:52:08 PM PST 23
Finished Dec 31 12:52:23 PM PST 23
Peak memory 204884 kb
Host smart-955de01e-c069-4f4a-830c-749e3c686a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571497095 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.2571497095
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.4192467091
Short name T25
Test name
Test status
Simulation time 541633103 ps
CPU time 3.74 seconds
Started Dec 31 12:52:10 PM PST 23
Finished Dec 31 12:52:29 PM PST 23
Peak memory 232936 kb
Host smart-03f4e91f-7838-4b55-b79b-0199a09f5b0d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192467091 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.4192467091
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.2199783828
Short name T473
Test name
Test status
Simulation time 45881386 ps
CPU time 0.86 seconds
Started Dec 31 12:52:02 PM PST 23
Finished Dec 31 12:52:11 PM PST 23
Peak memory 204532 kb
Host smart-42312415-7965-4d56-8dbb-00c47b760439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199783828 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.2199783828
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.12708943
Short name T255
Test name
Test status
Simulation time 171730773 ps
CPU time 3.68 seconds
Started Dec 31 12:52:10 PM PST 23
Finished Dec 31 12:52:29 PM PST 23
Peak memory 206032 kb
Host smart-6a9fc20c-8e82-4ad5-b74c-0ed38031dcdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12708943 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.12708943
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_alert.1842312727
Short name T270
Test name
Test status
Simulation time 18209879 ps
CPU time 0.96 seconds
Started Dec 31 12:52:05 PM PST 23
Finished Dec 31 12:52:24 PM PST 23
Peak memory 205908 kb
Host smart-d2254105-26be-4c2a-9c96-1e71272b4353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842312727 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1842312727
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.93599671
Short name T115
Test name
Test status
Simulation time 30097415 ps
CPU time 0.87 seconds
Started Dec 31 12:52:04 PM PST 23
Finished Dec 31 12:52:12 PM PST 23
Peak memory 204588 kb
Host smart-3a649699-5d93-4310-bcc8-a679795602cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93599671 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.93599671
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.1952930984
Short name T221
Test name
Test status
Simulation time 12006524 ps
CPU time 0.85 seconds
Started Dec 31 12:52:06 PM PST 23
Finished Dec 31 12:52:20 PM PST 23
Peak memory 214264 kb
Host smart-f183ced0-0cdb-4537-aea6-4ff81f0b4d1f
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952930984 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.1952930984
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.2888994532
Short name T725
Test name
Test status
Simulation time 22467710 ps
CPU time 0.98 seconds
Started Dec 31 12:52:14 PM PST 23
Finished Dec 31 12:52:29 PM PST 23
Peak memory 214344 kb
Host smart-737875cd-d96e-40fc-bfbf-3019aa44f4b4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888994532 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.2888994532
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.3588671814
Short name T674
Test name
Test status
Simulation time 26129840 ps
CPU time 1.27 seconds
Started Dec 31 12:52:06 PM PST 23
Finished Dec 31 12:52:20 PM PST 23
Peak memory 215968 kb
Host smart-0a424551-dd6f-48fb-a64b-a286d03c590c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588671814 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.3588671814
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.3541509546
Short name T657
Test name
Test status
Simulation time 50210075 ps
CPU time 0.92 seconds
Started Dec 31 12:52:10 PM PST 23
Finished Dec 31 12:52:26 PM PST 23
Peak memory 205196 kb
Host smart-6ac1e219-b341-4e16-8532-e5bcff5ae20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541509546 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.3541509546
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.2240692950
Short name T703
Test name
Test status
Simulation time 23755643 ps
CPU time 0.91 seconds
Started Dec 31 12:52:10 PM PST 23
Finished Dec 31 12:52:25 PM PST 23
Peak memory 214516 kb
Host smart-2555a536-3bb6-4a44-8b33-999585856e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240692950 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.2240692950
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.1750930954
Short name T343
Test name
Test status
Simulation time 13633904 ps
CPU time 0.9 seconds
Started Dec 31 12:52:07 PM PST 23
Finished Dec 31 12:52:22 PM PST 23
Peak memory 204712 kb
Host smart-de5337a0-8073-41c7-b6f5-c4fa1de70f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750930954 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.1750930954
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.2972144655
Short name T26
Test name
Test status
Simulation time 770545994 ps
CPU time 3.58 seconds
Started Dec 31 12:52:15 PM PST 23
Finished Dec 31 12:52:32 PM PST 23
Peak memory 232092 kb
Host smart-b2fc2dc0-6f0a-4edc-b272-8cce53d3b848
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972144655 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.2972144655
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.3451796438
Short name T514
Test name
Test status
Simulation time 37072241 ps
CPU time 0.81 seconds
Started Dec 31 12:52:12 PM PST 23
Finished Dec 31 12:52:27 PM PST 23
Peak memory 204688 kb
Host smart-1830f3f9-dba7-471b-ad7d-e8f0ebf67065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451796438 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.3451796438
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.2114755992
Short name T699
Test name
Test status
Simulation time 155798620 ps
CPU time 1.87 seconds
Started Dec 31 12:52:12 PM PST 23
Finished Dec 31 12:52:29 PM PST 23
Peak memory 205972 kb
Host smart-ff908523-176a-4edb-aa8e-442e1e13ee7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114755992 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.2114755992
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.743339153
Short name T654
Test name
Test status
Simulation time 68408045362 ps
CPU time 1431.79 seconds
Started Dec 31 12:52:11 PM PST 23
Finished Dec 31 01:16:18 PM PST 23
Peak memory 217012 kb
Host smart-612b35f1-c441-41bc-8080-5f96f4d5ea6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743339153 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.743339153
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.1728332229
Short name T344
Test name
Test status
Simulation time 62391633 ps
CPU time 0.96 seconds
Started Dec 31 12:52:13 PM PST 23
Finished Dec 31 12:52:29 PM PST 23
Peak memory 205312 kb
Host smart-2460e917-2f04-4ec7-9e64-ce80c93a0d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728332229 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.1728332229
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.3528627924
Short name T861
Test name
Test status
Simulation time 14176869 ps
CPU time 0.88 seconds
Started Dec 31 12:52:30 PM PST 23
Finished Dec 31 12:52:40 PM PST 23
Peak memory 204492 kb
Host smart-868525cd-834e-4d2a-bca0-052ca5f4da07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528627924 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.3528627924
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.1144584797
Short name T669
Test name
Test status
Simulation time 22817150 ps
CPU time 1.02 seconds
Started Dec 31 12:52:14 PM PST 23
Finished Dec 31 12:52:30 PM PST 23
Peak memory 214400 kb
Host smart-0bde7adf-016a-494c-8dec-60c7d64282cc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144584797 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.1144584797
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.856891062
Short name T264
Test name
Test status
Simulation time 19741437 ps
CPU time 1.09 seconds
Started Dec 31 12:52:14 PM PST 23
Finished Dec 31 12:52:30 PM PST 23
Peak memory 214404 kb
Host smart-2653d22b-26c8-4227-a812-3ac2148f12c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856891062 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.856891062
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_intr.2047361237
Short name T650
Test name
Test status
Simulation time 20429293 ps
CPU time 0.99 seconds
Started Dec 31 12:52:30 PM PST 23
Finished Dec 31 12:52:40 PM PST 23
Peak memory 214432 kb
Host smart-beef6e38-08e5-47cf-8c10-99be9adbe03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047361237 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.2047361237
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.1500415651
Short name T831
Test name
Test status
Simulation time 12558758 ps
CPU time 0.86 seconds
Started Dec 31 12:52:10 PM PST 23
Finished Dec 31 12:52:26 PM PST 23
Peak memory 204688 kb
Host smart-18614ad4-eef5-4487-a819-cc02236e9592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500415651 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1500415651
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.1891555405
Short name T819
Test name
Test status
Simulation time 155306870 ps
CPU time 1.45 seconds
Started Dec 31 12:52:09 PM PST 23
Finished Dec 31 12:52:25 PM PST 23
Peak memory 205320 kb
Host smart-5b8d5b87-0fb2-483d-b69d-b0a05c10527b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891555405 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.1891555405
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.2080089229
Short name T619
Test name
Test status
Simulation time 169398639809 ps
CPU time 457.77 seconds
Started Dec 31 12:52:08 PM PST 23
Finished Dec 31 01:00:00 PM PST 23
Peak memory 215424 kb
Host smart-2957b479-bec5-4aa5-9456-3f2d144fa843
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080089229 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.2080089229
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/101.edn_genbits.988383947
Short name T972
Test name
Test status
Simulation time 36562178 ps
CPU time 0.9 seconds
Started Dec 31 12:53:46 PM PST 23
Finished Dec 31 12:54:00 PM PST 23
Peak memory 205600 kb
Host smart-a0a0be18-9682-49fa-9bb0-7f7e6fc35e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988383947 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.988383947
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.2111581765
Short name T477
Test name
Test status
Simulation time 36490331 ps
CPU time 1.03 seconds
Started Dec 31 12:54:45 PM PST 23
Finished Dec 31 12:54:49 PM PST 23
Peak memory 205132 kb
Host smart-154edc6b-fa2f-46fb-9347-e8ca28dcdb29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111581765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.2111581765
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.1331894009
Short name T919
Test name
Test status
Simulation time 66522383 ps
CPU time 1.06 seconds
Started Dec 31 12:53:35 PM PST 23
Finished Dec 31 12:53:49 PM PST 23
Peak memory 205452 kb
Host smart-f40d63d7-703d-4669-81e2-0bf914718dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331894009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.1331894009
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.511792630
Short name T23
Test name
Test status
Simulation time 46788309 ps
CPU time 0.89 seconds
Started Dec 31 12:54:00 PM PST 23
Finished Dec 31 12:54:11 PM PST 23
Peak memory 205092 kb
Host smart-d7483c2a-c2b9-4f88-a589-f2ab32bcdaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511792630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.511792630
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.4110328561
Short name T638
Test name
Test status
Simulation time 40036492 ps
CPU time 0.9 seconds
Started Dec 31 12:54:27 PM PST 23
Finished Dec 31 12:54:29 PM PST 23
Peak memory 204880 kb
Host smart-9afa4b78-c48d-4143-ad72-25ecda62694e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110328561 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.4110328561
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.3139143096
Short name T38
Test name
Test status
Simulation time 167256347 ps
CPU time 1.15 seconds
Started Dec 31 12:54:43 PM PST 23
Finished Dec 31 12:54:47 PM PST 23
Peak memory 205428 kb
Host smart-c00932ae-728f-4ea9-9169-52d45f203919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139143096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.3139143096
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.320564461
Short name T617
Test name
Test status
Simulation time 129862350 ps
CPU time 1.04 seconds
Started Dec 31 12:53:58 PM PST 23
Finished Dec 31 12:54:08 PM PST 23
Peak memory 205348 kb
Host smart-93962238-be58-4f21-912e-022b3d6a3b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320564461 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.320564461
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.2060408628
Short name T493
Test name
Test status
Simulation time 224859506 ps
CPU time 3.03 seconds
Started Dec 31 12:54:25 PM PST 23
Finished Dec 31 12:54:30 PM PST 23
Peak memory 214108 kb
Host smart-557c3ac1-3db5-4a03-a8b2-1f22bbc64735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060408628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.2060408628
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.979988994
Short name T545
Test name
Test status
Simulation time 31699091 ps
CPU time 0.91 seconds
Started Dec 31 12:53:48 PM PST 23
Finished Dec 31 12:54:02 PM PST 23
Peak memory 205084 kb
Host smart-c17d8d68-ce8e-4719-966b-4fa469e431cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979988994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.979988994
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.1421833710
Short name T776
Test name
Test status
Simulation time 21093036 ps
CPU time 1 seconds
Started Dec 31 12:52:15 PM PST 23
Finished Dec 31 12:52:30 PM PST 23
Peak memory 205188 kb
Host smart-0a454206-faf4-475b-bcf8-fc42ff7ae6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421833710 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.1421833710
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.2674284976
Short name T655
Test name
Test status
Simulation time 15114211 ps
CPU time 0.89 seconds
Started Dec 31 12:52:18 PM PST 23
Finished Dec 31 12:52:33 PM PST 23
Peak memory 205132 kb
Host smart-7befdb88-62be-43b4-8440-ce28eb776564
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674284976 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.2674284976
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.3675756038
Short name T552
Test name
Test status
Simulation time 152181139 ps
CPU time 0.98 seconds
Started Dec 31 12:52:23 PM PST 23
Finished Dec 31 12:52:36 PM PST 23
Peak memory 214416 kb
Host smart-48a79888-a766-4472-8807-dda8f2f230dc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675756038 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.3675756038
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.149040657
Short name T599
Test name
Test status
Simulation time 37548586 ps
CPU time 0.99 seconds
Started Dec 31 12:52:13 PM PST 23
Finished Dec 31 12:52:29 PM PST 23
Peak memory 215736 kb
Host smart-26cf887d-1ae6-4980-b91f-542e3dbd8596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149040657 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.149040657
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.3454625634
Short name T939
Test name
Test status
Simulation time 36481655 ps
CPU time 0.99 seconds
Started Dec 31 12:52:23 PM PST 23
Finished Dec 31 12:52:36 PM PST 23
Peak memory 205396 kb
Host smart-c93ff123-5618-4d6f-94f8-2a8ab76a31aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454625634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.3454625634
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.241742108
Short name T886
Test name
Test status
Simulation time 26036410 ps
CPU time 0.91 seconds
Started Dec 31 12:52:13 PM PST 23
Finished Dec 31 12:52:29 PM PST 23
Peak memory 214480 kb
Host smart-0a2e3f45-b165-4233-b6e9-1fe6cb127371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241742108 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.241742108
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.3920642653
Short name T76
Test name
Test status
Simulation time 11346330 ps
CPU time 0.85 seconds
Started Dec 31 12:52:20 PM PST 23
Finished Dec 31 12:52:34 PM PST 23
Peak memory 204792 kb
Host smart-d699b2a7-bd02-416e-a4d3-4b91b5e95426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920642653 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.3920642653
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.1326040295
Short name T779
Test name
Test status
Simulation time 172381248 ps
CPU time 1.52 seconds
Started Dec 31 12:52:21 PM PST 23
Finished Dec 31 12:52:35 PM PST 23
Peak memory 205200 kb
Host smart-6acfd0ca-2bea-46ab-9329-6120649d56f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326040295 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1326040295
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.2391557254
Short name T485
Test name
Test status
Simulation time 57485647941 ps
CPU time 380.5 seconds
Started Dec 31 12:52:26 PM PST 23
Finished Dec 31 12:58:57 PM PST 23
Peak memory 214592 kb
Host smart-1f6ddd77-f64d-45b6-b7de-d1faf49ccd7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391557254 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.2391557254
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.963295682
Short name T783
Test name
Test status
Simulation time 22231320 ps
CPU time 1.08 seconds
Started Dec 31 12:53:59 PM PST 23
Finished Dec 31 12:54:10 PM PST 23
Peak memory 214132 kb
Host smart-842e796a-4849-4a45-b7ca-4b4d35fe90a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963295682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.963295682
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.3102491045
Short name T836
Test name
Test status
Simulation time 11911850 ps
CPU time 0.87 seconds
Started Dec 31 12:54:03 PM PST 23
Finished Dec 31 12:54:12 PM PST 23
Peak memory 204920 kb
Host smart-32191d89-446a-4fe9-8ee3-03d692545946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102491045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.3102491045
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.273284255
Short name T792
Test name
Test status
Simulation time 29843319 ps
CPU time 0.98 seconds
Started Dec 31 12:53:49 PM PST 23
Finished Dec 31 12:54:02 PM PST 23
Peak memory 205736 kb
Host smart-2fb299ff-4896-4bac-b422-5338080918a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273284255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.273284255
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.706053396
Short name T35
Test name
Test status
Simulation time 83167459 ps
CPU time 1.06 seconds
Started Dec 31 12:54:15 PM PST 23
Finished Dec 31 12:54:18 PM PST 23
Peak memory 205436 kb
Host smart-b7cb0c13-998a-416e-935c-0e298e661fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706053396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.706053396
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.4074707414
Short name T579
Test name
Test status
Simulation time 400040755 ps
CPU time 3.56 seconds
Started Dec 31 12:53:52 PM PST 23
Finished Dec 31 12:54:07 PM PST 23
Peak memory 214112 kb
Host smart-4e23838c-b70f-443f-a4eb-6abd45b490b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074707414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.4074707414
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.1868732595
Short name T645
Test name
Test status
Simulation time 301439521 ps
CPU time 1.01 seconds
Started Dec 31 12:54:10 PM PST 23
Finished Dec 31 12:54:15 PM PST 23
Peak memory 204884 kb
Host smart-c22e7f00-7c6c-49c4-a086-774f61e2da1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868732595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.1868732595
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.3149076645
Short name T539
Test name
Test status
Simulation time 245695001 ps
CPU time 1.21 seconds
Started Dec 31 12:54:06 PM PST 23
Finished Dec 31 12:54:14 PM PST 23
Peak memory 214180 kb
Host smart-28496e0a-8580-4885-9077-1d384eceadb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149076645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.3149076645
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.3255559949
Short name T83
Test name
Test status
Simulation time 21016001 ps
CPU time 1.09 seconds
Started Dec 31 12:53:58 PM PST 23
Finished Dec 31 12:54:09 PM PST 23
Peak memory 205312 kb
Host smart-277116b5-2432-4fa4-b0cb-b0a0084cb5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255559949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.3255559949
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.4186738628
Short name T706
Test name
Test status
Simulation time 17514701 ps
CPU time 1.05 seconds
Started Dec 31 12:53:44 PM PST 23
Finished Dec 31 12:53:57 PM PST 23
Peak memory 205624 kb
Host smart-dbf6e543-d8b5-4ad5-ae05-4df4e7993e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186738628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.4186738628
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.2684838044
Short name T947
Test name
Test status
Simulation time 150018233 ps
CPU time 2.21 seconds
Started Dec 31 12:54:44 PM PST 23
Finished Dec 31 12:54:49 PM PST 23
Peak memory 214072 kb
Host smart-aa5083e8-5bc5-46bf-b580-804dbf2e2691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684838044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.2684838044
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert_test.2771363582
Short name T740
Test name
Test status
Simulation time 63666745 ps
CPU time 0.82 seconds
Started Dec 31 12:52:19 PM PST 23
Finished Dec 31 12:52:34 PM PST 23
Peak memory 204384 kb
Host smart-7679cf06-32bc-4023-b5b6-8aafa5fb1ca6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771363582 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2771363582
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.1536780805
Short name T887
Test name
Test status
Simulation time 51874836 ps
CPU time 1.03 seconds
Started Dec 31 12:52:24 PM PST 23
Finished Dec 31 12:52:36 PM PST 23
Peak memory 214504 kb
Host smart-c7797f23-f13e-4c33-bdad-dc26eff3d978
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536780805 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.1536780805
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.3220881440
Short name T262
Test name
Test status
Simulation time 34685543 ps
CPU time 0.87 seconds
Started Dec 31 12:52:17 PM PST 23
Finished Dec 31 12:52:32 PM PST 23
Peak memory 214704 kb
Host smart-c4166457-108e-46a5-9c41-1f3850e0821f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220881440 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.3220881440
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.3210702488
Short name T813
Test name
Test status
Simulation time 41511954 ps
CPU time 0.94 seconds
Started Dec 31 12:52:19 PM PST 23
Finished Dec 31 12:52:33 PM PST 23
Peak memory 205572 kb
Host smart-dea982fd-3471-42a3-887f-c7323d357fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210702488 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.3210702488
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_smoke.3674572273
Short name T504
Test name
Test status
Simulation time 49998524 ps
CPU time 0.84 seconds
Started Dec 31 12:52:15 PM PST 23
Finished Dec 31 12:52:30 PM PST 23
Peak memory 204916 kb
Host smart-8c02d82e-6573-49d6-bce5-03914c36ed50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674572273 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.3674572273
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.3277041235
Short name T975
Test name
Test status
Simulation time 57899271 ps
CPU time 1.73 seconds
Started Dec 31 12:52:12 PM PST 23
Finished Dec 31 12:52:28 PM PST 23
Peak memory 205872 kb
Host smart-dbcb5621-7b15-4c10-a812-90c33744a4c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277041235 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.3277041235
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.1277221676
Short name T566
Test name
Test status
Simulation time 90812295613 ps
CPU time 1065.33 seconds
Started Dec 31 12:52:18 PM PST 23
Finished Dec 31 01:10:17 PM PST 23
Peak memory 217196 kb
Host smart-58a77063-14a9-4ecc-99df-b49a48e565a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277221676 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.1277221676
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.1600393397
Short name T308
Test name
Test status
Simulation time 45015859 ps
CPU time 0.93 seconds
Started Dec 31 12:54:29 PM PST 23
Finished Dec 31 12:54:32 PM PST 23
Peak memory 205360 kb
Host smart-8f1d9be4-e2db-4a8b-ba6e-195c38507d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600393397 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.1600393397
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.692714747
Short name T800
Test name
Test status
Simulation time 68562800 ps
CPU time 0.95 seconds
Started Dec 31 12:54:43 PM PST 23
Finished Dec 31 12:54:46 PM PST 23
Peak memory 205332 kb
Host smart-e06db454-7502-46db-8ea7-6167cbb51da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692714747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.692714747
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.1617634514
Short name T601
Test name
Test status
Simulation time 195113705 ps
CPU time 2.48 seconds
Started Dec 31 12:53:57 PM PST 23
Finished Dec 31 12:54:09 PM PST 23
Peak memory 214068 kb
Host smart-13c4f99a-7b0c-4235-8288-d258d2847431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617634514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.1617634514
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.601124356
Short name T834
Test name
Test status
Simulation time 29400699 ps
CPU time 0.98 seconds
Started Dec 31 12:53:49 PM PST 23
Finished Dec 31 12:54:02 PM PST 23
Peak memory 205036 kb
Host smart-91153714-3709-4d3e-b3d3-2d1d5cf3b60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601124356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.601124356
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.3155829771
Short name T587
Test name
Test status
Simulation time 38860067 ps
CPU time 1.25 seconds
Started Dec 31 12:54:49 PM PST 23
Finished Dec 31 12:54:55 PM PST 23
Peak memory 205736 kb
Host smart-bc311cd7-cc59-47fd-b7a5-ad7c4316c0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155829771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.3155829771
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.3077544540
Short name T929
Test name
Test status
Simulation time 131078227 ps
CPU time 3.1 seconds
Started Dec 31 12:54:43 PM PST 23
Finished Dec 31 12:54:49 PM PST 23
Peak memory 214108 kb
Host smart-425abd91-3ee7-4849-b1fd-50cf2b3a8b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077544540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.3077544540
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.48105518
Short name T528
Test name
Test status
Simulation time 19918950 ps
CPU time 0.97 seconds
Started Dec 31 12:54:29 PM PST 23
Finished Dec 31 12:54:32 PM PST 23
Peak memory 205320 kb
Host smart-95f845c4-6df6-48c4-b4e6-16746ba62683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48105518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.48105518
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.1293110362
Short name T769
Test name
Test status
Simulation time 99422065 ps
CPU time 1.08 seconds
Started Dec 31 12:54:03 PM PST 23
Finished Dec 31 12:54:12 PM PST 23
Peak memory 214160 kb
Host smart-e1c38fa2-d9fe-4caa-9b0a-36508f0446a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293110362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.1293110362
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.3260537102
Short name T620
Test name
Test status
Simulation time 17821520 ps
CPU time 1.11 seconds
Started Dec 31 12:54:27 PM PST 23
Finished Dec 31 12:54:30 PM PST 23
Peak memory 205632 kb
Host smart-cdf997e7-9abd-417b-b581-e2e2799280a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260537102 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.3260537102
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.1404634323
Short name T802
Test name
Test status
Simulation time 58939366 ps
CPU time 0.96 seconds
Started Dec 31 12:52:30 PM PST 23
Finished Dec 31 12:52:40 PM PST 23
Peak memory 205224 kb
Host smart-44127179-a209-4721-9993-c95ba9cd5861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404634323 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.1404634323
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.3596827982
Short name T640
Test name
Test status
Simulation time 15699633 ps
CPU time 0.85 seconds
Started Dec 31 12:52:26 PM PST 23
Finished Dec 31 12:52:37 PM PST 23
Peak memory 204472 kb
Host smart-be9ccffc-7942-4612-aa92-9a169ba3b5f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596827982 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3596827982
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.555091765
Short name T806
Test name
Test status
Simulation time 32846313 ps
CPU time 0.81 seconds
Started Dec 31 12:52:23 PM PST 23
Finished Dec 31 12:52:35 PM PST 23
Peak memory 214244 kb
Host smart-348da1a5-e30c-4b9a-9211-e77eb6a71033
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555091765 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.555091765
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_err.2369668011
Short name T554
Test name
Test status
Simulation time 18050422 ps
CPU time 1.43 seconds
Started Dec 31 12:52:14 PM PST 23
Finished Dec 31 12:52:30 PM PST 23
Peak memory 221732 kb
Host smart-c6da5add-9a96-457c-a286-82ec1b4569c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369668011 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.2369668011
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.4064760306
Short name T667
Test name
Test status
Simulation time 76268385 ps
CPU time 0.97 seconds
Started Dec 31 12:52:27 PM PST 23
Finished Dec 31 12:52:38 PM PST 23
Peak memory 204832 kb
Host smart-05e7265b-0869-4f67-83c8-8f5b34f089b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064760306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.4064760306
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.4140606871
Short name T105
Test name
Test status
Simulation time 19508277 ps
CPU time 1.06 seconds
Started Dec 31 12:52:19 PM PST 23
Finished Dec 31 12:52:33 PM PST 23
Peak memory 214452 kb
Host smart-c1cac2ae-acbb-4924-8a7a-f52ca6160ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140606871 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.4140606871
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.1359664557
Short name T632
Test name
Test status
Simulation time 14036702 ps
CPU time 0.92 seconds
Started Dec 31 12:52:19 PM PST 23
Finished Dec 31 12:52:33 PM PST 23
Peak memory 204852 kb
Host smart-66c0889b-d6a5-4501-b652-a6de2cb23f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359664557 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.1359664557
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.3908755650
Short name T285
Test name
Test status
Simulation time 440078261 ps
CPU time 3.26 seconds
Started Dec 31 12:52:13 PM PST 23
Finished Dec 31 12:52:31 PM PST 23
Peak memory 205776 kb
Host smart-eee6ff89-b203-4054-a804-d10bf01e6dcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908755650 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.3908755650
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.538256492
Short name T700
Test name
Test status
Simulation time 97550656417 ps
CPU time 599.8 seconds
Started Dec 31 12:52:29 PM PST 23
Finished Dec 31 01:02:38 PM PST 23
Peak memory 215432 kb
Host smart-b0bcd831-91f6-44ef-bc86-4d5c9decc4b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538256492 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.538256492
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.3587309499
Short name T966
Test name
Test status
Simulation time 277526398 ps
CPU time 2.44 seconds
Started Dec 31 12:53:38 PM PST 23
Finished Dec 31 12:53:53 PM PST 23
Peak memory 214156 kb
Host smart-de84043a-48c5-456a-b535-c6ba26a5ea14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587309499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.3587309499
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.1129309987
Short name T309
Test name
Test status
Simulation time 28767635 ps
CPU time 1.07 seconds
Started Dec 31 12:54:37 PM PST 23
Finished Dec 31 12:54:41 PM PST 23
Peak memory 205508 kb
Host smart-365e8d37-2861-4955-87f4-77e0763aa7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129309987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.1129309987
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.1448169718
Short name T798
Test name
Test status
Simulation time 13782327 ps
CPU time 0.92 seconds
Started Dec 31 12:55:07 PM PST 23
Finished Dec 31 12:55:13 PM PST 23
Peak memory 205036 kb
Host smart-43e0337a-52df-4f81-a4e2-a0c614a9ea60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448169718 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.1448169718
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.2472471974
Short name T907
Test name
Test status
Simulation time 36214705 ps
CPU time 0.91 seconds
Started Dec 31 12:53:48 PM PST 23
Finished Dec 31 12:54:01 PM PST 23
Peak memory 205280 kb
Host smart-c8c5ceb2-0f3b-45c3-99e5-3da59ea49117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472471974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.2472471974
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.153401790
Short name T644
Test name
Test status
Simulation time 15530562 ps
CPU time 0.9 seconds
Started Dec 31 12:55:08 PM PST 23
Finished Dec 31 12:55:20 PM PST 23
Peak memory 204932 kb
Host smart-77f4c6a1-8bc5-4c15-8896-6252d3f48b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153401790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.153401790
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.3980490052
Short name T871
Test name
Test status
Simulation time 19449228 ps
CPU time 1.17 seconds
Started Dec 31 12:54:27 PM PST 23
Finished Dec 31 12:54:30 PM PST 23
Peak memory 205556 kb
Host smart-7cf82bea-e5eb-47fb-9afe-8b55303e7b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980490052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.3980490052
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.3209301670
Short name T591
Test name
Test status
Simulation time 32816064 ps
CPU time 0.97 seconds
Started Dec 31 12:55:13 PM PST 23
Finished Dec 31 12:55:21 PM PST 23
Peak memory 205404 kb
Host smart-79ad4cf6-2d44-4634-88a5-b966c21d0cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209301670 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.3209301670
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.2433460230
Short name T805
Test name
Test status
Simulation time 276355914 ps
CPU time 3.35 seconds
Started Dec 31 12:54:20 PM PST 23
Finished Dec 31 12:54:25 PM PST 23
Peak memory 214192 kb
Host smart-060cc889-a6da-47d9-b642-dcd749d96dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433460230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.2433460230
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.3598597497
Short name T693
Test name
Test status
Simulation time 32105494 ps
CPU time 0.94 seconds
Started Dec 31 12:54:54 PM PST 23
Finished Dec 31 12:55:00 PM PST 23
Peak memory 205036 kb
Host smart-7617fbfe-5b5e-4c40-bc63-176b521cbfa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598597497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.3598597497
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.68398881
Short name T345
Test name
Test status
Simulation time 20368372 ps
CPU time 0.99 seconds
Started Dec 31 12:52:26 PM PST 23
Finished Dec 31 12:52:37 PM PST 23
Peak memory 205176 kb
Host smart-8bbf3314-f1f7-485c-996a-53702f39dae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68398881 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.68398881
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.1781548293
Short name T862
Test name
Test status
Simulation time 18340859 ps
CPU time 0.96 seconds
Started Dec 31 12:52:26 PM PST 23
Finished Dec 31 12:52:37 PM PST 23
Peak memory 204632 kb
Host smart-c02eadd1-a81b-41f6-86a0-80a9985b1a16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781548293 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.1781548293
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_err.2955826506
Short name T796
Test name
Test status
Simulation time 31614026 ps
CPU time 1.34 seconds
Started Dec 31 12:52:29 PM PST 23
Finished Dec 31 12:52:40 PM PST 23
Peak memory 214612 kb
Host smart-5d2bf9e8-1ef3-4798-ab20-51a9e6307781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955826506 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.2955826506
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.3676588787
Short name T33
Test name
Test status
Simulation time 85416036 ps
CPU time 0.98 seconds
Started Dec 31 12:52:32 PM PST 23
Finished Dec 31 12:52:42 PM PST 23
Peak memory 205480 kb
Host smart-bc72a8d9-94c7-461e-9d69-6a13465e01d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676588787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.3676588787
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.887782129
Short name T3
Test name
Test status
Simulation time 21390243 ps
CPU time 0.97 seconds
Started Dec 31 12:52:31 PM PST 23
Finished Dec 31 12:52:41 PM PST 23
Peak memory 214448 kb
Host smart-63acaa8a-ad9a-49e3-bd82-6511bdb251e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887782129 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.887782129
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.3003527236
Short name T474
Test name
Test status
Simulation time 34505635 ps
CPU time 0.89 seconds
Started Dec 31 12:52:33 PM PST 23
Finished Dec 31 12:52:42 PM PST 23
Peak memory 204864 kb
Host smart-e9fe4103-8a21-45b5-8077-e7fc78d0bcee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003527236 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.3003527236
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.2424695136
Short name T784
Test name
Test status
Simulation time 553235529 ps
CPU time 3.29 seconds
Started Dec 31 12:52:28 PM PST 23
Finished Dec 31 12:52:41 PM PST 23
Peak memory 205760 kb
Host smart-14813708-3e16-4a4d-853e-66767888f7af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424695136 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.2424695136
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.969090259
Short name T318
Test name
Test status
Simulation time 107526958535 ps
CPU time 1204.53 seconds
Started Dec 31 12:52:35 PM PST 23
Finished Dec 31 01:12:49 PM PST 23
Peak memory 215832 kb
Host smart-9a7abb67-e197-4739-ba42-e167b6dd5a59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969090259 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.969090259
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.1065812963
Short name T560
Test name
Test status
Simulation time 29815912 ps
CPU time 0.91 seconds
Started Dec 31 12:54:40 PM PST 23
Finished Dec 31 12:54:43 PM PST 23
Peak memory 204828 kb
Host smart-5d13c918-e8f4-432c-84c9-28f46ff17c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065812963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.1065812963
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.649311173
Short name T41
Test name
Test status
Simulation time 103626360 ps
CPU time 2.9 seconds
Started Dec 31 12:54:26 PM PST 23
Finished Dec 31 12:54:30 PM PST 23
Peak memory 214212 kb
Host smart-9d0190de-4e7b-4b44-992a-a8a9672214d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649311173 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.649311173
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.2338725246
Short name T286
Test name
Test status
Simulation time 20183265 ps
CPU time 1.01 seconds
Started Dec 31 12:54:28 PM PST 23
Finished Dec 31 12:54:30 PM PST 23
Peak memory 205292 kb
Host smart-ad03da08-c3c6-49e2-95ce-284457c90088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338725246 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.2338725246
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.4079036336
Short name T305
Test name
Test status
Simulation time 14481956 ps
CPU time 0.98 seconds
Started Dec 31 12:55:05 PM PST 23
Finished Dec 31 12:55:11 PM PST 23
Peak memory 205036 kb
Host smart-699ddc95-85df-4bfa-a897-e3512e7f5378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079036336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.4079036336
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.1533989970
Short name T78
Test name
Test status
Simulation time 80205331 ps
CPU time 0.91 seconds
Started Dec 31 12:54:55 PM PST 23
Finished Dec 31 12:55:01 PM PST 23
Peak memory 205076 kb
Host smart-dc438efa-9c2f-4022-aadf-b172ae48fc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533989970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.1533989970
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.2684118756
Short name T695
Test name
Test status
Simulation time 31260571 ps
CPU time 0.99 seconds
Started Dec 31 12:53:57 PM PST 23
Finished Dec 31 12:54:07 PM PST 23
Peak memory 205588 kb
Host smart-3f3d00f7-576c-46fc-8d17-e1f3df8e0267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684118756 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.2684118756
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.1761017551
Short name T365
Test name
Test status
Simulation time 40715999 ps
CPU time 0.9 seconds
Started Dec 31 12:53:58 PM PST 23
Finished Dec 31 12:54:08 PM PST 23
Peak memory 205068 kb
Host smart-be0f5ac7-1c29-4d62-b582-8ee36508bb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761017551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.1761017551
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert_test.353307061
Short name T658
Test name
Test status
Simulation time 68146429 ps
CPU time 0.86 seconds
Started Dec 31 12:52:30 PM PST 23
Finished Dec 31 12:52:40 PM PST 23
Peak memory 205088 kb
Host smart-602dcf41-7dcb-4db9-8d3b-422a936566c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353307061 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.353307061
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.1639757322
Short name T125
Test name
Test status
Simulation time 51803921 ps
CPU time 0.81 seconds
Started Dec 31 12:52:27 PM PST 23
Finished Dec 31 12:52:38 PM PST 23
Peak memory 214288 kb
Host smart-10d4e43e-8505-410f-a10c-bec90ee124b5
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639757322 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.1639757322
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_err.2031019237
Short name T612
Test name
Test status
Simulation time 32222392 ps
CPU time 1.01 seconds
Started Dec 31 12:52:34 PM PST 23
Finished Dec 31 12:52:44 PM PST 23
Peak memory 215832 kb
Host smart-68a6a9fd-f917-471f-8fd9-232f6b5898b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031019237 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.2031019237
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.2936977573
Short name T542
Test name
Test status
Simulation time 37329208 ps
CPU time 1.02 seconds
Started Dec 31 12:52:26 PM PST 23
Finished Dec 31 12:52:37 PM PST 23
Peak memory 205468 kb
Host smart-7895c40b-5c44-4c16-8df8-96c90bff1fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936977573 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.2936977573
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.1535980712
Short name T51
Test name
Test status
Simulation time 18456282 ps
CPU time 1.14 seconds
Started Dec 31 12:52:25 PM PST 23
Finished Dec 31 12:52:37 PM PST 23
Peak memory 221804 kb
Host smart-3ea06fbd-09ea-47ff-9f6c-036193f802c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535980712 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.1535980712
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.736327128
Short name T951
Test name
Test status
Simulation time 39851479 ps
CPU time 0.86 seconds
Started Dec 31 12:52:23 PM PST 23
Finished Dec 31 12:52:36 PM PST 23
Peak memory 204756 kb
Host smart-de962991-db44-45b9-948c-f49ef95d39d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736327128 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.736327128
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.3886652426
Short name T688
Test name
Test status
Simulation time 547318213 ps
CPU time 3.09 seconds
Started Dec 31 12:52:32 PM PST 23
Finished Dec 31 12:52:44 PM PST 23
Peak memory 205964 kb
Host smart-b81fb364-59ab-4a3d-aa39-be1e08bff2ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886652426 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.3886652426
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/150.edn_genbits.1758454577
Short name T371
Test name
Test status
Simulation time 39367820 ps
CPU time 1.08 seconds
Started Dec 31 12:54:45 PM PST 23
Finished Dec 31 12:54:48 PM PST 23
Peak memory 205376 kb
Host smart-7cf61f33-41ab-4c5b-850a-cfcc2ad1b7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758454577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.1758454577
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.647361145
Short name T323
Test name
Test status
Simulation time 16195202 ps
CPU time 0.92 seconds
Started Dec 31 12:54:27 PM PST 23
Finished Dec 31 12:54:30 PM PST 23
Peak memory 204856 kb
Host smart-5368b07b-7f4d-4ebd-856f-35d9baa403ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647361145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.647361145
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.458892686
Short name T86
Test name
Test status
Simulation time 57341282 ps
CPU time 0.94 seconds
Started Dec 31 12:54:45 PM PST 23
Finished Dec 31 12:54:49 PM PST 23
Peak memory 205096 kb
Host smart-4bd60eec-3c6f-4f73-a830-2f34ae9f02fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458892686 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.458892686
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.1683659047
Short name T513
Test name
Test status
Simulation time 15888790 ps
CPU time 0.98 seconds
Started Dec 31 12:55:04 PM PST 23
Finished Dec 31 12:55:10 PM PST 23
Peak memory 205488 kb
Host smart-dd162565-aaca-4695-90e8-048039a5a011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683659047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.1683659047
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.4045432164
Short name T918
Test name
Test status
Simulation time 17482702 ps
CPU time 1.06 seconds
Started Dec 31 12:53:51 PM PST 23
Finished Dec 31 12:54:04 PM PST 23
Peak memory 205380 kb
Host smart-1201bb07-7092-41fb-9e93-a20238c08372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045432164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.4045432164
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.2221497540
Short name T364
Test name
Test status
Simulation time 15249791 ps
CPU time 0.97 seconds
Started Dec 31 12:54:02 PM PST 23
Finished Dec 31 12:54:12 PM PST 23
Peak memory 204980 kb
Host smart-f288a4af-56f3-4df4-baac-2ba5086727e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221497540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.2221497540
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.2398730661
Short name T954
Test name
Test status
Simulation time 89844043 ps
CPU time 1.03 seconds
Started Dec 31 12:53:58 PM PST 23
Finished Dec 31 12:54:09 PM PST 23
Peak memory 205068 kb
Host smart-2b3a1b4c-b73b-47f0-a3f2-d8cc6c3a5b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398730661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.2398730661
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.3107481357
Short name T924
Test name
Test status
Simulation time 28056450 ps
CPU time 0.95 seconds
Started Dec 31 12:54:41 PM PST 23
Finished Dec 31 12:54:44 PM PST 23
Peak memory 205448 kb
Host smart-2c71edb6-4e44-4044-8297-cb2d02db4a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107481357 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.3107481357
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.2081630639
Short name T361
Test name
Test status
Simulation time 21735028 ps
CPU time 1.08 seconds
Started Dec 31 12:53:57 PM PST 23
Finished Dec 31 12:54:08 PM PST 23
Peak memory 205512 kb
Host smart-be4062f4-2c98-4d15-952f-862e9f0aec9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081630639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.2081630639
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.1090619866
Short name T933
Test name
Test status
Simulation time 136476106 ps
CPU time 2.91 seconds
Started Dec 31 12:54:00 PM PST 23
Finished Dec 31 12:54:13 PM PST 23
Peak memory 214224 kb
Host smart-d84bf289-516b-426e-a888-f3530fa8b675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090619866 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.1090619866
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.3373717853
Short name T348
Test name
Test status
Simulation time 190297272 ps
CPU time 0.94 seconds
Started Dec 31 12:52:32 PM PST 23
Finished Dec 31 12:52:42 PM PST 23
Peak memory 205128 kb
Host smart-4f100e3e-5f90-49a1-a7fe-38b958ee26d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373717853 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.3373717853
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.2701164917
Short name T500
Test name
Test status
Simulation time 50908820 ps
CPU time 0.78 seconds
Started Dec 31 12:52:35 PM PST 23
Finished Dec 31 12:52:44 PM PST 23
Peak memory 204288 kb
Host smart-8a810c21-0eb4-4640-a14a-50f3eb0f1f1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701164917 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.2701164917
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.850000981
Short name T946
Test name
Test status
Simulation time 17421807 ps
CPU time 0.82 seconds
Started Dec 31 12:52:35 PM PST 23
Finished Dec 31 12:52:44 PM PST 23
Peak memory 214304 kb
Host smart-ff915fae-da54-4492-90f5-8b13220475d5
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850000981 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.850000981
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.2031614570
Short name T943
Test name
Test status
Simulation time 46460796 ps
CPU time 1.02 seconds
Started Dec 31 12:52:35 PM PST 23
Finished Dec 31 12:52:44 PM PST 23
Peak memory 214548 kb
Host smart-5632cbb8-e2df-4346-9fa7-170161b9ec11
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031614570 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.2031614570
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.2653132736
Short name T56
Test name
Test status
Simulation time 24195928 ps
CPU time 0.99 seconds
Started Dec 31 12:52:29 PM PST 23
Finished Dec 31 12:52:39 PM PST 23
Peak memory 221672 kb
Host smart-d65b45f6-7fc5-43b9-8a01-3933ddd6a141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653132736 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.2653132736
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.1486900931
Short name T952
Test name
Test status
Simulation time 52488224 ps
CPU time 0.95 seconds
Started Dec 31 12:52:34 PM PST 23
Finished Dec 31 12:52:43 PM PST 23
Peak memory 205480 kb
Host smart-4e558810-4b79-49ae-85a7-f518cc694152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486900931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.1486900931
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.2284258392
Short name T722
Test name
Test status
Simulation time 25827174 ps
CPU time 0.93 seconds
Started Dec 31 12:52:33 PM PST 23
Finished Dec 31 12:52:43 PM PST 23
Peak memory 214296 kb
Host smart-c8ec902a-ba35-40db-b115-199202ff315a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284258392 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.2284258392
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.318348669
Short name T573
Test name
Test status
Simulation time 40964071 ps
CPU time 0.8 seconds
Started Dec 31 12:52:26 PM PST 23
Finished Dec 31 12:52:37 PM PST 23
Peak memory 204440 kb
Host smart-6fdaa64f-dde6-4cb4-8a89-0917e4d2ac72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318348669 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.318348669
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.3461831723
Short name T523
Test name
Test status
Simulation time 220900951 ps
CPU time 2.82 seconds
Started Dec 31 12:52:31 PM PST 23
Finished Dec 31 12:52:43 PM PST 23
Peak memory 205712 kb
Host smart-2c27d15f-b018-43fa-9276-ca470a6824ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461831723 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.3461831723
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.999018320
Short name T626
Test name
Test status
Simulation time 162600023612 ps
CPU time 969.5 seconds
Started Dec 31 12:52:27 PM PST 23
Finished Dec 31 01:08:46 PM PST 23
Peak memory 216128 kb
Host smart-3a59f22c-86d4-4ec4-9d9b-dc0925087202
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999018320 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.999018320
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.1942663499
Short name T787
Test name
Test status
Simulation time 64456080 ps
CPU time 0.97 seconds
Started Dec 31 12:54:36 PM PST 23
Finished Dec 31 12:54:38 PM PST 23
Peak memory 205148 kb
Host smart-8e4976b6-112b-4372-9133-6191dcd988d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942663499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1942663499
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.4240057024
Short name T609
Test name
Test status
Simulation time 46256405 ps
CPU time 1.09 seconds
Started Dec 31 12:54:21 PM PST 23
Finished Dec 31 12:54:24 PM PST 23
Peak memory 205600 kb
Host smart-690170c1-f9b5-4a8b-9200-092b3837657d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240057024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.4240057024
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.3420359189
Short name T723
Test name
Test status
Simulation time 17178102 ps
CPU time 1.13 seconds
Started Dec 31 12:54:38 PM PST 23
Finished Dec 31 12:54:41 PM PST 23
Peak memory 205424 kb
Host smart-d559c10d-34b2-485c-af0c-c695ac0abd30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420359189 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.3420359189
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.1932942582
Short name T678
Test name
Test status
Simulation time 33120967 ps
CPU time 1.04 seconds
Started Dec 31 12:54:48 PM PST 23
Finished Dec 31 12:54:53 PM PST 23
Peak memory 205268 kb
Host smart-a9c01ac1-c896-4f07-b2ea-d16b7c63280c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932942582 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.1932942582
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.2560127784
Short name T580
Test name
Test status
Simulation time 20048525 ps
CPU time 1.16 seconds
Started Dec 31 12:54:44 PM PST 23
Finished Dec 31 12:54:48 PM PST 23
Peak memory 205196 kb
Host smart-5712cf35-6446-4783-b0ca-b95c54800d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560127784 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.2560127784
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.265525133
Short name T578
Test name
Test status
Simulation time 25087871 ps
CPU time 1.27 seconds
Started Dec 31 12:54:43 PM PST 23
Finished Dec 31 12:54:46 PM PST 23
Peak memory 205704 kb
Host smart-b3b41a12-75bd-491c-8bef-8887e38718ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265525133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.265525133
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.2396255924
Short name T791
Test name
Test status
Simulation time 35444553 ps
CPU time 1.57 seconds
Started Dec 31 12:54:54 PM PST 23
Finished Dec 31 12:55:00 PM PST 23
Peak memory 214112 kb
Host smart-6166f914-91cf-4207-bbb5-521801dc4a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396255924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.2396255924
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.486914524
Short name T367
Test name
Test status
Simulation time 26296310 ps
CPU time 0.87 seconds
Started Dec 31 12:53:47 PM PST 23
Finished Dec 31 12:54:00 PM PST 23
Peak memory 204988 kb
Host smart-e3af2adc-ce65-4792-bca9-47d8ae19ab39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486914524 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.486914524
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.2111184909
Short name T75
Test name
Test status
Simulation time 40781725 ps
CPU time 0.9 seconds
Started Dec 31 12:54:24 PM PST 23
Finished Dec 31 12:54:26 PM PST 23
Peak memory 205256 kb
Host smart-0806d35b-167f-48e6-89e5-8205acc80a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111184909 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.2111184909
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.1825177790
Short name T759
Test name
Test status
Simulation time 32405109 ps
CPU time 1.18 seconds
Started Dec 31 12:52:36 PM PST 23
Finished Dec 31 12:52:46 PM PST 23
Peak memory 205900 kb
Host smart-85b9d54e-1a43-43b8-b8e7-5fa7cdb2bac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825177790 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.1825177790
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.1421064460
Short name T962
Test name
Test status
Simulation time 38621865 ps
CPU time 0.8 seconds
Started Dec 31 12:52:28 PM PST 23
Finished Dec 31 12:52:38 PM PST 23
Peak memory 204352 kb
Host smart-c8934874-d485-4240-b1a1-5bd6646c6bfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421064460 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.1421064460
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.3487171976
Short name T131
Test name
Test status
Simulation time 22647649 ps
CPU time 0.83 seconds
Started Dec 31 12:52:44 PM PST 23
Finished Dec 31 12:52:49 PM PST 23
Peak memory 214236 kb
Host smart-2b474892-6b3e-446d-acac-f9b8edf3808a
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487171976 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.3487171976
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.1047644219
Short name T89
Test name
Test status
Simulation time 19190545 ps
CPU time 0.95 seconds
Started Dec 31 12:52:35 PM PST 23
Finished Dec 31 12:52:44 PM PST 23
Peak memory 214480 kb
Host smart-43daa42e-604c-46a0-a19d-42956d022076
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047644219 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.1047644219
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.8237654
Short name T469
Test name
Test status
Simulation time 43310392 ps
CPU time 1.14 seconds
Started Dec 31 12:52:41 PM PST 23
Finished Dec 31 12:52:47 PM PST 23
Peak memory 214660 kb
Host smart-b723e7fb-08a4-4ab8-afc3-df58ec38fcdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8237654 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.8237654
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.403459676
Short name T762
Test name
Test status
Simulation time 21743054 ps
CPU time 1 seconds
Started Dec 31 12:52:33 PM PST 23
Finished Dec 31 12:52:42 PM PST 23
Peak memory 204944 kb
Host smart-6bb0e5dd-f9db-409c-87ac-78c25124500d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403459676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.403459676
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.1885876595
Short name T851
Test name
Test status
Simulation time 81523472 ps
CPU time 0.8 seconds
Started Dec 31 12:52:39 PM PST 23
Finished Dec 31 12:52:46 PM PST 23
Peak memory 214348 kb
Host smart-574064cc-e74d-46eb-9753-fa523594c8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885876595 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.1885876595
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.1980833627
Short name T694
Test name
Test status
Simulation time 26029671 ps
CPU time 0.85 seconds
Started Dec 31 12:52:28 PM PST 23
Finished Dec 31 12:52:38 PM PST 23
Peak memory 204924 kb
Host smart-5b2eba01-e15b-4bb9-8cf2-8dbfc362e048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980833627 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.1980833627
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.2291049782
Short name T568
Test name
Test status
Simulation time 525104541 ps
CPU time 1.45 seconds
Started Dec 31 12:52:29 PM PST 23
Finished Dec 31 12:52:40 PM PST 23
Peak memory 205560 kb
Host smart-e725e21f-1425-40b7-9d09-bc2b76741ea7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291049782 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.2291049782
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.7851763
Short name T611
Test name
Test status
Simulation time 93028439791 ps
CPU time 306.62 seconds
Started Dec 31 12:52:31 PM PST 23
Finished Dec 31 12:57:47 PM PST 23
Peak memory 214532 kb
Host smart-ea9aac50-b3a7-4875-8b2e-b5e0a1d754a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7851763 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.7851763
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.3754760705
Short name T879
Test name
Test status
Simulation time 72613727 ps
CPU time 1.69 seconds
Started Dec 31 12:54:00 PM PST 23
Finished Dec 31 12:54:11 PM PST 23
Peak memory 214144 kb
Host smart-76832c57-bf0c-41ff-bb41-e8c3e2ea382a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754760705 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.3754760705
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.4243959721
Short name T604
Test name
Test status
Simulation time 86223447 ps
CPU time 0.97 seconds
Started Dec 31 12:54:25 PM PST 23
Finished Dec 31 12:54:28 PM PST 23
Peak memory 205468 kb
Host smart-d19e49d2-6a36-47c3-b0b3-2a4e5443b1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243959721 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.4243959721
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.3946208649
Short name T934
Test name
Test status
Simulation time 64119618 ps
CPU time 1.05 seconds
Started Dec 31 12:54:24 PM PST 23
Finished Dec 31 12:54:31 PM PST 23
Peak memory 205448 kb
Host smart-620d8196-3ba4-4c1e-afec-281fd9294ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946208649 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.3946208649
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.1763568355
Short name T968
Test name
Test status
Simulation time 24808239 ps
CPU time 1.03 seconds
Started Dec 31 12:53:54 PM PST 23
Finished Dec 31 12:54:05 PM PST 23
Peak memory 205204 kb
Host smart-847485e5-adb2-4bd8-9369-523827155dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763568355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.1763568355
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.2017415249
Short name T808
Test name
Test status
Simulation time 69292586 ps
CPU time 1.15 seconds
Started Dec 31 12:54:44 PM PST 23
Finished Dec 31 12:54:47 PM PST 23
Peak memory 214140 kb
Host smart-e0f23a26-3394-4a21-91d9-f4f89e62c137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017415249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.2017415249
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.530686964
Short name T692
Test name
Test status
Simulation time 135431376 ps
CPU time 1.06 seconds
Started Dec 31 12:54:46 PM PST 23
Finished Dec 31 12:54:51 PM PST 23
Peak memory 205192 kb
Host smart-099408f2-c393-410e-b8ee-f92b57351069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530686964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.530686964
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.3768132015
Short name T494
Test name
Test status
Simulation time 30829883 ps
CPU time 0.96 seconds
Started Dec 31 12:54:45 PM PST 23
Finished Dec 31 12:54:48 PM PST 23
Peak memory 205048 kb
Host smart-b46d79bd-9f58-4192-b998-5905a0daa3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768132015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.3768132015
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.2604283912
Short name T757
Test name
Test status
Simulation time 32712838 ps
CPU time 0.92 seconds
Started Dec 31 12:54:21 PM PST 23
Finished Dec 31 12:54:23 PM PST 23
Peak memory 205108 kb
Host smart-f28d1c1c-c2b0-414b-b290-da8fdfda5577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604283912 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.2604283912
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.3151057251
Short name T544
Test name
Test status
Simulation time 17841575 ps
CPU time 1.07 seconds
Started Dec 31 12:54:46 PM PST 23
Finished Dec 31 12:54:51 PM PST 23
Peak memory 205276 kb
Host smart-04be9e12-f305-4736-924d-13bec8b7f436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151057251 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.3151057251
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.3044513048
Short name T631
Test name
Test status
Simulation time 69873454 ps
CPU time 0.99 seconds
Started Dec 31 12:54:41 PM PST 23
Finished Dec 31 12:54:44 PM PST 23
Peak memory 205820 kb
Host smart-91ace38c-c13c-4b32-adbd-26ad1b343282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044513048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.3044513048
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert_test.2376872547
Short name T627
Test name
Test status
Simulation time 79793138 ps
CPU time 0.8 seconds
Started Dec 31 12:52:59 PM PST 23
Finished Dec 31 12:53:11 PM PST 23
Peak memory 204996 kb
Host smart-8fc906ff-98af-4a48-92b4-9fbe9cb1071e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376872547 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2376872547
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.713218999
Short name T220
Test name
Test status
Simulation time 38032026 ps
CPU time 0.87 seconds
Started Dec 31 12:52:53 PM PST 23
Finished Dec 31 12:52:54 PM PST 23
Peak memory 214212 kb
Host smart-c8f416ad-a9b1-495e-8f05-8e0c96442ac1
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713218999 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.713218999
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_err.961017207
Short name T839
Test name
Test status
Simulation time 140954331 ps
CPU time 1.33 seconds
Started Dec 31 12:53:05 PM PST 23
Finished Dec 31 12:53:19 PM PST 23
Peak memory 214780 kb
Host smart-476701d5-d237-4ffb-a15c-6a6b5fd42a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961017207 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.961017207
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.1862502494
Short name T766
Test name
Test status
Simulation time 75716181 ps
CPU time 1.01 seconds
Started Dec 31 12:52:31 PM PST 23
Finished Dec 31 12:52:41 PM PST 23
Peak memory 205472 kb
Host smart-f49232a2-3ced-4ced-8dc8-c9ea1a4ef051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862502494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.1862502494
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.3099457041
Short name T904
Test name
Test status
Simulation time 18486979 ps
CPU time 1 seconds
Started Dec 31 12:52:31 PM PST 23
Finished Dec 31 12:52:41 PM PST 23
Peak memory 214308 kb
Host smart-d5e4d742-ea9c-4788-b7cc-c6c7fc59ea1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099457041 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.3099457041
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.3535573189
Short name T501
Test name
Test status
Simulation time 85585336 ps
CPU time 0.83 seconds
Started Dec 31 12:52:34 PM PST 23
Finished Dec 31 12:52:43 PM PST 23
Peak memory 204836 kb
Host smart-36c110ae-4410-45c0-9a21-9cbc73a4dc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535573189 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.3535573189
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.585172765
Short name T824
Test name
Test status
Simulation time 322422147 ps
CPU time 3.93 seconds
Started Dec 31 12:52:30 PM PST 23
Finished Dec 31 12:52:43 PM PST 23
Peak memory 205892 kb
Host smart-b3e01742-465c-4bec-9498-5744b97799d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585172765 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.585172765
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.3638614831
Short name T856
Test name
Test status
Simulation time 45131662081 ps
CPU time 758.12 seconds
Started Dec 31 12:52:28 PM PST 23
Finished Dec 31 01:05:16 PM PST 23
Peak memory 214548 kb
Host smart-8ca783ea-476d-42ef-9a64-889d798901d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638614831 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.3638614831
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.1883963486
Short name T880
Test name
Test status
Simulation time 47142518 ps
CPU time 1.02 seconds
Started Dec 31 12:53:51 PM PST 23
Finished Dec 31 12:54:03 PM PST 23
Peak memory 205656 kb
Host smart-2fde6138-0428-4d0d-bc0b-abb8cb257ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883963486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.1883963486
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.1854910407
Short name T878
Test name
Test status
Simulation time 114523874 ps
CPU time 1.51 seconds
Started Dec 31 12:54:45 PM PST 23
Finished Dec 31 12:54:49 PM PST 23
Peak memory 214152 kb
Host smart-59016a35-dc81-44bb-828b-b69820ca7123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854910407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.1854910407
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.272526351
Short name T329
Test name
Test status
Simulation time 19955008 ps
CPU time 1.05 seconds
Started Dec 31 12:54:34 PM PST 23
Finished Dec 31 12:54:36 PM PST 23
Peak memory 205204 kb
Host smart-5e1d88dc-9cfe-471d-a27e-261de1448156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272526351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.272526351
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.160116767
Short name T84
Test name
Test status
Simulation time 66213967 ps
CPU time 1.1 seconds
Started Dec 31 12:54:16 PM PST 23
Finished Dec 31 12:54:19 PM PST 23
Peak memory 205576 kb
Host smart-08b72409-6b9d-4c0a-b3a0-0c6c9ff125f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160116767 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.160116767
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.702338382
Short name T595
Test name
Test status
Simulation time 39934835 ps
CPU time 1.19 seconds
Started Dec 31 12:54:48 PM PST 23
Finished Dec 31 12:54:54 PM PST 23
Peak memory 214092 kb
Host smart-37db6da4-bbc1-4e8f-b917-68d112c223ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702338382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.702338382
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.3042160162
Short name T936
Test name
Test status
Simulation time 88660917 ps
CPU time 0.89 seconds
Started Dec 31 12:53:53 PM PST 23
Finished Dec 31 12:54:04 PM PST 23
Peak memory 204896 kb
Host smart-8d04968a-7545-4019-b540-8080e123ddc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042160162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.3042160162
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.149269846
Short name T334
Test name
Test status
Simulation time 21509867 ps
CPU time 1.04 seconds
Started Dec 31 12:54:38 PM PST 23
Finished Dec 31 12:54:41 PM PST 23
Peak memory 205148 kb
Host smart-55bb8dff-1d6b-4f5f-a6a5-f53a37d28e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149269846 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.149269846
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.1926259305
Short name T530
Test name
Test status
Simulation time 15370336 ps
CPU time 1.05 seconds
Started Dec 31 12:54:49 PM PST 23
Finished Dec 31 12:54:56 PM PST 23
Peak memory 205224 kb
Host smart-e27de7c8-e858-4914-add0-bf89ed2b0baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926259305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.1926259305
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.3403235142
Short name T942
Test name
Test status
Simulation time 43121209 ps
CPU time 1.31 seconds
Started Dec 31 12:54:09 PM PST 23
Finished Dec 31 12:54:15 PM PST 23
Peak memory 214128 kb
Host smart-cecec77a-0535-453a-92ed-77c29dda1296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403235142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.3403235142
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.2964008143
Short name T896
Test name
Test status
Simulation time 21260513 ps
CPU time 0.89 seconds
Started Dec 31 12:54:29 PM PST 23
Finished Dec 31 12:54:32 PM PST 23
Peak memory 205060 kb
Host smart-306573c8-0c59-4709-9f49-e8cfde91d4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964008143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.2964008143
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.4172932012
Short name T773
Test name
Test status
Simulation time 20267693 ps
CPU time 1.02 seconds
Started Dec 31 12:52:53 PM PST 23
Finished Dec 31 12:52:55 PM PST 23
Peak memory 205872 kb
Host smart-ff23c5de-aaa2-4049-9251-140585a36b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172932012 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.4172932012
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.1966939278
Short name T570
Test name
Test status
Simulation time 28983700 ps
CPU time 0.84 seconds
Started Dec 31 12:53:03 PM PST 23
Finished Dec 31 12:53:18 PM PST 23
Peak memory 204532 kb
Host smart-b6ba1e11-7cf4-4933-bbc2-6b7bf4e63d51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966939278 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.1966939278
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.3354700332
Short name T178
Test name
Test status
Simulation time 83891734 ps
CPU time 1.04 seconds
Started Dec 31 12:53:03 PM PST 23
Finished Dec 31 12:53:18 PM PST 23
Peak memory 214512 kb
Host smart-6f7f23a0-b7e7-4e85-a6fd-10b16f3fcff9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354700332 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.3354700332
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.3891091873
Short name T182
Test name
Test status
Simulation time 23606094 ps
CPU time 1.07 seconds
Started Dec 31 12:53:23 PM PST 23
Finished Dec 31 12:53:37 PM PST 23
Peak memory 214628 kb
Host smart-d9fc8e12-a4b5-43b5-be4a-4afd908d348b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891091873 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.3891091873
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.3468235053
Short name T292
Test name
Test status
Simulation time 31680318 ps
CPU time 0.89 seconds
Started Dec 31 12:52:58 PM PST 23
Finished Dec 31 12:53:03 PM PST 23
Peak memory 204864 kb
Host smart-73d82d64-7e81-4d46-a5cf-605c609eb7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468235053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.3468235053
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.4139226812
Short name T60
Test name
Test status
Simulation time 69570134 ps
CPU time 0.8 seconds
Started Dec 31 12:53:03 PM PST 23
Finished Dec 31 12:53:18 PM PST 23
Peak memory 214292 kb
Host smart-9d08c1df-6006-4765-90b8-f0213aa32d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139226812 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.4139226812
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.2758061343
Short name T512
Test name
Test status
Simulation time 38779643 ps
CPU time 0.87 seconds
Started Dec 31 12:52:52 PM PST 23
Finished Dec 31 12:52:54 PM PST 23
Peak memory 204864 kb
Host smart-47bab1f1-95ec-48f4-8cf1-740a62e536fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758061343 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.2758061343
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.2952152362
Short name T254
Test name
Test status
Simulation time 105788502 ps
CPU time 1.79 seconds
Started Dec 31 12:53:13 PM PST 23
Finished Dec 31 12:53:31 PM PST 23
Peak memory 205344 kb
Host smart-1baae901-24ed-4527-bd31-e8e2d55793a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952152362 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.2952152362
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.1076690193
Short name T111
Test name
Test status
Simulation time 115955193294 ps
CPU time 745.03 seconds
Started Dec 31 12:52:59 PM PST 23
Finished Dec 31 01:05:35 PM PST 23
Peak memory 215172 kb
Host smart-5767eee2-b5cc-4b3a-9106-6677738b58cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076690193 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.1076690193
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.1423835137
Short name T716
Test name
Test status
Simulation time 63055184 ps
CPU time 0.99 seconds
Started Dec 31 12:54:56 PM PST 23
Finished Dec 31 12:55:01 PM PST 23
Peak memory 205116 kb
Host smart-07ea121b-a7ea-4ad5-939c-179557b07095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423835137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.1423835137
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.2638858019
Short name T72
Test name
Test status
Simulation time 29750289 ps
CPU time 0.95 seconds
Started Dec 31 12:53:58 PM PST 23
Finished Dec 31 12:54:09 PM PST 23
Peak memory 204724 kb
Host smart-011e0dcb-e6b0-4920-a22f-a22e5784be93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638858019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2638858019
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.3499071289
Short name T325
Test name
Test status
Simulation time 27059617 ps
CPU time 0.97 seconds
Started Dec 31 12:54:34 PM PST 23
Finished Dec 31 12:54:37 PM PST 23
Peak memory 205608 kb
Host smart-983b77f2-4248-4a8b-975c-849f8df28292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499071289 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.3499071289
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.1381667981
Short name T931
Test name
Test status
Simulation time 59544565 ps
CPU time 1.04 seconds
Started Dec 31 12:54:31 PM PST 23
Finished Dec 31 12:54:34 PM PST 23
Peak memory 204784 kb
Host smart-ab61edd2-3b0a-49a1-aa5b-ba0dc4ccc8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381667981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.1381667981
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.3660693978
Short name T772
Test name
Test status
Simulation time 92067927 ps
CPU time 1.07 seconds
Started Dec 31 12:54:12 PM PST 23
Finished Dec 31 12:54:16 PM PST 23
Peak memory 205500 kb
Host smart-b54f7b4f-f245-4c80-9518-4fd1e0d0c2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660693978 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.3660693978
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.1581111350
Short name T875
Test name
Test status
Simulation time 127715402 ps
CPU time 0.95 seconds
Started Dec 31 12:54:10 PM PST 23
Finished Dec 31 12:54:15 PM PST 23
Peak memory 205628 kb
Host smart-971e075e-ade1-4261-831a-aab472f14021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581111350 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.1581111350
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.4233787995
Short name T949
Test name
Test status
Simulation time 73625234 ps
CPU time 0.85 seconds
Started Dec 31 12:54:12 PM PST 23
Finished Dec 31 12:54:17 PM PST 23
Peak memory 205080 kb
Host smart-2c5aeb30-14bf-4ab3-a134-9269bd583e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233787995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.4233787995
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.691753297
Short name T302
Test name
Test status
Simulation time 103076769 ps
CPU time 1.24 seconds
Started Dec 31 12:54:00 PM PST 23
Finished Dec 31 12:54:10 PM PST 23
Peak memory 214172 kb
Host smart-406ba334-4ff7-4939-9e68-a105cf22cd42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691753297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.691753297
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.3644793302
Short name T368
Test name
Test status
Simulation time 50003609 ps
CPU time 0.84 seconds
Started Dec 31 12:53:57 PM PST 23
Finished Dec 31 12:54:08 PM PST 23
Peak memory 204796 kb
Host smart-12312351-a153-4cf5-baac-2af6017094e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644793302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.3644793302
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.416821600
Short name T16
Test name
Test status
Simulation time 17622593 ps
CPU time 0.97 seconds
Started Dec 31 12:52:14 PM PST 23
Finished Dec 31 12:52:29 PM PST 23
Peak memory 205916 kb
Host smart-f5551004-35a5-4873-b763-85ffc4ff1b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416821600 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.416821600
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.430207868
Short name T730
Test name
Test status
Simulation time 20858681 ps
CPU time 1.01 seconds
Started Dec 31 12:52:11 PM PST 23
Finished Dec 31 12:52:27 PM PST 23
Peak memory 204640 kb
Host smart-0097ca3d-439f-4788-b3a0-13a994b32a03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430207868 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.430207868
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.2029638058
Short name T216
Test name
Test status
Simulation time 20626432 ps
CPU time 0.84 seconds
Started Dec 31 12:52:05 PM PST 23
Finished Dec 31 12:52:17 PM PST 23
Peak memory 214320 kb
Host smart-61545f4c-678d-4014-8446-c0d28f8e4d49
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029638058 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2029638058
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.2841757441
Short name T778
Test name
Test status
Simulation time 154195040 ps
CPU time 1.1 seconds
Started Dec 31 12:52:07 PM PST 23
Finished Dec 31 12:52:20 PM PST 23
Peak memory 214552 kb
Host smart-a2a4aba4-ff40-4c50-afd0-acceabe31397
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841757441 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.2841757441
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.1776350438
Short name T267
Test name
Test status
Simulation time 21147915 ps
CPU time 1.02 seconds
Started Dec 31 12:52:13 PM PST 23
Finished Dec 31 12:52:30 PM PST 23
Peak memory 214788 kb
Host smart-afce0b82-e354-43e1-a082-906bf61b0dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776350438 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.1776350438
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.4095562044
Short name T596
Test name
Test status
Simulation time 293925076 ps
CPU time 2.86 seconds
Started Dec 31 12:52:09 PM PST 23
Finished Dec 31 12:52:26 PM PST 23
Peak memory 214092 kb
Host smart-9c71e702-396a-49e1-a24a-900872433762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095562044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.4095562044
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.2338039074
Short name T94
Test name
Test status
Simulation time 40849463 ps
CPU time 0.81 seconds
Started Dec 31 12:52:11 PM PST 23
Finished Dec 31 12:52:27 PM PST 23
Peak memory 214320 kb
Host smart-8d2643be-0c74-42d9-9db8-08b202293504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338039074 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.2338039074
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_smoke.3591823010
Short name T799
Test name
Test status
Simulation time 15149071 ps
CPU time 0.89 seconds
Started Dec 31 12:52:10 PM PST 23
Finished Dec 31 12:52:26 PM PST 23
Peak memory 204668 kb
Host smart-f061738c-c253-46c8-8746-0e8b16c7eb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591823010 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.3591823010
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.1198746135
Short name T515
Test name
Test status
Simulation time 784902669 ps
CPU time 4.78 seconds
Started Dec 31 12:52:02 PM PST 23
Finished Dec 31 12:52:14 PM PST 23
Peak memory 206024 kb
Host smart-084b7210-2b37-4b2d-afad-727ceb3e0367
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198746135 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.1198746135
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.3802603093
Short name T847
Test name
Test status
Simulation time 57500784790 ps
CPU time 1254.86 seconds
Started Dec 31 12:52:10 PM PST 23
Finished Dec 31 01:13:20 PM PST 23
Peak memory 214844 kb
Host smart-84f0b0bc-512e-4199-bdce-17226c0bedd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802603093 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.3802603093
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert_test.1221336673
Short name T742
Test name
Test status
Simulation time 46951643 ps
CPU time 0.88 seconds
Started Dec 31 12:52:47 PM PST 23
Finished Dec 31 12:52:50 PM PST 23
Peak memory 204528 kb
Host smart-79ae0b34-2a5e-4a84-96a8-84081721d780
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221336673 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.1221336673
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.2557770214
Short name T186
Test name
Test status
Simulation time 17366230 ps
CPU time 0.93 seconds
Started Dec 31 12:53:06 PM PST 23
Finished Dec 31 12:53:31 PM PST 23
Peak memory 214516 kb
Host smart-9efdd68c-d3b3-4dc9-b3eb-785ead74d486
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557770214 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.2557770214
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.2255858574
Short name T225
Test name
Test status
Simulation time 19131442 ps
CPU time 1 seconds
Started Dec 31 12:52:59 PM PST 23
Finished Dec 31 12:53:03 PM PST 23
Peak memory 215744 kb
Host smart-4cdefabb-1d8d-4bbd-be02-1d95afd0457b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255858574 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.2255858574
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.785440162
Short name T643
Test name
Test status
Simulation time 31234286 ps
CPU time 1 seconds
Started Dec 31 12:53:11 PM PST 23
Finished Dec 31 12:53:23 PM PST 23
Peak memory 205360 kb
Host smart-34c88e09-951b-44b9-bec6-67958abb93f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785440162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.785440162
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.3076986436
Short name T602
Test name
Test status
Simulation time 22813349 ps
CPU time 1.05 seconds
Started Dec 31 12:53:07 PM PST 23
Finished Dec 31 12:53:19 PM PST 23
Peak memory 221764 kb
Host smart-99b75988-f501-4c27-9342-2288af03eb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076986436 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.3076986436
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.3960522722
Short name T605
Test name
Test status
Simulation time 37820946 ps
CPU time 0.84 seconds
Started Dec 31 12:52:54 PM PST 23
Finished Dec 31 12:52:56 PM PST 23
Peak memory 204568 kb
Host smart-85e66384-be3c-4055-834a-bf77d52dd2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960522722 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.3960522722
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.2158090173
Short name T677
Test name
Test status
Simulation time 439308300 ps
CPU time 2.43 seconds
Started Dec 31 12:52:40 PM PST 23
Finished Dec 31 12:52:48 PM PST 23
Peak memory 205464 kb
Host smart-91dc88e7-410d-48f1-98cf-0eb3fed2c457
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158090173 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.2158090173
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.254331967
Short name T106
Test name
Test status
Simulation time 77821766448 ps
CPU time 481.14 seconds
Started Dec 31 12:53:09 PM PST 23
Finished Dec 31 01:01:20 PM PST 23
Peak memory 214444 kb
Host smart-5195ef63-d237-413a-a962-b412f9b9d107
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254331967 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.254331967
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.3435052672
Short name T761
Test name
Test status
Simulation time 64586008 ps
CPU time 1.28 seconds
Started Dec 31 12:54:10 PM PST 23
Finished Dec 31 12:54:15 PM PST 23
Peak memory 214088 kb
Host smart-b40568f1-7e2b-4f73-89e1-2577337de1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435052672 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.3435052672
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.855634005
Short name T336
Test name
Test status
Simulation time 92622672 ps
CPU time 1.21 seconds
Started Dec 31 12:54:03 PM PST 23
Finished Dec 31 12:54:12 PM PST 23
Peak memory 214136 kb
Host smart-0641e67d-c6f9-4ae3-8db4-a4f9e3a5f670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855634005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.855634005
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.978857798
Short name T809
Test name
Test status
Simulation time 18343550 ps
CPU time 0.98 seconds
Started Dec 31 12:54:35 PM PST 23
Finished Dec 31 12:54:38 PM PST 23
Peak memory 205240 kb
Host smart-6c87535d-1512-4658-b16f-f4d58191dfba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978857798 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.978857798
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.2480648639
Short name T536
Test name
Test status
Simulation time 44721311 ps
CPU time 0.96 seconds
Started Dec 31 12:54:14 PM PST 23
Finished Dec 31 12:54:18 PM PST 23
Peak memory 205284 kb
Host smart-2d4d887f-9cd5-4a8e-9a97-bec57391a73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480648639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2480648639
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.3060897943
Short name T789
Test name
Test status
Simulation time 58628877 ps
CPU time 0.98 seconds
Started Dec 31 12:54:29 PM PST 23
Finished Dec 31 12:54:32 PM PST 23
Peak memory 205492 kb
Host smart-5e373e59-3859-4ba3-8381-1642f82cfae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060897943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.3060897943
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.1782094017
Short name T714
Test name
Test status
Simulation time 17193003 ps
CPU time 1.11 seconds
Started Dec 31 12:55:09 PM PST 23
Finished Dec 31 12:55:17 PM PST 23
Peak memory 205164 kb
Host smart-20f560df-f394-423e-8fc3-1fb4ba0f8c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782094017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.1782094017
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.1394665598
Short name T553
Test name
Test status
Simulation time 154560374 ps
CPU time 1.11 seconds
Started Dec 31 12:54:12 PM PST 23
Finished Dec 31 12:54:17 PM PST 23
Peak memory 205184 kb
Host smart-1660eb64-4cb5-410e-9c1f-e99be2ff21fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394665598 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.1394665598
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.2246777624
Short name T881
Test name
Test status
Simulation time 16055582 ps
CPU time 0.91 seconds
Started Dec 31 12:54:12 PM PST 23
Finished Dec 31 12:54:16 PM PST 23
Peak memory 205044 kb
Host smart-38738d6c-53c7-4d85-bfee-42beff6a87b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246777624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.2246777624
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.494551996
Short name T771
Test name
Test status
Simulation time 110930679 ps
CPU time 0.91 seconds
Started Dec 31 12:53:07 PM PST 23
Finished Dec 31 12:53:18 PM PST 23
Peak memory 205256 kb
Host smart-7ce41470-87c7-4fec-bf49-3784a2783935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494551996 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.494551996
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.3817797143
Short name T623
Test name
Test status
Simulation time 100637803 ps
CPU time 0.82 seconds
Started Dec 31 12:52:59 PM PST 23
Finished Dec 31 12:53:11 PM PST 23
Peak memory 205280 kb
Host smart-8379c506-af5b-462f-9e11-534fc8a5ffca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817797143 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.3817797143
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.1786014456
Short name T257
Test name
Test status
Simulation time 13720004 ps
CPU time 0.84 seconds
Started Dec 31 12:53:08 PM PST 23
Finished Dec 31 12:53:19 PM PST 23
Peak memory 214328 kb
Host smart-cbcb6026-36cd-4257-99b4-a7322a510b2b
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786014456 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.1786014456
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.2368890558
Short name T42
Test name
Test status
Simulation time 95050115 ps
CPU time 1.05 seconds
Started Dec 31 12:53:02 PM PST 23
Finished Dec 31 12:53:16 PM PST 23
Peak memory 214472 kb
Host smart-c2025737-fd63-44db-b5a7-e505d9a03c7c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368890558 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.2368890558
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.481214205
Short name T797
Test name
Test status
Simulation time 115397548 ps
CPU time 1.21 seconds
Started Dec 31 12:53:10 PM PST 23
Finished Dec 31 12:53:21 PM PST 23
Peak memory 227548 kb
Host smart-0e1a7059-79f9-4263-96b7-6199ec797254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481214205 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.481214205
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.226995758
Short name T535
Test name
Test status
Simulation time 24383037 ps
CPU time 1.18 seconds
Started Dec 31 12:53:06 PM PST 23
Finished Dec 31 12:53:19 PM PST 23
Peak memory 205328 kb
Host smart-b7f99640-bcd7-4430-9fee-056f359df7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226995758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.226995758
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.850808892
Short name T54
Test name
Test status
Simulation time 26477885 ps
CPU time 1.04 seconds
Started Dec 31 12:53:05 PM PST 23
Finished Dec 31 12:53:18 PM PST 23
Peak memory 221400 kb
Host smart-95f34e0b-6a4a-4971-856d-44b18997ec3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850808892 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.850808892
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.1322685184
Short name T891
Test name
Test status
Simulation time 41014893 ps
CPU time 0.84 seconds
Started Dec 31 12:52:53 PM PST 23
Finished Dec 31 12:52:56 PM PST 23
Peak memory 204568 kb
Host smart-af8be7d0-b0bc-44c8-b675-5133cd88f2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322685184 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.1322685184
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.808886088
Short name T969
Test name
Test status
Simulation time 759799650 ps
CPU time 4.24 seconds
Started Dec 31 12:52:59 PM PST 23
Finished Dec 31 12:53:07 PM PST 23
Peak memory 205980 kb
Host smart-fe0da364-e65a-4dde-9381-442d43b32fa9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808886088 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.808886088
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.1889414519
Short name T481
Test name
Test status
Simulation time 59125886224 ps
CPU time 693.67 seconds
Started Dec 31 12:53:17 PM PST 23
Finished Dec 31 01:05:07 PM PST 23
Peak memory 215188 kb
Host smart-dbc33eb3-b33f-41b9-82b7-142362b3300a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889414519 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.1889414519
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.2514704779
Short name T44
Test name
Test status
Simulation time 102787507 ps
CPU time 0.9 seconds
Started Dec 31 12:54:31 PM PST 23
Finished Dec 31 12:54:38 PM PST 23
Peak memory 205188 kb
Host smart-9a5ca828-279d-4e3f-8157-8b50946812d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514704779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.2514704779
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.225656379
Short name T812
Test name
Test status
Simulation time 106811723 ps
CPU time 1.25 seconds
Started Dec 31 12:54:30 PM PST 23
Finished Dec 31 12:54:33 PM PST 23
Peak memory 214180 kb
Host smart-8ee2c5e5-ed0b-4145-9fd9-8db2f852c4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225656379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.225656379
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.1356742929
Short name T287
Test name
Test status
Simulation time 26771422 ps
CPU time 0.94 seconds
Started Dec 31 12:54:10 PM PST 23
Finished Dec 31 12:54:15 PM PST 23
Peak memory 205048 kb
Host smart-51ba962e-2e19-4802-bf01-cecd0b94aa3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356742929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.1356742929
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.1769130297
Short name T561
Test name
Test status
Simulation time 37699042 ps
CPU time 0.88 seconds
Started Dec 31 12:54:42 PM PST 23
Finished Dec 31 12:54:45 PM PST 23
Peak memory 204864 kb
Host smart-4e0c6d63-e86b-425a-ac20-8547800fdf2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769130297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.1769130297
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.193110591
Short name T525
Test name
Test status
Simulation time 47782032 ps
CPU time 0.91 seconds
Started Dec 31 12:55:14 PM PST 23
Finished Dec 31 12:55:21 PM PST 23
Peak memory 204800 kb
Host smart-20b7ce3a-b344-4db4-9042-1522a1f07b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193110591 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.193110591
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.3273760612
Short name T956
Test name
Test status
Simulation time 90083892 ps
CPU time 0.92 seconds
Started Dec 31 12:54:17 PM PST 23
Finished Dec 31 12:54:20 PM PST 23
Peak memory 205036 kb
Host smart-8ccae1f4-7b99-41b8-8196-992c398b9ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273760612 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.3273760612
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.1377536746
Short name T749
Test name
Test status
Simulation time 42269817 ps
CPU time 0.85 seconds
Started Dec 31 12:54:21 PM PST 23
Finished Dec 31 12:54:23 PM PST 23
Peak memory 205020 kb
Host smart-7abde09d-8f7e-4054-be8b-b2fa3db5a1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377536746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.1377536746
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.2459814880
Short name T927
Test name
Test status
Simulation time 62932878 ps
CPU time 0.98 seconds
Started Dec 31 12:54:27 PM PST 23
Finished Dec 31 12:54:30 PM PST 23
Peak memory 205504 kb
Host smart-5cbcd729-a244-4fa3-9860-564058d38091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459814880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.2459814880
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.3313506274
Short name T489
Test name
Test status
Simulation time 24401278 ps
CPU time 0.97 seconds
Started Dec 31 12:54:20 PM PST 23
Finished Dec 31 12:54:22 PM PST 23
Peak memory 205388 kb
Host smart-365728e1-ff48-4aaf-ba8d-a3422a4b48da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313506274 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.3313506274
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.2396491367
Short name T872
Test name
Test status
Simulation time 33352046 ps
CPU time 1.01 seconds
Started Dec 31 12:54:41 PM PST 23
Finished Dec 31 12:54:44 PM PST 23
Peak memory 214184 kb
Host smart-7c8f8ad6-0926-43ee-b1d1-d509be984813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396491367 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.2396491367
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.2467241571
Short name T562
Test name
Test status
Simulation time 20967939 ps
CPU time 1.01 seconds
Started Dec 31 12:52:55 PM PST 23
Finished Dec 31 12:53:00 PM PST 23
Peak memory 205416 kb
Host smart-55b2690d-83f7-49ae-b0f4-b6c67f3d3e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467241571 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.2467241571
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.3834689841
Short name T903
Test name
Test status
Simulation time 15630551 ps
CPU time 0.88 seconds
Started Dec 31 12:53:02 PM PST 23
Finished Dec 31 12:53:15 PM PST 23
Peak memory 204616 kb
Host smart-ba72f974-9306-4ff6-9d89-9ea4ac101949
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834689841 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.3834689841
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.1124266233
Short name T177
Test name
Test status
Simulation time 28584959 ps
CPU time 1.08 seconds
Started Dec 31 12:53:05 PM PST 23
Finished Dec 31 12:53:19 PM PST 23
Peak memory 214460 kb
Host smart-d2c56350-e2c8-45ae-a59d-00a7669fccf1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124266233 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.1124266233
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.739569528
Short name T849
Test name
Test status
Simulation time 61591582 ps
CPU time 0.99 seconds
Started Dec 31 12:53:08 PM PST 23
Finished Dec 31 12:53:19 PM PST 23
Peak memory 215944 kb
Host smart-8c114675-9700-4a57-b4cd-b519cf01d965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739569528 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.739569528
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.2714378501
Short name T953
Test name
Test status
Simulation time 42036804 ps
CPU time 0.83 seconds
Started Dec 31 12:53:07 PM PST 23
Finished Dec 31 12:53:18 PM PST 23
Peak memory 204968 kb
Host smart-dabbc739-78dc-4b6a-840c-938ae3a3575b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714378501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.2714378501
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.1312756867
Short name T5
Test name
Test status
Simulation time 18873074 ps
CPU time 1.03 seconds
Started Dec 31 12:52:53 PM PST 23
Finished Dec 31 12:52:55 PM PST 23
Peak memory 214508 kb
Host smart-357de338-d06b-44ea-86ca-1b674ec4a21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312756867 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.1312756867
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.4079419956
Short name T767
Test name
Test status
Simulation time 25063217 ps
CPU time 0.86 seconds
Started Dec 31 12:53:11 PM PST 23
Finished Dec 31 12:53:22 PM PST 23
Peak memory 204788 kb
Host smart-c8bf1e71-8cb9-4b94-97de-f2f044261c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079419956 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.4079419956
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.1926576967
Short name T795
Test name
Test status
Simulation time 131598260 ps
CPU time 3.31 seconds
Started Dec 31 12:53:20 PM PST 23
Finished Dec 31 12:53:38 PM PST 23
Peak memory 205932 kb
Host smart-b9ef2a6f-2a75-41ac-ad7c-4fb20398b52e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926576967 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.1926576967
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/220.edn_genbits.3431123228
Short name T894
Test name
Test status
Simulation time 41422009 ps
CPU time 1.07 seconds
Started Dec 31 12:54:10 PM PST 23
Finished Dec 31 12:54:15 PM PST 23
Peak memory 205400 kb
Host smart-7aee314e-946f-417c-bd63-baa6ae585eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431123228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.3431123228
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.1845283590
Short name T288
Test name
Test status
Simulation time 80141191 ps
CPU time 0.99 seconds
Started Dec 31 12:54:26 PM PST 23
Finished Dec 31 12:54:29 PM PST 23
Peak memory 205528 kb
Host smart-7124817a-6d8e-49b9-a6f8-00634195b305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845283590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.1845283590
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.30573186
Short name T373
Test name
Test status
Simulation time 15904256 ps
CPU time 0.92 seconds
Started Dec 31 12:54:41 PM PST 23
Finished Dec 31 12:54:44 PM PST 23
Peak memory 204904 kb
Host smart-0d1e061f-731d-4bd8-a4b7-197a3e6152bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30573186 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.30573186
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.2083512643
Short name T533
Test name
Test status
Simulation time 17787884 ps
CPU time 1 seconds
Started Dec 31 12:54:12 PM PST 23
Finished Dec 31 12:54:17 PM PST 23
Peak memory 205192 kb
Host smart-d06b5f93-def8-499e-a460-4a7b022168bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083512643 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.2083512643
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.2112383321
Short name T866
Test name
Test status
Simulation time 67391504 ps
CPU time 1 seconds
Started Dec 31 12:54:11 PM PST 23
Finished Dec 31 12:54:16 PM PST 23
Peak memory 205144 kb
Host smart-b2b785d1-6e46-4407-a812-952fed04c73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112383321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.2112383321
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.3769714834
Short name T295
Test name
Test status
Simulation time 16877157 ps
CPU time 0.99 seconds
Started Dec 31 12:54:11 PM PST 23
Finished Dec 31 12:54:22 PM PST 23
Peak memory 205500 kb
Host smart-26c633cf-065c-4488-96c6-81916a844a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769714834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.3769714834
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.4158714822
Short name T328
Test name
Test status
Simulation time 43514390 ps
CPU time 1.02 seconds
Started Dec 31 12:54:45 PM PST 23
Finished Dec 31 12:54:49 PM PST 23
Peak memory 205580 kb
Host smart-c6f36ef0-0112-4552-a03a-f3a06766119d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158714822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.4158714822
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.2482077227
Short name T728
Test name
Test status
Simulation time 85309001 ps
CPU time 2.59 seconds
Started Dec 31 12:54:13 PM PST 23
Finished Dec 31 12:54:19 PM PST 23
Peak memory 214084 kb
Host smart-085a34dc-f4ef-4437-a0ce-e52c5204229e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482077227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.2482077227
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.951090065
Short name T618
Test name
Test status
Simulation time 143068002 ps
CPU time 2.36 seconds
Started Dec 31 12:54:12 PM PST 23
Finished Dec 31 12:54:17 PM PST 23
Peak memory 214140 kb
Host smart-5e3689f8-8b8b-4e2e-b059-00d9feeff6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951090065 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.951090065
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.873754480
Short name T572
Test name
Test status
Simulation time 18171346 ps
CPU time 1.02 seconds
Started Dec 31 12:52:57 PM PST 23
Finished Dec 31 12:53:02 PM PST 23
Peak memory 206012 kb
Host smart-08108a7f-0f19-46b8-9e95-7bddebd9b620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873754480 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.873754480
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.1258346362
Short name T935
Test name
Test status
Simulation time 15917518 ps
CPU time 0.87 seconds
Started Dec 31 12:53:21 PM PST 23
Finished Dec 31 12:53:36 PM PST 23
Peak memory 205072 kb
Host smart-9755155f-21fe-4f29-961a-cb0441047521
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258346362 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.1258346362
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.3866668596
Short name T203
Test name
Test status
Simulation time 30930104 ps
CPU time 0.79 seconds
Started Dec 31 12:52:55 PM PST 23
Finished Dec 31 12:53:00 PM PST 23
Peak memory 214252 kb
Host smart-3f79f7ab-a1c4-4e8a-a6bd-4e7d7ebf39b8
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866668596 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3866668596
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_err.817016043
Short name T606
Test name
Test status
Simulation time 20322297 ps
CPU time 0.97 seconds
Started Dec 31 12:53:05 PM PST 23
Finished Dec 31 12:53:18 PM PST 23
Peak memory 215944 kb
Host smart-de3aa361-5110-4021-ae89-e7d12a63c5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817016043 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.817016043
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.3452517577
Short name T649
Test name
Test status
Simulation time 60160073 ps
CPU time 1.19 seconds
Started Dec 31 12:53:00 PM PST 23
Finished Dec 31 12:53:13 PM PST 23
Peak memory 214172 kb
Host smart-665561e9-6651-4e0e-be61-77fcf5c2f9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452517577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.3452517577
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.1429027601
Short name T37
Test name
Test status
Simulation time 30544940 ps
CPU time 0.84 seconds
Started Dec 31 12:53:01 PM PST 23
Finished Dec 31 12:53:14 PM PST 23
Peak memory 214280 kb
Host smart-97e5d836-bdd6-4fa0-9dee-108ddf9c9e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429027601 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.1429027601
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.1444986235
Short name T873
Test name
Test status
Simulation time 137590540 ps
CPU time 0.82 seconds
Started Dec 31 12:53:12 PM PST 23
Finished Dec 31 12:53:28 PM PST 23
Peak memory 204608 kb
Host smart-f14c3061-6ba7-4ce4-a98a-cab0f33cccfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444986235 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.1444986235
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.2390582279
Short name T107
Test name
Test status
Simulation time 1148000002 ps
CPU time 2.96 seconds
Started Dec 31 12:53:07 PM PST 23
Finished Dec 31 12:53:20 PM PST 23
Peak memory 205704 kb
Host smart-a2a2dd2e-1b58-406f-9037-3b4a4a13e295
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390582279 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.2390582279
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/230.edn_genbits.92649670
Short name T689
Test name
Test status
Simulation time 70218326 ps
CPU time 1.3 seconds
Started Dec 31 12:54:23 PM PST 23
Finished Dec 31 12:54:25 PM PST 23
Peak memory 205900 kb
Host smart-194a85be-978e-4a1a-a274-794c603176e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92649670 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.92649670
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.2281483917
Short name T608
Test name
Test status
Simulation time 60358604 ps
CPU time 2.51 seconds
Started Dec 31 12:54:12 PM PST 23
Finished Dec 31 12:54:18 PM PST 23
Peak memory 214116 kb
Host smart-0928f4bc-5ca0-4115-b6f9-e9235b8e9346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281483917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.2281483917
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.650845424
Short name T705
Test name
Test status
Simulation time 146416775 ps
CPU time 1.12 seconds
Started Dec 31 12:54:14 PM PST 23
Finished Dec 31 12:54:18 PM PST 23
Peak memory 205380 kb
Host smart-afdbbe00-4286-4d39-8f4b-ebacbf6d9be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650845424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.650845424
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.1055154725
Short name T630
Test name
Test status
Simulation time 49589694 ps
CPU time 0.9 seconds
Started Dec 31 12:54:45 PM PST 23
Finished Dec 31 12:54:48 PM PST 23
Peak memory 205208 kb
Host smart-de16db6f-98fc-416a-9960-a680d90e8391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055154725 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.1055154725
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.473928118
Short name T66
Test name
Test status
Simulation time 31216566 ps
CPU time 0.93 seconds
Started Dec 31 12:54:13 PM PST 23
Finished Dec 31 12:54:17 PM PST 23
Peak memory 205104 kb
Host smart-9d7d32bd-5fcd-4215-b795-7e15cac63f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473928118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.473928118
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.2500979493
Short name T77
Test name
Test status
Simulation time 125798556 ps
CPU time 0.89 seconds
Started Dec 31 12:54:48 PM PST 23
Finished Dec 31 12:54:53 PM PST 23
Peak memory 204836 kb
Host smart-16bc6872-b1fb-4f69-9342-05be607a0cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500979493 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.2500979493
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.3145310012
Short name T914
Test name
Test status
Simulation time 21976560 ps
CPU time 1.05 seconds
Started Dec 31 12:53:11 PM PST 23
Finished Dec 31 12:53:22 PM PST 23
Peak memory 205656 kb
Host smart-d9544e76-b882-435e-a2e2-157e048b18d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145310012 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.3145310012
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.2855748988
Short name T893
Test name
Test status
Simulation time 11039082 ps
CPU time 0.82 seconds
Started Dec 31 12:53:06 PM PST 23
Finished Dec 31 12:53:18 PM PST 23
Peak memory 204068 kb
Host smart-89055e9a-29cf-4e3d-a5b4-a2032df4e760
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855748988 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.2855748988
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.2341719812
Short name T965
Test name
Test status
Simulation time 116843126 ps
CPU time 1.42 seconds
Started Dec 31 12:53:05 PM PST 23
Finished Dec 31 12:53:19 PM PST 23
Peak memory 214512 kb
Host smart-61c3f6e2-e2ad-408c-abfb-b9f0038be277
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341719812 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.2341719812
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.1378610810
Short name T229
Test name
Test status
Simulation time 20194239 ps
CPU time 1.04 seconds
Started Dec 31 12:53:03 PM PST 23
Finished Dec 31 12:53:18 PM PST 23
Peak memory 215568 kb
Host smart-3930b205-64b8-4030-8f5f-5ece331f2765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378610810 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.1378610810
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.692937450
Short name T717
Test name
Test status
Simulation time 51179122 ps
CPU time 0.94 seconds
Started Dec 31 12:52:59 PM PST 23
Finished Dec 31 12:53:03 PM PST 23
Peak memory 205368 kb
Host smart-62d745cb-e5ba-45ab-8e27-358c0f16683c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692937450 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.692937450
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.1142651132
Short name T743
Test name
Test status
Simulation time 20673834 ps
CPU time 1.09 seconds
Started Dec 31 12:52:54 PM PST 23
Finished Dec 31 12:52:58 PM PST 23
Peak memory 221852 kb
Host smart-f7912078-4c14-474b-a5a4-96e900eee077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142651132 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.1142651132
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.1777105730
Short name T715
Test name
Test status
Simulation time 24860664 ps
CPU time 0.87 seconds
Started Dec 31 12:53:07 PM PST 23
Finished Dec 31 12:53:18 PM PST 23
Peak memory 204808 kb
Host smart-8444ab1d-5ff9-44f1-8fe3-15eb82c9a309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777105730 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.1777105730
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.621858667
Short name T491
Test name
Test status
Simulation time 99199180 ps
CPU time 2.28 seconds
Started Dec 31 12:52:58 PM PST 23
Finished Dec 31 12:53:04 PM PST 23
Peak memory 205828 kb
Host smart-9d104499-be12-4117-bbae-a7489b5935d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621858667 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.621858667
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.1773309996
Short name T534
Test name
Test status
Simulation time 86974630297 ps
CPU time 208.15 seconds
Started Dec 31 12:53:08 PM PST 23
Finished Dec 31 12:56:46 PM PST 23
Peak memory 216180 kb
Host smart-ba6ea92b-a0e4-4fa2-ba0e-28cc0f9c6ddf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773309996 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1773309996
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.949796870
Short name T549
Test name
Test status
Simulation time 62668328 ps
CPU time 0.96 seconds
Started Dec 31 12:54:39 PM PST 23
Finished Dec 31 12:54:41 PM PST 23
Peak memory 205512 kb
Host smart-9470bc6d-3dad-4f66-9cfa-6214924f6ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949796870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.949796870
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.554236441
Short name T300
Test name
Test status
Simulation time 56526656 ps
CPU time 1.13 seconds
Started Dec 31 12:54:45 PM PST 23
Finished Dec 31 12:54:49 PM PST 23
Peak memory 214188 kb
Host smart-927025fe-a32d-4b70-bbcc-d36e6a48b1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554236441 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.554236441
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.1293283136
Short name T475
Test name
Test status
Simulation time 55284046 ps
CPU time 1.47 seconds
Started Dec 31 12:54:46 PM PST 23
Finished Dec 31 12:54:52 PM PST 23
Peak memory 214124 kb
Host smart-4495cf14-b883-4bcc-b614-00237cda9d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293283136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1293283136
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.584835225
Short name T747
Test name
Test status
Simulation time 19099257 ps
CPU time 0.99 seconds
Started Dec 31 12:54:35 PM PST 23
Finished Dec 31 12:54:37 PM PST 23
Peak memory 205136 kb
Host smart-9cb82d99-8089-4979-8361-3feae2a4dd6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584835225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.584835225
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.1482009710
Short name T957
Test name
Test status
Simulation time 28211582 ps
CPU time 0.91 seconds
Started Dec 31 12:54:39 PM PST 23
Finished Dec 31 12:54:42 PM PST 23
Peak memory 205424 kb
Host smart-1aa6bdaa-a92d-4203-ae4f-c8365f6f5214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482009710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.1482009710
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.337746924
Short name T662
Test name
Test status
Simulation time 35213736 ps
CPU time 1 seconds
Started Dec 31 12:54:24 PM PST 23
Finished Dec 31 12:54:26 PM PST 23
Peak memory 205596 kb
Host smart-728a7231-bb91-4fe8-aa18-acf6458e47fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337746924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.337746924
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.1676404173
Short name T763
Test name
Test status
Simulation time 12376973 ps
CPU time 0.94 seconds
Started Dec 31 12:54:49 PM PST 23
Finished Dec 31 12:54:54 PM PST 23
Peak memory 205024 kb
Host smart-7b74ff3a-184a-4c95-af0d-dcbb7eb6c3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676404173 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.1676404173
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.1206257323
Short name T739
Test name
Test status
Simulation time 18825646 ps
CPU time 1.03 seconds
Started Dec 31 12:54:29 PM PST 23
Finished Dec 31 12:54:31 PM PST 23
Peak memory 205648 kb
Host smart-b6958639-aa25-4a57-917e-0123bd034ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206257323 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.1206257323
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.196354214
Short name T629
Test name
Test status
Simulation time 95228720 ps
CPU time 1.02 seconds
Started Dec 31 12:54:42 PM PST 23
Finished Dec 31 12:54:45 PM PST 23
Peak memory 214064 kb
Host smart-cd6bf72d-11d7-4009-86f0-4332b98b121d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196354214 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.196354214
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.793485897
Short name T860
Test name
Test status
Simulation time 119218688 ps
CPU time 0.94 seconds
Started Dec 31 12:53:11 PM PST 23
Finished Dec 31 12:53:32 PM PST 23
Peak memory 205948 kb
Host smart-b9d28e10-4b73-407c-8bb0-8e70c6164458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793485897 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.793485897
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.37646574
Short name T854
Test name
Test status
Simulation time 56308457 ps
CPU time 0.91 seconds
Started Dec 31 12:53:26 PM PST 23
Finished Dec 31 12:53:40 PM PST 23
Peak memory 205140 kb
Host smart-c1a5f81d-cbee-4341-aa5e-2b7ea74aa4d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37646574 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.37646574
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.1035860586
Short name T817
Test name
Test status
Simulation time 34862100 ps
CPU time 0.83 seconds
Started Dec 31 12:53:40 PM PST 23
Finished Dec 31 12:53:53 PM PST 23
Peak memory 214216 kb
Host smart-7277c02b-3e6e-4aa3-b645-edc939c6db46
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035860586 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.1035860586
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.1280083733
Short name T117
Test name
Test status
Simulation time 24665962 ps
CPU time 1.07 seconds
Started Dec 31 12:53:00 PM PST 23
Finished Dec 31 12:53:13 PM PST 23
Peak memory 214528 kb
Host smart-3f4f1395-6225-420d-972e-b18d7f3b4cd4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280083733 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.1280083733
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.652674607
Short name T15
Test name
Test status
Simulation time 18999618 ps
CPU time 1.14 seconds
Started Dec 31 12:53:07 PM PST 23
Finished Dec 31 12:53:19 PM PST 23
Peak memory 228444 kb
Host smart-1f6ac910-8574-489d-88e6-41e413fe55ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652674607 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.652674607
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.3376251468
Short name T557
Test name
Test status
Simulation time 18175080 ps
CPU time 1.12 seconds
Started Dec 31 12:53:05 PM PST 23
Finished Dec 31 12:53:19 PM PST 23
Peak memory 214084 kb
Host smart-d33a60fe-b33e-4efa-9dda-d9575b3523c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376251468 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3376251468
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.922621346
Short name T882
Test name
Test status
Simulation time 28935744 ps
CPU time 0.83 seconds
Started Dec 31 12:53:13 PM PST 23
Finished Dec 31 12:53:31 PM PST 23
Peak memory 214232 kb
Host smart-8610d741-e9f5-4d06-8428-a2a69f6e818c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922621346 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.922621346
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.2739101423
Short name T807
Test name
Test status
Simulation time 41951625 ps
CPU time 0.86 seconds
Started Dec 31 12:52:58 PM PST 23
Finished Dec 31 12:53:02 PM PST 23
Peak memory 204552 kb
Host smart-bdafc04f-1aca-40ec-9124-656eb051c187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739101423 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.2739101423
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.1595628268
Short name T850
Test name
Test status
Simulation time 499395366 ps
CPU time 1.76 seconds
Started Dec 31 12:53:15 PM PST 23
Finished Dec 31 12:53:34 PM PST 23
Peak memory 205636 kb
Host smart-1a35829c-0299-4eba-8966-6bd1f50340e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595628268 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.1595628268
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.1762303164
Short name T635
Test name
Test status
Simulation time 233368391099 ps
CPU time 524.04 seconds
Started Dec 31 12:53:05 PM PST 23
Finished Dec 31 01:02:02 PM PST 23
Peak memory 215260 kb
Host smart-85e5143a-7af9-4fb5-b260-8cf9dfd0a99f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762303164 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.1762303164
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.380713539
Short name T885
Test name
Test status
Simulation time 58619817 ps
CPU time 1.01 seconds
Started Dec 31 12:54:47 PM PST 23
Finished Dec 31 12:54:52 PM PST 23
Peak memory 214076 kb
Host smart-88ae77b6-df53-4f9c-bcc7-f52eee25d4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380713539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.380713539
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.3248466426
Short name T780
Test name
Test status
Simulation time 57129921 ps
CPU time 2.12 seconds
Started Dec 31 12:54:37 PM PST 23
Finished Dec 31 12:54:41 PM PST 23
Peak memory 214204 kb
Host smart-2344c5be-df1f-4235-b27f-fbe6e78a7d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248466426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.3248466426
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.1090441032
Short name T567
Test name
Test status
Simulation time 25267078 ps
CPU time 0.9 seconds
Started Dec 31 12:54:41 PM PST 23
Finished Dec 31 12:54:44 PM PST 23
Peak memory 204996 kb
Host smart-7a6dd50b-f3dc-4129-95d2-74d4aa025fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090441032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.1090441032
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.152549947
Short name T479
Test name
Test status
Simulation time 58582011 ps
CPU time 1.07 seconds
Started Dec 31 12:54:42 PM PST 23
Finished Dec 31 12:54:45 PM PST 23
Peak memory 205432 kb
Host smart-d27a72b0-cf39-410f-bc6d-cab1adf775a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152549947 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.152549947
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.1510659482
Short name T897
Test name
Test status
Simulation time 18765513 ps
CPU time 1.05 seconds
Started Dec 31 12:54:08 PM PST 23
Finished Dec 31 12:54:14 PM PST 23
Peak memory 205096 kb
Host smart-d087001a-5ce2-4b34-889c-2de6d3022ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510659482 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.1510659482
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.477028330
Short name T775
Test name
Test status
Simulation time 72177203 ps
CPU time 1.27 seconds
Started Dec 31 12:54:52 PM PST 23
Finished Dec 31 12:54:58 PM PST 23
Peak memory 214032 kb
Host smart-e3bb3803-4560-4f6b-bbe1-b9411126d427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477028330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.477028330
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.1194211506
Short name T843
Test name
Test status
Simulation time 18298748 ps
CPU time 0.98 seconds
Started Dec 31 12:54:25 PM PST 23
Finished Dec 31 12:54:28 PM PST 23
Peak memory 205084 kb
Host smart-19e852db-770f-4c2a-a3db-d4d529e08975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194211506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.1194211506
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.1210475071
Short name T825
Test name
Test status
Simulation time 410143812 ps
CPU time 3.7 seconds
Started Dec 31 12:54:56 PM PST 23
Finished Dec 31 12:55:04 PM PST 23
Peak memory 214152 kb
Host smart-8e1bbe38-0453-4ef1-9adc-a9d77f4dd43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210475071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.1210475071
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.1928136246
Short name T299
Test name
Test status
Simulation time 53810748 ps
CPU time 0.88 seconds
Started Dec 31 12:54:53 PM PST 23
Finished Dec 31 12:54:58 PM PST 23
Peak memory 204960 kb
Host smart-b35a251b-6c35-44aa-8b7c-594571071f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928136246 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.1928136246
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.3877681655
Short name T506
Test name
Test status
Simulation time 33077624 ps
CPU time 1.05 seconds
Started Dec 31 12:54:27 PM PST 23
Finished Dec 31 12:54:29 PM PST 23
Peak memory 214092 kb
Host smart-485ed7c7-2e9b-4c93-915e-60e8195214dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877681655 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.3877681655
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.1745636448
Short name T665
Test name
Test status
Simulation time 86927696 ps
CPU time 0.98 seconds
Started Dec 31 12:53:44 PM PST 23
Finished Dec 31 12:53:57 PM PST 23
Peak memory 205368 kb
Host smart-7d597add-217b-4495-85c9-bbc85bae9603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745636448 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.1745636448
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.3853286155
Short name T845
Test name
Test status
Simulation time 27637531 ps
CPU time 0.83 seconds
Started Dec 31 12:53:47 PM PST 23
Finished Dec 31 12:54:00 PM PST 23
Peak memory 205396 kb
Host smart-093f64a6-40b9-4c84-9fb1-365571b60b59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853286155 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.3853286155
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.1855247846
Short name T133
Test name
Test status
Simulation time 42431106 ps
CPU time 0.85 seconds
Started Dec 31 12:53:44 PM PST 23
Finished Dec 31 12:53:57 PM PST 23
Peak memory 214268 kb
Host smart-d440ac80-a36c-4461-8f58-b1197403c5a0
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855247846 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.1855247846
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.324231441
Short name T737
Test name
Test status
Simulation time 32436580 ps
CPU time 1.09 seconds
Started Dec 31 12:53:35 PM PST 23
Finished Dec 31 12:53:49 PM PST 23
Peak memory 214568 kb
Host smart-e8eefa38-9ce1-47f6-8341-4ad2b33801b6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324231441 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_di
sable_auto_req_mode.324231441
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_genbits.1305140013
Short name T955
Test name
Test status
Simulation time 18522228 ps
CPU time 1.19 seconds
Started Dec 31 12:53:43 PM PST 23
Finished Dec 31 12:53:56 PM PST 23
Peak memory 205712 kb
Host smart-f921abf6-7abc-497d-86fd-6343bfad152f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305140013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.1305140013
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.2406382535
Short name T745
Test name
Test status
Simulation time 22610670 ps
CPU time 0.92 seconds
Started Dec 31 12:53:44 PM PST 23
Finished Dec 31 12:53:57 PM PST 23
Peak memory 214272 kb
Host smart-9da9a179-03a5-4f57-9d5b-cee2c93a5018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406382535 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.2406382535
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.3695558859
Short name T832
Test name
Test status
Simulation time 45811685 ps
CPU time 0.86 seconds
Started Dec 31 12:53:32 PM PST 23
Finished Dec 31 12:53:45 PM PST 23
Peak memory 204848 kb
Host smart-8207d462-3882-458a-ac5f-4a0249908c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695558859 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.3695558859
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.1824837498
Short name T526
Test name
Test status
Simulation time 379437560 ps
CPU time 4.45 seconds
Started Dec 31 12:53:14 PM PST 23
Finished Dec 31 12:53:36 PM PST 23
Peak memory 205720 kb
Host smart-89689f05-eed7-45a7-928c-15adf86fe857
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824837498 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.1824837498
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.1809062967
Short name T603
Test name
Test status
Simulation time 29426327595 ps
CPU time 239.08 seconds
Started Dec 31 12:53:16 PM PST 23
Finished Dec 31 12:57:32 PM PST 23
Peak memory 215396 kb
Host smart-d750c3b9-eab8-4212-b0dc-36adc0c9193f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809062967 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.1809062967
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.645949995
Short name T637
Test name
Test status
Simulation time 106852964 ps
CPU time 2.63 seconds
Started Dec 31 12:54:04 PM PST 23
Finished Dec 31 12:54:14 PM PST 23
Peak memory 214160 kb
Host smart-f62f95c3-e7b2-4c13-bc01-101be316ac11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645949995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.645949995
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.1083863762
Short name T559
Test name
Test status
Simulation time 33057165 ps
CPU time 0.99 seconds
Started Dec 31 12:55:08 PM PST 23
Finished Dec 31 12:55:14 PM PST 23
Peak memory 205332 kb
Host smart-6e34d075-11ff-4f10-af37-9f2d010e681e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083863762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.1083863762
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.2735355592
Short name T330
Test name
Test status
Simulation time 40654814 ps
CPU time 0.96 seconds
Started Dec 31 12:54:22 PM PST 23
Finished Dec 31 12:54:29 PM PST 23
Peak memory 205464 kb
Host smart-f869193d-5d59-4872-b20b-6c1a8b2826cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735355592 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.2735355592
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.4079269321
Short name T585
Test name
Test status
Simulation time 309638761 ps
CPU time 1.17 seconds
Started Dec 31 12:54:12 PM PST 23
Finished Dec 31 12:54:20 PM PST 23
Peak memory 205512 kb
Host smart-2202574b-21ea-4ad2-91d8-8005f1e7d628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079269321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.4079269321
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.680375480
Short name T823
Test name
Test status
Simulation time 68154941 ps
CPU time 1.09 seconds
Started Dec 31 12:54:47 PM PST 23
Finished Dec 31 12:54:53 PM PST 23
Peak memory 205396 kb
Host smart-d5a67e28-0e06-43e2-a41a-66e2746c906c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680375480 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.680375480
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.3136246577
Short name T967
Test name
Test status
Simulation time 17115288 ps
CPU time 1.04 seconds
Started Dec 31 12:55:04 PM PST 23
Finished Dec 31 12:55:10 PM PST 23
Peak memory 205760 kb
Host smart-d4bae97f-aff0-455b-b4c0-0d2e2b1f2467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136246577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.3136246577
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.3719383386
Short name T363
Test name
Test status
Simulation time 76152921 ps
CPU time 0.91 seconds
Started Dec 31 12:54:28 PM PST 23
Finished Dec 31 12:54:31 PM PST 23
Peak memory 205028 kb
Host smart-343e37cb-b144-4401-ab3d-29c530bc9636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719383386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.3719383386
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.4165773474
Short name T656
Test name
Test status
Simulation time 89211909 ps
CPU time 1.02 seconds
Started Dec 31 12:54:53 PM PST 23
Finished Dec 31 12:54:58 PM PST 23
Peak memory 205176 kb
Host smart-5d9139e3-6bbb-467b-b646-a29889260435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165773474 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.4165773474
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.963294368
Short name T362
Test name
Test status
Simulation time 60560358 ps
CPU time 0.98 seconds
Started Dec 31 12:54:17 PM PST 23
Finished Dec 31 12:54:20 PM PST 23
Peak memory 205328 kb
Host smart-4606bda2-681f-4fa0-ad1c-b27c90b1b1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963294368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.963294368
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.2803990511
Short name T12
Test name
Test status
Simulation time 21112741 ps
CPU time 1.09 seconds
Started Dec 31 12:55:01 PM PST 23
Finished Dec 31 12:55:08 PM PST 23
Peak memory 214116 kb
Host smart-c9e554d5-049a-4b94-8f2b-64c31bfe7485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803990511 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.2803990511
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.2771601665
Short name T349
Test name
Test status
Simulation time 66053866 ps
CPU time 0.94 seconds
Started Dec 31 12:53:24 PM PST 23
Finished Dec 31 12:53:38 PM PST 23
Peak memory 205316 kb
Host smart-6554da0f-a5ba-4989-81bf-1af51624df48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771601665 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.2771601665
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.4063798525
Short name T484
Test name
Test status
Simulation time 69608574 ps
CPU time 0.86 seconds
Started Dec 31 12:53:10 PM PST 23
Finished Dec 31 12:53:20 PM PST 23
Peak memory 204524 kb
Host smart-36a4d1f9-c603-463c-b8a4-7be5577eaef2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063798525 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.4063798525
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.2866220899
Short name T192
Test name
Test status
Simulation time 21929355 ps
CPU time 0.95 seconds
Started Dec 31 12:53:11 PM PST 23
Finished Dec 31 12:53:24 PM PST 23
Peak memory 214532 kb
Host smart-0496cdbe-8ca3-440a-bfb6-a81c9f72d91a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866220899 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.2866220899
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.2241137911
Short name T478
Test name
Test status
Simulation time 18574486 ps
CPU time 1.34 seconds
Started Dec 31 12:53:13 PM PST 23
Finished Dec 31 12:53:32 PM PST 23
Peak memory 215848 kb
Host smart-f95e3b46-a928-433d-9676-a03970a5ef80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241137911 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.2241137911
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.3650515403
Short name T801
Test name
Test status
Simulation time 82708422 ps
CPU time 0.91 seconds
Started Dec 31 12:53:08 PM PST 23
Finished Dec 31 12:53:19 PM PST 23
Peak memory 204996 kb
Host smart-7df61732-cad5-4a00-a0fd-1f2d56c3c3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650515403 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.3650515403
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.3092752337
Short name T488
Test name
Test status
Simulation time 30262740 ps
CPU time 0.9 seconds
Started Dec 31 12:52:56 PM PST 23
Finished Dec 31 12:53:01 PM PST 23
Peak memory 214296 kb
Host smart-801593d9-f3a6-4647-b1ee-9d53fd8c2602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092752337 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.3092752337
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.1974156579
Short name T616
Test name
Test status
Simulation time 42558576 ps
CPU time 0.81 seconds
Started Dec 31 12:53:01 PM PST 23
Finished Dec 31 12:53:13 PM PST 23
Peak memory 204736 kb
Host smart-191e95d1-db04-49ad-b1bb-9afbbd8d5a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974156579 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.1974156579
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.3112347838
Short name T785
Test name
Test status
Simulation time 269987605 ps
CPU time 3.15 seconds
Started Dec 31 12:53:09 PM PST 23
Finished Dec 31 12:53:21 PM PST 23
Peak memory 205520 kb
Host smart-081e040c-dcbc-4ef2-9463-5dc5e310c180
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112347838 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.3112347838
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.2874056141
Short name T563
Test name
Test status
Simulation time 42042714593 ps
CPU time 470.21 seconds
Started Dec 31 12:52:59 PM PST 23
Finished Dec 31 01:00:52 PM PST 23
Peak memory 214488 kb
Host smart-838c8bdf-1b7f-4865-abb6-2dbc068ee669
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874056141 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.2874056141
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.14087330
Short name T297
Test name
Test status
Simulation time 46438614 ps
CPU time 0.88 seconds
Started Dec 31 12:55:09 PM PST 23
Finished Dec 31 12:55:16 PM PST 23
Peak memory 204788 kb
Host smart-abcee143-c702-495d-b814-acf035c646cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14087330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.14087330
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.1340121708
Short name T948
Test name
Test status
Simulation time 19592356 ps
CPU time 1.2 seconds
Started Dec 31 12:55:00 PM PST 23
Finished Dec 31 12:55:07 PM PST 23
Peak memory 205608 kb
Host smart-810ee09c-bca1-458a-b8e9-6343c139cc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340121708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.1340121708
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.3859081262
Short name T39
Test name
Test status
Simulation time 52492185 ps
CPU time 0.89 seconds
Started Dec 31 12:54:06 PM PST 23
Finished Dec 31 12:54:14 PM PST 23
Peak memory 204836 kb
Host smart-a5559615-677b-454f-a6a5-7660dd6ca255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859081262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.3859081262
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.1393379154
Short name T884
Test name
Test status
Simulation time 26314930 ps
CPU time 0.91 seconds
Started Dec 31 12:54:40 PM PST 23
Finished Dec 31 12:54:43 PM PST 23
Peak memory 205076 kb
Host smart-46db0ef5-31c9-4ecb-b2fb-6ffc6d1b7a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393379154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.1393379154
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.1832343943
Short name T666
Test name
Test status
Simulation time 80436322 ps
CPU time 1.09 seconds
Started Dec 31 12:55:10 PM PST 23
Finished Dec 31 12:55:18 PM PST 23
Peak memory 205492 kb
Host smart-633e3597-9b7e-4b80-a576-5e7d7fc9eaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832343943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.1832343943
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.1440271845
Short name T331
Test name
Test status
Simulation time 52331182 ps
CPU time 1 seconds
Started Dec 31 12:54:32 PM PST 23
Finished Dec 31 12:54:34 PM PST 23
Peak memory 205400 kb
Host smart-1ec9af8d-3f8d-4789-88e3-eb6c0921a5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440271845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.1440271845
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.3589466015
Short name T755
Test name
Test status
Simulation time 26600626 ps
CPU time 1.26 seconds
Started Dec 31 12:54:26 PM PST 23
Finished Dec 31 12:54:29 PM PST 23
Peak memory 205460 kb
Host smart-2abf4201-e7d6-4a9b-93b7-e1fd1cab7a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589466015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3589466015
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.4283980352
Short name T541
Test name
Test status
Simulation time 237171543 ps
CPU time 2.5 seconds
Started Dec 31 12:54:24 PM PST 23
Finished Dec 31 12:54:29 PM PST 23
Peak memory 213956 kb
Host smart-48e7cec9-11be-4227-8f7d-6efaf78ecfee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283980352 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.4283980352
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.2922698298
Short name T636
Test name
Test status
Simulation time 55434242 ps
CPU time 0.99 seconds
Started Dec 31 12:54:59 PM PST 23
Finished Dec 31 12:55:06 PM PST 23
Peak memory 205584 kb
Host smart-08d70e32-82eb-43bb-95ac-20a3a3809228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922698298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.2922698298
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.3417800420
Short name T354
Test name
Test status
Simulation time 28070323 ps
CPU time 1.07 seconds
Started Dec 31 12:53:31 PM PST 23
Finished Dec 31 12:53:44 PM PST 23
Peak memory 205952 kb
Host smart-0f430d6d-ff04-4a29-bf70-38b16653ba55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417800420 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.3417800420
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.1249213495
Short name T624
Test name
Test status
Simulation time 19635946 ps
CPU time 0.96 seconds
Started Dec 31 12:53:26 PM PST 23
Finished Dec 31 12:53:40 PM PST 23
Peak memory 205048 kb
Host smart-70a29df6-787e-4d87-ac20-00a26c0cc7c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249213495 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.1249213495
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.3183600453
Short name T911
Test name
Test status
Simulation time 17782484 ps
CPU time 0.85 seconds
Started Dec 31 12:53:20 PM PST 23
Finished Dec 31 12:53:36 PM PST 23
Peak memory 214252 kb
Host smart-41c423df-0788-4164-ac15-d60053de8da9
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183600453 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.3183600453
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.555698220
Short name T569
Test name
Test status
Simulation time 321152797 ps
CPU time 1.08 seconds
Started Dec 31 12:53:33 PM PST 23
Finished Dec 31 12:53:46 PM PST 23
Peak memory 214444 kb
Host smart-eb896bb8-c7a4-43f7-b142-745989f6873d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555698220 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_di
sable_auto_req_mode.555698220
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.474816977
Short name T263
Test name
Test status
Simulation time 178999524 ps
CPU time 0.98 seconds
Started Dec 31 12:53:38 PM PST 23
Finished Dec 31 12:53:51 PM PST 23
Peak memory 214716 kb
Host smart-6f6376b4-5bf3-4cff-a1d5-95015506e98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474816977 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.474816977
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.452595305
Short name T760
Test name
Test status
Simulation time 179199348 ps
CPU time 1.03 seconds
Started Dec 31 12:53:20 PM PST 23
Finished Dec 31 12:53:36 PM PST 23
Peak memory 205144 kb
Host smart-7e9139d9-2dd3-4c16-8693-749617db9f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452595305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.452595305
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_smoke.639045253
Short name T73
Test name
Test status
Simulation time 44363422 ps
CPU time 0.83 seconds
Started Dec 31 12:53:35 PM PST 23
Finished Dec 31 12:53:51 PM PST 23
Peak memory 204732 kb
Host smart-a01e6785-a8d6-452a-ad37-e93a2486ed35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639045253 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.639045253
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.786870275
Short name T468
Test name
Test status
Simulation time 52264091 ps
CPU time 1.09 seconds
Started Dec 31 12:53:21 PM PST 23
Finished Dec 31 12:53:36 PM PST 23
Peak memory 205484 kb
Host smart-1bd9f4c5-d88a-4a6d-b12b-5c329d23ffab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786870275 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.786870275
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.138149221
Short name T820
Test name
Test status
Simulation time 31278199747 ps
CPU time 746.55 seconds
Started Dec 31 12:53:05 PM PST 23
Finished Dec 31 01:05:44 PM PST 23
Peak memory 215112 kb
Host smart-edf933b4-c117-4f1c-b30f-31cb04ee08cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138149221 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.138149221
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.2817855642
Short name T519
Test name
Test status
Simulation time 85905479 ps
CPU time 1.01 seconds
Started Dec 31 12:54:11 PM PST 23
Finished Dec 31 12:54:15 PM PST 23
Peak memory 205124 kb
Host smart-70951a76-caed-44f3-8cc7-7ff6b5cc69d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817855642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.2817855642
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.2446889274
Short name T62
Test name
Test status
Simulation time 40357252 ps
CPU time 0.89 seconds
Started Dec 31 12:54:21 PM PST 23
Finished Dec 31 12:54:23 PM PST 23
Peak memory 205024 kb
Host smart-b91203fd-88d9-4f02-b90f-a55cb7392deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446889274 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.2446889274
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.66442089
Short name T556
Test name
Test status
Simulation time 20279242 ps
CPU time 0.99 seconds
Started Dec 31 12:54:17 PM PST 23
Finished Dec 31 12:54:20 PM PST 23
Peak memory 205184 kb
Host smart-b0d1e4b3-08ae-4113-b116-78dd914674c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66442089 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.66442089
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.460561276
Short name T502
Test name
Test status
Simulation time 21841259 ps
CPU time 1.04 seconds
Started Dec 31 12:54:36 PM PST 23
Finished Dec 31 12:54:38 PM PST 23
Peak memory 214100 kb
Host smart-9d4f5e36-4197-455e-bffe-43ac8e647039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460561276 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.460561276
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.3646598020
Short name T374
Test name
Test status
Simulation time 157536616 ps
CPU time 0.85 seconds
Started Dec 31 12:54:14 PM PST 23
Finished Dec 31 12:54:18 PM PST 23
Peak memory 205052 kb
Host smart-013f6e34-f4d2-499e-8b7c-bf28abd03336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646598020 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.3646598020
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.4009826325
Short name T734
Test name
Test status
Simulation time 42204050 ps
CPU time 1.88 seconds
Started Dec 31 12:55:09 PM PST 23
Finished Dec 31 12:55:22 PM PST 23
Peak memory 214132 kb
Host smart-26f8f306-b17a-4810-bfaa-fc34f92e4637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009826325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.4009826325
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.4195666097
Short name T628
Test name
Test status
Simulation time 56987921 ps
CPU time 1.02 seconds
Started Dec 31 12:54:17 PM PST 23
Finished Dec 31 12:54:20 PM PST 23
Peak memory 205256 kb
Host smart-dd31c11f-d9bf-4c3b-afa9-9f7dcd8c16cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195666097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.4195666097
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.245015025
Short name T522
Test name
Test status
Simulation time 57456374 ps
CPU time 2.35 seconds
Started Dec 31 12:54:36 PM PST 23
Finished Dec 31 12:54:39 PM PST 23
Peak memory 214196 kb
Host smart-e6b7707e-46a7-4a7c-89db-b749b62494fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245015025 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.245015025
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.2007164220
Short name T524
Test name
Test status
Simulation time 15669861 ps
CPU time 0.93 seconds
Started Dec 31 12:54:44 PM PST 23
Finished Dec 31 12:54:48 PM PST 23
Peak memory 205112 kb
Host smart-7c89490f-914b-4e87-acc2-e2eeb6439efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007164220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.2007164220
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.1920787836
Short name T736
Test name
Test status
Simulation time 76378476 ps
CPU time 0.92 seconds
Started Dec 31 12:53:16 PM PST 23
Finished Dec 31 12:53:34 PM PST 23
Peak memory 205132 kb
Host smart-77cc893d-178b-4061-b6c3-b1e500dd237c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920787836 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.1920787836
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.2901209325
Short name T846
Test name
Test status
Simulation time 16291676 ps
CPU time 0.87 seconds
Started Dec 31 12:53:14 PM PST 23
Finished Dec 31 12:53:33 PM PST 23
Peak memory 205040 kb
Host smart-90208d53-0ed7-44a5-a72b-4047d008b5a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901209325 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.2901209325
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.3994151095
Short name T256
Test name
Test status
Simulation time 99479980 ps
CPU time 0.93 seconds
Started Dec 31 12:53:11 PM PST 23
Finished Dec 31 12:53:23 PM PST 23
Peak memory 214496 kb
Host smart-9780fa6d-27fd-469b-9288-36dec627d599
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994151095 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.3994151095
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.4138410137
Short name T173
Test name
Test status
Simulation time 23484247 ps
CPU time 1.02 seconds
Started Dec 31 12:53:00 PM PST 23
Finished Dec 31 12:53:12 PM PST 23
Peak memory 228684 kb
Host smart-411a47a8-beab-4d12-8261-f8b5c191d3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138410137 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.4138410137
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.1010814946
Short name T322
Test name
Test status
Simulation time 13587640 ps
CPU time 0.93 seconds
Started Dec 31 12:53:59 PM PST 23
Finished Dec 31 12:54:09 PM PST 23
Peak memory 205384 kb
Host smart-ec93f77b-45ea-4c9f-ba6c-5dfe5eae3d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010814946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.1010814946
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.3648882982
Short name T582
Test name
Test status
Simulation time 40005601 ps
CPU time 0.97 seconds
Started Dec 31 12:53:34 PM PST 23
Finished Dec 31 12:53:47 PM PST 23
Peak memory 221804 kb
Host smart-3b461428-7308-43af-b170-1170f2ae49f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648882982 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.3648882982
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.984531770
Short name T652
Test name
Test status
Simulation time 39045002 ps
CPU time 0.85 seconds
Started Dec 31 12:53:27 PM PST 23
Finished Dec 31 12:53:40 PM PST 23
Peak memory 204548 kb
Host smart-61426b48-4f4f-4b99-8646-ade9cfda871b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984531770 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.984531770
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.1215449583
Short name T509
Test name
Test status
Simulation time 796566571 ps
CPU time 4.17 seconds
Started Dec 31 12:53:12 PM PST 23
Finished Dec 31 12:53:30 PM PST 23
Peak memory 205980 kb
Host smart-886a04bd-a455-4de5-b931-656b40155c2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215449583 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1215449583
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.2778765867
Short name T899
Test name
Test status
Simulation time 136569679009 ps
CPU time 757.35 seconds
Started Dec 31 12:53:38 PM PST 23
Finished Dec 31 01:06:28 PM PST 23
Peak memory 214316 kb
Host smart-c87054b3-2e5b-48d0-afe8-f70b0cb4287b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778765867 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.2778765867
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.998360156
Short name T758
Test name
Test status
Simulation time 15080773 ps
CPU time 0.9 seconds
Started Dec 31 12:54:38 PM PST 23
Finished Dec 31 12:54:41 PM PST 23
Peak memory 205008 kb
Host smart-66ca6348-cbe8-447b-b4ee-3fa3afcdffd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998360156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.998360156
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.4112588009
Short name T837
Test name
Test status
Simulation time 51659224 ps
CPU time 0.95 seconds
Started Dec 31 12:54:34 PM PST 23
Finished Dec 31 12:54:37 PM PST 23
Peak memory 204976 kb
Host smart-bf5b51c0-ab0f-4beb-9bf6-c0e09735dadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112588009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.4112588009
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.3129255020
Short name T768
Test name
Test status
Simulation time 69272037 ps
CPU time 0.89 seconds
Started Dec 31 12:54:33 PM PST 23
Finished Dec 31 12:54:34 PM PST 23
Peak memory 205216 kb
Host smart-8e0c90e7-5fb7-4b8f-82c0-07cc400f3a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129255020 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.3129255020
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.3267371676
Short name T675
Test name
Test status
Simulation time 38221304 ps
CPU time 1.86 seconds
Started Dec 31 12:54:49 PM PST 23
Finished Dec 31 12:54:55 PM PST 23
Peak memory 214096 kb
Host smart-920d244c-a6d1-417a-80da-ec8c43e04464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267371676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.3267371676
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.1887577161
Short name T22
Test name
Test status
Simulation time 42588461 ps
CPU time 0.89 seconds
Started Dec 31 12:54:30 PM PST 23
Finished Dec 31 12:54:32 PM PST 23
Peak memory 204908 kb
Host smart-300da11b-97d1-42eb-8a1a-88c5e45a7048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887577161 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.1887577161
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.748054440
Short name T960
Test name
Test status
Simulation time 18320043 ps
CPU time 1.17 seconds
Started Dec 31 12:54:45 PM PST 23
Finished Dec 31 12:54:49 PM PST 23
Peak memory 214180 kb
Host smart-3d410291-e83e-4d81-8ddf-7628615fc9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748054440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.748054440
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.1807225128
Short name T360
Test name
Test status
Simulation time 18523098 ps
CPU time 1 seconds
Started Dec 31 12:55:03 PM PST 23
Finished Dec 31 12:55:10 PM PST 23
Peak memory 205452 kb
Host smart-3dbb699d-244f-4d39-a3b5-e815b5c6e894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807225128 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.1807225128
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.2424820806
Short name T811
Test name
Test status
Simulation time 25614537 ps
CPU time 0.98 seconds
Started Dec 31 12:54:35 PM PST 23
Finished Dec 31 12:54:38 PM PST 23
Peak memory 205568 kb
Host smart-0c996b37-1df5-4002-8e2a-e3931ab1dee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424820806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.2424820806
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.3369066841
Short name T729
Test name
Test status
Simulation time 19297645 ps
CPU time 1.03 seconds
Started Dec 31 12:54:05 PM PST 23
Finished Dec 31 12:54:13 PM PST 23
Peak memory 205356 kb
Host smart-70802b4a-dc63-41a7-80f7-bbbaf8a7f124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369066841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.3369066841
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.1850229227
Short name T333
Test name
Test status
Simulation time 121530105 ps
CPU time 0.92 seconds
Started Dec 31 12:54:44 PM PST 23
Finished Dec 31 12:54:47 PM PST 23
Peak memory 204936 kb
Host smart-36072b7e-be2d-48f1-ba70-dfbb5bed1235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850229227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.1850229227
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert_test.680760927
Short name T490
Test name
Test status
Simulation time 33425178 ps
CPU time 0.83 seconds
Started Dec 31 12:52:10 PM PST 23
Finished Dec 31 12:52:25 PM PST 23
Peak memory 204320 kb
Host smart-07049f89-434d-451b-abfc-777a6573d5da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680760927 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.680760927
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.1502942972
Short name T202
Test name
Test status
Simulation time 18422696 ps
CPU time 0.84 seconds
Started Dec 31 12:52:09 PM PST 23
Finished Dec 31 12:52:24 PM PST 23
Peak memory 214300 kb
Host smart-f2248698-8f17-489c-85a5-f73a551b7f53
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502942972 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.1502942972
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.2182595277
Short name T201
Test name
Test status
Simulation time 49135495 ps
CPU time 1.04 seconds
Started Dec 31 12:52:15 PM PST 23
Finished Dec 31 12:52:30 PM PST 23
Peak memory 214536 kb
Host smart-0d40a42c-6d56-4f2b-a9e5-8f3e9c0d8f8b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182595277 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.2182595277
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.2983900464
Short name T57
Test name
Test status
Simulation time 27265200 ps
CPU time 0.79 seconds
Started Dec 31 12:52:07 PM PST 23
Finished Dec 31 12:52:20 PM PST 23
Peak memory 215508 kb
Host smart-735d7688-a390-40a2-95cc-80a904772168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983900464 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.2983900464
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.4110040248
Short name T366
Test name
Test status
Simulation time 18038324 ps
CPU time 1.06 seconds
Started Dec 31 12:52:18 PM PST 23
Finished Dec 31 12:52:32 PM PST 23
Peak memory 205624 kb
Host smart-7c7f2987-c33e-4f18-8060-8d992669143c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110040248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.4110040248
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.627298734
Short name T865
Test name
Test status
Simulation time 23093636 ps
CPU time 0.96 seconds
Started Dec 31 12:52:10 PM PST 23
Finished Dec 31 12:52:26 PM PST 23
Peak memory 214260 kb
Host smart-41d57825-7149-4c9d-ba54-28bb38c0ded8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627298734 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.627298734
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.4192862997
Short name T341
Test name
Test status
Simulation time 14058800 ps
CPU time 0.92 seconds
Started Dec 31 12:52:02 PM PST 23
Finished Dec 31 12:52:11 PM PST 23
Peak memory 204856 kb
Host smart-3c306326-de49-481f-8a8b-1ffabc3d13c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192862997 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.4192862997
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.618725901
Short name T65
Test name
Test status
Simulation time 2178380243 ps
CPU time 4.21 seconds
Started Dec 31 12:52:06 PM PST 23
Finished Dec 31 12:52:23 PM PST 23
Peak memory 233028 kb
Host smart-1d26ae5e-44d9-4cb1-938a-21ea4102116a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618725901 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.618725901
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.3798151849
Short name T756
Test name
Test status
Simulation time 18628526 ps
CPU time 0.87 seconds
Started Dec 31 12:52:10 PM PST 23
Finished Dec 31 12:52:25 PM PST 23
Peak memory 204612 kb
Host smart-f82e28bb-8637-4546-b732-4bd55d4c0ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798151849 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.3798151849
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.3509038468
Short name T110
Test name
Test status
Simulation time 702334687 ps
CPU time 3.87 seconds
Started Dec 31 12:52:03 PM PST 23
Finished Dec 31 12:52:15 PM PST 23
Peak memory 205564 kb
Host smart-f217896b-ab8b-4865-8569-0681f1370580
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509038468 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.3509038468
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.1423637786
Short name T731
Test name
Test status
Simulation time 40351742760 ps
CPU time 967.9 seconds
Started Dec 31 12:52:05 PM PST 23
Finished Dec 31 01:08:21 PM PST 23
Peak memory 215756 kb
Host smart-855f2565-efb2-4534-a565-fdf2d27ca143
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423637786 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.1423637786
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.1798195146
Short name T676
Test name
Test status
Simulation time 17803263 ps
CPU time 0.95 seconds
Started Dec 31 12:53:15 PM PST 23
Finished Dec 31 12:53:34 PM PST 23
Peak memory 205288 kb
Host smart-52474525-5f7d-4a94-9740-89e4f367eca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798195146 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1798195146
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.4039886910
Short name T590
Test name
Test status
Simulation time 39404530 ps
CPU time 1.23 seconds
Started Dec 31 12:53:30 PM PST 23
Finished Dec 31 12:53:44 PM PST 23
Peak memory 204700 kb
Host smart-142304af-f49b-4478-98f6-6fb9c850bd75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039886910 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.4039886910
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.836442371
Short name T122
Test name
Test status
Simulation time 17611193 ps
CPU time 0.81 seconds
Started Dec 31 12:53:15 PM PST 23
Finished Dec 31 12:53:33 PM PST 23
Peak memory 214204 kb
Host smart-6a10aeb4-61ca-4024-af61-a1e8970d3b7e
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836442371 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.836442371
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_err.4208281728
Short name T6
Test name
Test status
Simulation time 20061013 ps
CPU time 1.3 seconds
Started Dec 31 12:53:07 PM PST 23
Finished Dec 31 12:53:19 PM PST 23
Peak memory 214592 kb
Host smart-f50be697-94be-4ff6-b21a-7022ad76bbaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208281728 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.4208281728
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.978332199
Short name T294
Test name
Test status
Simulation time 34473300 ps
CPU time 0.98 seconds
Started Dec 31 12:53:30 PM PST 23
Finished Dec 31 12:53:43 PM PST 23
Peak memory 205792 kb
Host smart-4dbde853-6c3a-46a3-9d1e-044f6bfc7821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978332199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.978332199
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.1584916860
Short name T735
Test name
Test status
Simulation time 24815103 ps
CPU time 0.88 seconds
Started Dec 31 12:53:11 PM PST 23
Finished Dec 31 12:53:23 PM PST 23
Peak memory 214196 kb
Host smart-d9e769f3-7cfc-4507-80d9-9136b3933890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584916860 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.1584916860
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.881338451
Short name T471
Test name
Test status
Simulation time 21938977 ps
CPU time 0.86 seconds
Started Dec 31 12:53:25 PM PST 23
Finished Dec 31 12:53:39 PM PST 23
Peak memory 204576 kb
Host smart-76d60f0d-78fc-4b1f-badf-d356e9abc329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881338451 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.881338451
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.4221465736
Short name T113
Test name
Test status
Simulation time 1070995661 ps
CPU time 3 seconds
Started Dec 31 12:53:25 PM PST 23
Finished Dec 31 12:53:40 PM PST 23
Peak memory 205852 kb
Host smart-1e1e460c-a1dc-4525-b276-fc0961d76fc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221465736 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.4221465736
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2997639070
Short name T753
Test name
Test status
Simulation time 83386774756 ps
CPU time 1804.31 seconds
Started Dec 31 12:53:40 PM PST 23
Finished Dec 31 01:23:56 PM PST 23
Peak memory 220008 kb
Host smart-7fc9e8a7-4bf7-4425-9ffe-bdeeb95b517d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997639070 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.2997639070
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.3524156230
Short name T352
Test name
Test status
Simulation time 75215062 ps
CPU time 0.9 seconds
Started Dec 31 12:53:32 PM PST 23
Finished Dec 31 12:53:45 PM PST 23
Peak memory 205080 kb
Host smart-7b66d206-b6f3-4f14-9522-583ff682c16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524156230 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.3524156230
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.4285488821
Short name T671
Test name
Test status
Simulation time 28802118 ps
CPU time 0.88 seconds
Started Dec 31 12:53:11 PM PST 23
Finished Dec 31 12:53:22 PM PST 23
Peak memory 205412 kb
Host smart-8fb5ab06-e632-4bf7-8ecf-a5fcba638696
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285488821 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.4285488821
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.534224490
Short name T124
Test name
Test status
Simulation time 36723617 ps
CPU time 0.8 seconds
Started Dec 31 12:53:15 PM PST 23
Finished Dec 31 12:53:33 PM PST 23
Peak memory 214316 kb
Host smart-6fa291bd-32d8-4f72-93e2-f05e304852e8
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534224490 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.534224490
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.2434813377
Short name T870
Test name
Test status
Simulation time 217336198 ps
CPU time 1.27 seconds
Started Dec 31 12:53:29 PM PST 23
Finished Dec 31 12:53:42 PM PST 23
Peak memory 214508 kb
Host smart-07d9cf28-0ccd-43af-9502-0d0a0a3202a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434813377 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.2434813377
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.4075439527
Short name T7
Test name
Test status
Simulation time 43797784 ps
CPU time 1.11 seconds
Started Dec 31 12:53:13 PM PST 23
Finished Dec 31 12:53:31 PM PST 23
Peak memory 214480 kb
Host smart-23ca52c8-99ec-4124-a163-85f75cdb47b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075439527 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.4075439527
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.2181035061
Short name T496
Test name
Test status
Simulation time 36384776 ps
CPU time 1.2 seconds
Started Dec 31 12:53:26 PM PST 23
Finished Dec 31 12:53:40 PM PST 23
Peak memory 205620 kb
Host smart-ba0bce46-d9f0-41c1-aef4-59a1b0b6701e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181035061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.2181035061
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.1656623063
Short name T516
Test name
Test status
Simulation time 25371351 ps
CPU time 0.93 seconds
Started Dec 31 12:53:11 PM PST 23
Finished Dec 31 12:53:24 PM PST 23
Peak memory 214496 kb
Host smart-08093527-0e96-422d-9c2e-7cb5b7ecdc3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656623063 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.1656623063
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.734142039
Short name T20
Test name
Test status
Simulation time 42523552 ps
CPU time 0.85 seconds
Started Dec 31 12:53:24 PM PST 23
Finished Dec 31 12:53:38 PM PST 23
Peak memory 204716 kb
Host smart-73661e0b-87e6-4ebb-aedf-614b0054dc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734142039 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.734142039
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.2764420183
Short name T848
Test name
Test status
Simulation time 2613292118 ps
CPU time 3.55 seconds
Started Dec 31 12:53:14 PM PST 23
Finished Dec 31 12:53:34 PM PST 23
Peak memory 206004 kb
Host smart-41f670b5-4728-4f2d-a679-c213ff6de836
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764420183 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.2764420183
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.899229020
Short name T511
Test name
Test status
Simulation time 91858124150 ps
CPU time 490.56 seconds
Started Dec 31 12:53:27 PM PST 23
Finished Dec 31 01:01:50 PM PST 23
Peak memory 215024 kb
Host smart-a780219f-f5a4-4016-813d-8c2649622cb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899229020 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.899229020
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.1653602665
Short name T710
Test name
Test status
Simulation time 70691855 ps
CPU time 0.98 seconds
Started Dec 31 12:53:34 PM PST 23
Finished Dec 31 12:53:47 PM PST 23
Peak memory 205652 kb
Host smart-0333e4b0-8a55-49d6-8850-fdd635dff9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653602665 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.1653602665
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.3427582418
Short name T486
Test name
Test status
Simulation time 30117237 ps
CPU time 0.95 seconds
Started Dec 31 12:53:32 PM PST 23
Finished Dec 31 12:53:45 PM PST 23
Peak memory 205008 kb
Host smart-0a98420e-021c-4bab-b912-681a430d1202
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427582418 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.3427582418
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.1539326391
Short name T121
Test name
Test status
Simulation time 36817909 ps
CPU time 0.81 seconds
Started Dec 31 12:53:34 PM PST 23
Finished Dec 31 12:53:48 PM PST 23
Peak memory 214308 kb
Host smart-d009a0f1-af9d-4dbb-8bb8-d31c3f471513
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539326391 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.1539326391
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.4200717964
Short name T958
Test name
Test status
Simulation time 43711348 ps
CPU time 1.01 seconds
Started Dec 31 12:53:36 PM PST 23
Finished Dec 31 12:53:50 PM PST 23
Peak memory 214440 kb
Host smart-e7effdfa-17ae-4972-ae72-65e90b1916d7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200717964 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.4200717964
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.4261332536
Short name T651
Test name
Test status
Simulation time 33158108 ps
CPU time 0.97 seconds
Started Dec 31 12:53:45 PM PST 23
Finished Dec 31 12:53:58 PM PST 23
Peak memory 221724 kb
Host smart-8a835606-cc8a-479c-ac68-a1839ee9d193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261332536 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.4261332536
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.1010339961
Short name T538
Test name
Test status
Simulation time 18435259 ps
CPU time 1.12 seconds
Started Dec 31 12:53:21 PM PST 23
Finished Dec 31 12:53:36 PM PST 23
Peak memory 205644 kb
Host smart-8223be29-e40b-4af8-8888-9da3c3601b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010339961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.1010339961
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.3730195478
Short name T98
Test name
Test status
Simulation time 32752694 ps
CPU time 0.87 seconds
Started Dec 31 12:53:28 PM PST 23
Finished Dec 31 12:53:41 PM PST 23
Peak memory 214464 kb
Host smart-a3d56ff5-6913-4794-87f5-82c0a6a13b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730195478 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.3730195478
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.641233428
Short name T69
Test name
Test status
Simulation time 20411826 ps
CPU time 0.85 seconds
Started Dec 31 12:53:25 PM PST 23
Finished Dec 31 12:53:39 PM PST 23
Peak memory 204824 kb
Host smart-209868f1-0a79-47a7-85cd-971fcc76754e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641233428 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.641233428
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.2452580796
Short name T827
Test name
Test status
Simulation time 120363181 ps
CPU time 2.89 seconds
Started Dec 31 12:53:40 PM PST 23
Finished Dec 31 12:53:55 PM PST 23
Peak memory 205712 kb
Host smart-dcc2064a-bd19-4bdb-b111-5639c3b04ff1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452580796 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.2452580796
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.1927026798
Short name T738
Test name
Test status
Simulation time 46160055317 ps
CPU time 495.37 seconds
Started Dec 31 12:53:40 PM PST 23
Finished Dec 31 01:02:08 PM PST 23
Peak memory 215352 kb
Host smart-a1aa8d8e-8f3a-404a-82c2-6e0fb61921da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927026798 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.1927026798
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.365899589
Short name T112
Test name
Test status
Simulation time 22179486 ps
CPU time 1.05 seconds
Started Dec 31 12:53:28 PM PST 23
Finished Dec 31 12:53:41 PM PST 23
Peak memory 205248 kb
Host smart-cedc7c3b-23ac-4429-9bb3-cb7d7cd4d28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365899589 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.365899589
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.884073162
Short name T565
Test name
Test status
Simulation time 37169822 ps
CPU time 0.9 seconds
Started Dec 31 12:53:51 PM PST 23
Finished Dec 31 12:54:04 PM PST 23
Peak memory 204508 kb
Host smart-dda95fb5-db22-40ce-9773-3f7c49907bfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884073162 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.884073162
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.415753840
Short name T883
Test name
Test status
Simulation time 98944743 ps
CPU time 0.99 seconds
Started Dec 31 12:53:17 PM PST 23
Finished Dec 31 12:53:35 PM PST 23
Peak memory 214508 kb
Host smart-fcbbff26-22e2-408e-b293-33f87152d874
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415753840 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_di
sable_auto_req_mode.415753840
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.3676140156
Short name T858
Test name
Test status
Simulation time 35693315 ps
CPU time 0.94 seconds
Started Dec 31 12:53:39 PM PST 23
Finished Dec 31 12:53:52 PM PST 23
Peak memory 221560 kb
Host smart-bfa57ed5-5a49-4802-8577-5687b3a5e341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676140156 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.3676140156
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.989301393
Short name T588
Test name
Test status
Simulation time 13727891 ps
CPU time 1 seconds
Started Dec 31 12:53:26 PM PST 23
Finished Dec 31 12:53:40 PM PST 23
Peak memory 205168 kb
Host smart-51f5bb85-e860-438e-a878-b169c8e443c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989301393 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.989301393
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.4182058006
Short name T109
Test name
Test status
Simulation time 26452215 ps
CPU time 0.82 seconds
Started Dec 31 12:53:37 PM PST 23
Finished Dec 31 12:53:51 PM PST 23
Peak memory 214368 kb
Host smart-638c112b-0187-454b-8f35-243f61937a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182058006 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.4182058006
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.1940514918
Short name T641
Test name
Test status
Simulation time 28176345 ps
CPU time 0.89 seconds
Started Dec 31 12:53:43 PM PST 23
Finished Dec 31 12:53:56 PM PST 23
Peak memory 204732 kb
Host smart-f2a08eb1-521d-497e-b4d1-8ad01a0edf0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940514918 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.1940514918
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.3492183592
Short name T543
Test name
Test status
Simulation time 55693296 ps
CPU time 1.58 seconds
Started Dec 31 12:53:35 PM PST 23
Finished Dec 31 12:53:49 PM PST 23
Peak memory 205660 kb
Host smart-31f14a27-58a5-4c75-8389-7c87d485deaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492183592 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3492183592
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.2697934322
Short name T971
Test name
Test status
Simulation time 58942443748 ps
CPU time 656.43 seconds
Started Dec 31 12:53:37 PM PST 23
Finished Dec 31 01:04:46 PM PST 23
Peak memory 215380 kb
Host smart-a572dd3e-6c81-48f4-8ceb-b055534db2ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697934322 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.2697934322
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.2659600894
Short name T752
Test name
Test status
Simulation time 112408013 ps
CPU time 0.94 seconds
Started Dec 31 12:53:31 PM PST 23
Finished Dec 31 12:53:44 PM PST 23
Peak memory 205056 kb
Host smart-a9f98d46-1f70-4485-b0cb-da031640eec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659600894 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.2659600894
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.215607646
Short name T867
Test name
Test status
Simulation time 14097741 ps
CPU time 0.85 seconds
Started Dec 31 12:53:43 PM PST 23
Finished Dec 31 12:53:57 PM PST 23
Peak memory 204540 kb
Host smart-518cddea-2d00-459d-98e0-3f0341170096
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215607646 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.215607646
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.1403951691
Short name T193
Test name
Test status
Simulation time 96817961 ps
CPU time 1.09 seconds
Started Dec 31 12:53:46 PM PST 23
Finished Dec 31 12:54:00 PM PST 23
Peak memory 214512 kb
Host smart-96f518c2-a84c-4f9e-9c4b-0786e2c282fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403951691 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.1403951691
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.451237171
Short name T709
Test name
Test status
Simulation time 32494609 ps
CPU time 1.38 seconds
Started Dec 31 12:53:45 PM PST 23
Finished Dec 31 12:53:59 PM PST 23
Peak memory 227568 kb
Host smart-29a56bfc-ade9-433d-b434-3e9b95ff3836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451237171 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.451237171
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.3819534622
Short name T359
Test name
Test status
Simulation time 31424061 ps
CPU time 0.98 seconds
Started Dec 31 12:53:51 PM PST 23
Finished Dec 31 12:54:04 PM PST 23
Peak memory 205128 kb
Host smart-b8edbe0b-fbf5-47b1-99a3-5909f9647d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819534622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.3819534622
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.682727785
Short name T683
Test name
Test status
Simulation time 20313036 ps
CPU time 1.15 seconds
Started Dec 31 12:53:57 PM PST 23
Finished Dec 31 12:54:08 PM PST 23
Peak memory 221840 kb
Host smart-bb510d01-0edc-4434-b65c-b1bcdffe4853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682727785 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.682727785
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.1842020947
Short name T537
Test name
Test status
Simulation time 15403891 ps
CPU time 0.92 seconds
Started Dec 31 12:53:25 PM PST 23
Finished Dec 31 12:53:39 PM PST 23
Peak memory 204768 kb
Host smart-d3af3654-2682-4a1c-ba4a-7d1276d8eb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842020947 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.1842020947
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.362130063
Short name T712
Test name
Test status
Simulation time 449623612 ps
CPU time 3.09 seconds
Started Dec 31 12:53:33 PM PST 23
Finished Dec 31 12:53:48 PM PST 23
Peak memory 205884 kb
Host smart-a41aa144-7036-4aac-b2eb-780ac3764e28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362130063 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.362130063
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.1868590072
Short name T751
Test name
Test status
Simulation time 78654124443 ps
CPU time 834.76 seconds
Started Dec 31 12:53:35 PM PST 23
Finished Dec 31 01:07:43 PM PST 23
Peak memory 215164 kb
Host smart-2062baea-0974-4747-bdec-0b438c3b6ab6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868590072 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.1868590072
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.358010149
Short name T621
Test name
Test status
Simulation time 20554558 ps
CPU time 0.95 seconds
Started Dec 31 12:53:48 PM PST 23
Finished Dec 31 12:54:02 PM PST 23
Peak memory 205144 kb
Host smart-614d8ec7-5442-4b92-96a5-4e5de3ebfc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358010149 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.358010149
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.3804322883
Short name T920
Test name
Test status
Simulation time 39293345 ps
CPU time 0.88 seconds
Started Dec 31 12:53:38 PM PST 23
Finished Dec 31 12:53:51 PM PST 23
Peak memory 204612 kb
Host smart-6a519d70-5bd4-46a2-8359-a36c586d30fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804322883 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.3804322883
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.1139129787
Short name T127
Test name
Test status
Simulation time 12746790 ps
CPU time 0.89 seconds
Started Dec 31 12:53:41 PM PST 23
Finished Dec 31 12:53:53 PM PST 23
Peak memory 214480 kb
Host smart-a78009e9-af67-4570-ab96-1efcea4daca5
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139129787 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.1139129787
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.3830930042
Short name T672
Test name
Test status
Simulation time 50187881 ps
CPU time 1.09 seconds
Started Dec 31 12:53:36 PM PST 23
Finished Dec 31 12:53:49 PM PST 23
Peak memory 214508 kb
Host smart-55325ba6-11f1-4bdb-b0d7-d21937051048
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830930042 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.3830930042
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.1029117556
Short name T259
Test name
Test status
Simulation time 18259504 ps
CPU time 1 seconds
Started Dec 31 12:53:49 PM PST 23
Finished Dec 31 12:54:02 PM PST 23
Peak memory 215844 kb
Host smart-fb68856e-4a93-455a-befa-a9c473c0c6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029117556 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.1029117556
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.3192195484
Short name T938
Test name
Test status
Simulation time 22978800 ps
CPU time 0.9 seconds
Started Dec 31 12:53:43 PM PST 23
Finished Dec 31 12:53:55 PM PST 23
Peak memory 204864 kb
Host smart-4c5021ad-1448-45ac-945a-b064dbc1e2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192195484 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.3192195484
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.1638463308
Short name T548
Test name
Test status
Simulation time 29740861 ps
CPU time 0.83 seconds
Started Dec 31 12:53:49 PM PST 23
Finished Dec 31 12:54:02 PM PST 23
Peak memory 214484 kb
Host smart-1e713b91-8e25-4404-a267-d1f672eabe8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638463308 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.1638463308
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.1797137869
Short name T529
Test name
Test status
Simulation time 20015825 ps
CPU time 0.86 seconds
Started Dec 31 12:53:45 PM PST 23
Finished Dec 31 12:53:58 PM PST 23
Peak memory 204920 kb
Host smart-2dc0b682-074f-4a12-ac09-b540e5117b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797137869 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.1797137869
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.820401773
Short name T803
Test name
Test status
Simulation time 67095776 ps
CPU time 1.72 seconds
Started Dec 31 12:53:36 PM PST 23
Finished Dec 31 12:53:51 PM PST 23
Peak memory 205800 kb
Host smart-f0d6a03c-606d-4c6b-aa24-69ab0634911b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820401773 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.820401773
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_alert.3848255864
Short name T275
Test name
Test status
Simulation time 18472436 ps
CPU time 0.92 seconds
Started Dec 31 12:53:38 PM PST 23
Finished Dec 31 12:53:51 PM PST 23
Peak memory 205092 kb
Host smart-a1b18d1c-00d8-4675-ae07-c493c8f5fd2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848255864 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.3848255864
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.4171063955
Short name T19
Test name
Test status
Simulation time 126087025 ps
CPU time 0.88 seconds
Started Dec 31 12:53:42 PM PST 23
Finished Dec 31 12:53:55 PM PST 23
Peak memory 204624 kb
Host smart-903f3be0-442c-4b33-9707-c07edfaad714
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171063955 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.4171063955
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.3794049483
Short name T733
Test name
Test status
Simulation time 19552940 ps
CPU time 0.88 seconds
Started Dec 31 12:53:40 PM PST 23
Finished Dec 31 12:53:53 PM PST 23
Peak memory 214208 kb
Host smart-8d6f5482-4a91-4182-81d5-f6da7664dc52
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794049483 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.3794049483
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.3440688207
Short name T196
Test name
Test status
Simulation time 38475133 ps
CPU time 1.08 seconds
Started Dec 31 12:54:00 PM PST 23
Finished Dec 31 12:54:11 PM PST 23
Peak memory 214516 kb
Host smart-08d1d39b-5af6-4aa1-acc9-f0c6c5aba3bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440688207 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.3440688207
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.3658819144
Short name T114
Test name
Test status
Simulation time 31446543 ps
CPU time 1.39 seconds
Started Dec 31 12:53:52 PM PST 23
Finished Dec 31 12:54:04 PM PST 23
Peak memory 214728 kb
Host smart-2187e1b6-d4f8-42e1-8ecc-c4ece507189c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658819144 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.3658819144
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.1764844022
Short name T584
Test name
Test status
Simulation time 37891559 ps
CPU time 0.94 seconds
Started Dec 31 12:53:34 PM PST 23
Finished Dec 31 12:53:47 PM PST 23
Peak memory 204940 kb
Host smart-1d55f01e-5ebf-4f72-8a85-e3e93871ebf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764844022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.1764844022
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.1733473625
Short name T498
Test name
Test status
Simulation time 22664977 ps
CPU time 0.96 seconds
Started Dec 31 12:53:59 PM PST 23
Finished Dec 31 12:54:10 PM PST 23
Peak memory 214464 kb
Host smart-36c2ab99-7201-405a-a28c-44636e533147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733473625 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.1733473625
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.899093832
Short name T915
Test name
Test status
Simulation time 14910619 ps
CPU time 0.86 seconds
Started Dec 31 12:53:57 PM PST 23
Finished Dec 31 12:54:08 PM PST 23
Peak memory 204804 kb
Host smart-eda29a2b-59ab-46ef-b921-b8ea662941bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899093832 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.899093832
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.3100519505
Short name T660
Test name
Test status
Simulation time 122627813 ps
CPU time 1.78 seconds
Started Dec 31 12:53:46 PM PST 23
Finished Dec 31 12:54:00 PM PST 23
Peak memory 205812 kb
Host smart-c4ffbc23-0bf6-4643-b18e-b94de5628779
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100519505 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.3100519505
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.1766037726
Short name T895
Test name
Test status
Simulation time 497098545294 ps
CPU time 1110.63 seconds
Started Dec 31 12:53:48 PM PST 23
Finished Dec 31 01:12:31 PM PST 23
Peak memory 217760 kb
Host smart-d254d352-4a55-4db5-9f96-e52be552582a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766037726 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.1766037726
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.4224075520
Short name T353
Test name
Test status
Simulation time 32527356 ps
CPU time 0.95 seconds
Started Dec 31 12:53:51 PM PST 23
Finished Dec 31 12:54:03 PM PST 23
Peak memory 205412 kb
Host smart-85335697-3e31-4011-846d-be9cdbacc311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224075520 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.4224075520
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.3249619149
Short name T642
Test name
Test status
Simulation time 95159007 ps
CPU time 0.92 seconds
Started Dec 31 12:54:20 PM PST 23
Finished Dec 31 12:54:22 PM PST 23
Peak memory 204688 kb
Host smart-731a2cb3-bd02-4d36-960f-9d7ac319757d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249619149 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.3249619149
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.422095822
Short name T764
Test name
Test status
Simulation time 22928714 ps
CPU time 0.88 seconds
Started Dec 31 12:53:49 PM PST 23
Finished Dec 31 12:54:02 PM PST 23
Peak memory 214284 kb
Host smart-748bc966-fe06-4038-a5c1-782fafcfda14
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422095822 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.422095822
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.708214446
Short name T71
Test name
Test status
Simulation time 65062081 ps
CPU time 0.93 seconds
Started Dec 31 12:54:02 PM PST 23
Finished Dec 31 12:54:12 PM PST 23
Peak memory 206336 kb
Host smart-698c8491-8e6c-4374-adce-f18faf1d7ce3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708214446 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_di
sable_auto_req_mode.708214446
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.2722877761
Short name T804
Test name
Test status
Simulation time 36743580 ps
CPU time 0.83 seconds
Started Dec 31 12:54:24 PM PST 23
Finished Dec 31 12:54:26 PM PST 23
Peak memory 215616 kb
Host smart-8ca16102-b216-4b45-a09b-1e5cd18fae4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722877761 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.2722877761
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.1489723765
Short name T686
Test name
Test status
Simulation time 22599214 ps
CPU time 1.09 seconds
Started Dec 31 12:53:41 PM PST 23
Finished Dec 31 12:53:54 PM PST 23
Peak memory 214224 kb
Host smart-62ec8f31-45df-4fb6-9bbb-a8d25dd1cfd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489723765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1489723765
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.521092431
Short name T964
Test name
Test status
Simulation time 23367865 ps
CPU time 0.9 seconds
Started Dec 31 12:53:58 PM PST 23
Finished Dec 31 12:54:09 PM PST 23
Peak memory 214248 kb
Host smart-135c94a9-a5e7-4f8f-b653-2a29eefe0048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521092431 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.521092431
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.3492645904
Short name T690
Test name
Test status
Simulation time 20992581 ps
CPU time 0.86 seconds
Started Dec 31 12:54:18 PM PST 23
Finished Dec 31 12:54:25 PM PST 23
Peak memory 204984 kb
Host smart-1fb046bf-e00e-421c-b2fe-e3fb1243b536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492645904 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.3492645904
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.1118706052
Short name T744
Test name
Test status
Simulation time 169365091 ps
CPU time 2.97 seconds
Started Dec 31 12:53:48 PM PST 23
Finished Dec 31 12:54:03 PM PST 23
Peak memory 205632 kb
Host smart-ec88f474-0d89-405d-873a-e3795937c662
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118706052 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.1118706052
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.4075767352
Short name T646
Test name
Test status
Simulation time 47599274518 ps
CPU time 1069.71 seconds
Started Dec 31 12:54:17 PM PST 23
Finished Dec 31 01:12:09 PM PST 23
Peak memory 215448 kb
Host smart-1eeb676b-3fd9-4b54-91ca-5e4c5fa778ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075767352 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.4075767352
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.1856852689
Short name T687
Test name
Test status
Simulation time 34918268 ps
CPU time 0.98 seconds
Started Dec 31 12:53:43 PM PST 23
Finished Dec 31 12:53:57 PM PST 23
Peak memory 205872 kb
Host smart-19df72fd-2b0a-4776-82a3-56ca2190b0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856852689 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.1856852689
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.3508972816
Short name T941
Test name
Test status
Simulation time 137793173 ps
CPU time 0.8 seconds
Started Dec 31 12:54:00 PM PST 23
Finished Dec 31 12:54:13 PM PST 23
Peak memory 202928 kb
Host smart-95e43946-fbb8-4300-8ece-3128aa9ebd65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508972816 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.3508972816
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.1369204007
Short name T224
Test name
Test status
Simulation time 18959460 ps
CPU time 0.86 seconds
Started Dec 31 12:53:59 PM PST 23
Finished Dec 31 12:54:09 PM PST 23
Peak memory 214216 kb
Host smart-da6e6d8c-f77c-45ea-85a5-5d1995aab67e
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369204007 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.1369204007
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.969305519
Short name T786
Test name
Test status
Simulation time 111798771 ps
CPU time 1.09 seconds
Started Dec 31 12:53:33 PM PST 23
Finished Dec 31 12:53:46 PM PST 23
Peak memory 214424 kb
Host smart-91b5ac37-ee03-41df-8360-f42a4bf3dff3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969305519 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_di
sable_auto_req_mode.969305519
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.1414466588
Short name T188
Test name
Test status
Simulation time 58341767 ps
CPU time 1.08 seconds
Started Dec 31 12:53:31 PM PST 23
Finished Dec 31 12:53:44 PM PST 23
Peak memory 229980 kb
Host smart-e4556c2b-fd60-4017-b916-672cb43ae033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414466588 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.1414466588
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.2812826857
Short name T21
Test name
Test status
Simulation time 112573431 ps
CPU time 0.94 seconds
Started Dec 31 12:53:48 PM PST 23
Finished Dec 31 12:54:01 PM PST 23
Peak memory 205020 kb
Host smart-a193bcd5-42f2-4ef5-aa35-d639350694b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812826857 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.2812826857
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.4038980893
Short name T482
Test name
Test status
Simulation time 45548589 ps
CPU time 0.82 seconds
Started Dec 31 12:53:41 PM PST 23
Finished Dec 31 12:53:54 PM PST 23
Peak memory 214100 kb
Host smart-728c077a-36f1-4066-9af5-a223e4d8d157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038980893 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.4038980893
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.1560354328
Short name T68
Test name
Test status
Simulation time 100905397 ps
CPU time 0.88 seconds
Started Dec 31 12:53:45 PM PST 23
Finished Dec 31 12:53:58 PM PST 23
Peak memory 204656 kb
Host smart-f709b763-985d-48d3-80fc-4175ad4ee919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560354328 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.1560354328
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.3027787720
Short name T754
Test name
Test status
Simulation time 259173840 ps
CPU time 0.88 seconds
Started Dec 31 12:53:55 PM PST 23
Finished Dec 31 12:54:06 PM PST 23
Peak memory 204396 kb
Host smart-1f6a6601-74ce-451f-962c-e25065277b01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027787720 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.3027787720
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.409700633
Short name T732
Test name
Test status
Simulation time 90613758657 ps
CPU time 2291.1 seconds
Started Dec 31 12:53:42 PM PST 23
Finished Dec 31 01:32:06 PM PST 23
Peak memory 225812 kb
Host smart-7467b45b-dc16-4595-9569-eed2f4f86719
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409700633 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.409700633
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.4155857679
Short name T92
Test name
Test status
Simulation time 62152008 ps
CPU time 0.95 seconds
Started Dec 31 12:53:32 PM PST 23
Finished Dec 31 12:53:45 PM PST 23
Peak memory 205032 kb
Host smart-c89d30a6-ac9b-4707-8d90-1f886d4be158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155857679 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.4155857679
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.2920234075
Short name T682
Test name
Test status
Simulation time 12217673 ps
CPU time 0.82 seconds
Started Dec 31 12:53:28 PM PST 23
Finished Dec 31 12:53:40 PM PST 23
Peak memory 204432 kb
Host smart-9c6b3dc0-ba51-4405-8e77-7332d5cf35bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920234075 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.2920234075
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.135354006
Short name T930
Test name
Test status
Simulation time 296149277 ps
CPU time 0.96 seconds
Started Dec 31 12:53:52 PM PST 23
Finished Dec 31 12:54:04 PM PST 23
Peak memory 214484 kb
Host smart-55528010-6ee2-4fb9-8127-a95bade9ddeb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135354006 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_di
sable_auto_req_mode.135354006
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.283466672
Short name T81
Test name
Test status
Simulation time 29167710 ps
CPU time 1.18 seconds
Started Dec 31 12:53:46 PM PST 23
Finished Dec 31 12:54:00 PM PST 23
Peak memory 216908 kb
Host smart-bbc07fca-3356-4b56-9d92-f7d01e760e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283466672 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.283466672
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.678949156
Short name T916
Test name
Test status
Simulation time 12327249 ps
CPU time 0.92 seconds
Started Dec 31 12:53:47 PM PST 23
Finished Dec 31 12:54:01 PM PST 23
Peak memory 205152 kb
Host smart-7f0f9af4-7531-48a5-b255-e1ce3a83cef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678949156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.678949156
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.2139832514
Short name T103
Test name
Test status
Simulation time 23127903 ps
CPU time 0.91 seconds
Started Dec 31 12:53:31 PM PST 23
Finished Dec 31 12:53:44 PM PST 23
Peak memory 214500 kb
Host smart-453ad5db-e18a-41eb-a62c-e5e6008f049c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139832514 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.2139832514
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.2610009373
Short name T467
Test name
Test status
Simulation time 39502876 ps
CPU time 0.83 seconds
Started Dec 31 12:53:35 PM PST 23
Finished Dec 31 12:53:48 PM PST 23
Peak memory 204856 kb
Host smart-2cf560a3-23fc-4908-8b24-b36f92cb3654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610009373 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.2610009373
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.28925620
Short name T63
Test name
Test status
Simulation time 515039019 ps
CPU time 3.07 seconds
Started Dec 31 12:53:42 PM PST 23
Finished Dec 31 12:53:57 PM PST 23
Peak memory 206024 kb
Host smart-fd26856a-5b08-451c-a95a-344242332873
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28925620 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.28925620
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.3411775203
Short name T320
Test name
Test status
Simulation time 346901681798 ps
CPU time 2152.74 seconds
Started Dec 31 12:53:42 PM PST 23
Finished Dec 31 01:29:47 PM PST 23
Peak memory 219852 kb
Host smart-da14dd8b-4ba7-489a-8b0f-a1c41b05a5ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411775203 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.3411775203
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.3556383400
Short name T347
Test name
Test status
Simulation time 61288492 ps
CPU time 1.02 seconds
Started Dec 31 12:52:09 PM PST 23
Finished Dec 31 12:52:25 PM PST 23
Peak memory 205116 kb
Host smart-e84dae9e-4c8c-4c17-989d-afe37c22615c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556383400 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.3556383400
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.1836165780
Short name T826
Test name
Test status
Simulation time 11451767 ps
CPU time 0.83 seconds
Started Dec 31 12:52:18 PM PST 23
Finished Dec 31 12:52:32 PM PST 23
Peak memory 204120 kb
Host smart-09429043-68db-42be-885b-5c0e22f97621
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836165780 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.1836165780
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.2789087705
Short name T774
Test name
Test status
Simulation time 18269080 ps
CPU time 0.82 seconds
Started Dec 31 12:52:10 PM PST 23
Finished Dec 31 12:52:26 PM PST 23
Peak memory 214284 kb
Host smart-77240ec2-3afa-4433-be04-931eb7654a3c
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789087705 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.2789087705
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.336760097
Short name T842
Test name
Test status
Simulation time 24687948 ps
CPU time 0.96 seconds
Started Dec 31 12:52:10 PM PST 23
Finished Dec 31 12:52:26 PM PST 23
Peak memory 214508 kb
Host smart-df57897e-4e93-46d3-9c03-b0b4fd052b87
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336760097 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_dis
able_auto_req_mode.336760097
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.1628671552
Short name T260
Test name
Test status
Simulation time 24358355 ps
CPU time 0.93 seconds
Started Dec 31 12:52:12 PM PST 23
Finished Dec 31 12:52:28 PM PST 23
Peak memory 214432 kb
Host smart-81f923d8-c071-4d16-82b0-3e898089b2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628671552 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.1628671552
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.1382231560
Short name T970
Test name
Test status
Simulation time 65774991 ps
CPU time 1.31 seconds
Started Dec 31 12:52:12 PM PST 23
Finished Dec 31 12:52:28 PM PST 23
Peak memory 205664 kb
Host smart-0b1e8d22-b346-42c0-9d9f-026149a53a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382231560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1382231560
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_regwen.281270504
Short name T279
Test name
Test status
Simulation time 17038493 ps
CPU time 0.86 seconds
Started Dec 31 12:52:09 PM PST 23
Finished Dec 31 12:52:24 PM PST 23
Peak memory 204800 kb
Host smart-0f79580c-a8d2-4ad3-8879-8ea8a03c5796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281270504 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.281270504
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.2254622172
Short name T64
Test name
Test status
Simulation time 1564928843 ps
CPU time 5.99 seconds
Started Dec 31 12:52:13 PM PST 23
Finished Dec 31 12:52:34 PM PST 23
Peak memory 232584 kb
Host smart-166f63e2-d5db-4a3d-b879-64fa40235cca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254622172 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.2254622172
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.3419942576
Short name T840
Test name
Test status
Simulation time 15068742 ps
CPU time 0.92 seconds
Started Dec 31 12:52:07 PM PST 23
Finished Dec 31 12:52:22 PM PST 23
Peak memory 204860 kb
Host smart-10e69a50-832d-43f3-8f00-41eeb53829da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419942576 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3419942576
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.678065368
Short name T852
Test name
Test status
Simulation time 284923136 ps
CPU time 1.6 seconds
Started Dec 31 12:52:10 PM PST 23
Finished Dec 31 12:52:26 PM PST 23
Peak memory 205828 kb
Host smart-c3051247-490d-430d-8c19-4e32aa1f7a04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678065368 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.678065368
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.4225397114
Short name T708
Test name
Test status
Simulation time 34714264408 ps
CPU time 435.82 seconds
Started Dec 31 12:52:09 PM PST 23
Finished Dec 31 12:59:40 PM PST 23
Peak memory 215216 kb
Host smart-04db129a-b661-4a6c-92b0-31e028cb8947
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225397114 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.4225397114
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.1286396095
Short name T355
Test name
Test status
Simulation time 24076761 ps
CPU time 0.97 seconds
Started Dec 31 12:53:41 PM PST 23
Finished Dec 31 12:53:54 PM PST 23
Peak memory 205188 kb
Host smart-3d0c1464-b8f5-419a-bacc-18b78451131a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286396095 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.1286396095
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.3650847532
Short name T593
Test name
Test status
Simulation time 40658840 ps
CPU time 0.82 seconds
Started Dec 31 12:54:01 PM PST 23
Finished Dec 31 12:54:11 PM PST 23
Peak memory 204360 kb
Host smart-34599bf7-f51c-484c-9a10-0c422fb57825
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650847532 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3650847532
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.351295754
Short name T269
Test name
Test status
Simulation time 42281563 ps
CPU time 0.87 seconds
Started Dec 31 12:53:59 PM PST 23
Finished Dec 31 12:54:09 PM PST 23
Peak memory 214224 kb
Host smart-87f94d6d-d4ac-41b4-a8a5-cf05feaa0454
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351295754 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.351295754
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.843389063
Short name T704
Test name
Test status
Simulation time 76398734 ps
CPU time 0.99 seconds
Started Dec 31 12:53:45 PM PST 23
Finished Dec 31 12:53:59 PM PST 23
Peak memory 214444 kb
Host smart-5d51f2bf-1945-41e3-bc46-6843b7f5e8b8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843389063 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_di
sable_auto_req_mode.843389063
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.799118675
Short name T174
Test name
Test status
Simulation time 22749735 ps
CPU time 1.13 seconds
Started Dec 31 12:53:35 PM PST 23
Finished Dec 31 12:53:49 PM PST 23
Peak memory 214504 kb
Host smart-7c6a9619-10db-4fcc-8bad-7cfa091a5496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799118675 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.799118675
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.3900003282
Short name T10
Test name
Test status
Simulation time 73848930 ps
CPU time 0.95 seconds
Started Dec 31 12:53:41 PM PST 23
Finished Dec 31 12:53:53 PM PST 23
Peak memory 214032 kb
Host smart-12a68a6f-99a7-4d1d-9227-e64b0b7908ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900003282 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.3900003282
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.78744626
Short name T889
Test name
Test status
Simulation time 38630012 ps
CPU time 0.9 seconds
Started Dec 31 12:53:37 PM PST 23
Finished Dec 31 12:53:51 PM PST 23
Peak memory 214464 kb
Host smart-fb80b947-76f1-4448-bf87-737ba374d74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78744626 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.78744626
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.3255850953
Short name T564
Test name
Test status
Simulation time 28693437 ps
CPU time 0.86 seconds
Started Dec 31 12:53:42 PM PST 23
Finished Dec 31 12:53:55 PM PST 23
Peak memory 204656 kb
Host smart-c03aed2c-18d3-4087-a1d2-164362da5f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255850953 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.3255850953
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.3594942658
Short name T921
Test name
Test status
Simulation time 267441529 ps
CPU time 3.44 seconds
Started Dec 31 12:53:41 PM PST 23
Finished Dec 31 12:53:57 PM PST 23
Peak memory 206020 kb
Host smart-13a2ad07-bd5b-4854-a34c-576ae8776f00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594942658 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.3594942658
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.2343755957
Short name T684
Test name
Test status
Simulation time 35326392784 ps
CPU time 888.91 seconds
Started Dec 31 12:53:35 PM PST 23
Finished Dec 31 01:08:36 PM PST 23
Peak memory 217796 kb
Host smart-ba7f1723-d6bf-45f9-8eba-3727a931f958
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343755957 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.2343755957
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.1389910077
Short name T18
Test name
Test status
Simulation time 26731312 ps
CPU time 0.92 seconds
Started Dec 31 12:53:45 PM PST 23
Finished Dec 31 12:53:58 PM PST 23
Peak memory 205180 kb
Host smart-15c12948-a9b5-47c5-8bd9-d45a99214478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389910077 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.1389910077
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.2433155251
Short name T770
Test name
Test status
Simulation time 17515771 ps
CPU time 0.78 seconds
Started Dec 31 12:53:36 PM PST 23
Finished Dec 31 12:53:49 PM PST 23
Peak memory 204092 kb
Host smart-89eb8d3b-aa6e-4be6-b441-10cd26a65066
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433155251 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.2433155251
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.917453739
Short name T187
Test name
Test status
Simulation time 23174907 ps
CPU time 1 seconds
Started Dec 31 12:53:40 PM PST 23
Finished Dec 31 12:53:53 PM PST 23
Peak memory 214572 kb
Host smart-5b6dd7f7-f366-4e05-b0a0-93c0cc7506b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917453739 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_di
sable_auto_req_mode.917453739
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.644657917
Short name T205
Test name
Test status
Simulation time 31623437 ps
CPU time 1.34 seconds
Started Dec 31 12:53:37 PM PST 23
Finished Dec 31 12:53:51 PM PST 23
Peak memory 221820 kb
Host smart-c387f2ef-b9d2-4697-bcd2-9b702f8b1bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644657917 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.644657917
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.1671946282
Short name T701
Test name
Test status
Simulation time 16975275 ps
CPU time 0.95 seconds
Started Dec 31 12:53:54 PM PST 23
Finished Dec 31 12:54:06 PM PST 23
Peak memory 205048 kb
Host smart-2bc3a44d-445a-47cb-a55c-45fba8ff40c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671946282 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.1671946282
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.1157114690
Short name T104
Test name
Test status
Simulation time 31598539 ps
CPU time 0.87 seconds
Started Dec 31 12:53:37 PM PST 23
Finished Dec 31 12:53:51 PM PST 23
Peak memory 214316 kb
Host smart-47229f86-35e8-4da1-9de0-a81ecfe7894b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157114690 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.1157114690
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.3285447685
Short name T520
Test name
Test status
Simulation time 55936341 ps
CPU time 0.82 seconds
Started Dec 31 12:54:03 PM PST 23
Finished Dec 31 12:54:12 PM PST 23
Peak memory 204760 kb
Host smart-58492798-b62b-4491-ace3-8331cfa2e38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285447685 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.3285447685
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.1133088423
Short name T592
Test name
Test status
Simulation time 344214872 ps
CPU time 2.28 seconds
Started Dec 31 12:53:46 PM PST 23
Finished Dec 31 12:54:05 PM PST 23
Peak memory 205864 kb
Host smart-5b204747-d540-4c40-b2f0-879edea3e2d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133088423 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.1133088423
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.1871854689
Short name T833
Test name
Test status
Simulation time 154900505761 ps
CPU time 1955.3 seconds
Started Dec 31 12:53:43 PM PST 23
Finished Dec 31 01:26:30 PM PST 23
Peak memory 223268 kb
Host smart-b458a1b2-8322-4424-8d17-cad14d6972c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871854689 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.1871854689
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.3318799314
Short name T351
Test name
Test status
Simulation time 18846833 ps
CPU time 0.96 seconds
Started Dec 31 12:53:22 PM PST 23
Finished Dec 31 12:53:37 PM PST 23
Peak memory 205192 kb
Host smart-681155a1-318e-4831-afaa-b34a7a6cf15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318799314 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.3318799314
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.4212468964
Short name T633
Test name
Test status
Simulation time 14766616 ps
CPU time 0.88 seconds
Started Dec 31 12:53:57 PM PST 23
Finished Dec 31 12:54:08 PM PST 23
Peak memory 204560 kb
Host smart-f9c47c96-0ec3-4a55-a5aa-a01644b5c809
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212468964 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.4212468964
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.4193312139
Short name T876
Test name
Test status
Simulation time 16098135 ps
CPU time 0.86 seconds
Started Dec 31 12:54:13 PM PST 23
Finished Dec 31 12:54:17 PM PST 23
Peak memory 214492 kb
Host smart-ff8ead64-369f-40be-b80c-66b99051d673
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193312139 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.4193312139
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.3158078659
Short name T70
Test name
Test status
Simulation time 88556471 ps
CPU time 0.98 seconds
Started Dec 31 12:53:55 PM PST 23
Finished Dec 31 12:54:06 PM PST 23
Peak memory 214448 kb
Host smart-e25f4dc4-4073-4a53-93f9-29fa70f2f9a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158078659 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.3158078659
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.1339722661
Short name T268
Test name
Test status
Simulation time 20097005 ps
CPU time 1.06 seconds
Started Dec 31 12:53:33 PM PST 23
Finished Dec 31 12:53:46 PM PST 23
Peak memory 214788 kb
Host smart-3c36ab44-a179-49f4-a8f9-5d75482e433b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339722661 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.1339722661
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_intr.764362242
Short name T101
Test name
Test status
Simulation time 19777759 ps
CPU time 1.09 seconds
Started Dec 31 12:53:44 PM PST 23
Finished Dec 31 12:53:57 PM PST 23
Peak memory 225616 kb
Host smart-42c99187-02ad-43e1-96e9-d5f3f4d047e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764362242 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.764362242
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.3677318492
Short name T517
Test name
Test status
Simulation time 25348112 ps
CPU time 0.91 seconds
Started Dec 31 12:53:32 PM PST 23
Finished Dec 31 12:53:45 PM PST 23
Peak memory 204840 kb
Host smart-e7c7445f-13cc-4f85-b8ac-db9f1123c1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677318492 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.3677318492
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.2747657097
Short name T495
Test name
Test status
Simulation time 354448341 ps
CPU time 2.52 seconds
Started Dec 31 12:53:45 PM PST 23
Finished Dec 31 12:53:59 PM PST 23
Peak memory 205484 kb
Host smart-506bbd5b-5913-4a7b-a4d8-0cc693dc5e1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747657097 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.2747657097
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_alert.2660386540
Short name T937
Test name
Test status
Simulation time 19453374 ps
CPU time 0.95 seconds
Started Dec 31 12:53:48 PM PST 23
Finished Dec 31 12:54:02 PM PST 23
Peak memory 205164 kb
Host smart-a88a37f1-cca5-44fe-adca-76dfa51bbef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660386540 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2660386540
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.862193629
Short name T492
Test name
Test status
Simulation time 31585154 ps
CPU time 0.92 seconds
Started Dec 31 12:53:51 PM PST 23
Finished Dec 31 12:54:04 PM PST 23
Peak memory 205068 kb
Host smart-b921539c-9bda-4cdf-bde1-c977998acc9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862193629 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.862193629
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.1073185113
Short name T85
Test name
Test status
Simulation time 33361175 ps
CPU time 0.83 seconds
Started Dec 31 12:53:36 PM PST 23
Finished Dec 31 12:53:50 PM PST 23
Peak memory 214340 kb
Host smart-c561f700-ca02-4b81-9c4c-1c87e328b7e6
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073185113 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.1073185113
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_err.2701671108
Short name T782
Test name
Test status
Simulation time 27275309 ps
CPU time 0.92 seconds
Started Dec 31 12:53:33 PM PST 23
Finished Dec 31 12:53:46 PM PST 23
Peak memory 215952 kb
Host smart-aee06a11-8e84-4087-b3be-ada06af82538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701671108 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.2701671108
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.327476681
Short name T326
Test name
Test status
Simulation time 206885688 ps
CPU time 1.3 seconds
Started Dec 31 12:53:43 PM PST 23
Finished Dec 31 12:53:56 PM PST 23
Peak memory 214096 kb
Host smart-b70fcc64-8c63-4e13-86cf-acc68d410758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327476681 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.327476681
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.2684382943
Short name T829
Test name
Test status
Simulation time 48035395 ps
CPU time 0.82 seconds
Started Dec 31 12:53:58 PM PST 23
Finished Dec 31 12:54:08 PM PST 23
Peak memory 214072 kb
Host smart-eced1b25-ef90-4413-8eb3-46d68f6763ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684382943 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.2684382943
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.3693528703
Short name T594
Test name
Test status
Simulation time 24967126 ps
CPU time 0.86 seconds
Started Dec 31 12:53:35 PM PST 23
Finished Dec 31 12:53:48 PM PST 23
Peak memory 204580 kb
Host smart-303b5411-e474-412f-b451-ab163f8594aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693528703 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.3693528703
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.3811635054
Short name T748
Test name
Test status
Simulation time 145110453 ps
CPU time 3.56 seconds
Started Dec 31 12:53:34 PM PST 23
Finished Dec 31 12:53:50 PM PST 23
Peak memory 205524 kb
Host smart-81615864-cc4d-41d1-b845-d2cf32420b04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811635054 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.3811635054
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.3837406163
Short name T510
Test name
Test status
Simulation time 57423803528 ps
CPU time 702.75 seconds
Started Dec 31 12:53:32 PM PST 23
Finished Dec 31 01:05:27 PM PST 23
Peak memory 215628 kb
Host smart-8d190e30-46ec-453c-bde7-9948bbc8eb30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837406163 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.3837406163
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.933052648
Short name T648
Test name
Test status
Simulation time 19004577 ps
CPU time 0.96 seconds
Started Dec 31 12:53:49 PM PST 23
Finished Dec 31 12:54:02 PM PST 23
Peak memory 205104 kb
Host smart-f753db25-a4b0-4f05-9d6b-d8b37babc88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933052648 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.933052648
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.2543005780
Short name T480
Test name
Test status
Simulation time 28459988 ps
CPU time 0.91 seconds
Started Dec 31 12:53:35 PM PST 23
Finished Dec 31 12:53:48 PM PST 23
Peak memory 204496 kb
Host smart-3099d7f5-2d7c-40bd-84f2-412687889084
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543005780 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.2543005780
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.1373762950
Short name T215
Test name
Test status
Simulation time 16359687 ps
CPU time 0.86 seconds
Started Dec 31 12:53:33 PM PST 23
Finished Dec 31 12:53:46 PM PST 23
Peak memory 214272 kb
Host smart-bc28b624-2ba0-4408-9a6f-37969d63b69f
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373762950 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.1373762950
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.471038924
Short name T119
Test name
Test status
Simulation time 19412007 ps
CPU time 0.96 seconds
Started Dec 31 12:53:28 PM PST 23
Finished Dec 31 12:53:41 PM PST 23
Peak memory 214596 kb
Host smart-2ac0b47e-2750-4080-bdce-7fb9a241628a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471038924 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_di
sable_auto_req_mode.471038924
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.3400611472
Short name T190
Test name
Test status
Simulation time 29916982 ps
CPU time 1.09 seconds
Started Dec 31 12:53:44 PM PST 23
Finished Dec 31 12:53:58 PM PST 23
Peak memory 229908 kb
Host smart-9805b841-ff0b-4672-a976-c62ebbde2bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400611472 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.3400611472
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.367963388
Short name T505
Test name
Test status
Simulation time 58690152 ps
CPU time 0.99 seconds
Started Dec 31 12:53:46 PM PST 23
Finished Dec 31 12:53:59 PM PST 23
Peak memory 204876 kb
Host smart-9703dfcd-5d18-4844-93ff-af668dee72fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367963388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.367963388
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.2562908874
Short name T80
Test name
Test status
Simulation time 20423141 ps
CPU time 1.03 seconds
Started Dec 31 12:53:35 PM PST 23
Finished Dec 31 12:53:48 PM PST 23
Peak memory 214512 kb
Host smart-81aceb61-904a-4dfa-b532-8a406b0be04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562908874 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.2562908874
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.1165323982
Short name T653
Test name
Test status
Simulation time 26371505 ps
CPU time 0.86 seconds
Started Dec 31 12:53:42 PM PST 23
Finished Dec 31 12:53:54 PM PST 23
Peak memory 204808 kb
Host smart-dadcb5db-d4fe-41f2-90dc-12a45ddb0485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165323982 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.1165323982
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.3488235796
Short name T901
Test name
Test status
Simulation time 686833167 ps
CPU time 4.17 seconds
Started Dec 31 12:53:50 PM PST 23
Finished Dec 31 12:54:06 PM PST 23
Peak memory 206032 kb
Host smart-fb479cba-96c2-40f2-936b-e0b01a39bf55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488235796 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.3488235796
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.1053071946
Short name T910
Test name
Test status
Simulation time 61056233726 ps
CPU time 1476.01 seconds
Started Dec 31 12:53:34 PM PST 23
Finished Dec 31 01:18:23 PM PST 23
Peak memory 219128 kb
Host smart-1e5eb953-db27-4b12-b411-edc61f762216
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053071946 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.1053071946
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert_test.2471176978
Short name T788
Test name
Test status
Simulation time 17947042 ps
CPU time 0.95 seconds
Started Dec 31 12:53:33 PM PST 23
Finished Dec 31 12:53:46 PM PST 23
Peak memory 204584 kb
Host smart-cb6c0ef3-c738-45a2-a43b-3e4ed9540f9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471176978 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.2471176978
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.3030206008
Short name T116
Test name
Test status
Simulation time 20076222 ps
CPU time 0.91 seconds
Started Dec 31 12:53:42 PM PST 23
Finished Dec 31 12:53:55 PM PST 23
Peak memory 214252 kb
Host smart-c8d05958-4d4b-4f2e-9ec2-92a1af30a5f1
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030206008 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3030206008
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.3215524026
Short name T900
Test name
Test status
Simulation time 59718304 ps
CPU time 1.02 seconds
Started Dec 31 12:53:36 PM PST 23
Finished Dec 31 12:53:50 PM PST 23
Peak memory 214500 kb
Host smart-3211b57f-f9ee-434b-8d34-26d3a8721026
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215524026 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.3215524026
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.844697860
Short name T959
Test name
Test status
Simulation time 36710324 ps
CPU time 0.97 seconds
Started Dec 31 12:53:35 PM PST 23
Finished Dec 31 12:53:49 PM PST 23
Peak memory 228492 kb
Host smart-c5dfea47-c862-423e-ae92-cd481218e545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844697860 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.844697860
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.3203928453
Short name T43
Test name
Test status
Simulation time 33899813 ps
CPU time 1.04 seconds
Started Dec 31 12:53:46 PM PST 23
Finished Dec 31 12:53:59 PM PST 23
Peak memory 205532 kb
Host smart-c9d27cf4-0f29-4b5d-a205-58ddeb82f7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203928453 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.3203928453
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.3794898519
Short name T102
Test name
Test status
Simulation time 18238051 ps
CPU time 0.97 seconds
Started Dec 31 12:53:37 PM PST 23
Finished Dec 31 12:53:51 PM PST 23
Peak memory 214468 kb
Host smart-2405cd02-1f73-4968-aa8c-5eda3cbd10eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794898519 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.3794898519
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.2212879676
Short name T713
Test name
Test status
Simulation time 59563804 ps
CPU time 0.86 seconds
Started Dec 31 12:53:37 PM PST 23
Finished Dec 31 12:53:51 PM PST 23
Peak memory 204904 kb
Host smart-eae8f4aa-6c07-4aee-a0e7-9940bf77083a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212879676 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.2212879676
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.435397083
Short name T864
Test name
Test status
Simulation time 400546741 ps
CPU time 3.52 seconds
Started Dec 31 12:53:45 PM PST 23
Finished Dec 31 12:54:02 PM PST 23
Peak memory 205864 kb
Host smart-ced2dacc-9dcf-420f-a9af-c09a79cfcf31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435397083 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.435397083
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_alert.2617495341
Short name T356
Test name
Test status
Simulation time 39123903 ps
CPU time 0.95 seconds
Started Dec 31 12:54:04 PM PST 23
Finished Dec 31 12:54:13 PM PST 23
Peak memory 205612 kb
Host smart-e823f6e8-3531-4f57-afb6-2a832013423a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617495341 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.2617495341
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.4248511218
Short name T600
Test name
Test status
Simulation time 60510547 ps
CPU time 0.88 seconds
Started Dec 31 12:53:59 PM PST 23
Finished Dec 31 12:54:09 PM PST 23
Peak memory 204592 kb
Host smart-276324f2-9377-4b65-81cf-2438e9c8a3f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248511218 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.4248511218
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.421348496
Short name T890
Test name
Test status
Simulation time 42077764 ps
CPU time 0.85 seconds
Started Dec 31 12:53:37 PM PST 23
Finished Dec 31 12:53:51 PM PST 23
Peak memory 214272 kb
Host smart-96b62aef-47e2-4d3c-8691-f052d8621bc3
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421348496 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.421348496
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.1340950745
Short name T180
Test name
Test status
Simulation time 264445829 ps
CPU time 1.13 seconds
Started Dec 31 12:53:52 PM PST 23
Finished Dec 31 12:54:04 PM PST 23
Peak memory 214656 kb
Host smart-1619fa20-33ed-4afe-9f8c-d9428e0fad4b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340950745 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.1340950745
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.589055527
Short name T855
Test name
Test status
Simulation time 30732876 ps
CPU time 1.19 seconds
Started Dec 31 12:53:57 PM PST 23
Finished Dec 31 12:54:08 PM PST 23
Peak memory 215712 kb
Host smart-73e9e8fe-daec-4673-b26d-e451a5838288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589055527 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.589055527
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.1660188243
Short name T841
Test name
Test status
Simulation time 77779547 ps
CPU time 1.09 seconds
Started Dec 31 12:53:45 PM PST 23
Finished Dec 31 12:53:59 PM PST 23
Peak memory 214124 kb
Host smart-c6332859-44e5-4123-88d8-484d4a408551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660188243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1660188243
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.385302449
Short name T230
Test name
Test status
Simulation time 38406257 ps
CPU time 0.85 seconds
Started Dec 31 12:53:41 PM PST 23
Finished Dec 31 12:53:54 PM PST 23
Peak memory 214072 kb
Host smart-70849a57-6fbd-4647-a1bb-c77187223979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385302449 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.385302449
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.1387576191
Short name T724
Test name
Test status
Simulation time 13790895 ps
CPU time 0.89 seconds
Started Dec 31 12:53:33 PM PST 23
Finished Dec 31 12:53:46 PM PST 23
Peak memory 204784 kb
Host smart-711d3f08-f8a8-4df2-adfa-b5bc1f308669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387576191 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.1387576191
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.1022259762
Short name T726
Test name
Test status
Simulation time 445411506 ps
CPU time 2.71 seconds
Started Dec 31 12:53:52 PM PST 23
Finished Dec 31 12:54:06 PM PST 23
Peak memory 205616 kb
Host smart-6f2165b1-9291-4fc2-8d6c-82307b3bf31c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022259762 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.1022259762
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.3875755119
Short name T922
Test name
Test status
Simulation time 1164844027845 ps
CPU time 1829.8 seconds
Started Dec 31 12:54:03 PM PST 23
Finished Dec 31 01:24:41 PM PST 23
Peak memory 221960 kb
Host smart-dcae0d11-6971-4eb0-9bce-00f7366655ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875755119 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.3875755119
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.77618856
Short name T668
Test name
Test status
Simulation time 18501473 ps
CPU time 1.08 seconds
Started Dec 31 12:53:56 PM PST 23
Finished Dec 31 12:54:07 PM PST 23
Peak memory 205920 kb
Host smart-e0db6477-5651-43f1-9ad4-c669812903d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77618856 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.77618856
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.1728407673
Short name T551
Test name
Test status
Simulation time 50142520 ps
CPU time 0.84 seconds
Started Dec 31 12:54:26 PM PST 23
Finished Dec 31 12:54:28 PM PST 23
Peak memory 204492 kb
Host smart-9883e9e1-eb6e-431a-9b9f-e718698bedd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728407673 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.1728407673
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.2265394770
Short name T908
Test name
Test status
Simulation time 13247982 ps
CPU time 0.88 seconds
Started Dec 31 12:54:09 PM PST 23
Finished Dec 31 12:54:15 PM PST 23
Peak memory 214492 kb
Host smart-7bfcf297-6457-4604-bbb5-965a8a1f84e7
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265394770 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.2265394770
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.1161465599
Short name T622
Test name
Test status
Simulation time 148594938 ps
CPU time 1.1 seconds
Started Dec 31 12:53:57 PM PST 23
Finished Dec 31 12:54:13 PM PST 23
Peak memory 214548 kb
Host smart-df54fa46-4c2e-4e81-85ec-59a17b193038
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161465599 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.1161465599
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.1000084305
Short name T720
Test name
Test status
Simulation time 65448945 ps
CPU time 0.97 seconds
Started Dec 31 12:54:06 PM PST 23
Finished Dec 31 12:54:13 PM PST 23
Peak memory 221036 kb
Host smart-14ae9d0f-5757-42be-afd9-4307286c1662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000084305 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.1000084305
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.3962129874
Short name T291
Test name
Test status
Simulation time 132233731 ps
CPU time 1.57 seconds
Started Dec 31 12:54:02 PM PST 23
Finished Dec 31 12:54:12 PM PST 23
Peak memory 214096 kb
Host smart-81f3a44f-8209-443f-b1f8-f52a4f4e7fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962129874 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3962129874
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.271756180
Short name T99
Test name
Test status
Simulation time 28360304 ps
CPU time 0.98 seconds
Started Dec 31 12:53:49 PM PST 23
Finished Dec 31 12:54:02 PM PST 23
Peak memory 225648 kb
Host smart-1ffc882d-b26a-4c39-b1c6-46d472781831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271756180 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.271756180
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.1399606891
Short name T507
Test name
Test status
Simulation time 17261148 ps
CPU time 0.92 seconds
Started Dec 31 12:53:39 PM PST 23
Finished Dec 31 12:53:52 PM PST 23
Peak memory 204800 kb
Host smart-2db55cff-e4f4-487f-a450-c3b9c59bd2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399606891 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.1399606891
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.612194078
Short name T711
Test name
Test status
Simulation time 152910930 ps
CPU time 2.14 seconds
Started Dec 31 12:53:37 PM PST 23
Finished Dec 31 12:53:52 PM PST 23
Peak memory 214132 kb
Host smart-c6fc77ec-bf6b-4c92-8dba-370b0d653199
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612194078 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.612194078
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3363217040
Short name T702
Test name
Test status
Simulation time 138103617326 ps
CPU time 1529.58 seconds
Started Dec 31 12:53:42 PM PST 23
Finished Dec 31 01:19:23 PM PST 23
Peak memory 218856 kb
Host smart-044ffaba-ba7a-4764-8dce-34dbb5634894
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363217040 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.3363217040
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.2333562443
Short name T547
Test name
Test status
Simulation time 31424888 ps
CPU time 1.01 seconds
Started Dec 31 12:53:30 PM PST 23
Finished Dec 31 12:53:43 PM PST 23
Peak memory 205132 kb
Host smart-ab3c773f-f5d0-4677-b79d-c3cdebf83900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333562443 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.2333562443
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.2987821771
Short name T487
Test name
Test status
Simulation time 88851426 ps
CPU time 1 seconds
Started Dec 31 12:53:52 PM PST 23
Finished Dec 31 12:54:04 PM PST 23
Peak memory 205468 kb
Host smart-966e55af-9606-4eb7-a2e4-274e80e6b52e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987821771 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.2987821771
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.1530447169
Short name T211
Test name
Test status
Simulation time 12228871 ps
CPU time 0.86 seconds
Started Dec 31 12:53:52 PM PST 23
Finished Dec 31 12:54:04 PM PST 23
Peak memory 214528 kb
Host smart-b59feb15-7106-4b0c-b8a9-07f1d9fb494f
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530447169 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.1530447169
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.2291513336
Short name T118
Test name
Test status
Simulation time 14862412 ps
CPU time 0.93 seconds
Started Dec 31 12:53:42 PM PST 23
Finished Dec 31 12:53:54 PM PST 23
Peak memory 214468 kb
Host smart-e28b27ce-c67b-481b-a115-58eb5a21228a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291513336 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.2291513336
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.2541282577
Short name T52
Test name
Test status
Simulation time 28692786 ps
CPU time 1.05 seconds
Started Dec 31 12:54:42 PM PST 23
Finished Dec 31 12:54:45 PM PST 23
Peak memory 221780 kb
Host smart-e7378ad1-a30a-497c-95ab-50fbb3d95ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541282577 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.2541282577
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.2170360920
Short name T293
Test name
Test status
Simulation time 71613121 ps
CPU time 0.88 seconds
Started Dec 31 12:54:25 PM PST 23
Finished Dec 31 12:54:28 PM PST 23
Peak memory 205016 kb
Host smart-817240cc-a58c-4452-b25b-9840b86bef7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170360920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.2170360920
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.1185475223
Short name T575
Test name
Test status
Simulation time 21165406 ps
CPU time 0.99 seconds
Started Dec 31 12:54:11 PM PST 23
Finished Dec 31 12:54:15 PM PST 23
Peak memory 214216 kb
Host smart-c20505e2-f6fd-4f68-8230-66da2d2aa961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185475223 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.1185475223
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.3726472048
Short name T470
Test name
Test status
Simulation time 11951756 ps
CPU time 0.86 seconds
Started Dec 31 12:53:50 PM PST 23
Finished Dec 31 12:54:03 PM PST 23
Peak memory 204812 kb
Host smart-5b9bd8b7-9200-44be-b3c7-a8babd9e86a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726472048 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.3726472048
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.2055870057
Short name T614
Test name
Test status
Simulation time 91403949 ps
CPU time 1.63 seconds
Started Dec 31 12:53:54 PM PST 23
Finished Dec 31 12:54:06 PM PST 23
Peak memory 205104 kb
Host smart-381e52d4-5811-4cb4-bbc6-bcb8389cb89e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055870057 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.2055870057
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.2416830044
Short name T317
Test name
Test status
Simulation time 52238078432 ps
CPU time 1312 seconds
Started Dec 31 12:54:31 PM PST 23
Finished Dec 31 01:16:25 PM PST 23
Peak memory 217068 kb
Host smart-5064c27c-8e02-4a92-a8c8-fc1293e6bb4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416830044 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.2416830044
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.1698497838
Short name T340
Test name
Test status
Simulation time 19450912 ps
CPU time 0.96 seconds
Started Dec 31 12:53:33 PM PST 23
Finished Dec 31 12:53:46 PM PST 23
Peak memory 205964 kb
Host smart-9267a538-2b87-4ec8-9fbd-4fc4d85d68eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698497838 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.1698497838
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.1118269788
Short name T926
Test name
Test status
Simulation time 24406380 ps
CPU time 0.92 seconds
Started Dec 31 12:53:33 PM PST 23
Finished Dec 31 12:53:46 PM PST 23
Peak memory 205220 kb
Host smart-14962cb2-dd81-4bda-a7b9-3423c478acf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118269788 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.1118269788
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.2244100903
Short name T550
Test name
Test status
Simulation time 43071330 ps
CPU time 0.86 seconds
Started Dec 31 12:53:50 PM PST 23
Finished Dec 31 12:54:03 PM PST 23
Peak memory 214344 kb
Host smart-1dbfc638-a24a-4fd7-bf06-47bd168b6238
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244100903 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2244100903
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.1955862877
Short name T93
Test name
Test status
Simulation time 80276587 ps
CPU time 0.89 seconds
Started Dec 31 12:54:01 PM PST 23
Finished Dec 31 12:54:11 PM PST 23
Peak memory 214656 kb
Host smart-f4b79c74-196f-4de8-a405-6f2ac728e54b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955862877 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.1955862877
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.1414400849
Short name T265
Test name
Test status
Simulation time 44347163 ps
CPU time 1.06 seconds
Started Dec 31 12:53:30 PM PST 23
Finished Dec 31 12:53:43 PM PST 23
Peak memory 216820 kb
Host smart-da9ee908-4ace-4408-a32d-ba562cf4bd30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414400849 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.1414400849
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.1867236182
Short name T909
Test name
Test status
Simulation time 21170809 ps
CPU time 1.31 seconds
Started Dec 31 12:54:01 PM PST 23
Finished Dec 31 12:54:12 PM PST 23
Peak memory 214200 kb
Host smart-8d4ccd16-99a3-4c81-a8a1-262e3be190b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867236182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.1867236182
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.1583621496
Short name T4
Test name
Test status
Simulation time 36882524 ps
CPU time 0.89 seconds
Started Dec 31 12:53:59 PM PST 23
Finished Dec 31 12:54:10 PM PST 23
Peak memory 214296 kb
Host smart-953c2dee-f3f9-4571-8a4f-76c4bcc1f24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583621496 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.1583621496
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.2653388965
Short name T663
Test name
Test status
Simulation time 23036339 ps
CPU time 0.86 seconds
Started Dec 31 12:55:04 PM PST 23
Finished Dec 31 12:55:10 PM PST 23
Peak memory 204568 kb
Host smart-d0f78f0d-92a8-4a44-b5d3-19b947b50d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653388965 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.2653388965
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.1436932237
Short name T571
Test name
Test status
Simulation time 111505607 ps
CPU time 1.78 seconds
Started Dec 31 12:53:42 PM PST 23
Finished Dec 31 12:53:55 PM PST 23
Peak memory 205752 kb
Host smart-fe80f9ff-bbe9-4239-9eb3-5f7a6a66f63f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436932237 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.1436932237
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.4171622053
Short name T324
Test name
Test status
Simulation time 17917121797 ps
CPU time 200.8 seconds
Started Dec 31 12:53:38 PM PST 23
Finished Dec 31 12:57:11 PM PST 23
Peak memory 214648 kb
Host smart-d488d1ea-5f22-4886-8b33-cb6bface08e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171622053 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.4171622053
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.1866950542
Short name T358
Test name
Test status
Simulation time 35664496 ps
CPU time 0.95 seconds
Started Dec 31 12:52:10 PM PST 23
Finished Dec 31 12:52:25 PM PST 23
Peak memory 205044 kb
Host smart-02c48c88-d59c-4d00-bba6-a6342c095d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866950542 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.1866950542
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.333397015
Short name T518
Test name
Test status
Simulation time 20124350 ps
CPU time 0.88 seconds
Started Dec 31 12:52:14 PM PST 23
Finished Dec 31 12:52:29 PM PST 23
Peak memory 204264 kb
Host smart-e8292be8-72aa-4132-b2e7-5474fbcac1ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333397015 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.333397015
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.2564435940
Short name T932
Test name
Test status
Simulation time 50970873 ps
CPU time 0.84 seconds
Started Dec 31 12:52:11 PM PST 23
Finished Dec 31 12:52:27 PM PST 23
Peak memory 214300 kb
Host smart-547a781b-4ade-481e-a966-4625410c75a4
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564435940 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.2564435940
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.640883667
Short name T200
Test name
Test status
Simulation time 27368338 ps
CPU time 1.08 seconds
Started Dec 31 12:52:15 PM PST 23
Finished Dec 31 12:52:32 PM PST 23
Peak memory 214612 kb
Host smart-3e756fb2-7fbe-413c-9b94-ec560a88d8db
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640883667 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_dis
able_auto_req_mode.640883667
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.489947005
Short name T794
Test name
Test status
Simulation time 170879704 ps
CPU time 1.25 seconds
Started Dec 31 12:52:12 PM PST 23
Finished Dec 31 12:52:29 PM PST 23
Peak memory 227468 kb
Host smart-d8cbd647-ad1e-4ec0-8da6-51e57f1efdaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489947005 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.489947005
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.4278163703
Short name T91
Test name
Test status
Simulation time 24096062 ps
CPU time 1.09 seconds
Started Dec 31 12:52:21 PM PST 23
Finished Dec 31 12:52:35 PM PST 23
Peak memory 205568 kb
Host smart-555327ec-fdd8-4c95-8a2d-3f362507f084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278163703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.4278163703
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.1463064212
Short name T877
Test name
Test status
Simulation time 36246191 ps
CPU time 0.84 seconds
Started Dec 31 12:52:19 PM PST 23
Finished Dec 31 12:52:34 PM PST 23
Peak memory 214220 kb
Host smart-2250afce-fb16-4910-9b3e-11e8d78be412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463064212 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.1463064212
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_smoke.319157778
Short name T905
Test name
Test status
Simulation time 56343769 ps
CPU time 0.84 seconds
Started Dec 31 12:52:15 PM PST 23
Finished Dec 31 12:52:31 PM PST 23
Peak memory 204688 kb
Host smart-d9c3975c-1964-4483-8325-82aae67d2a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319157778 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.319157778
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.3301387733
Short name T472
Test name
Test status
Simulation time 299222237 ps
CPU time 2.02 seconds
Started Dec 31 12:52:12 PM PST 23
Finished Dec 31 12:52:29 PM PST 23
Peak memory 205668 kb
Host smart-d46e1d79-603e-453b-b282-d2eb8e94cc51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301387733 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.3301387733
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.3808250138
Short name T483
Test name
Test status
Simulation time 22272037537 ps
CPU time 567.62 seconds
Started Dec 31 12:52:15 PM PST 23
Finished Dec 31 01:01:57 PM PST 23
Peak memory 214420 kb
Host smart-40051797-a741-4b8e-832a-0d1f0478588d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808250138 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.3808250138
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.2355826893
Short name T639
Test name
Test status
Simulation time 18680897 ps
CPU time 1 seconds
Started Dec 31 12:53:46 PM PST 23
Finished Dec 31 12:54:00 PM PST 23
Peak memory 215748 kb
Host smart-8ca55ebd-a2c8-4160-9ce7-b047c1a6e109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355826893 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.2355826893
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.267021187
Short name T634
Test name
Test status
Simulation time 36951917 ps
CPU time 0.96 seconds
Started Dec 31 12:54:02 PM PST 23
Finished Dec 31 12:54:12 PM PST 23
Peak memory 205100 kb
Host smart-5fca56b2-0d79-4e3a-b1f1-5b2ae70d90a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267021187 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.267021187
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.2274149322
Short name T212
Test name
Test status
Simulation time 27039559 ps
CPU time 0.81 seconds
Started Dec 31 12:53:38 PM PST 23
Finished Dec 31 12:53:51 PM PST 23
Peak memory 215328 kb
Host smart-3cbf90f7-8064-46ee-a621-661763c31eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274149322 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.2274149322
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.3689700097
Short name T74
Test name
Test status
Simulation time 33345995 ps
CPU time 0.91 seconds
Started Dec 31 12:53:38 PM PST 23
Finished Dec 31 12:53:55 PM PST 23
Peak memory 204904 kb
Host smart-7a78f6c1-ccfd-44d7-9f10-34527079b57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689700097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.3689700097
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_genbits.426320315
Short name T9
Test name
Test status
Simulation time 61409512 ps
CPU time 1.41 seconds
Started Dec 31 12:53:41 PM PST 23
Finished Dec 31 12:53:54 PM PST 23
Peak memory 214124 kb
Host smart-559e4a5b-026c-45d7-9688-c64bab6ad5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426320315 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.426320315
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.2833738876
Short name T597
Test name
Test status
Simulation time 32816618 ps
CPU time 0.98 seconds
Started Dec 31 12:54:18 PM PST 23
Finished Dec 31 12:54:21 PM PST 23
Peak memory 215760 kb
Host smart-9a7424c0-8666-42e6-86f5-eef795aa0814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833738876 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.2833738876
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.157160281
Short name T615
Test name
Test status
Simulation time 17936012 ps
CPU time 0.99 seconds
Started Dec 31 12:54:02 PM PST 23
Finished Dec 31 12:54:12 PM PST 23
Peak memory 205192 kb
Host smart-d164a2d1-adb0-4498-8272-cf2707a9b9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157160281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.157160281
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.1422595179
Short name T252
Test name
Test status
Simulation time 37462685 ps
CPU time 1.06 seconds
Started Dec 31 12:53:56 PM PST 23
Finished Dec 31 12:54:07 PM PST 23
Peak memory 214740 kb
Host smart-9aff4863-80a6-4c2e-a2c4-93972552be42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422595179 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.1422595179
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.4186574135
Short name T691
Test name
Test status
Simulation time 59588891 ps
CPU time 1.1 seconds
Started Dec 31 12:54:29 PM PST 23
Finished Dec 31 12:54:32 PM PST 23
Peak memory 205656 kb
Host smart-464566bb-998d-4dcb-9450-79b78e0cbad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186574135 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.4186574135
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.3586721528
Short name T213
Test name
Test status
Simulation time 19485893 ps
CPU time 1.14 seconds
Started Dec 31 12:54:32 PM PST 23
Finished Dec 31 12:54:34 PM PST 23
Peak memory 221708 kb
Host smart-75f532e6-2ad8-4af9-a8cb-e1fbd57804f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586721528 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.3586721528
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.4221685539
Short name T838
Test name
Test status
Simulation time 15739800 ps
CPU time 1.02 seconds
Started Dec 31 12:54:09 PM PST 23
Finished Dec 31 12:54:15 PM PST 23
Peak memory 205960 kb
Host smart-80be1fc1-baff-4eb4-b55e-f74808fd1b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221685539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.4221685539
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.2943459999
Short name T814
Test name
Test status
Simulation time 28262462 ps
CPU time 0.91 seconds
Started Dec 31 12:54:52 PM PST 23
Finished Dec 31 12:54:58 PM PST 23
Peak memory 220952 kb
Host smart-7d05d8f6-4a84-457c-847c-a13b4e10b92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943459999 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.2943459999
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.2029318226
Short name T555
Test name
Test status
Simulation time 18816787 ps
CPU time 0.96 seconds
Started Dec 31 12:55:07 PM PST 23
Finished Dec 31 12:55:13 PM PST 23
Peak memory 205500 kb
Host smart-b4732916-5add-4d44-b6dc-d6100da3f35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029318226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.2029318226
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.1860545878
Short name T184
Test name
Test status
Simulation time 20170810 ps
CPU time 1.04 seconds
Started Dec 31 12:54:29 PM PST 23
Finished Dec 31 12:54:36 PM PST 23
Peak memory 214540 kb
Host smart-7eb640c4-f5e7-41d4-96de-ca71d26c13a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860545878 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.1860545878
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.1159138691
Short name T370
Test name
Test status
Simulation time 22475314 ps
CPU time 1.01 seconds
Started Dec 31 12:54:21 PM PST 23
Finished Dec 31 12:54:23 PM PST 23
Peak memory 205072 kb
Host smart-c5008bfd-61f5-43c6-8e2a-326580b66977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159138691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.1159138691
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.3356120477
Short name T204
Test name
Test status
Simulation time 84676339 ps
CPU time 1.15 seconds
Started Dec 31 12:54:50 PM PST 23
Finished Dec 31 12:54:55 PM PST 23
Peak memory 221860 kb
Host smart-e9193029-c696-46a6-963d-3950fc724da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356120477 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.3356120477
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.3488319170
Short name T32
Test name
Test status
Simulation time 39004834 ps
CPU time 1.25 seconds
Started Dec 31 12:54:39 PM PST 23
Finished Dec 31 12:54:43 PM PST 23
Peak memory 205452 kb
Host smart-682a08d0-a22e-4a32-a7ec-927e3673cc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488319170 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.3488319170
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.1061144653
Short name T197
Test name
Test status
Simulation time 69273139 ps
CPU time 1.04 seconds
Started Dec 31 12:54:35 PM PST 23
Finished Dec 31 12:54:38 PM PST 23
Peak memory 214656 kb
Host smart-befc5098-4404-49b3-bec8-7bb2f6be5d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061144653 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.1061144653
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.2600349754
Short name T718
Test name
Test status
Simulation time 14551539 ps
CPU time 0.91 seconds
Started Dec 31 12:54:56 PM PST 23
Finished Dec 31 12:55:02 PM PST 23
Peak memory 204864 kb
Host smart-118fca9f-6836-4965-ac88-6a778d70a539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600349754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.2600349754
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.4145647752
Short name T274
Test name
Test status
Simulation time 42469859 ps
CPU time 0.92 seconds
Started Dec 31 12:52:15 PM PST 23
Finished Dec 31 12:52:31 PM PST 23
Peak memory 205832 kb
Host smart-e94bc34a-e184-4f66-9204-049e2a79a8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145647752 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.4145647752
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.445711838
Short name T815
Test name
Test status
Simulation time 90093185 ps
CPU time 0.94 seconds
Started Dec 31 12:52:10 PM PST 23
Finished Dec 31 12:52:26 PM PST 23
Peak memory 204648 kb
Host smart-12c7aae4-6a32-44ab-8192-a68bbd6c4496
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445711838 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.445711838
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.800785915
Short name T185
Test name
Test status
Simulation time 17437802 ps
CPU time 0.96 seconds
Started Dec 31 12:52:09 PM PST 23
Finished Dec 31 12:52:24 PM PST 23
Peak memory 214464 kb
Host smart-cbe9f152-9e04-4ab4-9493-cbd553696edf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800785915 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_dis
able_auto_req_mode.800785915
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.1013214330
Short name T790
Test name
Test status
Simulation time 18119709 ps
CPU time 1.35 seconds
Started Dec 31 12:52:06 PM PST 23
Finished Dec 31 12:52:20 PM PST 23
Peak memory 221456 kb
Host smart-0b78070a-8593-4be3-9bfe-f2db8b5b5812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013214330 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.1013214330
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.1789716241
Short name T719
Test name
Test status
Simulation time 68395904 ps
CPU time 2.39 seconds
Started Dec 31 12:52:10 PM PST 23
Finished Dec 31 12:52:27 PM PST 23
Peak memory 213984 kb
Host smart-f1c3c3ff-3a54-43f0-b668-9c47ed04a561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789716241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.1789716241
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.898895372
Short name T661
Test name
Test status
Simulation time 26515593 ps
CPU time 1.02 seconds
Started Dec 31 12:52:13 PM PST 23
Finished Dec 31 12:52:29 PM PST 23
Peak memory 221784 kb
Host smart-7816e1d0-ff78-4706-a899-3fd2acc37fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898895372 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.898895372
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_smoke.1515593296
Short name T781
Test name
Test status
Simulation time 44940463 ps
CPU time 0.82 seconds
Started Dec 31 12:52:19 PM PST 23
Finished Dec 31 12:52:34 PM PST 23
Peak memory 204804 kb
Host smart-0f175faf-248c-476e-86fd-c8c59952ee55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515593296 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.1515593296
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.1531223040
Short name T925
Test name
Test status
Simulation time 644215795 ps
CPU time 3.94 seconds
Started Dec 31 12:52:07 PM PST 23
Finished Dec 31 12:52:25 PM PST 23
Peak memory 205944 kb
Host smart-59927951-0bd8-4484-840f-09247167ec88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531223040 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.1531223040
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.2107540112
Short name T577
Test name
Test status
Simulation time 143528967082 ps
CPU time 559.05 seconds
Started Dec 31 12:52:14 PM PST 23
Finished Dec 31 01:01:48 PM PST 23
Peak memory 215504 kb
Host smart-253eaae3-919c-43a4-92d4-01a4d7eb395a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107540112 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.2107540112
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.961692216
Short name T14
Test name
Test status
Simulation time 23330710 ps
CPU time 0.95 seconds
Started Dec 31 12:54:33 PM PST 23
Finished Dec 31 12:54:36 PM PST 23
Peak memory 221224 kb
Host smart-558e0219-fa93-4470-ab08-d7f5919453fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961692216 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.961692216
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.2446413903
Short name T950
Test name
Test status
Simulation time 22037942 ps
CPU time 0.91 seconds
Started Dec 31 12:54:34 PM PST 23
Finished Dec 31 12:54:37 PM PST 23
Peak memory 205144 kb
Host smart-033dd627-0e09-49fa-a786-8bb4946932e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446413903 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.2446413903
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.3888263802
Short name T208
Test name
Test status
Simulation time 26926752 ps
CPU time 0.82 seconds
Started Dec 31 12:54:00 PM PST 23
Finished Dec 31 12:54:11 PM PST 23
Peak memory 215340 kb
Host smart-8ba7628e-9e99-4f27-8514-50c6050e8f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888263802 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.3888263802
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.4118135846
Short name T681
Test name
Test status
Simulation time 20856597 ps
CPU time 1.11 seconds
Started Dec 31 12:53:50 PM PST 23
Finished Dec 31 12:54:03 PM PST 23
Peak memory 205468 kb
Host smart-b44cdfc5-b6c7-4263-9c34-9c7b223ceac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118135846 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.4118135846
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.2599412795
Short name T912
Test name
Test status
Simulation time 18267769 ps
CPU time 1.11 seconds
Started Dec 31 12:53:46 PM PST 23
Finished Dec 31 12:54:00 PM PST 23
Peak memory 221636 kb
Host smart-e7f0e900-e614-4a6c-b84d-027721e028be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599412795 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.2599412795
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.2003588154
Short name T892
Test name
Test status
Simulation time 87692003 ps
CPU time 0.96 seconds
Started Dec 31 12:54:12 PM PST 23
Finished Dec 31 12:54:16 PM PST 23
Peak memory 205536 kb
Host smart-7d065792-c938-4948-b6c7-a0cf307ceb9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003588154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.2003588154
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.3192000560
Short name T673
Test name
Test status
Simulation time 24715426 ps
CPU time 1.26 seconds
Started Dec 31 12:54:24 PM PST 23
Finished Dec 31 12:54:28 PM PST 23
Peak memory 228420 kb
Host smart-0a658c5a-cecc-4b82-8f85-f7a718d5a6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192000560 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.3192000560
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.3169335157
Short name T822
Test name
Test status
Simulation time 17945403 ps
CPU time 1 seconds
Started Dec 31 12:53:57 PM PST 23
Finished Dec 31 12:54:08 PM PST 23
Peak memory 205408 kb
Host smart-e6120504-bbfa-4386-b1c9-212a1b6b08fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169335157 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.3169335157
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.2055812768
Short name T55
Test name
Test status
Simulation time 53247665 ps
CPU time 1.08 seconds
Started Dec 31 12:53:33 PM PST 23
Finished Dec 31 12:53:46 PM PST 23
Peak memory 228424 kb
Host smart-9f4cbfc3-2227-472d-8b79-f01bf0e7b7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055812768 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.2055812768
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.1575968999
Short name T857
Test name
Test status
Simulation time 47220809 ps
CPU time 0.94 seconds
Started Dec 31 12:53:44 PM PST 23
Finished Dec 31 12:53:57 PM PST 23
Peak memory 205052 kb
Host smart-6348f2ff-e820-4b21-a860-2b17d311ef9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575968999 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.1575968999
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.2714428935
Short name T888
Test name
Test status
Simulation time 18450091 ps
CPU time 1.01 seconds
Started Dec 31 12:53:42 PM PST 23
Finished Dec 31 12:53:54 PM PST 23
Peak memory 215868 kb
Host smart-ed24dedf-97fb-4d6e-9466-2439b19901ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714428935 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.2714428935
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.3953545629
Short name T874
Test name
Test status
Simulation time 39948802 ps
CPU time 1.87 seconds
Started Dec 31 12:53:42 PM PST 23
Finished Dec 31 12:53:55 PM PST 23
Peak memory 214192 kb
Host smart-fcb10a13-c3d8-468f-b946-5770d2bc2bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953545629 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.3953545629
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.2492590603
Short name T172
Test name
Test status
Simulation time 43736855 ps
CPU time 1.17 seconds
Started Dec 31 12:54:10 PM PST 23
Finished Dec 31 12:54:15 PM PST 23
Peak memory 214592 kb
Host smart-7690e4cb-5665-454d-b4ff-e90f31ff77fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492590603 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.2492590603
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.3984726758
Short name T2
Test name
Test status
Simulation time 53822308 ps
CPU time 0.89 seconds
Started Dec 31 12:53:57 PM PST 23
Finished Dec 31 12:54:08 PM PST 23
Peak memory 205084 kb
Host smart-fd545fcf-d494-4ead-bda5-963433e56faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984726758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.3984726758
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.1857419622
Short name T189
Test name
Test status
Simulation time 19776459 ps
CPU time 1.55 seconds
Started Dec 31 12:54:02 PM PST 23
Finished Dec 31 12:54:12 PM PST 23
Peak memory 230024 kb
Host smart-1058ca62-5e2a-4270-a1e9-09daa48d0f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857419622 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1857419622
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.969068583
Short name T327
Test name
Test status
Simulation time 227037885 ps
CPU time 1.03 seconds
Started Dec 31 12:53:43 PM PST 23
Finished Dec 31 12:53:56 PM PST 23
Peak memory 205488 kb
Host smart-7f51e95a-dd10-41ec-b660-0ae8115bd3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969068583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.969068583
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_genbits.1411474489
Short name T777
Test name
Test status
Simulation time 24068838 ps
CPU time 0.96 seconds
Started Dec 31 12:53:41 PM PST 23
Finished Dec 31 12:53:53 PM PST 23
Peak memory 205332 kb
Host smart-754229fa-f6f4-4fab-88e7-25bad8da8e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411474489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.1411474489
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.2555658139
Short name T120
Test name
Test status
Simulation time 18797360 ps
CPU time 1.03 seconds
Started Dec 31 12:53:52 PM PST 23
Finished Dec 31 12:54:04 PM PST 23
Peak memory 214624 kb
Host smart-0199d26c-949d-4f0b-9496-6999feca95bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555658139 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.2555658139
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.3518202308
Short name T721
Test name
Test status
Simulation time 116717565 ps
CPU time 2.57 seconds
Started Dec 31 12:53:57 PM PST 23
Finished Dec 31 12:54:09 PM PST 23
Peak memory 214124 kb
Host smart-2533416d-c828-46e0-b829-9dfd5b48025e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518202308 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.3518202308
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.1631208011
Short name T357
Test name
Test status
Simulation time 115305313 ps
CPU time 0.95 seconds
Started Dec 31 12:52:13 PM PST 23
Finished Dec 31 12:52:29 PM PST 23
Peak memory 205940 kb
Host smart-13c912aa-9d23-4b17-8d62-9c0ed69cc5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631208011 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.1631208011
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.3389810454
Short name T923
Test name
Test status
Simulation time 39337393 ps
CPU time 0.8 seconds
Started Dec 31 12:52:14 PM PST 23
Finished Dec 31 12:52:29 PM PST 23
Peak memory 204352 kb
Host smart-56814beb-2a47-4dfb-be9f-be06a0853600
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389810454 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.3389810454
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.3568413867
Short name T830
Test name
Test status
Simulation time 12346347 ps
CPU time 0.87 seconds
Started Dec 31 12:52:12 PM PST 23
Finished Dec 31 12:52:28 PM PST 23
Peak memory 214440 kb
Host smart-1e7d0045-d77e-4c59-97e1-fb5ffa29b886
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568413867 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.3568413867
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.306581371
Short name T868
Test name
Test status
Simulation time 59893438 ps
CPU time 0.99 seconds
Started Dec 31 12:52:09 PM PST 23
Finished Dec 31 12:52:24 PM PST 23
Peak memory 214528 kb
Host smart-e60cf390-2237-4cb0-abfe-9cfebcc56a66
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306581371 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_dis
able_auto_req_mode.306581371
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.3733292651
Short name T944
Test name
Test status
Simulation time 68351475 ps
CPU time 0.97 seconds
Started Dec 31 12:52:09 PM PST 23
Finished Dec 31 12:52:24 PM PST 23
Peak memory 217008 kb
Host smart-63e5ef0a-44d4-459b-b15b-cb6688ecf2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733292651 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.3733292651
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.1274517961
Short name T647
Test name
Test status
Simulation time 37126225 ps
CPU time 1.29 seconds
Started Dec 31 12:52:10 PM PST 23
Finished Dec 31 12:52:26 PM PST 23
Peak memory 205556 kb
Host smart-af9b961b-729c-4341-8ff3-1475dc6498b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274517961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1274517961
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.4110547759
Short name T100
Test name
Test status
Simulation time 22384981 ps
CPU time 1 seconds
Started Dec 31 12:52:12 PM PST 23
Finished Dec 31 12:52:28 PM PST 23
Peak memory 225620 kb
Host smart-a365133b-2c61-49e4-82fc-241da308bc78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110547759 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.4110547759
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.2962706915
Short name T339
Test name
Test status
Simulation time 69411805 ps
CPU time 0.79 seconds
Started Dec 31 12:52:14 PM PST 23
Finished Dec 31 12:52:29 PM PST 23
Peak memory 204652 kb
Host smart-43bcf429-9857-4fa8-83a2-f5c49b500afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962706915 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.2962706915
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.1582064851
Short name T853
Test name
Test status
Simulation time 23719444 ps
CPU time 0.87 seconds
Started Dec 31 12:52:08 PM PST 23
Finished Dec 31 12:52:22 PM PST 23
Peak memory 204868 kb
Host smart-64b70b3d-124b-4421-ad1c-03df309784e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582064851 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.1582064851
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.1732665945
Short name T253
Test name
Test status
Simulation time 24617320 ps
CPU time 1.08 seconds
Started Dec 31 12:52:08 PM PST 23
Finished Dec 31 12:52:23 PM PST 23
Peak memory 204784 kb
Host smart-17bf5ec9-b881-4fe8-a579-a30c7ace95ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732665945 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.1732665945
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.3905202378
Short name T319
Test name
Test status
Simulation time 77906215537 ps
CPU time 1948.98 seconds
Started Dec 31 12:52:08 PM PST 23
Finished Dec 31 01:24:52 PM PST 23
Peak memory 222908 kb
Host smart-9b02e5a2-a71a-4068-9d09-20aa0fa7af63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905202378 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.3905202378
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.1255693569
Short name T50
Test name
Test status
Simulation time 28946613 ps
CPU time 1.27 seconds
Started Dec 31 12:53:37 PM PST 23
Finished Dec 31 12:53:51 PM PST 23
Peak memory 221868 kb
Host smart-2ff0b437-4d99-4bfe-84c3-5c8b2d279062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255693569 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.1255693569
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.1969523964
Short name T685
Test name
Test status
Simulation time 78547081 ps
CPU time 0.99 seconds
Started Dec 31 12:53:51 PM PST 23
Finished Dec 31 12:54:04 PM PST 23
Peak memory 205456 kb
Host smart-15747ee7-7685-4f5d-80f0-a8f11abfcdf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969523964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.1969523964
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.101233673
Short name T222
Test name
Test status
Simulation time 22692679 ps
CPU time 0.86 seconds
Started Dec 31 12:53:39 PM PST 23
Finished Dec 31 12:53:52 PM PST 23
Peak memory 215624 kb
Host smart-ae6119c2-08a1-4a51-b558-28c0b25d29a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101233673 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.101233673
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.1920576332
Short name T659
Test name
Test status
Simulation time 158792757 ps
CPU time 2.35 seconds
Started Dec 31 12:53:50 PM PST 23
Finished Dec 31 12:54:04 PM PST 23
Peak memory 214076 kb
Host smart-6a518dcd-dfdf-4dfc-b36f-738a800285b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920576332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.1920576332
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.4008577820
Short name T79
Test name
Test status
Simulation time 79175473 ps
CPU time 1 seconds
Started Dec 31 12:54:07 PM PST 23
Finished Dec 31 12:54:14 PM PST 23
Peak memory 216796 kb
Host smart-b292284f-fbb6-4473-9558-ae1ee1102492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008577820 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.4008577820
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.2920927174
Short name T306
Test name
Test status
Simulation time 133200628 ps
CPU time 2.99 seconds
Started Dec 31 12:53:56 PM PST 23
Finished Dec 31 12:54:09 PM PST 23
Peak memory 214164 kb
Host smart-5606c924-d3f4-4093-8455-bee52e79b3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920927174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.2920927174
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.2723949539
Short name T828
Test name
Test status
Simulation time 67986724 ps
CPU time 1.14 seconds
Started Dec 31 12:53:48 PM PST 23
Finished Dec 31 12:54:01 PM PST 23
Peak memory 221740 kb
Host smart-140c58c6-be9f-4fef-ae85-9cf78fba13ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723949539 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.2723949539
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.524157811
Short name T810
Test name
Test status
Simulation time 19332095 ps
CPU time 1.02 seconds
Started Dec 31 12:53:53 PM PST 23
Finished Dec 31 12:54:05 PM PST 23
Peak memory 205212 kb
Host smart-6c60871d-e7ec-4ae5-a04b-4fa1d69f3268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524157811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.524157811
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.769722876
Short name T198
Test name
Test status
Simulation time 34555240 ps
CPU time 0.92 seconds
Started Dec 31 12:53:56 PM PST 23
Finished Dec 31 12:54:07 PM PST 23
Peak memory 214588 kb
Host smart-2fdbac49-a6f3-4ea2-9ddd-77a69f7e1c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769722876 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.769722876
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.1709821930
Short name T531
Test name
Test status
Simulation time 74917687 ps
CPU time 1.59 seconds
Started Dec 31 12:54:12 PM PST 23
Finished Dec 31 12:54:16 PM PST 23
Peak memory 214144 kb
Host smart-d308c999-e373-4ecc-a466-eedc71d27d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709821930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.1709821930
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.2880144081
Short name T945
Test name
Test status
Simulation time 23302786 ps
CPU time 0.89 seconds
Started Dec 31 12:54:05 PM PST 23
Finished Dec 31 12:54:13 PM PST 23
Peak memory 215788 kb
Host smart-bb394276-5d41-4a84-b24b-b1c0fa01a86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880144081 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.2880144081
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.1943386762
Short name T540
Test name
Test status
Simulation time 130868622 ps
CPU time 1.08 seconds
Started Dec 31 12:53:43 PM PST 23
Finished Dec 31 12:53:56 PM PST 23
Peak memory 214128 kb
Host smart-3b580f7a-673d-4aa4-9445-2ff253d54335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943386762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.1943386762
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.31898426
Short name T175
Test name
Test status
Simulation time 37377306 ps
CPU time 1.1 seconds
Started Dec 31 12:53:51 PM PST 23
Finished Dec 31 12:54:04 PM PST 23
Peak memory 228340 kb
Host smart-c1ac9160-3884-4953-9100-ed3cd3f08bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31898426 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.31898426
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.894253140
Short name T670
Test name
Test status
Simulation time 70743312 ps
CPU time 1.05 seconds
Started Dec 31 12:53:46 PM PST 23
Finished Dec 31 12:53:59 PM PST 23
Peak memory 205336 kb
Host smart-eded4f68-b2e2-449d-8ecc-c1610f9c3a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894253140 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.894253140
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.1602275671
Short name T132
Test name
Test status
Simulation time 72778038 ps
CPU time 0.91 seconds
Started Dec 31 12:53:59 PM PST 23
Finished Dec 31 12:54:09 PM PST 23
Peak memory 214616 kb
Host smart-67c8aaba-0824-42aa-8765-f8fb0c27ab29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602275671 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.1602275671
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.1870324479
Short name T963
Test name
Test status
Simulation time 15387418 ps
CPU time 0.95 seconds
Started Dec 31 12:53:45 PM PST 23
Finished Dec 31 12:53:58 PM PST 23
Peak memory 205536 kb
Host smart-a60e114d-e4ac-436e-84b1-a5da1c78a65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870324479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.1870324479
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.2442922880
Short name T974
Test name
Test status
Simulation time 24005898 ps
CPU time 0.95 seconds
Started Dec 31 12:53:34 PM PST 23
Finished Dec 31 12:53:47 PM PST 23
Peak memory 214548 kb
Host smart-725f1571-0891-428a-9afb-4af705905b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442922880 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.2442922880
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.321488974
Short name T589
Test name
Test status
Simulation time 14658826 ps
CPU time 1.04 seconds
Started Dec 31 12:54:13 PM PST 23
Finished Dec 31 12:54:17 PM PST 23
Peak memory 205628 kb
Host smart-88d216f0-4972-4d4b-b53b-cd4056656a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321488974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.321488974
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.3212322284
Short name T266
Test name
Test status
Simulation time 21705378 ps
CPU time 1.04 seconds
Started Dec 31 12:54:21 PM PST 23
Finished Dec 31 12:54:23 PM PST 23
Peak memory 214644 kb
Host smart-73f4d2f8-5b4e-4c89-9c62-23d1444c62e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212322284 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.3212322284
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.3132006858
Short name T290
Test name
Test status
Simulation time 18498215 ps
CPU time 1.15 seconds
Started Dec 31 12:53:37 PM PST 23
Finished Dec 31 12:53:50 PM PST 23
Peak memory 205628 kb
Host smart-2a769353-6543-4b99-9121-1f00f875c39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132006858 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.3132006858
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.3344264551
Short name T350
Test name
Test status
Simulation time 35935769 ps
CPU time 0.99 seconds
Started Dec 31 12:52:08 PM PST 23
Finished Dec 31 12:52:23 PM PST 23
Peak memory 205964 kb
Host smart-4a546efa-6706-49fe-83b9-9e036851ac03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344264551 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.3344264551
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.2622030126
Short name T503
Test name
Test status
Simulation time 37874240 ps
CPU time 0.82 seconds
Started Dec 31 12:52:13 PM PST 23
Finished Dec 31 12:52:29 PM PST 23
Peak memory 204328 kb
Host smart-dc8812c8-d1be-4839-842a-de44b77a1712
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622030126 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.2622030126
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.4262070240
Short name T227
Test name
Test status
Simulation time 16625497 ps
CPU time 0.8 seconds
Started Dec 31 12:52:17 PM PST 23
Finished Dec 31 12:52:31 PM PST 23
Peak memory 214308 kb
Host smart-90183052-a494-4a4c-91f0-b0208b643f33
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262070240 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.4262070240
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.3655606023
Short name T128
Test name
Test status
Simulation time 85926390 ps
CPU time 0.96 seconds
Started Dec 31 12:52:11 PM PST 23
Finished Dec 31 12:52:27 PM PST 23
Peak memory 206292 kb
Host smart-ef6f8227-9a01-481d-b569-d0829e8f2434
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655606023 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.3655606023
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.1303170095
Short name T586
Test name
Test status
Simulation time 18532193 ps
CPU time 1.41 seconds
Started Dec 31 12:52:09 PM PST 23
Finished Dec 31 12:52:25 PM PST 23
Peak memory 221732 kb
Host smart-802445fd-e085-4818-99ac-d175eacceff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303170095 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.1303170095
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.827696899
Short name T869
Test name
Test status
Simulation time 32037841 ps
CPU time 1.04 seconds
Started Dec 31 12:52:12 PM PST 23
Finished Dec 31 12:52:28 PM PST 23
Peak memory 205356 kb
Host smart-0e7431f8-59aa-4018-b490-7650bfa69f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827696899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.827696899
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.562849145
Short name T527
Test name
Test status
Simulation time 20449330 ps
CPU time 1.01 seconds
Started Dec 31 12:52:14 PM PST 23
Finished Dec 31 12:52:30 PM PST 23
Peak memory 214212 kb
Host smart-a4888bb3-77df-48d2-9ead-bff352310f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562849145 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.562849145
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.424541647
Short name T816
Test name
Test status
Simulation time 11589992 ps
CPU time 0.85 seconds
Started Dec 31 12:52:11 PM PST 23
Finished Dec 31 12:52:26 PM PST 23
Peak memory 204544 kb
Host smart-b3864d68-d32c-4380-9fc4-28f1307243bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424541647 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.424541647
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.2636811785
Short name T625
Test name
Test status
Simulation time 41257075 ps
CPU time 0.8 seconds
Started Dec 31 12:52:17 PM PST 23
Finished Dec 31 12:52:31 PM PST 23
Peak memory 204888 kb
Host smart-25751d8d-1e12-47b4-b325-83023425a039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636811785 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.2636811785
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.1110525066
Short name T973
Test name
Test status
Simulation time 110429918 ps
CPU time 1.66 seconds
Started Dec 31 12:52:19 PM PST 23
Finished Dec 31 12:52:34 PM PST 23
Peak memory 205512 kb
Host smart-988268d7-355c-4dce-a564-7be18af86084
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110525066 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.1110525066
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.2846962713
Short name T613
Test name
Test status
Simulation time 92734180437 ps
CPU time 713.23 seconds
Started Dec 31 12:52:12 PM PST 23
Finished Dec 31 01:04:20 PM PST 23
Peak memory 215716 kb
Host smart-72831437-3bb6-474d-8284-3446fd081edd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846962713 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.2846962713
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.1246922371
Short name T532
Test name
Test status
Simulation time 31641467 ps
CPU time 0.98 seconds
Started Dec 31 12:53:46 PM PST 23
Finished Dec 31 12:54:00 PM PST 23
Peak memory 221664 kb
Host smart-0d37f921-4198-439c-91fa-f7f7a73a6b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246922371 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.1246922371
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/81.edn_err.1797105578
Short name T179
Test name
Test status
Simulation time 21489304 ps
CPU time 1.05 seconds
Started Dec 31 12:53:55 PM PST 23
Finished Dec 31 12:54:07 PM PST 23
Peak memory 214608 kb
Host smart-c0f43158-993d-4c0d-9c46-6d01fca234a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797105578 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.1797105578
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.4112682636
Short name T697
Test name
Test status
Simulation time 42295776 ps
CPU time 1.9 seconds
Started Dec 31 12:53:58 PM PST 23
Finished Dec 31 12:54:10 PM PST 23
Peak memory 214060 kb
Host smart-947f302d-e4f2-4c86-9535-5ef3d2b683ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112682636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.4112682636
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_genbits.1715245604
Short name T375
Test name
Test status
Simulation time 17348448 ps
CPU time 1.04 seconds
Started Dec 31 12:53:52 PM PST 23
Finished Dec 31 12:54:04 PM PST 23
Peak memory 214112 kb
Host smart-b3d86af0-d3f4-4131-9627-f87aa3055229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715245604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.1715245604
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.1728833895
Short name T34
Test name
Test status
Simulation time 30113842 ps
CPU time 0.84 seconds
Started Dec 31 12:54:06 PM PST 23
Finished Dec 31 12:54:13 PM PST 23
Peak memory 215548 kb
Host smart-5d28d9b4-1e5c-4dd6-b11c-4f640e6f7b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728833895 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.1728833895
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.2392998702
Short name T698
Test name
Test status
Simulation time 93602749 ps
CPU time 0.93 seconds
Started Dec 31 12:53:43 PM PST 23
Finished Dec 31 12:53:56 PM PST 23
Peak memory 204804 kb
Host smart-3b1d0a2a-5080-4303-89c4-c0ebb3d7e276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392998702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.2392998702
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.3127858842
Short name T521
Test name
Test status
Simulation time 32041875 ps
CPU time 1.02 seconds
Started Dec 31 12:53:41 PM PST 23
Finished Dec 31 12:53:53 PM PST 23
Peak memory 215872 kb
Host smart-9aa0edcd-0c63-4e34-8665-a24d702214bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127858842 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.3127858842
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.3228034257
Short name T90
Test name
Test status
Simulation time 42468452 ps
CPU time 1.12 seconds
Started Dec 31 12:54:21 PM PST 23
Finished Dec 31 12:54:28 PM PST 23
Peak memory 205544 kb
Host smart-a28a8a31-2496-47e5-ba76-b71493fe5ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228034257 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.3228034257
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.248178161
Short name T765
Test name
Test status
Simulation time 22523245 ps
CPU time 0.93 seconds
Started Dec 31 12:54:19 PM PST 23
Finished Dec 31 12:54:22 PM PST 23
Peak memory 215836 kb
Host smart-342a10a3-a7ce-4b2d-922f-cf8816d3384d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248178161 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.248178161
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.3512089345
Short name T61
Test name
Test status
Simulation time 44067294 ps
CPU time 1.12 seconds
Started Dec 31 12:53:37 PM PST 23
Finished Dec 31 12:53:51 PM PST 23
Peak memory 214092 kb
Host smart-5a7943e8-8c4d-460c-add5-94144279fb7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512089345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.3512089345
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.2151139986
Short name T940
Test name
Test status
Simulation time 22936962 ps
CPU time 1.1 seconds
Started Dec 31 12:53:48 PM PST 23
Finished Dec 31 12:54:01 PM PST 23
Peak memory 214676 kb
Host smart-0d878011-dcba-4da2-aa72-812cebc38f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151139986 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.2151139986
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.894632874
Short name T741
Test name
Test status
Simulation time 35183803 ps
CPU time 1.04 seconds
Started Dec 31 12:53:31 PM PST 23
Finished Dec 31 12:53:44 PM PST 23
Peak memory 214132 kb
Host smart-2db76ee1-aa37-45f8-a678-88b7dce43774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894632874 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.894632874
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.4106807166
Short name T183
Test name
Test status
Simulation time 23761239 ps
CPU time 1.11 seconds
Started Dec 31 12:54:21 PM PST 23
Finished Dec 31 12:54:23 PM PST 23
Peak memory 214604 kb
Host smart-76004b36-8dfe-4e6a-939d-2d05d9a49fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106807166 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.4106807166
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.3836618808
Short name T863
Test name
Test status
Simulation time 47720103 ps
CPU time 0.99 seconds
Started Dec 31 12:53:45 PM PST 23
Finished Dec 31 12:53:59 PM PST 23
Peak memory 205004 kb
Host smart-07e2486c-3ac1-4d4c-b11f-4dfd6054e7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836618808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.3836618808
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.1701518759
Short name T750
Test name
Test status
Simulation time 49582983 ps
CPU time 1.04 seconds
Started Dec 31 12:54:38 PM PST 23
Finished Dec 31 12:54:41 PM PST 23
Peak memory 228320 kb
Host smart-7ba3dfff-2256-4ff9-872f-069362766093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701518759 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.1701518759
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.4018611131
Short name T376
Test name
Test status
Simulation time 193042119 ps
CPU time 1.75 seconds
Started Dec 31 12:54:18 PM PST 23
Finished Dec 31 12:54:22 PM PST 23
Peak memory 214164 kb
Host smart-7be4598b-b8e2-4057-8b3c-e9420eb10ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018611131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.4018611131
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.1587596073
Short name T194
Test name
Test status
Simulation time 22709986 ps
CPU time 1.12 seconds
Started Dec 31 12:54:13 PM PST 23
Finished Dec 31 12:54:17 PM PST 23
Peak memory 214568 kb
Host smart-c5f7eeea-0b66-4d3c-97a6-8b91d9be3bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587596073 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.1587596073
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.3578513609
Short name T664
Test name
Test status
Simulation time 59117138 ps
CPU time 0.93 seconds
Started Dec 31 12:53:58 PM PST 23
Finished Dec 31 12:54:09 PM PST 23
Peak memory 205020 kb
Host smart-24c532b6-00ec-42c3-b715-d0446afe8c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578513609 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.3578513609
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.4183353391
Short name T276
Test name
Test status
Simulation time 18188833 ps
CPU time 0.92 seconds
Started Dec 31 12:52:16 PM PST 23
Finished Dec 31 12:52:31 PM PST 23
Peak memory 205036 kb
Host smart-81fda65e-a810-4e32-b9ad-3e5a40364c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183353391 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.4183353391
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.4229768614
Short name T546
Test name
Test status
Simulation time 32082424 ps
CPU time 0.87 seconds
Started Dec 31 12:52:09 PM PST 23
Finished Dec 31 12:52:24 PM PST 23
Peak memory 204568 kb
Host smart-25d7ac2a-0cf2-4093-a895-807714137898
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229768614 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.4229768614
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.1427678273
Short name T583
Test name
Test status
Simulation time 21503647 ps
CPU time 0.84 seconds
Started Dec 31 12:52:14 PM PST 23
Finished Dec 31 12:52:29 PM PST 23
Peak memory 214284 kb
Host smart-4511bf4f-a253-4ded-9c23-a46ffc719664
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427678273 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.1427678273
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.1338036121
Short name T679
Test name
Test status
Simulation time 39379189 ps
CPU time 0.99 seconds
Started Dec 31 12:52:12 PM PST 23
Finished Dec 31 12:52:28 PM PST 23
Peak memory 214488 kb
Host smart-a819d4bc-8e94-4ff0-83a5-53a1b8cc7ec5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338036121 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.1338036121
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.1637735014
Short name T210
Test name
Test status
Simulation time 28488062 ps
CPU time 1.03 seconds
Started Dec 31 12:52:19 PM PST 23
Finished Dec 31 12:52:34 PM PST 23
Peak memory 221580 kb
Host smart-b52d74a0-b21e-4dd1-8907-77442a16d68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637735014 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.1637735014
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.2122481272
Short name T338
Test name
Test status
Simulation time 41468701 ps
CPU time 0.91 seconds
Started Dec 31 12:52:10 PM PST 23
Finished Dec 31 12:52:25 PM PST 23
Peak memory 205812 kb
Host smart-3b0c6c1e-57c0-4694-a268-af947258f2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122481272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.2122481272
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.922220838
Short name T598
Test name
Test status
Simulation time 28449982 ps
CPU time 0.89 seconds
Started Dec 31 12:52:12 PM PST 23
Finished Dec 31 12:52:28 PM PST 23
Peak memory 214212 kb
Host smart-bca6f094-2db0-4ded-b5d9-5f0becf4cf23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922220838 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.922220838
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.380460025
Short name T898
Test name
Test status
Simulation time 13098738 ps
CPU time 0.95 seconds
Started Dec 31 12:52:10 PM PST 23
Finished Dec 31 12:52:25 PM PST 23
Peak memory 204872 kb
Host smart-0e13aca6-567e-47a5-b3c0-9c9ad1e0485f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380460025 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.380460025
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.2929328874
Short name T497
Test name
Test status
Simulation time 48211431 ps
CPU time 0.89 seconds
Started Dec 31 12:52:18 PM PST 23
Finished Dec 31 12:52:32 PM PST 23
Peak memory 204372 kb
Host smart-661afca7-8dc8-4ce7-8765-95b51a6ab669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929328874 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.2929328874
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.814040785
Short name T917
Test name
Test status
Simulation time 325300211 ps
CPU time 3.46 seconds
Started Dec 31 12:52:13 PM PST 23
Finished Dec 31 12:52:31 PM PST 23
Peak memory 214100 kb
Host smart-6a7d39cd-f6a8-400c-ac54-683c9af3b8ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814040785 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.814040785
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.2816544977
Short name T680
Test name
Test status
Simulation time 203330867464 ps
CPU time 820.05 seconds
Started Dec 31 12:52:17 PM PST 23
Finished Dec 31 01:06:11 PM PST 23
Peak memory 215604 kb
Host smart-b2273e88-1f3f-4e44-a6eb-d12884ade283
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816544977 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.2816544977
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.3082354563
Short name T821
Test name
Test status
Simulation time 56262022 ps
CPU time 0.8 seconds
Started Dec 31 12:54:27 PM PST 23
Finished Dec 31 12:54:29 PM PST 23
Peak memory 215504 kb
Host smart-19a77987-7a9e-4ea2-9d5a-0788af518d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082354563 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.3082354563
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.1700731382
Short name T859
Test name
Test status
Simulation time 240462754 ps
CPU time 3.56 seconds
Started Dec 31 12:54:45 PM PST 23
Finished Dec 31 12:54:51 PM PST 23
Peak memory 214160 kb
Host smart-66f0603c-b089-490b-91f5-f2dc0e217429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700731382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.1700731382
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.4125867064
Short name T96
Test name
Test status
Simulation time 25149168 ps
CPU time 0.94 seconds
Started Dec 31 12:53:54 PM PST 23
Finished Dec 31 12:54:06 PM PST 23
Peak memory 214392 kb
Host smart-aa64a2b3-2bd2-4305-8fd7-74d6cf517879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125867064 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.4125867064
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.624552885
Short name T576
Test name
Test status
Simulation time 145708881 ps
CPU time 1.36 seconds
Started Dec 31 12:53:54 PM PST 23
Finished Dec 31 12:54:06 PM PST 23
Peak memory 214132 kb
Host smart-a4b6e4be-da8f-40ca-b6b0-2ef59549062c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624552885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.624552885
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.2884712559
Short name T206
Test name
Test status
Simulation time 21090544 ps
CPU time 0.93 seconds
Started Dec 31 12:53:57 PM PST 23
Finished Dec 31 12:54:08 PM PST 23
Peak memory 215696 kb
Host smart-8faed351-3f73-4cd3-9f0a-a6e76f417cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884712559 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.2884712559
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.1373737707
Short name T610
Test name
Test status
Simulation time 32359396 ps
CPU time 0.94 seconds
Started Dec 31 12:53:52 PM PST 23
Finished Dec 31 12:54:04 PM PST 23
Peak memory 205028 kb
Host smart-1c4abe82-0682-4874-a940-21b1a59d7bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373737707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.1373737707
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.1049332428
Short name T67
Test name
Test status
Simulation time 126167618 ps
CPU time 1.06 seconds
Started Dec 31 12:53:35 PM PST 23
Finished Dec 31 12:53:49 PM PST 23
Peak memory 228436 kb
Host smart-6cfa02e8-6672-4f2f-ac0c-f664ad8cbf2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049332428 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.1049332428
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.3669088459
Short name T607
Test name
Test status
Simulation time 31274413 ps
CPU time 1.1 seconds
Started Dec 31 12:53:56 PM PST 23
Finished Dec 31 12:54:07 PM PST 23
Peak memory 214168 kb
Host smart-a919d5f3-9f14-4426-a36d-e3f017894fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669088459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.3669088459
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.1297360354
Short name T207
Test name
Test status
Simulation time 32725000 ps
CPU time 0.82 seconds
Started Dec 31 12:54:09 PM PST 23
Finished Dec 31 12:54:15 PM PST 23
Peak memory 215612 kb
Host smart-56cb6157-04aa-4eef-a818-90af5c8069cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297360354 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.1297360354
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.2633537199
Short name T574
Test name
Test status
Simulation time 24535142 ps
CPU time 0.94 seconds
Started Dec 31 12:54:34 PM PST 23
Finished Dec 31 12:54:36 PM PST 23
Peak memory 205348 kb
Host smart-81d72301-40e1-4e0b-8980-7e9c68563649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633537199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.2633537199
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.2095366078
Short name T251
Test name
Test status
Simulation time 26100032 ps
CPU time 1.01 seconds
Started Dec 31 12:54:32 PM PST 23
Finished Dec 31 12:54:38 PM PST 23
Peak memory 228172 kb
Host smart-926a8896-77b1-4c6a-927b-d03613331961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095366078 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.2095366078
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.2688011744
Short name T581
Test name
Test status
Simulation time 61884134 ps
CPU time 0.97 seconds
Started Dec 31 12:54:28 PM PST 23
Finished Dec 31 12:54:30 PM PST 23
Peak memory 205372 kb
Host smart-e636beb7-6883-4ba2-b4c6-d11e9297948b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688011744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.2688011744
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.2103054525
Short name T217
Test name
Test status
Simulation time 18836456 ps
CPU time 0.95 seconds
Started Dec 31 12:54:05 PM PST 23
Finished Dec 31 12:54:13 PM PST 23
Peak memory 215624 kb
Host smart-31de8178-6435-4ada-b902-b99fb1ad40e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103054525 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.2103054525
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.2417194748
Short name T727
Test name
Test status
Simulation time 34045148 ps
CPU time 1.04 seconds
Started Dec 31 12:55:06 PM PST 23
Finished Dec 31 12:55:13 PM PST 23
Peak memory 205284 kb
Host smart-78d5f64d-89e4-4074-94ea-761551171a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417194748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.2417194748
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.1842114792
Short name T844
Test name
Test status
Simulation time 41369809 ps
CPU time 0.88 seconds
Started Dec 31 12:54:18 PM PST 23
Finished Dec 31 12:54:21 PM PST 23
Peak memory 214864 kb
Host smart-951ef6b2-3e43-4c32-9dea-694b525b6706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842114792 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.1842114792
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.1490765959
Short name T961
Test name
Test status
Simulation time 20258087 ps
CPU time 0.98 seconds
Started Dec 31 12:54:14 PM PST 23
Finished Dec 31 12:54:18 PM PST 23
Peak memory 205256 kb
Host smart-d32e3c15-c241-44d9-9497-2118e82c5825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490765959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.1490765959
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.1153850
Short name T218
Test name
Test status
Simulation time 46538806 ps
CPU time 0.78 seconds
Started Dec 31 12:54:27 PM PST 23
Finished Dec 31 12:54:30 PM PST 23
Peak memory 215276 kb
Host smart-b6cfd212-f6f1-4c6d-8c3c-00c6d523e050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153850 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.1153850
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.3313199365
Short name T746
Test name
Test status
Simulation time 46087617 ps
CPU time 0.96 seconds
Started Dec 31 12:54:46 PM PST 23
Finished Dec 31 12:54:50 PM PST 23
Peak memory 205536 kb
Host smart-511af1d2-642d-4baa-b855-b25f00cc0540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313199365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.3313199365
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.3884406852
Short name T209
Test name
Test status
Simulation time 26733475 ps
CPU time 0.94 seconds
Started Dec 31 12:55:15 PM PST 23
Finished Dec 31 12:55:22 PM PST 23
Peak memory 221624 kb
Host smart-cb1f42cb-79e4-46e1-a415-5a65ecdfb94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884406852 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.3884406852
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.3089700485
Short name T818
Test name
Test status
Simulation time 16499930 ps
CPU time 1.06 seconds
Started Dec 31 12:53:54 PM PST 23
Finished Dec 31 12:54:06 PM PST 23
Peak memory 205704 kb
Host smart-dc112dcf-aa49-4af6-a9c5-58a330c7a7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089700485 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.3089700485
Directory /workspace/99.edn_genbits/latest
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