Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.06 99.02 92.32 96.84 93.42 98.62 99.77 99.40


Total test records in report: 939
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T766 /workspace/coverage/default/15.edn_alert_test.1490156621 Jan 03 12:45:45 PM PST 24 Jan 03 12:47:14 PM PST 24 40289771 ps
T767 /workspace/coverage/default/121.edn_genbits.2745686017 Jan 03 12:47:02 PM PST 24 Jan 03 12:48:04 PM PST 24 35919275 ps
T768 /workspace/coverage/default/37.edn_disable.3526607744 Jan 03 12:46:06 PM PST 24 Jan 03 12:47:36 PM PST 24 10911479 ps
T769 /workspace/coverage/default/40.edn_intr.3487815267 Jan 03 12:45:58 PM PST 24 Jan 03 12:47:32 PM PST 24 26533162 ps
T770 /workspace/coverage/default/16.edn_smoke.2077045086 Jan 03 12:46:03 PM PST 24 Jan 03 12:47:27 PM PST 24 12914026 ps
T771 /workspace/coverage/default/3.edn_alert.108669688 Jan 03 12:45:01 PM PST 24 Jan 03 12:46:35 PM PST 24 18677407 ps
T772 /workspace/coverage/default/13.edn_smoke.383719110 Jan 03 12:45:07 PM PST 24 Jan 03 12:46:41 PM PST 24 35713495 ps
T773 /workspace/coverage/default/4.edn_intr.1566118500 Jan 03 12:45:11 PM PST 24 Jan 03 12:46:48 PM PST 24 24703942 ps
T774 /workspace/coverage/default/8.edn_smoke.2753928122 Jan 03 12:45:45 PM PST 24 Jan 03 12:47:14 PM PST 24 27644801 ps
T775 /workspace/coverage/default/18.edn_disable.1667165486 Jan 03 12:46:06 PM PST 24 Jan 03 12:47:37 PM PST 24 33833152 ps
T776 /workspace/coverage/default/241.edn_genbits.810128484 Jan 03 12:47:23 PM PST 24 Jan 03 12:48:14 PM PST 24 30189532 ps
T777 /workspace/coverage/default/289.edn_genbits.3556488843 Jan 03 12:48:17 PM PST 24 Jan 03 12:48:44 PM PST 24 44448560 ps
T778 /workspace/coverage/default/48.edn_smoke.34895011 Jan 03 12:46:42 PM PST 24 Jan 03 12:47:53 PM PST 24 13579650 ps
T779 /workspace/coverage/default/36.edn_alert_test.865494152 Jan 03 12:45:53 PM PST 24 Jan 03 12:47:18 PM PST 24 48454569 ps
T780 /workspace/coverage/default/29.edn_alert_test.1567072975 Jan 03 12:45:57 PM PST 24 Jan 03 12:47:30 PM PST 24 40852889 ps
T219 /workspace/coverage/default/29.edn_alert.1010436204 Jan 03 12:45:35 PM PST 24 Jan 03 12:47:07 PM PST 24 19231066 ps
T781 /workspace/coverage/default/25.edn_smoke.3371609777 Jan 03 12:45:38 PM PST 24 Jan 03 12:47:15 PM PST 24 20517714 ps
T123 /workspace/coverage/default/23.edn_disable.2390647048 Jan 03 12:45:46 PM PST 24 Jan 03 12:47:11 PM PST 24 13518167 ps
T782 /workspace/coverage/default/127.edn_genbits.2318167381 Jan 03 12:47:06 PM PST 24 Jan 03 12:48:06 PM PST 24 21167759 ps
T783 /workspace/coverage/default/290.edn_genbits.1560091848 Jan 03 12:48:09 PM PST 24 Jan 03 12:48:38 PM PST 24 18469538 ps
T784 /workspace/coverage/default/16.edn_intr.3513677786 Jan 03 12:45:47 PM PST 24 Jan 03 12:47:15 PM PST 24 19097593 ps
T785 /workspace/coverage/default/9.edn_intr.2976968552 Jan 03 12:45:29 PM PST 24 Jan 03 12:46:59 PM PST 24 21599581 ps
T227 /workspace/coverage/default/18.edn_alert.2240717667 Jan 03 12:45:42 PM PST 24 Jan 03 12:47:22 PM PST 24 23767946 ps
T786 /workspace/coverage/default/14.edn_stress_all.2238123464 Jan 03 12:45:46 PM PST 24 Jan 03 12:47:23 PM PST 24 138586868 ps
T787 /workspace/coverage/default/98.edn_err.3619606100 Jan 03 12:46:26 PM PST 24 Jan 03 12:47:55 PM PST 24 18096041 ps
T788 /workspace/coverage/default/33.edn_stress_all.2893855415 Jan 03 12:45:45 PM PST 24 Jan 03 12:47:15 PM PST 24 21351244 ps
T789 /workspace/coverage/default/39.edn_err.1926883995 Jan 03 12:46:43 PM PST 24 Jan 03 12:47:54 PM PST 24 30396822 ps
T790 /workspace/coverage/default/3.edn_smoke.2288004903 Jan 03 12:45:13 PM PST 24 Jan 03 12:46:47 PM PST 24 27332219 ps
T791 /workspace/coverage/default/38.edn_disable.2066308398 Jan 03 12:45:55 PM PST 24 Jan 03 12:47:44 PM PST 24 10837010 ps
T792 /workspace/coverage/default/26.edn_stress_all_with_rand_reset.3368425096 Jan 03 12:46:06 PM PST 24 Jan 03 12:52:05 PM PST 24 51812615246 ps
T793 /workspace/coverage/default/27.edn_stress_all.395948525 Jan 03 12:46:00 PM PST 24 Jan 03 12:47:27 PM PST 24 857354466 ps
T794 /workspace/coverage/default/141.edn_genbits.1243434565 Jan 03 12:47:19 PM PST 24 Jan 03 12:48:13 PM PST 24 70868315 ps
T795 /workspace/coverage/default/16.edn_disable_auto_req_mode.1123309939 Jan 03 12:45:37 PM PST 24 Jan 03 12:47:41 PM PST 24 51927595 ps
T796 /workspace/coverage/default/4.edn_smoke.592599319 Jan 03 12:45:05 PM PST 24 Jan 03 12:46:35 PM PST 24 20652507 ps
T797 /workspace/coverage/default/31.edn_intr.3498000743 Jan 03 12:45:48 PM PST 24 Jan 03 12:47:30 PM PST 24 18613436 ps
T798 /workspace/coverage/default/43.edn_smoke.1568081649 Jan 03 12:46:01 PM PST 24 Jan 03 12:47:27 PM PST 24 17339796 ps
T799 /workspace/coverage/default/9.edn_alert.1412843391 Jan 03 12:45:07 PM PST 24 Jan 03 12:46:40 PM PST 24 33467399 ps
T800 /workspace/coverage/default/40.edn_smoke.2707186692 Jan 03 12:46:11 PM PST 24 Jan 03 12:47:33 PM PST 24 15377706 ps
T801 /workspace/coverage/default/30.edn_alert.3868592366 Jan 03 12:45:43 PM PST 24 Jan 03 12:47:28 PM PST 24 60132923 ps
T802 /workspace/coverage/default/0.edn_stress_all.4220935345 Jan 03 12:44:53 PM PST 24 Jan 03 12:46:27 PM PST 24 48741768 ps
T803 /workspace/coverage/default/38.edn_stress_all.3756215856 Jan 03 12:46:06 PM PST 24 Jan 03 12:47:41 PM PST 24 157457652 ps
T804 /workspace/coverage/default/38.edn_intr.1101843287 Jan 03 12:46:01 PM PST 24 Jan 03 12:47:41 PM PST 24 39935035 ps
T805 /workspace/coverage/default/102.edn_genbits.3743294299 Jan 03 12:46:26 PM PST 24 Jan 03 12:47:50 PM PST 24 40005398 ps
T806 /workspace/coverage/default/2.edn_intr.4110554257 Jan 03 12:45:02 PM PST 24 Jan 03 12:46:54 PM PST 24 18456404 ps
T807 /workspace/coverage/default/42.edn_alert.3443354307 Jan 03 12:46:03 PM PST 24 Jan 03 12:47:29 PM PST 24 17801609 ps
T808 /workspace/coverage/default/65.edn_err.365882786 Jan 03 12:46:27 PM PST 24 Jan 03 12:47:45 PM PST 24 24037089 ps
T809 /workspace/coverage/default/57.edn_genbits.2216041763 Jan 03 12:47:01 PM PST 24 Jan 03 12:48:03 PM PST 24 70502063 ps
T810 /workspace/coverage/default/34.edn_disable_auto_req_mode.3431689014 Jan 03 12:46:32 PM PST 24 Jan 03 12:47:49 PM PST 24 25997064 ps
T811 /workspace/coverage/default/25.edn_stress_all.3649224621 Jan 03 12:45:30 PM PST 24 Jan 03 12:47:11 PM PST 24 198763270 ps
T812 /workspace/coverage/default/12.edn_alert_test.4152618606 Jan 03 12:44:58 PM PST 24 Jan 03 12:46:32 PM PST 24 37129714 ps
T813 /workspace/coverage/default/6.edn_regwen.3769456625 Jan 03 12:45:10 PM PST 24 Jan 03 12:46:44 PM PST 24 22175469 ps
T814 /workspace/coverage/default/72.edn_genbits.3288605225 Jan 03 12:46:52 PM PST 24 Jan 03 12:48:00 PM PST 24 62005380 ps
T815 /workspace/coverage/default/242.edn_genbits.2923517889 Jan 03 12:47:34 PM PST 24 Jan 03 12:48:20 PM PST 24 79289256 ps
T816 /workspace/coverage/default/40.edn_err.266354617 Jan 03 12:46:00 PM PST 24 Jan 03 12:47:25 PM PST 24 33770102 ps
T817 /workspace/coverage/default/103.edn_genbits.3203377975 Jan 03 12:46:31 PM PST 24 Jan 03 12:47:50 PM PST 24 29901743 ps
T818 /workspace/coverage/default/11.edn_smoke.2750183617 Jan 03 12:45:09 PM PST 24 Jan 03 12:46:44 PM PST 24 12597583 ps
T819 /workspace/coverage/default/12.edn_err.3758660144 Jan 03 12:44:51 PM PST 24 Jan 03 12:46:30 PM PST 24 28289590 ps
T820 /workspace/coverage/default/46.edn_stress_all.1636448160 Jan 03 12:45:53 PM PST 24 Jan 03 12:47:19 PM PST 24 106802725 ps
T821 /workspace/coverage/default/41.edn_disable_auto_req_mode.1649048298 Jan 03 12:46:11 PM PST 24 Jan 03 12:47:33 PM PST 24 92364937 ps
T822 /workspace/coverage/default/52.edn_genbits.1201792265 Jan 03 12:46:19 PM PST 24 Jan 03 12:47:40 PM PST 24 14093137 ps
T823 /workspace/coverage/default/45.edn_stress_all.3091233203 Jan 03 12:45:50 PM PST 24 Jan 03 12:47:22 PM PST 24 683404440 ps
T824 /workspace/coverage/default/25.edn_alert_test.3128924968 Jan 03 12:45:54 PM PST 24 Jan 03 12:47:46 PM PST 24 49646382 ps
T251 /workspace/coverage/default/128.edn_genbits.479648648 Jan 03 12:47:05 PM PST 24 Jan 03 12:48:05 PM PST 24 165772488 ps
T825 /workspace/coverage/default/158.edn_genbits.19706421 Jan 03 12:47:20 PM PST 24 Jan 03 12:48:13 PM PST 24 87106482 ps
T826 /workspace/coverage/default/25.edn_intr.2776327582 Jan 03 12:45:30 PM PST 24 Jan 03 12:47:02 PM PST 24 33428443 ps
T827 /workspace/coverage/default/28.edn_err.1419757741 Jan 03 12:45:34 PM PST 24 Jan 03 12:47:46 PM PST 24 68781603 ps
T228 /workspace/coverage/default/19.edn_alert.3208657765 Jan 03 12:46:00 PM PST 24 Jan 03 12:47:40 PM PST 24 58178741 ps
T828 /workspace/coverage/default/47.edn_stress_all_with_rand_reset.4176951009 Jan 03 12:46:22 PM PST 24 Jan 03 01:02:02 PM PST 24 81404534022 ps
T829 /workspace/coverage/default/2.edn_stress_all_with_rand_reset.1976746875 Jan 03 12:45:11 PM PST 24 Jan 03 01:17:42 PM PST 24 144633716761 ps
T122 /workspace/coverage/default/34.edn_disable.341438111 Jan 03 12:46:32 PM PST 24 Jan 03 12:47:49 PM PST 24 11115091 ps
T830 /workspace/coverage/default/35.edn_stress_all.1751041733 Jan 03 12:45:50 PM PST 24 Jan 03 12:47:28 PM PST 24 314868818 ps
T831 /workspace/coverage/default/161.edn_genbits.1752806709 Jan 03 12:47:21 PM PST 24 Jan 03 12:48:13 PM PST 24 42321053 ps
T832 /workspace/coverage/default/134.edn_genbits.3814230334 Jan 03 12:47:19 PM PST 24 Jan 03 12:48:13 PM PST 24 65993040 ps
T833 /workspace/coverage/default/30.edn_genbits.2873040618 Jan 03 12:46:00 PM PST 24 Jan 03 12:47:24 PM PST 24 14812237 ps
T834 /workspace/coverage/default/32.edn_err.4132948455 Jan 03 12:45:35 PM PST 24 Jan 03 12:47:12 PM PST 24 20846794 ps
T835 /workspace/coverage/default/82.edn_err.2193182096 Jan 03 12:46:38 PM PST 24 Jan 03 12:47:50 PM PST 24 19790002 ps
T836 /workspace/coverage/default/49.edn_alert_test.4115512248 Jan 03 12:46:58 PM PST 24 Jan 03 12:48:01 PM PST 24 17882493 ps
T837 /workspace/coverage/default/14.edn_smoke.2972619188 Jan 03 12:45:46 PM PST 24 Jan 03 12:47:21 PM PST 24 21472081 ps
T838 /workspace/coverage/default/11.edn_stress_all_with_rand_reset.3649029071 Jan 03 12:45:29 PM PST 24 Jan 03 12:57:06 PM PST 24 26903879971 ps
T839 /workspace/coverage/default/49.edn_err.960637162 Jan 03 12:47:02 PM PST 24 Jan 03 12:48:04 PM PST 24 29440487 ps
T840 /workspace/coverage/default/25.edn_genbits.2346651165 Jan 03 12:45:29 PM PST 24 Jan 03 12:47:13 PM PST 24 28648803 ps
T841 /workspace/coverage/default/135.edn_genbits.2961297532 Jan 03 12:47:28 PM PST 24 Jan 03 12:48:16 PM PST 24 84099960 ps
T842 /workspace/coverage/default/150.edn_genbits.2715310632 Jan 03 12:47:19 PM PST 24 Jan 03 12:48:14 PM PST 24 64603400 ps
T258 /workspace/coverage/default/277.edn_genbits.1115918492 Jan 03 12:48:02 PM PST 24 Jan 03 12:48:35 PM PST 24 20184501 ps
T843 /workspace/coverage/default/26.edn_smoke.3128641259 Jan 03 12:45:44 PM PST 24 Jan 03 12:47:28 PM PST 24 69737337 ps
T844 /workspace/coverage/default/109.edn_genbits.1498157630 Jan 03 12:46:42 PM PST 24 Jan 03 12:47:53 PM PST 24 32657358 ps
T845 /workspace/coverage/default/223.edn_genbits.2587846212 Jan 03 12:47:29 PM PST 24 Jan 03 12:48:16 PM PST 24 17826215 ps
T846 /workspace/coverage/default/44.edn_alert.162696498 Jan 03 12:46:01 PM PST 24 Jan 03 12:47:27 PM PST 24 39353292 ps
T847 /workspace/coverage/default/261.edn_genbits.2714684045 Jan 03 12:48:10 PM PST 24 Jan 03 12:48:38 PM PST 24 20346247 ps
T848 /workspace/coverage/default/245.edn_genbits.3796165780 Jan 03 12:47:26 PM PST 24 Jan 03 12:48:15 PM PST 24 58405521 ps
T849 /workspace/coverage/default/143.edn_genbits.4107575967 Jan 03 12:47:22 PM PST 24 Jan 03 12:48:17 PM PST 24 261283147 ps
T850 /workspace/coverage/default/3.edn_stress_all.1320713892 Jan 03 12:45:22 PM PST 24 Jan 03 12:47:06 PM PST 24 301819463 ps
T851 /workspace/coverage/default/146.edn_genbits.1321884910 Jan 03 12:47:22 PM PST 24 Jan 03 12:48:13 PM PST 24 22942791 ps
T852 /workspace/coverage/default/118.edn_genbits.3431055297 Jan 03 12:47:04 PM PST 24 Jan 03 12:48:05 PM PST 24 23998867 ps
T853 /workspace/coverage/default/15.edn_stress_all_with_rand_reset.277281132 Jan 03 12:45:57 PM PST 24 Jan 03 01:05:51 PM PST 24 57919224067 ps
T854 /workspace/coverage/default/292.edn_genbits.2665182065 Jan 03 12:48:11 PM PST 24 Jan 03 12:48:39 PM PST 24 13499681 ps
T855 /workspace/coverage/default/69.edn_genbits.2587328082 Jan 03 12:46:57 PM PST 24 Jan 03 12:48:02 PM PST 24 74350431 ps
T856 /workspace/coverage/default/2.edn_disable_auto_req_mode.3386814639 Jan 03 12:44:37 PM PST 24 Jan 03 12:45:54 PM PST 24 81160652 ps
T857 /workspace/coverage/default/155.edn_genbits.3397678943 Jan 03 12:47:17 PM PST 24 Jan 03 12:48:12 PM PST 24 19910742 ps
T858 /workspace/coverage/default/9.edn_stress_all_with_rand_reset.2998917555 Jan 03 12:45:04 PM PST 24 Jan 03 12:55:54 PM PST 24 21266257167 ps
T859 /workspace/coverage/default/123.edn_genbits.1823221107 Jan 03 12:47:06 PM PST 24 Jan 03 12:48:06 PM PST 24 41724527 ps
T860 /workspace/coverage/default/76.edn_genbits.2541593719 Jan 03 12:46:38 PM PST 24 Jan 03 12:47:50 PM PST 24 28127492 ps
T861 /workspace/coverage/default/220.edn_genbits.3773531386 Jan 03 12:47:30 PM PST 24 Jan 03 12:48:17 PM PST 24 27111712 ps
T115 /workspace/coverage/default/92.edn_err.2362282204 Jan 03 12:46:57 PM PST 24 Jan 03 12:48:01 PM PST 24 63069306 ps
T862 /workspace/coverage/default/33.edn_alert.2040060595 Jan 03 12:45:51 PM PST 24 Jan 03 12:47:29 PM PST 24 19031314 ps
T863 /workspace/coverage/default/2.edn_smoke.4221436542 Jan 03 12:44:46 PM PST 24 Jan 03 12:46:09 PM PST 24 38940646 ps
T101 /workspace/coverage/default/21.edn_intr.436774058 Jan 03 12:45:57 PM PST 24 Jan 03 12:47:41 PM PST 24 20452166 ps
T864 /workspace/coverage/default/113.edn_genbits.268992486 Jan 03 12:47:04 PM PST 24 Jan 03 12:48:05 PM PST 24 69454451 ps
T865 /workspace/coverage/default/47.edn_stress_all.1486136322 Jan 03 12:46:32 PM PST 24 Jan 03 12:47:48 PM PST 24 122296118 ps
T866 /workspace/coverage/default/9.edn_err.1287986459 Jan 03 12:45:49 PM PST 24 Jan 03 12:47:28 PM PST 24 21901641 ps
T867 /workspace/coverage/default/45.edn_err.2787378856 Jan 03 12:46:32 PM PST 24 Jan 03 12:47:48 PM PST 24 26699987 ps
T868 /workspace/coverage/default/230.edn_genbits.2259164853 Jan 03 12:47:19 PM PST 24 Jan 03 12:48:12 PM PST 24 31321974 ps
T869 /workspace/coverage/default/259.edn_genbits.3224281084 Jan 03 12:48:07 PM PST 24 Jan 03 12:48:37 PM PST 24 31974553 ps
T870 /workspace/coverage/default/278.edn_genbits.446679736 Jan 03 12:48:01 PM PST 24 Jan 03 12:48:34 PM PST 24 21292640 ps
T871 /workspace/coverage/default/43.edn_disable_auto_req_mode.1600095053 Jan 03 12:46:05 PM PST 24 Jan 03 12:47:30 PM PST 24 14153095 ps
T872 /workspace/coverage/default/49.edn_genbits.3475104888 Jan 03 12:46:56 PM PST 24 Jan 03 12:48:01 PM PST 24 20932632 ps
T873 /workspace/coverage/default/148.edn_genbits.4006323331 Jan 03 12:47:19 PM PST 24 Jan 03 12:48:12 PM PST 24 23001916 ps
T874 /workspace/coverage/default/13.edn_disable.193769239 Jan 03 12:45:25 PM PST 24 Jan 03 12:47:15 PM PST 24 11266670 ps
T875 /workspace/coverage/default/31.edn_alert.331251459 Jan 03 12:45:45 PM PST 24 Jan 03 12:47:43 PM PST 24 53423268 ps
T876 /workspace/coverage/default/36.edn_err.3807781617 Jan 03 12:45:47 PM PST 24 Jan 03 12:47:19 PM PST 24 24830585 ps
T877 /workspace/coverage/default/42.edn_intr.3262493736 Jan 03 12:45:53 PM PST 24 Jan 03 12:47:32 PM PST 24 23607381 ps
T878 /workspace/coverage/default/41.edn_intr.4261022434 Jan 03 12:45:48 PM PST 24 Jan 03 12:47:44 PM PST 24 20138288 ps
T879 /workspace/coverage/default/183.edn_genbits.2790830247 Jan 03 12:47:27 PM PST 24 Jan 03 12:48:15 PM PST 24 50746879 ps
T880 /workspace/coverage/default/32.edn_disable.934804405 Jan 03 12:46:03 PM PST 24 Jan 03 12:47:28 PM PST 24 25995780 ps
T881 /workspace/coverage/default/217.edn_genbits.2484881772 Jan 03 12:47:30 PM PST 24 Jan 03 12:48:16 PM PST 24 13083165 ps
T882 /workspace/coverage/default/201.edn_genbits.3110718617 Jan 03 12:47:27 PM PST 24 Jan 03 12:48:16 PM PST 24 112379196 ps
T883 /workspace/coverage/default/97.edn_genbits.969608795 Jan 03 12:46:59 PM PST 24 Jan 03 12:48:02 PM PST 24 15851608 ps
T884 /workspace/coverage/default/19.edn_smoke.1312264662 Jan 03 12:45:34 PM PST 24 Jan 03 12:47:06 PM PST 24 18385597 ps
T885 /workspace/coverage/default/171.edn_genbits.2829358937 Jan 03 12:47:24 PM PST 24 Jan 03 12:48:14 PM PST 24 50873100 ps
T886 /workspace/coverage/default/47.edn_err.2385615685 Jan 03 12:46:27 PM PST 24 Jan 03 12:47:43 PM PST 24 20252709 ps
T887 /workspace/coverage/default/26.edn_err.1410423693 Jan 03 12:45:11 PM PST 24 Jan 03 12:46:47 PM PST 24 23542051 ps
T888 /workspace/coverage/default/2.edn_genbits.1134001442 Jan 03 12:44:56 PM PST 24 Jan 03 12:46:28 PM PST 24 14722272 ps
T889 /workspace/coverage/default/34.edn_stress_all_with_rand_reset.2272628697 Jan 03 12:45:53 PM PST 24 Jan 03 12:59:37 PM PST 24 31184167743 ps
T890 /workspace/coverage/default/10.edn_genbits.1620606894 Jan 03 12:45:38 PM PST 24 Jan 03 12:47:19 PM PST 24 23978997 ps
T891 /workspace/coverage/default/80.edn_genbits.2662752357 Jan 03 12:46:36 PM PST 24 Jan 03 12:47:49 PM PST 24 102236855 ps
T892 /workspace/coverage/default/44.edn_alert_test.262107503 Jan 03 12:45:46 PM PST 24 Jan 03 12:47:15 PM PST 24 16117014 ps
T893 /workspace/coverage/default/42.edn_stress_all.1742589241 Jan 03 12:45:57 PM PST 24 Jan 03 12:47:41 PM PST 24 364724268 ps
T894 /workspace/coverage/default/50.edn_genbits.1371524373 Jan 03 12:46:55 PM PST 24 Jan 03 12:48:01 PM PST 24 16481811 ps
T895 /workspace/coverage/default/1.edn_disable_auto_req_mode.54391395 Jan 03 12:45:25 PM PST 24 Jan 03 12:47:04 PM PST 24 19756186 ps
T896 /workspace/coverage/default/41.edn_alert.1313764770 Jan 03 12:46:11 PM PST 24 Jan 03 12:47:34 PM PST 24 20667938 ps
T220 /workspace/coverage/default/20.edn_alert.1016846712 Jan 03 12:45:27 PM PST 24 Jan 03 12:46:55 PM PST 24 25307422 ps
T897 /workspace/coverage/default/89.edn_genbits.2478004215 Jan 03 12:46:45 PM PST 24 Jan 03 12:47:55 PM PST 24 99731152 ps
T898 /workspace/coverage/default/18.edn_err.3027860219 Jan 03 12:45:56 PM PST 24 Jan 03 12:47:20 PM PST 24 19336664 ps
T899 /workspace/coverage/default/24.edn_alert_test.2177642286 Jan 03 12:45:38 PM PST 24 Jan 03 12:47:18 PM PST 24 47908360 ps
T900 /workspace/coverage/default/45.edn_disable_auto_req_mode.3136582598 Jan 03 12:46:02 PM PST 24 Jan 03 12:47:33 PM PST 24 84891460 ps
T901 /workspace/coverage/default/238.edn_genbits.772800447 Jan 03 12:47:27 PM PST 24 Jan 03 12:48:17 PM PST 24 46332281 ps
T902 /workspace/coverage/default/66.edn_genbits.3203343026 Jan 03 12:46:23 PM PST 24 Jan 03 12:47:41 PM PST 24 15216795 ps
T903 /workspace/coverage/default/228.edn_genbits.4218435622 Jan 03 12:47:27 PM PST 24 Jan 03 12:48:16 PM PST 24 159862089 ps
T252 /workspace/coverage/default/144.edn_genbits.1078589713 Jan 03 12:47:16 PM PST 24 Jan 03 12:48:11 PM PST 24 72136405 ps
T904 /workspace/coverage/default/213.edn_genbits.2402140406 Jan 03 12:47:32 PM PST 24 Jan 03 12:48:17 PM PST 24 24231344 ps
T905 /workspace/coverage/default/86.edn_genbits.960822896 Jan 03 12:46:27 PM PST 24 Jan 03 12:47:46 PM PST 24 114533315 ps
T906 /workspace/coverage/default/24.edn_disable_auto_req_mode.2212339664 Jan 03 12:45:20 PM PST 24 Jan 03 12:47:07 PM PST 24 16326394 ps
T907 /workspace/coverage/default/11.edn_err.1672430679 Jan 03 12:45:36 PM PST 24 Jan 03 12:47:16 PM PST 24 25456044 ps
T908 /workspace/coverage/default/30.edn_disable_auto_req_mode.2810671386 Jan 03 12:46:29 PM PST 24 Jan 03 12:47:51 PM PST 24 188982106 ps
T909 /workspace/coverage/default/40.edn_stress_all_with_rand_reset.3119528939 Jan 03 12:46:08 PM PST 24 Jan 03 01:04:35 PM PST 24 146255694995 ps
T910 /workspace/coverage/default/268.edn_genbits.1852710922 Jan 03 12:48:25 PM PST 24 Jan 03 12:48:49 PM PST 24 15044962 ps
T911 /workspace/coverage/default/20.edn_stress_all_with_rand_reset.2085203095 Jan 03 12:45:54 PM PST 24 Jan 03 01:08:46 PM PST 24 232815062774 ps
T912 /workspace/coverage/default/26.edn_disable_auto_req_mode.2658660083 Jan 03 12:46:05 PM PST 24 Jan 03 12:47:35 PM PST 24 28573852 ps
T913 /workspace/coverage/default/84.edn_genbits.2319297769 Jan 03 12:46:26 PM PST 24 Jan 03 12:47:55 PM PST 24 52845865 ps
T914 /workspace/coverage/default/8.edn_alert.2292080 Jan 03 12:45:30 PM PST 24 Jan 03 12:47:02 PM PST 24 38593687 ps
T242 /workspace/coverage/default/98.edn_genbits.1043766495 Jan 03 12:46:49 PM PST 24 Jan 03 12:47:58 PM PST 24 70731497 ps
T915 /workspace/coverage/default/18.edn_genbits.2690740425 Jan 03 12:45:23 PM PST 24 Jan 03 12:46:58 PM PST 24 21215922 ps
T916 /workspace/coverage/default/21.edn_disable_auto_req_mode.1316468690 Jan 03 12:45:23 PM PST 24 Jan 03 12:46:56 PM PST 24 108006693 ps
T917 /workspace/coverage/default/1.edn_alert_test.2508360752 Jan 03 12:44:50 PM PST 24 Jan 03 12:46:31 PM PST 24 56578140 ps
T918 /workspace/coverage/default/179.edn_genbits.3619793109 Jan 03 12:47:28 PM PST 24 Jan 03 12:48:16 PM PST 24 41374593 ps
T919 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2991022312 Jan 03 12:36:58 PM PST 24 Jan 03 12:38:07 PM PST 24 92699517 ps
T920 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.491419318 Jan 03 12:37:03 PM PST 24 Jan 03 12:38:22 PM PST 24 13537953 ps
T921 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2939922325 Jan 03 12:37:10 PM PST 24 Jan 03 12:38:18 PM PST 24 723126155 ps
T922 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1909371048 Jan 03 12:36:24 PM PST 24 Jan 03 12:37:58 PM PST 24 46575241 ps
T923 /workspace/coverage/cover_reg_top/3.edn_tl_errors.3596988542 Jan 03 12:37:20 PM PST 24 Jan 03 12:38:43 PM PST 24 168587602 ps
T924 /workspace/coverage/cover_reg_top/37.edn_intr_test.3924519637 Jan 03 12:37:07 PM PST 24 Jan 03 12:38:27 PM PST 24 50878927 ps
T925 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.503817971 Jan 03 12:36:51 PM PST 24 Jan 03 12:38:07 PM PST 24 33913121 ps
T926 /workspace/coverage/cover_reg_top/5.edn_csr_rw.56661113 Jan 03 12:36:47 PM PST 24 Jan 03 12:38:06 PM PST 24 84442057 ps
T927 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.2102883403 Jan 03 12:37:01 PM PST 24 Jan 03 12:38:16 PM PST 24 277829867 ps
T928 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2367922521 Jan 03 12:37:08 PM PST 24 Jan 03 12:38:19 PM PST 24 35879474 ps
T929 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1617540086 Jan 03 12:37:21 PM PST 24 Jan 03 12:38:35 PM PST 24 47195172 ps
T930 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3940128403 Jan 03 12:36:51 PM PST 24 Jan 03 12:38:21 PM PST 24 45503904 ps
T931 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1967892997 Jan 03 12:37:25 PM PST 24 Jan 03 12:38:42 PM PST 24 272611941 ps
T177 /workspace/coverage/cover_reg_top/7.edn_csr_rw.502699942 Jan 03 12:37:21 PM PST 24 Jan 03 12:38:35 PM PST 24 25664467 ps
T178 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2923685305 Jan 03 12:37:11 PM PST 24 Jan 03 12:38:32 PM PST 24 47884182 ps
T932 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.4260811418 Jan 03 12:37:27 PM PST 24 Jan 03 12:38:56 PM PST 24 69252688 ps
T933 /workspace/coverage/cover_reg_top/15.edn_tl_errors.882890491 Jan 03 12:37:12 PM PST 24 Jan 03 12:38:21 PM PST 24 348852728 ps
T934 /workspace/coverage/cover_reg_top/4.edn_tl_errors.2653212431 Jan 03 12:37:10 PM PST 24 Jan 03 12:38:19 PM PST 24 57285528 ps
T935 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3505458572 Jan 03 12:37:39 PM PST 24 Jan 03 12:39:05 PM PST 24 124377790 ps
T936 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3347485537 Jan 03 12:37:23 PM PST 24 Jan 03 12:38:44 PM PST 24 15523892 ps
T937 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.749410303 Jan 03 12:37:03 PM PST 24 Jan 03 12:38:14 PM PST 24 27536334 ps
T938 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.721584243 Jan 03 12:36:58 PM PST 24 Jan 03 12:38:23 PM PST 24 188510196 ps
T939 /workspace/coverage/cover_reg_top/0.edn_intr_test.2936891754 Jan 03 12:37:19 PM PST 24 Jan 03 12:38:50 PM PST 24 34142510 ps
T179 /workspace/coverage/cover_reg_top/14.edn_csr_rw.1600153957 Jan 03 12:36:33 PM PST 24 Jan 03 12:38:08 PM PST 24 13643430 ps

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.3592301348
Short name T19
Test name
Test status
Simulation time 19973984 ps
CPU time 0.76 seconds
Started Jan 03 12:37:08 PM PST 24
Finished Jan 03 12:38:19 PM PST 24
Peak memory 205684 kb
Host smart-2af4ad7d-6a62-4576-a4be-9ca7274581dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592301348 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.3592301348
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/default/162.edn_genbits.1250301770
Short name T2
Test name
Test status
Simulation time 189429127 ps
CPU time 2.74 seconds
Started Jan 03 12:47:26 PM PST 24
Finished Jan 03 12:48:17 PM PST 24
Peak memory 214160 kb
Host smart-c9e2d209-43ad-4fab-b073-770160c98e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250301770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.1250301770
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3986263470
Short name T20
Test name
Test status
Simulation time 86083684 ps
CPU time 2.22 seconds
Started Jan 03 12:36:33 PM PST 24
Finished Jan 03 12:37:59 PM PST 24
Peak memory 206008 kb
Host smart-f78eea91-110a-4110-b73c-60b7e3d1b0f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986263470 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.3986263470
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/default/27.edn_genbits.783804602
Short name T36
Test name
Test status
Simulation time 19382575 ps
CPU time 1.05 seconds
Started Jan 03 12:45:32 PM PST 24
Finished Jan 03 12:47:05 PM PST 24
Peak memory 205644 kb
Host smart-a3544712-d64e-4678-8a4b-738b269519b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783804602 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.783804602
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.3349373547
Short name T5
Test name
Test status
Simulation time 183774586267 ps
CPU time 1074.69 seconds
Started Jan 03 12:45:41 PM PST 24
Finished Jan 03 01:05:16 PM PST 24
Peak memory 216780 kb
Host smart-21623b0c-2e56-46b7-bdbb-4145638694f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349373547 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.3349373547
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.edn_err.1037642515
Short name T7
Test name
Test status
Simulation time 76713166 ps
CPU time 1.04 seconds
Started Jan 03 12:46:35 PM PST 24
Finished Jan 03 12:47:49 PM PST 24
Peak memory 228208 kb
Host smart-b10d280f-5c96-4bf7-a264-834f84d8e239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037642515 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1037642515
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/1.edn_sec_cm.219395027
Short name T29
Test name
Test status
Simulation time 2291444621 ps
CPU time 3.06 seconds
Started Jan 03 12:44:46 PM PST 24
Finished Jan 03 12:46:20 PM PST 24
Peak memory 232064 kb
Host smart-1a10713e-3ef0-44da-90eb-09d847777ece
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219395027 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.219395027
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.834727402
Short name T140
Test name
Test status
Simulation time 520785331 ps
CPU time 3.26 seconds
Started Jan 03 12:36:53 PM PST 24
Finished Jan 03 12:38:07 PM PST 24
Peak memory 214328 kb
Host smart-72d0e99e-9743-4f93-bd42-266082fd56ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834727402 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.834727402
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/default/11.edn_intr.2674463211
Short name T72
Test name
Test status
Simulation time 18935646 ps
CPU time 1.04 seconds
Started Jan 03 12:45:32 PM PST 24
Finished Jan 03 12:47:10 PM PST 24
Peak memory 214588 kb
Host smart-a13a238a-d0ef-44bf-a17c-3a83e9d888dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674463211 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.2674463211
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/182.edn_genbits.1626687517
Short name T13
Test name
Test status
Simulation time 24023115 ps
CPU time 1.16 seconds
Started Jan 03 12:47:26 PM PST 24
Finished Jan 03 12:48:15 PM PST 24
Peak memory 214224 kb
Host smart-bfe78c24-ad82-4e31-b6c0-ec564434650b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626687517 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.1626687517
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.2195654400
Short name T22
Test name
Test status
Simulation time 34638657 ps
CPU time 0.76 seconds
Started Jan 03 12:37:12 PM PST 24
Finished Jan 03 12:38:25 PM PST 24
Peak memory 205988 kb
Host smart-6deb2b3b-119c-4c1e-a9bf-4e34735bd3fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195654400 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.2195654400
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/default/45.edn_alert.2384984207
Short name T77
Test name
Test status
Simulation time 17683452 ps
CPU time 0.96 seconds
Started Jan 03 12:46:09 PM PST 24
Finished Jan 03 12:47:38 PM PST 24
Peak memory 206116 kb
Host smart-40241683-4846-497f-954d-9a5d3f268921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384984207 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.2384984207
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.3934885032
Short name T163
Test name
Test status
Simulation time 20804964 ps
CPU time 0.75 seconds
Started Jan 03 12:36:40 PM PST 24
Finished Jan 03 12:38:22 PM PST 24
Peak memory 205680 kb
Host smart-89cd0880-19bc-433c-a6af-98b9d3305aa5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934885032 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.3934885032
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.3033994280
Short name T82
Test name
Test status
Simulation time 649736169439 ps
CPU time 1679.51 seconds
Started Jan 03 12:46:07 PM PST 24
Finished Jan 03 01:15:29 PM PST 24
Peak memory 229364 kb
Host smart-cc3d49c0-56e2-4927-af8a-99dd01375e48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033994280 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.3033994280
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_regwen.1966564964
Short name T213
Test name
Test status
Simulation time 15814701 ps
CPU time 0.96 seconds
Started Jan 03 12:45:11 PM PST 24
Finished Jan 03 12:46:47 PM PST 24
Peak memory 204676 kb
Host smart-40dd47ab-8a21-4957-88f1-00d7b1a1ee5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966564964 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.1966564964
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/30.edn_err.694781643
Short name T95
Test name
Test status
Simulation time 34305175 ps
CPU time 0.88 seconds
Started Jan 03 12:45:49 PM PST 24
Finished Jan 03 12:47:28 PM PST 24
Peak memory 214796 kb
Host smart-e2574ea2-df04-430c-bbca-8d5b9a783ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694781643 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.694781643
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.4049307681
Short name T133
Test name
Test status
Simulation time 145468790 ps
CPU time 2.68 seconds
Started Jan 03 12:37:25 PM PST 24
Finished Jan 03 12:38:41 PM PST 24
Peak memory 205964 kb
Host smart-9fc57c25-fbb3-4620-99dc-d1377f3b1554
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049307681 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.4049307681
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/default/62.edn_genbits.2545572552
Short name T199
Test name
Test status
Simulation time 114649812 ps
CPU time 1.01 seconds
Started Jan 03 12:46:43 PM PST 24
Finished Jan 03 12:47:55 PM PST 24
Peak memory 205472 kb
Host smart-ae6c2831-470a-4eef-84ef-379fd0a85511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545572552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.2545572552
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_genbits.1890818875
Short name T12
Test name
Test status
Simulation time 88526167 ps
CPU time 1.25 seconds
Started Jan 03 12:46:28 PM PST 24
Finished Jan 03 12:47:44 PM PST 24
Peak memory 214160 kb
Host smart-1e6d59f4-0963-4c22-990b-61aa63da7be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890818875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.1890818875
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.436774058
Short name T101
Test name
Test status
Simulation time 20452166 ps
CPU time 1.13 seconds
Started Jan 03 12:45:57 PM PST 24
Finished Jan 03 12:47:41 PM PST 24
Peak memory 225588 kb
Host smart-7bfb4a77-8b57-40fb-be3b-ec3eae5b1a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436774058 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.436774058
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/114.edn_genbits.2945354369
Short name T263
Test name
Test status
Simulation time 22524810 ps
CPU time 1 seconds
Started Jan 03 12:47:03 PM PST 24
Finished Jan 03 12:48:04 PM PST 24
Peak memory 205008 kb
Host smart-01f839d0-4e90-49da-bbcc-ca0d0d285d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945354369 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.2945354369
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.1270286658
Short name T239
Test name
Test status
Simulation time 30081612 ps
CPU time 1.09 seconds
Started Jan 03 12:47:04 PM PST 24
Finished Jan 03 12:48:05 PM PST 24
Peak memory 205720 kb
Host smart-d7ad32c4-719a-4689-8038-fd1572c1ea34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270286658 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.1270286658
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_alert.2667231207
Short name T222
Test name
Test status
Simulation time 55115994 ps
CPU time 0.93 seconds
Started Jan 03 12:44:42 PM PST 24
Finished Jan 03 12:46:10 PM PST 24
Peak memory 206000 kb
Host smart-13fcdeb5-1d1d-4dc2-be2d-a0b3d00a2e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667231207 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.2667231207
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert.2701976433
Short name T216
Test name
Test status
Simulation time 20891695 ps
CPU time 0.98 seconds
Started Jan 03 12:45:04 PM PST 24
Finished Jan 03 12:46:33 PM PST 24
Peak memory 205120 kb
Host smart-7155a867-d100-41f1-b414-c23d49bafeb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701976433 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.2701976433
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert.1966018273
Short name T17
Test name
Test status
Simulation time 34528453 ps
CPU time 0.92 seconds
Started Jan 03 12:46:13 PM PST 24
Finished Jan 03 12:47:37 PM PST 24
Peak memory 205256 kb
Host smart-9a381465-02da-4b70-9c0c-5a2bd505715c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966018273 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.1966018273
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.2416307560
Short name T235
Test name
Test status
Simulation time 125544588 ps
CPU time 1.4 seconds
Started Jan 03 12:47:19 PM PST 24
Finished Jan 03 12:48:13 PM PST 24
Peak memory 214376 kb
Host smart-0aecb507-032f-429f-bf53-5413b9773480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416307560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.2416307560
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_regwen.296795443
Short name T211
Test name
Test status
Simulation time 33335620 ps
CPU time 0.8 seconds
Started Jan 03 12:44:44 PM PST 24
Finished Jan 03 12:46:18 PM PST 24
Peak memory 204852 kb
Host smart-3ff12724-e696-43ad-b808-e4f066d530c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296795443 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.296795443
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/117.edn_genbits.3143107491
Short name T441
Test name
Test status
Simulation time 16935001 ps
CPU time 0.98 seconds
Started Jan 03 12:47:00 PM PST 24
Finished Jan 03 12:48:02 PM PST 24
Peak memory 205476 kb
Host smart-f025fd9d-aec3-4bd0-9c14-9bcb142dfca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143107491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.3143107491
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.1991023048
Short name T117
Test name
Test status
Simulation time 25194240 ps
CPU time 0.96 seconds
Started Jan 03 12:46:09 PM PST 24
Finished Jan 03 12:47:36 PM PST 24
Peak memory 214560 kb
Host smart-5d37c73d-971a-467c-983c-0a45d7769d7b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991023048 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.1991023048
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/176.edn_genbits.3429421468
Short name T11
Test name
Test status
Simulation time 17701733 ps
CPU time 1.05 seconds
Started Jan 03 12:47:26 PM PST 24
Finished Jan 03 12:48:15 PM PST 24
Peak memory 214340 kb
Host smart-f931a2d3-b9c9-48a8-a49f-a21f2a680bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429421468 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.3429421468
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_regwen.4115838265
Short name T84
Test name
Test status
Simulation time 49546017 ps
CPU time 0.83 seconds
Started Jan 03 12:44:57 PM PST 24
Finished Jan 03 12:46:38 PM PST 24
Peak memory 204820 kb
Host smart-a1a21740-315f-48e0-9e89-20e0aeb6d0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115838265 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.4115838265
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/132.edn_genbits.1862106794
Short name T32
Test name
Test status
Simulation time 43268932 ps
CPU time 0.87 seconds
Started Jan 03 12:47:24 PM PST 24
Finished Jan 03 12:48:14 PM PST 24
Peak memory 205280 kb
Host smart-6e34ced3-98cb-433a-a240-533bce35bd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862106794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.1862106794
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.3058722544
Short name T249
Test name
Test status
Simulation time 283021589 ps
CPU time 1.04 seconds
Started Jan 03 12:47:43 PM PST 24
Finished Jan 03 12:48:26 PM PST 24
Peak memory 204880 kb
Host smart-0467cc22-a74b-49fe-8c38-32cea227f421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058722544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.3058722544
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.2357716861
Short name T69
Test name
Test status
Simulation time 52667915 ps
CPU time 0.97 seconds
Started Jan 03 12:47:20 PM PST 24
Finished Jan 03 12:48:13 PM PST 24
Peak memory 205480 kb
Host smart-a4ffb29a-6202-480b-8e62-d499da34733f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357716861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.2357716861
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.3587509241
Short name T272
Test name
Test status
Simulation time 16557782 ps
CPU time 0.91 seconds
Started Jan 03 12:47:25 PM PST 24
Finished Jan 03 12:48:14 PM PST 24
Peak memory 205068 kb
Host smart-d07bf606-db02-4901-9957-5bbe0fa6519e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587509241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.3587509241
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.2631017634
Short name T267
Test name
Test status
Simulation time 166337020 ps
CPU time 0.91 seconds
Started Jan 03 12:47:26 PM PST 24
Finished Jan 03 12:48:15 PM PST 24
Peak memory 204828 kb
Host smart-03d6420a-1a91-4f9a-be3b-d25b4571fbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631017634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.2631017634
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.538276349
Short name T279
Test name
Test status
Simulation time 16579294 ps
CPU time 0.94 seconds
Started Jan 03 12:47:22 PM PST 24
Finished Jan 03 12:48:13 PM PST 24
Peak memory 205336 kb
Host smart-1eee2ae0-099f-45b8-975b-74677e985a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538276349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.538276349
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_disable.3151614422
Short name T106
Test name
Test status
Simulation time 31793245 ps
CPU time 0.81 seconds
Started Jan 03 12:44:48 PM PST 24
Finished Jan 03 12:46:09 PM PST 24
Peak memory 214496 kb
Host smart-b6c597a4-e557-418f-9c33-68b52ddf3925
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151614422 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.3151614422
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/11.edn_alert_test.94096198
Short name T399
Test name
Test status
Simulation time 17754338 ps
CPU time 0.93 seconds
Started Jan 03 12:45:15 PM PST 24
Finished Jan 03 12:46:45 PM PST 24
Peak memory 205440 kb
Host smart-fd9cd9e3-3283-40ea-a4ce-7b27e5fe3c52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94096198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.94096198
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_err.1949358234
Short name T74
Test name
Test status
Simulation time 42623443 ps
CPU time 1.05 seconds
Started Jan 03 12:45:42 PM PST 24
Finished Jan 03 12:47:13 PM PST 24
Peak memory 214688 kb
Host smart-3f7206e2-3cd3-451a-a45b-63a45549d33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949358234 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.1949358234
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_intr.1107171192
Short name T98
Test name
Test status
Simulation time 18098889 ps
CPU time 0.99 seconds
Started Jan 03 12:45:47 PM PST 24
Finished Jan 03 12:47:19 PM PST 24
Peak memory 214652 kb
Host smart-3d5e6e8c-a296-444a-be73-64441f0a35db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107171192 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.1107171192
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/29.edn_intr.71133540
Short name T90
Test name
Test status
Simulation time 21683275 ps
CPU time 0.96 seconds
Started Jan 03 12:45:32 PM PST 24
Finished Jan 03 12:47:10 PM PST 24
Peak memory 214488 kb
Host smart-1265e3e5-afa1-472b-8db3-98d425bd4b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71133540 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.71133540
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1307373308
Short name T195
Test name
Test status
Simulation time 263713152 ps
CPU time 1.97 seconds
Started Jan 03 12:37:18 PM PST 24
Finished Jan 03 12:38:28 PM PST 24
Peak memory 206024 kb
Host smart-b101244e-50bd-4c4c-ae64-035aef4cc3da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307373308 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.1307373308
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.3175689737
Short name T27
Test name
Test status
Simulation time 19973216 ps
CPU time 0.78 seconds
Started Jan 03 12:37:20 PM PST 24
Finished Jan 03 12:38:30 PM PST 24
Peak memory 205572 kb
Host smart-27c39b74-09a8-45df-90f2-46a37c70b21d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175689737 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3175689737
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/default/0.edn_genbits.1778922183
Short name T275
Test name
Test status
Simulation time 27952490 ps
CPU time 0.97 seconds
Started Jan 03 12:44:56 PM PST 24
Finished Jan 03 12:46:22 PM PST 24
Peak memory 205072 kb
Host smart-7a14e5db-d4df-4154-98ff-5e8556d93fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778922183 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.1778922183
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.835745249
Short name T241
Test name
Test status
Simulation time 133567592 ps
CPU time 2.58 seconds
Started Jan 03 12:46:22 PM PST 24
Finished Jan 03 12:47:50 PM PST 24
Peak memory 214208 kb
Host smart-3b46902f-8849-4d16-a222-7cc71ca6a091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835745249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.835745249
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_err.1672430679
Short name T907
Test name
Test status
Simulation time 25456044 ps
CPU time 1.12 seconds
Started Jan 03 12:45:36 PM PST 24
Finished Jan 03 12:47:16 PM PST 24
Peak memory 215060 kb
Host smart-2e73817e-55de-4e6e-913c-86a9265ebdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672430679 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.1672430679
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/118.edn_genbits.3431055297
Short name T852
Test name
Test status
Simulation time 23998867 ps
CPU time 0.92 seconds
Started Jan 03 12:47:04 PM PST 24
Finished Jan 03 12:48:05 PM PST 24
Peak memory 205544 kb
Host smart-639ea0de-b513-48c5-8896-9ae765ec84ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431055297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.3431055297
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.479648648
Short name T251
Test name
Test status
Simulation time 165772488 ps
CPU time 1.3 seconds
Started Jan 03 12:47:05 PM PST 24
Finished Jan 03 12:48:05 PM PST 24
Peak memory 214308 kb
Host smart-0fed8c84-f7c1-4c6f-8ebc-f7eecb7ae9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479648648 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.479648648
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.770729423
Short name T422
Test name
Test status
Simulation time 35850889 ps
CPU time 1 seconds
Started Jan 03 12:47:20 PM PST 24
Finished Jan 03 12:48:15 PM PST 24
Peak memory 205540 kb
Host smart-a3f3f376-35ef-4425-9365-5fa45dead7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770729423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.770729423
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/140.edn_genbits.2834417495
Short name T243
Test name
Test status
Simulation time 29357583 ps
CPU time 0.91 seconds
Started Jan 03 12:47:19 PM PST 24
Finished Jan 03 12:48:13 PM PST 24
Peak memory 205156 kb
Host smart-ea4b520c-b625-4411-b0fb-5af63448b4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834417495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2834417495
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_genbits.3923289372
Short name T742
Test name
Test status
Simulation time 22498235 ps
CPU time 1.06 seconds
Started Jan 03 12:45:46 PM PST 24
Finished Jan 03 12:47:12 PM PST 24
Peak memory 205440 kb
Host smart-368a36e8-358c-49eb-9a4f-9af5104b1195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923289372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.3923289372
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.2240717667
Short name T227
Test name
Test status
Simulation time 23767946 ps
CPU time 0.97 seconds
Started Jan 03 12:45:42 PM PST 24
Finished Jan 03 12:47:22 PM PST 24
Peak memory 206104 kb
Host smart-234c1c62-bbda-415f-aa15-ad3f2662f8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240717667 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.2240717667
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.3868480515
Short name T254
Test name
Test status
Simulation time 135922283 ps
CPU time 1.07 seconds
Started Jan 03 12:47:27 PM PST 24
Finished Jan 03 12:48:16 PM PST 24
Peak memory 205564 kb
Host smart-55bb3243-880a-411a-b7a5-83e3e0cda057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868480515 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3868480515
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.1782320168
Short name T187
Test name
Test status
Simulation time 18101366 ps
CPU time 0.97 seconds
Started Jan 03 12:45:41 PM PST 24
Finished Jan 03 12:47:09 PM PST 24
Peak memory 206212 kb
Host smart-0f6fc313-0f23-4490-a74a-bbf2738be4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782320168 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.1782320168
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert.1286697031
Short name T218
Test name
Test status
Simulation time 33805529 ps
CPU time 0.95 seconds
Started Jan 03 12:45:42 PM PST 24
Finished Jan 03 12:47:17 PM PST 24
Peak memory 206036 kb
Host smart-f976a00a-745a-40d0-b331-de5a602ab23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286697031 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.1286697031
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/235.edn_genbits.3398775637
Short name T261
Test name
Test status
Simulation time 40676343 ps
CPU time 0.95 seconds
Started Jan 03 12:47:26 PM PST 24
Finished Jan 03 12:48:15 PM PST 24
Peak memory 205364 kb
Host smart-a9c98159-c871-4159-8cb9-32a4937b2c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398775637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.3398775637
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.349425197
Short name T246
Test name
Test status
Simulation time 208674129 ps
CPU time 2.86 seconds
Started Jan 03 12:48:14 PM PST 24
Finished Jan 03 12:48:44 PM PST 24
Peak memory 214216 kb
Host smart-e1b5eace-90ad-4f9e-a8c4-7fb0e8198c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349425197 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.349425197
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.1115918492
Short name T258
Test name
Test status
Simulation time 20184501 ps
CPU time 1.05 seconds
Started Jan 03 12:48:02 PM PST 24
Finished Jan 03 12:48:35 PM PST 24
Peak memory 206016 kb
Host smart-15498ddc-b6aa-48dd-a25b-05ca97037529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115918492 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.1115918492
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_disable.357325182
Short name T79
Test name
Test status
Simulation time 12865596 ps
CPU time 0.89 seconds
Started Jan 03 12:45:43 PM PST 24
Finished Jan 03 12:47:13 PM PST 24
Peak memory 214580 kb
Host smart-c7938c8c-d9a2-4f7f-ae32-6e44d6423fd2
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357325182 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.357325182
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable.2390647048
Short name T123
Test name
Test status
Simulation time 13518167 ps
CPU time 0.87 seconds
Started Jan 03 12:45:46 PM PST 24
Finished Jan 03 12:47:11 PM PST 24
Peak memory 214684 kb
Host smart-c780f86f-6016-439a-9969-0ebc94177aa7
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390647048 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.2390647048
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable.3890486082
Short name T120
Test name
Test status
Simulation time 12154725 ps
CPU time 0.85 seconds
Started Jan 03 12:45:20 PM PST 24
Finished Jan 03 12:46:50 PM PST 24
Peak memory 214652 kb
Host smart-25d03cbf-11a9-4561-94e3-06c83f8bfbe4
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890486082 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.3890486082
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.1384911712
Short name T108
Test name
Test status
Simulation time 230642337 ps
CPU time 1.03 seconds
Started Jan 03 12:45:49 PM PST 24
Finished Jan 03 12:47:18 PM PST 24
Peak memory 214696 kb
Host smart-deed0853-b633-44eb-8256-40debc23c7cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384911712 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.1384911712
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_disable.341438111
Short name T122
Test name
Test status
Simulation time 11115091 ps
CPU time 0.85 seconds
Started Jan 03 12:46:32 PM PST 24
Finished Jan 03 12:47:49 PM PST 24
Peak memory 214524 kb
Host smart-8dd7cc01-8ef6-47ff-b6a6-cbd717a01297
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341438111 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.341438111
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable.467570418
Short name T125
Test name
Test status
Simulation time 22572155 ps
CPU time 0.85 seconds
Started Jan 03 12:46:03 PM PST 24
Finished Jan 03 12:47:27 PM PST 24
Peak memory 214440 kb
Host smart-911fe55f-d3b0-4d82-bfff-3f75ae35e231
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467570418 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.467570418
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable.470378255
Short name T124
Test name
Test status
Simulation time 13821598 ps
CPU time 0.87 seconds
Started Jan 03 12:45:23 PM PST 24
Finished Jan 03 12:46:55 PM PST 24
Peak memory 214424 kb
Host smart-b5573637-7d0a-46c7-b5d1-b9a12809a3a8
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470378255 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.470378255
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/193.edn_genbits.1736239952
Short name T206
Test name
Test status
Simulation time 44172190 ps
CPU time 1.49 seconds
Started Jan 03 12:47:30 PM PST 24
Finished Jan 03 12:48:17 PM PST 24
Peak memory 214188 kb
Host smart-82321bdc-29d6-456c-887f-86db9d617c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736239952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.1736239952
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.643839845
Short name T171
Test name
Test status
Simulation time 31833140 ps
CPU time 1.1 seconds
Started Jan 03 12:36:41 PM PST 24
Finished Jan 03 12:37:57 PM PST 24
Peak memory 206008 kb
Host smart-0f35801a-0cfb-4683-8537-d8bf9acdaa84
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643839845 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.643839845
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1626725818
Short name T319
Test name
Test status
Simulation time 118336280 ps
CPU time 3.21 seconds
Started Jan 03 12:37:05 PM PST 24
Finished Jan 03 12:38:21 PM PST 24
Peak memory 206004 kb
Host smart-949a3b78-fb4f-412d-b670-d82fc7d86edf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626725818 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.1626725818
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2923685305
Short name T178
Test name
Test status
Simulation time 47884182 ps
CPU time 0.8 seconds
Started Jan 03 12:37:11 PM PST 24
Finished Jan 03 12:38:32 PM PST 24
Peak memory 205728 kb
Host smart-083207fa-bc05-418c-9e7d-f0bcde2c3509
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923685305 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.2923685305
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2991022312
Short name T919
Test name
Test status
Simulation time 92699517 ps
CPU time 1.04 seconds
Started Jan 03 12:36:58 PM PST 24
Finished Jan 03 12:38:07 PM PST 24
Peak memory 214268 kb
Host smart-43c92cb5-30ad-48f7-9f7e-31dec7c571f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991022312 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.2991022312
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.2936891754
Short name T939
Test name
Test status
Simulation time 34142510 ps
CPU time 0.75 seconds
Started Jan 03 12:37:19 PM PST 24
Finished Jan 03 12:38:50 PM PST 24
Peak memory 205816 kb
Host smart-eab06adc-7ddd-4558-99d4-0e58177f374f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936891754 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.2936891754
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.1498689661
Short name T337
Test name
Test status
Simulation time 39470161 ps
CPU time 2.49 seconds
Started Jan 03 12:37:07 PM PST 24
Finished Jan 03 12:38:17 PM PST 24
Peak memory 214556 kb
Host smart-65ae814b-fb26-45e3-b24f-229027550e7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498689661 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.1498689661
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1057053705
Short name T175
Test name
Test status
Simulation time 22999026 ps
CPU time 1.1 seconds
Started Jan 03 12:37:07 PM PST 24
Finished Jan 03 12:38:17 PM PST 24
Peak memory 205992 kb
Host smart-aeeb0d3a-a0e0-4370-9151-aca5ca0c5e8d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057053705 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.1057053705
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2117247199
Short name T166
Test name
Test status
Simulation time 680446079 ps
CPU time 4.73 seconds
Started Jan 03 12:36:54 PM PST 24
Finished Jan 03 12:38:08 PM PST 24
Peak memory 205904 kb
Host smart-07de3cde-953a-4f5a-9cd9-1bbba3c239b0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117247199 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2117247199
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3057820023
Short name T317
Test name
Test status
Simulation time 18703381 ps
CPU time 0.94 seconds
Started Jan 03 12:37:01 PM PST 24
Finished Jan 03 12:38:21 PM PST 24
Peak memory 205996 kb
Host smart-e9df2397-d9b3-4430-b778-f2352219a776
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057820023 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.3057820023
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3018060304
Short name T301
Test name
Test status
Simulation time 35303396 ps
CPU time 1.08 seconds
Started Jan 03 12:37:43 PM PST 24
Finished Jan 03 12:38:59 PM PST 24
Peak memory 214236 kb
Host smart-e9bfd631-f8e8-41e2-ad4c-59ed4ff08c3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018060304 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.3018060304
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.3317739217
Short name T172
Test name
Test status
Simulation time 40952598 ps
CPU time 0.86 seconds
Started Jan 03 12:37:28 PM PST 24
Finished Jan 03 12:38:37 PM PST 24
Peak memory 205816 kb
Host smart-0daa31ba-32c0-4aea-bf16-abdb65dd1502
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317739217 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.3317739217
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.165581049
Short name T304
Test name
Test status
Simulation time 17819931 ps
CPU time 0.76 seconds
Started Jan 03 12:37:22 PM PST 24
Finished Jan 03 12:38:35 PM PST 24
Peak memory 205696 kb
Host smart-96004650-e973-4f04-89ee-7954c61fa8b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165581049 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.165581049
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.775115085
Short name T138
Test name
Test status
Simulation time 118939094 ps
CPU time 1.24 seconds
Started Jan 03 12:38:12 PM PST 24
Finished Jan 03 12:39:31 PM PST 24
Peak memory 205868 kb
Host smart-262ac2a6-7d61-41ee-8cc2-8d9a99fa29d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775115085 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_out
standing.775115085
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.2184318032
Short name T334
Test name
Test status
Simulation time 42815340 ps
CPU time 1.74 seconds
Started Jan 03 12:37:20 PM PST 24
Finished Jan 03 12:38:31 PM PST 24
Peak memory 214248 kb
Host smart-be2159cb-efb5-49b6-b67c-ef76a6047001
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184318032 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.2184318032
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1284027742
Short name T358
Test name
Test status
Simulation time 135707279 ps
CPU time 1.97 seconds
Started Jan 03 12:36:51 PM PST 24
Finished Jan 03 12:38:07 PM PST 24
Peak memory 206064 kb
Host smart-2ccc3c33-d2e1-4898-834b-bae9ba54ca6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284027742 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.1284027742
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3969048096
Short name T348
Test name
Test status
Simulation time 110652125 ps
CPU time 0.85 seconds
Started Jan 03 12:36:46 PM PST 24
Finished Jan 03 12:38:22 PM PST 24
Peak memory 205728 kb
Host smart-4c57cf30-c175-4be8-ba87-4beea1fcc1c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969048096 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.3969048096
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.2076616389
Short name T176
Test name
Test status
Simulation time 11633658 ps
CPU time 0.89 seconds
Started Jan 03 12:37:18 PM PST 24
Finished Jan 03 12:38:27 PM PST 24
Peak memory 205880 kb
Host smart-b32fffc2-da65-4e99-84d4-c2098779c78b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076616389 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.2076616389
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.2083527800
Short name T338
Test name
Test status
Simulation time 39325255 ps
CPU time 0.78 seconds
Started Jan 03 12:36:53 PM PST 24
Finished Jan 03 12:38:07 PM PST 24
Peak memory 205752 kb
Host smart-cef7f6c2-dd44-4439-9554-156dcb7db646
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083527800 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2083527800
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1087993658
Short name T152
Test name
Test status
Simulation time 25723752 ps
CPU time 1.11 seconds
Started Jan 03 12:37:20 PM PST 24
Finished Jan 03 12:38:30 PM PST 24
Peak memory 205932 kb
Host smart-b42e0296-b2fb-43af-a829-1900ef85688c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087993658 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.1087993658
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.215784754
Short name T360
Test name
Test status
Simulation time 134094214 ps
CPU time 1 seconds
Started Jan 03 12:37:18 PM PST 24
Finished Jan 03 12:38:28 PM PST 24
Peak memory 214224 kb
Host smart-fa8c427d-d076-4372-a2d3-f208256e794b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215784754 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.215784754
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.1360931201
Short name T156
Test name
Test status
Simulation time 14566515 ps
CPU time 0.86 seconds
Started Jan 03 12:37:12 PM PST 24
Finished Jan 03 12:38:25 PM PST 24
Peak memory 205980 kb
Host smart-0649e197-4246-4c0c-bcb9-b953398e2df5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360931201 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.1360931201
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.402691244
Short name T351
Test name
Test status
Simulation time 14787309 ps
CPU time 0.84 seconds
Started Jan 03 12:37:22 PM PST 24
Finished Jan 03 12:38:39 PM PST 24
Peak memory 205876 kb
Host smart-698b027c-927e-4d67-9a76-9f7217a06e67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402691244 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.402691244
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.749410303
Short name T937
Test name
Test status
Simulation time 27536334 ps
CPU time 0.89 seconds
Started Jan 03 12:37:03 PM PST 24
Finished Jan 03 12:38:14 PM PST 24
Peak memory 205944 kb
Host smart-1c4b9151-53c6-4ba3-b1ec-e7fb043d69d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749410303 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_ou
tstanding.749410303
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.3880002797
Short name T349
Test name
Test status
Simulation time 323765440 ps
CPU time 2.96 seconds
Started Jan 03 12:37:19 PM PST 24
Finished Jan 03 12:38:37 PM PST 24
Peak memory 214104 kb
Host smart-b5e0b8ec-e0a9-4ac2-aede-8a27bf502dcd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880002797 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.3880002797
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.524642998
Short name T347
Test name
Test status
Simulation time 319026980 ps
CPU time 2.27 seconds
Started Jan 03 12:37:11 PM PST 24
Finished Jan 03 12:38:21 PM PST 24
Peak memory 206040 kb
Host smart-070f8d25-0a13-4632-8700-09518ff76005
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524642998 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.524642998
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2645160887
Short name T160
Test name
Test status
Simulation time 48417048 ps
CPU time 1.38 seconds
Started Jan 03 12:37:15 PM PST 24
Finished Jan 03 12:38:24 PM PST 24
Peak memory 214204 kb
Host smart-51537bd8-d9b7-4da8-9560-d763f1a86570
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645160887 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.2645160887
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.3226171273
Short name T161
Test name
Test status
Simulation time 41079658 ps
CPU time 0.85 seconds
Started Jan 03 12:36:39 PM PST 24
Finished Jan 03 12:37:56 PM PST 24
Peak memory 206024 kb
Host smart-60290d50-9d70-4bf3-9f08-98a7c4a88de9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226171273 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.3226171273
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.927311903
Short name T343
Test name
Test status
Simulation time 15109848 ps
CPU time 0.83 seconds
Started Jan 03 12:37:32 PM PST 24
Finished Jan 03 12:38:54 PM PST 24
Peak memory 205972 kb
Host smart-283c6d57-132c-4577-a13a-1276ad85069d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927311903 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.927311903
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.923138088
Short name T151
Test name
Test status
Simulation time 37144412 ps
CPU time 1.03 seconds
Started Jan 03 12:37:16 PM PST 24
Finished Jan 03 12:38:29 PM PST 24
Peak memory 205876 kb
Host smart-ba93933f-b4d1-484c-850e-ea46346ccb8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923138088 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_ou
tstanding.923138088
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.3325621776
Short name T330
Test name
Test status
Simulation time 189581827 ps
CPU time 3.09 seconds
Started Jan 03 12:37:16 PM PST 24
Finished Jan 03 12:38:31 PM PST 24
Peak memory 214140 kb
Host smart-29218538-8056-4621-a87f-b51eab158a64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325621776 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3325621776
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.4260811418
Short name T932
Test name
Test status
Simulation time 69252688 ps
CPU time 2.13 seconds
Started Jan 03 12:37:27 PM PST 24
Finished Jan 03 12:38:56 PM PST 24
Peak memory 206004 kb
Host smart-4451c036-a719-4f17-9003-8842689e74f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260811418 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.4260811418
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.313885552
Short name T345
Test name
Test status
Simulation time 99563091 ps
CPU time 1.07 seconds
Started Jan 03 12:37:18 PM PST 24
Finished Jan 03 12:38:32 PM PST 24
Peak memory 214140 kb
Host smart-b28a8c21-9449-4b5a-883f-fda3fe4bc882
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313885552 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.313885552
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.822430437
Short name T305
Test name
Test status
Simulation time 51781701 ps
CPU time 0.82 seconds
Started Jan 03 12:37:18 PM PST 24
Finished Jan 03 12:38:27 PM PST 24
Peak memory 205808 kb
Host smart-40924bbe-d94f-4f2d-b87c-fc90311fe644
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822430437 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.822430437
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.3971368149
Short name T293
Test name
Test status
Simulation time 41963679 ps
CPU time 0.8 seconds
Started Jan 03 12:37:04 PM PST 24
Finished Jan 03 12:38:16 PM PST 24
Peak memory 205984 kb
Host smart-b3366813-e953-40c0-851d-3c8705281674
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971368149 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.3971368149
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2505301292
Short name T333
Test name
Test status
Simulation time 20173965 ps
CPU time 1.03 seconds
Started Jan 03 12:37:12 PM PST 24
Finished Jan 03 12:38:27 PM PST 24
Peak memory 205888 kb
Host smart-410fc7da-7458-4978-88bf-661e53ce099b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505301292 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.2505301292
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.2197913764
Short name T336
Test name
Test status
Simulation time 20783997 ps
CPU time 1.46 seconds
Started Jan 03 12:37:20 PM PST 24
Finished Jan 03 12:38:41 PM PST 24
Peak memory 214068 kb
Host smart-dbcc25e9-22dd-4699-be39-12094d51622d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197913764 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.2197913764
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.721584243
Short name T938
Test name
Test status
Simulation time 188510196 ps
CPU time 2.44 seconds
Started Jan 03 12:36:58 PM PST 24
Finished Jan 03 12:38:23 PM PST 24
Peak memory 206004 kb
Host smart-abf080c8-c757-45ab-88fb-3026827e93bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721584243 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.721584243
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1302950189
Short name T316
Test name
Test status
Simulation time 45308166 ps
CPU time 1.11 seconds
Started Jan 03 12:36:55 PM PST 24
Finished Jan 03 12:38:29 PM PST 24
Peak memory 214236 kb
Host smart-b1245bda-6ccc-4ef0-b06d-4a0247aac3db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302950189 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.1302950189
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.1600153957
Short name T179
Test name
Test status
Simulation time 13643430 ps
CPU time 0.88 seconds
Started Jan 03 12:36:33 PM PST 24
Finished Jan 03 12:38:08 PM PST 24
Peak memory 205936 kb
Host smart-21fb7e8b-b8ce-469c-9ec2-77a335cf963c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600153957 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.1600153957
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.1124746832
Short name T309
Test name
Test status
Simulation time 17579439 ps
CPU time 0.91 seconds
Started Jan 03 12:37:37 PM PST 24
Finished Jan 03 12:38:52 PM PST 24
Peak memory 205924 kb
Host smart-2b9cea20-927b-448f-b855-b342a1ce208b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124746832 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.1124746832
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3747662606
Short name T168
Test name
Test status
Simulation time 31733712 ps
CPU time 0.9 seconds
Started Jan 03 12:36:55 PM PST 24
Finished Jan 03 12:38:07 PM PST 24
Peak memory 205932 kb
Host smart-a2989998-352e-46fe-938a-3a94585f0cf5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747662606 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.3747662606
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.3756022322
Short name T142
Test name
Test status
Simulation time 553711034 ps
CPU time 3.44 seconds
Started Jan 03 12:37:04 PM PST 24
Finished Jan 03 12:38:28 PM PST 24
Peak memory 214220 kb
Host smart-1b304479-d078-4606-9141-6941b36493a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756022322 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.3756022322
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3861085598
Short name T321
Test name
Test status
Simulation time 47358721 ps
CPU time 1.56 seconds
Started Jan 03 12:37:27 PM PST 24
Finished Jan 03 12:38:37 PM PST 24
Peak memory 205892 kb
Host smart-074373fb-92fc-4968-b4bf-268fe31d6379
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861085598 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.3861085598
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.3381137719
Short name T315
Test name
Test status
Simulation time 23703433 ps
CPU time 0.96 seconds
Started Jan 03 12:37:18 PM PST 24
Finished Jan 03 12:38:27 PM PST 24
Peak memory 215920 kb
Host smart-95454182-75c0-47da-ab69-f112dee0735f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381137719 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.3381137719
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.1883316961
Short name T297
Test name
Test status
Simulation time 24246942 ps
CPU time 0.83 seconds
Started Jan 03 12:37:14 PM PST 24
Finished Jan 03 12:38:23 PM PST 24
Peak memory 205904 kb
Host smart-bbd454e9-18ab-4d6a-9b4e-96a94b3391df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883316961 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.1883316961
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3814050610
Short name T314
Test name
Test status
Simulation time 16253435 ps
CPU time 0.96 seconds
Started Jan 03 12:37:22 PM PST 24
Finished Jan 03 12:38:39 PM PST 24
Peak memory 205952 kb
Host smart-beea38de-e8ad-4bb1-af81-4a47e57ccc95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814050610 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.3814050610
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.882890491
Short name T933
Test name
Test status
Simulation time 348852728 ps
CPU time 2.12 seconds
Started Jan 03 12:37:12 PM PST 24
Finished Jan 03 12:38:21 PM PST 24
Peak memory 214168 kb
Host smart-146ad6b3-e819-4fd7-9505-8f17f063f4ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882890491 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.882890491
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.644129593
Short name T167
Test name
Test status
Simulation time 132002089 ps
CPU time 2.6 seconds
Started Jan 03 12:37:21 PM PST 24
Finished Jan 03 12:38:32 PM PST 24
Peak memory 205868 kb
Host smart-a77ab795-9727-4e4d-ade2-bc5df699d7f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644129593 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.644129593
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.4087962965
Short name T134
Test name
Test status
Simulation time 71459709 ps
CPU time 1.14 seconds
Started Jan 03 12:37:24 PM PST 24
Finished Jan 03 12:38:39 PM PST 24
Peak memory 214124 kb
Host smart-a8d83830-e344-461a-876c-a944a9bdccf2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087962965 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.4087962965
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.1366640078
Short name T318
Test name
Test status
Simulation time 23353034 ps
CPU time 0.83 seconds
Started Jan 03 12:37:18 PM PST 24
Finished Jan 03 12:38:27 PM PST 24
Peak memory 205872 kb
Host smart-40640e04-814a-4cb8-929a-3d413e1c1cd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366640078 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1366640078
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3806818551
Short name T310
Test name
Test status
Simulation time 28090118 ps
CPU time 0.77 seconds
Started Jan 03 12:37:43 PM PST 24
Finished Jan 03 12:38:58 PM PST 24
Peak memory 205672 kb
Host smart-85b6924b-96a6-4b18-9f6f-d873f6f943a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806818551 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3806818551
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1617540086
Short name T929
Test name
Test status
Simulation time 47195172 ps
CPU time 1.1 seconds
Started Jan 03 12:37:21 PM PST 24
Finished Jan 03 12:38:35 PM PST 24
Peak memory 205872 kb
Host smart-fd8b7df0-207d-4070-97a1-92a2344c95b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617540086 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.1617540086
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.4052977946
Short name T359
Test name
Test status
Simulation time 120945708 ps
CPU time 2.25 seconds
Started Jan 03 12:37:40 PM PST 24
Finished Jan 03 12:38:52 PM PST 24
Peak memory 214152 kb
Host smart-96bcce13-97ee-4bcb-a1a1-c114790bf41a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052977946 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.4052977946
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3505458572
Short name T935
Test name
Test status
Simulation time 124377790 ps
CPU time 2.86 seconds
Started Jan 03 12:37:39 PM PST 24
Finished Jan 03 12:39:05 PM PST 24
Peak memory 205880 kb
Host smart-724ed47f-05c4-4f39-8b33-e0ab0c42d81e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505458572 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.3505458572
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.4054758452
Short name T341
Test name
Test status
Simulation time 81711349 ps
CPU time 1.13 seconds
Started Jan 03 12:36:59 PM PST 24
Finished Jan 03 12:38:19 PM PST 24
Peak memory 214160 kb
Host smart-bbdbf09d-4e9a-4427-a468-db8efaaf13d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054758452 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.4054758452
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.4128162379
Short name T173
Test name
Test status
Simulation time 44713034 ps
CPU time 0.81 seconds
Started Jan 03 12:37:25 PM PST 24
Finished Jan 03 12:38:39 PM PST 24
Peak memory 205676 kb
Host smart-cf8e534a-85d1-4d34-af0f-cdff364566c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128162379 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.4128162379
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.494074408
Short name T327
Test name
Test status
Simulation time 16866635 ps
CPU time 0.88 seconds
Started Jan 03 12:37:23 PM PST 24
Finished Jan 03 12:38:49 PM PST 24
Peak memory 205668 kb
Host smart-224f374b-3068-43cb-843f-ce5e307c1807
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494074408 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.494074408
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.164112387
Short name T180
Test name
Test status
Simulation time 75139833 ps
CPU time 1.24 seconds
Started Jan 03 12:37:15 PM PST 24
Finished Jan 03 12:38:24 PM PST 24
Peak memory 205980 kb
Host smart-4842d97f-7fef-4e9b-a223-32f4b9f35802
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164112387 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_ou
tstanding.164112387
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.3334829961
Short name T157
Test name
Test status
Simulation time 65940777 ps
CPU time 1.38 seconds
Started Jan 03 12:36:52 PM PST 24
Finished Jan 03 12:38:11 PM PST 24
Peak memory 214220 kb
Host smart-19d60659-fb70-4f61-8be7-752c447a7807
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334829961 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.3334829961
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3607300126
Short name T147
Test name
Test status
Simulation time 46604391 ps
CPU time 1.48 seconds
Started Jan 03 12:37:19 PM PST 24
Finished Jan 03 12:38:36 PM PST 24
Peak memory 205880 kb
Host smart-79837af0-329d-4160-956e-b5357f0c8c0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607300126 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3607300126
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3551904930
Short name T129
Test name
Test status
Simulation time 37698592 ps
CPU time 1.26 seconds
Started Jan 03 12:37:24 PM PST 24
Finished Jan 03 12:38:41 PM PST 24
Peak memory 214312 kb
Host smart-2336a0a6-77bb-4e8a-8723-6f1fb48feecb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551904930 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.3551904930
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.1178870217
Short name T146
Test name
Test status
Simulation time 24827563 ps
CPU time 0.83 seconds
Started Jan 03 12:37:15 PM PST 24
Finished Jan 03 12:38:24 PM PST 24
Peak memory 205880 kb
Host smart-f2cb68e2-f0c9-42fc-a432-d9f13a0c4a3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178870217 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1178870217
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.2355514958
Short name T181
Test name
Test status
Simulation time 14753920 ps
CPU time 0.8 seconds
Started Jan 03 12:37:02 PM PST 24
Finished Jan 03 12:38:24 PM PST 24
Peak memory 205976 kb
Host smart-d772ba4f-71a0-42b0-9bb5-01cb1f8deb90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355514958 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2355514958
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1193957460
Short name T162
Test name
Test status
Simulation time 46333797 ps
CPU time 0.96 seconds
Started Jan 03 12:37:18 PM PST 24
Finished Jan 03 12:38:27 PM PST 24
Peak memory 205992 kb
Host smart-ee8c25c0-4643-4fe1-b3cc-3424b631a5d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193957460 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.1193957460
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.3231463291
Short name T158
Test name
Test status
Simulation time 595161855 ps
CPU time 2.91 seconds
Started Jan 03 12:37:31 PM PST 24
Finished Jan 03 12:39:00 PM PST 24
Peak memory 214280 kb
Host smart-b59ca112-cfd5-46a8-910e-9d6f0d0926ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231463291 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3231463291
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3813383723
Short name T131
Test name
Test status
Simulation time 109673040 ps
CPU time 1.34 seconds
Started Jan 03 12:36:51 PM PST 24
Finished Jan 03 12:38:22 PM PST 24
Peak memory 205912 kb
Host smart-d7ef57fd-b016-40b3-be1e-9b542c97152e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813383723 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.3813383723
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3347485537
Short name T936
Test name
Test status
Simulation time 15523892 ps
CPU time 0.92 seconds
Started Jan 03 12:37:23 PM PST 24
Finished Jan 03 12:38:44 PM PST 24
Peak memory 205920 kb
Host smart-295cb4ed-6eab-4fd8-90d3-2fe997a4c9a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347485537 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3347485537
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.3237221893
Short name T303
Test name
Test status
Simulation time 27384373 ps
CPU time 0.87 seconds
Started Jan 03 12:37:10 PM PST 24
Finished Jan 03 12:38:25 PM PST 24
Peak memory 206004 kb
Host smart-86fafeba-5531-417a-9a88-a242af4035d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237221893 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.3237221893
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.3416347609
Short name T339
Test name
Test status
Simulation time 65841956 ps
CPU time 0.81 seconds
Started Jan 03 12:37:09 PM PST 24
Finished Jan 03 12:38:29 PM PST 24
Peak memory 205976 kb
Host smart-838c1963-a9dc-4ba0-91df-5fe62b8bacf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416347609 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.3416347609
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1835807012
Short name T328
Test name
Test status
Simulation time 94672230 ps
CPU time 1.23 seconds
Started Jan 03 12:37:25 PM PST 24
Finished Jan 03 12:38:34 PM PST 24
Peak memory 205892 kb
Host smart-8ba1ee9a-c0d7-46ce-ba6a-8ff89e1b13a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835807012 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.1835807012
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.4113893055
Short name T139
Test name
Test status
Simulation time 106425515 ps
CPU time 3.12 seconds
Started Jan 03 12:37:05 PM PST 24
Finished Jan 03 12:38:25 PM PST 24
Peak memory 214224 kb
Host smart-7b876394-28af-4077-b0c9-e12ad67cc50f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113893055 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.4113893055
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2939922325
Short name T921
Test name
Test status
Simulation time 723126155 ps
CPU time 1.96 seconds
Started Jan 03 12:37:10 PM PST 24
Finished Jan 03 12:38:18 PM PST 24
Peak memory 205952 kb
Host smart-22729df9-6142-4dfa-9279-30dc5f751bef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939922325 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.2939922325
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.2102883403
Short name T927
Test name
Test status
Simulation time 277829867 ps
CPU time 1.06 seconds
Started Jan 03 12:37:01 PM PST 24
Finished Jan 03 12:38:16 PM PST 24
Peak memory 206044 kb
Host smart-3e155b3d-0ddd-424e-8d7d-52362a7f14b2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102883403 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.2102883403
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.4072536886
Short name T153
Test name
Test status
Simulation time 1047504743 ps
CPU time 6.03 seconds
Started Jan 03 12:37:17 PM PST 24
Finished Jan 03 12:38:32 PM PST 24
Peak memory 205916 kb
Host smart-0c16362d-51e7-4984-8605-3bb771126188
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072536886 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.4072536886
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2416539403
Short name T322
Test name
Test status
Simulation time 55097655 ps
CPU time 0.86 seconds
Started Jan 03 12:36:42 PM PST 24
Finished Jan 03 12:38:00 PM PST 24
Peak memory 205876 kb
Host smart-ce08e412-5e09-41bd-afaa-ec1c7bc3d334
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416539403 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.2416539403
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1642242625
Short name T289
Test name
Test status
Simulation time 77557459 ps
CPU time 0.99 seconds
Started Jan 03 12:36:57 PM PST 24
Finished Jan 03 12:38:21 PM PST 24
Peak memory 214176 kb
Host smart-f9157f8a-e391-43fc-bf0a-fcf9b0b6a699
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642242625 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.1642242625
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.1035156598
Short name T170
Test name
Test status
Simulation time 41115015 ps
CPU time 0.81 seconds
Started Jan 03 12:36:56 PM PST 24
Finished Jan 03 12:38:19 PM PST 24
Peak memory 205976 kb
Host smart-1d28ed5c-b923-402b-a048-4924be8ae53c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035156598 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.1035156598
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.526326886
Short name T137
Test name
Test status
Simulation time 61433948 ps
CPU time 1.42 seconds
Started Jan 03 12:37:25 PM PST 24
Finished Jan 03 12:38:34 PM PST 24
Peak memory 205900 kb
Host smart-d6c87d9e-74c5-4be0-8b0e-937393667422
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526326886 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_out
standing.526326886
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.2037518644
Short name T130
Test name
Test status
Simulation time 202642283 ps
CPU time 3.34 seconds
Started Jan 03 12:36:29 PM PST 24
Finished Jan 03 12:38:04 PM PST 24
Peak memory 214244 kb
Host smart-0c1e8018-751f-4419-bb0d-ce4db66f0b02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037518644 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.2037518644
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1100239309
Short name T194
Test name
Test status
Simulation time 84930063 ps
CPU time 2.23 seconds
Started Jan 03 12:37:31 PM PST 24
Finished Jan 03 12:38:41 PM PST 24
Peak memory 206004 kb
Host smart-f9206a1b-099f-428e-9afb-b5a18fe7446b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100239309 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.1100239309
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.3328073715
Short name T291
Test name
Test status
Simulation time 20772617 ps
CPU time 0.84 seconds
Started Jan 03 12:37:27 PM PST 24
Finished Jan 03 12:38:37 PM PST 24
Peak memory 205668 kb
Host smart-4bb627ad-c8c9-4721-a6c0-d456f46bd4de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328073715 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.3328073715
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.4258727907
Short name T28
Test name
Test status
Simulation time 14989969 ps
CPU time 0.85 seconds
Started Jan 03 12:37:15 PM PST 24
Finished Jan 03 12:38:24 PM PST 24
Peak memory 205984 kb
Host smart-4c1819e7-29a9-4b23-bec7-e2ba584082ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258727907 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.4258727907
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.2804839992
Short name T350
Test name
Test status
Simulation time 21776125 ps
CPU time 0.79 seconds
Started Jan 03 12:37:29 PM PST 24
Finished Jan 03 12:38:51 PM PST 24
Peak memory 205904 kb
Host smart-9c462277-2173-4235-a15d-1c57f593ad73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804839992 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.2804839992
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.1904707509
Short name T340
Test name
Test status
Simulation time 20916044 ps
CPU time 0.79 seconds
Started Jan 03 12:37:08 PM PST 24
Finished Jan 03 12:38:15 PM PST 24
Peak memory 205880 kb
Host smart-f8cc8a2d-9399-44b7-9747-5a914b1db928
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904707509 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.1904707509
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.941092072
Short name T344
Test name
Test status
Simulation time 16184351 ps
CPU time 0.87 seconds
Started Jan 03 12:37:18 PM PST 24
Finished Jan 03 12:38:32 PM PST 24
Peak memory 206044 kb
Host smart-be8c7255-76dd-467a-b806-2f6e38a98ccc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941092072 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.941092072
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.2000658503
Short name T292
Test name
Test status
Simulation time 112809622 ps
CPU time 0.84 seconds
Started Jan 03 12:37:27 PM PST 24
Finished Jan 03 12:38:37 PM PST 24
Peak memory 205824 kb
Host smart-0c82b804-4e17-4df3-90c0-3f60ee468621
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000658503 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.2000658503
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.836926859
Short name T165
Test name
Test status
Simulation time 66267714 ps
CPU time 0.85 seconds
Started Jan 03 12:37:25 PM PST 24
Finished Jan 03 12:38:34 PM PST 24
Peak memory 205904 kb
Host smart-bde7cb6d-ef69-4906-b3f6-00370a59d382
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836926859 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.836926859
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.802076781
Short name T306
Test name
Test status
Simulation time 57130291 ps
CPU time 0.8 seconds
Started Jan 03 12:37:02 PM PST 24
Finished Jan 03 12:38:24 PM PST 24
Peak memory 205880 kb
Host smart-609a9d9d-f742-4008-beea-70acfeed1890
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802076781 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.802076781
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.4017007895
Short name T342
Test name
Test status
Simulation time 11586894 ps
CPU time 0.77 seconds
Started Jan 03 12:37:24 PM PST 24
Finished Jan 03 12:38:38 PM PST 24
Peak memory 205668 kb
Host smart-40571b05-a901-4aff-8115-1d5cc9d3dd84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017007895 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.4017007895
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.3605597253
Short name T357
Test name
Test status
Simulation time 24722726 ps
CPU time 0.83 seconds
Started Jan 03 12:37:22 PM PST 24
Finished Jan 03 12:38:54 PM PST 24
Peak memory 205992 kb
Host smart-e5b66ec5-e125-4132-8f90-21746dbbf077
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605597253 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.3605597253
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1495381067
Short name T335
Test name
Test status
Simulation time 28211740 ps
CPU time 0.93 seconds
Started Jan 03 12:37:08 PM PST 24
Finished Jan 03 12:38:15 PM PST 24
Peak memory 206016 kb
Host smart-845d7fa1-1d00-4b84-a0e2-691608334c42
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495381067 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.1495381067
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2145699249
Short name T353
Test name
Test status
Simulation time 59561580 ps
CPU time 3.16 seconds
Started Jan 03 12:37:24 PM PST 24
Finished Jan 03 12:38:36 PM PST 24
Peak memory 206028 kb
Host smart-932c8a73-b085-4c09-86dd-97f44193f376
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145699249 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.2145699249
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.491419318
Short name T920
Test name
Test status
Simulation time 13537953 ps
CPU time 0.83 seconds
Started Jan 03 12:37:03 PM PST 24
Finished Jan 03 12:38:22 PM PST 24
Peak memory 205868 kb
Host smart-828d9446-ae9e-440a-a03e-e10f6d2da07f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491419318 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.491419318
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1967892997
Short name T931
Test name
Test status
Simulation time 272611941 ps
CPU time 1.24 seconds
Started Jan 03 12:37:25 PM PST 24
Finished Jan 03 12:38:42 PM PST 24
Peak memory 214204 kb
Host smart-97e00f02-5309-43b2-8dc5-3a6111172bb1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967892997 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.1967892997
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.1145985605
Short name T145
Test name
Test status
Simulation time 19168036 ps
CPU time 0.87 seconds
Started Jan 03 12:37:37 PM PST 24
Finished Jan 03 12:38:49 PM PST 24
Peak memory 205892 kb
Host smart-9a2a36a4-3004-4899-8356-ae03fd51e68f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145985605 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.1145985605
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.3965080482
Short name T354
Test name
Test status
Simulation time 70635514 ps
CPU time 0.79 seconds
Started Jan 03 12:37:06 PM PST 24
Finished Jan 03 12:38:21 PM PST 24
Peak memory 205888 kb
Host smart-0d321fa3-e712-4767-b36f-ed2873825c79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965080482 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.3965080482
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.453884436
Short name T320
Test name
Test status
Simulation time 33637239 ps
CPU time 0.89 seconds
Started Jan 03 12:37:15 PM PST 24
Finished Jan 03 12:38:23 PM PST 24
Peak memory 205892 kb
Host smart-a957e14e-a6ea-477e-9fc8-0e190afecaca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453884436 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_out
standing.453884436
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.3596988542
Short name T923
Test name
Test status
Simulation time 168587602 ps
CPU time 3.04 seconds
Started Jan 03 12:37:20 PM PST 24
Finished Jan 03 12:38:43 PM PST 24
Peak memory 214192 kb
Host smart-c2446cea-f846-42dc-82de-1e5d1e31c197
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596988542 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.3596988542
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2882062115
Short name T144
Test name
Test status
Simulation time 739712586 ps
CPU time 1.55 seconds
Started Jan 03 12:37:28 PM PST 24
Finished Jan 03 12:38:43 PM PST 24
Peak memory 205864 kb
Host smart-71ef0c3b-a4eb-4c7a-a8de-796b4a5f3751
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882062115 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.2882062115
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.3198185565
Short name T25
Test name
Test status
Simulation time 89122874 ps
CPU time 0.82 seconds
Started Jan 03 12:36:51 PM PST 24
Finished Jan 03 12:38:07 PM PST 24
Peak memory 205736 kb
Host smart-cda1d32e-e934-45d8-8d05-d1e6c07a6553
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198185565 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.3198185565
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.2839077791
Short name T299
Test name
Test status
Simulation time 136642965 ps
CPU time 0.74 seconds
Started Jan 03 12:37:22 PM PST 24
Finished Jan 03 12:38:55 PM PST 24
Peak memory 205792 kb
Host smart-0174e08a-dbfb-452f-a3d8-e9a581c48e7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839077791 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.2839077791
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.2452505962
Short name T312
Test name
Test status
Simulation time 100015101 ps
CPU time 0.8 seconds
Started Jan 03 12:37:12 PM PST 24
Finished Jan 03 12:38:34 PM PST 24
Peak memory 205796 kb
Host smart-dba7e159-f90b-42e5-8927-de48ffdfaac6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452505962 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2452505962
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.472933442
Short name T313
Test name
Test status
Simulation time 25130720 ps
CPU time 0.77 seconds
Started Jan 03 12:37:07 PM PST 24
Finished Jan 03 12:38:19 PM PST 24
Peak memory 205804 kb
Host smart-65bcbdae-9edb-4efc-b5a8-35194f10a2d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472933442 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.472933442
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.3891872188
Short name T21
Test name
Test status
Simulation time 30348862 ps
CPU time 0.75 seconds
Started Jan 03 12:37:17 PM PST 24
Finished Jan 03 12:38:27 PM PST 24
Peak memory 205792 kb
Host smart-968e904a-4bef-4c9c-bef5-376196a8c1a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891872188 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.3891872188
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.3162961453
Short name T295
Test name
Test status
Simulation time 40254319 ps
CPU time 0.79 seconds
Started Jan 03 12:37:19 PM PST 24
Finished Jan 03 12:39:00 PM PST 24
Peak memory 205784 kb
Host smart-9fa20009-b6f5-41ea-83da-09dd4750a031
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162961453 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.3162961453
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.2178920094
Short name T325
Test name
Test status
Simulation time 111205859 ps
CPU time 0.87 seconds
Started Jan 03 12:37:10 PM PST 24
Finished Jan 03 12:38:25 PM PST 24
Peak memory 205992 kb
Host smart-58e29828-7ff9-450b-9ab1-50c9fa67e1fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178920094 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.2178920094
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.3924519637
Short name T924
Test name
Test status
Simulation time 50878927 ps
CPU time 0.83 seconds
Started Jan 03 12:37:07 PM PST 24
Finished Jan 03 12:38:27 PM PST 24
Peak memory 205920 kb
Host smart-d7d7afa9-c84a-4e30-a652-36c131246a86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924519637 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.3924519637
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.1610757465
Short name T290
Test name
Test status
Simulation time 24395391 ps
CPU time 0.84 seconds
Started Jan 03 12:37:09 PM PST 24
Finished Jan 03 12:38:17 PM PST 24
Peak memory 205992 kb
Host smart-b0f2db10-c002-4ea7-8579-fb89bfc8dd65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610757465 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.1610757465
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.670927358
Short name T155
Test name
Test status
Simulation time 21323192 ps
CPU time 0.89 seconds
Started Jan 03 12:37:35 PM PST 24
Finished Jan 03 12:38:53 PM PST 24
Peak memory 205892 kb
Host smart-b071f76c-edf8-4c34-8e46-799eb5bb7b8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670927358 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.670927358
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2960755165
Short name T135
Test name
Test status
Simulation time 22648621 ps
CPU time 1.06 seconds
Started Jan 03 12:36:43 PM PST 24
Finished Jan 03 12:37:58 PM PST 24
Peak memory 206012 kb
Host smart-3437d76c-5c94-4203-ba14-d538b651e31a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960755165 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.2960755165
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2099670260
Short name T174
Test name
Test status
Simulation time 110513272 ps
CPU time 3.06 seconds
Started Jan 03 12:36:56 PM PST 24
Finished Jan 03 12:38:13 PM PST 24
Peak memory 205948 kb
Host smart-7567e2ff-0c6a-4f3a-a220-67dd0816575d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099670260 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.2099670260
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.449079584
Short name T332
Test name
Test status
Simulation time 27443178 ps
CPU time 0.86 seconds
Started Jan 03 12:36:34 PM PST 24
Finished Jan 03 12:37:53 PM PST 24
Peak memory 205992 kb
Host smart-98ab8879-2bb5-4ba5-a8ad-114380a73772
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449079584 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.449079584
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2981996993
Short name T128
Test name
Test status
Simulation time 27538361 ps
CPU time 0.94 seconds
Started Jan 03 12:37:13 PM PST 24
Finished Jan 03 12:38:35 PM PST 24
Peak memory 214184 kb
Host smart-4ec6c95b-3342-496d-941a-28278129cb08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981996993 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.2981996993
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.2646080153
Short name T164
Test name
Test status
Simulation time 45681881 ps
CPU time 0.83 seconds
Started Jan 03 12:36:35 PM PST 24
Finished Jan 03 12:37:53 PM PST 24
Peak memory 206012 kb
Host smart-e15ea3cc-253b-48a9-a973-965e60837e75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646080153 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2646080153
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.2645903725
Short name T311
Test name
Test status
Simulation time 16933857 ps
CPU time 0.77 seconds
Started Jan 03 12:37:06 PM PST 24
Finished Jan 03 12:38:13 PM PST 24
Peak memory 205920 kb
Host smart-51421a7d-820a-44c2-9deb-8b9713efc61f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645903725 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.2645903725
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.503817971
Short name T925
Test name
Test status
Simulation time 33913121 ps
CPU time 0.96 seconds
Started Jan 03 12:36:51 PM PST 24
Finished Jan 03 12:38:07 PM PST 24
Peak memory 205920 kb
Host smart-7ba4944d-0225-4cef-90ca-7dda4a86d09f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503817971 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_out
standing.503817971
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.2653212431
Short name T934
Test name
Test status
Simulation time 57285528 ps
CPU time 2.04 seconds
Started Jan 03 12:37:10 PM PST 24
Finished Jan 03 12:38:19 PM PST 24
Peak memory 214232 kb
Host smart-ba33d168-5c8a-4b4d-b5a8-c29f15085a53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653212431 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.2653212431
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.4156960884
Short name T346
Test name
Test status
Simulation time 13390641 ps
CPU time 0.82 seconds
Started Jan 03 12:37:13 PM PST 24
Finished Jan 03 12:38:25 PM PST 24
Peak memory 205880 kb
Host smart-1cb4a22a-23cf-46e2-9c5e-cd74d20c6ae8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156960884 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.4156960884
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.2597900225
Short name T307
Test name
Test status
Simulation time 79865709 ps
CPU time 0.78 seconds
Started Jan 03 12:37:28 PM PST 24
Finished Jan 03 12:38:55 PM PST 24
Peak memory 205804 kb
Host smart-d2771aac-9bab-4723-946e-fce05971d5db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597900225 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.2597900225
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.401824395
Short name T294
Test name
Test status
Simulation time 54130158 ps
CPU time 0.83 seconds
Started Jan 03 12:37:17 PM PST 24
Finished Jan 03 12:38:27 PM PST 24
Peak memory 205888 kb
Host smart-2bcf4cc6-a062-49b9-b260-c9f88598af28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401824395 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.401824395
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.293147668
Short name T323
Test name
Test status
Simulation time 15998329 ps
CPU time 0.88 seconds
Started Jan 03 12:37:17 PM PST 24
Finished Jan 03 12:38:32 PM PST 24
Peak memory 205984 kb
Host smart-db4d85e0-9167-4376-94cf-835e9a7433d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293147668 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.293147668
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.2290140456
Short name T149
Test name
Test status
Simulation time 51704236 ps
CPU time 0.82 seconds
Started Jan 03 12:37:15 PM PST 24
Finished Jan 03 12:38:24 PM PST 24
Peak memory 205900 kb
Host smart-417b15b2-eedd-46cb-a437-4a070c8d32e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290140456 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.2290140456
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.3157439003
Short name T150
Test name
Test status
Simulation time 64024135 ps
CPU time 0.79 seconds
Started Jan 03 12:37:48 PM PST 24
Finished Jan 03 12:39:07 PM PST 24
Peak memory 206032 kb
Host smart-b9b806f9-e391-4068-a366-5b1819e52d76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157439003 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.3157439003
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.1803297697
Short name T298
Test name
Test status
Simulation time 41260824 ps
CPU time 0.78 seconds
Started Jan 03 12:37:23 PM PST 24
Finished Jan 03 12:38:45 PM PST 24
Peak memory 205688 kb
Host smart-0b60dd5c-6770-424d-9a61-b95745f04211
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803297697 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1803297697
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.2903126150
Short name T154
Test name
Test status
Simulation time 27064763 ps
CPU time 0.83 seconds
Started Jan 03 12:37:25 PM PST 24
Finished Jan 03 12:38:39 PM PST 24
Peak memory 205948 kb
Host smart-b9b21a0c-0df4-480f-8103-fb69533b2d43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903126150 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.2903126150
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.2948908185
Short name T300
Test name
Test status
Simulation time 31589494 ps
CPU time 0.76 seconds
Started Jan 03 12:37:00 PM PST 24
Finished Jan 03 12:38:08 PM PST 24
Peak memory 205796 kb
Host smart-a9d81a5a-c568-4457-9b01-7f9a4f455bd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948908185 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.2948908185
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.4047948463
Short name T143
Test name
Test status
Simulation time 22216198 ps
CPU time 1.12 seconds
Started Jan 03 12:36:52 PM PST 24
Finished Jan 03 12:38:10 PM PST 24
Peak memory 214416 kb
Host smart-9c6b86e9-7fdc-4ef2-840f-e867d052210c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047948463 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.4047948463
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.56661113
Short name T926
Test name
Test status
Simulation time 84442057 ps
CPU time 0.75 seconds
Started Jan 03 12:36:47 PM PST 24
Finished Jan 03 12:38:06 PM PST 24
Peak memory 205800 kb
Host smart-157369fe-761d-4125-ab7d-6976a7b39ba3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56661113 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.56661113
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.1557140936
Short name T331
Test name
Test status
Simulation time 11866542 ps
CPU time 0.79 seconds
Started Jan 03 12:36:39 PM PST 24
Finished Jan 03 12:38:00 PM PST 24
Peak memory 205920 kb
Host smart-8c403ea3-4eac-4fb0-baf8-218f256c5744
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557140936 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.1557140936
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.3806385306
Short name T329
Test name
Test status
Simulation time 130382492 ps
CPU time 2.22 seconds
Started Jan 03 12:36:33 PM PST 24
Finished Jan 03 12:38:08 PM PST 24
Peak memory 214288 kb
Host smart-de65583a-60fd-4026-ac09-471f24055962
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806385306 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.3806385306
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3895322138
Short name T26
Test name
Test status
Simulation time 180225270 ps
CPU time 3.56 seconds
Started Jan 03 12:37:06 PM PST 24
Finished Jan 03 12:38:24 PM PST 24
Peak memory 206012 kb
Host smart-643c74f8-fc17-4a04-8de8-9b2bd62539ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895322138 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.3895322138
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3039994502
Short name T288
Test name
Test status
Simulation time 25920685 ps
CPU time 1.74 seconds
Started Jan 03 12:37:15 PM PST 24
Finished Jan 03 12:38:24 PM PST 24
Peak memory 214208 kb
Host smart-d33f781e-abf0-4d5f-9986-03db56e69d84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039994502 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.3039994502
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.3883584400
Short name T23
Test name
Test status
Simulation time 45385824 ps
CPU time 0.83 seconds
Started Jan 03 12:36:50 PM PST 24
Finished Jan 03 12:38:22 PM PST 24
Peak memory 205872 kb
Host smart-3b341466-621c-4f8d-b92e-f5c24fc124c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883584400 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.3883584400
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.1481263190
Short name T169
Test name
Test status
Simulation time 25257733 ps
CPU time 0.83 seconds
Started Jan 03 12:37:07 PM PST 24
Finished Jan 03 12:38:16 PM PST 24
Peak memory 205928 kb
Host smart-49fdc5ee-200b-4172-8282-5ef2c6b19c13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481263190 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.1481263190
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2310982446
Short name T356
Test name
Test status
Simulation time 102825786 ps
CPU time 1.06 seconds
Started Jan 03 12:37:11 PM PST 24
Finished Jan 03 12:38:21 PM PST 24
Peak memory 206004 kb
Host smart-097f3df8-2fc7-48e1-9533-dc349baf5327
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310982446 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.2310982446
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.1250706653
Short name T136
Test name
Test status
Simulation time 231941954 ps
CPU time 2.17 seconds
Started Jan 03 12:37:06 PM PST 24
Finished Jan 03 12:38:18 PM PST 24
Peak memory 214116 kb
Host smart-25ec01d0-d8f2-4ee9-bbcc-f3f565ee08a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250706653 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.1250706653
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1909371048
Short name T922
Test name
Test status
Simulation time 46575241 ps
CPU time 1.44 seconds
Started Jan 03 12:36:24 PM PST 24
Finished Jan 03 12:37:58 PM PST 24
Peak memory 206004 kb
Host smart-b1f001a0-5fcc-4729-a3e2-586e8a302651
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909371048 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.1909371048
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2367922521
Short name T928
Test name
Test status
Simulation time 35879474 ps
CPU time 1.13 seconds
Started Jan 03 12:37:08 PM PST 24
Finished Jan 03 12:38:19 PM PST 24
Peak memory 214144 kb
Host smart-3e2f9545-bc80-4274-bf6a-23d7d0b39c3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367922521 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2367922521
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.502699942
Short name T177
Test name
Test status
Simulation time 25664467 ps
CPU time 0.84 seconds
Started Jan 03 12:37:21 PM PST 24
Finished Jan 03 12:38:35 PM PST 24
Peak memory 206000 kb
Host smart-dbba8154-0610-410e-a750-6184d30980b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502699942 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.502699942
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.242033297
Short name T182
Test name
Test status
Simulation time 30855463 ps
CPU time 0.77 seconds
Started Jan 03 12:36:54 PM PST 24
Finished Jan 03 12:38:04 PM PST 24
Peak memory 205820 kb
Host smart-66fd18bd-ce7f-4a0e-927c-43d4d10eb977
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242033297 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.242033297
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3940128403
Short name T930
Test name
Test status
Simulation time 45503904 ps
CPU time 0.9 seconds
Started Jan 03 12:36:51 PM PST 24
Finished Jan 03 12:38:21 PM PST 24
Peak memory 205972 kb
Host smart-5823b455-e413-4bbf-ac7f-ec0ccab02804
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940128403 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.3940128403
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.30975126
Short name T355
Test name
Test status
Simulation time 132161975 ps
CPU time 2.33 seconds
Started Jan 03 12:37:00 PM PST 24
Finished Jan 03 12:38:20 PM PST 24
Peak memory 214392 kb
Host smart-3720ca1c-4f42-4c38-9d30-17f2e5039119
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30975126 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.30975126
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3178090521
Short name T24
Test name
Test status
Simulation time 141566308 ps
CPU time 1.35 seconds
Started Jan 03 12:36:51 PM PST 24
Finished Jan 03 12:38:22 PM PST 24
Peak memory 206004 kb
Host smart-5cc3fe05-d7b9-42b2-bc27-6399d8172e50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178090521 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.3178090521
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.352829033
Short name T132
Test name
Test status
Simulation time 23034003 ps
CPU time 1.18 seconds
Started Jan 03 12:36:17 PM PST 24
Finished Jan 03 12:38:16 PM PST 24
Peak memory 214248 kb
Host smart-64b19ed8-7c3b-4007-9497-83aa11cd6856
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352829033 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.352829033
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.210921024
Short name T148
Test name
Test status
Simulation time 12810774 ps
CPU time 0.83 seconds
Started Jan 03 12:37:14 PM PST 24
Finished Jan 03 12:38:23 PM PST 24
Peak memory 205608 kb
Host smart-fddae8bc-ce75-47a2-82f2-197913a7a388
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210921024 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.210921024
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.2362187790
Short name T308
Test name
Test status
Simulation time 29190875 ps
CPU time 0.8 seconds
Started Jan 03 12:36:41 PM PST 24
Finished Jan 03 12:37:57 PM PST 24
Peak memory 205668 kb
Host smart-78a8e98d-5d7b-403b-a606-f04424de0ed0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362187790 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.2362187790
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2762218995
Short name T141
Test name
Test status
Simulation time 43751054 ps
CPU time 1.03 seconds
Started Jan 03 12:36:47 PM PST 24
Finished Jan 03 12:38:07 PM PST 24
Peak memory 205980 kb
Host smart-d77080c0-a480-41f0-8933-0e7d1a82dee2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762218995 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.2762218995
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.964018986
Short name T302
Test name
Test status
Simulation time 48224334 ps
CPU time 1.54 seconds
Started Jan 03 12:37:07 PM PST 24
Finished Jan 03 12:38:20 PM PST 24
Peak memory 214252 kb
Host smart-7df2a627-88d9-4e9d-b9bc-ed2ccf781e67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964018986 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.964018986
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.3705951809
Short name T159
Test name
Test status
Simulation time 823825599 ps
CPU time 2.06 seconds
Started Jan 03 12:37:28 PM PST 24
Finished Jan 03 12:38:39 PM PST 24
Peak memory 205924 kb
Host smart-18360305-b15a-49d5-ae17-02bf541ef782
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705951809 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.3705951809
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2807093161
Short name T324
Test name
Test status
Simulation time 33334498 ps
CPU time 0.89 seconds
Started Jan 03 12:36:55 PM PST 24
Finished Jan 03 12:38:21 PM PST 24
Peak memory 206164 kb
Host smart-c14fc42f-8b9a-4eb7-a36b-e7916619d021
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807093161 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.2807093161
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.2770468297
Short name T183
Test name
Test status
Simulation time 17547168 ps
CPU time 0.76 seconds
Started Jan 03 12:37:06 PM PST 24
Finished Jan 03 12:38:13 PM PST 24
Peak memory 205724 kb
Host smart-20d65484-b058-49e2-9e5f-ec5a50d852ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770468297 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.2770468297
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.2577910454
Short name T296
Test name
Test status
Simulation time 11766179 ps
CPU time 0.79 seconds
Started Jan 03 12:37:07 PM PST 24
Finished Jan 03 12:38:19 PM PST 24
Peak memory 205912 kb
Host smart-a2efd0d5-26d7-4b1d-9e6a-c2aac61c2bf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577910454 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.2577910454
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1172099054
Short name T326
Test name
Test status
Simulation time 21194179 ps
CPU time 1.1 seconds
Started Jan 03 12:37:23 PM PST 24
Finished Jan 03 12:39:04 PM PST 24
Peak memory 205980 kb
Host smart-17fbcb57-b078-4f0a-85da-65b2c162bf46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172099054 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.1172099054
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.3483201024
Short name T361
Test name
Test status
Simulation time 50085978 ps
CPU time 1.88 seconds
Started Jan 03 12:37:10 PM PST 24
Finished Jan 03 12:38:18 PM PST 24
Peak memory 214264 kb
Host smart-21552f46-4153-4af9-98b7-7fa7081e4b9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483201024 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.3483201024
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.816794632
Short name T352
Test name
Test status
Simulation time 53249015 ps
CPU time 1.69 seconds
Started Jan 03 12:37:20 PM PST 24
Finished Jan 03 12:38:42 PM PST 24
Peak memory 205684 kb
Host smart-f85a8569-1914-4e5a-9e21-7f8379586d72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816794632 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.816794632
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.1958532539
Short name T191
Test name
Test status
Simulation time 22298930 ps
CPU time 0.95 seconds
Started Jan 03 12:45:25 PM PST 24
Finished Jan 03 12:47:04 PM PST 24
Peak memory 205944 kb
Host smart-ddbcd873-375e-4334-a54e-e2ca5ebbe53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958532539 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.1958532539
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.3969305247
Short name T485
Test name
Test status
Simulation time 27340064 ps
CPU time 0.83 seconds
Started Jan 03 12:44:58 PM PST 24
Finished Jan 03 12:46:31 PM PST 24
Peak memory 205596 kb
Host smart-84d368d5-d3a2-4e5a-86ce-0bb5f747254c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969305247 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.3969305247
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.177876423
Short name T606
Test name
Test status
Simulation time 376298804 ps
CPU time 1.2 seconds
Started Jan 03 12:44:54 PM PST 24
Finished Jan 03 12:46:25 PM PST 24
Peak memory 214648 kb
Host smart-e5762797-aa3f-45d0-b7e2-7bd6a21116d3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177876423 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_dis
able_auto_req_mode.177876423
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.1283821717
Short name T416
Test name
Test status
Simulation time 20431908 ps
CPU time 0.91 seconds
Started Jan 03 12:44:35 PM PST 24
Finished Jan 03 12:46:15 PM PST 24
Peak memory 215636 kb
Host smart-ce1c0a0d-7330-4c64-aa9f-1ebbfb936652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283821717 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.1283821717
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_smoke.2407081678
Short name T549
Test name
Test status
Simulation time 19701498 ps
CPU time 0.82 seconds
Started Jan 03 12:45:00 PM PST 24
Finished Jan 03 12:46:35 PM PST 24
Peak memory 204852 kb
Host smart-9023790e-2024-4eb4-9065-00d9312c280f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407081678 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.2407081678
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.4220935345
Short name T802
Test name
Test status
Simulation time 48741768 ps
CPU time 1.47 seconds
Started Jan 03 12:44:53 PM PST 24
Finished Jan 03 12:46:27 PM PST 24
Peak memory 205760 kb
Host smart-6708ad77-9099-4020-b773-11451d56a11d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220935345 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.4220935345
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.1060081647
Short name T700
Test name
Test status
Simulation time 84745788363 ps
CPU time 1335.51 seconds
Started Jan 03 12:44:53 PM PST 24
Finished Jan 03 01:08:32 PM PST 24
Peak memory 219764 kb
Host smart-5cf3631b-126e-4b69-b159-7fadc723ced4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060081647 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.1060081647
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert_test.2508360752
Short name T917
Test name
Test status
Simulation time 56578140 ps
CPU time 0.87 seconds
Started Jan 03 12:44:50 PM PST 24
Finished Jan 03 12:46:31 PM PST 24
Peak memory 204552 kb
Host smart-c7e2652d-4b16-4d51-b51b-8fb4ee8b1618
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508360752 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.2508360752
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.54391395
Short name T895
Test name
Test status
Simulation time 19756186 ps
CPU time 0.99 seconds
Started Jan 03 12:45:25 PM PST 24
Finished Jan 03 12:47:04 PM PST 24
Peak memory 214500 kb
Host smart-a4c78ff2-d915-4ed5-b295-1080a9b3c679
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54391395 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disa
ble_auto_req_mode.54391395
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.3886032582
Short name T509
Test name
Test status
Simulation time 74354404 ps
CPU time 1.12 seconds
Started Jan 03 12:45:13 PM PST 24
Finished Jan 03 12:46:46 PM PST 24
Peak memory 214784 kb
Host smart-018b648f-54b9-40ec-9b23-6e0eed3df9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886032582 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.3886032582
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_intr.2814474979
Short name T48
Test name
Test status
Simulation time 19820023 ps
CPU time 1.12 seconds
Started Jan 03 12:45:04 PM PST 24
Finished Jan 03 12:46:38 PM PST 24
Peak memory 221992 kb
Host smart-e9c07cd8-8f5b-43da-b0e5-1fc5b21adb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814474979 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.2814474979
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_smoke.1717383164
Short name T80
Test name
Test status
Simulation time 41991666 ps
CPU time 0.83 seconds
Started Jan 03 12:44:49 PM PST 24
Finished Jan 03 12:46:44 PM PST 24
Peak memory 204588 kb
Host smart-939dc72a-bc1c-4c71-aa5c-2799fd777844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717383164 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1717383164
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.2201106757
Short name T714
Test name
Test status
Simulation time 49248697603 ps
CPU time 1200.16 seconds
Started Jan 03 12:44:40 PM PST 24
Finished Jan 03 01:06:08 PM PST 24
Peak memory 217012 kb
Host smart-a616ea5b-be60-4929-b178-5e1fce971076
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201106757 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.2201106757
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.2560470795
Short name T618
Test name
Test status
Simulation time 70579187 ps
CPU time 0.93 seconds
Started Jan 03 12:45:35 PM PST 24
Finished Jan 03 12:47:05 PM PST 24
Peak memory 205168 kb
Host smart-72679d54-d490-4b1e-b96f-fd31a683b2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560470795 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.2560470795
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_disable.3872994084
Short name T431
Test name
Test status
Simulation time 22112848 ps
CPU time 0.82 seconds
Started Jan 03 12:45:02 PM PST 24
Finished Jan 03 12:46:35 PM PST 24
Peak memory 214304 kb
Host smart-a83dbe40-5744-4b78-af32-ba8035bec7d5
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872994084 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.3872994084
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_err.670879262
Short name T516
Test name
Test status
Simulation time 38263560 ps
CPU time 0.83 seconds
Started Jan 03 12:45:15 PM PST 24
Finished Jan 03 12:46:45 PM PST 24
Peak memory 215884 kb
Host smart-fa07c1bc-0f55-4531-8fc9-7d88d930ac81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670879262 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.670879262
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.1620606894
Short name T890
Test name
Test status
Simulation time 23978997 ps
CPU time 1.09 seconds
Started Jan 03 12:45:38 PM PST 24
Finished Jan 03 12:47:19 PM PST 24
Peak memory 214276 kb
Host smart-4a4ff1cc-1112-40a2-8e5e-976782f1a494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620606894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.1620606894
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.3792266043
Short name T479
Test name
Test status
Simulation time 26737327 ps
CPU time 0.92 seconds
Started Jan 03 12:45:07 PM PST 24
Finished Jan 03 12:46:37 PM PST 24
Peak memory 214456 kb
Host smart-25f0f523-20e9-474f-99f1-405940425ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792266043 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.3792266043
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.3527242069
Short name T640
Test name
Test status
Simulation time 27129655 ps
CPU time 0.85 seconds
Started Jan 03 12:45:13 PM PST 24
Finished Jan 03 12:46:42 PM PST 24
Peak memory 205068 kb
Host smart-380d2318-6035-48dc-81e3-4f668ea6618d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527242069 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.3527242069
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.169258716
Short name T681
Test name
Test status
Simulation time 234514086 ps
CPU time 1.8 seconds
Started Jan 03 12:44:55 PM PST 24
Finished Jan 03 12:46:26 PM PST 24
Peak memory 205952 kb
Host smart-fd12989e-97df-479f-b914-b452ec874b76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169258716 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.169258716
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.2418975235
Short name T411
Test name
Test status
Simulation time 331200395971 ps
CPU time 1805.58 seconds
Started Jan 03 12:44:59 PM PST 24
Finished Jan 03 01:16:45 PM PST 24
Peak memory 219508 kb
Host smart-b456eb01-5fda-48b3-bc15-8d529cd352fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418975235 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.2418975235
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.1402095887
Short name T285
Test name
Test status
Simulation time 57237963 ps
CPU time 1.32 seconds
Started Jan 03 12:46:23 PM PST 24
Finished Jan 03 12:47:43 PM PST 24
Peak memory 214204 kb
Host smart-6a71e9d4-5c67-4636-80f9-e4fce7d0999c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402095887 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.1402095887
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.763951654
Short name T722
Test name
Test status
Simulation time 62093437 ps
CPU time 1.11 seconds
Started Jan 03 12:46:31 PM PST 24
Finished Jan 03 12:47:45 PM PST 24
Peak memory 205580 kb
Host smart-642a1e3c-df9b-4ee0-b637-52a368914590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763951654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.763951654
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.3743294299
Short name T805
Test name
Test status
Simulation time 40005398 ps
CPU time 0.97 seconds
Started Jan 03 12:46:26 PM PST 24
Finished Jan 03 12:47:50 PM PST 24
Peak memory 205336 kb
Host smart-c40172a2-6b6e-49d6-8106-a0a775f6f55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743294299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.3743294299
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.3203377975
Short name T817
Test name
Test status
Simulation time 29901743 ps
CPU time 1.07 seconds
Started Jan 03 12:46:31 PM PST 24
Finished Jan 03 12:47:50 PM PST 24
Peak memory 214336 kb
Host smart-7443b847-083d-44e1-84b3-c899d516c49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203377975 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.3203377975
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.203603496
Short name T454
Test name
Test status
Simulation time 28639203 ps
CPU time 0.93 seconds
Started Jan 03 12:46:49 PM PST 24
Finished Jan 03 12:47:57 PM PST 24
Peak memory 205524 kb
Host smart-e9e93417-1369-44da-a6bc-2c097ab4a148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203603496 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.203603496
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.1839940822
Short name T424
Test name
Test status
Simulation time 19713711 ps
CPU time 1.06 seconds
Started Jan 03 12:46:59 PM PST 24
Finished Jan 03 12:48:02 PM PST 24
Peak memory 205552 kb
Host smart-3c996580-0fd7-4a44-b90d-e79fdbf3df83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839940822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.1839940822
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.2802900750
Short name T232
Test name
Test status
Simulation time 26540533 ps
CPU time 0.89 seconds
Started Jan 03 12:46:19 PM PST 24
Finished Jan 03 12:47:39 PM PST 24
Peak memory 205072 kb
Host smart-ed7eae37-aa43-4ce6-b0c4-40cb8a48d423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802900750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.2802900750
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.752742079
Short name T491
Test name
Test status
Simulation time 28824012 ps
CPU time 0.99 seconds
Started Jan 03 12:46:49 PM PST 24
Finished Jan 03 12:47:58 PM PST 24
Peak memory 214156 kb
Host smart-d7f3b143-feb9-4af1-8005-a31391a9ffdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752742079 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.752742079
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.1498157630
Short name T844
Test name
Test status
Simulation time 32657358 ps
CPU time 0.95 seconds
Started Jan 03 12:46:42 PM PST 24
Finished Jan 03 12:47:53 PM PST 24
Peak memory 205652 kb
Host smart-e4ae8778-1fa9-439e-b157-b08313350bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498157630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.1498157630
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.3538577624
Short name T190
Test name
Test status
Simulation time 60258443 ps
CPU time 0.93 seconds
Started Jan 03 12:45:50 PM PST 24
Finished Jan 03 12:47:19 PM PST 24
Peak memory 206008 kb
Host smart-82f33ecc-3d25-4be5-bc3a-6c7c15935ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538577624 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.3538577624
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.1826083214
Short name T86
Test name
Test status
Simulation time 50614812 ps
CPU time 1.01 seconds
Started Jan 03 12:45:07 PM PST 24
Finished Jan 03 12:46:41 PM PST 24
Peak memory 214496 kb
Host smart-4a2fdc6c-706c-4048-8f88-b9d9a09e9fc6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826083214 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.1826083214
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_genbits.2181882169
Short name T421
Test name
Test status
Simulation time 35900988 ps
CPU time 1.18 seconds
Started Jan 03 12:45:05 PM PST 24
Finished Jan 03 12:46:45 PM PST 24
Peak memory 205852 kb
Host smart-f71dbf8a-28c8-4543-8903-5d523ff65bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181882169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.2181882169
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_smoke.2750183617
Short name T818
Test name
Test status
Simulation time 12597583 ps
CPU time 0.87 seconds
Started Jan 03 12:45:09 PM PST 24
Finished Jan 03 12:46:44 PM PST 24
Peak memory 205000 kb
Host smart-6b9cc86e-1812-44ef-9c40-12fe5ca6c99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750183617 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.2750183617
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.1642013266
Short name T83
Test name
Test status
Simulation time 235779505 ps
CPU time 2.45 seconds
Started Jan 03 12:45:22 PM PST 24
Finished Jan 03 12:47:03 PM PST 24
Peak memory 206184 kb
Host smart-1207440e-4b04-4a3a-b975-1d73e77d4924
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642013266 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1642013266
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.3649029071
Short name T838
Test name
Test status
Simulation time 26903879971 ps
CPU time 599.07 seconds
Started Jan 03 12:45:29 PM PST 24
Finished Jan 03 12:57:06 PM PST 24
Peak memory 215988 kb
Host smart-07ebdeed-ef8a-4224-aa4b-99e179612a6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649029071 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.3649029071
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.3662865685
Short name T743
Test name
Test status
Simulation time 33276077 ps
CPU time 0.79 seconds
Started Jan 03 12:46:26 PM PST 24
Finished Jan 03 12:47:56 PM PST 24
Peak memory 205052 kb
Host smart-caa249e3-3c74-48e5-bc11-817a174ff2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662865685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.3662865685
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.804369660
Short name T238
Test name
Test status
Simulation time 14615198 ps
CPU time 0.95 seconds
Started Jan 03 12:46:27 PM PST 24
Finished Jan 03 12:47:45 PM PST 24
Peak memory 205620 kb
Host smart-53ae7454-0d21-48e4-b3fa-e15543c69808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804369660 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.804369660
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.2333191242
Short name T262
Test name
Test status
Simulation time 24825204 ps
CPU time 0.85 seconds
Started Jan 03 12:46:27 PM PST 24
Finished Jan 03 12:47:44 PM PST 24
Peak memory 205164 kb
Host smart-1e89f2de-51c1-45e7-8ed3-110f1fb6d8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333191242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.2333191242
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.268992486
Short name T864
Test name
Test status
Simulation time 69454451 ps
CPU time 1.01 seconds
Started Jan 03 12:47:04 PM PST 24
Finished Jan 03 12:48:05 PM PST 24
Peak memory 205316 kb
Host smart-ce0ed4d9-ac02-47a0-a5bb-ccf9409f745d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268992486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.268992486
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.221011874
Short name T66
Test name
Test status
Simulation time 70985141 ps
CPU time 1.09 seconds
Started Jan 03 12:47:03 PM PST 24
Finished Jan 03 12:48:04 PM PST 24
Peak memory 214296 kb
Host smart-c691fd39-c28a-4c61-9901-28103508ef9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221011874 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.221011874
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.5299088
Short name T536
Test name
Test status
Simulation time 41854082 ps
CPU time 1.05 seconds
Started Jan 03 12:47:07 PM PST 24
Finished Jan 03 12:48:06 PM PST 24
Peak memory 205736 kb
Host smart-22993acf-0832-402a-bfae-df3cf0517734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5299088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.5299088
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.3731721861
Short name T429
Test name
Test status
Simulation time 46539396 ps
CPU time 0.91 seconds
Started Jan 03 12:47:04 PM PST 24
Finished Jan 03 12:48:05 PM PST 24
Peak memory 205112 kb
Host smart-46379516-0bfb-4776-bfbe-bfc041ad3c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731721861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3731721861
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert_test.4152618606
Short name T812
Test name
Test status
Simulation time 37129714 ps
CPU time 0.92 seconds
Started Jan 03 12:44:58 PM PST 24
Finished Jan 03 12:46:32 PM PST 24
Peak memory 204592 kb
Host smart-6640d401-4d03-418d-8f87-dc147a5555fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152618606 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.4152618606
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.2980312070
Short name T436
Test name
Test status
Simulation time 59880838 ps
CPU time 0.79 seconds
Started Jan 03 12:45:20 PM PST 24
Finished Jan 03 12:47:05 PM PST 24
Peak memory 214332 kb
Host smart-f3f963c0-690c-4083-a8b0-7c3aa74768a8
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980312070 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.2980312070
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_err.3758660144
Short name T819
Test name
Test status
Simulation time 28289590 ps
CPU time 1.17 seconds
Started Jan 03 12:44:51 PM PST 24
Finished Jan 03 12:46:30 PM PST 24
Peak memory 216996 kb
Host smart-2693f8b9-bc58-4799-add2-97663d1f6a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758660144 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.3758660144
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.3248781520
Short name T245
Test name
Test status
Simulation time 62351928 ps
CPU time 1.08 seconds
Started Jan 03 12:45:11 PM PST 24
Finished Jan 03 12:46:57 PM PST 24
Peak memory 205836 kb
Host smart-14a23b6f-16d2-4743-839b-01565167c6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248781520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.3248781520
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.877312304
Short name T636
Test name
Test status
Simulation time 20285878 ps
CPU time 0.94 seconds
Started Jan 03 12:45:01 PM PST 24
Finished Jan 03 12:46:29 PM PST 24
Peak memory 214532 kb
Host smart-84896525-c4e0-43cf-9de4-27b08583f9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877312304 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.877312304
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.3928997022
Short name T538
Test name
Test status
Simulation time 68363397 ps
CPU time 0.81 seconds
Started Jan 03 12:45:16 PM PST 24
Finished Jan 03 12:46:46 PM PST 24
Peak memory 204472 kb
Host smart-09928d0c-4457-4f78-964f-29a85d5aa288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928997022 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.3928997022
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.2613195033
Short name T410
Test name
Test status
Simulation time 200815292 ps
CPU time 2.62 seconds
Started Jan 03 12:45:03 PM PST 24
Finished Jan 03 12:46:50 PM PST 24
Peak memory 205940 kb
Host smart-100821ac-5025-4953-84b0-6c79846c1829
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613195033 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.2613195033
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.3166142695
Short name T537
Test name
Test status
Simulation time 147967255773 ps
CPU time 1602.47 seconds
Started Jan 03 12:45:06 PM PST 24
Finished Jan 03 01:13:23 PM PST 24
Peak memory 218744 kb
Host smart-09449a4d-b73e-4d1e-bfdc-f2d335b71d8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166142695 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.3166142695
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.3315955467
Short name T555
Test name
Test status
Simulation time 41417552 ps
CPU time 1.72 seconds
Started Jan 03 12:47:06 PM PST 24
Finished Jan 03 12:48:06 PM PST 24
Peak memory 214216 kb
Host smart-39b2d51d-2477-4b0a-a369-dd1c520f04c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315955467 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.3315955467
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.2745686017
Short name T767
Test name
Test status
Simulation time 35919275 ps
CPU time 1.04 seconds
Started Jan 03 12:47:02 PM PST 24
Finished Jan 03 12:48:04 PM PST 24
Peak memory 205376 kb
Host smart-6fc8b637-9d55-4641-863c-cd39e8a4e94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745686017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.2745686017
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.2828789074
Short name T371
Test name
Test status
Simulation time 70844055 ps
CPU time 1.41 seconds
Started Jan 03 12:47:06 PM PST 24
Finished Jan 03 12:48:06 PM PST 24
Peak memory 214192 kb
Host smart-36308dea-9065-4e0b-81e0-3b1bb0077c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828789074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.2828789074
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.1823221107
Short name T859
Test name
Test status
Simulation time 41724527 ps
CPU time 0.9 seconds
Started Jan 03 12:47:06 PM PST 24
Finished Jan 03 12:48:06 PM PST 24
Peak memory 205476 kb
Host smart-f7b2b5ff-a565-482c-be12-8f6eb810c15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823221107 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.1823221107
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.704457661
Short name T689
Test name
Test status
Simulation time 60617251 ps
CPU time 0.92 seconds
Started Jan 03 12:47:04 PM PST 24
Finished Jan 03 12:48:05 PM PST 24
Peak memory 205552 kb
Host smart-ced20bd5-0ec3-4bab-9837-bbbabb7ea95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704457661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.704457661
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.1778047778
Short name T590
Test name
Test status
Simulation time 17288143 ps
CPU time 1.19 seconds
Started Jan 03 12:47:02 PM PST 24
Finished Jan 03 12:48:04 PM PST 24
Peak memory 205352 kb
Host smart-0d046dc8-859b-4be1-a310-2d1bca551daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778047778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.1778047778
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.2318167381
Short name T782
Test name
Test status
Simulation time 21167759 ps
CPU time 0.92 seconds
Started Jan 03 12:47:06 PM PST 24
Finished Jan 03 12:48:06 PM PST 24
Peak memory 205124 kb
Host smart-9691d225-3189-4df8-b648-9c6ddd07c153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318167381 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.2318167381
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.2905876223
Short name T737
Test name
Test status
Simulation time 48106818 ps
CPU time 1.02 seconds
Started Jan 03 12:47:23 PM PST 24
Finished Jan 03 12:48:14 PM PST 24
Peak memory 205804 kb
Host smart-21c227ef-2c3b-465f-b178-7f25fa36fd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905876223 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.2905876223
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.3352528763
Short name T225
Test name
Test status
Simulation time 28480975 ps
CPU time 0.95 seconds
Started Jan 03 12:45:07 PM PST 24
Finished Jan 03 12:46:40 PM PST 24
Peak memory 205892 kb
Host smart-8f354440-b023-4b22-ae51-34e915f09091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352528763 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.3352528763
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.3073942541
Short name T460
Test name
Test status
Simulation time 43660705 ps
CPU time 0.84 seconds
Started Jan 03 12:45:17 PM PST 24
Finished Jan 03 12:46:48 PM PST 24
Peak memory 205260 kb
Host smart-3dd145dd-1c39-4089-907a-4c2ff9d19265
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073942541 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3073942541
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.193769239
Short name T874
Test name
Test status
Simulation time 11266670 ps
CPU time 0.88 seconds
Started Jan 03 12:45:25 PM PST 24
Finished Jan 03 12:47:15 PM PST 24
Peak memory 214356 kb
Host smart-8320b51e-d5f5-45a0-acb3-286266ef52bd
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193769239 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.193769239
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.3926117974
Short name T451
Test name
Test status
Simulation time 71739449 ps
CPU time 0.96 seconds
Started Jan 03 12:45:26 PM PST 24
Finished Jan 03 12:46:59 PM PST 24
Peak memory 214588 kb
Host smart-3ed4f409-fa50-4972-8eab-f7482ad30423
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926117974 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.3926117974
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.754111129
Short name T667
Test name
Test status
Simulation time 22025174 ps
CPU time 1.19 seconds
Started Jan 03 12:45:57 PM PST 24
Finished Jan 03 12:47:30 PM PST 24
Peak memory 215980 kb
Host smart-4d2285b1-e42c-4aee-8fff-82345f1f9980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754111129 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.754111129
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.987130451
Short name T374
Test name
Test status
Simulation time 75822374 ps
CPU time 0.96 seconds
Started Jan 03 12:45:07 PM PST 24
Finished Jan 03 12:46:40 PM PST 24
Peak memory 214116 kb
Host smart-a6014573-698f-4c4f-b4ce-19283520af81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987130451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.987130451
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.1179374982
Short name T748
Test name
Test status
Simulation time 26615439 ps
CPU time 0.91 seconds
Started Jan 03 12:45:09 PM PST 24
Finished Jan 03 12:46:40 PM PST 24
Peak memory 214424 kb
Host smart-331c85ac-615d-47d3-84f6-37753150babd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179374982 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.1179374982
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.383719110
Short name T772
Test name
Test status
Simulation time 35713495 ps
CPU time 0.81 seconds
Started Jan 03 12:45:07 PM PST 24
Finished Jan 03 12:46:41 PM PST 24
Peak memory 204864 kb
Host smart-73142f63-e3a8-4293-b0a8-4516ba897220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383719110 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.383719110
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.3769677623
Short name T453
Test name
Test status
Simulation time 881729386 ps
CPU time 1.85 seconds
Started Jan 03 12:45:05 PM PST 24
Finished Jan 03 12:46:42 PM PST 24
Peak memory 205996 kb
Host smart-08d9befa-dec7-4de4-b86f-c551a72ece1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769677623 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.3769677623
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.2692330226
Short name T493
Test name
Test status
Simulation time 27257961637 ps
CPU time 313.14 seconds
Started Jan 03 12:44:58 PM PST 24
Finished Jan 03 12:51:44 PM PST 24
Peak memory 214628 kb
Host smart-6273b3a4-0cd8-4070-a143-5e4054436f0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692330226 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.2692330226
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.1128238966
Short name T580
Test name
Test status
Simulation time 14225860 ps
CPU time 0.96 seconds
Started Jan 03 12:47:18 PM PST 24
Finished Jan 03 12:48:12 PM PST 24
Peak memory 214172 kb
Host smart-6fe8aa26-7918-4892-8ab4-df0934348242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128238966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1128238966
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.3322672012
Short name T448
Test name
Test status
Simulation time 16683603 ps
CPU time 0.96 seconds
Started Jan 03 12:47:18 PM PST 24
Finished Jan 03 12:48:12 PM PST 24
Peak memory 205144 kb
Host smart-8866e144-02d4-4995-8af5-6c8a9bce47b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322672012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.3322672012
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.1394649377
Short name T473
Test name
Test status
Simulation time 56427935 ps
CPU time 1.09 seconds
Started Jan 03 12:47:19 PM PST 24
Finished Jan 03 12:48:12 PM PST 24
Peak memory 205676 kb
Host smart-44b57e9d-93ae-4226-b335-d33027c1bee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394649377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1394649377
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.3814230334
Short name T832
Test name
Test status
Simulation time 65993040 ps
CPU time 1.66 seconds
Started Jan 03 12:47:19 PM PST 24
Finished Jan 03 12:48:13 PM PST 24
Peak memory 214144 kb
Host smart-a984bbf0-c99e-44e7-9e53-e0ad66a76852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814230334 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.3814230334
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.2961297532
Short name T841
Test name
Test status
Simulation time 84099960 ps
CPU time 1.1 seconds
Started Jan 03 12:47:28 PM PST 24
Finished Jan 03 12:48:16 PM PST 24
Peak memory 214336 kb
Host smart-efd973a6-f5e9-4d21-a17d-14b7c506bdbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961297532 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.2961297532
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.1920325002
Short name T730
Test name
Test status
Simulation time 158113518 ps
CPU time 2.19 seconds
Started Jan 03 12:47:27 PM PST 24
Finished Jan 03 12:48:17 PM PST 24
Peak memory 214132 kb
Host smart-583dd579-345c-4ed3-9656-32474725e335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920325002 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.1920325002
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.4059200810
Short name T552
Test name
Test status
Simulation time 102642548 ps
CPU time 1.03 seconds
Started Jan 03 12:47:23 PM PST 24
Finished Jan 03 12:48:14 PM PST 24
Peak memory 205520 kb
Host smart-0490c520-002f-48e0-be4e-599f9278e8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059200810 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.4059200810
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.1534073252
Short name T259
Test name
Test status
Simulation time 127764519 ps
CPU time 2.83 seconds
Started Jan 03 12:47:21 PM PST 24
Finished Jan 03 12:48:15 PM PST 24
Peak memory 214320 kb
Host smart-39b89242-55cf-484c-8103-4a64d617b0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534073252 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.1534073252
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.5940200
Short name T668
Test name
Test status
Simulation time 20092245 ps
CPU time 0.97 seconds
Started Jan 03 12:46:06 PM PST 24
Finished Jan 03 12:47:37 PM PST 24
Peak memory 205404 kb
Host smart-9cdcc978-86f5-4983-abb9-e60f7b525742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5940200 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.5940200
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.928624293
Short name T623
Test name
Test status
Simulation time 25895223 ps
CPU time 0.86 seconds
Started Jan 03 12:46:06 PM PST 24
Finished Jan 03 12:47:37 PM PST 24
Peak memory 204792 kb
Host smart-5ee49146-025b-4f63-9312-fc289c97ae0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928624293 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.928624293
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.3566437716
Short name T105
Test name
Test status
Simulation time 30561653 ps
CPU time 0.78 seconds
Started Jan 03 12:45:33 PM PST 24
Finished Jan 03 12:47:02 PM PST 24
Peak memory 214444 kb
Host smart-4eb90443-78f5-48a1-afdd-f0e235ff261f
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566437716 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.3566437716
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.3488334369
Short name T111
Test name
Test status
Simulation time 32644461 ps
CPU time 0.91 seconds
Started Jan 03 12:45:50 PM PST 24
Finished Jan 03 12:47:18 PM PST 24
Peak memory 214560 kb
Host smart-ceb7e40e-fefd-4960-99a3-2cde9e9d1a46
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488334369 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.3488334369
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.3600296925
Short name T564
Test name
Test status
Simulation time 50287792 ps
CPU time 0.98 seconds
Started Jan 03 12:45:12 PM PST 24
Finished Jan 03 12:46:47 PM PST 24
Peak memory 215816 kb
Host smart-0f7d6f7e-ffd8-4c60-a404-e7e637cc4ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600296925 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.3600296925
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.3765309185
Short name T418
Test name
Test status
Simulation time 15014660 ps
CPU time 0.95 seconds
Started Jan 03 12:45:50 PM PST 24
Finished Jan 03 12:47:18 PM PST 24
Peak memory 214132 kb
Host smart-e7a503f7-649f-4db5-ad47-c80454b8447c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765309185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.3765309185
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.2269131517
Short name T50
Test name
Test status
Simulation time 37162899 ps
CPU time 0.95 seconds
Started Jan 03 12:46:03 PM PST 24
Finished Jan 03 12:47:27 PM PST 24
Peak memory 221320 kb
Host smart-7c7fc1b3-0b76-4e31-8454-bc08b0e044d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269131517 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.2269131517
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.2972619188
Short name T837
Test name
Test status
Simulation time 21472081 ps
CPU time 0.81 seconds
Started Jan 03 12:45:46 PM PST 24
Finished Jan 03 12:47:21 PM PST 24
Peak memory 204740 kb
Host smart-00d06754-91e1-46c5-93af-9cb6d0627a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972619188 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.2972619188
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.2238123464
Short name T786
Test name
Test status
Simulation time 138586868 ps
CPU time 2.73 seconds
Started Jan 03 12:45:46 PM PST 24
Finished Jan 03 12:47:23 PM PST 24
Peak memory 206172 kb
Host smart-276c32cc-c98b-44cb-90f2-4f7e65e4a47b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238123464 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.2238123464
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.1447088357
Short name T54
Test name
Test status
Simulation time 418126792343 ps
CPU time 2531.1 seconds
Started Jan 03 12:45:32 PM PST 24
Finished Jan 03 01:29:12 PM PST 24
Peak memory 222460 kb
Host smart-903c40bc-2fc9-40fd-af32-4490143a3312
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447088357 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.1447088357
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/141.edn_genbits.1243434565
Short name T794
Test name
Test status
Simulation time 70868315 ps
CPU time 1.29 seconds
Started Jan 03 12:47:19 PM PST 24
Finished Jan 03 12:48:13 PM PST 24
Peak memory 214348 kb
Host smart-ed3f0284-8293-465a-84e0-731e8e8824f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243434565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.1243434565
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.162046022
Short name T34
Test name
Test status
Simulation time 15970647 ps
CPU time 0.99 seconds
Started Jan 03 12:47:22 PM PST 24
Finished Jan 03 12:48:13 PM PST 24
Peak memory 205076 kb
Host smart-098e2239-e9f4-4c6e-8fc0-771ebca665bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162046022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.162046022
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.4107575967
Short name T849
Test name
Test status
Simulation time 261283147 ps
CPU time 4.05 seconds
Started Jan 03 12:47:22 PM PST 24
Finished Jan 03 12:48:17 PM PST 24
Peak memory 214176 kb
Host smart-83898a75-b58b-4d97-9e67-8b468743cfdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107575967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.4107575967
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.1078589713
Short name T252
Test name
Test status
Simulation time 72136405 ps
CPU time 1.25 seconds
Started Jan 03 12:47:16 PM PST 24
Finished Jan 03 12:48:11 PM PST 24
Peak memory 213916 kb
Host smart-b40fa025-db00-4f29-8867-f30ccda8e5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078589713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.1078589713
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.2565454123
Short name T44
Test name
Test status
Simulation time 20572741 ps
CPU time 1.05 seconds
Started Jan 03 12:47:19 PM PST 24
Finished Jan 03 12:48:13 PM PST 24
Peak memory 205348 kb
Host smart-6d1fbfc9-9f8f-423d-835b-2a7bdddcd454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565454123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.2565454123
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.1321884910
Short name T851
Test name
Test status
Simulation time 22942791 ps
CPU time 1.12 seconds
Started Jan 03 12:47:22 PM PST 24
Finished Jan 03 12:48:13 PM PST 24
Peak memory 205524 kb
Host smart-35b08501-40c6-4625-aadc-43d184e28606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321884910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.1321884910
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.3283463791
Short name T744
Test name
Test status
Simulation time 21790858 ps
CPU time 0.88 seconds
Started Jan 03 12:47:24 PM PST 24
Finished Jan 03 12:48:14 PM PST 24
Peak memory 205248 kb
Host smart-b238ecad-ef60-4620-8282-230868a98abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283463791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3283463791
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.4006323331
Short name T873
Test name
Test status
Simulation time 23001916 ps
CPU time 1.05 seconds
Started Jan 03 12:47:19 PM PST 24
Finished Jan 03 12:48:12 PM PST 24
Peak memory 214244 kb
Host smart-cfe87bdd-dbf9-4e03-a2f8-add7950d2af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006323331 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.4006323331
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.1545370648
Short name T565
Test name
Test status
Simulation time 66839313 ps
CPU time 0.99 seconds
Started Jan 03 12:47:19 PM PST 24
Finished Jan 03 12:48:12 PM PST 24
Peak memory 205580 kb
Host smart-c390051c-d662-48fe-bc96-b0e27a47038c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545370648 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.1545370648
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.1826880377
Short name T224
Test name
Test status
Simulation time 57816662 ps
CPU time 0.9 seconds
Started Jan 03 12:45:41 PM PST 24
Finished Jan 03 12:47:22 PM PST 24
Peak memory 206104 kb
Host smart-435894ea-3719-4860-9930-7d6c4f806ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826880377 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.1826880377
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.1490156621
Short name T766
Test name
Test status
Simulation time 40289771 ps
CPU time 0.86 seconds
Started Jan 03 12:45:45 PM PST 24
Finished Jan 03 12:47:14 PM PST 24
Peak memory 204516 kb
Host smart-c79c173f-1d38-4d54-afce-fca31e6fdcee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490156621 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.1490156621
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.764624007
Short name T647
Test name
Test status
Simulation time 14290597 ps
CPU time 0.87 seconds
Started Jan 03 12:45:42 PM PST 24
Finished Jan 03 12:47:18 PM PST 24
Peak memory 214552 kb
Host smart-2f939f49-d33e-4050-8d47-2aadcd3d6461
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764624007 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.764624007
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.1222884348
Short name T447
Test name
Test status
Simulation time 14524881 ps
CPU time 0.86 seconds
Started Jan 03 12:45:37 PM PST 24
Finished Jan 03 12:47:16 PM PST 24
Peak memory 214608 kb
Host smart-fe59cbc3-8c13-43ed-b7ca-7e9c9298e4fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222884348 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.1222884348
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.1827480890
Short name T676
Test name
Test status
Simulation time 22785238 ps
CPU time 1.33 seconds
Started Jan 03 12:45:49 PM PST 24
Finished Jan 03 12:47:29 PM PST 24
Peak memory 229968 kb
Host smart-996561ab-61bb-4431-a94e-e6d5ba7303db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827480890 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.1827480890
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.757721563
Short name T432
Test name
Test status
Simulation time 27604283 ps
CPU time 0.95 seconds
Started Jan 03 12:46:00 PM PST 24
Finished Jan 03 12:47:23 PM PST 24
Peak memory 205420 kb
Host smart-d0cf2a13-9224-4514-96ee-cf25a630bce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757721563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.757721563
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.1661735756
Short name T747
Test name
Test status
Simulation time 22186391 ps
CPU time 1.06 seconds
Started Jan 03 12:45:28 PM PST 24
Finished Jan 03 12:47:04 PM PST 24
Peak memory 221848 kb
Host smart-9dc9af02-acb0-46ae-8022-5cbdd0de4122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661735756 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.1661735756
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.1543282719
Short name T642
Test name
Test status
Simulation time 44169561 ps
CPU time 0.87 seconds
Started Jan 03 12:45:40 PM PST 24
Finished Jan 03 12:47:13 PM PST 24
Peak memory 204632 kb
Host smart-6f9ef61b-b0e0-4d63-967b-c6af145f2ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543282719 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.1543282719
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.2496153141
Short name T515
Test name
Test status
Simulation time 410269521 ps
CPU time 2.45 seconds
Started Jan 03 12:45:44 PM PST 24
Finished Jan 03 12:47:17 PM PST 24
Peak memory 206000 kb
Host smart-b05057db-a922-4726-82d4-cbfda14519ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496153141 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.2496153141
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.277281132
Short name T853
Test name
Test status
Simulation time 57919224067 ps
CPU time 1106.96 seconds
Started Jan 03 12:45:57 PM PST 24
Finished Jan 03 01:05:51 PM PST 24
Peak memory 214520 kb
Host smart-af7168fa-e363-44a4-9b1f-a2393978aa7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277281132 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.277281132
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.2715310632
Short name T842
Test name
Test status
Simulation time 64603400 ps
CPU time 2.66 seconds
Started Jan 03 12:47:19 PM PST 24
Finished Jan 03 12:48:14 PM PST 24
Peak memory 214192 kb
Host smart-6fd39ee0-d51a-450e-a350-61e0e148507d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715310632 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.2715310632
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.1573218461
Short name T609
Test name
Test status
Simulation time 23376573 ps
CPU time 1.03 seconds
Started Jan 03 12:47:17 PM PST 24
Finished Jan 03 12:48:12 PM PST 24
Peak memory 214300 kb
Host smart-f834b2e9-605a-4570-9882-a293e06522e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573218461 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.1573218461
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.2966186784
Short name T202
Test name
Test status
Simulation time 16443782 ps
CPU time 1.02 seconds
Started Jan 03 12:47:22 PM PST 24
Finished Jan 03 12:48:13 PM PST 24
Peak memory 205572 kb
Host smart-3fe693a7-2027-49ef-b302-e7b96fa21297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966186784 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.2966186784
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.3397678943
Short name T857
Test name
Test status
Simulation time 19910742 ps
CPU time 0.9 seconds
Started Jan 03 12:47:17 PM PST 24
Finished Jan 03 12:48:12 PM PST 24
Peak memory 205528 kb
Host smart-dd11e9b0-eb6c-472b-ac35-82173a3cdb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397678943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.3397678943
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.3878345402
Short name T283
Test name
Test status
Simulation time 99575771 ps
CPU time 1.02 seconds
Started Jan 03 12:47:28 PM PST 24
Finished Jan 03 12:48:16 PM PST 24
Peak memory 205484 kb
Host smart-ae101b0d-d8b3-44cf-b09d-9e35f8b92cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878345402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.3878345402
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.100674722
Short name T655
Test name
Test status
Simulation time 59839401 ps
CPU time 0.96 seconds
Started Jan 03 12:47:21 PM PST 24
Finished Jan 03 12:48:13 PM PST 24
Peak memory 205692 kb
Host smart-2f6126a4-edb2-4859-bbe7-acfc7af50774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100674722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.100674722
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.19706421
Short name T825
Test name
Test status
Simulation time 87106482 ps
CPU time 0.87 seconds
Started Jan 03 12:47:20 PM PST 24
Finished Jan 03 12:48:13 PM PST 24
Peak memory 205184 kb
Host smart-ac174e52-b79f-47c1-9e05-99736462983c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19706421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.19706421
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.1904656258
Short name T576
Test name
Test status
Simulation time 16634027 ps
CPU time 0.95 seconds
Started Jan 03 12:46:11 PM PST 24
Finished Jan 03 12:47:35 PM PST 24
Peak memory 205928 kb
Host smart-2ca8dfd2-5622-4e00-b674-6a5db96db872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904656258 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.1904656258
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.1292180025
Short name T469
Test name
Test status
Simulation time 19341943 ps
CPU time 0.75 seconds
Started Jan 03 12:45:55 PM PST 24
Finished Jan 03 12:47:19 PM PST 24
Peak memory 204388 kb
Host smart-9e175a29-c719-49c4-9022-cfa93b456a0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292180025 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.1292180025
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.762049963
Short name T456
Test name
Test status
Simulation time 34373596 ps
CPU time 0.81 seconds
Started Jan 03 12:45:26 PM PST 24
Finished Jan 03 12:47:01 PM PST 24
Peak memory 214388 kb
Host smart-0af298a4-ea15-4d70-a6ff-5595704a04f9
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762049963 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.762049963
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.1123309939
Short name T795
Test name
Test status
Simulation time 51927595 ps
CPU time 1.03 seconds
Started Jan 03 12:45:37 PM PST 24
Finished Jan 03 12:47:41 PM PST 24
Peak memory 214528 kb
Host smart-2cb8448d-af67-4df6-b5d2-27d5348fcf96
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123309939 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.1123309939
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.1097123163
Short name T486
Test name
Test status
Simulation time 18810407 ps
CPU time 1.11 seconds
Started Jan 03 12:45:44 PM PST 24
Finished Jan 03 12:47:23 PM PST 24
Peak memory 215848 kb
Host smart-de8a7bc3-40bd-4b0c-b9ee-b917fc9dada7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097123163 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.1097123163
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_intr.3513677786
Short name T784
Test name
Test status
Simulation time 19097593 ps
CPU time 1.11 seconds
Started Jan 03 12:45:47 PM PST 24
Finished Jan 03 12:47:15 PM PST 24
Peak memory 214684 kb
Host smart-e6f108d3-63ee-4ec5-af2c-dab53ae06332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513677786 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.3513677786
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.2077045086
Short name T770
Test name
Test status
Simulation time 12914026 ps
CPU time 0.89 seconds
Started Jan 03 12:46:03 PM PST 24
Finished Jan 03 12:47:27 PM PST 24
Peak memory 204816 kb
Host smart-77b81ccd-a385-4b21-90b5-4254952c53bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077045086 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.2077045086
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.592507917
Short name T561
Test name
Test status
Simulation time 27116087 ps
CPU time 1.13 seconds
Started Jan 03 12:45:45 PM PST 24
Finished Jan 03 12:47:36 PM PST 24
Peak memory 205912 kb
Host smart-95b5b74c-186b-4de4-85fd-7f42b9e4f779
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592507917 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.592507917
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.1702008107
Short name T370
Test name
Test status
Simulation time 53591091538 ps
CPU time 1240.75 seconds
Started Jan 03 12:45:56 PM PST 24
Finished Jan 03 01:08:01 PM PST 24
Peak memory 217128 kb
Host smart-23160ad2-f896-44c5-8c55-be4b57112ee5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702008107 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.1702008107
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.2933401640
Short name T474
Test name
Test status
Simulation time 322274541 ps
CPU time 1.11 seconds
Started Jan 03 12:47:22 PM PST 24
Finished Jan 03 12:48:14 PM PST 24
Peak memory 205248 kb
Host smart-0a97ee33-8b59-479b-a3ad-923054c06f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933401640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.2933401640
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.1752806709
Short name T831
Test name
Test status
Simulation time 42321053 ps
CPU time 0.97 seconds
Started Jan 03 12:47:21 PM PST 24
Finished Jan 03 12:48:13 PM PST 24
Peak memory 205552 kb
Host smart-9bddad70-769a-41f7-83cf-8e9540a99139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752806709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.1752806709
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.4084624856
Short name T423
Test name
Test status
Simulation time 47267363 ps
CPU time 1.91 seconds
Started Jan 03 12:47:20 PM PST 24
Finished Jan 03 12:48:14 PM PST 24
Peak memory 214324 kb
Host smart-eb610058-7153-4103-a2b1-52f12b062dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084624856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.4084624856
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.3460969786
Short name T277
Test name
Test status
Simulation time 68062990 ps
CPU time 0.92 seconds
Started Jan 03 12:47:24 PM PST 24
Finished Jan 03 12:48:14 PM PST 24
Peak memory 205404 kb
Host smart-0f7f4d2d-cfe6-4831-8bc8-8d0d2c960ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460969786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.3460969786
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.2688690642
Short name T230
Test name
Test status
Simulation time 43122586 ps
CPU time 0.88 seconds
Started Jan 03 12:47:20 PM PST 24
Finished Jan 03 12:48:13 PM PST 24
Peak memory 205424 kb
Host smart-36997868-fa0c-4b3b-8d4b-45832b6a4fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688690642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.2688690642
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.2439605853
Short name T554
Test name
Test status
Simulation time 261465713 ps
CPU time 3.65 seconds
Started Jan 03 12:47:18 PM PST 24
Finished Jan 03 12:48:15 PM PST 24
Peak memory 214204 kb
Host smart-837d688e-0e17-4ae8-8a00-5493ea022457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439605853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.2439605853
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.3590111029
Short name T434
Test name
Test status
Simulation time 55013211 ps
CPU time 0.94 seconds
Started Jan 03 12:47:23 PM PST 24
Finished Jan 03 12:48:14 PM PST 24
Peak memory 205200 kb
Host smart-b3cd4743-3145-4d66-b9da-b326c2b41291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590111029 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.3590111029
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.3907002297
Short name T60
Test name
Test status
Simulation time 84860641 ps
CPU time 0.97 seconds
Started Jan 03 12:47:20 PM PST 24
Finished Jan 03 12:48:13 PM PST 24
Peak memory 205160 kb
Host smart-2b295507-ce8c-43bd-a907-47be8381f07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907002297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.3907002297
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert_test.3630440873
Short name T679
Test name
Test status
Simulation time 40580649 ps
CPU time 0.82 seconds
Started Jan 03 12:45:08 PM PST 24
Finished Jan 03 12:46:45 PM PST 24
Peak memory 204528 kb
Host smart-0c138978-61fb-4aa3-ba7f-f20c12143439
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630440873 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3630440873
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.2974486292
Short name T653
Test name
Test status
Simulation time 32318422 ps
CPU time 0.94 seconds
Started Jan 03 12:45:50 PM PST 24
Finished Jan 03 12:47:18 PM PST 24
Peak memory 214776 kb
Host smart-da40a4c5-5512-48ad-8fec-8763df10ceb2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974486292 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.2974486292
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.1450432968
Short name T398
Test name
Test status
Simulation time 25794481 ps
CPU time 0.87 seconds
Started Jan 03 12:45:45 PM PST 24
Finished Jan 03 12:47:19 PM PST 24
Peak memory 215756 kb
Host smart-bccb5d4d-f624-4fe9-b5c3-e0ea8910dc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450432968 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.1450432968
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.1230765133
Short name T721
Test name
Test status
Simulation time 42142231 ps
CPU time 0.92 seconds
Started Jan 03 12:46:03 PM PST 24
Finished Jan 03 12:47:28 PM PST 24
Peak memory 205312 kb
Host smart-265398d3-1913-45e4-8ce4-2ac0c5303018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230765133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.1230765133
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.3233636362
Short name T682
Test name
Test status
Simulation time 32763043 ps
CPU time 0.84 seconds
Started Jan 03 12:45:54 PM PST 24
Finished Jan 03 12:47:28 PM PST 24
Peak memory 214520 kb
Host smart-1be9100a-3fc4-4bd4-8eb0-076562091f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233636362 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3233636362
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.555994526
Short name T420
Test name
Test status
Simulation time 12539055 ps
CPU time 0.88 seconds
Started Jan 03 12:45:39 PM PST 24
Finished Jan 03 12:47:19 PM PST 24
Peak memory 205024 kb
Host smart-2d22c444-696b-485f-87ed-645882614929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555994526 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.555994526
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.1092561289
Short name T489
Test name
Test status
Simulation time 572040119 ps
CPU time 2.84 seconds
Started Jan 03 12:45:49 PM PST 24
Finished Jan 03 12:47:16 PM PST 24
Peak memory 205700 kb
Host smart-5aa95c31-bbb3-48c6-a4a0-718cd1bb4ad6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092561289 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1092561289
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.2323689993
Short name T604
Test name
Test status
Simulation time 604401313470 ps
CPU time 1308.03 seconds
Started Jan 03 12:46:03 PM PST 24
Finished Jan 03 01:09:15 PM PST 24
Peak memory 219192 kb
Host smart-e8628463-a360-403f-ba54-56f3e8cfef33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323689993 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.2323689993
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.3708882446
Short name T586
Test name
Test status
Simulation time 53701238 ps
CPU time 0.89 seconds
Started Jan 03 12:47:17 PM PST 24
Finished Jan 03 12:48:12 PM PST 24
Peak memory 205248 kb
Host smart-dfc3046a-1123-4ac0-a324-887a38e73e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708882446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.3708882446
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.2829358937
Short name T885
Test name
Test status
Simulation time 50873100 ps
CPU time 1.03 seconds
Started Jan 03 12:47:24 PM PST 24
Finished Jan 03 12:48:14 PM PST 24
Peak memory 205152 kb
Host smart-1f0adc43-0321-4c72-bb51-e03c83bd2ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829358937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.2829358937
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.488084919
Short name T387
Test name
Test status
Simulation time 18976369 ps
CPU time 0.98 seconds
Started Jan 03 12:47:22 PM PST 24
Finished Jan 03 12:48:18 PM PST 24
Peak memory 205312 kb
Host smart-07928cf9-b30d-4d0e-9643-b3df59031298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488084919 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.488084919
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.3097404383
Short name T459
Test name
Test status
Simulation time 28155701 ps
CPU time 1.02 seconds
Started Jan 03 12:47:22 PM PST 24
Finished Jan 03 12:48:13 PM PST 24
Peak memory 205552 kb
Host smart-2f2ed174-f277-4c26-92cf-2a871e9895f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097404383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.3097404383
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.306239678
Short name T59
Test name
Test status
Simulation time 103414432 ps
CPU time 1.05 seconds
Started Jan 03 12:47:22 PM PST 24
Finished Jan 03 12:48:14 PM PST 24
Peak memory 205320 kb
Host smart-ccd50e5a-3ee7-45f8-bcaf-e472fba447b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306239678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.306239678
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.3263336966
Short name T372
Test name
Test status
Simulation time 84928022 ps
CPU time 0.93 seconds
Started Jan 03 12:47:27 PM PST 24
Finished Jan 03 12:48:16 PM PST 24
Peak memory 205184 kb
Host smart-e6b6f0f6-9814-45ea-9d4c-e54e90aa6f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263336966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.3263336966
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.3619793109
Short name T918
Test name
Test status
Simulation time 41374593 ps
CPU time 0.98 seconds
Started Jan 03 12:47:28 PM PST 24
Finished Jan 03 12:48:16 PM PST 24
Peak memory 205580 kb
Host smart-8091afd4-a47f-4a53-af86-4e461a410c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619793109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.3619793109
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert_test.991275552
Short name T490
Test name
Test status
Simulation time 52978000 ps
CPU time 0.89 seconds
Started Jan 03 12:45:43 PM PST 24
Finished Jan 03 12:47:13 PM PST 24
Peak memory 204808 kb
Host smart-73720a62-b451-4acc-9df7-cd612e3a0437
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991275552 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.991275552
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.1667165486
Short name T775
Test name
Test status
Simulation time 33833152 ps
CPU time 0.85 seconds
Started Jan 03 12:46:06 PM PST 24
Finished Jan 03 12:47:37 PM PST 24
Peak memory 214344 kb
Host smart-0e79c447-e302-4bde-9a70-3a3daad1c400
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667165486 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.1667165486
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.2122226656
Short name T577
Test name
Test status
Simulation time 20846501 ps
CPU time 1 seconds
Started Jan 03 12:45:13 PM PST 24
Finished Jan 03 12:46:47 PM PST 24
Peak memory 214484 kb
Host smart-eac9b182-a8fb-47e7-95e6-66af445c60ee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122226656 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.2122226656
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.3027860219
Short name T898
Test name
Test status
Simulation time 19336664 ps
CPU time 0.94 seconds
Started Jan 03 12:45:56 PM PST 24
Finished Jan 03 12:47:20 PM PST 24
Peak memory 215828 kb
Host smart-f8d98db0-99da-43fd-bfa8-4dfa52813101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027860219 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.3027860219
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.2690740425
Short name T915
Test name
Test status
Simulation time 21215922 ps
CPU time 1.06 seconds
Started Jan 03 12:45:23 PM PST 24
Finished Jan 03 12:46:58 PM PST 24
Peak memory 205604 kb
Host smart-0f62d6ca-1d45-4f0a-93aa-081dcf58321a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690740425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.2690740425
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.849687743
Short name T562
Test name
Test status
Simulation time 24245742 ps
CPU time 0.9 seconds
Started Jan 03 12:45:33 PM PST 24
Finished Jan 03 12:47:06 PM PST 24
Peak memory 214720 kb
Host smart-25d8513a-13ec-435e-a902-111d7db147b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849687743 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.849687743
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.1118445425
Short name T541
Test name
Test status
Simulation time 18306583 ps
CPU time 0.83 seconds
Started Jan 03 12:45:24 PM PST 24
Finished Jan 03 12:46:53 PM PST 24
Peak memory 204556 kb
Host smart-3804f918-5356-4f0e-9c82-aa71b0e3f763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118445425 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.1118445425
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.3798750266
Short name T364
Test name
Test status
Simulation time 258468500 ps
CPU time 3.95 seconds
Started Jan 03 12:45:55 PM PST 24
Finished Jan 03 12:47:24 PM PST 24
Peak memory 206148 kb
Host smart-dfb8bf7e-0f12-4afc-8f05-8275d8924140
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798750266 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.3798750266
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.870796238
Short name T61
Test name
Test status
Simulation time 115811323292 ps
CPU time 742.04 seconds
Started Jan 03 12:45:26 PM PST 24
Finished Jan 03 12:59:21 PM PST 24
Peak memory 216296 kb
Host smart-e3b72f95-a8c2-4b9d-9b4a-cb30e744e58a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870796238 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.870796238
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.1524076688
Short name T534
Test name
Test status
Simulation time 22508092 ps
CPU time 1.14 seconds
Started Jan 03 12:47:27 PM PST 24
Finished Jan 03 12:48:16 PM PST 24
Peak memory 214172 kb
Host smart-ba2e2441-b61d-4cd9-811e-b2d8fe2f4788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524076688 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.1524076688
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.3817714805
Short name T408
Test name
Test status
Simulation time 16151226 ps
CPU time 0.9 seconds
Started Jan 03 12:47:20 PM PST 24
Finished Jan 03 12:48:13 PM PST 24
Peak memory 204992 kb
Host smart-baa649d2-42a3-4d2c-9091-bfd314677e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817714805 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.3817714805
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.2790830247
Short name T879
Test name
Test status
Simulation time 50746879 ps
CPU time 0.89 seconds
Started Jan 03 12:47:27 PM PST 24
Finished Jan 03 12:48:15 PM PST 24
Peak memory 205052 kb
Host smart-e19fb5ca-e9e6-430a-8fb9-b7626b0dd0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790830247 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.2790830247
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.340283259
Short name T535
Test name
Test status
Simulation time 17879770 ps
CPU time 1.14 seconds
Started Jan 03 12:47:22 PM PST 24
Finished Jan 03 12:48:13 PM PST 24
Peak memory 205736 kb
Host smart-76ee1453-bf51-460c-a736-61ecf4b4168d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340283259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.340283259
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.450965058
Short name T611
Test name
Test status
Simulation time 17078283 ps
CPU time 1.02 seconds
Started Jan 03 12:47:26 PM PST 24
Finished Jan 03 12:48:15 PM PST 24
Peak memory 205496 kb
Host smart-b222b558-a14f-4036-b97e-d11582d15b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450965058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.450965058
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.25480077
Short name T582
Test name
Test status
Simulation time 32959914 ps
CPU time 1 seconds
Started Jan 03 12:47:27 PM PST 24
Finished Jan 03 12:48:16 PM PST 24
Peak memory 205668 kb
Host smart-42ea7b2a-c892-44f4-bff3-f8f3917ee0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25480077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.25480077
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.2140813445
Short name T200
Test name
Test status
Simulation time 42687254 ps
CPU time 0.95 seconds
Started Jan 03 12:47:33 PM PST 24
Finished Jan 03 12:48:19 PM PST 24
Peak memory 205344 kb
Host smart-73441bb7-b4ad-4775-bfa1-17361690dff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140813445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.2140813445
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.2222132955
Short name T113
Test name
Test status
Simulation time 63057957 ps
CPU time 1.57 seconds
Started Jan 03 12:47:33 PM PST 24
Finished Jan 03 12:48:19 PM PST 24
Peak memory 214328 kb
Host smart-1a6085a8-8135-4f9e-8159-5c2ccec849d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222132955 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.2222132955
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.2898004429
Short name T575
Test name
Test status
Simulation time 18709215 ps
CPU time 1.1 seconds
Started Jan 03 12:47:26 PM PST 24
Finished Jan 03 12:48:15 PM PST 24
Peak memory 214316 kb
Host smart-1c0460b8-e27a-4497-b3f3-0576265885d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898004429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.2898004429
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.3208657765
Short name T228
Test name
Test status
Simulation time 58178741 ps
CPU time 0.92 seconds
Started Jan 03 12:46:00 PM PST 24
Finished Jan 03 12:47:40 PM PST 24
Peak memory 206128 kb
Host smart-38287705-c943-4961-8264-3d809782f23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208657765 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.3208657765
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.1379159015
Short name T521
Test name
Test status
Simulation time 67669187 ps
CPU time 0.81 seconds
Started Jan 03 12:45:29 PM PST 24
Finished Jan 03 12:47:08 PM PST 24
Peak memory 205456 kb
Host smart-0fc74462-18cc-4ca5-8bdc-cd91c6c1f319
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379159015 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.1379159015
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.2824254424
Short name T409
Test name
Test status
Simulation time 17206767 ps
CPU time 0.97 seconds
Started Jan 03 12:45:29 PM PST 24
Finished Jan 03 12:47:07 PM PST 24
Peak memory 214736 kb
Host smart-01652e33-b711-4572-97d4-a2a68fc740fb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824254424 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.2824254424
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.977335473
Short name T495
Test name
Test status
Simulation time 34120198 ps
CPU time 0.9 seconds
Started Jan 03 12:45:25 PM PST 24
Finished Jan 03 12:47:12 PM PST 24
Peak memory 221252 kb
Host smart-fcd8e996-0a4a-431d-8c43-33ef71e5826f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977335473 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.977335473
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.218632923
Short name T378
Test name
Test status
Simulation time 20144270 ps
CPU time 0.98 seconds
Started Jan 03 12:45:22 PM PST 24
Finished Jan 03 12:47:07 PM PST 24
Peak memory 205368 kb
Host smart-ab413cac-80a7-41b9-87dc-e80c6d94a2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218632923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.218632923
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.3094720073
Short name T392
Test name
Test status
Simulation time 19878922 ps
CPU time 1.04 seconds
Started Jan 03 12:45:13 PM PST 24
Finished Jan 03 12:46:47 PM PST 24
Peak memory 214264 kb
Host smart-176c842c-7353-4451-805a-6971152e7805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094720073 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3094720073
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.1312264662
Short name T884
Test name
Test status
Simulation time 18385597 ps
CPU time 0.81 seconds
Started Jan 03 12:45:34 PM PST 24
Finished Jan 03 12:47:06 PM PST 24
Peak memory 204848 kb
Host smart-f554a577-e2a3-4d2c-a59a-68fd78941738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312264662 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.1312264662
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.1671513108
Short name T437
Test name
Test status
Simulation time 138610195413 ps
CPU time 608.98 seconds
Started Jan 03 12:45:11 PM PST 24
Finished Jan 03 12:56:55 PM PST 24
Peak memory 214548 kb
Host smart-da490ddb-27bb-4319-a900-bafa5516e40f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671513108 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.1671513108
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.1310183573
Short name T428
Test name
Test status
Simulation time 33405305 ps
CPU time 0.99 seconds
Started Jan 03 12:47:27 PM PST 24
Finished Jan 03 12:48:16 PM PST 24
Peak memory 205364 kb
Host smart-0506732b-386c-47a9-90a5-eeabdcdae017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310183573 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.1310183573
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.987631920
Short name T81
Test name
Test status
Simulation time 50753621 ps
CPU time 0.94 seconds
Started Jan 03 12:47:23 PM PST 24
Finished Jan 03 12:48:14 PM PST 24
Peak memory 205304 kb
Host smart-d5c6eaee-9ad9-440f-8bb4-959050b75c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987631920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.987631920
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.1239557861
Short name T557
Test name
Test status
Simulation time 135090060 ps
CPU time 1 seconds
Started Jan 03 12:47:50 PM PST 24
Finished Jan 03 12:48:28 PM PST 24
Peak memory 205612 kb
Host smart-71cedfa1-9086-42af-aa71-226036989c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239557861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.1239557861
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.2224736381
Short name T728
Test name
Test status
Simulation time 565926424 ps
CPU time 5.26 seconds
Started Jan 03 12:47:27 PM PST 24
Finished Jan 03 12:48:20 PM PST 24
Peak memory 214144 kb
Host smart-aeaac245-83f4-455c-8632-405dfa9ba8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224736381 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2224736381
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.976662843
Short name T43
Test name
Test status
Simulation time 55625148 ps
CPU time 1.08 seconds
Started Jan 03 12:47:25 PM PST 24
Finished Jan 03 12:48:14 PM PST 24
Peak memory 205704 kb
Host smart-b5ad84dd-ae33-4fed-a23b-665ebe9323c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976662843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.976662843
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.3128799080
Short name T443
Test name
Test status
Simulation time 122803919 ps
CPU time 0.96 seconds
Started Jan 03 12:47:23 PM PST 24
Finished Jan 03 12:48:14 PM PST 24
Peak memory 205500 kb
Host smart-06d90b0d-f3fa-41bb-9b2e-954738521296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128799080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.3128799080
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.369698527
Short name T445
Test name
Test status
Simulation time 61918223 ps
CPU time 1.1 seconds
Started Jan 03 12:47:37 PM PST 24
Finished Jan 03 12:48:23 PM PST 24
Peak memory 205704 kb
Host smart-712cb2c0-9d20-4e18-b3c3-8269211fc425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369698527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.369698527
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.1064600731
Short name T40
Test name
Test status
Simulation time 60646403 ps
CPU time 0.93 seconds
Started Jan 03 12:47:32 PM PST 24
Finished Jan 03 12:48:18 PM PST 24
Peak memory 205372 kb
Host smart-5382cc6f-4ee8-4c5d-8b0a-a63656374fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064600731 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.1064600731
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.3697028722
Short name T215
Test name
Test status
Simulation time 41255145 ps
CPU time 0.93 seconds
Started Jan 03 12:45:00 PM PST 24
Finished Jan 03 12:46:35 PM PST 24
Peak memory 206100 kb
Host smart-57a533e6-85fb-4c44-bdc8-fe9573db8249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697028722 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.3697028722
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.813823109
Short name T475
Test name
Test status
Simulation time 55220518 ps
CPU time 0.87 seconds
Started Jan 03 12:44:47 PM PST 24
Finished Jan 03 12:46:10 PM PST 24
Peak memory 205324 kb
Host smart-aa5e35c0-5759-459b-a5da-1225095ac9bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813823109 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.813823109
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.1416647630
Short name T725
Test name
Test status
Simulation time 18165769 ps
CPU time 0.87 seconds
Started Jan 03 12:45:00 PM PST 24
Finished Jan 03 12:46:35 PM PST 24
Peak memory 214668 kb
Host smart-42329889-5030-415c-b768-0b801fd24e31
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416647630 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.1416647630
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.3386814639
Short name T856
Test name
Test status
Simulation time 81160652 ps
CPU time 1.03 seconds
Started Jan 03 12:44:37 PM PST 24
Finished Jan 03 12:45:54 PM PST 24
Peak memory 214504 kb
Host smart-5146e389-0182-4f94-b8c6-b6ab782ae97c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386814639 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.3386814639
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.2704372810
Short name T89
Test name
Test status
Simulation time 19360676 ps
CPU time 1.06 seconds
Started Jan 03 12:45:20 PM PST 24
Finished Jan 03 12:47:00 PM PST 24
Peak memory 215884 kb
Host smart-e2127b18-db7b-47da-9173-df27cde1e696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704372810 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.2704372810
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.1134001442
Short name T888
Test name
Test status
Simulation time 14722272 ps
CPU time 0.99 seconds
Started Jan 03 12:44:56 PM PST 24
Finished Jan 03 12:46:28 PM PST 24
Peak memory 205328 kb
Host smart-5300a8bd-7b65-4d0d-b379-d44a676b67ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134001442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.1134001442
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.4110554257
Short name T806
Test name
Test status
Simulation time 18456404 ps
CPU time 0.99 seconds
Started Jan 03 12:45:02 PM PST 24
Finished Jan 03 12:46:54 PM PST 24
Peak memory 214648 kb
Host smart-ca0b2673-a6ff-4ce0-acc3-883d9d9a12e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110554257 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.4110554257
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_sec_cm.1588945723
Short name T31
Test name
Test status
Simulation time 1392557355 ps
CPU time 3.11 seconds
Started Jan 03 12:45:11 PM PST 24
Finished Jan 03 12:46:50 PM PST 24
Peak memory 232684 kb
Host smart-22b92d1b-2c4a-4fcf-a8c5-1f0360837887
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588945723 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.1588945723
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.4221436542
Short name T863
Test name
Test status
Simulation time 38940646 ps
CPU time 0.82 seconds
Started Jan 03 12:44:46 PM PST 24
Finished Jan 03 12:46:09 PM PST 24
Peak memory 204828 kb
Host smart-24d1a1f2-2c9e-4b54-8db9-d1c361038f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221436542 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.4221436542
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.727515868
Short name T442
Test name
Test status
Simulation time 73737817 ps
CPU time 1.34 seconds
Started Jan 03 12:45:19 PM PST 24
Finished Jan 03 12:47:04 PM PST 24
Peak memory 205804 kb
Host smart-10181f40-2417-4ee0-a114-c64c1de4f254
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727515868 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.727515868
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.1976746875
Short name T829
Test name
Test status
Simulation time 144633716761 ps
CPU time 1851.81 seconds
Started Jan 03 12:45:11 PM PST 24
Finished Jan 03 01:17:42 PM PST 24
Peak memory 222572 kb
Host smart-60093d56-326b-4838-ade7-b20a04301fee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976746875 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.1976746875
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.1016846712
Short name T220
Test name
Test status
Simulation time 25307422 ps
CPU time 0.91 seconds
Started Jan 03 12:45:27 PM PST 24
Finished Jan 03 12:46:55 PM PST 24
Peak memory 205208 kb
Host smart-1c2a0e8e-8373-48c2-baad-9261f29ac1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016846712 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.1016846712
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.1487673092
Short name T709
Test name
Test status
Simulation time 17190524 ps
CPU time 0.93 seconds
Started Jan 03 12:45:43 PM PST 24
Finished Jan 03 12:47:13 PM PST 24
Peak memory 204636 kb
Host smart-1326f38a-7ebb-464f-a40b-bacfc792b3b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487673092 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.1487673092
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.2432738704
Short name T65
Test name
Test status
Simulation time 188143600 ps
CPU time 1.07 seconds
Started Jan 03 12:45:34 PM PST 24
Finished Jan 03 12:47:06 PM PST 24
Peak memory 214444 kb
Host smart-c2d15c1a-5558-48e9-9b51-322d2e249af2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432738704 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.2432738704
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.1464032392
Short name T88
Test name
Test status
Simulation time 22433478 ps
CPU time 0.85 seconds
Started Jan 03 12:46:18 PM PST 24
Finished Jan 03 12:47:45 PM PST 24
Peak memory 215568 kb
Host smart-42e02e1c-e75b-4133-b416-f3810a805b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464032392 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.1464032392
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.1463413683
Short name T559
Test name
Test status
Simulation time 50999327 ps
CPU time 1.4 seconds
Started Jan 03 12:46:08 PM PST 24
Finished Jan 03 12:47:39 PM PST 24
Peak memory 214344 kb
Host smart-45b67c97-37b0-4a06-84fb-0829e26cf34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463413683 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.1463413683
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.1990404801
Short name T765
Test name
Test status
Simulation time 36995193 ps
CPU time 0.83 seconds
Started Jan 03 12:45:23 PM PST 24
Finished Jan 03 12:46:56 PM PST 24
Peak memory 214548 kb
Host smart-e8c195af-7885-4cec-ad17-32edbb441233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990404801 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.1990404801
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.1518594940
Short name T415
Test name
Test status
Simulation time 15148736 ps
CPU time 0.86 seconds
Started Jan 03 12:46:03 PM PST 24
Finished Jan 03 12:47:27 PM PST 24
Peak memory 204928 kb
Host smart-e5d8a349-4166-443d-891b-998f6bbff9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518594940 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.1518594940
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.1932599514
Short name T197
Test name
Test status
Simulation time 708178155 ps
CPU time 3.41 seconds
Started Jan 03 12:45:46 PM PST 24
Finished Jan 03 12:47:14 PM PST 24
Peak memory 206160 kb
Host smart-14b6db5b-b8a1-4950-a033-6146e040c24b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932599514 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.1932599514
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.2085203095
Short name T911
Test name
Test status
Simulation time 232815062774 ps
CPU time 1288.33 seconds
Started Jan 03 12:45:54 PM PST 24
Finished Jan 03 01:08:46 PM PST 24
Peak memory 217320 kb
Host smart-4d7cdf4c-68d4-4ea1-a290-9bd916c9fa0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085203095 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.2085203095
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.1736783520
Short name T584
Test name
Test status
Simulation time 29680895 ps
CPU time 0.92 seconds
Started Jan 03 12:47:32 PM PST 24
Finished Jan 03 12:48:18 PM PST 24
Peak memory 205232 kb
Host smart-b2d5e3ab-9236-414f-b282-ca8e56220da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736783520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.1736783520
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.3110718617
Short name T882
Test name
Test status
Simulation time 112379196 ps
CPU time 1.28 seconds
Started Jan 03 12:47:27 PM PST 24
Finished Jan 03 12:48:16 PM PST 24
Peak memory 205348 kb
Host smart-590528e3-448f-4492-a6b3-865b1074b584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110718617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.3110718617
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.1324522694
Short name T205
Test name
Test status
Simulation time 39915651 ps
CPU time 1.12 seconds
Started Jan 03 12:47:26 PM PST 24
Finished Jan 03 12:48:15 PM PST 24
Peak memory 214228 kb
Host smart-e4877bc3-7288-450b-b16b-4165e93af040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324522694 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.1324522694
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.3960467978
Short name T499
Test name
Test status
Simulation time 33078220 ps
CPU time 1.02 seconds
Started Jan 03 12:47:29 PM PST 24
Finished Jan 03 12:48:16 PM PST 24
Peak memory 205416 kb
Host smart-cfafe78a-e28f-42b2-a606-5ec3e3f8c865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960467978 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.3960467978
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.2034938851
Short name T503
Test name
Test status
Simulation time 502109724 ps
CPU time 4.59 seconds
Started Jan 03 12:47:26 PM PST 24
Finished Jan 03 12:48:18 PM PST 24
Peak memory 214056 kb
Host smart-ffc7f986-1edc-4011-a839-69d502237551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034938851 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.2034938851
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.3126944934
Short name T487
Test name
Test status
Simulation time 119397586 ps
CPU time 1.84 seconds
Started Jan 03 12:47:45 PM PST 24
Finished Jan 03 12:48:27 PM PST 24
Peak memory 214168 kb
Host smart-0d45aa03-cc39-4760-9bd4-3d566a3489fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126944934 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3126944934
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.2491025603
Short name T63
Test name
Test status
Simulation time 26077286 ps
CPU time 1 seconds
Started Jan 03 12:47:32 PM PST 24
Finished Jan 03 12:48:18 PM PST 24
Peak memory 205380 kb
Host smart-db7bb29b-b550-4ef1-bcdd-df1c14947250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491025603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.2491025603
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.3833750620
Short name T67
Test name
Test status
Simulation time 47288848 ps
CPU time 0.97 seconds
Started Jan 03 12:48:13 PM PST 24
Finished Jan 03 12:48:41 PM PST 24
Peak memory 205484 kb
Host smart-adada99e-b91a-4da1-97e3-d528eeae6f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833750620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.3833750620
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.1594391116
Short name T280
Test name
Test status
Simulation time 35542393 ps
CPU time 0.89 seconds
Started Jan 03 12:47:28 PM PST 24
Finished Jan 03 12:48:16 PM PST 24
Peak memory 204992 kb
Host smart-58983d72-7877-4a03-a033-5cf16d95afec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594391116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.1594391116
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.237510050
Short name T457
Test name
Test status
Simulation time 40005901 ps
CPU time 1.73 seconds
Started Jan 03 12:47:31 PM PST 24
Finished Jan 03 12:48:18 PM PST 24
Peak memory 214164 kb
Host smart-a38016f5-f653-464b-9c2d-d0ecedca864a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237510050 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.237510050
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert_test.620931205
Short name T600
Test name
Test status
Simulation time 51456308 ps
CPU time 0.85 seconds
Started Jan 03 12:45:45 PM PST 24
Finished Jan 03 12:47:19 PM PST 24
Peak memory 204560 kb
Host smart-937e40ef-347b-4f3d-b100-1bf9b46c7685
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620931205 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.620931205
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.981298375
Short name T513
Test name
Test status
Simulation time 12259387 ps
CPU time 0.85 seconds
Started Jan 03 12:45:27 PM PST 24
Finished Jan 03 12:47:07 PM PST 24
Peak memory 214640 kb
Host smart-6b0c10b4-b0c0-41cc-ab0f-af059de825d7
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981298375 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.981298375
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.1316468690
Short name T916
Test name
Test status
Simulation time 108006693 ps
CPU time 0.97 seconds
Started Jan 03 12:45:23 PM PST 24
Finished Jan 03 12:46:56 PM PST 24
Peak memory 214724 kb
Host smart-73bf2a02-e9e3-4eb4-9513-83bee350ceb6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316468690 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.1316468690
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.4246845830
Short name T614
Test name
Test status
Simulation time 27228798 ps
CPU time 0.79 seconds
Started Jan 03 12:45:39 PM PST 24
Finished Jan 03 12:47:11 PM PST 24
Peak memory 215528 kb
Host smart-fe383bdb-7d3f-4058-be68-b106cd0223ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246845830 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.4246845830
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.1812970025
Short name T413
Test name
Test status
Simulation time 45193450 ps
CPU time 1.83 seconds
Started Jan 03 12:45:34 PM PST 24
Finished Jan 03 12:47:07 PM PST 24
Peak memory 214136 kb
Host smart-af6c54f9-96cc-4c8a-9de3-d67f643f904d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812970025 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.1812970025
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_smoke.952283280
Short name T625
Test name
Test status
Simulation time 24822562 ps
CPU time 0.89 seconds
Started Jan 03 12:46:02 PM PST 24
Finished Jan 03 12:47:34 PM PST 24
Peak memory 204976 kb
Host smart-2c77a17d-da04-4203-97bf-b12bde20e9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952283280 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.952283280
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.2454641036
Short name T236
Test name
Test status
Simulation time 101982577 ps
CPU time 1.64 seconds
Started Jan 03 12:45:40 PM PST 24
Finished Jan 03 12:47:22 PM PST 24
Peak memory 205416 kb
Host smart-9fbcfc9c-6901-4098-b517-a47a01b8f063
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454641036 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.2454641036
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.442961962
Short name T710
Test name
Test status
Simulation time 86869630756 ps
CPU time 931.44 seconds
Started Jan 03 12:45:48 PM PST 24
Finished Jan 03 01:02:44 PM PST 24
Peak memory 216440 kb
Host smart-f4c2aa23-129e-474a-85f7-9f38e2d181f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442961962 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.442961962
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.3487845395
Short name T746
Test name
Test status
Simulation time 163070951 ps
CPU time 1.53 seconds
Started Jan 03 12:47:31 PM PST 24
Finished Jan 03 12:48:18 PM PST 24
Peak memory 214168 kb
Host smart-e1118496-8904-4ddd-82af-51ef7ecc4c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487845395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.3487845395
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.2433331769
Short name T35
Test name
Test status
Simulation time 20033960 ps
CPU time 1.24 seconds
Started Jan 03 12:47:35 PM PST 24
Finished Jan 03 12:48:21 PM PST 24
Peak memory 205580 kb
Host smart-d944ac82-a8ad-414f-bfed-40300f27e0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433331769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.2433331769
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.1737957180
Short name T57
Test name
Test status
Simulation time 13929611 ps
CPU time 0.95 seconds
Started Jan 03 12:47:35 PM PST 24
Finished Jan 03 12:48:21 PM PST 24
Peak memory 205580 kb
Host smart-903a8516-fb3d-4abb-b355-f822d649f63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737957180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.1737957180
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.2402140406
Short name T904
Test name
Test status
Simulation time 24231344 ps
CPU time 0.92 seconds
Started Jan 03 12:47:32 PM PST 24
Finished Jan 03 12:48:17 PM PST 24
Peak memory 205300 kb
Host smart-9fe3d7cb-6e72-4725-ac94-e681d6d9b6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402140406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.2402140406
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.1228005007
Short name T637
Test name
Test status
Simulation time 205548100 ps
CPU time 1.07 seconds
Started Jan 03 12:47:30 PM PST 24
Finished Jan 03 12:48:17 PM PST 24
Peak memory 205060 kb
Host smart-2531b6e8-b815-4ad9-8a11-284819d261bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228005007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.1228005007
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.1043830519
Short name T248
Test name
Test status
Simulation time 34571340 ps
CPU time 0.99 seconds
Started Jan 03 12:47:37 PM PST 24
Finished Jan 03 12:48:22 PM PST 24
Peak memory 205600 kb
Host smart-a5d78c80-7753-43a5-beeb-a5241b881ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043830519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.1043830519
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.333863236
Short name T234
Test name
Test status
Simulation time 40253089 ps
CPU time 0.88 seconds
Started Jan 03 12:47:35 PM PST 24
Finished Jan 03 12:48:21 PM PST 24
Peak memory 205248 kb
Host smart-e4938e16-ddbc-4a27-a621-da3860ad0580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333863236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.333863236
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.2484881772
Short name T881
Test name
Test status
Simulation time 13083165 ps
CPU time 0.94 seconds
Started Jan 03 12:47:30 PM PST 24
Finished Jan 03 12:48:16 PM PST 24
Peak memory 205224 kb
Host smart-425f8995-a177-4355-95d8-71bcb7496f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484881772 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.2484881772
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.2603651598
Short name T276
Test name
Test status
Simulation time 21033923 ps
CPU time 0.9 seconds
Started Jan 03 12:47:29 PM PST 24
Finished Jan 03 12:48:16 PM PST 24
Peak memory 205120 kb
Host smart-53efe0c3-db30-48c6-98bd-599d21c38063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603651598 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.2603651598
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.1995516681
Short name T435
Test name
Test status
Simulation time 20846130 ps
CPU time 1.25 seconds
Started Jan 03 12:47:36 PM PST 24
Finished Jan 03 12:48:22 PM PST 24
Peak memory 205952 kb
Host smart-ae5d3ca1-984c-405f-845e-589c9d152f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995516681 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.1995516681
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.3213288979
Short name T376
Test name
Test status
Simulation time 66545638 ps
CPU time 0.89 seconds
Started Jan 03 12:45:05 PM PST 24
Finished Jan 03 12:46:42 PM PST 24
Peak memory 214472 kb
Host smart-a2659483-8b65-4587-b22c-79a799563ab4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213288979 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.3213288979
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.3204743187
Short name T754
Test name
Test status
Simulation time 26708383 ps
CPU time 1.22 seconds
Started Jan 03 12:45:06 PM PST 24
Finished Jan 03 12:46:48 PM PST 24
Peak memory 214780 kb
Host smart-89fafd14-5ab9-48e7-b968-3bb9d8a93486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204743187 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.3204743187
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.4072426084
Short name T255
Test name
Test status
Simulation time 29933737 ps
CPU time 0.97 seconds
Started Jan 03 12:45:37 PM PST 24
Finished Jan 03 12:47:40 PM PST 24
Peak memory 205588 kb
Host smart-ebc96a9b-0c31-418b-b1a2-f6d088069be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072426084 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.4072426084
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.2299875746
Short name T669
Test name
Test status
Simulation time 26908071 ps
CPU time 0.83 seconds
Started Jan 03 12:45:33 PM PST 24
Finished Jan 03 12:47:10 PM PST 24
Peak memory 214408 kb
Host smart-60c49c47-fa9e-4b2e-8540-4bcdc3b66f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299875746 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.2299875746
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.3699165619
Short name T362
Test name
Test status
Simulation time 46789897 ps
CPU time 0.84 seconds
Started Jan 03 12:46:09 PM PST 24
Finished Jan 03 12:47:33 PM PST 24
Peak memory 204572 kb
Host smart-0179281c-ba5d-4101-a128-f1d924aa0be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699165619 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.3699165619
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.3079901261
Short name T594
Test name
Test status
Simulation time 203640349 ps
CPU time 4.22 seconds
Started Jan 03 12:45:32 PM PST 24
Finished Jan 03 12:47:10 PM PST 24
Peak memory 206076 kb
Host smart-c04e53da-42fe-4d58-9f3a-aa7cfaf5f820
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079901261 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.3079901261
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.655501571
Short name T540
Test name
Test status
Simulation time 184743623719 ps
CPU time 1110.68 seconds
Started Jan 03 12:46:08 PM PST 24
Finished Jan 03 01:06:01 PM PST 24
Peak memory 216788 kb
Host smart-844cedc7-e19d-4e92-9f72-306972aeb748
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655501571 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.655501571
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.3773531386
Short name T861
Test name
Test status
Simulation time 27111712 ps
CPU time 0.96 seconds
Started Jan 03 12:47:30 PM PST 24
Finished Jan 03 12:48:17 PM PST 24
Peak memory 205592 kb
Host smart-9ef19b07-34cc-41df-9d59-d8774dd388b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773531386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.3773531386
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.2255138241
Short name T756
Test name
Test status
Simulation time 55261637 ps
CPU time 2.4 seconds
Started Jan 03 12:47:30 PM PST 24
Finished Jan 03 12:48:18 PM PST 24
Peak memory 214100 kb
Host smart-d0736340-a024-4fb7-9204-9d48ac8461be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255138241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.2255138241
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.2571400366
Short name T379
Test name
Test status
Simulation time 24086499 ps
CPU time 1.21 seconds
Started Jan 03 12:47:29 PM PST 24
Finished Jan 03 12:48:16 PM PST 24
Peak memory 214228 kb
Host smart-89effc3a-79e5-4967-b0bd-f0f3ddb5f37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571400366 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.2571400366
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.2587846212
Short name T845
Test name
Test status
Simulation time 17826215 ps
CPU time 0.99 seconds
Started Jan 03 12:47:29 PM PST 24
Finished Jan 03 12:48:16 PM PST 24
Peak memory 205228 kb
Host smart-630f7cd3-4711-4bfb-9d93-bc52a2771fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587846212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.2587846212
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.3189528695
Short name T716
Test name
Test status
Simulation time 25655017 ps
CPU time 0.94 seconds
Started Jan 03 12:47:41 PM PST 24
Finished Jan 03 12:48:24 PM PST 24
Peak memory 205412 kb
Host smart-b8c0bfe5-f272-4989-bcb1-52eb9ad62ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189528695 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.3189528695
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.4123448327
Short name T591
Test name
Test status
Simulation time 23561772 ps
CPU time 1.04 seconds
Started Jan 03 12:47:24 PM PST 24
Finished Jan 03 12:48:16 PM PST 24
Peak memory 205680 kb
Host smart-fe83ecc4-0319-457e-92f0-e25eebd0798b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123448327 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.4123448327
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.3165557661
Short name T506
Test name
Test status
Simulation time 18529057 ps
CPU time 1.07 seconds
Started Jan 03 12:47:21 PM PST 24
Finished Jan 03 12:48:13 PM PST 24
Peak memory 205908 kb
Host smart-cf5600a0-e1a8-4440-be8b-aeca1fcb3a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165557661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.3165557661
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.3142763084
Short name T452
Test name
Test status
Simulation time 85781984 ps
CPU time 1.09 seconds
Started Jan 03 12:47:26 PM PST 24
Finished Jan 03 12:48:15 PM PST 24
Peak memory 205496 kb
Host smart-95e30ef8-710e-448f-9ee4-3d19609572df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142763084 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.3142763084
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.4218435622
Short name T903
Test name
Test status
Simulation time 159862089 ps
CPU time 0.93 seconds
Started Jan 03 12:47:27 PM PST 24
Finished Jan 03 12:48:16 PM PST 24
Peak memory 205068 kb
Host smart-c9cb431a-bb06-4ed3-b36f-6d1a69fc881f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218435622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.4218435622
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.3856072614
Short name T514
Test name
Test status
Simulation time 29048521 ps
CPU time 0.88 seconds
Started Jan 03 12:47:42 PM PST 24
Finished Jan 03 12:48:25 PM PST 24
Peak memory 205100 kb
Host smart-b47defa0-c853-4d02-8312-8d4a246565ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856072614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.3856072614
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.2418815437
Short name T691
Test name
Test status
Simulation time 35381348 ps
CPU time 0.95 seconds
Started Jan 03 12:45:51 PM PST 24
Finished Jan 03 12:47:22 PM PST 24
Peak memory 205352 kb
Host smart-baa68548-3d84-47a5-9af6-5cf86a12b3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418815437 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.2418815437
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.2802409348
Short name T593
Test name
Test status
Simulation time 14203319 ps
CPU time 0.85 seconds
Started Jan 03 12:45:39 PM PST 24
Finished Jan 03 12:47:11 PM PST 24
Peak memory 204428 kb
Host smart-05da2edc-8a20-428a-a008-c456de83270a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802409348 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.2802409348
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.3886090263
Short name T116
Test name
Test status
Simulation time 39071018 ps
CPU time 0.94 seconds
Started Jan 03 12:45:27 PM PST 24
Finished Jan 03 12:47:05 PM PST 24
Peak memory 214724 kb
Host smart-2e0dcf46-d1e5-427a-9864-d930e0c87fb8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886090263 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.3886090263
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_genbits.3842730309
Short name T470
Test name
Test status
Simulation time 233540572 ps
CPU time 0.94 seconds
Started Jan 03 12:45:49 PM PST 24
Finished Jan 03 12:47:14 PM PST 24
Peak memory 205400 kb
Host smart-cc8d2202-d137-402c-92c2-af05d147c029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842730309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.3842730309
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_smoke.896313329
Short name T425
Test name
Test status
Simulation time 36731349 ps
CPU time 0.83 seconds
Started Jan 03 12:45:20 PM PST 24
Finished Jan 03 12:46:53 PM PST 24
Peak memory 204944 kb
Host smart-48f05a29-e0d4-4738-8536-f5b76b1e1777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896313329 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.896313329
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.2272911196
Short name T433
Test name
Test status
Simulation time 416849619 ps
CPU time 4.44 seconds
Started Jan 03 12:45:30 PM PST 24
Finished Jan 03 12:47:07 PM PST 24
Peak memory 205952 kb
Host smart-8b3f3ae3-276b-4c05-8c9f-e06579b71cb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272911196 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.2272911196
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/230.edn_genbits.2259164853
Short name T868
Test name
Test status
Simulation time 31321974 ps
CPU time 1.12 seconds
Started Jan 03 12:47:19 PM PST 24
Finished Jan 03 12:48:12 PM PST 24
Peak memory 205724 kb
Host smart-3213c721-eb1d-4570-9d10-5d4546b4d8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259164853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.2259164853
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.365853809
Short name T430
Test name
Test status
Simulation time 2557803507 ps
CPU time 63.36 seconds
Started Jan 03 12:47:28 PM PST 24
Finished Jan 03 12:49:18 PM PST 24
Peak memory 214248 kb
Host smart-4660dc02-6868-456a-ba99-9ad21190dea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365853809 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.365853809
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.2992275368
Short name T752
Test name
Test status
Simulation time 45297145 ps
CPU time 1.07 seconds
Started Jan 03 12:47:23 PM PST 24
Finished Jan 03 12:48:14 PM PST 24
Peak memory 205460 kb
Host smart-74d1cceb-fe96-46e6-9aca-b8a866cfeb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992275368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.2992275368
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.3728699588
Short name T528
Test name
Test status
Simulation time 21406802 ps
CPU time 0.95 seconds
Started Jan 03 12:47:26 PM PST 24
Finished Jan 03 12:48:15 PM PST 24
Peak memory 205084 kb
Host smart-c1d2c006-3ba7-42b6-bc47-bc27b8e78956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728699588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.3728699588
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.1987846598
Short name T599
Test name
Test status
Simulation time 22046582 ps
CPU time 0.95 seconds
Started Jan 03 12:47:26 PM PST 24
Finished Jan 03 12:48:15 PM PST 24
Peak memory 205484 kb
Host smart-88d78d68-132d-4ce4-8bc3-d6e133084b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987846598 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.1987846598
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.4023171306
Short name T375
Test name
Test status
Simulation time 29700436 ps
CPU time 0.93 seconds
Started Jan 03 12:47:27 PM PST 24
Finished Jan 03 12:48:16 PM PST 24
Peak memory 204780 kb
Host smart-d48ec7b1-05b4-456d-9132-1beaed4782b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023171306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.4023171306
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.3141075490
Short name T287
Test name
Test status
Simulation time 15238858 ps
CPU time 0.99 seconds
Started Jan 03 12:47:33 PM PST 24
Finished Jan 03 12:48:19 PM PST 24
Peak memory 214188 kb
Host smart-c0e7bd3f-6d60-4e85-a078-a04c65346328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141075490 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.3141075490
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.772800447
Short name T901
Test name
Test status
Simulation time 46332281 ps
CPU time 1.96 seconds
Started Jan 03 12:47:27 PM PST 24
Finished Jan 03 12:48:17 PM PST 24
Peak memory 214276 kb
Host smart-99f21235-b449-49d7-b539-7259378770d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772800447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.772800447
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.2690501818
Short name T750
Test name
Test status
Simulation time 102095390 ps
CPU time 1.02 seconds
Started Jan 03 12:47:23 PM PST 24
Finished Jan 03 12:48:14 PM PST 24
Peak memory 205488 kb
Host smart-26c350de-963f-4003-b16c-d5b5790d29c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690501818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.2690501818
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.3577869201
Short name T659
Test name
Test status
Simulation time 60217397 ps
CPU time 0.94 seconds
Started Jan 03 12:45:48 PM PST 24
Finished Jan 03 12:47:14 PM PST 24
Peak memory 206008 kb
Host smart-d10d61cb-ffab-4a79-8900-b9b0f70b8419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577869201 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.3577869201
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.2177642286
Short name T899
Test name
Test status
Simulation time 47908360 ps
CPU time 0.81 seconds
Started Jan 03 12:45:38 PM PST 24
Finished Jan 03 12:47:18 PM PST 24
Peak memory 204332 kb
Host smart-3d50e59c-8725-43b2-a000-d1ba520d466b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177642286 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.2177642286
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.2212339664
Short name T906
Test name
Test status
Simulation time 16326394 ps
CPU time 0.94 seconds
Started Jan 03 12:45:20 PM PST 24
Finished Jan 03 12:47:07 PM PST 24
Peak memory 214712 kb
Host smart-a3861fad-9a59-4cc8-b3f0-3d08a7f4caf6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212339664 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.2212339664
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_genbits.2363337191
Short name T685
Test name
Test status
Simulation time 168674083 ps
CPU time 1.14 seconds
Started Jan 03 12:45:10 PM PST 24
Finished Jan 03 12:46:43 PM PST 24
Peak memory 205976 kb
Host smart-a1533bf8-45b2-44f1-a585-27dd5b0946a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363337191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.2363337191
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.2584525428
Short name T391
Test name
Test status
Simulation time 34062413 ps
CPU time 0.83 seconds
Started Jan 03 12:45:38 PM PST 24
Finished Jan 03 12:47:41 PM PST 24
Peak memory 214208 kb
Host smart-3db6531d-b6d3-41bf-9051-27365e2c8f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584525428 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.2584525428
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.3952141279
Short name T695
Test name
Test status
Simulation time 42830570 ps
CPU time 0.82 seconds
Started Jan 03 12:45:49 PM PST 24
Finished Jan 03 12:47:18 PM PST 24
Peak memory 205004 kb
Host smart-4a0a7705-923d-4c94-bf74-b988452a7cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952141279 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.3952141279
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.1472572135
Short name T389
Test name
Test status
Simulation time 66884907 ps
CPU time 1.88 seconds
Started Jan 03 12:45:04 PM PST 24
Finished Jan 03 12:46:42 PM PST 24
Peak memory 205828 kb
Host smart-dcfbff7f-9446-4852-a40a-3376aeb78f01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472572135 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.1472572135
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.3759116974
Short name T6
Test name
Test status
Simulation time 14595333288 ps
CPU time 381.54 seconds
Started Jan 03 12:45:58 PM PST 24
Finished Jan 03 12:53:52 PM PST 24
Peak memory 215924 kb
Host smart-7c15df65-7d83-42cc-ba52-17401ef0c688
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759116974 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.3759116974
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.3522945932
Short name T10
Test name
Test status
Simulation time 73062864 ps
CPU time 1.85 seconds
Started Jan 03 12:47:26 PM PST 24
Finished Jan 03 12:48:16 PM PST 24
Peak memory 214228 kb
Host smart-91bf9109-df37-475a-8a74-e679b4268ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522945932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.3522945932
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.810128484
Short name T776
Test name
Test status
Simulation time 30189532 ps
CPU time 0.92 seconds
Started Jan 03 12:47:23 PM PST 24
Finished Jan 03 12:48:14 PM PST 24
Peak memory 205276 kb
Host smart-5baa9c6c-6163-43df-9e96-905154252449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810128484 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.810128484
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.2923517889
Short name T815
Test name
Test status
Simulation time 79289256 ps
CPU time 1.46 seconds
Started Jan 03 12:47:34 PM PST 24
Finished Jan 03 12:48:20 PM PST 24
Peak memory 205916 kb
Host smart-fd3fc42a-d7b0-4d9d-ba89-c967155b586c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923517889 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.2923517889
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.3438957640
Short name T556
Test name
Test status
Simulation time 14700292 ps
CPU time 0.98 seconds
Started Jan 03 12:47:22 PM PST 24
Finished Jan 03 12:48:13 PM PST 24
Peak memory 205656 kb
Host smart-28b431a3-cf48-4ac6-8bd5-225335393f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438957640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.3438957640
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.1257497067
Short name T498
Test name
Test status
Simulation time 32238180 ps
CPU time 1.24 seconds
Started Jan 03 12:47:36 PM PST 24
Finished Jan 03 12:48:21 PM PST 24
Peak memory 205712 kb
Host smart-c71328f4-c011-40d9-855f-7a8db177d348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257497067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.1257497067
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.3796165780
Short name T848
Test name
Test status
Simulation time 58405521 ps
CPU time 0.94 seconds
Started Jan 03 12:47:26 PM PST 24
Finished Jan 03 12:48:15 PM PST 24
Peak memory 205476 kb
Host smart-36362c73-b9ce-4689-9405-ffbb9ddd4104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796165780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.3796165780
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.1685072562
Short name T461
Test name
Test status
Simulation time 104598003 ps
CPU time 1.32 seconds
Started Jan 03 12:47:27 PM PST 24
Finished Jan 03 12:48:16 PM PST 24
Peak memory 213880 kb
Host smart-760ceebe-4b67-4c7e-8c68-c60bbe904d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685072562 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.1685072562
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.610277302
Short name T567
Test name
Test status
Simulation time 80759473 ps
CPU time 1.01 seconds
Started Jan 03 12:47:35 PM PST 24
Finished Jan 03 12:48:20 PM PST 24
Peak memory 205392 kb
Host smart-a8ec3b03-e6d9-4ac3-a4e7-43f6ca5c5ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610277302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.610277302
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.4222070214
Short name T38
Test name
Test status
Simulation time 53482097 ps
CPU time 0.97 seconds
Started Jan 03 12:47:35 PM PST 24
Finished Jan 03 12:48:20 PM PST 24
Peak memory 205628 kb
Host smart-05433c10-fb09-45d8-bdba-b592ffd96614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222070214 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.4222070214
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.1786136413
Short name T419
Test name
Test status
Simulation time 50881835 ps
CPU time 1.97 seconds
Started Jan 03 12:48:08 PM PST 24
Finished Jan 03 12:48:38 PM PST 24
Peak memory 214260 kb
Host smart-a5923325-9f8f-452d-a694-4427a1a777c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786136413 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.1786136413
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.500772232
Short name T687
Test name
Test status
Simulation time 103065835 ps
CPU time 0.98 seconds
Started Jan 03 12:46:01 PM PST 24
Finished Jan 03 12:47:27 PM PST 24
Peak memory 205980 kb
Host smart-c5c1f2fe-78bb-4507-af72-3198ec6ba156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500772232 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.500772232
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.3128924968
Short name T824
Test name
Test status
Simulation time 49646382 ps
CPU time 0.88 seconds
Started Jan 03 12:45:54 PM PST 24
Finished Jan 03 12:47:46 PM PST 24
Peak memory 205288 kb
Host smart-4aaac321-f22f-44b7-b97e-48e0b7f8091c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128924968 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.3128924968
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.2888310397
Short name T405
Test name
Test status
Simulation time 12824089 ps
CPU time 0.85 seconds
Started Jan 03 12:45:26 PM PST 24
Finished Jan 03 12:47:05 PM PST 24
Peak memory 214436 kb
Host smart-a6b18628-b87d-4967-aeda-5f953a2ff194
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888310397 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2888310397
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_err.745266210
Short name T47
Test name
Test status
Simulation time 26856452 ps
CPU time 1.2 seconds
Started Jan 03 12:45:07 PM PST 24
Finished Jan 03 12:46:49 PM PST 24
Peak memory 221856 kb
Host smart-8f6338f5-dc1a-4a40-ada2-4aa386170934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745266210 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.745266210
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.2346651165
Short name T840
Test name
Test status
Simulation time 28648803 ps
CPU time 0.87 seconds
Started Jan 03 12:45:29 PM PST 24
Finished Jan 03 12:47:13 PM PST 24
Peak memory 204852 kb
Host smart-5f0792f4-1d66-4ce2-899c-0b53c702cb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346651165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.2346651165
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.2776327582
Short name T826
Test name
Test status
Simulation time 33428443 ps
CPU time 0.93 seconds
Started Jan 03 12:45:30 PM PST 24
Finished Jan 03 12:47:02 PM PST 24
Peak memory 221820 kb
Host smart-e88a5315-b14c-4c51-b047-a18bf99b4289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776327582 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.2776327582
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.3371609777
Short name T781
Test name
Test status
Simulation time 20517714 ps
CPU time 0.83 seconds
Started Jan 03 12:45:38 PM PST 24
Finished Jan 03 12:47:15 PM PST 24
Peak memory 204824 kb
Host smart-b4ce8fe7-f03a-428a-8c9f-4f07f9fbf9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371609777 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.3371609777
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.3649224621
Short name T811
Test name
Test status
Simulation time 198763270 ps
CPU time 3.99 seconds
Started Jan 03 12:45:30 PM PST 24
Finished Jan 03 12:47:11 PM PST 24
Peak memory 206068 kb
Host smart-4a8f1583-c4de-4d57-83a9-874c28a3b48d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649224621 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.3649224621
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.46443044
Short name T196
Test name
Test status
Simulation time 146543989329 ps
CPU time 628.83 seconds
Started Jan 03 12:45:24 PM PST 24
Finished Jan 03 12:57:24 PM PST 24
Peak memory 216300 kb
Host smart-b8445a12-0a1e-4d6a-b30b-341fd6c2d5ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46443044 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.46443044
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.2388128354
Short name T244
Test name
Test status
Simulation time 27962168 ps
CPU time 0.91 seconds
Started Jan 03 12:48:11 PM PST 24
Finished Jan 03 12:48:44 PM PST 24
Peak memory 205884 kb
Host smart-2333b8f8-3ce6-4105-aece-00b051b09571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388128354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.2388128354
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.2349072556
Short name T523
Test name
Test status
Simulation time 509996730 ps
CPU time 3.59 seconds
Started Jan 03 12:48:02 PM PST 24
Finished Jan 03 12:48:37 PM PST 24
Peak memory 214176 kb
Host smart-28f693bd-92a4-4c63-93ef-eeda28fd8cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349072556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.2349072556
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.3040266927
Short name T240
Test name
Test status
Simulation time 130338723 ps
CPU time 3 seconds
Started Jan 03 12:48:11 PM PST 24
Finished Jan 03 12:48:41 PM PST 24
Peak memory 214344 kb
Host smart-e600bec6-6c36-4819-af6b-a6d2f81d7eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040266927 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.3040266927
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.2312663847
Short name T688
Test name
Test status
Simulation time 58551480 ps
CPU time 0.96 seconds
Started Jan 03 12:48:17 PM PST 24
Finished Jan 03 12:48:43 PM PST 24
Peak memory 204860 kb
Host smart-4d410766-f780-401c-bf87-c9b16443ab21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312663847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.2312663847
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.3770961133
Short name T273
Test name
Test status
Simulation time 47075786 ps
CPU time 0.86 seconds
Started Jan 03 12:48:07 PM PST 24
Finished Jan 03 12:48:37 PM PST 24
Peak memory 205132 kb
Host smart-ff9933fa-9938-48b1-a30c-287dd9a07c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770961133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.3770961133
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.2229646009
Short name T471
Test name
Test status
Simulation time 12542656 ps
CPU time 0.92 seconds
Started Jan 03 12:48:05 PM PST 24
Finished Jan 03 12:48:36 PM PST 24
Peak memory 205068 kb
Host smart-c464eeb5-ad9b-4d81-b3d6-01d259a84561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229646009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.2229646009
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.676762275
Short name T605
Test name
Test status
Simulation time 18995012 ps
CPU time 0.98 seconds
Started Jan 03 12:48:23 PM PST 24
Finished Jan 03 12:48:47 PM PST 24
Peak memory 214224 kb
Host smart-e6c229ed-eb3a-4489-95fe-e6a5231653b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676762275 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.676762275
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.977192507
Short name T649
Test name
Test status
Simulation time 31137833 ps
CPU time 0.94 seconds
Started Jan 03 12:48:26 PM PST 24
Finished Jan 03 12:48:50 PM PST 24
Peak memory 204988 kb
Host smart-cc343015-35db-4756-8ad2-c3cadd3d4017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977192507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.977192507
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.2114163390
Short name T708
Test name
Test status
Simulation time 2266913067 ps
CPU time 72.18 seconds
Started Jan 03 12:48:12 PM PST 24
Finished Jan 03 12:49:52 PM PST 24
Peak memory 214320 kb
Host smart-4c58de07-4da3-4ef7-88ae-50b2e097860c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114163390 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.2114163390
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.3224281084
Short name T869
Test name
Test status
Simulation time 31974553 ps
CPU time 0.97 seconds
Started Jan 03 12:48:07 PM PST 24
Finished Jan 03 12:48:37 PM PST 24
Peak memory 205540 kb
Host smart-bed095e6-de01-4604-8208-a50d7b3b4b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224281084 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.3224281084
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.1887011695
Short name T717
Test name
Test status
Simulation time 34992623 ps
CPU time 0.96 seconds
Started Jan 03 12:45:17 PM PST 24
Finished Jan 03 12:46:55 PM PST 24
Peak memory 206056 kb
Host smart-cae2ee2d-ff2e-404b-9ab6-f20bf9423a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887011695 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.1887011695
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.706106613
Short name T579
Test name
Test status
Simulation time 38019280 ps
CPU time 0.8 seconds
Started Jan 03 12:45:49 PM PST 24
Finished Jan 03 12:47:14 PM PST 24
Peak memory 204464 kb
Host smart-3bb26f9c-3f04-4bbe-955f-6772f28f0e33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706106613 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.706106613
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.224708687
Short name T760
Test name
Test status
Simulation time 40967739 ps
CPU time 0.82 seconds
Started Jan 03 12:45:41 PM PST 24
Finished Jan 03 12:47:09 PM PST 24
Peak memory 214320 kb
Host smart-98b46bcd-6db3-41a9-8872-573543468088
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224708687 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.224708687
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.2658660083
Short name T912
Test name
Test status
Simulation time 28573852 ps
CPU time 1.02 seconds
Started Jan 03 12:46:05 PM PST 24
Finished Jan 03 12:47:35 PM PST 24
Peak memory 214536 kb
Host smart-1b1925c2-df7d-468a-a5ab-42aca5b9e2fa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658660083 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.2658660083
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.1410423693
Short name T887
Test name
Test status
Simulation time 23542051 ps
CPU time 1.17 seconds
Started Jan 03 12:45:11 PM PST 24
Finished Jan 03 12:46:47 PM PST 24
Peak memory 221776 kb
Host smart-a04f82dc-69d2-425e-a728-95b7a37147c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410423693 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.1410423693
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.2508205432
Short name T670
Test name
Test status
Simulation time 46390312 ps
CPU time 0.9 seconds
Started Jan 03 12:45:44 PM PST 24
Finished Jan 03 12:47:43 PM PST 24
Peak memory 205152 kb
Host smart-ca194550-37b0-41a4-9b4a-eff474e50144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508205432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.2508205432
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.3253460035
Short name T464
Test name
Test status
Simulation time 38877298 ps
CPU time 0.91 seconds
Started Jan 03 12:45:41 PM PST 24
Finished Jan 03 12:47:22 PM PST 24
Peak memory 221176 kb
Host smart-9fcd33b2-63a7-4e61-b5a3-86c8dcbfe031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253460035 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.3253460035
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.3128641259
Short name T843
Test name
Test status
Simulation time 69737337 ps
CPU time 0.81 seconds
Started Jan 03 12:45:44 PM PST 24
Finished Jan 03 12:47:28 PM PST 24
Peak memory 204952 kb
Host smart-129014ca-1b85-4f2b-aada-c3001e0649bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128641259 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.3128641259
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.3281153072
Short name T654
Test name
Test status
Simulation time 127275782 ps
CPU time 2.03 seconds
Started Jan 03 12:45:35 PM PST 24
Finished Jan 03 12:47:34 PM PST 24
Peak memory 205900 kb
Host smart-f0c56944-bd1e-4b4e-87e5-5534f09f6b9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281153072 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3281153072
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.3368425096
Short name T792
Test name
Test status
Simulation time 51812615246 ps
CPU time 268.15 seconds
Started Jan 03 12:46:06 PM PST 24
Finished Jan 03 12:52:05 PM PST 24
Peak memory 214908 kb
Host smart-3e42ab8f-1db0-4d25-97c6-42fbb09948e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368425096 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.3368425096
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.1504222297
Short name T250
Test name
Test status
Simulation time 20548941 ps
CPU time 1.12 seconds
Started Jan 03 12:48:10 PM PST 24
Finished Jan 03 12:48:39 PM PST 24
Peak memory 214216 kb
Host smart-91b5e7c6-8573-4a42-ae92-c5724f02c84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504222297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.1504222297
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.2714684045
Short name T847
Test name
Test status
Simulation time 20346247 ps
CPU time 0.91 seconds
Started Jan 03 12:48:10 PM PST 24
Finished Jan 03 12:48:38 PM PST 24
Peak memory 205136 kb
Host smart-73b959ca-5347-43f1-838e-350bedb616e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714684045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.2714684045
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.1930489864
Short name T530
Test name
Test status
Simulation time 51160225 ps
CPU time 0.91 seconds
Started Jan 03 12:48:15 PM PST 24
Finished Jan 03 12:48:42 PM PST 24
Peak memory 205188 kb
Host smart-6ba573a5-d398-4f43-8ba8-3fd68171fac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930489864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.1930489864
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.807153236
Short name T278
Test name
Test status
Simulation time 201148382 ps
CPU time 1.08 seconds
Started Jan 03 12:48:06 PM PST 24
Finished Jan 03 12:48:37 PM PST 24
Peak memory 205556 kb
Host smart-e6434299-c0a3-4230-975f-93bc4a272e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807153236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.807153236
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.1560585722
Short name T639
Test name
Test status
Simulation time 17607660 ps
CPU time 0.96 seconds
Started Jan 03 12:48:24 PM PST 24
Finished Jan 03 12:48:48 PM PST 24
Peak memory 205252 kb
Host smart-a328ab88-3c48-4b2c-84b3-552f5108db26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560585722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.1560585722
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.1709536182
Short name T282
Test name
Test status
Simulation time 26564497 ps
CPU time 0.95 seconds
Started Jan 03 12:48:02 PM PST 24
Finished Jan 03 12:48:35 PM PST 24
Peak memory 205028 kb
Host smart-1b2d40a3-a56a-414b-b5b3-20049e007a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709536182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.1709536182
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.2879890736
Short name T616
Test name
Test status
Simulation time 15882606 ps
CPU time 1.02 seconds
Started Jan 03 12:48:08 PM PST 24
Finished Jan 03 12:48:37 PM PST 24
Peak memory 205204 kb
Host smart-07090152-069b-4bb6-9488-32d657fb863e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879890736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.2879890736
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1852710922
Short name T910
Test name
Test status
Simulation time 15044962 ps
CPU time 0.9 seconds
Started Jan 03 12:48:25 PM PST 24
Finished Jan 03 12:48:49 PM PST 24
Peak memory 205388 kb
Host smart-78e250db-3d09-4a28-990d-b15a2d7552f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852710922 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1852710922
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.4099439279
Short name T598
Test name
Test status
Simulation time 237723699 ps
CPU time 3.41 seconds
Started Jan 03 12:48:16 PM PST 24
Finished Jan 03 12:48:46 PM PST 24
Peak memory 214332 kb
Host smart-5ec0f9aa-369c-4687-9b5e-f85133a81f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099439279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.4099439279
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.2716264069
Short name T664
Test name
Test status
Simulation time 46562225 ps
CPU time 1.06 seconds
Started Jan 03 12:45:40 PM PST 24
Finished Jan 03 12:47:28 PM PST 24
Peak memory 205944 kb
Host smart-72b4883e-b457-4147-8b57-0752bb66a5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716264069 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.2716264069
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.620511839
Short name T458
Test name
Test status
Simulation time 17582797 ps
CPU time 0.81 seconds
Started Jan 03 12:46:06 PM PST 24
Finished Jan 03 12:47:37 PM PST 24
Peak memory 205100 kb
Host smart-29c1876c-9a61-43c5-9e21-7aa2768f0c88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620511839 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.620511839
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.2726477275
Short name T568
Test name
Test status
Simulation time 87291154 ps
CPU time 1.03 seconds
Started Jan 03 12:45:25 PM PST 24
Finished Jan 03 12:47:05 PM PST 24
Peak memory 215744 kb
Host smart-822d16b3-c7b7-44ae-aa63-57440a74dd8d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726477275 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.2726477275
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.1165936733
Short name T680
Test name
Test status
Simulation time 20466326 ps
CPU time 1.02 seconds
Started Jan 03 12:45:55 PM PST 24
Finished Jan 03 12:47:36 PM PST 24
Peak memory 221808 kb
Host smart-8960d9bd-9d05-4400-9384-2732b2f8a941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165936733 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.1165936733
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_intr.2398553868
Short name T75
Test name
Test status
Simulation time 36077536 ps
CPU time 0.86 seconds
Started Jan 03 12:45:22 PM PST 24
Finished Jan 03 12:47:02 PM PST 24
Peak memory 214520 kb
Host smart-0ae68cdb-a773-46fe-8a7e-d86d33135754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398553868 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.2398553868
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.1330990860
Short name T678
Test name
Test status
Simulation time 45805590 ps
CPU time 0.88 seconds
Started Jan 03 12:45:31 PM PST 24
Finished Jan 03 12:47:28 PM PST 24
Peak memory 205112 kb
Host smart-89a41d46-9ac7-4573-b3ca-847148987e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330990860 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.1330990860
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.395948525
Short name T793
Test name
Test status
Simulation time 857354466 ps
CPU time 3.96 seconds
Started Jan 03 12:46:00 PM PST 24
Finished Jan 03 12:47:27 PM PST 24
Peak memory 206136 kb
Host smart-61814601-dd7b-4456-934f-831e9cbfd8b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395948525 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.395948525
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/270.edn_genbits.3098374406
Short name T635
Test name
Test status
Simulation time 245765670 ps
CPU time 1.53 seconds
Started Jan 03 12:48:13 PM PST 24
Finished Jan 03 12:48:41 PM PST 24
Peak memory 214328 kb
Host smart-0486af41-fb4f-4161-a890-38aca7bb1f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098374406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.3098374406
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.3700518472
Short name T231
Test name
Test status
Simulation time 33510427 ps
CPU time 1.22 seconds
Started Jan 03 12:48:18 PM PST 24
Finished Jan 03 12:48:44 PM PST 24
Peak memory 205628 kb
Host smart-9ef88b48-2024-4249-b85a-713ba84b0667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700518472 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.3700518472
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.1363262632
Short name T385
Test name
Test status
Simulation time 15962089 ps
CPU time 1.04 seconds
Started Jan 03 12:48:22 PM PST 24
Finished Jan 03 12:48:47 PM PST 24
Peak memory 205572 kb
Host smart-8f7c648b-bc66-4e8a-a67c-91de2ca4e415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363262632 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1363262632
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.1434015684
Short name T706
Test name
Test status
Simulation time 18104433 ps
CPU time 1.03 seconds
Started Jan 03 12:48:18 PM PST 24
Finished Jan 03 12:48:44 PM PST 24
Peak memory 214260 kb
Host smart-5ab6ce3d-933c-43d0-8068-40fa4cdff23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434015684 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.1434015684
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.94220416
Short name T698
Test name
Test status
Simulation time 49378781 ps
CPU time 0.88 seconds
Started Jan 03 12:48:01 PM PST 24
Finished Jan 03 12:48:34 PM PST 24
Peak memory 204896 kb
Host smart-9532357e-27d3-4ae5-bd41-60f797767bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94220416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.94220416
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2143079249
Short name T233
Test name
Test status
Simulation time 34469261 ps
CPU time 0.9 seconds
Started Jan 03 12:48:05 PM PST 24
Finished Jan 03 12:48:36 PM PST 24
Peak memory 205204 kb
Host smart-2b457727-8fb3-4a85-b86c-7754c4369870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143079249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2143079249
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.3780531664
Short name T645
Test name
Test status
Simulation time 22517848 ps
CPU time 0.97 seconds
Started Jan 03 12:48:19 PM PST 24
Finished Jan 03 12:48:46 PM PST 24
Peak memory 205592 kb
Host smart-ac5ed300-dfd0-4c14-84fb-00e142f6ffd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780531664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3780531664
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.446679736
Short name T870
Test name
Test status
Simulation time 21292640 ps
CPU time 0.9 seconds
Started Jan 03 12:48:01 PM PST 24
Finished Jan 03 12:48:34 PM PST 24
Peak memory 204876 kb
Host smart-56792abf-c1fb-4274-b400-9e02fd1d2a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446679736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.446679736
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.2438764836
Short name T271
Test name
Test status
Simulation time 69476697 ps
CPU time 0.88 seconds
Started Jan 03 12:48:21 PM PST 24
Finished Jan 03 12:48:46 PM PST 24
Peak memory 205216 kb
Host smart-7dd3effb-541f-4f0f-9c03-9d66d463cb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438764836 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.2438764836
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.335942537
Short name T229
Test name
Test status
Simulation time 18859758 ps
CPU time 1.07 seconds
Started Jan 03 12:45:34 PM PST 24
Finished Jan 03 12:47:06 PM PST 24
Peak memory 205964 kb
Host smart-91c540ae-be97-429d-b052-9d4fd7f69d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335942537 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.335942537
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.3450666328
Short name T666
Test name
Test status
Simulation time 16695007 ps
CPU time 0.9 seconds
Started Jan 03 12:45:58 PM PST 24
Finished Jan 03 12:47:44 PM PST 24
Peak memory 205132 kb
Host smart-177c3bbe-a4ce-400f-a06c-ef35bc718abb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450666328 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.3450666328
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.3218163306
Short name T643
Test name
Test status
Simulation time 46746306 ps
CPU time 0.84 seconds
Started Jan 03 12:45:44 PM PST 24
Finished Jan 03 12:47:46 PM PST 24
Peak memory 214556 kb
Host smart-1ca1de60-e5f7-43cc-806f-013cb708e2e9
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218163306 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.3218163306
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.1812611579
Short name T566
Test name
Test status
Simulation time 33772237 ps
CPU time 0.95 seconds
Started Jan 03 12:45:42 PM PST 24
Finished Jan 03 12:47:13 PM PST 24
Peak memory 214692 kb
Host smart-c5caea8b-2cd8-43b0-b969-30a38213e261
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812611579 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.1812611579
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.1419757741
Short name T827
Test name
Test status
Simulation time 68781603 ps
CPU time 0.77 seconds
Started Jan 03 12:45:34 PM PST 24
Finished Jan 03 12:47:46 PM PST 24
Peak memory 215868 kb
Host smart-627504b8-cfbb-445c-bd32-935ee06460d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419757741 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.1419757741
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.2437072201
Short name T720
Test name
Test status
Simulation time 52257216 ps
CPU time 0.89 seconds
Started Jan 03 12:45:25 PM PST 24
Finished Jan 03 12:47:18 PM PST 24
Peak memory 205136 kb
Host smart-4e5a000d-c2f9-49ef-a1c7-27f90fbf6420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437072201 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.2437072201
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.3078722568
Short name T723
Test name
Test status
Simulation time 46837576 ps
CPU time 0.79 seconds
Started Jan 03 12:45:48 PM PST 24
Finished Jan 03 12:47:14 PM PST 24
Peak memory 214356 kb
Host smart-f0f7b0f3-de6d-4af4-a76b-2c096c04adac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078722568 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.3078722568
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.857299987
Short name T39
Test name
Test status
Simulation time 15384253 ps
CPU time 0.87 seconds
Started Jan 03 12:45:22 PM PST 24
Finished Jan 03 12:46:59 PM PST 24
Peak memory 204660 kb
Host smart-ad9e5726-322f-466b-9c67-26f46b707a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857299987 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.857299987
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.3000215704
Short name T518
Test name
Test status
Simulation time 140290546 ps
CPU time 2.27 seconds
Started Jan 03 12:46:11 PM PST 24
Finished Jan 03 12:47:35 PM PST 24
Peak memory 205896 kb
Host smart-f70703ce-1b16-4ccb-996c-54973f0d778f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000215704 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.3000215704
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.699868388
Short name T397
Test name
Test status
Simulation time 107438195074 ps
CPU time 2134.72 seconds
Started Jan 03 12:45:57 PM PST 24
Finished Jan 03 01:23:04 PM PST 24
Peak memory 221896 kb
Host smart-e884a7a5-98a7-4d23-876e-77c0ba692727
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699868388 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.699868388
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.1771404094
Short name T585
Test name
Test status
Simulation time 24825095 ps
CPU time 0.99 seconds
Started Jan 03 12:48:15 PM PST 24
Finished Jan 03 12:48:42 PM PST 24
Peak memory 214116 kb
Host smart-3d1ae0fe-7582-43bd-b9db-f86598db8cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771404094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.1771404094
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.402221747
Short name T520
Test name
Test status
Simulation time 38836793 ps
CPU time 0.9 seconds
Started Jan 03 12:48:15 PM PST 24
Finished Jan 03 12:48:42 PM PST 24
Peak memory 205276 kb
Host smart-5dbe95c8-42d3-4cfc-be15-50e0725c1a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402221747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.402221747
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.4259197879
Short name T488
Test name
Test status
Simulation time 21216351 ps
CPU time 1.06 seconds
Started Jan 03 12:48:13 PM PST 24
Finished Jan 03 12:48:41 PM PST 24
Peak memory 205228 kb
Host smart-d82f1312-5bbb-442b-8945-8419d07a5a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259197879 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.4259197879
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.3884004409
Short name T266
Test name
Test status
Simulation time 13710708 ps
CPU time 1.02 seconds
Started Jan 03 12:47:49 PM PST 24
Finished Jan 03 12:48:28 PM PST 24
Peak memory 205484 kb
Host smart-abdbe326-9c07-4205-a35b-916adefa34e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884004409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.3884004409
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.2986034688
Short name T761
Test name
Test status
Simulation time 31123920 ps
CPU time 1.01 seconds
Started Jan 03 12:48:19 PM PST 24
Finished Jan 03 12:48:45 PM PST 24
Peak memory 205752 kb
Host smart-a8e4c7c5-37dc-45a7-88a5-22eb61d6487e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986034688 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.2986034688
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.353586358
Short name T551
Test name
Test status
Simulation time 48752723 ps
CPU time 0.89 seconds
Started Jan 03 12:48:15 PM PST 24
Finished Jan 03 12:48:42 PM PST 24
Peak memory 205252 kb
Host smart-92482230-5839-42f8-941d-a190cdfc2754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353586358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.353586358
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.3874247195
Short name T482
Test name
Test status
Simulation time 43557333 ps
CPU time 1.26 seconds
Started Jan 03 12:48:41 PM PST 24
Finished Jan 03 12:49:07 PM PST 24
Peak memory 214228 kb
Host smart-2ab95d6a-f3c8-41db-90a8-75292c248445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874247195 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.3874247195
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.289507545
Short name T270
Test name
Test status
Simulation time 28847611 ps
CPU time 1.35 seconds
Started Jan 03 12:47:58 PM PST 24
Finished Jan 03 12:48:33 PM PST 24
Peak memory 214292 kb
Host smart-d4f2821a-7edd-4f6c-a047-9eacda990406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289507545 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.289507545
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.2266218109
Short name T570
Test name
Test status
Simulation time 19982241 ps
CPU time 0.92 seconds
Started Jan 03 12:47:59 PM PST 24
Finished Jan 03 12:48:33 PM PST 24
Peak memory 204900 kb
Host smart-b1bceb91-b159-4828-a851-601b691e6e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266218109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.2266218109
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.3556488843
Short name T777
Test name
Test status
Simulation time 44448560 ps
CPU time 1.21 seconds
Started Jan 03 12:48:17 PM PST 24
Finished Jan 03 12:48:44 PM PST 24
Peak memory 214248 kb
Host smart-e60ba75a-b026-44c9-bf29-233b195c7077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556488843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.3556488843
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.1010436204
Short name T219
Test name
Test status
Simulation time 19231066 ps
CPU time 0.94 seconds
Started Jan 03 12:45:35 PM PST 24
Finished Jan 03 12:47:07 PM PST 24
Peak memory 205076 kb
Host smart-43d6f485-9095-4fc5-933b-0237f619cd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010436204 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.1010436204
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.1567072975
Short name T780
Test name
Test status
Simulation time 40852889 ps
CPU time 0.98 seconds
Started Jan 03 12:45:57 PM PST 24
Finished Jan 03 12:47:30 PM PST 24
Peak memory 205200 kb
Host smart-304f8b46-6302-4975-a0f4-f5d6ca033ed8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567072975 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.1567072975
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.70708851
Short name T107
Test name
Test status
Simulation time 23084902 ps
CPU time 0.85 seconds
Started Jan 03 12:45:54 PM PST 24
Finished Jan 03 12:47:28 PM PST 24
Peak memory 214628 kb
Host smart-d55425b4-5666-43b1-9033-5ea1bb0c29f3
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70708851 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.70708851
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.372077766
Short name T693
Test name
Test status
Simulation time 141650479 ps
CPU time 1.11 seconds
Started Jan 03 12:45:44 PM PST 24
Finished Jan 03 12:47:28 PM PST 24
Peak memory 214428 kb
Host smart-59a5cd29-a142-4961-9c9b-a61f71d1b8af
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372077766 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_di
sable_auto_req_mode.372077766
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.3365722278
Short name T621
Test name
Test status
Simulation time 34433392 ps
CPU time 0.89 seconds
Started Jan 03 12:45:44 PM PST 24
Finished Jan 03 12:47:16 PM PST 24
Peak memory 214672 kb
Host smart-2c96909d-3199-4487-af7f-cb08c3d4f66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365722278 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.3365722278
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.1633019427
Short name T718
Test name
Test status
Simulation time 16654244 ps
CPU time 0.93 seconds
Started Jan 03 12:45:44 PM PST 24
Finished Jan 03 12:47:16 PM PST 24
Peak memory 205380 kb
Host smart-2c4372fc-90df-4bcd-9e97-541c0e151604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633019427 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.1633019427
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_smoke.2061044047
Short name T363
Test name
Test status
Simulation time 29131079 ps
CPU time 0.79 seconds
Started Jan 03 12:45:59 PM PST 24
Finished Jan 03 12:47:24 PM PST 24
Peak memory 204724 kb
Host smart-d62a8953-503e-4ba0-a925-9379d8760955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061044047 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.2061044047
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.2779748881
Short name T665
Test name
Test status
Simulation time 608417962 ps
CPU time 2.92 seconds
Started Jan 03 12:46:35 PM PST 24
Finished Jan 03 12:47:51 PM PST 24
Peak memory 205516 kb
Host smart-66785c98-43b7-4011-904c-bfd7a43dfa49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779748881 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.2779748881
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.1820583364
Short name T253
Test name
Test status
Simulation time 35184697006 ps
CPU time 836.16 seconds
Started Jan 03 12:45:26 PM PST 24
Finished Jan 03 01:00:54 PM PST 24
Peak memory 215288 kb
Host smart-6890d2c9-c24a-4ff6-9ff9-c55c384dd2dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820583364 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.1820583364
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.1560091848
Short name T783
Test name
Test status
Simulation time 18469538 ps
CPU time 1.23 seconds
Started Jan 03 12:48:09 PM PST 24
Finished Jan 03 12:48:38 PM PST 24
Peak memory 205772 kb
Host smart-150d5146-8bec-43cd-b42e-1bd751aae735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560091848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.1560091848
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.219992084
Short name T85
Test name
Test status
Simulation time 76590106 ps
CPU time 1.03 seconds
Started Jan 03 12:48:09 PM PST 24
Finished Jan 03 12:48:38 PM PST 24
Peak memory 205308 kb
Host smart-3f21df00-e5a5-4af3-8a82-1362aa5ef3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219992084 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.219992084
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.2665182065
Short name T854
Test name
Test status
Simulation time 13499681 ps
CPU time 0.89 seconds
Started Jan 03 12:48:11 PM PST 24
Finished Jan 03 12:48:39 PM PST 24
Peak memory 205036 kb
Host smart-43f4be8b-c7c2-45e2-93cd-872758106715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665182065 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.2665182065
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.2142365370
Short name T578
Test name
Test status
Simulation time 129418823 ps
CPU time 2.34 seconds
Started Jan 03 12:48:16 PM PST 24
Finished Jan 03 12:48:44 PM PST 24
Peak memory 214248 kb
Host smart-00a01a40-d84c-4268-9414-8a26032908c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142365370 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2142365370
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.1325847907
Short name T674
Test name
Test status
Simulation time 101711530 ps
CPU time 1.07 seconds
Started Jan 03 12:48:13 PM PST 24
Finished Jan 03 12:48:41 PM PST 24
Peak memory 214352 kb
Host smart-62f6ac66-ef53-4b04-ab4c-615d867fcfca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325847907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.1325847907
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.1278836088
Short name T207
Test name
Test status
Simulation time 27551631 ps
CPU time 1.16 seconds
Started Jan 03 12:48:08 PM PST 24
Finished Jan 03 12:48:38 PM PST 24
Peak memory 206028 kb
Host smart-f4d21fdb-8c20-4181-9693-40c8f72e1eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278836088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.1278836088
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.2489751974
Short name T33
Test name
Test status
Simulation time 53503006 ps
CPU time 1.01 seconds
Started Jan 03 12:48:02 PM PST 24
Finished Jan 03 12:48:35 PM PST 24
Peak memory 205576 kb
Host smart-ac170224-7d67-46b7-a5cc-b946a2d3150d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489751974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.2489751974
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.2057595272
Short name T762
Test name
Test status
Simulation time 60674538 ps
CPU time 1.12 seconds
Started Jan 03 12:48:22 PM PST 24
Finished Jan 03 12:48:47 PM PST 24
Peak memory 205416 kb
Host smart-322f167c-0508-411a-b6bb-2a699ea48eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057595272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.2057595272
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.3212787078
Short name T735
Test name
Test status
Simulation time 65258220 ps
CPU time 2.63 seconds
Started Jan 03 12:48:07 PM PST 24
Finished Jan 03 12:48:39 PM PST 24
Peak memory 214128 kb
Host smart-2885208e-fa79-4085-b715-370e146552e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212787078 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.3212787078
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.3564480433
Short name T526
Test name
Test status
Simulation time 34660014 ps
CPU time 0.99 seconds
Started Jan 03 12:48:36 PM PST 24
Finished Jan 03 12:49:03 PM PST 24
Peak memory 205560 kb
Host smart-44159a1d-3b37-4059-9bd3-3c5c4b163ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564480433 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.3564480433
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.108669688
Short name T771
Test name
Test status
Simulation time 18677407 ps
CPU time 0.97 seconds
Started Jan 03 12:45:01 PM PST 24
Finished Jan 03 12:46:35 PM PST 24
Peak memory 206056 kb
Host smart-30271716-f594-44b3-bcc3-1fddaca5fe41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108669688 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.108669688
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_err.1512445691
Short name T613
Test name
Test status
Simulation time 32774749 ps
CPU time 0.86 seconds
Started Jan 03 12:45:20 PM PST 24
Finished Jan 03 12:46:53 PM PST 24
Peak memory 215640 kb
Host smart-0d1ee32c-e438-41ee-b50c-37277f8beba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512445691 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.1512445691
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.2872338813
Short name T675
Test name
Test status
Simulation time 16328233 ps
CPU time 0.99 seconds
Started Jan 03 12:45:31 PM PST 24
Finished Jan 03 12:47:09 PM PST 24
Peak memory 205356 kb
Host smart-ae97fd09-5388-4ba0-8c5b-d81926c42156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872338813 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.2872338813
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.2296643676
Short name T97
Test name
Test status
Simulation time 19143918 ps
CPU time 1.05 seconds
Started Jan 03 12:45:02 PM PST 24
Finished Jan 03 12:46:54 PM PST 24
Peak memory 214472 kb
Host smart-1e7198c9-33ed-4749-8bec-40be3be00741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296643676 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.2296643676
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.1299918566
Short name T210
Test name
Test status
Simulation time 15101617 ps
CPU time 0.87 seconds
Started Jan 03 12:45:09 PM PST 24
Finished Jan 03 12:46:44 PM PST 24
Peak memory 205000 kb
Host smart-e47207ac-c74e-4d75-96ad-91b5e4a7f020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299918566 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.1299918566
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_smoke.2288004903
Short name T790
Test name
Test status
Simulation time 27332219 ps
CPU time 0.81 seconds
Started Jan 03 12:45:13 PM PST 24
Finished Jan 03 12:46:47 PM PST 24
Peak memory 204964 kb
Host smart-4bf9c88a-3fcf-4352-89a5-6b042e676460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288004903 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.2288004903
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.1320713892
Short name T850
Test name
Test status
Simulation time 301819463 ps
CPU time 1.99 seconds
Started Jan 03 12:45:22 PM PST 24
Finished Jan 03 12:47:06 PM PST 24
Peak memory 206084 kb
Host smart-80a0c089-9664-448f-812c-be22d6aee4a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320713892 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.1320713892
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3954817506
Short name T627
Test name
Test status
Simulation time 37944473877 ps
CPU time 414.46 seconds
Started Jan 03 12:45:49 PM PST 24
Finished Jan 03 12:54:12 PM PST 24
Peak memory 215164 kb
Host smart-127ad97b-33ef-4ac1-a1f3-c45d03dfb4f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954817506 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3954817506
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.3868592366
Short name T801
Test name
Test status
Simulation time 60132923 ps
CPU time 0.95 seconds
Started Jan 03 12:45:43 PM PST 24
Finished Jan 03 12:47:28 PM PST 24
Peak memory 206096 kb
Host smart-833626fa-cdf7-4025-9883-2130a2bcfe2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868592366 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.3868592366
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.3631611712
Short name T624
Test name
Test status
Simulation time 40802844 ps
CPU time 0.84 seconds
Started Jan 03 12:45:47 PM PST 24
Finished Jan 03 12:47:41 PM PST 24
Peak memory 204556 kb
Host smart-43c4ef21-b95a-4e59-b6fe-6e74fd65bf28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631611712 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3631611712
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.3557377329
Short name T673
Test name
Test status
Simulation time 17360451 ps
CPU time 0.88 seconds
Started Jan 03 12:45:42 PM PST 24
Finished Jan 03 12:47:09 PM PST 24
Peak memory 214476 kb
Host smart-5c7b3e72-9140-4805-8a5e-c72b4cf15394
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557377329 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.3557377329
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.2810671386
Short name T908
Test name
Test status
Simulation time 188982106 ps
CPU time 1 seconds
Started Jan 03 12:46:29 PM PST 24
Finished Jan 03 12:47:51 PM PST 24
Peak memory 214648 kb
Host smart-e561c1f6-a9eb-48fb-9e84-b37d5658bd64
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810671386 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.2810671386
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_genbits.2873040618
Short name T833
Test name
Test status
Simulation time 14812237 ps
CPU time 0.86 seconds
Started Jan 03 12:46:00 PM PST 24
Finished Jan 03 12:47:24 PM PST 24
Peak memory 205016 kb
Host smart-04a1f0e8-d85e-4141-98a5-e06bbe78411f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873040618 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.2873040618
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.3411286374
Short name T14
Test name
Test status
Simulation time 21238631 ps
CPU time 1.14 seconds
Started Jan 03 12:46:04 PM PST 24
Finished Jan 03 12:47:27 PM PST 24
Peak memory 221500 kb
Host smart-3ee79d63-1dce-4943-a84d-05f35bf75c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411286374 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.3411286374
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.3974613520
Short name T581
Test name
Test status
Simulation time 75815059 ps
CPU time 0.82 seconds
Started Jan 03 12:45:51 PM PST 24
Finished Jan 03 12:47:22 PM PST 24
Peak memory 204932 kb
Host smart-9da1d034-2c25-4ad8-af88-0717cdd1fd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974613520 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.3974613520
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.179595346
Short name T533
Test name
Test status
Simulation time 29364861 ps
CPU time 1.09 seconds
Started Jan 03 12:46:10 PM PST 24
Finished Jan 03 12:47:40 PM PST 24
Peak memory 205384 kb
Host smart-b7e47488-000e-48ec-98ae-b5a9529995cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179595346 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.179595346
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.610373392
Short name T595
Test name
Test status
Simulation time 49149451962 ps
CPU time 240.06 seconds
Started Jan 03 12:45:43 PM PST 24
Finished Jan 03 12:51:11 PM PST 24
Peak memory 215484 kb
Host smart-2b333596-024d-4cb4-9234-52be601e80ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610373392 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.610373392
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.331251459
Short name T875
Test name
Test status
Simulation time 53423268 ps
CPU time 0.9 seconds
Started Jan 03 12:45:45 PM PST 24
Finished Jan 03 12:47:43 PM PST 24
Peak memory 205228 kb
Host smart-b8741088-8161-4756-9777-b864ace21c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331251459 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.331251459
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.3023996328
Short name T615
Test name
Test status
Simulation time 53518116 ps
CPU time 0.85 seconds
Started Jan 03 12:45:35 PM PST 24
Finished Jan 03 12:47:04 PM PST 24
Peak memory 204608 kb
Host smart-2e2d1549-7cd2-4ed3-b7ac-93732726da3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023996328 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.3023996328
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_err.2564922806
Short name T476
Test name
Test status
Simulation time 31707785 ps
CPU time 0.89 seconds
Started Jan 03 12:45:39 PM PST 24
Finished Jan 03 12:47:10 PM PST 24
Peak memory 221236 kb
Host smart-4ecb4e2a-8744-45bd-a8df-f6bf6c6b6d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564922806 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.2564922806
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.1566635424
Short name T237
Test name
Test status
Simulation time 147682888 ps
CPU time 3.11 seconds
Started Jan 03 12:45:44 PM PST 24
Finished Jan 03 12:47:18 PM PST 24
Peak memory 214164 kb
Host smart-0c919985-2f20-4304-aec6-0691547c7021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566635424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.1566635424
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.3498000743
Short name T797
Test name
Test status
Simulation time 18613436 ps
CPU time 0.92 seconds
Started Jan 03 12:45:48 PM PST 24
Finished Jan 03 12:47:30 PM PST 24
Peak memory 214512 kb
Host smart-2fc7d1bc-8351-4d18-8f1d-3849368cd357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498000743 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.3498000743
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.3429874104
Short name T711
Test name
Test status
Simulation time 55331016 ps
CPU time 0.81 seconds
Started Jan 03 12:45:56 PM PST 24
Finished Jan 03 12:47:22 PM PST 24
Peak memory 204692 kb
Host smart-e0d91401-c1ec-4051-aab5-53a31329140e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429874104 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.3429874104
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.2041882466
Short name T198
Test name
Test status
Simulation time 48822117405 ps
CPU time 1057.59 seconds
Started Jan 03 12:45:30 PM PST 24
Finished Jan 03 01:04:44 PM PST 24
Peak memory 215156 kb
Host smart-4901a91c-fcfe-4fff-ab2d-a15ce90a0286
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041882466 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.2041882466
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.611165901
Short name T740
Test name
Test status
Simulation time 45834987 ps
CPU time 0.93 seconds
Started Jan 03 12:45:46 PM PST 24
Finished Jan 03 12:47:11 PM PST 24
Peak memory 205480 kb
Host smart-0c70c6c4-b697-4e62-947a-ee26e40b075e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611165901 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.611165901
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.570466283
Short name T661
Test name
Test status
Simulation time 24214367 ps
CPU time 0.83 seconds
Started Jan 03 12:45:35 PM PST 24
Finished Jan 03 12:47:19 PM PST 24
Peak memory 204564 kb
Host smart-ff04b90f-42f7-468e-af3c-dc99590c1b24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570466283 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.570466283
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.934804405
Short name T880
Test name
Test status
Simulation time 25995780 ps
CPU time 0.92 seconds
Started Jan 03 12:46:03 PM PST 24
Finished Jan 03 12:47:28 PM PST 24
Peak memory 214468 kb
Host smart-57f3ecc5-9e29-4857-a078-4441d1f87f74
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934804405 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.934804405
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.3832859788
Short name T446
Test name
Test status
Simulation time 31028719 ps
CPU time 1.06 seconds
Started Jan 03 12:45:49 PM PST 24
Finished Jan 03 12:47:14 PM PST 24
Peak memory 214712 kb
Host smart-25e45f2f-dff4-4684-b4cc-589eae0181a3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832859788 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.3832859788
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.4132948455
Short name T834
Test name
Test status
Simulation time 20846794 ps
CPU time 1.07 seconds
Started Jan 03 12:45:35 PM PST 24
Finished Jan 03 12:47:12 PM PST 24
Peak memory 221724 kb
Host smart-4516b074-c313-4549-8150-4943e6e51870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132948455 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.4132948455
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.4180128560
Short name T704
Test name
Test status
Simulation time 114883711 ps
CPU time 0.96 seconds
Started Jan 03 12:45:46 PM PST 24
Finished Jan 03 12:47:11 PM PST 24
Peak memory 205068 kb
Host smart-1285b284-427c-466d-840e-b4dcdafdb720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180128560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.4180128560
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.3460157073
Short name T94
Test name
Test status
Simulation time 18938226 ps
CPU time 1.05 seconds
Started Jan 03 12:46:05 PM PST 24
Finished Jan 03 12:47:31 PM PST 24
Peak memory 214488 kb
Host smart-aa88a12d-5919-4235-b866-299f81df1156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460157073 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.3460157073
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.2891679948
Short name T574
Test name
Test status
Simulation time 37941423 ps
CPU time 0.78 seconds
Started Jan 03 12:46:03 PM PST 24
Finished Jan 03 12:47:28 PM PST 24
Peak memory 204824 kb
Host smart-92290a59-35d8-49fc-a37d-952f0dfac4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891679948 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.2891679948
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.530618358
Short name T546
Test name
Test status
Simulation time 1338025457 ps
CPU time 2.19 seconds
Started Jan 03 12:46:07 PM PST 24
Finished Jan 03 12:47:33 PM PST 24
Peak memory 205512 kb
Host smart-47ce0a25-414b-467a-a994-aef43f570c3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530618358 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.530618358
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.327346651
Short name T603
Test name
Test status
Simulation time 71891775529 ps
CPU time 395.16 seconds
Started Jan 03 12:46:04 PM PST 24
Finished Jan 03 12:54:15 PM PST 24
Peak memory 216812 kb
Host smart-8b23bc0d-538a-47ca-a099-7e59925032da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327346651 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.327346651
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.2040060595
Short name T862
Test name
Test status
Simulation time 19031314 ps
CPU time 0.97 seconds
Started Jan 03 12:45:51 PM PST 24
Finished Jan 03 12:47:29 PM PST 24
Peak memory 206168 kb
Host smart-30b8a410-86e7-46a5-a711-a601fce0c129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040060595 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.2040060595
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.3486315427
Short name T727
Test name
Test status
Simulation time 25737158 ps
CPU time 0.85 seconds
Started Jan 03 12:45:37 PM PST 24
Finished Jan 03 12:47:19 PM PST 24
Peak memory 205148 kb
Host smart-4df3180e-279e-429c-9c42-59f5e26b7fbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486315427 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.3486315427
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.3666896780
Short name T483
Test name
Test status
Simulation time 11350842 ps
CPU time 0.87 seconds
Started Jan 03 12:45:22 PM PST 24
Finished Jan 03 12:47:07 PM PST 24
Peak memory 214524 kb
Host smart-4d8315e8-2580-460d-a587-38adf9b6706b
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666896780 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.3666896780
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.3754263508
Short name T505
Test name
Test status
Simulation time 66703872 ps
CPU time 0.94 seconds
Started Jan 03 12:46:09 PM PST 24
Finished Jan 03 12:47:34 PM PST 24
Peak memory 214476 kb
Host smart-2a25e303-fd60-4247-9eba-5999b7cc8d5d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754263508 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.3754263508
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.918806778
Short name T690
Test name
Test status
Simulation time 73090095 ps
CPU time 1.02 seconds
Started Jan 03 12:45:50 PM PST 24
Finished Jan 03 12:47:18 PM PST 24
Peak memory 228416 kb
Host smart-d012a6b1-96d4-4662-88ba-4714df52eecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918806778 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.918806778
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.4188380813
Short name T286
Test name
Test status
Simulation time 47453949 ps
CPU time 1.25 seconds
Started Jan 03 12:45:42 PM PST 24
Finished Jan 03 12:47:13 PM PST 24
Peak memory 214344 kb
Host smart-9f7c00ea-7eb6-4f04-b3a9-69cffdc04439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188380813 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.4188380813
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.1455296063
Short name T96
Test name
Test status
Simulation time 17865009 ps
CPU time 1.01 seconds
Started Jan 03 12:45:53 PM PST 24
Finished Jan 03 12:47:30 PM PST 24
Peak memory 214496 kb
Host smart-aabcca6e-89d3-46ab-9c0a-8e1231c26cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455296063 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.1455296063
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.2803953796
Short name T692
Test name
Test status
Simulation time 15994247 ps
CPU time 0.93 seconds
Started Jan 03 12:46:08 PM PST 24
Finished Jan 03 12:47:31 PM PST 24
Peak memory 204796 kb
Host smart-1234a230-9a70-4f87-9caf-cb40ec2fb5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803953796 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.2803953796
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.2893855415
Short name T788
Test name
Test status
Simulation time 21351244 ps
CPU time 0.99 seconds
Started Jan 03 12:45:45 PM PST 24
Finished Jan 03 12:47:15 PM PST 24
Peak memory 205040 kb
Host smart-3ccc9504-7608-49de-a021-161e2dbfcf37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893855415 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.2893855415
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.4024063413
Short name T260
Test name
Test status
Simulation time 55004969418 ps
CPU time 1158.94 seconds
Started Jan 03 12:46:02 PM PST 24
Finished Jan 03 01:06:53 PM PST 24
Peak memory 214468 kb
Host smart-bb7d9a6a-ab3a-4951-a0eb-2f8fb4d34ed3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024063413 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.4024063413
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.1762744106
Short name T18
Test name
Test status
Simulation time 49092825 ps
CPU time 0.94 seconds
Started Jan 03 12:45:44 PM PST 24
Finished Jan 03 12:47:16 PM PST 24
Peak memory 205416 kb
Host smart-2f923397-949c-4604-be06-843a7af3f317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762744106 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.1762744106
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.1655410805
Short name T46
Test name
Test status
Simulation time 16573750 ps
CPU time 0.89 seconds
Started Jan 03 12:45:55 PM PST 24
Finished Jan 03 12:47:43 PM PST 24
Peak memory 204712 kb
Host smart-0f7c1934-7f11-4a82-8dca-db4fe3b6fc53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655410805 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1655410805
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.3431689014
Short name T810
Test name
Test status
Simulation time 25997064 ps
CPU time 1.02 seconds
Started Jan 03 12:46:32 PM PST 24
Finished Jan 03 12:47:49 PM PST 24
Peak memory 214532 kb
Host smart-72498d1d-a863-44d2-9597-d612733024b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431689014 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.3431689014
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.786736506
Short name T587
Test name
Test status
Simulation time 35644683 ps
CPU time 1.04 seconds
Started Jan 03 12:45:42 PM PST 24
Finished Jan 03 12:47:09 PM PST 24
Peak memory 215904 kb
Host smart-0cfff542-d6d7-4354-8587-a56ccf64152f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786736506 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.786736506
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.4007078400
Short name T739
Test name
Test status
Simulation time 29145638 ps
CPU time 0.87 seconds
Started Jan 03 12:45:32 PM PST 24
Finished Jan 03 12:47:10 PM PST 24
Peak memory 205020 kb
Host smart-d0021fb5-0e0a-422c-b7da-3b90f6301216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007078400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.4007078400
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.1225209761
Short name T542
Test name
Test status
Simulation time 27080921 ps
CPU time 0.82 seconds
Started Jan 03 12:45:45 PM PST 24
Finished Jan 03 12:47:14 PM PST 24
Peak memory 214400 kb
Host smart-0eb3c982-e373-4975-9603-286030825bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225209761 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.1225209761
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.730995452
Short name T631
Test name
Test status
Simulation time 19967864 ps
CPU time 0.84 seconds
Started Jan 03 12:46:01 PM PST 24
Finished Jan 03 12:47:41 PM PST 24
Peak memory 204868 kb
Host smart-b04f0d2f-c946-40e9-898b-47fcbb2022fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730995452 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.730995452
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.4190746353
Short name T686
Test name
Test status
Simulation time 589491441 ps
CPU time 3.29 seconds
Started Jan 03 12:45:34 PM PST 24
Finished Jan 03 12:47:15 PM PST 24
Peak memory 206004 kb
Host smart-f83150d7-ff69-4f08-aef2-d33480e62175
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190746353 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.4190746353
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.2272628697
Short name T889
Test name
Test status
Simulation time 31184167743 ps
CPU time 740.03 seconds
Started Jan 03 12:45:53 PM PST 24
Finished Jan 03 12:59:37 PM PST 24
Peak memory 215548 kb
Host smart-64a19fce-c0e0-41b1-b2c8-e1bbc58679fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272628697 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.2272628697
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.1072292703
Short name T184
Test name
Test status
Simulation time 26431971 ps
CPU time 0.93 seconds
Started Jan 03 12:45:50 PM PST 24
Finished Jan 03 12:47:18 PM PST 24
Peak memory 206024 kb
Host smart-ddbc5ce3-ff84-4c99-a2d4-19a19e9d4e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072292703 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.1072292703
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.832385025
Short name T602
Test name
Test status
Simulation time 60369387 ps
CPU time 0.84 seconds
Started Jan 03 12:45:45 PM PST 24
Finished Jan 03 12:47:12 PM PST 24
Peak memory 205180 kb
Host smart-69c8106b-3401-4e3e-b3da-ec96651f5e91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832385025 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.832385025
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.968550637
Short name T531
Test name
Test status
Simulation time 15319248 ps
CPU time 0.79 seconds
Started Jan 03 12:45:37 PM PST 24
Finished Jan 03 12:47:40 PM PST 24
Peak memory 214528 kb
Host smart-7613efb1-c0ef-4045-ba92-7fb8ce5b0b65
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968550637 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.968550637
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.3747290262
Short name T109
Test name
Test status
Simulation time 93135854 ps
CPU time 0.91 seconds
Started Jan 03 12:46:01 PM PST 24
Finished Jan 03 12:47:49 PM PST 24
Peak memory 214588 kb
Host smart-4285087b-f17f-45bc-a892-fc9b502dcef3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747290262 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.3747290262
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.879492196
Short name T634
Test name
Test status
Simulation time 41614351 ps
CPU time 0.94 seconds
Started Jan 03 12:45:47 PM PST 24
Finished Jan 03 12:47:41 PM PST 24
Peak memory 215992 kb
Host smart-e5e8698b-c47c-4819-b330-35d72bb0d985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879492196 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.879492196
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.3530686675
Short name T395
Test name
Test status
Simulation time 76613545 ps
CPU time 1.05 seconds
Started Jan 03 12:45:51 PM PST 24
Finished Jan 03 12:47:23 PM PST 24
Peak memory 205664 kb
Host smart-7c5f2832-7e34-4d17-b23f-cfad33e90bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530686675 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.3530686675
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.313196432
Short name T99
Test name
Test status
Simulation time 23972779 ps
CPU time 1.08 seconds
Started Jan 03 12:45:44 PM PST 24
Finished Jan 03 12:47:16 PM PST 24
Peak memory 214596 kb
Host smart-f3f31c97-1033-494a-913a-6e9b4e361513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313196432 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.313196432
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.2629264106
Short name T382
Test name
Test status
Simulation time 15257721 ps
CPU time 0.87 seconds
Started Jan 03 12:45:58 PM PST 24
Finished Jan 03 12:47:23 PM PST 24
Peak memory 204892 kb
Host smart-47bc12e9-7036-483c-bc68-a2dfb82fae44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629264106 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.2629264106
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.1751041733
Short name T830
Test name
Test status
Simulation time 314868818 ps
CPU time 3.67 seconds
Started Jan 03 12:45:50 PM PST 24
Finished Jan 03 12:47:28 PM PST 24
Peak memory 206016 kb
Host smart-9bfac524-b536-4726-a2cf-0194d34848d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751041733 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.1751041733
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.3250002813
Short name T247
Test name
Test status
Simulation time 40467670841 ps
CPU time 783.83 seconds
Started Jan 03 12:46:01 PM PST 24
Finished Jan 03 01:00:30 PM PST 24
Peak memory 216228 kb
Host smart-6d543ae0-3557-42ae-a5f9-4c80f35ba419
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250002813 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.3250002813
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.1286226963
Short name T658
Test name
Test status
Simulation time 70904460 ps
CPU time 0.94 seconds
Started Jan 03 12:45:36 PM PST 24
Finished Jan 03 12:47:09 PM PST 24
Peak memory 205280 kb
Host smart-a4f4883f-3951-4436-acef-95e09a8edc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286226963 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.1286226963
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.865494152
Short name T779
Test name
Test status
Simulation time 48454569 ps
CPU time 0.83 seconds
Started Jan 03 12:45:53 PM PST 24
Finished Jan 03 12:47:18 PM PST 24
Peak memory 204752 kb
Host smart-f1851541-50cd-4d81-ba1a-5b7a4bfc8ac6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865494152 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.865494152
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.2463913704
Short name T450
Test name
Test status
Simulation time 16016467 ps
CPU time 0.96 seconds
Started Jan 03 12:45:23 PM PST 24
Finished Jan 03 12:47:06 PM PST 24
Peak memory 214444 kb
Host smart-ef83a6c6-80c5-4e0c-84d6-240436550308
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463913704 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.2463913704
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.2148255519
Short name T388
Test name
Test status
Simulation time 23595844 ps
CPU time 0.89 seconds
Started Jan 03 12:45:45 PM PST 24
Finished Jan 03 12:47:14 PM PST 24
Peak memory 214584 kb
Host smart-a027dd30-312d-4f5e-99c7-0e9d138a3628
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148255519 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.2148255519
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.3807781617
Short name T876
Test name
Test status
Simulation time 24830585 ps
CPU time 1.18 seconds
Started Jan 03 12:45:47 PM PST 24
Finished Jan 03 12:47:19 PM PST 24
Peak memory 215988 kb
Host smart-d27f7e66-0807-4ad5-a889-64d5e046bcfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807781617 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.3807781617
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.2716726279
Short name T439
Test name
Test status
Simulation time 25720526 ps
CPU time 0.93 seconds
Started Jan 03 12:45:42 PM PST 24
Finished Jan 03 12:47:28 PM PST 24
Peak memory 205284 kb
Host smart-5c471687-3431-433f-9ebe-1dbd38184168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716726279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.2716726279
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.3300363283
Short name T641
Test name
Test status
Simulation time 32299264 ps
CPU time 0.83 seconds
Started Jan 03 12:45:42 PM PST 24
Finished Jan 03 12:47:28 PM PST 24
Peak memory 214608 kb
Host smart-6f4f1506-ffa1-439a-a01c-845ca526fe19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300363283 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.3300363283
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.1941106712
Short name T401
Test name
Test status
Simulation time 36051854 ps
CPU time 0.84 seconds
Started Jan 03 12:45:40 PM PST 24
Finished Jan 03 12:47:13 PM PST 24
Peak memory 204912 kb
Host smart-c21a6e74-d6ef-4eb6-80c0-34da881b8c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941106712 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.1941106712
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.4131308755
Short name T78
Test name
Test status
Simulation time 431849092 ps
CPU time 1.43 seconds
Started Jan 03 12:46:02 PM PST 24
Finished Jan 03 12:47:35 PM PST 24
Peak memory 205248 kb
Host smart-28b4c02c-3a3f-4f22-af08-7b95977d5538
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131308755 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.4131308755
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.2861629899
Short name T103
Test name
Test status
Simulation time 110557217848 ps
CPU time 2226.01 seconds
Started Jan 03 12:45:53 PM PST 24
Finished Jan 03 01:24:23 PM PST 24
Peak memory 222092 kb
Host smart-858c1fe8-3336-4e9a-92cf-9e2d7d246fbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861629899 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.2861629899
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.102217596
Short name T188
Test name
Test status
Simulation time 115459113 ps
CPU time 0.91 seconds
Started Jan 03 12:46:10 PM PST 24
Finished Jan 03 12:47:40 PM PST 24
Peak memory 205484 kb
Host smart-b39c48e4-8a20-4fb2-8546-741d282343b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102217596 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.102217596
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.893074473
Short name T652
Test name
Test status
Simulation time 20664960 ps
CPU time 0.88 seconds
Started Jan 03 12:46:06 PM PST 24
Finished Jan 03 12:47:37 PM PST 24
Peak memory 205340 kb
Host smart-7944e7cb-aef2-474d-b87b-7e1979d23237
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893074473 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.893074473
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.3526607744
Short name T768
Test name
Test status
Simulation time 10911479 ps
CPU time 0.82 seconds
Started Jan 03 12:46:06 PM PST 24
Finished Jan 03 12:47:36 PM PST 24
Peak memory 214584 kb
Host smart-6662cde7-1f65-4da8-b2be-4248cfb8c5b0
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526607744 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.3526607744
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.1627965999
Short name T753
Test name
Test status
Simulation time 110755676 ps
CPU time 1.01 seconds
Started Jan 03 12:45:53 PM PST 24
Finished Jan 03 12:47:17 PM PST 24
Peak memory 214740 kb
Host smart-f1849c15-85f0-4b2b-bf7b-dabf03676d24
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627965999 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.1627965999
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.881297457
Short name T512
Test name
Test status
Simulation time 31559775 ps
CPU time 0.84 seconds
Started Jan 03 12:46:14 PM PST 24
Finished Jan 03 12:47:41 PM PST 24
Peak memory 215352 kb
Host smart-d4cf05ed-b481-4053-9acb-c8a49bee10d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881297457 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.881297457
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.801143121
Short name T705
Test name
Test status
Simulation time 8811893237 ps
CPU time 115.11 seconds
Started Jan 03 12:46:02 PM PST 24
Finished Jan 03 12:49:28 PM PST 24
Peak memory 214316 kb
Host smart-dbab4529-d04b-41da-b2d5-703b033bada3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801143121 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.801143121
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.3272212436
Short name T466
Test name
Test status
Simulation time 110247675 ps
CPU time 0.79 seconds
Started Jan 03 12:46:13 PM PST 24
Finished Jan 03 12:47:36 PM PST 24
Peak memory 214336 kb
Host smart-6cde4224-9ce7-493b-86c6-6a4d2f65a9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272212436 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.3272212436
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.4124679896
Short name T368
Test name
Test status
Simulation time 15559603 ps
CPU time 0.9 seconds
Started Jan 03 12:46:01 PM PST 24
Finished Jan 03 12:47:38 PM PST 24
Peak memory 204852 kb
Host smart-f7c755fe-c249-4de1-a696-3e4ca34839dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124679896 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.4124679896
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.2137139426
Short name T417
Test name
Test status
Simulation time 283277034 ps
CPU time 2.92 seconds
Started Jan 03 12:46:02 PM PST 24
Finished Jan 03 12:47:40 PM PST 24
Peak memory 205956 kb
Host smart-2e9b6a2e-0c93-45d5-b6ef-a04d00af12b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137139426 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.2137139426
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_alert.1696260208
Short name T189
Test name
Test status
Simulation time 20790916 ps
CPU time 0.99 seconds
Started Jan 03 12:46:04 PM PST 24
Finished Jan 03 12:47:38 PM PST 24
Peak memory 205260 kb
Host smart-aef968ee-cf45-491c-bbb4-910f2a23b256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696260208 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.1696260208
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.43534269
Short name T56
Test name
Test status
Simulation time 55129590 ps
CPU time 0.8 seconds
Started Jan 03 12:45:58 PM PST 24
Finished Jan 03 12:47:43 PM PST 24
Peak memory 204608 kb
Host smart-50a7120a-cfa2-4e63-89fb-c1df89c8220b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43534269 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.43534269
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.2066308398
Short name T791
Test name
Test status
Simulation time 10837010 ps
CPU time 0.82 seconds
Started Jan 03 12:45:55 PM PST 24
Finished Jan 03 12:47:44 PM PST 24
Peak memory 214356 kb
Host smart-140c5cf1-021a-4706-b72c-4e3cc03dcb1e
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066308398 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.2066308398
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.2936274267
Short name T620
Test name
Test status
Simulation time 106090760 ps
CPU time 0.94 seconds
Started Jan 03 12:46:27 PM PST 24
Finished Jan 03 12:47:45 PM PST 24
Peak memory 214476 kb
Host smart-fe58ca42-593d-423c-84bd-820ffa44f2bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936274267 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.2936274267
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.2380553559
Short name T759
Test name
Test status
Simulation time 19173023 ps
CPU time 1.15 seconds
Started Jan 03 12:45:54 PM PST 24
Finished Jan 03 12:47:47 PM PST 24
Peak memory 228324 kb
Host smart-d5d784e7-17a1-493f-bb06-445a676ed0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380553559 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.2380553559
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.2854511597
Short name T394
Test name
Test status
Simulation time 17263115 ps
CPU time 0.93 seconds
Started Jan 03 12:46:04 PM PST 24
Finished Jan 03 12:47:27 PM PST 24
Peak memory 204960 kb
Host smart-1e0bf42a-e428-4210-b031-107a290d18f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854511597 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.2854511597
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.1101843287
Short name T804
Test name
Test status
Simulation time 39935035 ps
CPU time 0.83 seconds
Started Jan 03 12:46:01 PM PST 24
Finished Jan 03 12:47:41 PM PST 24
Peak memory 214552 kb
Host smart-e88b85ab-265b-4d6a-9e75-a06d2c7a06a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101843287 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1101843287
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.3501995154
Short name T404
Test name
Test status
Simulation time 22009029 ps
CPU time 0.86 seconds
Started Jan 03 12:45:54 PM PST 24
Finished Jan 03 12:47:43 PM PST 24
Peak memory 204964 kb
Host smart-c261e213-793b-4c26-abe4-808f6b6007a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501995154 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.3501995154
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.3756215856
Short name T803
Test name
Test status
Simulation time 157457652 ps
CPU time 3.77 seconds
Started Jan 03 12:46:06 PM PST 24
Finished Jan 03 12:47:41 PM PST 24
Peak memory 206160 kb
Host smart-b057a3b5-1ae4-4d77-97e5-4c974c894ded
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756215856 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.3756215856
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.1645261499
Short name T713
Test name
Test status
Simulation time 214285085751 ps
CPU time 2375.55 seconds
Started Jan 03 12:46:06 PM PST 24
Finished Jan 03 01:27:11 PM PST 24
Peak memory 221856 kb
Host smart-de8d3398-ff51-4881-a592-127e032ff504
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645261499 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.1645261499
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.2417508113
Short name T660
Test name
Test status
Simulation time 52601174 ps
CPU time 0.94 seconds
Started Jan 03 12:46:07 PM PST 24
Finished Jan 03 12:47:30 PM PST 24
Peak memory 205212 kb
Host smart-adceee7d-130b-4612-a39b-ee3af76b6f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417508113 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2417508113
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.3236624916
Short name T701
Test name
Test status
Simulation time 21927114 ps
CPU time 0.99 seconds
Started Jan 03 12:45:52 PM PST 24
Finished Jan 03 12:47:18 PM PST 24
Peak memory 204788 kb
Host smart-eba19ef8-24ae-4ad1-acf1-bd43deb0aec1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236624916 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.3236624916
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.1268335072
Short name T121
Test name
Test status
Simulation time 13430776 ps
CPU time 0.87 seconds
Started Jan 03 12:45:55 PM PST 24
Finished Jan 03 12:47:21 PM PST 24
Peak memory 214616 kb
Host smart-cd80d044-d545-44b1-94b1-1c138f053d2e
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268335072 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.1268335072
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.3563570802
Short name T662
Test name
Test status
Simulation time 17424673 ps
CPU time 0.93 seconds
Started Jan 03 12:46:07 PM PST 24
Finished Jan 03 12:47:38 PM PST 24
Peak memory 214648 kb
Host smart-6c22c98d-7035-4371-9f8b-183321079e95
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563570802 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.3563570802
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.1926883995
Short name T789
Test name
Test status
Simulation time 30396822 ps
CPU time 0.94 seconds
Started Jan 03 12:46:43 PM PST 24
Finished Jan 03 12:47:54 PM PST 24
Peak memory 221584 kb
Host smart-7ba9f198-bc64-4d2d-8bab-011f8a63aba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926883995 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.1926883995
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.706204225
Short name T256
Test name
Test status
Simulation time 34942052 ps
CPU time 0.83 seconds
Started Jan 03 12:45:47 PM PST 24
Finished Jan 03 12:47:15 PM PST 24
Peak memory 205172 kb
Host smart-66be34b2-ef0c-48cc-9ac8-2ec33cf55a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706204225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.706204225
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.1981019047
Short name T553
Test name
Test status
Simulation time 23569606 ps
CPU time 0.9 seconds
Started Jan 03 12:46:02 PM PST 24
Finished Jan 03 12:47:33 PM PST 24
Peak memory 214332 kb
Host smart-c3b485d6-9657-4b4d-a095-a39561c2c334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981019047 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.1981019047
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.122400942
Short name T733
Test name
Test status
Simulation time 15067245 ps
CPU time 0.9 seconds
Started Jan 03 12:46:02 PM PST 24
Finished Jan 03 12:47:34 PM PST 24
Peak memory 204692 kb
Host smart-0dffd488-754a-4672-85a2-72ba53543e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122400942 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.122400942
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.2188106575
Short name T68
Test name
Test status
Simulation time 139894918 ps
CPU time 3.3 seconds
Started Jan 03 12:45:52 PM PST 24
Finished Jan 03 12:47:19 PM PST 24
Peak memory 206004 kb
Host smart-38c7eda9-18ae-466f-b95f-cc3d332f750a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188106575 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.2188106575
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.935339565
Short name T396
Test name
Test status
Simulation time 70878415608 ps
CPU time 1076.26 seconds
Started Jan 03 12:45:59 PM PST 24
Finished Jan 03 01:05:19 PM PST 24
Peak memory 217292 kb
Host smart-56a7c498-348d-4fcb-8cb1-7bdf167e5549
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935339565 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.935339565
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.2984848404
Short name T186
Test name
Test status
Simulation time 20468455 ps
CPU time 0.99 seconds
Started Jan 03 12:45:01 PM PST 24
Finished Jan 03 12:46:35 PM PST 24
Peak memory 206048 kb
Host smart-d30422d4-ebbb-4fbf-a12c-103e62292566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984848404 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.2984848404
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.3369896461
Short name T588
Test name
Test status
Simulation time 50000533 ps
CPU time 0.86 seconds
Started Jan 03 12:45:09 PM PST 24
Finished Jan 03 12:46:47 PM PST 24
Peak memory 204668 kb
Host smart-5141c1f3-2572-4f83-9b59-1696bbb3d508
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369896461 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.3369896461
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.991935357
Short name T386
Test name
Test status
Simulation time 40841714 ps
CPU time 0.82 seconds
Started Jan 03 12:44:52 PM PST 24
Finished Jan 03 12:46:18 PM PST 24
Peak memory 214524 kb
Host smart-25056781-7d8d-4897-880b-b821aff3b369
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991935357 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.991935357
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.2358181111
Short name T741
Test name
Test status
Simulation time 195509940 ps
CPU time 1.03 seconds
Started Jan 03 12:45:05 PM PST 24
Finished Jan 03 12:46:42 PM PST 24
Peak memory 214728 kb
Host smart-a2cfd3ab-8c4d-47f3-9284-05e24574e0d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358181111 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.2358181111
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_genbits.4077818252
Short name T203
Test name
Test status
Simulation time 19915529 ps
CPU time 1.11 seconds
Started Jan 03 12:45:23 PM PST 24
Finished Jan 03 12:47:08 PM PST 24
Peak memory 214340 kb
Host smart-091a1935-187f-43f6-938f-69d45c8dc8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077818252 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.4077818252
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.1566118500
Short name T773
Test name
Test status
Simulation time 24703942 ps
CPU time 0.9 seconds
Started Jan 03 12:45:11 PM PST 24
Finished Jan 03 12:46:48 PM PST 24
Peak memory 214688 kb
Host smart-131aa726-91ce-4341-9cc8-969c638f5dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566118500 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.1566118500
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_sec_cm.2337078628
Short name T30
Test name
Test status
Simulation time 253389873 ps
CPU time 4.26 seconds
Started Jan 03 12:45:02 PM PST 24
Finished Jan 03 12:46:42 PM PST 24
Peak memory 231616 kb
Host smart-54fafec5-c22f-4393-870e-c561be43f782
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337078628 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.2337078628
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.592599319
Short name T796
Test name
Test status
Simulation time 20652507 ps
CPU time 0.84 seconds
Started Jan 03 12:45:05 PM PST 24
Finished Jan 03 12:46:35 PM PST 24
Peak memory 205116 kb
Host smart-7983353a-fb5d-4dde-8a85-dc3e7c31c504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592599319 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.592599319
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.1095224461
Short name T58
Test name
Test status
Simulation time 76737393 ps
CPU time 2.15 seconds
Started Jan 03 12:45:19 PM PST 24
Finished Jan 03 12:46:55 PM PST 24
Peak memory 205748 kb
Host smart-aae11c22-df98-475d-926e-30835a37cd0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095224461 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1095224461
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.2126958686
Short name T383
Test name
Test status
Simulation time 14963991760 ps
CPU time 344.6 seconds
Started Jan 03 12:45:11 PM PST 24
Finished Jan 03 12:52:32 PM PST 24
Peak memory 215024 kb
Host smart-deca7b24-4496-4593-89cb-a59fdeccf8b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126958686 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.2126958686
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.1759548636
Short name T519
Test name
Test status
Simulation time 289236491 ps
CPU time 0.94 seconds
Started Jan 03 12:46:04 PM PST 24
Finished Jan 03 12:47:27 PM PST 24
Peak memory 205284 kb
Host smart-de187aac-9146-480e-b142-e7fbea0077e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759548636 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.1759548636
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.1097875752
Short name T757
Test name
Test status
Simulation time 19757549 ps
CPU time 0.95 seconds
Started Jan 03 12:46:01 PM PST 24
Finished Jan 03 12:47:41 PM PST 24
Peak memory 204660 kb
Host smart-5f1fbc52-6c90-41d2-9729-3c06b0a65fc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097875752 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.1097875752
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.3584703902
Short name T522
Test name
Test status
Simulation time 21051756 ps
CPU time 0.92 seconds
Started Jan 03 12:46:11 PM PST 24
Finished Jan 03 12:47:41 PM PST 24
Peak memory 214612 kb
Host smart-d2c72119-3ead-4c4e-a1bd-3a7682407f43
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584703902 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.3584703902
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.266354617
Short name T816
Test name
Test status
Simulation time 33770102 ps
CPU time 0.85 seconds
Started Jan 03 12:46:00 PM PST 24
Finished Jan 03 12:47:25 PM PST 24
Peak memory 215884 kb
Host smart-a7176d0d-6409-4af2-b717-47c24fb412f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266354617 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.266354617
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.4187085274
Short name T656
Test name
Test status
Simulation time 18942452 ps
CPU time 1.01 seconds
Started Jan 03 12:45:48 PM PST 24
Finished Jan 03 12:47:14 PM PST 24
Peak memory 205264 kb
Host smart-c1262d2e-4ae9-4e0d-b5b8-300c061d7a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187085274 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.4187085274
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.3487815267
Short name T769
Test name
Test status
Simulation time 26533162 ps
CPU time 0.9 seconds
Started Jan 03 12:45:58 PM PST 24
Finished Jan 03 12:47:32 PM PST 24
Peak memory 214532 kb
Host smart-3339a650-9c2b-4287-9e33-0c82197a13b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487815267 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.3487815267
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.2707186692
Short name T800
Test name
Test status
Simulation time 15377706 ps
CPU time 0.82 seconds
Started Jan 03 12:46:11 PM PST 24
Finished Jan 03 12:47:33 PM PST 24
Peak memory 205020 kb
Host smart-8f390434-8ef1-482b-833b-cfd641cfe8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707186692 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.2707186692
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.268153516
Short name T366
Test name
Test status
Simulation time 121244431 ps
CPU time 2.96 seconds
Started Jan 03 12:46:10 PM PST 24
Finished Jan 03 12:47:41 PM PST 24
Peak memory 206000 kb
Host smart-887c4240-14bf-4cb1-a4b4-ca05c73edeb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268153516 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.268153516
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.3119528939
Short name T909
Test name
Test status
Simulation time 146255694995 ps
CPU time 1024.04 seconds
Started Jan 03 12:46:08 PM PST 24
Finished Jan 03 01:04:35 PM PST 24
Peak memory 215784 kb
Host smart-c632ed46-831c-4541-859c-e14c2a393876
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119528939 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.3119528939
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.1313764770
Short name T896
Test name
Test status
Simulation time 20667938 ps
CPU time 0.99 seconds
Started Jan 03 12:46:11 PM PST 24
Finished Jan 03 12:47:34 PM PST 24
Peak memory 205072 kb
Host smart-7fe91caf-39be-4ddd-a942-cc29fb1b5f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313764770 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.1313764770
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.632732476
Short name T365
Test name
Test status
Simulation time 36059467 ps
CPU time 0.83 seconds
Started Jan 03 12:46:06 PM PST 24
Finished Jan 03 12:47:38 PM PST 24
Peak memory 205228 kb
Host smart-24ea3c32-99c7-4fb7-be24-2648ec057246
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632732476 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.632732476
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.3788021901
Short name T462
Test name
Test status
Simulation time 19611327 ps
CPU time 0.83 seconds
Started Jan 03 12:46:05 PM PST 24
Finished Jan 03 12:47:32 PM PST 24
Peak memory 214496 kb
Host smart-439a1007-d830-4259-ba55-c92949551b83
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788021901 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.3788021901
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.1649048298
Short name T821
Test name
Test status
Simulation time 92364937 ps
CPU time 0.98 seconds
Started Jan 03 12:46:11 PM PST 24
Finished Jan 03 12:47:33 PM PST 24
Peak memory 214608 kb
Host smart-4b8885b9-a219-4444-a354-22fb1bc074b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649048298 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.1649048298
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.2979384734
Short name T532
Test name
Test status
Simulation time 19047648 ps
CPU time 1 seconds
Started Jan 03 12:45:52 PM PST 24
Finished Jan 03 12:47:17 PM PST 24
Peak memory 215792 kb
Host smart-30a11467-0392-40b5-9de8-218460a1e327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979384734 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2979384734
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.218858160
Short name T201
Test name
Test status
Simulation time 25051193 ps
CPU time 0.89 seconds
Started Jan 03 12:46:00 PM PST 24
Finished Jan 03 12:47:24 PM PST 24
Peak memory 205136 kb
Host smart-55062876-ebbf-4546-810c-28d18096c3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218858160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.218858160
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.4261022434
Short name T878
Test name
Test status
Simulation time 20138288 ps
CPU time 0.99 seconds
Started Jan 03 12:45:48 PM PST 24
Finished Jan 03 12:47:44 PM PST 24
Peak memory 214656 kb
Host smart-1026f737-af43-4de9-8a41-b65f50c0a355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261022434 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.4261022434
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.3946539483
Short name T736
Test name
Test status
Simulation time 115921702 ps
CPU time 0.82 seconds
Started Jan 03 12:45:53 PM PST 24
Finished Jan 03 12:47:17 PM PST 24
Peak memory 204636 kb
Host smart-e6717bca-b8f8-46f4-84b7-42752ef2e2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946539483 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.3946539483
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.3917594734
Short name T55
Test name
Test status
Simulation time 379120464 ps
CPU time 3.99 seconds
Started Jan 03 12:46:08 PM PST 24
Finished Jan 03 12:47:35 PM PST 24
Peak memory 205920 kb
Host smart-93a68be4-1837-47b6-b3a6-0accaec273bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917594734 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.3917594734
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.1185186229
Short name T738
Test name
Test status
Simulation time 123972551327 ps
CPU time 829.56 seconds
Started Jan 03 12:46:14 PM PST 24
Finished Jan 03 01:01:31 PM PST 24
Peak memory 215140 kb
Host smart-0ee24114-86f4-4336-9cbf-e164c79f4c53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185186229 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.1185186229
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.3443354307
Short name T807
Test name
Test status
Simulation time 17801609 ps
CPU time 0.97 seconds
Started Jan 03 12:46:03 PM PST 24
Finished Jan 03 12:47:29 PM PST 24
Peak memory 205444 kb
Host smart-5e8bfd70-80c5-456b-af17-a070f1f63662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443354307 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.3443354307
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.3055490677
Short name T367
Test name
Test status
Simulation time 14487204 ps
CPU time 0.87 seconds
Started Jan 03 12:46:03 PM PST 24
Finished Jan 03 12:47:27 PM PST 24
Peak memory 204560 kb
Host smart-0f91d3f9-4acf-40dc-95fb-91294f032e62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055490677 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.3055490677
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.1998342563
Short name T126
Test name
Test status
Simulation time 31730938 ps
CPU time 0.81 seconds
Started Jan 03 12:45:47 PM PST 24
Finished Jan 03 12:47:19 PM PST 24
Peak memory 214500 kb
Host smart-f102ed34-79f7-4f29-b897-bf0fed73731d
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998342563 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.1998342563
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_err.3922096698
Short name T496
Test name
Test status
Simulation time 67744466 ps
CPU time 1.01 seconds
Started Jan 03 12:45:49 PM PST 24
Finished Jan 03 12:47:28 PM PST 24
Peak memory 217196 kb
Host smart-c023f222-5dcf-4d92-9ca8-1581e8f92ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922096698 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.3922096698
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.1147317184
Short name T62
Test name
Test status
Simulation time 14956743 ps
CPU time 0.93 seconds
Started Jan 03 12:46:08 PM PST 24
Finished Jan 03 12:47:30 PM PST 24
Peak memory 205296 kb
Host smart-01bf473b-df17-4a5e-a54e-40c30b802c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147317184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.1147317184
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.3262493736
Short name T877
Test name
Test status
Simulation time 23607381 ps
CPU time 0.98 seconds
Started Jan 03 12:45:53 PM PST 24
Finished Jan 03 12:47:32 PM PST 24
Peak memory 222004 kb
Host smart-b63fe9db-875e-4221-82f9-6e9a40079be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262493736 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.3262493736
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.1456590924
Short name T525
Test name
Test status
Simulation time 13568176 ps
CPU time 0.85 seconds
Started Jan 03 12:46:00 PM PST 24
Finished Jan 03 12:47:23 PM PST 24
Peak memory 204808 kb
Host smart-8da9dcb0-1343-434c-8fb3-777eabaa6342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456590924 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.1456590924
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.1742589241
Short name T893
Test name
Test status
Simulation time 364724268 ps
CPU time 2.85 seconds
Started Jan 03 12:45:57 PM PST 24
Finished Jan 03 12:47:41 PM PST 24
Peak memory 206100 kb
Host smart-0dbff5a4-28ce-4b93-beb0-bc84e1721ac7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742589241 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.1742589241
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.1742914339
Short name T712
Test name
Test status
Simulation time 221108057232 ps
CPU time 998.11 seconds
Started Jan 03 12:45:45 PM PST 24
Finished Jan 03 01:04:21 PM PST 24
Peak memory 216636 kb
Host smart-19d4721e-e2ca-462e-a17c-2363c76b68a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742914339 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.1742914339
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.3252042383
Short name T226
Test name
Test status
Simulation time 18333172 ps
CPU time 0.96 seconds
Started Jan 03 12:45:55 PM PST 24
Finished Jan 03 12:47:21 PM PST 24
Peak memory 205920 kb
Host smart-ae1ea994-ebd4-438d-b624-b0ed1c79fc16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252042383 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.3252042383
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.4033411951
Short name T527
Test name
Test status
Simulation time 14286649 ps
CPU time 0.85 seconds
Started Jan 03 12:46:02 PM PST 24
Finished Jan 03 12:47:38 PM PST 24
Peak memory 204768 kb
Host smart-32d95146-f8fb-4c7c-8eed-bf9f12055505
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033411951 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.4033411951
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.3110612111
Short name T37
Test name
Test status
Simulation time 32961838 ps
CPU time 0.84 seconds
Started Jan 03 12:46:28 PM PST 24
Finished Jan 03 12:47:45 PM PST 24
Peak memory 214368 kb
Host smart-bcf3bb56-c41d-44f0-87ce-d88d25a8a927
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110612111 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.3110612111
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.1600095053
Short name T871
Test name
Test status
Simulation time 14153095 ps
CPU time 0.88 seconds
Started Jan 03 12:46:05 PM PST 24
Finished Jan 03 12:47:30 PM PST 24
Peak memory 214708 kb
Host smart-b73b1730-66ed-4a09-a772-8424c1a9e183
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600095053 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.1600095053
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.434806690
Short name T601
Test name
Test status
Simulation time 33496735 ps
CPU time 0.96 seconds
Started Jan 03 12:46:31 PM PST 24
Finished Jan 03 12:47:50 PM PST 24
Peak memory 215040 kb
Host smart-6f67d487-ce35-4188-8097-2e73365ebda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434806690 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.434806690
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.1328460785
Short name T507
Test name
Test status
Simulation time 61572846 ps
CPU time 0.94 seconds
Started Jan 03 12:45:58 PM PST 24
Finished Jan 03 12:47:31 PM PST 24
Peak memory 205196 kb
Host smart-6d2a3f35-8dc9-473a-8ae5-88af2b98f9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328460785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.1328460785
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.1814681742
Short name T671
Test name
Test status
Simulation time 37745068 ps
CPU time 0.87 seconds
Started Jan 03 12:45:58 PM PST 24
Finished Jan 03 12:47:30 PM PST 24
Peak memory 214148 kb
Host smart-3a6fcb30-5d6e-4e59-910e-32205a61d98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814681742 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.1814681742
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.1568081649
Short name T798
Test name
Test status
Simulation time 17339796 ps
CPU time 0.97 seconds
Started Jan 03 12:46:01 PM PST 24
Finished Jan 03 12:47:27 PM PST 24
Peak memory 205104 kb
Host smart-cf740820-445e-414a-a3e3-c3138cf6723f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568081649 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.1568081649
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.4134157594
Short name T672
Test name
Test status
Simulation time 539134958 ps
CPU time 2.14 seconds
Started Jan 03 12:46:01 PM PST 24
Finished Jan 03 12:47:29 PM PST 24
Peak memory 205180 kb
Host smart-3510e36f-ab23-4bb3-b3cf-d917f473c400
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134157594 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.4134157594
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.1026576314
Short name T703
Test name
Test status
Simulation time 97655350188 ps
CPU time 2137.68 seconds
Started Jan 03 12:46:34 PM PST 24
Finished Jan 03 01:23:24 PM PST 24
Peak memory 221812 kb
Host smart-8a08b980-97eb-49a5-8786-c1ad9cb1c1f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026576314 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.1026576314
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.162696498
Short name T846
Test name
Test status
Simulation time 39353292 ps
CPU time 0.96 seconds
Started Jan 03 12:46:01 PM PST 24
Finished Jan 03 12:47:27 PM PST 24
Peak memory 206104 kb
Host smart-55aa0b61-6f6a-4533-aa54-45bc51629dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162696498 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.162696498
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.262107503
Short name T892
Test name
Test status
Simulation time 16117014 ps
CPU time 0.84 seconds
Started Jan 03 12:45:46 PM PST 24
Finished Jan 03 12:47:15 PM PST 24
Peak memory 205076 kb
Host smart-2f9291ae-8e97-47a5-9fc6-42c9ad65379a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262107503 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.262107503
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.3871172200
Short name T403
Test name
Test status
Simulation time 12901224 ps
CPU time 0.83 seconds
Started Jan 03 12:45:46 PM PST 24
Finished Jan 03 12:47:12 PM PST 24
Peak memory 214556 kb
Host smart-7d214655-0eb4-4c39-8674-5229cc89d4fb
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871172200 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.3871172200
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.4284955722
Short name T269
Test name
Test status
Simulation time 27988575 ps
CPU time 1.03 seconds
Started Jan 03 12:46:01 PM PST 24
Finished Jan 03 12:47:27 PM PST 24
Peak memory 214580 kb
Host smart-93ee568f-08c1-4a8a-a0d0-4d8a6f761a01
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284955722 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.4284955722
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.794620751
Short name T622
Test name
Test status
Simulation time 35937687 ps
CPU time 1.44 seconds
Started Jan 03 12:45:57 PM PST 24
Finished Jan 03 12:47:26 PM PST 24
Peak memory 227620 kb
Host smart-af7872eb-1a6b-4fe3-a235-5c60ce48be2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794620751 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.794620751
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.1354767137
Short name T573
Test name
Test status
Simulation time 22386010 ps
CPU time 0.9 seconds
Started Jan 03 12:46:01 PM PST 24
Finished Jan 03 12:47:41 PM PST 24
Peak memory 205564 kb
Host smart-c5c11d89-24c9-4201-8a8c-b32991e6bdd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354767137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.1354767137
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.3262829567
Short name T724
Test name
Test status
Simulation time 25449648 ps
CPU time 0.87 seconds
Started Jan 03 12:46:03 PM PST 24
Finished Jan 03 12:47:41 PM PST 24
Peak memory 214436 kb
Host smart-9c1bc5eb-1922-4079-b8d8-28119fe77a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262829567 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.3262829567
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.1434428859
Short name T501
Test name
Test status
Simulation time 14339103 ps
CPU time 0.9 seconds
Started Jan 03 12:46:01 PM PST 24
Finished Jan 03 12:47:28 PM PST 24
Peak memory 204860 kb
Host smart-7b6aae67-8bbc-40d1-9fb3-1a36d740659a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434428859 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.1434428859
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.3216018724
Short name T369
Test name
Test status
Simulation time 68574877 ps
CPU time 1.76 seconds
Started Jan 03 12:46:11 PM PST 24
Finished Jan 03 12:47:35 PM PST 24
Peak memory 205700 kb
Host smart-269df3e7-ee5b-4937-b931-0cec37b897ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216018724 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.3216018724
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.1703994788
Short name T633
Test name
Test status
Simulation time 120071033220 ps
CPU time 1208.73 seconds
Started Jan 03 12:45:56 PM PST 24
Finished Jan 03 01:07:33 PM PST 24
Peak memory 216440 kb
Host smart-91d160ec-7011-4151-af80-a5e044172666
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703994788 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.1703994788
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert_test.737196958
Short name T764
Test name
Test status
Simulation time 75529755 ps
CPU time 0.9 seconds
Started Jan 03 12:46:07 PM PST 24
Finished Jan 03 12:47:38 PM PST 24
Peak memory 204764 kb
Host smart-92a833d1-95dc-4412-9a2a-087c0dad4716
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737196958 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.737196958
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.4022960278
Short name T563
Test name
Test status
Simulation time 87575089 ps
CPU time 0.81 seconds
Started Jan 03 12:46:33 PM PST 24
Finished Jan 03 12:47:54 PM PST 24
Peak memory 214492 kb
Host smart-d0d19b4e-1138-4abc-92f8-d8b50241b213
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022960278 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.4022960278
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.3136582598
Short name T900
Test name
Test status
Simulation time 84891460 ps
CPU time 1.1 seconds
Started Jan 03 12:46:02 PM PST 24
Finished Jan 03 12:47:33 PM PST 24
Peak memory 214672 kb
Host smart-0c400aaa-b47a-4b85-923b-9986e6be3d2d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136582598 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.3136582598
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.2787378856
Short name T867
Test name
Test status
Simulation time 26699987 ps
CPU time 0.95 seconds
Started Jan 03 12:46:32 PM PST 24
Finished Jan 03 12:47:48 PM PST 24
Peak memory 214504 kb
Host smart-0e9ac6e9-98fb-4907-8e5b-78e0eea6b2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787378856 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.2787378856
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.1044948765
Short name T597
Test name
Test status
Simulation time 87387360 ps
CPU time 2.2 seconds
Started Jan 03 12:46:02 PM PST 24
Finished Jan 03 12:47:39 PM PST 24
Peak memory 214288 kb
Host smart-61782f4d-f7e4-4f27-83c7-5e738f5026a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044948765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.1044948765
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.1298912841
Short name T427
Test name
Test status
Simulation time 19259841 ps
CPU time 0.99 seconds
Started Jan 03 12:45:50 PM PST 24
Finished Jan 03 12:47:18 PM PST 24
Peak memory 214284 kb
Host smart-fb95d3f6-af1a-437d-8f05-4fddb58cbcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298912841 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.1298912841
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.401384984
Short name T406
Test name
Test status
Simulation time 11933514 ps
CPU time 0.86 seconds
Started Jan 03 12:46:10 PM PST 24
Finished Jan 03 12:47:39 PM PST 24
Peak memory 204864 kb
Host smart-aedbab5d-ec30-4aa8-bc39-066406ef33dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401384984 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.401384984
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.3091233203
Short name T823
Test name
Test status
Simulation time 683404440 ps
CPU time 3.92 seconds
Started Jan 03 12:45:50 PM PST 24
Finished Jan 03 12:47:22 PM PST 24
Peak memory 206032 kb
Host smart-490f337e-861f-4426-8f45-07a80be3700d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091233203 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.3091233203
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.3385288342
Short name T648
Test name
Test status
Simulation time 63133897371 ps
CPU time 1534.75 seconds
Started Jan 03 12:45:58 PM PST 24
Finished Jan 03 01:13:04 PM PST 24
Peak memory 219408 kb
Host smart-e6e6294f-2c26-4328-b330-621a8608f72e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385288342 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.3385288342
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.92932963
Short name T16
Test name
Test status
Simulation time 18522289 ps
CPU time 1.02 seconds
Started Jan 03 12:46:14 PM PST 24
Finished Jan 03 12:47:42 PM PST 24
Peak memory 206096 kb
Host smart-3562fbab-544c-4a72-a9dd-69ca9516b28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92932963 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.92932963
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.3342690733
Short name T558
Test name
Test status
Simulation time 14763416 ps
CPU time 0.82 seconds
Started Jan 03 12:45:50 PM PST 24
Finished Jan 03 12:47:19 PM PST 24
Peak memory 204696 kb
Host smart-97dcc11b-0951-4d61-afea-1c4be90fa872
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342690733 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.3342690733
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.3526513608
Short name T632
Test name
Test status
Simulation time 31118428 ps
CPU time 0.83 seconds
Started Jan 03 12:45:56 PM PST 24
Finished Jan 03 12:47:19 PM PST 24
Peak memory 214536 kb
Host smart-358a6f5b-1e9a-4c86-8d69-35ed847012ba
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526513608 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.3526513608
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.626851466
Short name T480
Test name
Test status
Simulation time 19648939 ps
CPU time 0.91 seconds
Started Jan 03 12:46:01 PM PST 24
Finished Jan 03 12:47:28 PM PST 24
Peak memory 214464 kb
Host smart-00551acb-1ad2-4434-8df1-6b39b6797cf1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626851466 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_di
sable_auto_req_mode.626851466
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.2370627113
Short name T53
Test name
Test status
Simulation time 135020335 ps
CPU time 1.05 seconds
Started Jan 03 12:46:04 PM PST 24
Finished Jan 03 12:47:27 PM PST 24
Peak memory 221944 kb
Host smart-b582cb78-8b7d-4b52-89dc-56dc7ae619f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370627113 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.2370627113
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.4112398625
Short name T426
Test name
Test status
Simulation time 16973677 ps
CPU time 1.01 seconds
Started Jan 03 12:46:11 PM PST 24
Finished Jan 03 12:47:33 PM PST 24
Peak memory 205308 kb
Host smart-7d691a79-05a9-4ded-9b33-cbc80c6a1aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112398625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.4112398625
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.894232780
Short name T92
Test name
Test status
Simulation time 23556968 ps
CPU time 0.82 seconds
Started Jan 03 12:46:32 PM PST 24
Finished Jan 03 12:47:49 PM PST 24
Peak memory 214684 kb
Host smart-d094f12b-c65d-44a0-9332-47ebb16f6ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894232780 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.894232780
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.804554447
Short name T390
Test name
Test status
Simulation time 27530545 ps
CPU time 0.88 seconds
Started Jan 03 12:45:48 PM PST 24
Finished Jan 03 12:47:14 PM PST 24
Peak memory 204948 kb
Host smart-5e54a186-7e9f-4f8c-a1fa-0192f8a6c1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804554447 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.804554447
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.1636448160
Short name T820
Test name
Test status
Simulation time 106802725 ps
CPU time 2.33 seconds
Started Jan 03 12:45:53 PM PST 24
Finished Jan 03 12:47:19 PM PST 24
Peak memory 206140 kb
Host smart-196a9340-3080-4e0d-97e2-46f8a5487544
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636448160 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.1636448160
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_alert.2130211639
Short name T223
Test name
Test status
Simulation time 31449781 ps
CPU time 0.89 seconds
Started Jan 03 12:46:24 PM PST 24
Finished Jan 03 12:47:42 PM PST 24
Peak memory 205300 kb
Host smart-39cc5f7f-bd25-4170-96bf-68e1b13cef70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130211639 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2130211639
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.155972067
Short name T468
Test name
Test status
Simulation time 17963881 ps
CPU time 0.9 seconds
Started Jan 03 12:46:23 PM PST 24
Finished Jan 03 12:47:47 PM PST 24
Peak memory 205120 kb
Host smart-b01bc590-e00b-46d1-bb11-b47e7ce90bd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155972067 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.155972067
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.1322077875
Short name T651
Test name
Test status
Simulation time 22971008 ps
CPU time 0.91 seconds
Started Jan 03 12:46:20 PM PST 24
Finished Jan 03 12:47:40 PM PST 24
Peak memory 214544 kb
Host smart-a77a4cc4-6ff3-403e-a225-c277b07c0684
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322077875 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.1322077875
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.1949876172
Short name T112
Test name
Test status
Simulation time 18670455 ps
CPU time 0.97 seconds
Started Jan 03 12:46:24 PM PST 24
Finished Jan 03 12:47:42 PM PST 24
Peak memory 214644 kb
Host smart-013b6a09-ecde-4a3f-a514-f47e04224568
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949876172 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.1949876172
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.2385615685
Short name T886
Test name
Test status
Simulation time 20252709 ps
CPU time 1.03 seconds
Started Jan 03 12:46:27 PM PST 24
Finished Jan 03 12:47:43 PM PST 24
Peak memory 214572 kb
Host smart-602a9970-4ef2-4532-aa0d-ec96ac40c9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385615685 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.2385615685
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.1322393137
Short name T76
Test name
Test status
Simulation time 16067043 ps
CPU time 0.9 seconds
Started Jan 03 12:46:02 PM PST 24
Finished Jan 03 12:47:38 PM PST 24
Peak memory 205228 kb
Host smart-38468385-a000-40c4-b13e-b0ab0eee14dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322393137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.1322393137
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.3527461851
Short name T102
Test name
Test status
Simulation time 28619991 ps
CPU time 0.82 seconds
Started Jan 03 12:46:27 PM PST 24
Finished Jan 03 12:47:44 PM PST 24
Peak memory 214572 kb
Host smart-9d0e0698-b412-4ebe-9ffa-e3f54647178d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527461851 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.3527461851
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.505365811
Short name T381
Test name
Test status
Simulation time 47539064 ps
CPU time 0.85 seconds
Started Jan 03 12:45:58 PM PST 24
Finished Jan 03 12:47:30 PM PST 24
Peak memory 204980 kb
Host smart-eec0e893-7a2d-45c3-af54-927816ae871f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505365811 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.505365811
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.1486136322
Short name T865
Test name
Test status
Simulation time 122296118 ps
CPU time 1.65 seconds
Started Jan 03 12:46:32 PM PST 24
Finished Jan 03 12:47:48 PM PST 24
Peak memory 205332 kb
Host smart-6a94ecc8-0a31-4641-b1cf-bbee5ee75cae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486136322 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.1486136322
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.4176951009
Short name T828
Test name
Test status
Simulation time 81404534022 ps
CPU time 853.58 seconds
Started Jan 03 12:46:22 PM PST 24
Finished Jan 03 01:02:02 PM PST 24
Peak memory 215308 kb
Host smart-6bf749bf-dc33-4bbf-9467-05517bf93a96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176951009 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.4176951009
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.3052126911
Short name T539
Test name
Test status
Simulation time 62490400 ps
CPU time 1.01 seconds
Started Jan 03 12:46:28 PM PST 24
Finished Jan 03 12:47:45 PM PST 24
Peak memory 205448 kb
Host smart-b89ac417-6ac8-4bf5-94b8-467b2ba59fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052126911 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.3052126911
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.133267883
Short name T64
Test name
Test status
Simulation time 30420986 ps
CPU time 0.88 seconds
Started Jan 03 12:47:00 PM PST 24
Finished Jan 03 12:48:02 PM PST 24
Peak memory 204612 kb
Host smart-2b9ddc8c-213f-49a4-9f97-2295c6078024
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133267883 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.133267883
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.1934858224
Short name T127
Test name
Test status
Simulation time 13600582 ps
CPU time 0.88 seconds
Started Jan 03 12:46:23 PM PST 24
Finished Jan 03 12:47:42 PM PST 24
Peak memory 214452 kb
Host smart-6823eef0-2d15-4ee3-ae78-ff6aed0e271a
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934858224 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.1934858224
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.2241415255
Short name T732
Test name
Test status
Simulation time 25952311 ps
CPU time 0.97 seconds
Started Jan 03 12:46:29 PM PST 24
Finished Jan 03 12:47:53 PM PST 24
Peak memory 214536 kb
Host smart-585ccc76-17f1-4d32-ac8d-7db8596f2306
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241415255 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.2241415255
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.3298312370
Short name T630
Test name
Test status
Simulation time 37064750 ps
CPU time 1.05 seconds
Started Jan 03 12:46:55 PM PST 24
Finished Jan 03 12:48:01 PM PST 24
Peak memory 217148 kb
Host smart-4a8236b7-40d4-4f38-9d24-4de9b1126d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298312370 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.3298312370
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.3756527718
Short name T543
Test name
Test status
Simulation time 29755723 ps
CPU time 1.15 seconds
Started Jan 03 12:46:50 PM PST 24
Finished Jan 03 12:48:00 PM PST 24
Peak memory 205952 kb
Host smart-1b078972-6ce4-43f7-bdc7-b35f03ccfc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756527718 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.3756527718
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.1161543131
Short name T763
Test name
Test status
Simulation time 20921202 ps
CPU time 0.99 seconds
Started Jan 03 12:46:27 PM PST 24
Finished Jan 03 12:47:45 PM PST 24
Peak memory 214396 kb
Host smart-78d9d624-86cc-42d9-8843-be8f6f95e1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161543131 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.1161543131
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.34895011
Short name T778
Test name
Test status
Simulation time 13579650 ps
CPU time 0.93 seconds
Started Jan 03 12:46:42 PM PST 24
Finished Jan 03 12:47:53 PM PST 24
Peak memory 205092 kb
Host smart-d49fadde-fd33-4a74-ab04-d896a175ddd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34895011 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.34895011
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.1987552252
Short name T629
Test name
Test status
Simulation time 371927711 ps
CPU time 2.39 seconds
Started Jan 03 12:46:29 PM PST 24
Finished Jan 03 12:47:48 PM PST 24
Peak memory 205896 kb
Host smart-26a2b335-0d9f-496d-a0ab-92dc668ddf56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987552252 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.1987552252
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.4048271359
Short name T715
Test name
Test status
Simulation time 22580145260 ps
CPU time 507.9 seconds
Started Jan 03 12:46:51 PM PST 24
Finished Jan 03 12:56:27 PM PST 24
Peak memory 214632 kb
Host smart-67a19c69-3f2d-4dcc-b1fb-e2ff23b393ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048271359 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.4048271359
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.1908525114
Short name T217
Test name
Test status
Simulation time 34219425 ps
CPU time 1.01 seconds
Started Jan 03 12:46:51 PM PST 24
Finished Jan 03 12:48:00 PM PST 24
Peak memory 205280 kb
Host smart-6df1e978-56ff-42bd-ac00-f06994883b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908525114 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.1908525114
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.4115512248
Short name T836
Test name
Test status
Simulation time 17882493 ps
CPU time 0.9 seconds
Started Jan 03 12:46:58 PM PST 24
Finished Jan 03 12:48:01 PM PST 24
Peak memory 204588 kb
Host smart-4db3b015-2cfe-4bf8-bc73-06d7ec7575de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115512248 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.4115512248
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.613945116
Short name T3
Test name
Test status
Simulation time 20124968 ps
CPU time 0.84 seconds
Started Jan 03 12:47:02 PM PST 24
Finished Jan 03 12:48:03 PM PST 24
Peak memory 214516 kb
Host smart-a7655404-d594-4923-97e5-9b9d2ad9a86c
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613945116 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.613945116
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.2009978248
Short name T569
Test name
Test status
Simulation time 56731880 ps
CPU time 0.93 seconds
Started Jan 03 12:46:50 PM PST 24
Finished Jan 03 12:47:58 PM PST 24
Peak memory 214576 kb
Host smart-e7108463-1238-44df-8769-9c19a737bacb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009978248 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.2009978248
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.960637162
Short name T839
Test name
Test status
Simulation time 29440487 ps
CPU time 1.14 seconds
Started Jan 03 12:47:02 PM PST 24
Finished Jan 03 12:48:04 PM PST 24
Peak memory 217104 kb
Host smart-2089a12d-f22b-4595-9cd9-1f9a80228aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960637162 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.960637162
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.3475104888
Short name T872
Test name
Test status
Simulation time 20932632 ps
CPU time 1.03 seconds
Started Jan 03 12:46:56 PM PST 24
Finished Jan 03 12:48:01 PM PST 24
Peak memory 205456 kb
Host smart-51c93f35-c1c3-47ac-a3cb-6263532105b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475104888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3475104888
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.2483948181
Short name T93
Test name
Test status
Simulation time 18230819 ps
CPU time 1.08 seconds
Started Jan 03 12:46:27 PM PST 24
Finished Jan 03 12:47:44 PM PST 24
Peak memory 214668 kb
Host smart-f0856708-cf81-42f8-b448-1616c0f306f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483948181 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.2483948181
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.1738076401
Short name T463
Test name
Test status
Simulation time 14492336 ps
CPU time 0.88 seconds
Started Jan 03 12:46:28 PM PST 24
Finished Jan 03 12:47:48 PM PST 24
Peak memory 204948 kb
Host smart-0b930505-9480-4aaf-864b-b731d7531b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738076401 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.1738076401
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.2962412640
Short name T494
Test name
Test status
Simulation time 526631410 ps
CPU time 3.19 seconds
Started Jan 03 12:46:19 PM PST 24
Finished Jan 03 12:47:41 PM PST 24
Peak memory 214216 kb
Host smart-3e325350-460e-45b7-8b5f-05c73f26a9e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962412640 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2962412640
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_alert.3223327403
Short name T185
Test name
Test status
Simulation time 79293108 ps
CPU time 0.91 seconds
Started Jan 03 12:44:55 PM PST 24
Finished Jan 03 12:46:27 PM PST 24
Peak memory 205220 kb
Host smart-d95addce-ab99-40fc-bd0f-bf2e2004a734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223327403 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.3223327403
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.1766821826
Short name T646
Test name
Test status
Simulation time 19893800 ps
CPU time 0.89 seconds
Started Jan 03 12:45:07 PM PST 24
Finished Jan 03 12:46:36 PM PST 24
Peak memory 204728 kb
Host smart-d3ccb10b-ab63-41dd-8a3e-81b41549a5ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766821826 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.1766821826
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.2866542676
Short name T87
Test name
Test status
Simulation time 34937958 ps
CPU time 0.8 seconds
Started Jan 03 12:45:09 PM PST 24
Finished Jan 03 12:46:44 PM PST 24
Peak memory 214500 kb
Host smart-907bb28e-ca51-4bac-8172-64e13e3ee28a
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866542676 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.2866542676
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.44150734
Short name T412
Test name
Test status
Simulation time 36820739 ps
CPU time 0.98 seconds
Started Jan 03 12:45:10 PM PST 24
Finished Jan 03 12:46:40 PM PST 24
Peak memory 215972 kb
Host smart-f645e77c-8022-4e73-9a08-467e69045583
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44150734 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disa
ble_auto_req_mode.44150734
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.3494445948
Short name T393
Test name
Test status
Simulation time 29480540 ps
CPU time 1.14 seconds
Started Jan 03 12:45:03 PM PST 24
Finished Jan 03 12:46:37 PM PST 24
Peak memory 217208 kb
Host smart-1ad37840-6d34-428e-b4e4-3cfd36dd65b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494445948 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.3494445948
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.731997112
Short name T544
Test name
Test status
Simulation time 73978585 ps
CPU time 1.12 seconds
Started Jan 03 12:45:16 PM PST 24
Finished Jan 03 12:46:49 PM PST 24
Peak memory 205480 kb
Host smart-174623bd-c43d-4c0d-86e3-52d0f593f7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731997112 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.731997112
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.2553182461
Short name T91
Test name
Test status
Simulation time 79687661 ps
CPU time 0.81 seconds
Started Jan 03 12:45:32 PM PST 24
Finished Jan 03 12:47:01 PM PST 24
Peak memory 214512 kb
Host smart-65a7513d-7592-4fde-9c47-25e66ddefd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553182461 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.2553182461
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.1832483232
Short name T192
Test name
Test status
Simulation time 20257877 ps
CPU time 0.83 seconds
Started Jan 03 12:45:04 PM PST 24
Finished Jan 03 12:46:41 PM PST 24
Peak memory 204904 kb
Host smart-af9a3d02-290d-4492-9310-f164e446283d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832483232 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.1832483232
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_stress_all.580930044
Short name T455
Test name
Test status
Simulation time 620266403 ps
CPU time 2.99 seconds
Started Jan 03 12:45:40 PM PST 24
Finished Jan 03 12:47:20 PM PST 24
Peak memory 206080 kb
Host smart-11ca4885-5b88-4349-8caf-8b9495ea1dc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580930044 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.580930044
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.993435652
Short name T702
Test name
Test status
Simulation time 80308479528 ps
CPU time 1912.73 seconds
Started Jan 03 12:45:00 PM PST 24
Finished Jan 03 01:18:27 PM PST 24
Peak memory 222276 kb
Host smart-4d8424eb-6119-416a-a448-978cb2be3f1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993435652 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.993435652
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.3379702848
Short name T4
Test name
Test status
Simulation time 18949587 ps
CPU time 1.09 seconds
Started Jan 03 12:46:34 PM PST 24
Finished Jan 03 12:47:48 PM PST 24
Peak memory 215528 kb
Host smart-b5939144-28e1-495f-ab0f-5b724274f93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379702848 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.3379702848
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.1371524373
Short name T894
Test name
Test status
Simulation time 16481811 ps
CPU time 0.94 seconds
Started Jan 03 12:46:55 PM PST 24
Finished Jan 03 12:48:01 PM PST 24
Peak memory 205400 kb
Host smart-514bc6f8-674f-4bdd-800c-19ed00c97980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371524373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.1371524373
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.3106929837
Short name T731
Test name
Test status
Simulation time 21827778 ps
CPU time 1.17 seconds
Started Jan 03 12:46:52 PM PST 24
Finished Jan 03 12:48:00 PM PST 24
Peak memory 214808 kb
Host smart-e8624828-5d38-46b7-ba15-085480a82d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106929837 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.3106929837
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.3304497473
Short name T1
Test name
Test status
Simulation time 19892543 ps
CPU time 1.03 seconds
Started Jan 03 12:46:22 PM PST 24
Finished Jan 03 12:47:49 PM PST 24
Peak memory 205464 kb
Host smart-d37009be-a874-47fc-ad34-3d196248d3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304497473 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.3304497473
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.797023505
Short name T70
Test name
Test status
Simulation time 49291357 ps
CPU time 0.85 seconds
Started Jan 03 12:47:03 PM PST 24
Finished Jan 03 12:48:04 PM PST 24
Peak memory 214608 kb
Host smart-1079c746-85d6-4de4-ab02-35054003c791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797023505 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.797023505
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.1201792265
Short name T822
Test name
Test status
Simulation time 14093137 ps
CPU time 0.89 seconds
Started Jan 03 12:46:19 PM PST 24
Finished Jan 03 12:47:40 PM PST 24
Peak memory 205052 kb
Host smart-b16f89cf-58c9-4549-ae0a-2af9c6f70c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201792265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.1201792265
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.2826564291
Short name T208
Test name
Test status
Simulation time 48140520 ps
CPU time 0.81 seconds
Started Jan 03 12:46:46 PM PST 24
Finished Jan 03 12:47:55 PM PST 24
Peak memory 215856 kb
Host smart-4539c429-ca87-4d30-be95-268f39aec08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826564291 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.2826564291
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.626483258
Short name T407
Test name
Test status
Simulation time 71449998 ps
CPU time 1.26 seconds
Started Jan 03 12:46:26 PM PST 24
Finished Jan 03 12:47:56 PM PST 24
Peak memory 205848 kb
Host smart-cde023aa-4f0b-4695-9ae5-5822dc3e4c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626483258 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.626483258
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.2435368658
Short name T626
Test name
Test status
Simulation time 37578736 ps
CPU time 0.91 seconds
Started Jan 03 12:46:27 PM PST 24
Finished Jan 03 12:47:44 PM PST 24
Peak memory 221780 kb
Host smart-cfff5528-c999-43ee-9baa-df77219bf77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435368658 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.2435368658
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.636197396
Short name T268
Test name
Test status
Simulation time 44006380 ps
CPU time 0.84 seconds
Started Jan 03 12:46:23 PM PST 24
Finished Jan 03 12:47:40 PM PST 24
Peak memory 204800 kb
Host smart-17abe1f3-b1d0-4efb-b439-708520e2dee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636197396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.636197396
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.617749868
Short name T572
Test name
Test status
Simulation time 62853227 ps
CPU time 0.96 seconds
Started Jan 03 12:46:27 PM PST 24
Finished Jan 03 12:47:44 PM PST 24
Peak memory 215816 kb
Host smart-97e8a7ce-b34d-4af8-bf37-46d4f75290e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617749868 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.617749868
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.501233800
Short name T745
Test name
Test status
Simulation time 25635042 ps
CPU time 1.52 seconds
Started Jan 03 12:46:33 PM PST 24
Finished Jan 03 12:47:54 PM PST 24
Peak memory 206152 kb
Host smart-42bd958e-6571-4f46-b7cf-279dd351cbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501233800 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.501233800
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.3440144424
Short name T628
Test name
Test status
Simulation time 22315882 ps
CPU time 0.97 seconds
Started Jan 03 12:46:23 PM PST 24
Finished Jan 03 12:47:42 PM PST 24
Peak memory 221288 kb
Host smart-c363a823-0a65-4a84-b8cb-65be774c5200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440144424 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.3440144424
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.667078054
Short name T699
Test name
Test status
Simulation time 21527931 ps
CPU time 1.07 seconds
Started Jan 03 12:46:27 PM PST 24
Finished Jan 03 12:47:44 PM PST 24
Peak memory 205652 kb
Host smart-c0d72945-6bc0-4c7f-ada3-b4c97a64ac08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667078054 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.667078054
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.2778660119
Short name T663
Test name
Test status
Simulation time 18831207 ps
CPU time 0.95 seconds
Started Jan 03 12:46:58 PM PST 24
Finished Jan 03 12:48:02 PM PST 24
Peak memory 215816 kb
Host smart-b6ccc2c2-e533-414b-ac1b-022df6c8d147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778660119 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.2778660119
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.2216041763
Short name T809
Test name
Test status
Simulation time 70502063 ps
CPU time 1.06 seconds
Started Jan 03 12:47:01 PM PST 24
Finished Jan 03 12:48:03 PM PST 24
Peak memory 205688 kb
Host smart-0b875ee2-4698-453a-a907-90f7a0c6d05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216041763 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.2216041763
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.362438783
Short name T684
Test name
Test status
Simulation time 84528941 ps
CPU time 0.94 seconds
Started Jan 03 12:46:33 PM PST 24
Finished Jan 03 12:47:53 PM PST 24
Peak memory 214524 kb
Host smart-5f0ad2ff-a8d0-4424-8fd8-230488605e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362438783 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.362438783
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.903375379
Short name T729
Test name
Test status
Simulation time 58550712 ps
CPU time 1 seconds
Started Jan 03 12:46:55 PM PST 24
Finished Jan 03 12:48:01 PM PST 24
Peak memory 214196 kb
Host smart-3cc976d9-da20-4d2c-a141-c144ead1ad02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903375379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.903375379
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.2948656732
Short name T209
Test name
Test status
Simulation time 18938517 ps
CPU time 0.99 seconds
Started Jan 03 12:46:30 PM PST 24
Finished Jan 03 12:47:55 PM PST 24
Peak memory 215736 kb
Host smart-619957ae-6cff-428c-8e26-e030475d5827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948656732 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.2948656732
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.3751834686
Short name T204
Test name
Test status
Simulation time 74923953 ps
CPU time 1.36 seconds
Started Jan 03 12:46:45 PM PST 24
Finished Jan 03 12:47:55 PM PST 24
Peak memory 214348 kb
Host smart-5e491bc1-faa1-4a45-a404-ec80ca55d011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751834686 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3751834686
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.2078649053
Short name T221
Test name
Test status
Simulation time 72982452 ps
CPU time 0.98 seconds
Started Jan 03 12:44:56 PM PST 24
Finished Jan 03 12:46:22 PM PST 24
Peak memory 205836 kb
Host smart-98306c2c-fc2f-42f0-aa8a-7d71e8f09cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078649053 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.2078649053
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_disable.2079000160
Short name T119
Test name
Test status
Simulation time 12611157 ps
CPU time 0.85 seconds
Started Jan 03 12:45:13 PM PST 24
Finished Jan 03 12:46:43 PM PST 24
Peak memory 214564 kb
Host smart-e26c22cc-2123-4cf5-944c-7465a9d33725
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079000160 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.2079000160
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.1173093044
Short name T726
Test name
Test status
Simulation time 35851649 ps
CPU time 0.97 seconds
Started Jan 03 12:45:01 PM PST 24
Finished Jan 03 12:46:29 PM PST 24
Peak memory 214564 kb
Host smart-f08202cc-6d75-490e-8886-5980f9b80658
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173093044 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.1173093044
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.630876095
Short name T571
Test name
Test status
Simulation time 54504247 ps
CPU time 0.8 seconds
Started Jan 03 12:45:39 PM PST 24
Finished Jan 03 12:47:12 PM PST 24
Peak memory 215848 kb
Host smart-6d4d2444-6066-4242-aac3-262160eb27c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630876095 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.630876095
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.1549293520
Short name T592
Test name
Test status
Simulation time 25752160 ps
CPU time 1.12 seconds
Started Jan 03 12:45:05 PM PST 24
Finished Jan 03 12:46:42 PM PST 24
Peak memory 214168 kb
Host smart-0743bfac-cc82-44d7-bbac-df29847fac84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549293520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.1549293520
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.405587549
Short name T380
Test name
Test status
Simulation time 36160660 ps
CPU time 0.84 seconds
Started Jan 03 12:45:03 PM PST 24
Finished Jan 03 12:46:47 PM PST 24
Peak memory 214456 kb
Host smart-2fae425f-f471-46da-95a1-f2b4b85fa2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405587549 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.405587549
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.3769456625
Short name T813
Test name
Test status
Simulation time 22175469 ps
CPU time 0.87 seconds
Started Jan 03 12:45:10 PM PST 24
Finished Jan 03 12:46:44 PM PST 24
Peak memory 204796 kb
Host smart-fbdceb8a-a622-493b-adc6-a18be7587d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769456625 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.3769456625
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/60.edn_err.1644164116
Short name T644
Test name
Test status
Simulation time 57371865 ps
CPU time 1.02 seconds
Started Jan 03 12:46:59 PM PST 24
Finished Jan 03 12:48:02 PM PST 24
Peak memory 214732 kb
Host smart-6740f746-6f76-49bd-9dcf-941b3b958fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644164116 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.1644164116
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.2470009211
Short name T438
Test name
Test status
Simulation time 200901616 ps
CPU time 2.92 seconds
Started Jan 03 12:46:34 PM PST 24
Finished Jan 03 12:47:49 PM PST 24
Peak memory 214332 kb
Host smart-02e2538e-f1f2-497e-8b93-3a9d45d2a9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470009211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.2470009211
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.1773014085
Short name T400
Test name
Test status
Simulation time 22639040 ps
CPU time 0.87 seconds
Started Jan 03 12:46:31 PM PST 24
Finished Jan 03 12:47:50 PM PST 24
Peak memory 215580 kb
Host smart-36bf886f-4cf0-4240-b7e6-3523e2ebc019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773014085 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.1773014085
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.1498767254
Short name T502
Test name
Test status
Simulation time 35366769 ps
CPU time 1.08 seconds
Started Jan 03 12:46:30 PM PST 24
Finished Jan 03 12:47:46 PM PST 24
Peak memory 214144 kb
Host smart-20cbddfc-3e82-4a1e-b316-706bbd1066c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498767254 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.1498767254
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.3286183813
Short name T650
Test name
Test status
Simulation time 77085425 ps
CPU time 1.08 seconds
Started Jan 03 12:47:05 PM PST 24
Finished Jan 03 12:48:05 PM PST 24
Peak memory 228504 kb
Host smart-8e4dc876-b8d1-4656-86b0-4326027f08f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286183813 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.3286183813
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/63.edn_err.3523932857
Short name T511
Test name
Test status
Simulation time 276175701 ps
CPU time 1.3 seconds
Started Jan 03 12:46:44 PM PST 24
Finished Jan 03 12:47:54 PM PST 24
Peak memory 227680 kb
Host smart-0d32f4ec-d6e6-46c3-9ee4-e8f31771dc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523932857 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.3523932857
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.3600568533
Short name T697
Test name
Test status
Simulation time 14686264 ps
CPU time 0.89 seconds
Started Jan 03 12:47:05 PM PST 24
Finished Jan 03 12:48:05 PM PST 24
Peak memory 205172 kb
Host smart-d7524f05-3fde-4464-8617-0a93f587de21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600568533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.3600568533
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.1848162002
Short name T545
Test name
Test status
Simulation time 21527580 ps
CPU time 0.93 seconds
Started Jan 03 12:46:22 PM PST 24
Finished Jan 03 12:47:49 PM PST 24
Peak memory 215896 kb
Host smart-41653aa0-de46-4a30-bab5-e607ec2af1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848162002 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.1848162002
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.479053592
Short name T444
Test name
Test status
Simulation time 16435865 ps
CPU time 1.03 seconds
Started Jan 03 12:46:27 PM PST 24
Finished Jan 03 12:47:43 PM PST 24
Peak memory 205712 kb
Host smart-e965a148-ac33-4369-841b-91df00323436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479053592 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.479053592
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.365882786
Short name T808
Test name
Test status
Simulation time 24037089 ps
CPU time 1.1 seconds
Started Jan 03 12:46:27 PM PST 24
Finished Jan 03 12:47:45 PM PST 24
Peak memory 216044 kb
Host smart-674dba28-cddd-4077-9463-1b00c2eb2672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365882786 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.365882786
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.4259709273
Short name T477
Test name
Test status
Simulation time 130120158 ps
CPU time 2.47 seconds
Started Jan 03 12:46:26 PM PST 24
Finished Jan 03 12:47:51 PM PST 24
Peak memory 214108 kb
Host smart-82e6220e-b777-47dd-807d-9c3ea90d2359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259709273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.4259709273
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.4198316171
Short name T596
Test name
Test status
Simulation time 45046349 ps
CPU time 1.25 seconds
Started Jan 03 12:47:00 PM PST 24
Finished Jan 03 12:48:03 PM PST 24
Peak memory 221800 kb
Host smart-532be92e-a468-4c41-9eba-def3a928551d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198316171 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.4198316171
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.3203343026
Short name T902
Test name
Test status
Simulation time 15216795 ps
CPU time 0.95 seconds
Started Jan 03 12:46:23 PM PST 24
Finished Jan 03 12:47:41 PM PST 24
Peak memory 205648 kb
Host smart-b4b20772-daa1-4840-a22c-fa0ba577b23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203343026 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.3203343026
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_genbits.110142058
Short name T749
Test name
Test status
Simulation time 47674553 ps
CPU time 0.94 seconds
Started Jan 03 12:46:52 PM PST 24
Finished Jan 03 12:48:00 PM PST 24
Peak memory 205580 kb
Host smart-15003f67-37c7-472d-aedb-8df2d0936583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110142058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.110142058
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.1296368848
Short name T8
Test name
Test status
Simulation time 32604731 ps
CPU time 1.03 seconds
Started Jan 03 12:46:23 PM PST 24
Finished Jan 03 12:47:42 PM PST 24
Peak memory 216208 kb
Host smart-4df06556-7c8c-4fae-94b4-8d727d666f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296368848 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.1296368848
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.1897713969
Short name T719
Test name
Test status
Simulation time 32020493 ps
CPU time 0.92 seconds
Started Jan 03 12:46:51 PM PST 24
Finished Jan 03 12:47:58 PM PST 24
Peak memory 205148 kb
Host smart-f20b8b11-d96e-4bdb-a6d3-9a4a5537a0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897713969 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.1897713969
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.2321364067
Short name T517
Test name
Test status
Simulation time 18705312 ps
CPU time 1.06 seconds
Started Jan 03 12:46:32 PM PST 24
Finished Jan 03 12:47:49 PM PST 24
Peak memory 215640 kb
Host smart-dba5823b-de2d-48eb-81f2-5f8a328b8bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321364067 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.2321364067
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.2587328082
Short name T855
Test name
Test status
Simulation time 74350431 ps
CPU time 1.05 seconds
Started Jan 03 12:46:57 PM PST 24
Finished Jan 03 12:48:02 PM PST 24
Peak memory 205312 kb
Host smart-83a279cb-eb93-44e8-be41-c9f0d0580fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587328082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.2587328082
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert_test.2812532745
Short name T677
Test name
Test status
Simulation time 54192734 ps
CPU time 0.84 seconds
Started Jan 03 12:45:04 PM PST 24
Finished Jan 03 12:46:38 PM PST 24
Peak memory 204724 kb
Host smart-1d0d88b3-0dde-4ecb-a2fc-286419bb31a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812532745 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.2812532745
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.1995835563
Short name T755
Test name
Test status
Simulation time 23288492 ps
CPU time 0.86 seconds
Started Jan 03 12:45:13 PM PST 24
Finished Jan 03 12:46:54 PM PST 24
Peak memory 214344 kb
Host smart-9bc6b0bd-055d-450c-8053-615e902e4146
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995835563 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.1995835563
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_err.2955103787
Short name T384
Test name
Test status
Simulation time 24794534 ps
CPU time 0.95 seconds
Started Jan 03 12:45:37 PM PST 24
Finished Jan 03 12:47:16 PM PST 24
Peak memory 215036 kb
Host smart-ea77dde4-898f-423f-8218-3115c561e9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955103787 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.2955103787
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.812957195
Short name T440
Test name
Test status
Simulation time 60325138 ps
CPU time 0.96 seconds
Started Jan 03 12:45:31 PM PST 24
Finished Jan 03 12:47:04 PM PST 24
Peak memory 205652 kb
Host smart-e05714d6-645a-45cc-b23b-153a381d6c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812957195 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.812957195
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_regwen.3697322813
Short name T212
Test name
Test status
Simulation time 22572729 ps
CPU time 0.85 seconds
Started Jan 03 12:44:54 PM PST 24
Finished Jan 03 12:46:24 PM PST 24
Peak memory 204936 kb
Host smart-451792ac-8309-4754-a92b-c7e309256d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697322813 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.3697322813
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.1031028184
Short name T508
Test name
Test status
Simulation time 13695849 ps
CPU time 0.87 seconds
Started Jan 03 12:45:06 PM PST 24
Finished Jan 03 12:46:40 PM PST 24
Peak memory 204804 kb
Host smart-12f3a167-89e5-41f1-8eee-78567ec35b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031028184 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.1031028184
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.313607439
Short name T617
Test name
Test status
Simulation time 82057449 ps
CPU time 1.4 seconds
Started Jan 03 12:45:32 PM PST 24
Finished Jan 03 12:47:02 PM PST 24
Peak memory 205940 kb
Host smart-b72a9920-f325-42bd-8b82-222490113085
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313607439 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.313607439
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/70.edn_err.3031102899
Short name T71
Test name
Test status
Simulation time 41693314 ps
CPU time 1.06 seconds
Started Jan 03 12:46:24 PM PST 24
Finished Jan 03 12:47:41 PM PST 24
Peak memory 217120 kb
Host smart-226933bf-cdf7-4914-80b8-d24713aae7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031102899 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.3031102899
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.3262904791
Short name T612
Test name
Test status
Simulation time 122590994 ps
CPU time 1 seconds
Started Jan 03 12:47:03 PM PST 24
Finished Jan 03 12:48:04 PM PST 24
Peak memory 205696 kb
Host smart-60000e6d-eee5-4c5d-a4ac-7e60ff89cfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262904791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.3262904791
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.3166836906
Short name T550
Test name
Test status
Simulation time 28238858 ps
CPU time 1.23 seconds
Started Jan 03 12:47:04 PM PST 24
Finished Jan 03 12:48:05 PM PST 24
Peak memory 228312 kb
Host smart-41e06caa-47b0-400c-98ce-f5f83afefa6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166836906 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.3166836906
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.2479357076
Short name T497
Test name
Test status
Simulation time 16383985 ps
CPU time 0.96 seconds
Started Jan 03 12:46:26 PM PST 24
Finished Jan 03 12:47:55 PM PST 24
Peak memory 205656 kb
Host smart-2572c412-7aba-4912-af14-142d357a00e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479357076 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.2479357076
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.1264306475
Short name T114
Test name
Test status
Simulation time 26476706 ps
CPU time 1.16 seconds
Started Jan 03 12:46:31 PM PST 24
Finished Jan 03 12:47:45 PM PST 24
Peak memory 214744 kb
Host smart-3ccc9c05-84c6-4e3c-9f03-2fbba2b5717b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264306475 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.1264306475
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.3288605225
Short name T814
Test name
Test status
Simulation time 62005380 ps
CPU time 0.92 seconds
Started Jan 03 12:46:52 PM PST 24
Finished Jan 03 12:48:00 PM PST 24
Peak memory 205084 kb
Host smart-fd28bfd2-0c25-4c11-8beb-11253b9a27e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288605225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.3288605225
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.2895465198
Short name T377
Test name
Test status
Simulation time 37526860 ps
CPU time 1.09 seconds
Started Jan 03 12:46:49 PM PST 24
Finished Jan 03 12:47:57 PM PST 24
Peak memory 217160 kb
Host smart-e96034fe-8571-430f-8fd3-39df2217a4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895465198 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.2895465198
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.950916082
Short name T751
Test name
Test status
Simulation time 194669019 ps
CPU time 1.02 seconds
Started Jan 03 12:46:30 PM PST 24
Finished Jan 03 12:47:56 PM PST 24
Peak memory 205328 kb
Host smart-49f57473-9ebf-492e-9b6e-55feb574dd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950916082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.950916082
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.3007502596
Short name T607
Test name
Test status
Simulation time 36272690 ps
CPU time 1.03 seconds
Started Jan 03 12:46:57 PM PST 24
Finished Jan 03 12:48:02 PM PST 24
Peak memory 214540 kb
Host smart-cf00931b-7107-45ca-a94d-4d9a11c26b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007502596 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.3007502596
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.3324809632
Short name T41
Test name
Test status
Simulation time 156009507 ps
CPU time 2.33 seconds
Started Jan 03 12:46:30 PM PST 24
Finished Jan 03 12:47:47 PM PST 24
Peak memory 214112 kb
Host smart-79e2eb06-869a-40ea-aacc-e9effd1016d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324809632 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.3324809632
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.577406616
Short name T548
Test name
Test status
Simulation time 34459706 ps
CPU time 1.06 seconds
Started Jan 03 12:47:03 PM PST 24
Finished Jan 03 12:48:04 PM PST 24
Peak memory 216280 kb
Host smart-c864b7df-6a44-4319-891e-d636cd2f2566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577406616 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.577406616
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.3642189619
Short name T583
Test name
Test status
Simulation time 14796873 ps
CPU time 0.95 seconds
Started Jan 03 12:46:54 PM PST 24
Finished Jan 03 12:48:01 PM PST 24
Peak memory 205548 kb
Host smart-bd2ea3a2-d384-42c6-9a54-7c7c9f1b77b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642189619 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.3642189619
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.400109754
Short name T610
Test name
Test status
Simulation time 22110397 ps
CPU time 0.88 seconds
Started Jan 03 12:46:23 PM PST 24
Finished Jan 03 12:47:42 PM PST 24
Peak memory 215744 kb
Host smart-25c72023-8523-4d07-8fb2-63fd5ea709d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400109754 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.400109754
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.2541593719
Short name T860
Test name
Test status
Simulation time 28127492 ps
CPU time 1 seconds
Started Jan 03 12:46:38 PM PST 24
Finished Jan 03 12:47:50 PM PST 24
Peak memory 205464 kb
Host smart-6cf2c3f1-98b0-4138-9e1a-ea453c7a3ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541593719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.2541593719
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.766609628
Short name T492
Test name
Test status
Simulation time 19475289 ps
CPU time 1.06 seconds
Started Jan 03 12:46:23 PM PST 24
Finished Jan 03 12:47:42 PM PST 24
Peak memory 215800 kb
Host smart-893892eb-44be-46d0-872f-c6962fa89838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766609628 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.766609628
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.2763955080
Short name T257
Test name
Test status
Simulation time 35281290 ps
CPU time 0.99 seconds
Started Jan 03 12:46:40 PM PST 24
Finished Jan 03 12:47:56 PM PST 24
Peak memory 205592 kb
Host smart-67de1d9c-0178-4f38-92ac-1b49f54453a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763955080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.2763955080
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.26658877
Short name T49
Test name
Test status
Simulation time 19605701 ps
CPU time 1.19 seconds
Started Jan 03 12:46:24 PM PST 24
Finished Jan 03 12:47:48 PM PST 24
Peak memory 221820 kb
Host smart-0e26959e-4467-48ce-a2a6-137984412a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26658877 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.26658877
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.9143193
Short name T281
Test name
Test status
Simulation time 67484664 ps
CPU time 1.17 seconds
Started Jan 03 12:46:58 PM PST 24
Finished Jan 03 12:48:02 PM PST 24
Peak memory 206052 kb
Host smart-d29d3375-8dd0-4f7d-92a8-f4daeb397b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9143193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.9143193
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.3398495352
Short name T414
Test name
Test status
Simulation time 27109095 ps
CPU time 0.79 seconds
Started Jan 03 12:46:34 PM PST 24
Finished Jan 03 12:47:47 PM PST 24
Peak memory 215716 kb
Host smart-0f44e6db-429a-4129-b0d9-aa40d841c233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398495352 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.3398495352
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/8.edn_alert.2292080
Short name T914
Test name
Test status
Simulation time 38593687 ps
CPU time 0.98 seconds
Started Jan 03 12:45:30 PM PST 24
Finished Jan 03 12:47:02 PM PST 24
Peak memory 205884 kb
Host smart-fc2dd81a-da6b-47f1-a06a-8867a93d2f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292080 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.2292080
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.1123761858
Short name T104
Test name
Test status
Simulation time 43317503 ps
CPU time 0.9 seconds
Started Jan 03 12:45:08 PM PST 24
Finished Jan 03 12:46:41 PM PST 24
Peak memory 204604 kb
Host smart-87d7077f-5cf3-45ad-ad51-7a0c45fc7f1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123761858 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.1123761858
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.4192680576
Short name T118
Test name
Test status
Simulation time 21335981 ps
CPU time 0.85 seconds
Started Jan 03 12:45:34 PM PST 24
Finished Jan 03 12:47:46 PM PST 24
Peak memory 214436 kb
Host smart-d8fef927-62b9-4195-87c6-aa8af46bd732
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192680576 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.4192680576
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.1445965386
Short name T110
Test name
Test status
Simulation time 54416580 ps
CPU time 1.06 seconds
Started Jan 03 12:45:12 PM PST 24
Finished Jan 03 12:46:43 PM PST 24
Peak memory 214548 kb
Host smart-2a8c5f27-1262-4ce2-86ba-3e047d5a0034
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445965386 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.1445965386
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.2733865516
Short name T478
Test name
Test status
Simulation time 106775194 ps
CPU time 0.95 seconds
Started Jan 03 12:44:59 PM PST 24
Finished Jan 03 12:46:31 PM PST 24
Peak memory 214408 kb
Host smart-59d3c640-0830-4cb8-8fdf-0b6ffeda4f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733865516 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.2733865516
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.1016850912
Short name T484
Test name
Test status
Simulation time 1249740794 ps
CPU time 7.73 seconds
Started Jan 03 12:45:45 PM PST 24
Finished Jan 03 12:47:21 PM PST 24
Peak memory 214328 kb
Host smart-e1904267-6a54-4440-b4f9-5acd17c9f4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016850912 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.1016850912
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.1484104333
Short name T100
Test name
Test status
Simulation time 26607105 ps
CPU time 1.08 seconds
Started Jan 03 12:45:41 PM PST 24
Finished Jan 03 12:47:18 PM PST 24
Peak memory 214520 kb
Host smart-4764bbdf-16d5-45b8-8dd4-938ad087ed6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484104333 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.1484104333
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.1038992052
Short name T193
Test name
Test status
Simulation time 26152500 ps
CPU time 0.83 seconds
Started Jan 03 12:45:00 PM PST 24
Finished Jan 03 12:46:35 PM PST 24
Peak memory 205020 kb
Host smart-0eeb8bee-9fea-4366-9e5d-21f22ea4bbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038992052 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.1038992052
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.2753928122
Short name T774
Test name
Test status
Simulation time 27644801 ps
CPU time 0.86 seconds
Started Jan 03 12:45:45 PM PST 24
Finished Jan 03 12:47:14 PM PST 24
Peak memory 204904 kb
Host smart-f400cfc0-c608-4655-b719-ebb02a83e5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753928122 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.2753928122
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.2803548295
Short name T619
Test name
Test status
Simulation time 165051377 ps
CPU time 1.72 seconds
Started Jan 03 12:45:20 PM PST 24
Finished Jan 03 12:47:00 PM PST 24
Peak memory 205968 kb
Host smart-f3aa9d88-b134-4d39-8841-50932a3a3472
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803548295 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.2803548295
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/80.edn_err.3247846292
Short name T510
Test name
Test status
Simulation time 26505881 ps
CPU time 0.83 seconds
Started Jan 03 12:46:18 PM PST 24
Finished Jan 03 12:47:45 PM PST 24
Peak memory 215928 kb
Host smart-2c8e109a-3a08-4c94-b1bc-904906fe58a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247846292 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.3247846292
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.2662752357
Short name T891
Test name
Test status
Simulation time 102236855 ps
CPU time 1.07 seconds
Started Jan 03 12:46:36 PM PST 24
Finished Jan 03 12:47:49 PM PST 24
Peak memory 214336 kb
Host smart-03e5af6f-6453-4d47-aabb-da26a63ac593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662752357 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.2662752357
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.4093193177
Short name T51
Test name
Test status
Simulation time 29615059 ps
CPU time 1.23 seconds
Started Jan 03 12:46:26 PM PST 24
Finished Jan 03 12:47:55 PM PST 24
Peak memory 228680 kb
Host smart-ead63e3e-d88a-486c-94e1-5a083f3a5fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093193177 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.4093193177
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.667505976
Short name T529
Test name
Test status
Simulation time 80643721 ps
CPU time 1.79 seconds
Started Jan 03 12:46:55 PM PST 24
Finished Jan 03 12:48:02 PM PST 24
Peak memory 214160 kb
Host smart-69e002bb-4283-4664-8f79-8001314c8b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667505976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.667505976
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.2193182096
Short name T835
Test name
Test status
Simulation time 19790002 ps
CPU time 1.22 seconds
Started Jan 03 12:46:38 PM PST 24
Finished Jan 03 12:47:50 PM PST 24
Peak memory 221816 kb
Host smart-fa71c4e8-d58b-41a1-805e-640ea09dd095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193182096 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.2193182096
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.4232585203
Short name T265
Test name
Test status
Simulation time 127781601 ps
CPU time 0.9 seconds
Started Jan 03 12:46:27 PM PST 24
Finished Jan 03 12:47:44 PM PST 24
Peak memory 205192 kb
Host smart-5697e783-e431-482e-befb-db90c4e9513e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232585203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.4232585203
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.3735163516
Short name T657
Test name
Test status
Simulation time 53028242 ps
CPU time 1.21 seconds
Started Jan 03 12:46:43 PM PST 24
Finished Jan 03 12:47:54 PM PST 24
Peak memory 214716 kb
Host smart-b1b75d42-aa67-4e59-8f6b-2ae24a18a3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735163516 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.3735163516
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.4091218296
Short name T465
Test name
Test status
Simulation time 24359213 ps
CPU time 0.9 seconds
Started Jan 03 12:46:40 PM PST 24
Finished Jan 03 12:47:52 PM PST 24
Peak memory 205408 kb
Host smart-f6c7c9f2-3c8d-44db-8854-1821e7934b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091218296 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.4091218296
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.2639091150
Short name T734
Test name
Test status
Simulation time 54431944 ps
CPU time 0.99 seconds
Started Jan 03 12:46:33 PM PST 24
Finished Jan 03 12:47:55 PM PST 24
Peak memory 215832 kb
Host smart-8aa21206-caa1-4e99-aa73-e621aa0bc9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639091150 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.2639091150
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.2319297769
Short name T913
Test name
Test status
Simulation time 52845865 ps
CPU time 0.88 seconds
Started Jan 03 12:46:26 PM PST 24
Finished Jan 03 12:47:55 PM PST 24
Peak memory 205052 kb
Host smart-39d49b7d-4e8b-436d-83f4-4dcfaa192779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319297769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.2319297769
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.1212212874
Short name T402
Test name
Test status
Simulation time 28750934 ps
CPU time 0.81 seconds
Started Jan 03 12:46:39 PM PST 24
Finished Jan 03 12:47:51 PM PST 24
Peak memory 215648 kb
Host smart-ea32e973-da8b-49ad-bec3-9312ba3c9129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212212874 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.1212212874
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.4021248864
Short name T694
Test name
Test status
Simulation time 22090240 ps
CPU time 1.14 seconds
Started Jan 03 12:46:23 PM PST 24
Finished Jan 03 12:47:42 PM PST 24
Peak memory 205804 kb
Host smart-935b9d01-03af-409a-9e22-86ec804c5715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021248864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.4021248864
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.1601077906
Short name T608
Test name
Test status
Simulation time 43302161 ps
CPU time 1.17 seconds
Started Jan 03 12:46:35 PM PST 24
Finished Jan 03 12:47:48 PM PST 24
Peak memory 221856 kb
Host smart-4f6b628b-b362-4a58-824c-e30301245de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601077906 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.1601077906
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.960822896
Short name T905
Test name
Test status
Simulation time 114533315 ps
CPU time 2.61 seconds
Started Jan 03 12:46:27 PM PST 24
Finished Jan 03 12:47:46 PM PST 24
Peak memory 214172 kb
Host smart-61c6c621-09cd-462c-aa32-9f4f00f6b89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960822896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.960822896
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.420550481
Short name T696
Test name
Test status
Simulation time 26922311 ps
CPU time 1.11 seconds
Started Jan 03 12:46:24 PM PST 24
Finished Jan 03 12:47:42 PM PST 24
Peak memory 228380 kb
Host smart-4966e907-270e-4723-8b20-bfdd3e6851f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420550481 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.420550481
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.767237927
Short name T449
Test name
Test status
Simulation time 16542665 ps
CPU time 0.98 seconds
Started Jan 03 12:46:59 PM PST 24
Finished Jan 03 12:48:02 PM PST 24
Peak memory 205140 kb
Host smart-3fb0cf00-bad4-4e73-a55d-687566471c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767237927 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.767237927
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.107269433
Short name T500
Test name
Test status
Simulation time 34530671 ps
CPU time 1.35 seconds
Started Jan 03 12:46:59 PM PST 24
Finished Jan 03 12:48:02 PM PST 24
Peak memory 227744 kb
Host smart-c41f3cbe-8cef-4f3e-b001-b127951b3c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107269433 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.107269433
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.3921439577
Short name T707
Test name
Test status
Simulation time 79319549 ps
CPU time 0.88 seconds
Started Jan 03 12:47:35 PM PST 24
Finished Jan 03 12:48:21 PM PST 24
Peak memory 204856 kb
Host smart-cc376518-f765-42a7-9aa2-617d5cfeb55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921439577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.3921439577
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.890480444
Short name T467
Test name
Test status
Simulation time 19511079 ps
CPU time 1.01 seconds
Started Jan 03 12:46:42 PM PST 24
Finished Jan 03 12:47:53 PM PST 24
Peak memory 215888 kb
Host smart-d5a0b978-c13f-48cd-a5ca-34db1302c9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890480444 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.890480444
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.2478004215
Short name T897
Test name
Test status
Simulation time 99731152 ps
CPU time 1.28 seconds
Started Jan 03 12:46:45 PM PST 24
Finished Jan 03 12:47:55 PM PST 24
Peak memory 205784 kb
Host smart-c62e1324-a598-41f7-9de2-bfc40b1a5114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478004215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.2478004215
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.1412843391
Short name T799
Test name
Test status
Simulation time 33467399 ps
CPU time 0.88 seconds
Started Jan 03 12:45:07 PM PST 24
Finished Jan 03 12:46:40 PM PST 24
Peak memory 205256 kb
Host smart-ec205810-b9a5-4174-85d4-1f6690c20384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412843391 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.1412843391
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.959963614
Short name T472
Test name
Test status
Simulation time 51182249 ps
CPU time 0.85 seconds
Started Jan 03 12:45:04 PM PST 24
Finished Jan 03 12:46:32 PM PST 24
Peak memory 204656 kb
Host smart-a39db5af-5345-476b-bbea-0c7125121d26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959963614 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.959963614
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.1367066210
Short name T560
Test name
Test status
Simulation time 19176325 ps
CPU time 0.93 seconds
Started Jan 03 12:45:07 PM PST 24
Finished Jan 03 12:46:40 PM PST 24
Peak memory 214708 kb
Host smart-0f20999a-f380-4ebc-99ac-a88258c4c4cf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367066210 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.1367066210
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.1287986459
Short name T866
Test name
Test status
Simulation time 21901641 ps
CPU time 0.9 seconds
Started Jan 03 12:45:49 PM PST 24
Finished Jan 03 12:47:28 PM PST 24
Peak memory 215976 kb
Host smart-82263fb6-2588-44e9-b3b7-348dd7618a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287986459 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.1287986459
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.2671828318
Short name T284
Test name
Test status
Simulation time 19952632 ps
CPU time 1 seconds
Started Jan 03 12:44:51 PM PST 24
Finished Jan 03 12:46:30 PM PST 24
Peak memory 205364 kb
Host smart-8c529628-aaf9-45e1-9fc6-e32e72a3bc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671828318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.2671828318
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.2976968552
Short name T785
Test name
Test status
Simulation time 21599581 ps
CPU time 1.07 seconds
Started Jan 03 12:45:29 PM PST 24
Finished Jan 03 12:46:59 PM PST 24
Peak memory 221760 kb
Host smart-22632cea-168d-48b9-9464-647969bf0390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976968552 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.2976968552
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.3973145626
Short name T214
Test name
Test status
Simulation time 13656314 ps
CPU time 0.91 seconds
Started Jan 03 12:45:34 PM PST 24
Finished Jan 03 12:47:06 PM PST 24
Peak memory 204836 kb
Host smart-7366d697-afac-4025-8964-1587888c0deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973145626 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.3973145626
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.2097980233
Short name T504
Test name
Test status
Simulation time 96593102 ps
CPU time 0.85 seconds
Started Jan 03 12:45:19 PM PST 24
Finished Jan 03 12:46:51 PM PST 24
Peak memory 204824 kb
Host smart-30d7f6fe-46af-4a4c-831c-05a0f178663a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097980233 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.2097980233
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.2998917555
Short name T858
Test name
Test status
Simulation time 21266257167 ps
CPU time 548.78 seconds
Started Jan 03 12:45:04 PM PST 24
Finished Jan 03 12:55:54 PM PST 24
Peak memory 214620 kb
Host smart-bd97efc9-370d-47f8-9df9-fa85353b4b29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998917555 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.2998917555
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.4169304838
Short name T73
Test name
Test status
Simulation time 66858800 ps
CPU time 1.01 seconds
Started Jan 03 12:46:40 PM PST 24
Finished Jan 03 12:47:52 PM PST 24
Peak memory 217296 kb
Host smart-1f9e6e89-ad04-4463-9f46-012f435d6f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169304838 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.4169304838
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.336893543
Short name T264
Test name
Test status
Simulation time 18683700 ps
CPU time 0.95 seconds
Started Jan 03 12:46:32 PM PST 24
Finished Jan 03 12:47:48 PM PST 24
Peak memory 205164 kb
Host smart-1d652ddc-968d-48dd-b7e7-49dcfb31aa54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336893543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.336893543
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.440453752
Short name T524
Test name
Test status
Simulation time 24135593 ps
CPU time 1.09 seconds
Started Jan 03 12:46:30 PM PST 24
Finished Jan 03 12:47:45 PM PST 24
Peak memory 215920 kb
Host smart-46c966ea-490c-4d2e-92b5-911a7c9ec556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440453752 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.440453752
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.909491270
Short name T683
Test name
Test status
Simulation time 17470538 ps
CPU time 1.12 seconds
Started Jan 03 12:46:51 PM PST 24
Finished Jan 03 12:48:00 PM PST 24
Peak memory 214336 kb
Host smart-e80db83c-59ab-4b26-a6bc-45f6d8d6c514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909491270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.909491270
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.2362282204
Short name T115
Test name
Test status
Simulation time 63069306 ps
CPU time 0.99 seconds
Started Jan 03 12:46:57 PM PST 24
Finished Jan 03 12:48:01 PM PST 24
Peak memory 215748 kb
Host smart-a8a63c73-9e71-43cc-aa0b-2c19b04eec8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362282204 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.2362282204
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.2668467795
Short name T45
Test name
Test status
Simulation time 20601997 ps
CPU time 1.02 seconds
Started Jan 03 12:47:03 PM PST 24
Finished Jan 03 12:48:04 PM PST 24
Peak memory 205680 kb
Host smart-eaea9ef0-96e1-4dfe-b099-0494c0b18f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668467795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.2668467795
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.2693577117
Short name T52
Test name
Test status
Simulation time 23947705 ps
CPU time 1.02 seconds
Started Jan 03 12:46:28 PM PST 24
Finished Jan 03 12:47:43 PM PST 24
Peak memory 228324 kb
Host smart-39db36fa-b3fe-4316-8ce6-71332fbdc86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693577117 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.2693577117
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.1334323673
Short name T373
Test name
Test status
Simulation time 48083348 ps
CPU time 0.87 seconds
Started Jan 03 12:46:50 PM PST 24
Finished Jan 03 12:47:58 PM PST 24
Peak memory 205592 kb
Host smart-3055a3d6-1b3d-4287-88f7-b4004730733c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334323673 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.1334323673
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.3715271730
Short name T481
Test name
Test status
Simulation time 24047900 ps
CPU time 0.88 seconds
Started Jan 03 12:46:41 PM PST 24
Finished Jan 03 12:47:52 PM PST 24
Peak memory 216096 kb
Host smart-bd9fcc4a-63b0-4352-aa01-a301cead996e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715271730 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.3715271730
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.3244825141
Short name T42
Test name
Test status
Simulation time 23200583 ps
CPU time 1.07 seconds
Started Jan 03 12:46:29 PM PST 24
Finished Jan 03 12:47:51 PM PST 24
Peak memory 205664 kb
Host smart-1d67b7b8-e4ad-49de-812b-ce6757d14307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244825141 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.3244825141
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.2699441033
Short name T9
Test name
Test status
Simulation time 19740064 ps
CPU time 1.04 seconds
Started Jan 03 12:46:24 PM PST 24
Finished Jan 03 12:47:46 PM PST 24
Peak memory 214772 kb
Host smart-be3168dc-722d-4fd5-8cb5-0fd9731b0467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699441033 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.2699441033
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.995542411
Short name T274
Test name
Test status
Simulation time 106382736 ps
CPU time 0.94 seconds
Started Jan 03 12:46:27 PM PST 24
Finished Jan 03 12:47:47 PM PST 24
Peak memory 205348 kb
Host smart-73bbc64e-1425-4159-b07a-746f8f1ca3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995542411 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.995542411
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.2945697894
Short name T15
Test name
Test status
Simulation time 25298304 ps
CPU time 1.01 seconds
Started Jan 03 12:46:38 PM PST 24
Finished Jan 03 12:47:51 PM PST 24
Peak memory 221892 kb
Host smart-588444e8-4d3e-4de0-991c-8e8a1b08473f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945697894 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.2945697894
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.4134929931
Short name T589
Test name
Test status
Simulation time 117427752 ps
CPU time 0.96 seconds
Started Jan 03 12:47:00 PM PST 24
Finished Jan 03 12:48:03 PM PST 24
Peak memory 205184 kb
Host smart-6fdaa767-cbc8-4fb4-9005-7df401850ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134929931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.4134929931
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.515229959
Short name T547
Test name
Test status
Simulation time 39083874 ps
CPU time 0.98 seconds
Started Jan 03 12:46:55 PM PST 24
Finished Jan 03 12:48:01 PM PST 24
Peak memory 228768 kb
Host smart-e5ae7628-84c4-48dd-85b4-d83a135c0a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515229959 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.515229959
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.969608795
Short name T883
Test name
Test status
Simulation time 15851608 ps
CPU time 1.13 seconds
Started Jan 03 12:46:59 PM PST 24
Finished Jan 03 12:48:02 PM PST 24
Peak memory 205328 kb
Host smart-721dc356-ada2-4eb7-ad17-13e6c13453ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969608795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.969608795
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.3619606100
Short name T787
Test name
Test status
Simulation time 18096041 ps
CPU time 1.41 seconds
Started Jan 03 12:46:26 PM PST 24
Finished Jan 03 12:47:55 PM PST 24
Peak memory 221716 kb
Host smart-a2ef39b3-9b29-4a82-bf0b-d11b8a85fc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619606100 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.3619606100
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.1043766495
Short name T242
Test name
Test status
Simulation time 70731497 ps
CPU time 1.09 seconds
Started Jan 03 12:46:49 PM PST 24
Finished Jan 03 12:47:58 PM PST 24
Peak memory 214184 kb
Host smart-82a3ff9b-87c1-4bfe-88ed-a51672e0fe35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043766495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.1043766495
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.3820144810
Short name T758
Test name
Test status
Simulation time 19208452 ps
CPU time 1.27 seconds
Started Jan 03 12:46:40 PM PST 24
Finished Jan 03 12:47:52 PM PST 24
Peak memory 214652 kb
Host smart-9d66b363-e91b-41ee-8491-d8893c5525ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820144810 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.3820144810
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.3776408481
Short name T638
Test name
Test status
Simulation time 40581793 ps
CPU time 1.37 seconds
Started Jan 03 12:46:23 PM PST 24
Finished Jan 03 12:47:43 PM PST 24
Peak memory 214184 kb
Host smart-2351b766-a884-4a14-b02d-dc40458085bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776408481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.3776408481
Directory /workspace/99.edn_genbits/latest
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