Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.95 99.02 92.05 96.79 93.42 98.62 99.77 99.00


Total test records in report: 823
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T769 /workspace/coverage/cover_reg_top/18.edn_tl_errors.833104455 Jan 07 12:26:04 PM PST 24 Jan 07 12:27:03 PM PST 24 25161577 ps
T770 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3371848477 Jan 07 12:23:53 PM PST 24 Jan 07 12:24:08 PM PST 24 106097480 ps
T771 /workspace/coverage/cover_reg_top/35.edn_intr_test.2930469558 Jan 07 12:23:27 PM PST 24 Jan 07 12:23:33 PM PST 24 107368050 ps
T186 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2259430699 Jan 07 12:26:22 PM PST 24 Jan 07 12:27:26 PM PST 24 27408297 ps
T772 /workspace/coverage/cover_reg_top/22.edn_intr_test.3437069010 Jan 07 12:26:52 PM PST 24 Jan 07 12:28:09 PM PST 24 41406468 ps
T773 /workspace/coverage/cover_reg_top/33.edn_intr_test.572861654 Jan 07 12:27:05 PM PST 24 Jan 07 12:28:25 PM PST 24 11317325 ps
T774 /workspace/coverage/cover_reg_top/6.edn_intr_test.2561277373 Jan 07 12:26:59 PM PST 24 Jan 07 12:28:14 PM PST 24 26137752 ps
T775 /workspace/coverage/cover_reg_top/2.edn_intr_test.257335232 Jan 07 12:29:18 PM PST 24 Jan 07 12:30:54 PM PST 24 16658390 ps
T187 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1775975443 Jan 07 12:26:27 PM PST 24 Jan 07 12:27:40 PM PST 24 58944817 ps
T188 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2436803177 Jan 07 12:44:16 PM PST 24 Jan 07 12:46:49 PM PST 24 57094201 ps
T776 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2749112136 Jan 07 12:31:09 PM PST 24 Jan 07 12:32:24 PM PST 24 78409372 ps
T189 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.4063502857 Jan 07 12:26:19 PM PST 24 Jan 07 12:27:23 PM PST 24 59796306 ps
T777 /workspace/coverage/cover_reg_top/10.edn_tl_errors.1361752902 Jan 07 12:32:21 PM PST 24 Jan 07 12:34:05 PM PST 24 175204732 ps
T190 /workspace/coverage/cover_reg_top/7.edn_csr_rw.3609807339 Jan 07 12:31:18 PM PST 24 Jan 07 12:33:15 PM PST 24 48566817 ps
T778 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.602576697 Jan 07 12:29:09 PM PST 24 Jan 07 12:30:27 PM PST 24 148254348 ps
T779 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.4175603690 Jan 07 12:26:22 PM PST 24 Jan 07 12:27:27 PM PST 24 118470344 ps
T780 /workspace/coverage/cover_reg_top/5.edn_intr_test.2020746135 Jan 07 12:30:43 PM PST 24 Jan 07 12:32:14 PM PST 24 31537223 ps
T781 /workspace/coverage/cover_reg_top/39.edn_intr_test.1437051228 Jan 07 12:25:44 PM PST 24 Jan 07 12:26:44 PM PST 24 19205861 ps
T782 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3507077690 Jan 07 12:29:31 PM PST 24 Jan 07 12:31:06 PM PST 24 344147743 ps
T783 /workspace/coverage/cover_reg_top/43.edn_intr_test.1676247848 Jan 07 12:28:53 PM PST 24 Jan 07 12:30:05 PM PST 24 22032714 ps
T172 /workspace/coverage/cover_reg_top/9.edn_csr_rw.1100295360 Jan 07 12:29:44 PM PST 24 Jan 07 12:31:19 PM PST 24 41725389 ps
T180 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1646698051 Jan 07 12:29:49 PM PST 24 Jan 07 12:31:55 PM PST 24 33413346 ps
T181 /workspace/coverage/cover_reg_top/9.edn_intr_test.4087848870 Jan 07 12:26:34 PM PST 24 Jan 07 12:27:47 PM PST 24 11188910 ps
T784 /workspace/coverage/cover_reg_top/26.edn_intr_test.1130347363 Jan 07 12:31:46 PM PST 24 Jan 07 12:34:06 PM PST 24 44274758 ps
T785 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3789577581 Jan 07 12:35:04 PM PST 24 Jan 07 12:36:25 PM PST 24 130273313 ps
T786 /workspace/coverage/cover_reg_top/17.edn_intr_test.801527644 Jan 07 12:28:52 PM PST 24 Jan 07 12:30:49 PM PST 24 60240125 ps
T787 /workspace/coverage/cover_reg_top/5.edn_tl_errors.714401995 Jan 07 12:26:19 PM PST 24 Jan 07 12:27:24 PM PST 24 24629977 ps
T202 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3504975913 Jan 07 12:29:50 PM PST 24 Jan 07 12:31:41 PM PST 24 1084860144 ps
T788 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2098133259 Jan 07 12:35:33 PM PST 24 Jan 07 12:36:47 PM PST 24 70815732 ps
T173 /workspace/coverage/cover_reg_top/18.edn_csr_rw.1331994846 Jan 07 12:26:30 PM PST 24 Jan 07 12:27:43 PM PST 24 14543392 ps
T182 /workspace/coverage/cover_reg_top/11.edn_intr_test.954108487 Jan 07 12:26:28 PM PST 24 Jan 07 12:27:36 PM PST 24 31916725 ps
T183 /workspace/coverage/cover_reg_top/29.edn_intr_test.240854109 Jan 07 12:36:12 PM PST 24 Jan 07 12:37:20 PM PST 24 15834151 ps
T184 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3189923295 Jan 07 12:31:29 PM PST 24 Jan 07 12:32:48 PM PST 24 101367539 ps
T789 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.118737583 Jan 07 12:25:48 PM PST 24 Jan 07 12:26:49 PM PST 24 102339032 ps
T790 /workspace/coverage/cover_reg_top/19.edn_intr_test.1675189018 Jan 07 12:26:21 PM PST 24 Jan 07 12:27:27 PM PST 24 15046525 ps
T791 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3547861771 Jan 07 12:26:28 PM PST 24 Jan 07 12:27:39 PM PST 24 22975458 ps
T175 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.863893354 Jan 07 12:34:13 PM PST 24 Jan 07 12:35:41 PM PST 24 57568657 ps
T792 /workspace/coverage/cover_reg_top/49.edn_intr_test.1074530440 Jan 07 12:30:01 PM PST 24 Jan 07 12:31:47 PM PST 24 21484998 ps
T793 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3527832727 Jan 07 12:26:17 PM PST 24 Jan 07 12:27:21 PM PST 24 26418405 ps
T794 /workspace/coverage/cover_reg_top/32.edn_intr_test.702611755 Jan 07 12:23:53 PM PST 24 Jan 07 12:24:08 PM PST 24 23309616 ps
T795 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.499287458 Jan 07 12:24:42 PM PST 24 Jan 07 12:25:45 PM PST 24 113336770 ps
T796 /workspace/coverage/cover_reg_top/23.edn_intr_test.279586875 Jan 07 12:23:50 PM PST 24 Jan 07 12:24:02 PM PST 24 74914183 ps
T797 /workspace/coverage/cover_reg_top/31.edn_intr_test.2438281089 Jan 07 12:26:20 PM PST 24 Jan 07 12:27:24 PM PST 24 47623284 ps
T204 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.409368334 Jan 07 12:26:29 PM PST 24 Jan 07 12:27:40 PM PST 24 281750017 ps
T798 /workspace/coverage/cover_reg_top/0.edn_tl_errors.1003230118 Jan 07 12:26:27 PM PST 24 Jan 07 12:27:36 PM PST 24 32674842 ps
T799 /workspace/coverage/cover_reg_top/34.edn_intr_test.2759934314 Jan 07 12:37:03 PM PST 24 Jan 07 12:38:10 PM PST 24 14143838 ps
T800 /workspace/coverage/cover_reg_top/36.edn_intr_test.725181893 Jan 07 12:29:36 PM PST 24 Jan 07 12:31:19 PM PST 24 19605349 ps
T801 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.87161921 Jan 07 12:26:08 PM PST 24 Jan 07 12:27:10 PM PST 24 110336930 ps
T802 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2915038589 Jan 07 12:26:14 PM PST 24 Jan 07 12:27:18 PM PST 24 339773493 ps
T803 /workspace/coverage/cover_reg_top/13.edn_intr_test.3323854766 Jan 07 12:26:24 PM PST 24 Jan 07 12:27:30 PM PST 24 41733819 ps
T804 /workspace/coverage/cover_reg_top/0.edn_intr_test.1206788066 Jan 07 12:26:29 PM PST 24 Jan 07 12:27:38 PM PST 24 13250912 ps
T805 /workspace/coverage/cover_reg_top/12.edn_intr_test.2340052629 Jan 07 12:26:11 PM PST 24 Jan 07 12:27:13 PM PST 24 33785733 ps
T806 /workspace/coverage/cover_reg_top/12.edn_tl_errors.3730631423 Jan 07 12:26:21 PM PST 24 Jan 07 12:27:27 PM PST 24 113197661 ps
T807 /workspace/coverage/cover_reg_top/37.edn_intr_test.2376855055 Jan 07 12:25:45 PM PST 24 Jan 07 12:26:44 PM PST 24 13145706 ps
T808 /workspace/coverage/cover_reg_top/19.edn_csr_rw.7646018 Jan 07 12:25:52 PM PST 24 Jan 07 12:26:54 PM PST 24 33070290 ps
T809 /workspace/coverage/cover_reg_top/4.edn_csr_rw.82631936 Jan 07 12:30:19 PM PST 24 Jan 07 12:31:57 PM PST 24 15450614 ps
T810 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.4021198651 Jan 07 12:23:38 PM PST 24 Jan 07 12:23:46 PM PST 24 62974579 ps
T811 /workspace/coverage/cover_reg_top/38.edn_intr_test.3245334442 Jan 07 12:27:05 PM PST 24 Jan 07 12:28:25 PM PST 24 46789058 ps
T812 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2363555220 Jan 07 12:26:20 PM PST 24 Jan 07 12:27:24 PM PST 24 18575617 ps
T813 /workspace/coverage/cover_reg_top/14.edn_csr_rw.2169723076 Jan 07 12:26:27 PM PST 24 Jan 07 12:27:35 PM PST 24 15232381 ps
T814 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1922125423 Jan 07 12:31:31 PM PST 24 Jan 07 12:33:01 PM PST 24 96376327 ps
T815 /workspace/coverage/cover_reg_top/17.edn_csr_rw.1305587517 Jan 07 12:26:04 PM PST 24 Jan 07 12:27:02 PM PST 24 50984370 ps
T174 /workspace/coverage/cover_reg_top/15.edn_csr_rw.3473945758 Jan 07 12:23:10 PM PST 24 Jan 07 12:23:16 PM PST 24 26490470 ps
T176 /workspace/coverage/cover_reg_top/16.edn_csr_rw.3312823566 Jan 07 12:29:49 PM PST 24 Jan 07 12:31:15 PM PST 24 15165089 ps
T816 /workspace/coverage/cover_reg_top/1.edn_intr_test.1322964542 Jan 07 12:29:13 PM PST 24 Jan 07 12:30:43 PM PST 24 48358810 ps
T203 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2864761098 Jan 07 12:26:29 PM PST 24 Jan 07 12:27:40 PM PST 24 163236943 ps
T817 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2445461438 Jan 07 12:26:05 PM PST 24 Jan 07 12:27:18 PM PST 24 21698337 ps
T818 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2342246087 Jan 07 12:26:34 PM PST 24 Jan 07 12:27:47 PM PST 24 75137940 ps
T819 /workspace/coverage/cover_reg_top/47.edn_intr_test.2704092409 Jan 07 12:29:05 PM PST 24 Jan 07 12:31:00 PM PST 24 17101895 ps
T820 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.4087524324 Jan 07 12:26:19 PM PST 24 Jan 07 12:27:23 PM PST 24 140198072 ps
T821 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3242484222 Jan 07 12:30:33 PM PST 24 Jan 07 12:32:38 PM PST 24 117412726 ps
T822 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2923570801 Jan 07 12:26:17 PM PST 24 Jan 07 12:27:21 PM PST 24 57456238 ps
T823 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.4051178016 Jan 07 12:31:27 PM PST 24 Jan 07 12:33:14 PM PST 24 36626806 ps

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2174713168
Short name T20
Test name
Test status
Simulation time 335231768 ps
CPU time 2.25 seconds
Started Jan 07 12:29:31 PM PST 24
Finished Jan 07 12:31:06 PM PST 24
Peak memory 205612 kb
Host smart-0a7f6589-f574-4dea-84b2-665089e195dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174713168 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.2174713168
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/default/225.edn_genbits.4120604385
Short name T1
Test name
Test status
Simulation time 15088664 ps
CPU time 1.01 seconds
Started Jan 07 12:42:36 PM PST 24
Finished Jan 07 12:44:03 PM PST 24
Peak memory 214224 kb
Host smart-fd42d5e8-384b-423f-a45a-8774c03ed374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120604385 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.4120604385
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.3602441053
Short name T47
Test name
Test status
Simulation time 342424893063 ps
CPU time 1150.34 seconds
Started Jan 07 12:40:55 PM PST 24
Finished Jan 07 01:01:07 PM PST 24
Peak memory 218452 kb
Host smart-c3859763-3855-4900-9d10-74ef8efa29ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602441053 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.3602441053
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/277.edn_genbits.1335071990
Short name T54
Test name
Test status
Simulation time 29311789 ps
CPU time 1.33 seconds
Started Jan 07 12:43:06 PM PST 24
Finished Jan 07 12:44:45 PM PST 24
Peak memory 214180 kb
Host smart-fa975384-338d-40ad-a67a-071635e834af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335071990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.1335071990
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_err.4019793619
Short name T15
Test name
Test status
Simulation time 21630171 ps
CPU time 0.97 seconds
Started Jan 07 12:40:00 PM PST 24
Finished Jan 07 12:41:09 PM PST 24
Peak memory 221720 kb
Host smart-0d050f02-e01b-4add-8c2e-445b16390797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019793619 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.4019793619
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.794483314
Short name T2
Test name
Test status
Simulation time 77887783 ps
CPU time 1.01 seconds
Started Jan 07 12:40:44 PM PST 24
Finished Jan 07 12:42:25 PM PST 24
Peak memory 214508 kb
Host smart-4b842c7b-dc73-494e-951d-88cfc77f9bee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794483314 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_di
sable_auto_req_mode.794483314
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_sec_cm.3922980014
Short name T30
Test name
Test status
Simulation time 471679769 ps
CPU time 3.2 seconds
Started Jan 07 12:39:48 PM PST 24
Finished Jan 07 12:41:11 PM PST 24
Peak memory 231772 kb
Host smart-6076ad3e-a5eb-4a21-8f36-8aac610a0957
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922980014 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.3922980014
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.2229673849
Short name T27
Test name
Test status
Simulation time 196115943 ps
CPU time 0.86 seconds
Started Jan 07 12:31:12 PM PST 24
Finished Jan 07 12:32:54 PM PST 24
Peak memory 205148 kb
Host smart-a4ac0d42-846d-49d4-a6e1-2f8b66403c8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229673849 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.2229673849
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.2989169042
Short name T82
Test name
Test status
Simulation time 651415047649 ps
CPU time 2188.35 seconds
Started Jan 07 12:41:19 PM PST 24
Finished Jan 07 01:19:29 PM PST 24
Peak memory 221180 kb
Host smart-0a2bbbb3-bfc2-4ee4-a725-af77643dbd5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989169042 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.2989169042
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2349757854
Short name T143
Test name
Test status
Simulation time 209450237 ps
CPU time 1.55 seconds
Started Jan 07 12:26:21 PM PST 24
Finished Jan 07 12:27:27 PM PST 24
Peak memory 205608 kb
Host smart-645dd530-3fb5-482b-94d7-83d921b28dbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349757854 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2349757854
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/default/3.edn_intr.213779533
Short name T115
Test name
Test status
Simulation time 29696728 ps
CPU time 0.81 seconds
Started Jan 07 12:40:35 PM PST 24
Finished Jan 07 12:41:38 PM PST 24
Peak memory 214456 kb
Host smart-c7c59f85-602a-45e2-aa9e-aed4ab0c7ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213779533 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.213779533
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/45.edn_alert.2729759318
Short name T196
Test name
Test status
Simulation time 24889387 ps
CPU time 0.94 seconds
Started Jan 07 12:41:05 PM PST 24
Finished Jan 07 12:42:14 PM PST 24
Peak memory 205980 kb
Host smart-e20950df-be01-4ae5-944e-2653b9b13443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729759318 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.2729759318
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/78.edn_genbits.2145236382
Short name T55
Test name
Test status
Simulation time 50523973 ps
CPU time 0.93 seconds
Started Jan 07 12:41:46 PM PST 24
Finished Jan 07 12:43:12 PM PST 24
Peak memory 205532 kb
Host smart-993fb1ed-4419-4e09-8ec3-213ab94e4bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145236382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.2145236382
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_regwen.2869095898
Short name T218
Test name
Test status
Simulation time 118522442 ps
CPU time 0.82 seconds
Started Jan 07 12:40:05 PM PST 24
Finished Jan 07 12:41:55 PM PST 24
Peak memory 204812 kb
Host smart-28194d94-5899-4079-93a5-931d59c1c9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869095898 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.2869095898
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.2415980583
Short name T41
Test name
Test status
Simulation time 150843474 ps
CPU time 1.01 seconds
Started Jan 07 12:40:39 PM PST 24
Finished Jan 07 12:41:37 PM PST 24
Peak memory 214388 kb
Host smart-1eb0e6d7-1308-4cd4-a51a-a212f23df5dc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415980583 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.2415980583
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/67.edn_genbits.1320097042
Short name T12
Test name
Test status
Simulation time 48852509 ps
CPU time 1.2 seconds
Started Jan 07 12:41:22 PM PST 24
Finished Jan 07 12:42:39 PM PST 24
Peak memory 214116 kb
Host smart-d04509d8-01a4-4f4c-a016-49c29010bf19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320097042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.1320097042
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.4163406085
Short name T48
Test name
Test status
Simulation time 55918922 ps
CPU time 2.16 seconds
Started Jan 07 12:41:15 PM PST 24
Finished Jan 07 12:42:29 PM PST 24
Peak memory 214144 kb
Host smart-d2ca5444-5ad0-466e-9c1e-b82943004591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163406085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.4163406085
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.3803105627
Short name T117
Test name
Test status
Simulation time 18216927 ps
CPU time 1.03 seconds
Started Jan 07 12:40:06 PM PST 24
Finished Jan 07 12:41:09 PM PST 24
Peak memory 214520 kb
Host smart-d942e447-c839-4f83-b38b-22dfa18c7ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803105627 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3803105627
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.370558895
Short name T171
Test name
Test status
Simulation time 12802917 ps
CPU time 0.87 seconds
Started Jan 07 12:28:34 PM PST 24
Finished Jan 07 12:30:23 PM PST 24
Peak memory 205620 kb
Host smart-9b52f2a1-50eb-40db-91a0-c7820244e8ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370558895 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.370558895
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/default/197.edn_genbits.2063178360
Short name T238
Test name
Test status
Simulation time 15341029 ps
CPU time 0.9 seconds
Started Jan 07 12:42:35 PM PST 24
Finished Jan 07 12:43:47 PM PST 24
Peak memory 205028 kb
Host smart-e68e2f78-c037-4222-a1cd-dc5e1db0b1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063178360 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.2063178360
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1173609366
Short name T146
Test name
Test status
Simulation time 165507008 ps
CPU time 1.1 seconds
Started Jan 07 12:29:12 PM PST 24
Finished Jan 07 12:30:36 PM PST 24
Peak memory 205644 kb
Host smart-87cab3fd-8c1f-452f-a385-9a3fff20d49d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173609366 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.1173609366
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/default/99.edn_genbits.4273819868
Short name T87
Test name
Test status
Simulation time 16433423 ps
CPU time 1 seconds
Started Jan 07 12:41:21 PM PST 24
Finished Jan 07 12:43:13 PM PST 24
Peak memory 205504 kb
Host smart-2dd8fef2-3a10-4b39-8b64-c108568aa110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273819868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.4273819868
Directory /workspace/99.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.1640196685
Short name T122
Test name
Test status
Simulation time 210509277798 ps
CPU time 2572.93 seconds
Started Jan 07 12:40:00 PM PST 24
Finished Jan 07 01:24:04 PM PST 24
Peak memory 227584 kb
Host smart-d3800cf3-2e2c-4351-8dac-535f2a9c000c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640196685 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.1640196685
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_regwen.4150572229
Short name T225
Test name
Test status
Simulation time 26186055 ps
CPU time 0.83 seconds
Started Jan 07 12:40:38 PM PST 24
Finished Jan 07 12:41:59 PM PST 24
Peak memory 204712 kb
Host smart-0a872cd2-5fcf-4961-a10a-2e95a945512b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150572229 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.4150572229
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/28.edn_disable.3926824899
Short name T90
Test name
Test status
Simulation time 16916631 ps
CPU time 0.87 seconds
Started Jan 07 12:40:59 PM PST 24
Finished Jan 07 12:42:53 PM PST 24
Peak memory 214468 kb
Host smart-894edca7-81ad-4777-a55f-dba51a2dffef
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926824899 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.3926824899
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/11.edn_alert.1494094009
Short name T228
Test name
Test status
Simulation time 50741794 ps
CPU time 0.98 seconds
Started Jan 07 12:40:31 PM PST 24
Finished Jan 07 12:41:55 PM PST 24
Peak memory 205968 kb
Host smart-3cf9ed97-64d2-4a44-a9a4-c3b6dd64981f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494094009 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.1494094009
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert.4105897540
Short name T694
Test name
Test status
Simulation time 65356948 ps
CPU time 0.93 seconds
Started Jan 07 12:40:21 PM PST 24
Finished Jan 07 12:41:27 PM PST 24
Peak memory 205960 kb
Host smart-45e19e05-b368-4eaf-872a-5cdf00807915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105897540 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.4105897540
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert.2013915141
Short name T234
Test name
Test status
Simulation time 109769446 ps
CPU time 0.94 seconds
Started Jan 07 12:40:03 PM PST 24
Finished Jan 07 12:41:59 PM PST 24
Peak memory 205128 kb
Host smart-1b565c7e-4f95-45f1-9e26-59e116e92515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013915141 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.2013915141
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.3169936471
Short name T208
Test name
Test status
Simulation time 61304600 ps
CPU time 0.94 seconds
Started Jan 07 12:41:24 PM PST 24
Finished Jan 07 12:43:10 PM PST 24
Peak memory 205108 kb
Host smart-ad64e97f-7c17-4f09-8cdf-3959dc45673e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169936471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.3169936471
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.1365199270
Short name T279
Test name
Test status
Simulation time 94365949 ps
CPU time 2.07 seconds
Started Jan 07 12:42:36 PM PST 24
Finished Jan 07 12:44:02 PM PST 24
Peak memory 214160 kb
Host smart-ae91eb71-11ff-48a1-9fcf-ad5ac5dba8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365199270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.1365199270
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.2176313489
Short name T250
Test name
Test status
Simulation time 40906494 ps
CPU time 0.97 seconds
Started Jan 07 12:41:51 PM PST 24
Finished Jan 07 12:43:16 PM PST 24
Peak memory 205520 kb
Host smart-ff92ff62-d295-4584-88fd-d7a7ff7fb840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176313489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.2176313489
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.1748227904
Short name T521
Test name
Test status
Simulation time 75362276 ps
CPU time 1.05 seconds
Started Jan 07 12:42:03 PM PST 24
Finished Jan 07 12:43:25 PM PST 24
Peak memory 205184 kb
Host smart-ed848993-7eb6-4282-ae11-458920818e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748227904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.1748227904
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.332754820
Short name T246
Test name
Test status
Simulation time 217525192 ps
CPU time 2.35 seconds
Started Jan 07 12:42:34 PM PST 24
Finished Jan 07 12:44:09 PM PST 24
Peak memory 214084 kb
Host smart-108ca062-3424-41b7-a020-255be2b1bb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332754820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.332754820
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.1035084775
Short name T277
Test name
Test status
Simulation time 22101810 ps
CPU time 0.89 seconds
Started Jan 07 12:42:08 PM PST 24
Finished Jan 07 12:43:33 PM PST 24
Peak memory 205052 kb
Host smart-7543ba62-30d6-4d82-95e4-032d844109e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035084775 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.1035084775
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_stress_all.3445580265
Short name T71
Test name
Test status
Simulation time 40521457 ps
CPU time 1.3 seconds
Started Jan 07 12:41:12 PM PST 24
Finished Jan 07 12:42:44 PM PST 24
Peak memory 205596 kb
Host smart-493c72f0-ec16-4a99-8ec3-16cf14be9b8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445580265 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.3445580265
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/57.edn_err.829613082
Short name T116
Test name
Test status
Simulation time 26253326 ps
CPU time 1.26 seconds
Started Jan 07 12:41:45 PM PST 24
Finished Jan 07 12:43:34 PM PST 24
Peak memory 228324 kb
Host smart-911a9fc6-6956-4dd2-a449-90161dc6aedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829613082 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.829613082
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/8.edn_regwen.3073088202
Short name T201
Test name
Test status
Simulation time 57295275 ps
CPU time 0.8 seconds
Started Jan 07 12:40:32 PM PST 24
Finished Jan 07 12:41:38 PM PST 24
Peak memory 204928 kb
Host smart-fd0297ef-550c-430c-9dfe-ae44aada1a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073088202 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.3073088202
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_alert_test.1390647963
Short name T76
Test name
Test status
Simulation time 35394645 ps
CPU time 0.78 seconds
Started Jan 07 12:40:06 PM PST 24
Finished Jan 07 12:41:30 PM PST 24
Peak memory 204456 kb
Host smart-770adebf-4b46-4031-82aa-0ec1bc8dd613
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390647963 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.1390647963
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_err.3687556487
Short name T8
Test name
Test status
Simulation time 23659009 ps
CPU time 1.11 seconds
Started Jan 07 12:40:50 PM PST 24
Finished Jan 07 12:42:42 PM PST 24
Peak memory 214528 kb
Host smart-59980b19-3a89-4cdb-a649-be3f6f946445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687556487 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.3687556487
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/14.edn_intr.1827865819
Short name T118
Test name
Test status
Simulation time 19120954 ps
CPU time 1 seconds
Started Jan 07 12:40:11 PM PST 24
Finished Jan 07 12:41:38 PM PST 24
Peak memory 225504 kb
Host smart-f851b1a5-1236-4591-bb53-a2181f6dff7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827865819 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.1827865819
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.144602885
Short name T163
Test name
Test status
Simulation time 224776367 ps
CPU time 1.42 seconds
Started Jan 07 12:26:27 PM PST 24
Finished Jan 07 12:27:40 PM PST 24
Peak memory 205524 kb
Host smart-c8b3e2b5-ea33-4c96-a96a-f278ce9a12bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144602885 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.144602885
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/default/100.edn_genbits.4052789215
Short name T263
Test name
Test status
Simulation time 82281731 ps
CPU time 0.99 seconds
Started Jan 07 12:41:29 PM PST 24
Finished Jan 07 12:43:18 PM PST 24
Peak memory 205560 kb
Host smart-7a3b172a-b32e-4c1a-ad15-b822a073e25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052789215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.4052789215
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.1384160534
Short name T709
Test name
Test status
Simulation time 14093126 ps
CPU time 0.92 seconds
Started Jan 07 12:42:00 PM PST 24
Finished Jan 07 12:43:30 PM PST 24
Peak memory 205352 kb
Host smart-807d30e6-963c-4219-ae00-19795fced622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384160534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.1384160534
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_stress_all.1994396972
Short name T692
Test name
Test status
Simulation time 84475124 ps
CPU time 1.91 seconds
Started Jan 07 12:40:46 PM PST 24
Finished Jan 07 12:42:29 PM PST 24
Peak memory 205528 kb
Host smart-825b4923-e8f1-46c0-80fb-d38808136043
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994396972 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1994396972
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/114.edn_genbits.163817104
Short name T251
Test name
Test status
Simulation time 35849633 ps
CPU time 0.94 seconds
Started Jan 07 12:42:18 PM PST 24
Finished Jan 07 12:44:01 PM PST 24
Peak memory 214340 kb
Host smart-0ae94e83-59f1-4837-9b2d-b2c37c03f2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163817104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.163817104
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.1799715189
Short name T274
Test name
Test status
Simulation time 23645749 ps
CPU time 0.87 seconds
Started Jan 07 12:41:30 PM PST 24
Finished Jan 07 12:42:41 PM PST 24
Peak memory 205084 kb
Host smart-3b81a9ec-0c0d-4a33-a0af-ed302d2dac01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799715189 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.1799715189
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.3503167937
Short name T571
Test name
Test status
Simulation time 18231652 ps
CPU time 1.06 seconds
Started Jan 07 12:42:09 PM PST 24
Finished Jan 07 12:43:35 PM PST 24
Peak memory 205156 kb
Host smart-589e96f2-b879-4436-9737-537dac97ea71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503167937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.3503167937
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.3707313719
Short name T259
Test name
Test status
Simulation time 24658783 ps
CPU time 0.93 seconds
Started Jan 07 12:42:16 PM PST 24
Finished Jan 07 12:43:58 PM PST 24
Peak memory 204956 kb
Host smart-a4acfec1-e310-4fb3-922b-e3c87183cba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707313719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.3707313719
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.1409300726
Short name T242
Test name
Test status
Simulation time 33345311 ps
CPU time 1.51 seconds
Started Jan 07 12:42:06 PM PST 24
Finished Jan 07 12:43:38 PM PST 24
Peak memory 214312 kb
Host smart-0637cb72-5899-4b47-a075-90708da565e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409300726 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.1409300726
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.257509083
Short name T269
Test name
Test status
Simulation time 30221465 ps
CPU time 1.1 seconds
Started Jan 07 12:42:06 PM PST 24
Finished Jan 07 12:43:33 PM PST 24
Peak memory 205776 kb
Host smart-7b69756c-82fb-4927-be1b-0b613241d18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257509083 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.257509083
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.2940130777
Short name T99
Test name
Test status
Simulation time 20673893 ps
CPU time 1.14 seconds
Started Jan 07 12:42:40 PM PST 24
Finished Jan 07 12:44:29 PM PST 24
Peak memory 205288 kb
Host smart-45d826a5-1f9e-4259-b1f2-9d68c9ffc038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940130777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.2940130777
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.2482379095
Short name T382
Test name
Test status
Simulation time 138322571 ps
CPU time 0.88 seconds
Started Jan 07 12:41:04 PM PST 24
Finished Jan 07 12:42:28 PM PST 24
Peak memory 205256 kb
Host smart-75c995e6-9866-4f70-8870-6ea8b36e117d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482379095 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.2482379095
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/54.edn_genbits.2906207384
Short name T271
Test name
Test status
Simulation time 47007502 ps
CPU time 0.88 seconds
Started Jan 07 12:41:48 PM PST 24
Finished Jan 07 12:43:19 PM PST 24
Peak memory 205396 kb
Host smart-5cb25d92-edad-4ca5-8826-010c6107ab85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906207384 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.2906207384
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.815963736
Short name T112
Test name
Test status
Simulation time 38834143 ps
CPU time 0.78 seconds
Started Jan 07 12:40:26 PM PST 24
Finished Jan 07 12:41:26 PM PST 24
Peak memory 214388 kb
Host smart-18c9d8ed-f714-4d80-b8de-afd16e1acb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815963736 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.815963736
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/0.edn_disable.3464380981
Short name T136
Test name
Test status
Simulation time 11757943 ps
CPU time 0.85 seconds
Started Jan 07 12:39:37 PM PST 24
Finished Jan 07 12:40:51 PM PST 24
Peak memory 214708 kb
Host smart-365c3025-a6e7-4f47-8405-cabc362c34bb
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464380981 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.3464380981
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable.661659154
Short name T130
Test name
Test status
Simulation time 10832158 ps
CPU time 0.81 seconds
Started Jan 07 12:39:32 PM PST 24
Finished Jan 07 12:40:55 PM PST 24
Peak memory 214332 kb
Host smart-f0a62704-58f5-4040-b742-c4d45b940ced
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661659154 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.661659154
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.2224681914
Short name T737
Test name
Test status
Simulation time 82380388 ps
CPU time 1.02 seconds
Started Jan 07 12:40:44 PM PST 24
Finished Jan 07 12:41:42 PM PST 24
Peak memory 214656 kb
Host smart-983e71ec-e10f-453e-be0f-e78e2ee74d3a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224681914 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.2224681914
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_disable.3029225664
Short name T140
Test name
Test status
Simulation time 13855880 ps
CPU time 0.88 seconds
Started Jan 07 12:41:03 PM PST 24
Finished Jan 07 12:42:29 PM PST 24
Peak memory 214608 kb
Host smart-56c62652-ad71-40da-92d6-c49a066b04e7
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029225664 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3029225664
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable.323388301
Short name T131
Test name
Test status
Simulation time 36481401 ps
CPU time 0.82 seconds
Started Jan 07 12:40:16 PM PST 24
Finished Jan 07 12:41:48 PM PST 24
Peak memory 214504 kb
Host smart-c6b1f1f5-2420-4a98-84ce-b2afcd77dc64
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323388301 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.323388301
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable.1480886414
Short name T137
Test name
Test status
Simulation time 31822034 ps
CPU time 0.78 seconds
Started Jan 07 12:41:32 PM PST 24
Finished Jan 07 12:43:11 PM PST 24
Peak memory 214292 kb
Host smart-cfff60fa-d0aa-495a-926d-8f66eac86151
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480886414 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.1480886414
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/117.edn_genbits.3033188125
Short name T630
Test name
Test status
Simulation time 33526675 ps
CPU time 1.27 seconds
Started Jan 07 12:41:47 PM PST 24
Finished Jan 07 12:43:14 PM PST 24
Peak memory 214096 kb
Host smart-eb47c9a9-f351-4e7b-b181-53c2ce8a9b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033188125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.3033188125
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1611269952
Short name T166
Test name
Test status
Simulation time 141684354 ps
CPU time 1.06 seconds
Started Jan 07 12:35:15 PM PST 24
Finished Jan 07 12:37:06 PM PST 24
Peak memory 205604 kb
Host smart-9e03e119-d415-4e15-a185-36dd4fe227d9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611269952 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.1611269952
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.328618030
Short name T763
Test name
Test status
Simulation time 28216502 ps
CPU time 0.8 seconds
Started Jan 07 12:29:13 PM PST 24
Finished Jan 07 12:30:43 PM PST 24
Peak memory 205436 kb
Host smart-31c49695-9e2a-40c0-8fe6-fa813e95be16
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328618030 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.328618030
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3789577581
Short name T785
Test name
Test status
Simulation time 130273313 ps
CPU time 1.93 seconds
Started Jan 07 12:35:04 PM PST 24
Finished Jan 07 12:36:25 PM PST 24
Peak memory 213332 kb
Host smart-bc51a3b3-0f79-41ae-9768-572b671949b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789577581 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.3789577581
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.53868300
Short name T162
Test name
Test status
Simulation time 13312450 ps
CPU time 0.85 seconds
Started Jan 07 12:24:27 PM PST 24
Finished Jan 07 12:25:03 PM PST 24
Peak memory 206028 kb
Host smart-5879a5d1-871c-4042-b028-e6a320779f7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53868300 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.53868300
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.1206788066
Short name T804
Test name
Test status
Simulation time 13250912 ps
CPU time 0.81 seconds
Started Jan 07 12:26:29 PM PST 24
Finished Jan 07 12:27:38 PM PST 24
Peak memory 205596 kb
Host smart-a21514e7-086d-4bcf-a6e5-13f47b4d4cf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206788066 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1206788066
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.1003230118
Short name T798
Test name
Test status
Simulation time 32674842 ps
CPU time 1.98 seconds
Started Jan 07 12:26:27 PM PST 24
Finished Jan 07 12:27:36 PM PST 24
Peak memory 217036 kb
Host smart-4ab11349-4098-4cc0-ad19-32306586cd4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003230118 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.1003230118
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.4087524324
Short name T820
Test name
Test status
Simulation time 140198072 ps
CPU time 1.28 seconds
Started Jan 07 12:26:19 PM PST 24
Finished Jan 07 12:27:23 PM PST 24
Peak memory 205652 kb
Host smart-2bbb648d-241d-4867-96fd-79937db6cb8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087524324 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.4087524324
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.863893354
Short name T175
Test name
Test status
Simulation time 57568657 ps
CPU time 3.02 seconds
Started Jan 07 12:34:13 PM PST 24
Finished Jan 07 12:35:41 PM PST 24
Peak memory 205632 kb
Host smart-63078fca-4b38-47ed-931a-52b3e1437878
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863893354 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.863893354
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.4021198651
Short name T810
Test name
Test status
Simulation time 62974579 ps
CPU time 0.82 seconds
Started Jan 07 12:23:38 PM PST 24
Finished Jan 07 12:23:46 PM PST 24
Peak memory 205652 kb
Host smart-147b0f81-ae42-4935-a437-bdf84421ff08
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021198651 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.4021198651
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2342246087
Short name T818
Test name
Test status
Simulation time 75137940 ps
CPU time 1.07 seconds
Started Jan 07 12:26:34 PM PST 24
Finished Jan 07 12:27:47 PM PST 24
Peak memory 213904 kb
Host smart-759d7beb-7806-4e0a-b714-669111ed3d6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342246087 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.2342246087
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.442699816
Short name T191
Test name
Test status
Simulation time 37137124 ps
CPU time 0.8 seconds
Started Jan 07 12:26:27 PM PST 24
Finished Jan 07 12:27:35 PM PST 24
Peak memory 205408 kb
Host smart-58e50487-9ec0-4f29-b402-292a8e9b22ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442699816 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.442699816
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.1322964542
Short name T816
Test name
Test status
Simulation time 48358810 ps
CPU time 0.8 seconds
Started Jan 07 12:29:13 PM PST 24
Finished Jan 07 12:30:43 PM PST 24
Peak memory 205616 kb
Host smart-1fd7867b-a20b-49e1-9569-e40e930ef5bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322964542 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.1322964542
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3507077690
Short name T782
Test name
Test status
Simulation time 344147743 ps
CPU time 2.2 seconds
Started Jan 07 12:29:31 PM PST 24
Finished Jan 07 12:31:06 PM PST 24
Peak memory 205432 kb
Host smart-0bb68f76-cded-4a62-b689-b868f3462f5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507077690 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.3507077690
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2246174412
Short name T33
Test name
Test status
Simulation time 45792848 ps
CPU time 0.92 seconds
Started Jan 07 12:29:36 PM PST 24
Finished Jan 07 12:31:09 PM PST 24
Peak memory 213904 kb
Host smart-f8b18970-aa5b-4e94-bf2f-41f93c7dcbda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246174412 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.2246174412
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.465431367
Short name T160
Test name
Test status
Simulation time 42942266 ps
CPU time 0.83 seconds
Started Jan 07 12:32:50 PM PST 24
Finished Jan 07 12:34:02 PM PST 24
Peak memory 205456 kb
Host smart-129851e7-7264-48f1-b223-1c53475953c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465431367 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.465431367
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.873576914
Short name T62
Test name
Test status
Simulation time 53590894 ps
CPU time 0.84 seconds
Started Jan 07 12:23:36 PM PST 24
Finished Jan 07 12:23:44 PM PST 24
Peak memory 206032 kb
Host smart-78c7e0fa-125c-4057-9921-363ca81d1dd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873576914 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.873576914
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.1361752902
Short name T777
Test name
Test status
Simulation time 175204732 ps
CPU time 3.11 seconds
Started Jan 07 12:32:21 PM PST 24
Finished Jan 07 12:34:05 PM PST 24
Peak memory 213936 kb
Host smart-afd0de23-95b6-46d6-8da9-b5dda5814fd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361752902 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.1361752902
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1922125423
Short name T814
Test name
Test status
Simulation time 96376327 ps
CPU time 1.45 seconds
Started Jan 07 12:31:31 PM PST 24
Finished Jan 07 12:33:01 PM PST 24
Peak memory 205304 kb
Host smart-11efdac8-7b57-40b0-9593-e44b7468cbef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922125423 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.1922125423
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.4175603690
Short name T779
Test name
Test status
Simulation time 118470344 ps
CPU time 1.07 seconds
Started Jan 07 12:26:22 PM PST 24
Finished Jan 07 12:27:27 PM PST 24
Peak memory 213872 kb
Host smart-e1b8d5e4-44fb-4a8f-9e23-626c4ea71984
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175603690 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.4175603690
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.954108487
Short name T182
Test name
Test status
Simulation time 31916725 ps
CPU time 0.74 seconds
Started Jan 07 12:26:28 PM PST 24
Finished Jan 07 12:27:36 PM PST 24
Peak memory 205332 kb
Host smart-7b466e7d-7d91-4b95-a252-057acb8cf711
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954108487 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.954108487
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1775975443
Short name T187
Test name
Test status
Simulation time 58944817 ps
CPU time 1.33 seconds
Started Jan 07 12:26:27 PM PST 24
Finished Jan 07 12:27:40 PM PST 24
Peak memory 205604 kb
Host smart-ea7431b0-a03f-4877-afe0-d35dcfa34ac6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775975443 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.1775975443
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.602576697
Short name T778
Test name
Test status
Simulation time 148254348 ps
CPU time 1.42 seconds
Started Jan 07 12:29:09 PM PST 24
Finished Jan 07 12:30:27 PM PST 24
Peak memory 205532 kb
Host smart-c9441377-66dc-4942-9eb2-40e1e3427266
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602576697 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.602576697
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.2340052629
Short name T805
Test name
Test status
Simulation time 33785733 ps
CPU time 0.8 seconds
Started Jan 07 12:26:11 PM PST 24
Finished Jan 07 12:27:13 PM PST 24
Peak memory 204616 kb
Host smart-da909a0c-c62d-4ae9-91bd-405dc40bec79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340052629 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.2340052629
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3242484222
Short name T821
Test name
Test status
Simulation time 117412726 ps
CPU time 1.3 seconds
Started Jan 07 12:30:33 PM PST 24
Finished Jan 07 12:32:38 PM PST 24
Peak memory 205588 kb
Host smart-b6b3e910-ce42-4ef5-b575-c52246493c4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242484222 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.3242484222
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.3730631423
Short name T806
Test name
Test status
Simulation time 113197661 ps
CPU time 1.92 seconds
Started Jan 07 12:26:21 PM PST 24
Finished Jan 07 12:27:27 PM PST 24
Peak memory 213888 kb
Host smart-bdbf64de-c4d5-4cbd-80e3-98c9f4392ecd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730631423 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3730631423
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3527832727
Short name T793
Test name
Test status
Simulation time 26418405 ps
CPU time 1.26 seconds
Started Jan 07 12:26:17 PM PST 24
Finished Jan 07 12:27:21 PM PST 24
Peak memory 213860 kb
Host smart-2d86480e-0c30-40b7-abd4-cf8cc0adcc1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527832727 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.3527832727
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.3323854766
Short name T803
Test name
Test status
Simulation time 41733819 ps
CPU time 0.79 seconds
Started Jan 07 12:26:24 PM PST 24
Finished Jan 07 12:27:30 PM PST 24
Peak memory 205656 kb
Host smart-d03b83b1-f5e4-4178-b72e-8532efb23027
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323854766 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.3323854766
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.4194337156
Short name T26
Test name
Test status
Simulation time 383710221 ps
CPU time 3.19 seconds
Started Jan 07 12:26:05 PM PST 24
Finished Jan 07 12:27:09 PM PST 24
Peak memory 213792 kb
Host smart-f1eb6536-90e8-4f9f-9107-288269d8f8ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194337156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.4194337156
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.409368334
Short name T204
Test name
Test status
Simulation time 281750017 ps
CPU time 2.21 seconds
Started Jan 07 12:26:29 PM PST 24
Finished Jan 07 12:27:40 PM PST 24
Peak memory 205552 kb
Host smart-18c0bb99-5997-4f1e-9e9b-5ab362370af8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409368334 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.409368334
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1006690135
Short name T177
Test name
Test status
Simulation time 17805224 ps
CPU time 0.96 seconds
Started Jan 07 12:26:28 PM PST 24
Finished Jan 07 12:27:36 PM PST 24
Peak memory 213924 kb
Host smart-90fdd15a-8ddc-4faf-8100-1f7393971395
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006690135 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.1006690135
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.2169723076
Short name T813
Test name
Test status
Simulation time 15232381 ps
CPU time 0.84 seconds
Started Jan 07 12:26:27 PM PST 24
Finished Jan 07 12:27:35 PM PST 24
Peak memory 205600 kb
Host smart-aa823385-2309-4307-8b81-f1cc4b781bdc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169723076 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.2169723076
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.611046616
Short name T167
Test name
Test status
Simulation time 23230995 ps
CPU time 0.84 seconds
Started Jan 07 12:26:19 PM PST 24
Finished Jan 07 12:27:23 PM PST 24
Peak memory 205552 kb
Host smart-fe72d489-4241-44f1-8650-6d6fba68aae8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611046616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.611046616
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.4063502857
Short name T189
Test name
Test status
Simulation time 59796306 ps
CPU time 1.01 seconds
Started Jan 07 12:26:19 PM PST 24
Finished Jan 07 12:27:23 PM PST 24
Peak memory 205580 kb
Host smart-a6aec114-37c1-43f1-bb77-0104f3491fd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063502857 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.4063502857
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.4291345346
Short name T768
Test name
Test status
Simulation time 652477352 ps
CPU time 2.77 seconds
Started Jan 07 12:34:43 PM PST 24
Finished Jan 07 12:36:17 PM PST 24
Peak memory 214036 kb
Host smart-5f9164d4-055c-45ac-82b4-48d49e1b2b9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291345346 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.4291345346
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2585365851
Short name T198
Test name
Test status
Simulation time 99746287 ps
CPU time 1.5 seconds
Started Jan 07 12:31:28 PM PST 24
Finished Jan 07 12:33:07 PM PST 24
Peak memory 205516 kb
Host smart-59f5878a-424d-4190-8cf2-69e7957b2049
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585365851 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.2585365851
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.3601880175
Short name T22
Test name
Test status
Simulation time 37046171 ps
CPU time 1.31 seconds
Started Jan 07 12:25:37 PM PST 24
Finished Jan 07 12:26:41 PM PST 24
Peak memory 217196 kb
Host smart-fab7b593-6534-4580-807d-5d352f0d8390
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601880175 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.3601880175
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.3473945758
Short name T174
Test name
Test status
Simulation time 26490470 ps
CPU time 0.99 seconds
Started Jan 07 12:23:10 PM PST 24
Finished Jan 07 12:23:16 PM PST 24
Peak memory 204428 kb
Host smart-1befd0e8-d0e7-4cb2-ba1a-9e62db6ac01e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473945758 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.3473945758
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1646698051
Short name T180
Test name
Test status
Simulation time 33413346 ps
CPU time 1.28 seconds
Started Jan 07 12:29:49 PM PST 24
Finished Jan 07 12:31:55 PM PST 24
Peak memory 205608 kb
Host smart-2f2c5e19-c725-48ea-bb0a-34bad0597c6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646698051 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.1646698051
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.3216896320
Short name T185
Test name
Test status
Simulation time 149370131 ps
CPU time 2.61 seconds
Started Jan 07 12:34:11 PM PST 24
Finished Jan 07 12:36:03 PM PST 24
Peak memory 214020 kb
Host smart-904d6144-8291-48a3-833b-001b93fc01ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216896320 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.3216896320
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.87161921
Short name T801
Test name
Test status
Simulation time 110336930 ps
CPU time 1.35 seconds
Started Jan 07 12:26:08 PM PST 24
Finished Jan 07 12:27:10 PM PST 24
Peak memory 213944 kb
Host smart-dcaba78a-df33-4abc-9c4f-8c4e90968974
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87161921 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.87161921
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.3312823566
Short name T176
Test name
Test status
Simulation time 15165089 ps
CPU time 0.84 seconds
Started Jan 07 12:29:49 PM PST 24
Finished Jan 07 12:31:15 PM PST 24
Peak memory 205600 kb
Host smart-5647bb96-080b-4264-9060-4e7be4db7c80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312823566 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.3312823566
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.2235222167
Short name T179
Test name
Test status
Simulation time 105486434 ps
CPU time 3.28 seconds
Started Jan 07 12:28:36 PM PST 24
Finished Jan 07 12:29:49 PM PST 24
Peak memory 213924 kb
Host smart-f8f0c191-b608-4ec1-b456-a4d6728b68a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235222167 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.2235222167
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3508695795
Short name T169
Test name
Test status
Simulation time 156837511 ps
CPU time 2.1 seconds
Started Jan 07 12:35:17 PM PST 24
Finished Jan 07 12:36:34 PM PST 24
Peak memory 205636 kb
Host smart-13d9fbc1-e896-4913-b221-d342fdb85292
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508695795 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.3508695795
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2120402813
Short name T766
Test name
Test status
Simulation time 27783794 ps
CPU time 1.67 seconds
Started Jan 07 12:25:52 PM PST 24
Finished Jan 07 12:26:54 PM PST 24
Peak memory 213112 kb
Host smart-1ffdf27f-bbbe-440f-8a38-83d1bc16ec15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120402813 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2120402813
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.1305587517
Short name T815
Test name
Test status
Simulation time 50984370 ps
CPU time 0.88 seconds
Started Jan 07 12:26:04 PM PST 24
Finished Jan 07 12:27:02 PM PST 24
Peak memory 204712 kb
Host smart-4028a765-5e12-4148-bfc3-bed646769b0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305587517 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.1305587517
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.801527644
Short name T786
Test name
Test status
Simulation time 60240125 ps
CPU time 0.92 seconds
Started Jan 07 12:28:52 PM PST 24
Finished Jan 07 12:30:49 PM PST 24
Peak memory 205320 kb
Host smart-e1966d07-23b0-4b03-bf37-35e4503e7b20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801527644 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.801527644
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.118737583
Short name T789
Test name
Test status
Simulation time 102339032 ps
CPU time 1.25 seconds
Started Jan 07 12:25:48 PM PST 24
Finished Jan 07 12:26:49 PM PST 24
Peak memory 205968 kb
Host smart-ce5a290f-c400-48d2-b597-e3ce9f35fd6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118737583 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_ou
tstanding.118737583
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.1483957111
Short name T24
Test name
Test status
Simulation time 58436263 ps
CPU time 2.1 seconds
Started Jan 07 12:26:08 PM PST 24
Finished Jan 07 12:27:12 PM PST 24
Peak memory 213976 kb
Host smart-3144ce41-04d8-4015-84a2-bf0905e037b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483957111 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.1483957111
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.588438349
Short name T765
Test name
Test status
Simulation time 591502142 ps
CPU time 1.6 seconds
Started Jan 07 12:25:32 PM PST 24
Finished Jan 07 12:26:37 PM PST 24
Peak memory 205888 kb
Host smart-7dd58fee-d0b8-45a3-8c79-0b0101c5dec8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588438349 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.588438349
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.499287458
Short name T795
Test name
Test status
Simulation time 113336770 ps
CPU time 1.51 seconds
Started Jan 07 12:24:42 PM PST 24
Finished Jan 07 12:25:45 PM PST 24
Peak memory 214112 kb
Host smart-5278fe62-8caf-4691-a388-a769395f3a92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499287458 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.499287458
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.1331994846
Short name T173
Test name
Test status
Simulation time 14543392 ps
CPU time 0.88 seconds
Started Jan 07 12:26:30 PM PST 24
Finished Jan 07 12:27:43 PM PST 24
Peak memory 205640 kb
Host smart-abf7104e-d71d-40b5-8d39-2743be2277d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331994846 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1331994846
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.2130291229
Short name T155
Test name
Test status
Simulation time 34893947 ps
CPU time 0.83 seconds
Started Jan 07 12:24:59 PM PST 24
Finished Jan 07 12:26:09 PM PST 24
Peak memory 205920 kb
Host smart-5a1e9f8c-2db3-433b-8d2b-c51e8ec1f458
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130291229 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2130291229
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2363555220
Short name T812
Test name
Test status
Simulation time 18575617 ps
CPU time 1.06 seconds
Started Jan 07 12:26:20 PM PST 24
Finished Jan 07 12:27:24 PM PST 24
Peak memory 205704 kb
Host smart-06eeafb3-816f-489c-a5da-fdae2a01c275
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363555220 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.2363555220
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.833104455
Short name T769
Test name
Test status
Simulation time 25161577 ps
CPU time 1.62 seconds
Started Jan 07 12:26:04 PM PST 24
Finished Jan 07 12:27:03 PM PST 24
Peak memory 213064 kb
Host smart-c770380d-c4f4-4f73-ba5f-983bfa37528d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833104455 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.833104455
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2749112136
Short name T776
Test name
Test status
Simulation time 78409372 ps
CPU time 1.88 seconds
Started Jan 07 12:31:09 PM PST 24
Finished Jan 07 12:32:24 PM PST 24
Peak memory 205564 kb
Host smart-b2e5425a-2d54-4373-8c1c-94f62b14117c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749112136 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.2749112136
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3750716626
Short name T145
Test name
Test status
Simulation time 14057674 ps
CPU time 1.01 seconds
Started Jan 07 12:24:42 PM PST 24
Finished Jan 07 12:25:38 PM PST 24
Peak memory 222364 kb
Host smart-ab0223f4-067f-4773-8e82-c1f06c5cff05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750716626 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3750716626
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.7646018
Short name T808
Test name
Test status
Simulation time 33070290 ps
CPU time 0.78 seconds
Started Jan 07 12:25:52 PM PST 24
Finished Jan 07 12:26:54 PM PST 24
Peak memory 204768 kb
Host smart-03107dc2-b4ba-4bc6-82dc-1edddbef390d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7646018 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.7646018
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.1675189018
Short name T790
Test name
Test status
Simulation time 15046525 ps
CPU time 0.84 seconds
Started Jan 07 12:26:21 PM PST 24
Finished Jan 07 12:27:27 PM PST 24
Peak memory 205612 kb
Host smart-546a0d60-38f0-478e-a8a0-b85246edcc76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675189018 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.1675189018
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.2683361334
Short name T761
Test name
Test status
Simulation time 48985239 ps
CPU time 1.78 seconds
Started Jan 07 12:31:46 PM PST 24
Finished Jan 07 12:33:33 PM PST 24
Peak memory 213968 kb
Host smart-8bff63dc-653e-409a-8227-3f5c8a314d3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683361334 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.2683361334
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2915038589
Short name T802
Test name
Test status
Simulation time 339773493 ps
CPU time 2.17 seconds
Started Jan 07 12:26:14 PM PST 24
Finished Jan 07 12:27:18 PM PST 24
Peak memory 205628 kb
Host smart-8ba18f4f-3eb8-43ea-b245-816c0f94b87d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915038589 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.2915038589
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1645794280
Short name T170
Test name
Test status
Simulation time 35939386 ps
CPU time 1.45 seconds
Started Jan 07 12:29:21 PM PST 24
Finished Jan 07 12:31:02 PM PST 24
Peak memory 205252 kb
Host smart-ebf2a5a9-3c18-44cc-b032-6cd0c770fdff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645794280 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.1645794280
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.257335232
Short name T775
Test name
Test status
Simulation time 16658390 ps
CPU time 0.86 seconds
Started Jan 07 12:29:18 PM PST 24
Finished Jan 07 12:30:54 PM PST 24
Peak memory 205616 kb
Host smart-3c45a4b6-6f32-47ab-8e0d-ea15d5b07721
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257335232 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.257335232
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1493806541
Short name T28
Test name
Test status
Simulation time 78083391 ps
CPU time 1.21 seconds
Started Jan 07 12:23:53 PM PST 24
Finished Jan 07 12:24:08 PM PST 24
Peak memory 204444 kb
Host smart-822653c8-1064-433d-84e7-a2259de9265f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493806541 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.1493806541
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.2230156641
Short name T759
Test name
Test status
Simulation time 90972431 ps
CPU time 3.1 seconds
Started Jan 07 12:26:37 PM PST 24
Finished Jan 07 12:28:07 PM PST 24
Peak memory 214160 kb
Host smart-ab20c1e8-cec2-4cc9-a15a-1270cd456cfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230156641 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.2230156641
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.438006307
Short name T762
Test name
Test status
Simulation time 43837591 ps
CPU time 0.79 seconds
Started Jan 07 12:26:13 PM PST 24
Finished Jan 07 12:27:16 PM PST 24
Peak memory 205608 kb
Host smart-c8eb7871-8f1f-427e-8b1b-2ebe99b069c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438006307 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.438006307
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.3437069010
Short name T772
Test name
Test status
Simulation time 41406468 ps
CPU time 0.79 seconds
Started Jan 07 12:26:52 PM PST 24
Finished Jan 07 12:28:09 PM PST 24
Peak memory 205612 kb
Host smart-fa1d7ed6-f84f-4a78-aebb-f511e38bec91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437069010 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.3437069010
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.279586875
Short name T796
Test name
Test status
Simulation time 74914183 ps
CPU time 0.81 seconds
Started Jan 07 12:23:50 PM PST 24
Finished Jan 07 12:24:02 PM PST 24
Peak memory 205696 kb
Host smart-d9242c3f-9c1d-47f2-bca1-46860d99c8f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279586875 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.279586875
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.1190711574
Short name T205
Test name
Test status
Simulation time 23413466 ps
CPU time 0.78 seconds
Started Jan 07 12:26:30 PM PST 24
Finished Jan 07 12:27:40 PM PST 24
Peak memory 205636 kb
Host smart-3dbfe99b-a2f7-48ea-96d3-79bef71dc74c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190711574 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.1190711574
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.1130347363
Short name T784
Test name
Test status
Simulation time 44274758 ps
CPU time 0.8 seconds
Started Jan 07 12:31:46 PM PST 24
Finished Jan 07 12:34:06 PM PST 24
Peak memory 205648 kb
Host smart-92281859-abd6-48b3-9ec7-4aa798ea2b02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130347363 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.1130347363
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.2554053143
Short name T281
Test name
Test status
Simulation time 13223380 ps
CPU time 0.87 seconds
Started Jan 07 12:26:20 PM PST 24
Finished Jan 07 12:27:24 PM PST 24
Peak memory 205444 kb
Host smart-16c81cc6-1e64-417f-9d25-c7cf0f9639fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554053143 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2554053143
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.240854109
Short name T183
Test name
Test status
Simulation time 15834151 ps
CPU time 0.84 seconds
Started Jan 07 12:36:12 PM PST 24
Finished Jan 07 12:37:20 PM PST 24
Peak memory 205612 kb
Host smart-f74ba1f8-249b-486b-9921-a7610f64a473
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240854109 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.240854109
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1610989258
Short name T23
Test name
Test status
Simulation time 80421855 ps
CPU time 1.03 seconds
Started Jan 07 12:26:27 PM PST 24
Finished Jan 07 12:27:40 PM PST 24
Peak memory 205904 kb
Host smart-4b8f4f54-2b9e-420b-9f9e-a153a2b2c13d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610989258 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.1610989258
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.792939325
Short name T165
Test name
Test status
Simulation time 232353691 ps
CPU time 5.48 seconds
Started Jan 07 12:29:09 PM PST 24
Finished Jan 07 12:30:54 PM PST 24
Peak memory 205604 kb
Host smart-ba45c1c7-8cb5-4633-b8f7-9e140476f099
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792939325 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.792939325
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.692251838
Short name T764
Test name
Test status
Simulation time 43675050 ps
CPU time 0.87 seconds
Started Jan 07 12:32:50 PM PST 24
Finished Jan 07 12:34:02 PM PST 24
Peak memory 204952 kb
Host smart-db7cbbfe-0078-4fad-a2eb-5e58339ee20c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692251838 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.692251838
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2813423956
Short name T758
Test name
Test status
Simulation time 32617541 ps
CPU time 1.15 seconds
Started Jan 07 12:26:26 PM PST 24
Finished Jan 07 12:27:33 PM PST 24
Peak memory 213856 kb
Host smart-f4ddbeb9-d128-40c0-ab95-c7aef52bfbbf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813423956 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2813423956
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.350437208
Short name T161
Test name
Test status
Simulation time 44330507 ps
CPU time 0.89 seconds
Started Jan 07 12:29:08 PM PST 24
Finished Jan 07 12:30:42 PM PST 24
Peak memory 205508 kb
Host smart-ba0916d2-28cd-4be1-9910-b0d96177ef95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350437208 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.350437208
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2445461438
Short name T817
Test name
Test status
Simulation time 21698337 ps
CPU time 1 seconds
Started Jan 07 12:26:05 PM PST 24
Finished Jan 07 12:27:18 PM PST 24
Peak memory 205592 kb
Host smart-be169cfa-26a1-4b2d-b917-5bc0d68149e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445461438 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.2445461438
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.2130137713
Short name T25
Test name
Test status
Simulation time 58044713 ps
CPU time 0.79 seconds
Started Jan 07 12:36:42 PM PST 24
Finished Jan 07 12:37:49 PM PST 24
Peak memory 205420 kb
Host smart-4f368ae7-93d5-4c2f-be9e-cd5a4640c869
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130137713 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2130137713
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.2438281089
Short name T797
Test name
Test status
Simulation time 47623284 ps
CPU time 0.78 seconds
Started Jan 07 12:26:20 PM PST 24
Finished Jan 07 12:27:24 PM PST 24
Peak memory 205340 kb
Host smart-de46f26e-9e0e-41f9-ae83-6476d170303d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438281089 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.2438281089
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.702611755
Short name T794
Test name
Test status
Simulation time 23309616 ps
CPU time 1.04 seconds
Started Jan 07 12:23:53 PM PST 24
Finished Jan 07 12:24:08 PM PST 24
Peak memory 204512 kb
Host smart-28040b1b-72b4-4475-914b-15076b9e3f4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702611755 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.702611755
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.572861654
Short name T773
Test name
Test status
Simulation time 11317325 ps
CPU time 0.83 seconds
Started Jan 07 12:27:05 PM PST 24
Finished Jan 07 12:28:25 PM PST 24
Peak memory 205592 kb
Host smart-665650ae-589d-49f5-b567-af335c80c40c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572861654 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.572861654
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.2759934314
Short name T799
Test name
Test status
Simulation time 14143838 ps
CPU time 0.83 seconds
Started Jan 07 12:37:03 PM PST 24
Finished Jan 07 12:38:10 PM PST 24
Peak memory 204932 kb
Host smart-fc22e4cf-acb8-4f49-a7c9-8dc792cf58d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759934314 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.2759934314
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.2930469558
Short name T771
Test name
Test status
Simulation time 107368050 ps
CPU time 0.83 seconds
Started Jan 07 12:23:27 PM PST 24
Finished Jan 07 12:23:33 PM PST 24
Peak memory 204616 kb
Host smart-01f6a61b-d60f-4cc3-abb6-8c29e871c788
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930469558 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.2930469558
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.725181893
Short name T800
Test name
Test status
Simulation time 19605349 ps
CPU time 0.79 seconds
Started Jan 07 12:29:36 PM PST 24
Finished Jan 07 12:31:19 PM PST 24
Peak memory 205628 kb
Host smart-a311507a-0fd5-4a2a-a255-744e1e530d38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725181893 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.725181893
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.2376855055
Short name T807
Test name
Test status
Simulation time 13145706 ps
CPU time 0.81 seconds
Started Jan 07 12:25:45 PM PST 24
Finished Jan 07 12:26:44 PM PST 24
Peak memory 205508 kb
Host smart-bfc86ae6-d3c0-4655-a9f1-0fc8b5c2be3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376855055 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.2376855055
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.3245334442
Short name T811
Test name
Test status
Simulation time 46789058 ps
CPU time 0.82 seconds
Started Jan 07 12:27:05 PM PST 24
Finished Jan 07 12:28:25 PM PST 24
Peak memory 205592 kb
Host smart-d9caeca9-0656-4e35-939a-b5bb846b4356
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245334442 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.3245334442
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.1437051228
Short name T781
Test name
Test status
Simulation time 19205861 ps
CPU time 0.81 seconds
Started Jan 07 12:25:44 PM PST 24
Finished Jan 07 12:26:44 PM PST 24
Peak memory 204524 kb
Host smart-1889206a-dcbf-4324-8075-f0505f6207a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437051228 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.1437051228
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.1598950754
Short name T29
Test name
Test status
Simulation time 220797580 ps
CPU time 1.46 seconds
Started Jan 07 12:26:27 PM PST 24
Finished Jan 07 12:27:40 PM PST 24
Peak memory 205628 kb
Host smart-2b2c5474-82b7-4a59-895e-4840bf35a08a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598950754 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.1598950754
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3547861771
Short name T791
Test name
Test status
Simulation time 22975458 ps
CPU time 0.8 seconds
Started Jan 07 12:26:28 PM PST 24
Finished Jan 07 12:27:39 PM PST 24
Peak memory 205532 kb
Host smart-4d98b0ff-39f3-4c91-8401-8d0255870d7e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547861771 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3547861771
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.4051178016
Short name T823
Test name
Test status
Simulation time 36626806 ps
CPU time 1.04 seconds
Started Jan 07 12:31:27 PM PST 24
Finished Jan 07 12:33:14 PM PST 24
Peak memory 213924 kb
Host smart-d219e34a-fb67-4fad-9d9f-034b9b5a2914
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051178016 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.4051178016
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.82631936
Short name T809
Test name
Test status
Simulation time 15450614 ps
CPU time 0.88 seconds
Started Jan 07 12:30:19 PM PST 24
Finished Jan 07 12:31:57 PM PST 24
Peak memory 205520 kb
Host smart-35807ea3-94a7-4366-aaa3-6f5ab18c43dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82631936 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.82631936
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.3331847190
Short name T757
Test name
Test status
Simulation time 89524967 ps
CPU time 0.82 seconds
Started Jan 07 12:26:11 PM PST 24
Finished Jan 07 12:27:13 PM PST 24
Peak memory 204532 kb
Host smart-a52588fb-83df-4ede-b08d-4e01efbb036f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331847190 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.3331847190
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2259430699
Short name T186
Test name
Test status
Simulation time 27408297 ps
CPU time 1.03 seconds
Started Jan 07 12:26:22 PM PST 24
Finished Jan 07 12:27:26 PM PST 24
Peak memory 205680 kb
Host smart-7530db31-77ab-49df-9f48-1ab1ec9529c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259430699 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.2259430699
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.3634524060
Short name T178
Test name
Test status
Simulation time 56416834 ps
CPU time 2.03 seconds
Started Jan 07 12:29:55 PM PST 24
Finished Jan 07 12:31:36 PM PST 24
Peak memory 213560 kb
Host smart-de081dc4-ce0b-4408-98ca-f55251f00ac8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634524060 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.3634524060
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.2890868162
Short name T164
Test name
Test status
Simulation time 13037489 ps
CPU time 0.85 seconds
Started Jan 07 12:39:53 PM PST 24
Finished Jan 07 12:41:43 PM PST 24
Peak memory 205056 kb
Host smart-0c3e8e06-3151-4d46-835e-0915a00dbc8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890868162 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.2890868162
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.1433449776
Short name T756
Test name
Test status
Simulation time 50116016 ps
CPU time 0.83 seconds
Started Jan 07 12:26:39 PM PST 24
Finished Jan 07 12:27:57 PM PST 24
Peak memory 205536 kb
Host smart-77df2ebe-2fc4-4b4f-9028-98837bc05a64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433449776 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.1433449776
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.1676247848
Short name T783
Test name
Test status
Simulation time 22032714 ps
CPU time 0.79 seconds
Started Jan 07 12:28:53 PM PST 24
Finished Jan 07 12:30:05 PM PST 24
Peak memory 205444 kb
Host smart-16763ba0-011b-4200-90a7-158f94b6d425
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676247848 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.1676247848
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.321621951
Short name T61
Test name
Test status
Simulation time 15757971 ps
CPU time 0.88 seconds
Started Jan 07 12:26:34 PM PST 24
Finished Jan 07 12:27:47 PM PST 24
Peak memory 205888 kb
Host smart-dda7b4b8-5ce1-404f-b8be-1a8b25d1ba87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321621951 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.321621951
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.1552115031
Short name T154
Test name
Test status
Simulation time 30795815 ps
CPU time 0.75 seconds
Started Jan 07 12:26:26 PM PST 24
Finished Jan 07 12:27:34 PM PST 24
Peak memory 205432 kb
Host smart-2bcc713a-1c16-4ab4-aeb5-af2cf03ee9bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552115031 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.1552115031
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.2704092409
Short name T819
Test name
Test status
Simulation time 17101895 ps
CPU time 0.94 seconds
Started Jan 07 12:29:05 PM PST 24
Finished Jan 07 12:31:00 PM PST 24
Peak memory 205868 kb
Host smart-11b4db2e-7ace-42f2-97bb-e0a5fccec7ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704092409 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.2704092409
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.1074530440
Short name T792
Test name
Test status
Simulation time 21484998 ps
CPU time 0.78 seconds
Started Jan 07 12:30:01 PM PST 24
Finished Jan 07 12:31:47 PM PST 24
Peak memory 205592 kb
Host smart-8a57e8e1-0e89-4756-b724-86df91c9983a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074530440 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.1074530440
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3371848477
Short name T770
Test name
Test status
Simulation time 106097480 ps
CPU time 1.43 seconds
Started Jan 07 12:23:53 PM PST 24
Finished Jan 07 12:24:08 PM PST 24
Peak memory 212876 kb
Host smart-5e417be8-5351-43db-a076-5ccf129b263d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371848477 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.3371848477
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.2291719484
Short name T21
Test name
Test status
Simulation time 21612017 ps
CPU time 0.81 seconds
Started Jan 07 12:29:56 PM PST 24
Finished Jan 07 12:31:56 PM PST 24
Peak memory 205508 kb
Host smart-3bdae761-fc53-43ca-a55d-58c12edab590
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291719484 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.2291719484
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.2020746135
Short name T780
Test name
Test status
Simulation time 31537223 ps
CPU time 0.8 seconds
Started Jan 07 12:30:43 PM PST 24
Finished Jan 07 12:32:14 PM PST 24
Peak memory 204900 kb
Host smart-c74e2aca-7c06-430c-b061-015e49e67ac8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020746135 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.2020746135
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2923570801
Short name T822
Test name
Test status
Simulation time 57456238 ps
CPU time 1.23 seconds
Started Jan 07 12:26:17 PM PST 24
Finished Jan 07 12:27:21 PM PST 24
Peak memory 205612 kb
Host smart-df997577-d5b3-405f-837c-cb62aa9fae7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923570801 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.2923570801
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.714401995
Short name T787
Test name
Test status
Simulation time 24629977 ps
CPU time 1.67 seconds
Started Jan 07 12:26:19 PM PST 24
Finished Jan 07 12:27:24 PM PST 24
Peak memory 222068 kb
Host smart-9848dd56-f979-4412-b6a8-b28053141783
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714401995 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.714401995
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.2561277373
Short name T774
Test name
Test status
Simulation time 26137752 ps
CPU time 0.82 seconds
Started Jan 07 12:26:59 PM PST 24
Finished Jan 07 12:28:14 PM PST 24
Peak memory 205712 kb
Host smart-cf16f772-0e64-43a8-81fe-3c2913db1884
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561277373 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.2561277373
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2098133259
Short name T788
Test name
Test status
Simulation time 70815732 ps
CPU time 0.94 seconds
Started Jan 07 12:35:33 PM PST 24
Finished Jan 07 12:36:47 PM PST 24
Peak memory 205596 kb
Host smart-2e563a84-f3e8-45e5-bf65-f121d021e279
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098133259 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.2098133259
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2864761098
Short name T203
Test name
Test status
Simulation time 163236943 ps
CPU time 2.06 seconds
Started Jan 07 12:26:29 PM PST 24
Finished Jan 07 12:27:40 PM PST 24
Peak memory 205600 kb
Host smart-49f65e4d-d115-4c4c-b766-02aa3b81a45c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864761098 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.2864761098
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.3609807339
Short name T190
Test name
Test status
Simulation time 48566817 ps
CPU time 0.83 seconds
Started Jan 07 12:31:18 PM PST 24
Finished Jan 07 12:33:15 PM PST 24
Peak memory 205632 kb
Host smart-b1b6b7fa-ceea-4bab-84c8-a291eca72181
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609807339 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.3609807339
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2436803177
Short name T188
Test name
Test status
Simulation time 57094201 ps
CPU time 1.02 seconds
Started Jan 07 12:44:16 PM PST 24
Finished Jan 07 12:46:49 PM PST 24
Peak memory 206032 kb
Host smart-eafc6312-0f7b-4513-8e81-937dc29db051
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436803177 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.2436803177
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3783646133
Short name T168
Test name
Test status
Simulation time 45364690 ps
CPU time 1.5 seconds
Started Jan 07 12:43:10 PM PST 24
Finished Jan 07 12:44:21 PM PST 24
Peak memory 205852 kb
Host smart-79821a1b-2540-4fa9-a2e6-c199d2f70cc1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783646133 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.3783646133
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3119483821
Short name T760
Test name
Test status
Simulation time 70043094 ps
CPU time 1.03 seconds
Started Jan 07 12:33:41 PM PST 24
Finished Jan 07 12:35:30 PM PST 24
Peak memory 213908 kb
Host smart-b487902b-5f95-499a-8025-d50930c43bb1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119483821 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3119483821
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.3227742133
Short name T192
Test name
Test status
Simulation time 36911333 ps
CPU time 0.76 seconds
Started Jan 07 12:29:31 PM PST 24
Finished Jan 07 12:30:52 PM PST 24
Peak memory 204996 kb
Host smart-6ae772ff-e1d0-4a9a-b8fe-d5037b19f46c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227742133 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.3227742133
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1172455381
Short name T144
Test name
Test status
Simulation time 32564544 ps
CPU time 0.93 seconds
Started Jan 07 12:32:21 PM PST 24
Finished Jan 07 12:34:04 PM PST 24
Peak memory 213888 kb
Host smart-d224edf8-2807-44cb-905a-2d997e885441
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172455381 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.1172455381
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.1100295360
Short name T172
Test name
Test status
Simulation time 41725389 ps
CPU time 0.8 seconds
Started Jan 07 12:29:44 PM PST 24
Finished Jan 07 12:31:19 PM PST 24
Peak memory 205348 kb
Host smart-092681cd-5523-4625-ae2f-cc87b2b475fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100295360 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.1100295360
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.4087848870
Short name T181
Test name
Test status
Simulation time 11188910 ps
CPU time 0.79 seconds
Started Jan 07 12:26:34 PM PST 24
Finished Jan 07 12:27:47 PM PST 24
Peak memory 205476 kb
Host smart-2f507f36-8e20-435a-863b-516fbc057da1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087848870 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.4087848870
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3189923295
Short name T184
Test name
Test status
Simulation time 101367539 ps
CPU time 0.91 seconds
Started Jan 07 12:31:29 PM PST 24
Finished Jan 07 12:32:48 PM PST 24
Peak memory 205072 kb
Host smart-2794b509-4709-48f1-ba15-e56114aa1e02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189923295 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.3189923295
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.1276257550
Short name T767
Test name
Test status
Simulation time 72504818 ps
CPU time 2.06 seconds
Started Jan 07 12:33:30 PM PST 24
Finished Jan 07 12:34:36 PM PST 24
Peak memory 213904 kb
Host smart-4ac77cd3-bbc0-4630-adee-6a1a982c6eb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276257550 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.1276257550
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3504975913
Short name T202
Test name
Test status
Simulation time 1084860144 ps
CPU time 15.02 seconds
Started Jan 07 12:29:50 PM PST 24
Finished Jan 07 12:31:41 PM PST 24
Peak memory 205620 kb
Host smart-e6565d20-e70e-4127-8485-19100fe7a2fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504975913 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.3504975913
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.3594395385
Short name T389
Test name
Test status
Simulation time 36401245 ps
CPU time 1.03 seconds
Started Jan 07 12:40:03 PM PST 24
Finished Jan 07 12:42:09 PM PST 24
Peak memory 214544 kb
Host smart-766ccb1a-faa5-4edb-b247-7158513c925e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594395385 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.3594395385
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.1391090902
Short name T299
Test name
Test status
Simulation time 20070453 ps
CPU time 0.93 seconds
Started Jan 07 12:40:02 PM PST 24
Finished Jan 07 12:41:06 PM PST 24
Peak memory 215648 kb
Host smart-9f1bdc73-5707-4da1-b824-2d08f7ea7dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391090902 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.1391090902
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.444787135
Short name T308
Test name
Test status
Simulation time 32467018 ps
CPU time 0.89 seconds
Started Jan 07 12:39:25 PM PST 24
Finished Jan 07 12:40:51 PM PST 24
Peak memory 204852 kb
Host smart-f8e2321c-8eee-45c3-8df2-37dc9df2122b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444787135 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.444787135
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.3959086012
Short name T496
Test name
Test status
Simulation time 20824620 ps
CPU time 1.1 seconds
Started Jan 07 12:40:05 PM PST 24
Finished Jan 07 12:41:17 PM PST 24
Peak memory 221340 kb
Host smart-46754ddd-83f3-4bd2-aed5-bc6e3bbbc789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959086012 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.3959086012
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_sec_cm.2658417348
Short name T72
Test name
Test status
Simulation time 335415420 ps
CPU time 2.88 seconds
Started Jan 07 12:40:06 PM PST 24
Finished Jan 07 12:41:20 PM PST 24
Peak memory 232916 kb
Host smart-f3185b2c-0f59-4a87-8f2e-1ca0ae8e8b67
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658417348 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.2658417348
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.2095461083
Short name T302
Test name
Test status
Simulation time 30686598 ps
CPU time 0.83 seconds
Started Jan 07 12:39:54 PM PST 24
Finished Jan 07 12:41:27 PM PST 24
Peak memory 204584 kb
Host smart-39c11668-f9e3-4976-9d11-d2c6d735b181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095461083 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.2095461083
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.1813727701
Short name T679
Test name
Test status
Simulation time 23442241 ps
CPU time 0.98 seconds
Started Jan 07 12:40:07 PM PST 24
Finished Jan 07 12:41:30 PM PST 24
Peak memory 214540 kb
Host smart-0aa7ee99-5128-4357-b926-ce9605151293
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813727701 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.1813727701
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.2089886925
Short name T43
Test name
Test status
Simulation time 17920963 ps
CPU time 0.96 seconds
Started Jan 07 12:40:12 PM PST 24
Finished Jan 07 12:41:38 PM PST 24
Peak memory 215684 kb
Host smart-62347b23-19f7-48c6-a8a6-ca5b41b852d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089886925 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.2089886925
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_intr.2105482514
Short name T659
Test name
Test status
Simulation time 19650409 ps
CPU time 1.17 seconds
Started Jan 07 12:39:51 PM PST 24
Finished Jan 07 12:41:34 PM PST 24
Peak memory 221380 kb
Host smart-94903aff-9bc0-4334-aee8-da52debaeee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105482514 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.2105482514
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_sec_cm.3332061652
Short name T31
Test name
Test status
Simulation time 221096928 ps
CPU time 3.68 seconds
Started Jan 07 12:40:13 PM PST 24
Finished Jan 07 12:41:27 PM PST 24
Peak memory 231784 kb
Host smart-9394e35e-619f-4279-ba0e-0b28de699bfb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332061652 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.3332061652
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.816041253
Short name T559
Test name
Test status
Simulation time 13511467 ps
CPU time 0.87 seconds
Started Jan 07 12:39:48 PM PST 24
Finished Jan 07 12:40:58 PM PST 24
Peak memory 204596 kb
Host smart-bfff6709-67dc-4c3f-8cd5-a906fd0930c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816041253 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.816041253
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.177649259
Short name T461
Test name
Test status
Simulation time 59812432 ps
CPU time 1.67 seconds
Started Jan 07 12:40:02 PM PST 24
Finished Jan 07 12:41:23 PM PST 24
Peak memory 205936 kb
Host smart-b8dbdb01-c8f7-4bd5-943f-6e5bd06a9c2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177649259 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.177649259
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.1476982414
Short name T444
Test name
Test status
Simulation time 18274037768 ps
CPU time 400.72 seconds
Started Jan 07 12:40:32 PM PST 24
Finished Jan 07 12:48:15 PM PST 24
Peak memory 214816 kb
Host smart-fb72a804-7486-45ef-bcfc-5e1451dcce8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476982414 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.1476982414
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.1566670338
Short name T17
Test name
Test status
Simulation time 29053202 ps
CPU time 0.91 seconds
Started Jan 07 12:40:59 PM PST 24
Finished Jan 07 12:42:03 PM PST 24
Peak memory 205956 kb
Host smart-e2fa8ca2-6c7f-443a-b656-a601f270318a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566670338 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.1566670338
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.599570205
Short name T375
Test name
Test status
Simulation time 25998515 ps
CPU time 0.83 seconds
Started Jan 07 12:40:14 PM PST 24
Finished Jan 07 12:41:24 PM PST 24
Peak memory 205140 kb
Host smart-24e08dad-a38f-41c1-835c-92851eec3d63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599570205 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.599570205
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.95838965
Short name T304
Test name
Test status
Simulation time 68824535 ps
CPU time 0.79 seconds
Started Jan 07 12:40:53 PM PST 24
Finished Jan 07 12:42:16 PM PST 24
Peak memory 214304 kb
Host smart-97348649-15bd-48b5-8bdf-2574d316d361
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95838965 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.95838965
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_intr.4281681192
Short name T516
Test name
Test status
Simulation time 20153692 ps
CPU time 0.99 seconds
Started Jan 07 12:40:44 PM PST 24
Finished Jan 07 12:41:57 PM PST 24
Peak memory 214304 kb
Host smart-905ee07c-dcc6-4532-ab24-53e3acd6457f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281681192 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.4281681192
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.1908921127
Short name T75
Test name
Test status
Simulation time 46926652 ps
CPU time 0.83 seconds
Started Jan 07 12:40:14 PM PST 24
Finished Jan 07 12:42:12 PM PST 24
Peak memory 204684 kb
Host smart-dbde29a6-e46c-4380-9023-574ad89bd976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908921127 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1908921127
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.3831877444
Short name T518
Test name
Test status
Simulation time 375845516627 ps
CPU time 1571.18 seconds
Started Jan 07 12:40:30 PM PST 24
Finished Jan 07 01:07:51 PM PST 24
Peak memory 217548 kb
Host smart-695231cc-ae6e-4387-85b4-01522f14e2f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831877444 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.3831877444
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/102.edn_genbits.1561565156
Short name T687
Test name
Test status
Simulation time 92615754 ps
CPU time 2.2 seconds
Started Jan 07 12:41:35 PM PST 24
Finished Jan 07 12:42:48 PM PST 24
Peak memory 214152 kb
Host smart-3a052081-2a42-4ffa-b021-1906c7e62c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561565156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.1561565156
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.2623766774
Short name T295
Test name
Test status
Simulation time 19022338 ps
CPU time 0.85 seconds
Started Jan 07 12:41:37 PM PST 24
Finished Jan 07 12:42:58 PM PST 24
Peak memory 205040 kb
Host smart-bbfb090f-a5f6-4deb-a71e-875f03af0f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623766774 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.2623766774
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.1423313382
Short name T691
Test name
Test status
Simulation time 30757247 ps
CPU time 0.91 seconds
Started Jan 07 12:42:05 PM PST 24
Finished Jan 07 12:43:37 PM PST 24
Peak memory 205092 kb
Host smart-11bf8640-57c2-4b6d-885e-e8f5dded88a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423313382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.1423313382
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.1823814996
Short name T752
Test name
Test status
Simulation time 39658309 ps
CPU time 0.87 seconds
Started Jan 07 12:41:27 PM PST 24
Finished Jan 07 12:43:14 PM PST 24
Peak memory 204980 kb
Host smart-f9d714e5-e058-4988-a6ad-179fe943b38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823814996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.1823814996
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.817566438
Short name T129
Test name
Test status
Simulation time 49954009 ps
CPU time 2.04 seconds
Started Jan 07 12:41:51 PM PST 24
Finished Jan 07 12:43:26 PM PST 24
Peak memory 214112 kb
Host smart-164c6b8b-f4b1-4eb4-8666-8402f7cb76d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817566438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.817566438
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.2957830015
Short name T591
Test name
Test status
Simulation time 23434392 ps
CPU time 1.31 seconds
Started Jan 07 12:42:07 PM PST 24
Finished Jan 07 12:43:44 PM PST 24
Peak memory 205984 kb
Host smart-1a833bd4-55fa-4eea-9d67-4397878e00fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957830015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.2957830015
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.2585601160
Short name T689
Test name
Test status
Simulation time 18159207 ps
CPU time 1.11 seconds
Started Jan 07 12:41:46 PM PST 24
Finished Jan 07 12:42:58 PM PST 24
Peak memory 205648 kb
Host smart-81238ad1-ccfb-4410-8cb5-7f92e5c29ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585601160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.2585601160
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_disable.2025445233
Short name T690
Test name
Test status
Simulation time 13012132 ps
CPU time 0.86 seconds
Started Jan 07 12:40:49 PM PST 24
Finished Jan 07 12:42:27 PM PST 24
Peak memory 214440 kb
Host smart-b86138ca-55bb-4fd5-9fac-71807975a081
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025445233 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.2025445233
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_err.2944792709
Short name T434
Test name
Test status
Simulation time 18398267 ps
CPU time 1.07 seconds
Started Jan 07 12:40:49 PM PST 24
Finished Jan 07 12:41:55 PM PST 24
Peak memory 221748 kb
Host smart-db511492-f602-4208-9dce-393117919f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944792709 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.2944792709
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_intr.446186650
Short name T453
Test name
Test status
Simulation time 24341873 ps
CPU time 0.98 seconds
Started Jan 07 12:40:38 PM PST 24
Finished Jan 07 12:41:42 PM PST 24
Peak memory 221912 kb
Host smart-355cabba-180c-4652-9e5e-4c3777c477e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446186650 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.446186650
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.2479023258
Short name T121
Test name
Test status
Simulation time 265986290192 ps
CPU time 1780.99 seconds
Started Jan 07 12:40:39 PM PST 24
Finished Jan 07 01:11:23 PM PST 24
Peak memory 220968 kb
Host smart-3fae33a7-8069-478d-a3af-e256406d433c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479023258 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.2479023258
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.3293564104
Short name T280
Test name
Test status
Simulation time 9084752138 ps
CPU time 123.12 seconds
Started Jan 07 12:41:50 PM PST 24
Finished Jan 07 12:46:04 PM PST 24
Peak memory 214296 kb
Host smart-a33e1431-cf24-41a3-9b82-9dfe55cd4497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293564104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.3293564104
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.1739831188
Short name T474
Test name
Test status
Simulation time 17296722 ps
CPU time 0.93 seconds
Started Jan 07 12:41:49 PM PST 24
Finished Jan 07 12:43:40 PM PST 24
Peak memory 205000 kb
Host smart-d55ff733-af66-4e70-9244-867bccb6d76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739831188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.1739831188
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.1212029405
Short name T480
Test name
Test status
Simulation time 86216176 ps
CPU time 0.88 seconds
Started Jan 07 12:41:47 PM PST 24
Finished Jan 07 12:43:23 PM PST 24
Peak memory 205444 kb
Host smart-0fbf90e0-b8be-49a2-88ce-38703645a01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212029405 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.1212029405
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.1902246635
Short name T506
Test name
Test status
Simulation time 34045775 ps
CPU time 1.12 seconds
Started Jan 07 12:41:25 PM PST 24
Finished Jan 07 12:43:14 PM PST 24
Peak memory 214136 kb
Host smart-8e76ab9b-27b4-4fd2-ab0e-8123ca9e6367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902246635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.1902246635
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.279253014
Short name T265
Test name
Test status
Simulation time 39228543 ps
CPU time 0.85 seconds
Started Jan 07 12:41:45 PM PST 24
Finished Jan 07 12:43:14 PM PST 24
Peak memory 204888 kb
Host smart-907d5370-f9e7-459e-973b-e93f7afbf0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279253014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.279253014
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.3170934480
Short name T347
Test name
Test status
Simulation time 57111496 ps
CPU time 0.93 seconds
Started Jan 07 12:41:49 PM PST 24
Finished Jan 07 12:43:02 PM PST 24
Peak memory 205380 kb
Host smart-850cc355-feff-4012-8c94-4e565131586d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170934480 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.3170934480
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.3888001502
Short name T535
Test name
Test status
Simulation time 111002126 ps
CPU time 1.47 seconds
Started Jan 07 12:41:46 PM PST 24
Finished Jan 07 12:43:19 PM PST 24
Peak memory 214252 kb
Host smart-3a5985d9-a636-4dd5-83ed-0c54c5bf8842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888001502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3888001502
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.1636821744
Short name T702
Test name
Test status
Simulation time 23731920 ps
CPU time 0.94 seconds
Started Jan 07 12:40:40 PM PST 24
Finished Jan 07 12:41:44 PM PST 24
Peak memory 214496 kb
Host smart-40f15dae-0830-4478-b888-b3f148b8a79d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636821744 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.1636821744
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.898176713
Short name T570
Test name
Test status
Simulation time 19112780 ps
CPU time 1.15 seconds
Started Jan 07 12:40:02 PM PST 24
Finished Jan 07 12:41:20 PM PST 24
Peak memory 221724 kb
Host smart-fd575965-093d-4460-964f-698637842662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898176713 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.898176713
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.4185815534
Short name T421
Test name
Test status
Simulation time 16772043 ps
CPU time 0.94 seconds
Started Jan 07 12:40:06 PM PST 24
Finished Jan 07 12:41:18 PM PST 24
Peak memory 204932 kb
Host smart-b7de0a5d-84ef-43ab-85e1-89add572db2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185815534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.4185815534
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.911484565
Short name T619
Test name
Test status
Simulation time 25373176 ps
CPU time 0.9 seconds
Started Jan 07 12:40:30 PM PST 24
Finished Jan 07 12:41:37 PM PST 24
Peak memory 214272 kb
Host smart-ddf64431-638d-4eb3-90b4-356e2f16ae96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911484565 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.911484565
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.2851683217
Short name T80
Test name
Test status
Simulation time 16511434 ps
CPU time 0.82 seconds
Started Jan 07 12:40:38 PM PST 24
Finished Jan 07 12:42:16 PM PST 24
Peak memory 204676 kb
Host smart-b7e87d16-b3ec-4c12-b2ac-c3735a589139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851683217 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2851683217
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.1361481177
Short name T429
Test name
Test status
Simulation time 728136145 ps
CPU time 1.81 seconds
Started Jan 07 12:40:42 PM PST 24
Finished Jan 07 12:41:51 PM PST 24
Peak memory 205768 kb
Host smart-925accd5-b5d9-4014-8ef7-b844bb1c33b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361481177 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.1361481177
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.914097410
Short name T486
Test name
Test status
Simulation time 52074037392 ps
CPU time 578.69 seconds
Started Jan 07 12:40:12 PM PST 24
Finished Jan 07 12:51:16 PM PST 24
Peak memory 215376 kb
Host smart-4bdaedad-14da-4e64-a0da-98ae49e9b310
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914097410 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.914097410
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.980453798
Short name T348
Test name
Test status
Simulation time 22489314 ps
CPU time 1.1 seconds
Started Jan 07 12:41:10 PM PST 24
Finished Jan 07 12:42:17 PM PST 24
Peak memory 205596 kb
Host smart-e955e729-b612-4628-92ed-b4537601038a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980453798 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.980453798
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.781716875
Short name T708
Test name
Test status
Simulation time 16823625 ps
CPU time 0.95 seconds
Started Jan 07 12:41:37 PM PST 24
Finished Jan 07 12:43:04 PM PST 24
Peak memory 205128 kb
Host smart-5f5ae87b-f883-404f-9360-b8a7b3a43ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781716875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.781716875
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.312308450
Short name T426
Test name
Test status
Simulation time 33764072 ps
CPU time 1.2 seconds
Started Jan 07 12:42:11 PM PST 24
Finished Jan 07 12:43:27 PM PST 24
Peak memory 205512 kb
Host smart-42847d4a-f20a-4233-8cbb-c192feb9e9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312308450 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.312308450
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.1236686053
Short name T310
Test name
Test status
Simulation time 172634094 ps
CPU time 0.93 seconds
Started Jan 07 12:42:15 PM PST 24
Finished Jan 07 12:43:46 PM PST 24
Peak memory 205356 kb
Host smart-ce5e4402-51e8-45d4-b421-df3a98fe650d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236686053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.1236686053
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.4022655509
Short name T722
Test name
Test status
Simulation time 72790483 ps
CPU time 1.01 seconds
Started Jan 07 12:41:24 PM PST 24
Finished Jan 07 12:42:40 PM PST 24
Peak memory 214168 kb
Host smart-667a051c-215a-4480-b7d5-28b4f4ef5d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022655509 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.4022655509
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.676142147
Short name T529
Test name
Test status
Simulation time 22531285 ps
CPU time 0.97 seconds
Started Jan 07 12:42:10 PM PST 24
Finished Jan 07 12:43:27 PM PST 24
Peak memory 205552 kb
Host smart-fae2cdb8-22fd-42aa-8202-060302ab3546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676142147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.676142147
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.3960832504
Short name T270
Test name
Test status
Simulation time 41039301 ps
CPU time 0.99 seconds
Started Jan 07 12:41:53 PM PST 24
Finished Jan 07 12:43:16 PM PST 24
Peak memory 205500 kb
Host smart-fff400cc-7ee9-4ca2-be04-b395e7e89e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960832504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.3960832504
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.2748811211
Short name T289
Test name
Test status
Simulation time 32041403 ps
CPU time 0.91 seconds
Started Jan 07 12:41:25 PM PST 24
Finished Jan 07 12:42:51 PM PST 24
Peak memory 205044 kb
Host smart-3f515479-5c72-40a9-a310-05b0ab724588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748811211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.2748811211
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert_test.3756038677
Short name T307
Test name
Test status
Simulation time 41231049 ps
CPU time 0.97 seconds
Started Jan 07 12:40:05 PM PST 24
Finished Jan 07 12:41:36 PM PST 24
Peak memory 204680 kb
Host smart-623e5b0c-f65c-4bcd-bb50-0f3b496e1ff3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756038677 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3756038677
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.1286378877
Short name T360
Test name
Test status
Simulation time 13892053 ps
CPU time 0.86 seconds
Started Jan 07 12:40:47 PM PST 24
Finished Jan 07 12:41:52 PM PST 24
Peak memory 214432 kb
Host smart-06b05d60-d494-42d6-a927-e92f1a0b56d6
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286378877 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.1286378877
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.1648262904
Short name T414
Test name
Test status
Simulation time 16031838 ps
CPU time 0.97 seconds
Started Jan 07 12:40:43 PM PST 24
Finished Jan 07 12:42:38 PM PST 24
Peak memory 214600 kb
Host smart-7ccdb922-e122-4846-8388-c37ef6e1ee30
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648262904 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.1648262904
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.940102660
Short name T674
Test name
Test status
Simulation time 33096466 ps
CPU time 0.85 seconds
Started Jan 07 12:40:38 PM PST 24
Finished Jan 07 12:42:16 PM PST 24
Peak memory 215896 kb
Host smart-67a4bc50-1e15-47a8-83e5-3d3c8b07358c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940102660 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.940102660
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.3949266271
Short name T339
Test name
Test status
Simulation time 40171570 ps
CPU time 1.72 seconds
Started Jan 07 12:40:38 PM PST 24
Finished Jan 07 12:41:54 PM PST 24
Peak memory 214156 kb
Host smart-8dd77c7e-acfe-4d30-9bb9-1f1b4e1598da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949266271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.3949266271
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.3774708963
Short name T65
Test name
Test status
Simulation time 26871819 ps
CPU time 0.94 seconds
Started Jan 07 12:40:48 PM PST 24
Finished Jan 07 12:42:13 PM PST 24
Peak memory 221740 kb
Host smart-9fce3699-464d-43f1-a01c-924032577092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774708963 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.3774708963
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.425600767
Short name T562
Test name
Test status
Simulation time 14612932 ps
CPU time 0.84 seconds
Started Jan 07 12:40:22 PM PST 24
Finished Jan 07 12:41:21 PM PST 24
Peak memory 204928 kb
Host smart-976e6629-e51e-42cf-9950-68493093f48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425600767 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.425600767
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.1156182254
Short name T635
Test name
Test status
Simulation time 119534639 ps
CPU time 1.22 seconds
Started Jan 07 12:40:48 PM PST 24
Finished Jan 07 12:41:54 PM PST 24
Peak memory 205608 kb
Host smart-49ffcdab-32ac-40ff-b860-8827edd567e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156182254 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.1156182254
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.2897909336
Short name T148
Test name
Test status
Simulation time 35700594070 ps
CPU time 786.06 seconds
Started Jan 07 12:40:39 PM PST 24
Finished Jan 07 12:54:45 PM PST 24
Peak memory 214512 kb
Host smart-ac820a4b-0317-4d62-814d-4f17cbcf8897
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897909336 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.2897909336
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.322298000
Short name T645
Test name
Test status
Simulation time 16340809 ps
CPU time 1.07 seconds
Started Jan 07 12:41:53 PM PST 24
Finished Jan 07 12:43:13 PM PST 24
Peak memory 214172 kb
Host smart-267d38b9-499d-4170-bb3f-964372f09605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322298000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.322298000
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.3322630844
Short name T157
Test name
Test status
Simulation time 39634963 ps
CPU time 1.33 seconds
Started Jan 07 12:41:37 PM PST 24
Finished Jan 07 12:43:30 PM PST 24
Peak memory 214144 kb
Host smart-b8661280-33bb-47d5-a33d-481455e7af68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322630844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.3322630844
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.3427395388
Short name T631
Test name
Test status
Simulation time 36081968 ps
CPU time 1.17 seconds
Started Jan 07 12:42:03 PM PST 24
Finished Jan 07 12:43:25 PM PST 24
Peak memory 205600 kb
Host smart-b2eed6e1-ec15-49d1-88cf-8b707507c684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427395388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.3427395388
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.300528034
Short name T563
Test name
Test status
Simulation time 17264298 ps
CPU time 0.99 seconds
Started Jan 07 12:41:47 PM PST 24
Finished Jan 07 12:43:30 PM PST 24
Peak memory 205024 kb
Host smart-eac4ef90-e508-4eae-9c9a-8f3b2f6344e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300528034 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.300528034
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.1490070984
Short name T438
Test name
Test status
Simulation time 14999135 ps
CPU time 0.98 seconds
Started Jan 07 12:42:17 PM PST 24
Finished Jan 07 12:43:34 PM PST 24
Peak memory 205292 kb
Host smart-0b08ff69-9321-4e15-8705-f20da0f2c9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490070984 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.1490070984
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.1899697895
Short name T550
Test name
Test status
Simulation time 37974634 ps
CPU time 0.99 seconds
Started Jan 07 12:41:43 PM PST 24
Finished Jan 07 12:43:23 PM PST 24
Peak memory 205260 kb
Host smart-cee28ef3-2e63-4269-b028-801972c12087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899697895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1899697895
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.1694477001
Short name T49
Test name
Test status
Simulation time 43393381 ps
CPU time 1.92 seconds
Started Jan 07 12:41:52 PM PST 24
Finished Jan 07 12:43:22 PM PST 24
Peak memory 214036 kb
Host smart-e6d984d7-c9c9-41d4-b23e-52a9d6acef34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694477001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.1694477001
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.77714479
Short name T53
Test name
Test status
Simulation time 20726692 ps
CPU time 1.11 seconds
Started Jan 07 12:41:28 PM PST 24
Finished Jan 07 12:42:41 PM PST 24
Peak memory 205772 kb
Host smart-e7c19dbd-d036-483e-ae10-252138fe1e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77714479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.77714479
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.3977475208
Short name T229
Test name
Test status
Simulation time 81281482 ps
CPU time 0.88 seconds
Started Jan 07 12:40:27 PM PST 24
Finished Jan 07 12:41:30 PM PST 24
Peak memory 205372 kb
Host smart-2e391fbd-ce99-463d-8e2c-3085190a7dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977475208 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.3977475208
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.985776334
Short name T383
Test name
Test status
Simulation time 39421456 ps
CPU time 0.79 seconds
Started Jan 07 12:40:34 PM PST 24
Finished Jan 07 12:41:35 PM PST 24
Peak memory 205208 kb
Host smart-25816c17-c57d-4c1d-8385-210a92eb7dd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985776334 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.985776334
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.1452793534
Short name T617
Test name
Test status
Simulation time 12881723 ps
CPU time 0.86 seconds
Started Jan 07 12:40:07 PM PST 24
Finished Jan 07 12:41:44 PM PST 24
Peak memory 214592 kb
Host smart-747b6601-7867-4998-a12f-23863a742ba7
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452793534 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.1452793534
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.2894590106
Short name T96
Test name
Test status
Simulation time 25549530 ps
CPU time 1 seconds
Started Jan 07 12:40:40 PM PST 24
Finished Jan 07 12:42:24 PM PST 24
Peak memory 214504 kb
Host smart-f61ca1d7-17ce-4e78-8e02-c87f436f3e85
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894590106 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.2894590106
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.4188493958
Short name T351
Test name
Test status
Simulation time 18916204 ps
CPU time 1.24 seconds
Started Jan 07 12:40:12 PM PST 24
Finished Jan 07 12:41:24 PM PST 24
Peak memory 215952 kb
Host smart-c37fa1b3-0fec-4d0b-9077-779223d7587a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188493958 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.4188493958
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.775013877
Short name T749
Test name
Test status
Simulation time 26501142 ps
CPU time 1.22 seconds
Started Jan 07 12:40:15 PM PST 24
Finished Jan 07 12:41:25 PM PST 24
Peak memory 205480 kb
Host smart-5cf84eb6-1e50-4cb5-83e1-59019fa0d938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775013877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.775013877
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_smoke.549937160
Short name T678
Test name
Test status
Simulation time 17755490 ps
CPU time 0.78 seconds
Started Jan 07 12:40:13 PM PST 24
Finished Jan 07 12:41:17 PM PST 24
Peak memory 204584 kb
Host smart-b898b5d0-3925-457e-be7c-6e25784d2c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549937160 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.549937160
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.3783147346
Short name T661
Test name
Test status
Simulation time 141678313 ps
CPU time 1.16 seconds
Started Jan 07 12:40:12 PM PST 24
Finished Jan 07 12:41:46 PM PST 24
Peak memory 205036 kb
Host smart-3d298c18-2d3a-4586-a84c-fb777184ca7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783147346 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.3783147346
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.4140662613
Short name T77
Test name
Test status
Simulation time 53667940164 ps
CPU time 1321.18 seconds
Started Jan 07 12:40:58 PM PST 24
Finished Jan 07 01:04:49 PM PST 24
Peak memory 217524 kb
Host smart-2f9002a3-aca8-4422-858e-2852e32da8fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140662613 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.4140662613
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/141.edn_genbits.152261904
Short name T549
Test name
Test status
Simulation time 33408812 ps
CPU time 1.1 seconds
Started Jan 07 12:41:48 PM PST 24
Finished Jan 07 12:43:19 PM PST 24
Peak memory 214220 kb
Host smart-3b1e3a3c-6a04-492f-a1c3-dcce47397f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152261904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.152261904
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.219165991
Short name T680
Test name
Test status
Simulation time 152670677 ps
CPU time 0.99 seconds
Started Jan 07 12:41:36 PM PST 24
Finished Jan 07 12:43:05 PM PST 24
Peak memory 205316 kb
Host smart-9bfb582e-ba02-4f6b-97fa-614803ec51da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219165991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.219165991
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.3331239430
Short name T646
Test name
Test status
Simulation time 109066588 ps
CPU time 0.89 seconds
Started Jan 07 12:41:28 PM PST 24
Finished Jan 07 12:42:49 PM PST 24
Peak memory 205048 kb
Host smart-40b0472c-9f3a-430f-859c-2f4089601b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331239430 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.3331239430
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.1731247721
Short name T363
Test name
Test status
Simulation time 137594640 ps
CPU time 1.15 seconds
Started Jan 07 12:41:38 PM PST 24
Finished Jan 07 12:43:10 PM PST 24
Peak memory 214068 kb
Host smart-d656faad-40b2-4ebe-9389-0e04bd86f09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731247721 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.1731247721
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.2976246197
Short name T109
Test name
Test status
Simulation time 68723375 ps
CPU time 1.11 seconds
Started Jan 07 12:41:48 PM PST 24
Finished Jan 07 12:43:13 PM PST 24
Peak memory 214208 kb
Host smart-f7c7ae2a-a2fd-4ba5-8b9a-3f95c3241d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976246197 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2976246197
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.1403558685
Short name T608
Test name
Test status
Simulation time 23023198 ps
CPU time 1.11 seconds
Started Jan 07 12:42:04 PM PST 24
Finished Jan 07 12:43:24 PM PST 24
Peak memory 214152 kb
Host smart-350043c6-9c97-4346-9c96-ef8e7e1115ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403558685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.1403558685
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.2327666682
Short name T423
Test name
Test status
Simulation time 39621936 ps
CPU time 0.9 seconds
Started Jan 07 12:42:15 PM PST 24
Finished Jan 07 12:43:30 PM PST 24
Peak memory 204996 kb
Host smart-63ef4041-7414-48df-9876-21722b545309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327666682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.2327666682
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.2610803519
Short name T614
Test name
Test status
Simulation time 84819826 ps
CPU time 0.97 seconds
Started Jan 07 12:41:50 PM PST 24
Finished Jan 07 12:44:03 PM PST 24
Peak memory 205152 kb
Host smart-13c9e4fe-3aab-4efa-b6e5-68fd7e2e8eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610803519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.2610803519
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.2964749990
Short name T92
Test name
Test status
Simulation time 61542112 ps
CPU time 0.91 seconds
Started Jan 07 12:40:46 PM PST 24
Finished Jan 07 12:41:53 PM PST 24
Peak memory 206140 kb
Host smart-1447bd12-4d7b-4667-8e2a-9228d0c9b469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964749990 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.2964749990
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_disable.3262623977
Short name T746
Test name
Test status
Simulation time 31209296 ps
CPU time 0.79 seconds
Started Jan 07 12:40:22 PM PST 24
Finished Jan 07 12:41:35 PM PST 24
Peak memory 214144 kb
Host smart-524029a7-1510-4f95-b2e1-62668270cd28
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262623977 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.3262623977
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_err.2519174462
Short name T561
Test name
Test status
Simulation time 24664144 ps
CPU time 0.85 seconds
Started Jan 07 12:40:46 PM PST 24
Finished Jan 07 12:41:48 PM PST 24
Peak memory 215724 kb
Host smart-1bcd7109-3450-4317-acd3-f7797f6e2f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519174462 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.2519174462
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.335096746
Short name T340
Test name
Test status
Simulation time 14958074 ps
CPU time 0.95 seconds
Started Jan 07 12:40:36 PM PST 24
Finished Jan 07 12:41:37 PM PST 24
Peak memory 205508 kb
Host smart-ef5d2781-952f-424a-a775-1ab0e15ff0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335096746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.335096746
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.2420100202
Short name T391
Test name
Test status
Simulation time 22516655 ps
CPU time 0.85 seconds
Started Jan 07 12:40:43 PM PST 24
Finished Jan 07 12:41:49 PM PST 24
Peak memory 214480 kb
Host smart-2abd6bbe-0b8d-4f5f-8bfe-670d328aa9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420100202 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.2420100202
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.316205406
Short name T487
Test name
Test status
Simulation time 34957303 ps
CPU time 0.84 seconds
Started Jan 07 12:40:11 PM PST 24
Finished Jan 07 12:41:25 PM PST 24
Peak memory 204860 kb
Host smart-cc1d487d-a3e3-49dd-af3c-e8c354259e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316205406 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.316205406
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.1346671608
Short name T714
Test name
Test status
Simulation time 375317864 ps
CPU time 3.78 seconds
Started Jan 07 12:40:38 PM PST 24
Finished Jan 07 12:41:40 PM PST 24
Peak memory 206060 kb
Host smart-5c84174f-3e6d-4693-b814-65942fbe0c0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346671608 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.1346671608
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/150.edn_genbits.122378270
Short name T622
Test name
Test status
Simulation time 28749269 ps
CPU time 0.95 seconds
Started Jan 07 12:41:44 PM PST 24
Finished Jan 07 12:43:09 PM PST 24
Peak memory 205108 kb
Host smart-e839bfdc-4f97-473e-8114-1e53b58c4f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122378270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.122378270
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.3997145288
Short name T100
Test name
Test status
Simulation time 95439246 ps
CPU time 1.07 seconds
Started Jan 07 12:41:58 PM PST 24
Finished Jan 07 12:43:30 PM PST 24
Peak memory 205292 kb
Host smart-dea628f5-c3cc-407b-b1ba-1b95b5c2222e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997145288 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.3997145288
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.653892712
Short name T409
Test name
Test status
Simulation time 19377107 ps
CPU time 0.99 seconds
Started Jan 07 12:42:06 PM PST 24
Finished Jan 07 12:43:42 PM PST 24
Peak memory 205096 kb
Host smart-736aada6-e380-48bd-8c46-878c0921238e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653892712 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.653892712
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.1714365781
Short name T657
Test name
Test status
Simulation time 39665640 ps
CPU time 1.57 seconds
Started Jan 07 12:42:12 PM PST 24
Finished Jan 07 12:43:36 PM PST 24
Peak memory 214272 kb
Host smart-b5683641-8ade-42d0-809e-6ae00f1b8911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714365781 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1714365781
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.3063527539
Short name T718
Test name
Test status
Simulation time 26524656 ps
CPU time 0.95 seconds
Started Jan 07 12:41:39 PM PST 24
Finished Jan 07 12:43:20 PM PST 24
Peak memory 205172 kb
Host smart-fa6a6b12-3165-482e-887b-78febd75c9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063527539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.3063527539
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.104155989
Short name T415
Test name
Test status
Simulation time 64842189 ps
CPU time 0.95 seconds
Started Jan 07 12:41:58 PM PST 24
Finished Jan 07 12:43:27 PM PST 24
Peak memory 205300 kb
Host smart-e5373228-f8d4-457b-9dbb-43dd27f2f197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104155989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.104155989
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.2631670695
Short name T580
Test name
Test status
Simulation time 26032400 ps
CPU time 0.98 seconds
Started Jan 07 12:41:50 PM PST 24
Finished Jan 07 12:43:39 PM PST 24
Peak memory 214156 kb
Host smart-94225157-4f61-4571-b288-ec84e91c7151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631670695 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.2631670695
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.1899906284
Short name T728
Test name
Test status
Simulation time 32845383 ps
CPU time 1.02 seconds
Started Jan 07 12:41:38 PM PST 24
Finished Jan 07 12:43:03 PM PST 24
Peak memory 205708 kb
Host smart-f5f9e328-b102-40c4-86e2-7b57952dcb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899906284 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.1899906284
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.1754141248
Short name T545
Test name
Test status
Simulation time 29316397 ps
CPU time 0.91 seconds
Started Jan 07 12:40:15 PM PST 24
Finished Jan 07 12:41:25 PM PST 24
Peak memory 205208 kb
Host smart-eafadde4-7fe2-4c3c-b1e8-035cd78f2acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754141248 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.1754141248
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.1028603811
Short name T317
Test name
Test status
Simulation time 34099707 ps
CPU time 0.76 seconds
Started Jan 07 12:40:11 PM PST 24
Finished Jan 07 12:41:24 PM PST 24
Peak memory 204216 kb
Host smart-51979c89-8099-445a-b5fb-fb6bba0fef16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028603811 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.1028603811
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.1797652301
Short name T355
Test name
Test status
Simulation time 14838989 ps
CPU time 0.79 seconds
Started Jan 07 12:40:22 PM PST 24
Finished Jan 07 12:41:35 PM PST 24
Peak memory 214148 kb
Host smart-c889b5d5-7196-4fad-8b05-36a03402d567
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797652301 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.1797652301
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_err.1148405850
Short name T84
Test name
Test status
Simulation time 18786928 ps
CPU time 1.07 seconds
Started Jan 07 12:40:07 PM PST 24
Finished Jan 07 12:41:16 PM PST 24
Peak memory 215764 kb
Host smart-fe203c5f-1e20-4f87-bab6-33ab6d26e665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148405850 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.1148405850
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.636559954
Short name T39
Test name
Test status
Simulation time 120180295 ps
CPU time 1.11 seconds
Started Jan 07 12:40:48 PM PST 24
Finished Jan 07 12:42:01 PM PST 24
Peak memory 205480 kb
Host smart-7a89d0e2-815c-4455-a0bf-5c83d08cd8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636559954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.636559954
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.2518302447
Short name T658
Test name
Test status
Simulation time 80276070 ps
CPU time 0.78 seconds
Started Jan 07 12:40:49 PM PST 24
Finished Jan 07 12:41:51 PM PST 24
Peak memory 214348 kb
Host smart-441952e3-c562-4fa7-9d80-deb6bee0c5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518302447 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.2518302447
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_stress_all.709932946
Short name T640
Test name
Test status
Simulation time 347661380 ps
CPU time 3.49 seconds
Started Jan 07 12:39:59 PM PST 24
Finished Jan 07 12:41:19 PM PST 24
Peak memory 205640 kb
Host smart-e6db60f2-581c-4912-9037-60dc016addf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709932946 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.709932946
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/160.edn_genbits.1802585597
Short name T552
Test name
Test status
Simulation time 36926284 ps
CPU time 1.03 seconds
Started Jan 07 12:41:37 PM PST 24
Finished Jan 07 12:43:00 PM PST 24
Peak memory 214328 kb
Host smart-eda7f09a-9a58-437a-a415-b6298a26c793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802585597 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1802585597
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.3098509984
Short name T285
Test name
Test status
Simulation time 18867998 ps
CPU time 0.85 seconds
Started Jan 07 12:42:02 PM PST 24
Finished Jan 07 12:43:24 PM PST 24
Peak memory 204832 kb
Host smart-84a61afc-4b3d-468a-ac88-89029dc4a475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098509984 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.3098509984
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.3849079544
Short name T404
Test name
Test status
Simulation time 88413890 ps
CPU time 0.93 seconds
Started Jan 07 12:42:37 PM PST 24
Finished Jan 07 12:43:57 PM PST 24
Peak memory 214092 kb
Host smart-cf121e64-1ffa-4a9d-8843-7a6ec9d56e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849079544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3849079544
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.2608759660
Short name T275
Test name
Test status
Simulation time 191075921 ps
CPU time 1 seconds
Started Jan 07 12:42:05 PM PST 24
Finished Jan 07 12:43:25 PM PST 24
Peak memory 205096 kb
Host smart-7ae4150b-a4a4-4c18-a4ba-c024e64e9c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608759660 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.2608759660
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.2242863319
Short name T418
Test name
Test status
Simulation time 30152730 ps
CPU time 1.25 seconds
Started Jan 07 12:42:18 PM PST 24
Finished Jan 07 12:43:34 PM PST 24
Peak memory 205328 kb
Host smart-3b0b285d-4fc6-4ddf-8d1f-6651bd543bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242863319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.2242863319
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.324000318
Short name T560
Test name
Test status
Simulation time 32433839 ps
CPU time 0.96 seconds
Started Jan 07 12:42:08 PM PST 24
Finished Jan 07 12:43:47 PM PST 24
Peak memory 205364 kb
Host smart-2b574d45-ac75-4afe-adf8-95cd568bbd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324000318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.324000318
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.3085462814
Short name T93
Test name
Test status
Simulation time 178167687 ps
CPU time 2.47 seconds
Started Jan 07 12:42:42 PM PST 24
Finished Jan 07 12:44:17 PM PST 24
Peak memory 214036 kb
Host smart-6b0ec9c0-7acd-49d6-9fa1-34e78eabbb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085462814 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.3085462814
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.3625727551
Short name T195
Test name
Test status
Simulation time 43184971 ps
CPU time 0.9 seconds
Started Jan 07 12:40:43 PM PST 24
Finished Jan 07 12:42:13 PM PST 24
Peak memory 205268 kb
Host smart-485d40fa-8881-418c-bfbd-943606d57213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625727551 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.3625727551
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.2780271193
Short name T397
Test name
Test status
Simulation time 37166500 ps
CPU time 0.78 seconds
Started Jan 07 12:40:22 PM PST 24
Finished Jan 07 12:41:27 PM PST 24
Peak memory 204380 kb
Host smart-2568064f-5935-4f03-94f2-4a41ed6d17a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780271193 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.2780271193
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.4083279892
Short name T40
Test name
Test status
Simulation time 19226897 ps
CPU time 0.79 seconds
Started Jan 07 12:40:19 PM PST 24
Finished Jan 07 12:41:22 PM PST 24
Peak memory 214088 kb
Host smart-4baf19cc-73bd-4202-9474-01f52a8132ad
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083279892 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.4083279892
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.3692111509
Short name T625
Test name
Test status
Simulation time 48644880 ps
CPU time 1.02 seconds
Started Jan 07 12:40:14 PM PST 24
Finished Jan 07 12:41:18 PM PST 24
Peak memory 214540 kb
Host smart-8f3dc119-209e-47f7-909a-69f99c81c0e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692111509 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.3692111509
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_genbits.3914259400
Short name T350
Test name
Test status
Simulation time 18986508 ps
CPU time 1.05 seconds
Started Jan 07 12:40:52 PM PST 24
Finished Jan 07 12:41:53 PM PST 24
Peak memory 214160 kb
Host smart-51e34ed7-c962-481e-9861-53c15e6f80a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914259400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3914259400
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_smoke.2608342686
Short name T436
Test name
Test status
Simulation time 25779398 ps
CPU time 0.84 seconds
Started Jan 07 12:40:41 PM PST 24
Finished Jan 07 12:41:46 PM PST 24
Peak memory 204732 kb
Host smart-3337ef2d-50e7-402a-8cb4-bcd7b12d1844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608342686 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.2608342686
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.672980842
Short name T446
Test name
Test status
Simulation time 60177739 ps
CPU time 1.75 seconds
Started Jan 07 12:41:09 PM PST 24
Finished Jan 07 12:42:42 PM PST 24
Peak memory 205748 kb
Host smart-943bd37b-0fdf-499f-92e1-e268cca442c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672980842 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.672980842
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.1519174495
Short name T662
Test name
Test status
Simulation time 28373412600 ps
CPU time 344.66 seconds
Started Jan 07 12:40:54 PM PST 24
Finished Jan 07 12:47:57 PM PST 24
Peak memory 214372 kb
Host smart-ce6f4634-8099-41f9-893a-60b9acc9febc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519174495 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.1519174495
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.2457686797
Short name T89
Test name
Test status
Simulation time 21736477 ps
CPU time 1.07 seconds
Started Jan 07 12:42:37 PM PST 24
Finished Jan 07 12:43:55 PM PST 24
Peak memory 205932 kb
Host smart-d2300870-e474-4cf9-b074-961612dbb59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457686797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.2457686797
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.3896325062
Short name T509
Test name
Test status
Simulation time 48066650 ps
CPU time 0.84 seconds
Started Jan 07 12:42:10 PM PST 24
Finished Jan 07 12:43:27 PM PST 24
Peak memory 204868 kb
Host smart-541e79ba-22f1-4cc8-875b-ae1e4e0be07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896325062 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.3896325062
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.157656149
Short name T654
Test name
Test status
Simulation time 16721158 ps
CPU time 0.96 seconds
Started Jan 07 12:42:19 PM PST 24
Finished Jan 07 12:43:40 PM PST 24
Peak memory 205224 kb
Host smart-0dc3b5ff-5e49-4592-8380-16874098bd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157656149 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.157656149
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.2820216951
Short name T476
Test name
Test status
Simulation time 21554085 ps
CPU time 0.85 seconds
Started Jan 07 12:42:07 PM PST 24
Finished Jan 07 12:43:25 PM PST 24
Peak memory 205056 kb
Host smart-b0798ec4-661c-45c4-9376-0d347b3ccfbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820216951 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.2820216951
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.3571527463
Short name T615
Test name
Test status
Simulation time 38087566 ps
CPU time 1.69 seconds
Started Jan 07 12:42:31 PM PST 24
Finished Jan 07 12:44:08 PM PST 24
Peak memory 214168 kb
Host smart-9385dd8b-0776-47e7-b00c-705403e4a49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571527463 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.3571527463
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.2368812259
Short name T240
Test name
Test status
Simulation time 57487894 ps
CPU time 0.89 seconds
Started Jan 07 12:42:08 PM PST 24
Finished Jan 07 12:43:51 PM PST 24
Peak memory 205100 kb
Host smart-25a3f0b1-7d20-4fda-98f2-d80dc8cace41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368812259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.2368812259
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.891043358
Short name T221
Test name
Test status
Simulation time 20063877 ps
CPU time 0.95 seconds
Started Jan 07 12:40:44 PM PST 24
Finished Jan 07 12:42:25 PM PST 24
Peak memory 205264 kb
Host smart-0498f2d2-398e-4188-a2d9-211219d1b9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891043358 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.891043358
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.2195929286
Short name T394
Test name
Test status
Simulation time 39791234 ps
CPU time 0.75 seconds
Started Jan 07 12:40:10 PM PST 24
Finished Jan 07 12:41:43 PM PST 24
Peak memory 204220 kb
Host smart-9277f8c2-1757-418b-86f7-017038b7bf00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195929286 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2195929286
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.2636028219
Short name T7
Test name
Test status
Simulation time 13006565 ps
CPU time 0.81 seconds
Started Jan 07 12:40:18 PM PST 24
Finished Jan 07 12:41:23 PM PST 24
Peak memory 214148 kb
Host smart-7bdff937-2f86-4658-853a-36282e8bd25a
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636028219 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2636028219
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_err.3850983303
Short name T399
Test name
Test status
Simulation time 43215824 ps
CPU time 0.79 seconds
Started Jan 07 12:40:43 PM PST 24
Finished Jan 07 12:42:34 PM PST 24
Peak memory 215576 kb
Host smart-336726f7-3b88-49b8-a7ed-883b38b5db73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850983303 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.3850983303
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.3281278891
Short name T284
Test name
Test status
Simulation time 21967095 ps
CPU time 1.03 seconds
Started Jan 07 12:40:43 PM PST 24
Finished Jan 07 12:42:28 PM PST 24
Peak memory 205212 kb
Host smart-14bb28b5-6318-4dd1-bfe3-7f5bf620109b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281278891 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.3281278891
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.691112625
Short name T751
Test name
Test status
Simulation time 21313381 ps
CPU time 1.16 seconds
Started Jan 07 12:40:44 PM PST 24
Finished Jan 07 12:41:57 PM PST 24
Peak memory 221812 kb
Host smart-9c5234a2-01f3-42e3-955c-223ef71aa3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691112625 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.691112625
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_stress_all.1910365278
Short name T430
Test name
Test status
Simulation time 286286014 ps
CPU time 1.35 seconds
Started Jan 07 12:40:09 PM PST 24
Finished Jan 07 12:41:22 PM PST 24
Peak memory 204920 kb
Host smart-bb63872f-fd81-41f4-a5d3-88d4146ce2a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910365278 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1910365278
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.2110328036
Short name T553
Test name
Test status
Simulation time 373206406774 ps
CPU time 917.02 seconds
Started Jan 07 12:40:39 PM PST 24
Finished Jan 07 12:56:53 PM PST 24
Peak memory 216292 kb
Host smart-4cc7ae18-a7d9-4e0c-8e09-c8084ebfbee6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110328036 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.2110328036
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.2281118516
Short name T712
Test name
Test status
Simulation time 33453701 ps
CPU time 0.91 seconds
Started Jan 07 12:42:35 PM PST 24
Finished Jan 07 12:43:59 PM PST 24
Peak memory 205296 kb
Host smart-a9c4849f-6441-44e4-b7d3-da17bd89d5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281118516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.2281118516
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.3875587962
Short name T216
Test name
Test status
Simulation time 16759910 ps
CPU time 1.02 seconds
Started Jan 07 12:42:31 PM PST 24
Finished Jan 07 12:44:05 PM PST 24
Peak memory 205484 kb
Host smart-830e55ad-033b-4b22-979f-cee214f9a49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875587962 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.3875587962
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.2981970753
Short name T252
Test name
Test status
Simulation time 481116223 ps
CPU time 2.76 seconds
Started Jan 07 12:42:07 PM PST 24
Finished Jan 07 12:43:45 PM PST 24
Peak memory 214164 kb
Host smart-f649d550-2d49-436c-a025-612a06222b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981970753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.2981970753
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.645920614
Short name T467
Test name
Test status
Simulation time 67069262 ps
CPU time 1.55 seconds
Started Jan 07 12:42:07 PM PST 24
Finished Jan 07 12:43:31 PM PST 24
Peak memory 214168 kb
Host smart-e8af3d16-a775-484f-a4fb-abccb63b4a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645920614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.645920614
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.2063885265
Short name T716
Test name
Test status
Simulation time 21170689 ps
CPU time 0.84 seconds
Started Jan 07 12:42:02 PM PST 24
Finished Jan 07 12:43:25 PM PST 24
Peak memory 204900 kb
Host smart-a3f553ff-9a92-4455-a8f0-7c30ab3ded68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063885265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.2063885265
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.1228079742
Short name T213
Test name
Test status
Simulation time 28000206 ps
CPU time 0.99 seconds
Started Jan 07 12:42:39 PM PST 24
Finished Jan 07 12:43:56 PM PST 24
Peak memory 205636 kb
Host smart-c29c72ba-2d3f-40fa-8035-1d22242f33ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228079742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.1228079742
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.2141201618
Short name T735
Test name
Test status
Simulation time 16033946 ps
CPU time 0.92 seconds
Started Jan 07 12:42:33 PM PST 24
Finished Jan 07 12:44:00 PM PST 24
Peak memory 204784 kb
Host smart-9d2b294d-a1e8-49b2-8841-1cb2b7a621d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141201618 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.2141201618
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_disable.847616313
Short name T721
Test name
Test status
Simulation time 30500054 ps
CPU time 0.8 seconds
Started Jan 07 12:40:42 PM PST 24
Finished Jan 07 12:41:50 PM PST 24
Peak memory 214456 kb
Host smart-5a55c29f-481d-4141-973a-34b79a66dcd7
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847616313 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.847616313
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_err.817566846
Short name T468
Test name
Test status
Simulation time 20572259 ps
CPU time 1.06 seconds
Started Jan 07 12:40:53 PM PST 24
Finished Jan 07 12:42:09 PM PST 24
Peak memory 215624 kb
Host smart-581279a4-6990-4ca2-b1a7-932d9ef6f055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817566846 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.817566846
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.2041302697
Short name T400
Test name
Test status
Simulation time 31828046 ps
CPU time 0.8 seconds
Started Jan 07 12:40:17 PM PST 24
Finished Jan 07 12:41:38 PM PST 24
Peak memory 204972 kb
Host smart-eb6b317b-5c8c-4920-a744-a8ca7a5bd613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041302697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.2041302697
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_smoke.1394992994
Short name T158
Test name
Test status
Simulation time 31486935 ps
CPU time 0.84 seconds
Started Jan 07 12:40:56 PM PST 24
Finished Jan 07 12:42:06 PM PST 24
Peak memory 204908 kb
Host smart-70027e84-8daa-4bc2-a863-cbc98ba5e9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394992994 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.1394992994
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.1148186481
Short name T639
Test name
Test status
Simulation time 152502269 ps
CPU time 3.47 seconds
Started Jan 07 12:40:54 PM PST 24
Finished Jan 07 12:42:15 PM PST 24
Peak memory 205964 kb
Host smart-e5dbd1ca-59c3-4585-bd92-4c9baa32906d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148186481 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.1148186481
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/190.edn_genbits.4159232149
Short name T488
Test name
Test status
Simulation time 31048707 ps
CPU time 0.92 seconds
Started Jan 07 12:42:13 PM PST 24
Finished Jan 07 12:43:35 PM PST 24
Peak memory 205616 kb
Host smart-e2186681-f227-4b4e-b965-6dbb1446658a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159232149 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.4159232149
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.3108824014
Short name T334
Test name
Test status
Simulation time 51368484 ps
CPU time 0.86 seconds
Started Jan 07 12:42:06 PM PST 24
Finished Jan 07 12:43:37 PM PST 24
Peak memory 204988 kb
Host smart-c2c663f4-8118-462c-a7fe-4836a2d40920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108824014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.3108824014
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.3100795949
Short name T703
Test name
Test status
Simulation time 15732493 ps
CPU time 0.92 seconds
Started Jan 07 12:42:43 PM PST 24
Finished Jan 07 12:44:14 PM PST 24
Peak memory 205852 kb
Host smart-cbef3bb8-fd01-4d6e-b689-b6a372b243a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100795949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.3100795949
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.944815118
Short name T611
Test name
Test status
Simulation time 32033503 ps
CPU time 0.95 seconds
Started Jan 07 12:42:34 PM PST 24
Finished Jan 07 12:43:47 PM PST 24
Peak memory 205236 kb
Host smart-27e39c07-c6e5-4589-9097-cead5af1017b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944815118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.944815118
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.4104459192
Short name T241
Test name
Test status
Simulation time 36874456 ps
CPU time 1.07 seconds
Started Jan 07 12:42:34 PM PST 24
Finished Jan 07 12:44:03 PM PST 24
Peak memory 214164 kb
Host smart-03883653-8ed7-4700-9b5a-e7d6e2819b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104459192 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.4104459192
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.1918733047
Short name T456
Test name
Test status
Simulation time 14244721 ps
CPU time 0.85 seconds
Started Jan 07 12:42:35 PM PST 24
Finished Jan 07 12:43:55 PM PST 24
Peak memory 205012 kb
Host smart-7291d0f5-33ed-4241-a9ff-c3940c06d07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918733047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.1918733047
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.1742103187
Short name T318
Test name
Test status
Simulation time 42090031 ps
CPU time 0.99 seconds
Started Jan 07 12:42:37 PM PST 24
Finished Jan 07 12:44:16 PM PST 24
Peak memory 205356 kb
Host smart-ece2d2cd-e5fd-4ff7-9839-ce6461238c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742103187 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.1742103187
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert_test.25864496
Short name T300
Test name
Test status
Simulation time 28240523 ps
CPU time 0.88 seconds
Started Jan 07 12:40:09 PM PST 24
Finished Jan 07 12:41:27 PM PST 24
Peak memory 204604 kb
Host smart-e14f9bcf-921d-4b2c-9aa3-f3bc2dd4b526
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25864496 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.25864496
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.1056710392
Short name T522
Test name
Test status
Simulation time 22391417 ps
CPU time 0.79 seconds
Started Jan 07 12:40:23 PM PST 24
Finished Jan 07 12:41:38 PM PST 24
Peak memory 214276 kb
Host smart-2a7590ab-f18b-46db-a6a9-c919d57d86d5
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056710392 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.1056710392
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.4125011438
Short name T704
Test name
Test status
Simulation time 280774218 ps
CPU time 0.95 seconds
Started Jan 07 12:39:57 PM PST 24
Finished Jan 07 12:41:22 PM PST 24
Peak memory 214532 kb
Host smart-76c88796-7163-4423-988a-f48780759ab0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125011438 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.4125011438
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.2517323183
Short name T322
Test name
Test status
Simulation time 30376904 ps
CPU time 0.79 seconds
Started Jan 07 12:40:07 PM PST 24
Finished Jan 07 12:41:30 PM PST 24
Peak memory 215632 kb
Host smart-27cbd163-5ecf-40bb-a994-8fcc9f031234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517323183 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.2517323183
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.726185858
Short name T209
Test name
Test status
Simulation time 93461948 ps
CPU time 1.1 seconds
Started Jan 07 12:39:48 PM PST 24
Finished Jan 07 12:41:23 PM PST 24
Peak memory 214224 kb
Host smart-69e9eb16-fc14-43f8-a89b-9a0d73e532ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726185858 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.726185858
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.643488653
Short name T58
Test name
Test status
Simulation time 19962212 ps
CPU time 0.98 seconds
Started Jan 07 12:40:47 PM PST 24
Finished Jan 07 12:42:00 PM PST 24
Peak memory 225480 kb
Host smart-3a22fa1f-686f-422e-92a6-e506e20ea298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643488653 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.643488653
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_sec_cm.1134987251
Short name T32
Test name
Test status
Simulation time 698456667 ps
CPU time 5.19 seconds
Started Jan 07 12:40:05 PM PST 24
Finished Jan 07 12:41:29 PM PST 24
Peak memory 234504 kb
Host smart-b57f3874-a2fa-44e9-903a-9ce6341ef861
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134987251 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.1134987251
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.1517151796
Short name T656
Test name
Test status
Simulation time 39226121 ps
CPU time 0.8 seconds
Started Jan 07 12:41:12 PM PST 24
Finished Jan 07 12:42:19 PM PST 24
Peak memory 204656 kb
Host smart-22749b79-75f1-4b4d-a7a1-b47a9dd9f75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517151796 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.1517151796
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_alert.505469920
Short name T224
Test name
Test status
Simulation time 103068567 ps
CPU time 0.95 seconds
Started Jan 07 12:41:05 PM PST 24
Finished Jan 07 12:42:31 PM PST 24
Peak memory 205944 kb
Host smart-d00f033a-58a8-469f-920a-d78442d2bee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505469920 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.505469920
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.2168919649
Short name T3
Test name
Test status
Simulation time 27956793 ps
CPU time 0.82 seconds
Started Jan 07 12:40:43 PM PST 24
Finished Jan 07 12:41:44 PM PST 24
Peak memory 205156 kb
Host smart-a066332f-a1d1-4bad-97c8-a4f8774de93e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168919649 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.2168919649
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.3811987308
Short name T353
Test name
Test status
Simulation time 35885306 ps
CPU time 0.81 seconds
Started Jan 07 12:40:18 PM PST 24
Finished Jan 07 12:41:19 PM PST 24
Peak memory 214348 kb
Host smart-0de9052f-9da7-4807-b48f-732afcd480a3
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811987308 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.3811987308
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.3466884772
Short name T123
Test name
Test status
Simulation time 58175507 ps
CPU time 0.94 seconds
Started Jan 07 12:40:45 PM PST 24
Finished Jan 07 12:41:55 PM PST 24
Peak memory 214620 kb
Host smart-2a9a4999-403c-4adf-b0d9-2f13d48d139e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466884772 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.3466884772
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.2053777525
Short name T525
Test name
Test status
Simulation time 70179466 ps
CPU time 0.98 seconds
Started Jan 07 12:40:48 PM PST 24
Finished Jan 07 12:42:16 PM PST 24
Peak memory 214648 kb
Host smart-fedca17e-2378-410c-b55b-0e64a2767442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053777525 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.2053777525
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_smoke.1863449512
Short name T534
Test name
Test status
Simulation time 24040931 ps
CPU time 0.89 seconds
Started Jan 07 12:40:53 PM PST 24
Finished Jan 07 12:42:07 PM PST 24
Peak memory 204732 kb
Host smart-3350cd2a-9954-402c-a6b9-f876f6a81573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863449512 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.1863449512
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.3719553476
Short name T466
Test name
Test status
Simulation time 84737398 ps
CPU time 2.05 seconds
Started Jan 07 12:40:42 PM PST 24
Finished Jan 07 12:41:40 PM PST 24
Peak memory 206000 kb
Host smart-aa365b12-d252-491f-97b2-e56b4c4651e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719553476 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.3719553476
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.195859442
Short name T741
Test name
Test status
Simulation time 27596070873 ps
CPU time 669.77 seconds
Started Jan 07 12:40:50 PM PST 24
Finished Jan 07 12:53:26 PM PST 24
Peak memory 214468 kb
Host smart-21b969db-4036-4e9d-91fe-b9cb2b28ca40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195859442 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.195859442
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.3690640825
Short name T278
Test name
Test status
Simulation time 29253975 ps
CPU time 0.9 seconds
Started Jan 07 12:42:36 PM PST 24
Finished Jan 07 12:43:53 PM PST 24
Peak memory 205248 kb
Host smart-5555f8de-7ef3-4981-88d1-d6979cd5909d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690640825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.3690640825
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.4106591791
Short name T349
Test name
Test status
Simulation time 72247201 ps
CPU time 1.03 seconds
Started Jan 07 12:42:33 PM PST 24
Finished Jan 07 12:43:54 PM PST 24
Peak memory 205432 kb
Host smart-b10ee307-a23c-4534-a3e5-e3adbeb6dc5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106591791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.4106591791
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.3761592413
Short name T264
Test name
Test status
Simulation time 43171364 ps
CPU time 0.9 seconds
Started Jan 07 12:42:30 PM PST 24
Finished Jan 07 12:44:03 PM PST 24
Peak memory 204864 kb
Host smart-951d15e0-7482-4ea5-9e49-0660f1cf4c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761592413 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.3761592413
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.2399575278
Short name T624
Test name
Test status
Simulation time 203308502 ps
CPU time 2.73 seconds
Started Jan 07 12:42:34 PM PST 24
Finished Jan 07 12:43:49 PM PST 24
Peak memory 214156 kb
Host smart-de8fbd69-23ae-47a2-8ff9-688b8c98c19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399575278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2399575278
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.3933841978
Short name T675
Test name
Test status
Simulation time 85245211 ps
CPU time 0.93 seconds
Started Jan 07 12:42:33 PM PST 24
Finished Jan 07 12:43:54 PM PST 24
Peak memory 214240 kb
Host smart-75e19dfd-b78b-4ac9-af93-6edb546c40b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933841978 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.3933841978
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.4014837785
Short name T573
Test name
Test status
Simulation time 20872525 ps
CPU time 1.03 seconds
Started Jan 07 12:42:34 PM PST 24
Finished Jan 07 12:44:08 PM PST 24
Peak memory 205816 kb
Host smart-cc64b3a0-b0d6-4a42-be07-61e4cc4db563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014837785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.4014837785
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.3135801903
Short name T726
Test name
Test status
Simulation time 16455204 ps
CPU time 1.08 seconds
Started Jan 07 12:42:11 PM PST 24
Finished Jan 07 12:43:33 PM PST 24
Peak memory 214288 kb
Host smart-41e9b6d6-9c67-452e-86d6-b4595d05d424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135801903 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.3135801903
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.995485856
Short name T398
Test name
Test status
Simulation time 16177717 ps
CPU time 0.97 seconds
Started Jan 07 12:42:09 PM PST 24
Finished Jan 07 12:43:40 PM PST 24
Peak memory 205408 kb
Host smart-2d5b9551-c3f1-419e-b03b-77e762fecff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995485856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.995485856
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.2107313014
Short name T668
Test name
Test status
Simulation time 33986923 ps
CPU time 1.1 seconds
Started Jan 07 12:42:06 PM PST 24
Finished Jan 07 12:43:27 PM PST 24
Peak memory 214208 kb
Host smart-6a603164-345a-4624-bdc3-65a1dbcdb42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107313014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.2107313014
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.1082927774
Short name T222
Test name
Test status
Simulation time 17449348 ps
CPU time 0.95 seconds
Started Jan 07 12:40:21 PM PST 24
Finished Jan 07 12:41:38 PM PST 24
Peak memory 205356 kb
Host smart-d96ea4c0-8b37-4d71-a106-b9b998f4160f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082927774 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.1082927774
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.1781833352
Short name T574
Test name
Test status
Simulation time 149563185 ps
CPU time 0.87 seconds
Started Jan 07 12:40:49 PM PST 24
Finished Jan 07 12:41:55 PM PST 24
Peak memory 205136 kb
Host smart-235bd4ef-b75c-4aa8-bba2-0f57c683dfb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781833352 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.1781833352
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.3895106911
Short name T587
Test name
Test status
Simulation time 13948588 ps
CPU time 0.89 seconds
Started Jan 07 12:40:24 PM PST 24
Finished Jan 07 12:41:37 PM PST 24
Peak memory 214560 kb
Host smart-8539fa9c-da1f-4a6d-a16d-55ab9ffbfe43
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895106911 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.3895106911
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.2161454221
Short name T483
Test name
Test status
Simulation time 33181222 ps
CPU time 0.93 seconds
Started Jan 07 12:40:52 PM PST 24
Finished Jan 07 12:41:52 PM PST 24
Peak memory 214452 kb
Host smart-f6eb00bd-7650-4950-8030-6073c72d778b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161454221 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.2161454221
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_genbits.2109824070
Short name T211
Test name
Test status
Simulation time 21182962 ps
CPU time 0.99 seconds
Started Jan 07 12:40:49 PM PST 24
Finished Jan 07 12:42:01 PM PST 24
Peak memory 205192 kb
Host smart-d9985fb5-cde9-4abc-9aed-d0993cc35b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109824070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.2109824070
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.541619233
Short name T724
Test name
Test status
Simulation time 34824624 ps
CPU time 0.81 seconds
Started Jan 07 12:40:40 PM PST 24
Finished Jan 07 12:42:32 PM PST 24
Peak memory 214132 kb
Host smart-ca878996-b0e0-46de-868c-e15903d27eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541619233 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.541619233
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.152410595
Short name T627
Test name
Test status
Simulation time 38614410 ps
CPU time 0.82 seconds
Started Jan 07 12:40:50 PM PST 24
Finished Jan 07 12:42:26 PM PST 24
Peak memory 204744 kb
Host smart-cc124089-1cde-47f2-baf3-e378f9050520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152410595 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.152410595
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.3723784871
Short name T481
Test name
Test status
Simulation time 167068794 ps
CPU time 3.75 seconds
Started Jan 07 12:40:27 PM PST 24
Finished Jan 07 12:41:31 PM PST 24
Peak memory 205952 kb
Host smart-f69ff31e-42dd-4b17-9cd1-9303a3e3277c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723784871 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.3723784871
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.1427545221
Short name T255
Test name
Test status
Simulation time 14975547832 ps
CPU time 350.65 seconds
Started Jan 07 12:40:44 PM PST 24
Finished Jan 07 12:47:36 PM PST 24
Peak memory 215588 kb
Host smart-5344bb04-dd2a-4615-ac7a-0e4971b11ddc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427545221 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.1427545221
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.797900813
Short name T396
Test name
Test status
Simulation time 12550015 ps
CPU time 0.89 seconds
Started Jan 07 12:42:35 PM PST 24
Finished Jan 07 12:43:54 PM PST 24
Peak memory 205156 kb
Host smart-9925e072-34a7-4a39-b9e9-e08c63befa15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797900813 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.797900813
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.1222024828
Short name T276
Test name
Test status
Simulation time 37285334 ps
CPU time 1.35 seconds
Started Jan 07 12:42:04 PM PST 24
Finished Jan 07 12:43:27 PM PST 24
Peak memory 205904 kb
Host smart-bbca12bf-43ef-4d45-a456-30d0bd05283e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222024828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.1222024828
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.3162115264
Short name T554
Test name
Test status
Simulation time 253324039 ps
CPU time 1.26 seconds
Started Jan 07 12:42:11 PM PST 24
Finished Jan 07 12:43:50 PM PST 24
Peak memory 214176 kb
Host smart-5f00bf7a-bfa6-415c-8219-5bc7579ecafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162115264 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.3162115264
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.3032535163
Short name T581
Test name
Test status
Simulation time 43638389 ps
CPU time 0.98 seconds
Started Jan 07 12:42:10 PM PST 24
Finished Jan 07 12:43:53 PM PST 24
Peak memory 214168 kb
Host smart-4c5b25bc-4085-4227-ba10-a89d0ed5bacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032535163 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.3032535163
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.2960122307
Short name T576
Test name
Test status
Simulation time 5046408576 ps
CPU time 86.5 seconds
Started Jan 07 12:42:05 PM PST 24
Finished Jan 07 12:44:44 PM PST 24
Peak memory 214104 kb
Host smart-fb0098cc-3e6e-461b-baa9-18b6d8de7da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960122307 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.2960122307
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.2766636529
Short name T311
Test name
Test status
Simulation time 19214579 ps
CPU time 0.98 seconds
Started Jan 07 12:42:31 PM PST 24
Finished Jan 07 12:43:46 PM PST 24
Peak memory 205264 kb
Host smart-e675d409-0692-47f6-90ea-f4633dc4bc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766636529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.2766636529
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.1131538735
Short name T672
Test name
Test status
Simulation time 16293666 ps
CPU time 0.97 seconds
Started Jan 07 12:41:12 PM PST 24
Finished Jan 07 12:42:46 PM PST 24
Peak memory 206040 kb
Host smart-d6ee9cf9-bf41-428a-8465-abcd326d159b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131538735 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.1131538735
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_intr.3527700899
Short name T644
Test name
Test status
Simulation time 31156012 ps
CPU time 0.94 seconds
Started Jan 07 12:40:50 PM PST 24
Finished Jan 07 12:42:42 PM PST 24
Peak memory 221896 kb
Host smart-50f301a1-ce4d-4f1b-bfb8-9174d7062653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527700899 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.3527700899
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.2183989216
Short name T35
Test name
Test status
Simulation time 42909741 ps
CPU time 0.9 seconds
Started Jan 07 12:40:43 PM PST 24
Finished Jan 07 12:42:16 PM PST 24
Peak memory 204632 kb
Host smart-d7929131-a983-4fa3-8157-04b1558c18a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183989216 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.2183989216
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.854614492
Short name T512
Test name
Test status
Simulation time 154401111 ps
CPU time 3.57 seconds
Started Jan 07 12:40:34 PM PST 24
Finished Jan 07 12:42:00 PM PST 24
Peak memory 214348 kb
Host smart-bcd49f26-5ada-436a-b67d-d6eace781233
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854614492 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.854614492
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.1450728866
Short name T578
Test name
Test status
Simulation time 206259060893 ps
CPU time 957.2 seconds
Started Jan 07 12:40:53 PM PST 24
Finished Jan 07 12:58:05 PM PST 24
Peak memory 215072 kb
Host smart-6057d096-8147-444a-a021-d63898ae0140
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450728866 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.1450728866
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.53408876
Short name T441
Test name
Test status
Simulation time 4467751284 ps
CPU time 85.27 seconds
Started Jan 07 12:42:35 PM PST 24
Finished Jan 07 12:45:22 PM PST 24
Peak memory 214352 kb
Host smart-a81bd8b9-cc2e-465c-9fc7-bd3d4ee7c7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53408876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.53408876
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.1976771190
Short name T602
Test name
Test status
Simulation time 129526605 ps
CPU time 1.85 seconds
Started Jan 07 12:42:04 PM PST 24
Finished Jan 07 12:43:25 PM PST 24
Peak memory 214160 kb
Host smart-e607e8b9-0a07-41f1-ae94-b53f3d286aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976771190 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.1976771190
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.1974790160
Short name T253
Test name
Test status
Simulation time 135685328 ps
CPU time 1.87 seconds
Started Jan 07 12:42:14 PM PST 24
Finished Jan 07 12:43:48 PM PST 24
Peak memory 214204 kb
Host smart-86968d7d-c3de-4ec9-a2a2-3aa82064206f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974790160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.1974790160
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.566629557
Short name T731
Test name
Test status
Simulation time 22844242 ps
CPU time 1.09 seconds
Started Jan 07 12:42:08 PM PST 24
Finished Jan 07 12:43:49 PM PST 24
Peak memory 214292 kb
Host smart-701fbb8f-0aa7-4dff-a66c-1b773af7d851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566629557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.566629557
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.2870284069
Short name T705
Test name
Test status
Simulation time 17951264 ps
CPU time 1.03 seconds
Started Jan 07 12:42:09 PM PST 24
Finished Jan 07 12:43:57 PM PST 24
Peak memory 214160 kb
Host smart-aa6789fa-643d-4c84-96c6-d14b59ab033d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870284069 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.2870284069
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.3594063324
Short name T392
Test name
Test status
Simulation time 208956277 ps
CPU time 0.98 seconds
Started Jan 07 12:42:37 PM PST 24
Finished Jan 07 12:43:57 PM PST 24
Peak memory 205212 kb
Host smart-83ce6962-b0e4-4f41-8adf-8d5e452e6e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594063324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.3594063324
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.934682
Short name T214
Test name
Test status
Simulation time 17507992 ps
CPU time 1.03 seconds
Started Jan 07 12:42:06 PM PST 24
Finished Jan 07 12:43:42 PM PST 24
Peak memory 205644 kb
Host smart-a995830e-752c-4136-82e3-dc1fc6fcf96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.934682
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.2205966930
Short name T248
Test name
Test status
Simulation time 15189835 ps
CPU time 1.01 seconds
Started Jan 07 12:42:06 PM PST 24
Finished Jan 07 12:43:30 PM PST 24
Peak memory 205412 kb
Host smart-d28f8d36-2441-4076-af5c-4166d12e21b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205966930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.2205966930
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.2109172959
Short name T653
Test name
Test status
Simulation time 123647222 ps
CPU time 0.91 seconds
Started Jan 07 12:42:36 PM PST 24
Finished Jan 07 12:43:53 PM PST 24
Peak memory 205416 kb
Host smart-930fb289-2f2e-466b-b001-e02e3e797df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109172959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.2109172959
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.841828057
Short name T231
Test name
Test status
Simulation time 18914587 ps
CPU time 0.94 seconds
Started Jan 07 12:40:40 PM PST 24
Finished Jan 07 12:42:28 PM PST 24
Peak memory 205232 kb
Host smart-2738196c-8dae-4675-9fc3-8c3cb5ab018f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841828057 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.841828057
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.2661019253
Short name T613
Test name
Test status
Simulation time 26559191 ps
CPU time 0.81 seconds
Started Jan 07 12:40:56 PM PST 24
Finished Jan 07 12:42:12 PM PST 24
Peak memory 204512 kb
Host smart-6a2558b2-0499-4af6-9627-0cbd9bd2e42a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661019253 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.2661019253
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.2740065050
Short name T719
Test name
Test status
Simulation time 10904417 ps
CPU time 0.8 seconds
Started Jan 07 12:41:03 PM PST 24
Finished Jan 07 12:42:29 PM PST 24
Peak memory 214316 kb
Host smart-763e95c2-9270-4b6d-9861-7467cbb0695c
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740065050 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.2740065050
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.305759742
Short name T448
Test name
Test status
Simulation time 57450543 ps
CPU time 0.99 seconds
Started Jan 07 12:40:30 PM PST 24
Finished Jan 07 12:41:34 PM PST 24
Peak memory 214600 kb
Host smart-f1eb23fd-cf3c-488d-9bfa-235d0f1297d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305759742 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_di
sable_auto_req_mode.305759742
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.43386064
Short name T673
Test name
Test status
Simulation time 23611357 ps
CPU time 0.99 seconds
Started Jan 07 12:41:00 PM PST 24
Finished Jan 07 12:42:13 PM PST 24
Peak memory 221796 kb
Host smart-fb50dccc-78d5-4e7f-b0ec-086f403f7e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43386064 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.43386064
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.3665665851
Short name T57
Test name
Test status
Simulation time 45041925 ps
CPU time 1.79 seconds
Started Jan 07 12:40:31 PM PST 24
Finished Jan 07 12:41:41 PM PST 24
Peak memory 214056 kb
Host smart-10d62483-731f-4cea-ac23-2d82411400bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665665851 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.3665665851
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.318060640
Short name T6
Test name
Test status
Simulation time 21187807 ps
CPU time 1.02 seconds
Started Jan 07 12:41:01 PM PST 24
Finished Jan 07 12:42:06 PM PST 24
Peak memory 214476 kb
Host smart-94f4a34a-b925-4d2d-b19f-3bcc1707e614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318060640 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.318060640
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/231.edn_genbits.724863543
Short name T557
Test name
Test status
Simulation time 159907198 ps
CPU time 1.13 seconds
Started Jan 07 12:42:39 PM PST 24
Finished Jan 07 12:43:58 PM PST 24
Peak memory 205776 kb
Host smart-b2863fbc-cba7-47d6-aeca-7989be566bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724863543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.724863543
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.69711071
Short name T346
Test name
Test status
Simulation time 26824744 ps
CPU time 0.99 seconds
Started Jan 07 12:42:34 PM PST 24
Finished Jan 07 12:43:49 PM PST 24
Peak memory 205500 kb
Host smart-63931666-2cd6-4d1a-bec1-7c1da7150238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69711071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.69711071
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.206532110
Short name T523
Test name
Test status
Simulation time 39705807 ps
CPU time 1.02 seconds
Started Jan 07 12:42:11 PM PST 24
Finished Jan 07 12:43:27 PM PST 24
Peak memory 205524 kb
Host smart-6addee8c-942c-4a08-a912-6afb5d5a4186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206532110 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.206532110
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.1159829073
Short name T244
Test name
Test status
Simulation time 17464031 ps
CPU time 1.04 seconds
Started Jan 07 12:42:11 PM PST 24
Finished Jan 07 12:43:45 PM PST 24
Peak memory 205520 kb
Host smart-b713914f-a7e6-411e-a7c5-2d68cd399423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159829073 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.1159829073
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.964130579
Short name T106
Test name
Test status
Simulation time 62466643 ps
CPU time 0.97 seconds
Started Jan 07 12:42:23 PM PST 24
Finished Jan 07 12:43:59 PM PST 24
Peak memory 205488 kb
Host smart-a492f24e-6a2f-404c-8bee-0e5438e9ca30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964130579 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.964130579
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.1604123302
Short name T416
Test name
Test status
Simulation time 215571121 ps
CPU time 2.82 seconds
Started Jan 07 12:42:35 PM PST 24
Finished Jan 07 12:44:01 PM PST 24
Peak memory 214204 kb
Host smart-ff73c760-8e47-4499-8731-219a4a9c7913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604123302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.1604123302
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.3218716724
Short name T555
Test name
Test status
Simulation time 57278442 ps
CPU time 0.99 seconds
Started Jan 07 12:42:36 PM PST 24
Finished Jan 07 12:43:57 PM PST 24
Peak memory 205496 kb
Host smart-d6ed4c91-c14a-4501-9aa6-ef5c1937eb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218716724 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.3218716724
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.1961505582
Short name T227
Test name
Test status
Simulation time 20086950 ps
CPU time 0.94 seconds
Started Jan 07 12:40:54 PM PST 24
Finished Jan 07 12:42:13 PM PST 24
Peak memory 205916 kb
Host smart-f57e3192-578c-4e59-941f-630cfab82ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961505582 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.1961505582
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.2186175916
Short name T472
Test name
Test status
Simulation time 12468507 ps
CPU time 0.81 seconds
Started Jan 07 12:40:55 PM PST 24
Finished Jan 07 12:42:23 PM PST 24
Peak memory 204364 kb
Host smart-8a647656-5ea0-45bd-86d9-14e9ba3f0f3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186175916 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.2186175916
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.1796408425
Short name T124
Test name
Test status
Simulation time 27183341 ps
CPU time 1 seconds
Started Jan 07 12:41:14 PM PST 24
Finished Jan 07 12:42:47 PM PST 24
Peak memory 214552 kb
Host smart-8d9ac395-1451-484b-b73a-2e8de37f5765
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796408425 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.1796408425
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.710321633
Short name T408
Test name
Test status
Simulation time 53836919 ps
CPU time 0.79 seconds
Started Jan 07 12:40:45 PM PST 24
Finished Jan 07 12:42:18 PM PST 24
Peak memory 215684 kb
Host smart-2c98a1df-bbf9-4256-b814-b9e222502d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710321633 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.710321633
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.1064231921
Short name T747
Test name
Test status
Simulation time 17128978 ps
CPU time 0.91 seconds
Started Jan 07 12:40:57 PM PST 24
Finished Jan 07 12:42:37 PM PST 24
Peak memory 205004 kb
Host smart-9a22fc59-a02c-4f89-90ba-88d178bd0fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064231921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1064231921
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.1410190745
Short name T688
Test name
Test status
Simulation time 58862685 ps
CPU time 0.78 seconds
Started Jan 07 12:40:56 PM PST 24
Finished Jan 07 12:42:16 PM PST 24
Peak memory 214376 kb
Host smart-5242f475-d409-404b-b184-e0f2d6afcd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410190745 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.1410190745
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.862981840
Short name T740
Test name
Test status
Simulation time 24222179 ps
CPU time 0.87 seconds
Started Jan 07 12:40:54 PM PST 24
Finished Jan 07 12:42:24 PM PST 24
Peak memory 204836 kb
Host smart-61ff3caa-f7a1-4091-bddd-1313fbda87d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862981840 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.862981840
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.3286705754
Short name T323
Test name
Test status
Simulation time 189193459 ps
CPU time 2.31 seconds
Started Jan 07 12:40:42 PM PST 24
Finished Jan 07 12:41:48 PM PST 24
Peak memory 205864 kb
Host smart-656e8ee9-7590-4dc1-8ab1-ab0e3fd29e15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286705754 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.3286705754
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.1202021277
Short name T677
Test name
Test status
Simulation time 72000287023 ps
CPU time 883.58 seconds
Started Jan 07 12:40:47 PM PST 24
Finished Jan 07 12:57:00 PM PST 24
Peak memory 215472 kb
Host smart-789dbca4-206a-4b9c-a1e2-51145c7d11ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202021277 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1202021277
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.1256421692
Short name T98
Test name
Test status
Simulation time 31816419 ps
CPU time 0.96 seconds
Started Jan 07 12:42:19 PM PST 24
Finished Jan 07 12:43:57 PM PST 24
Peak memory 205520 kb
Host smart-a39a75be-1cf9-47db-a8ed-30f304bf61fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256421692 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.1256421692
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.2320586234
Short name T542
Test name
Test status
Simulation time 73860378 ps
CPU time 0.86 seconds
Started Jan 07 12:42:06 PM PST 24
Finished Jan 07 12:43:27 PM PST 24
Peak memory 204900 kb
Host smart-19f85adb-2230-471f-95aa-0fa5e0342c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320586234 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.2320586234
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.3917675818
Short name T536
Test name
Test status
Simulation time 20186856 ps
CPU time 1.01 seconds
Started Jan 07 12:42:06 PM PST 24
Finished Jan 07 12:43:30 PM PST 24
Peak memory 205416 kb
Host smart-93c1ac86-fb4b-47c5-8a05-62e78fab1896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917675818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.3917675818
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.892423153
Short name T742
Test name
Test status
Simulation time 45360120 ps
CPU time 0.91 seconds
Started Jan 07 12:42:12 PM PST 24
Finished Jan 07 12:43:27 PM PST 24
Peak memory 205204 kb
Host smart-8d9fcd09-4d13-4c9e-b9fa-6a960fdae26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892423153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.892423153
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.441024250
Short name T357
Test name
Test status
Simulation time 108131965 ps
CPU time 0.89 seconds
Started Jan 07 12:42:07 PM PST 24
Finished Jan 07 12:43:36 PM PST 24
Peak memory 205312 kb
Host smart-4c428370-c681-43da-a73f-3da5063f80cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441024250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.441024250
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.123174799
Short name T641
Test name
Test status
Simulation time 21472985 ps
CPU time 1.01 seconds
Started Jan 07 12:42:34 PM PST 24
Finished Jan 07 12:44:11 PM PST 24
Peak memory 205236 kb
Host smart-5e15ade8-3a9b-47a2-af28-f975cf76dbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123174799 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.123174799
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.1688617184
Short name T750
Test name
Test status
Simulation time 22981663 ps
CPU time 1.35 seconds
Started Jan 07 12:42:27 PM PST 24
Finished Jan 07 12:43:49 PM PST 24
Peak memory 205684 kb
Host smart-7abe2f28-2cb4-4a6a-b086-9a9f28f02d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688617184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.1688617184
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.2709597421
Short name T226
Test name
Test status
Simulation time 21969538 ps
CPU time 0.96 seconds
Started Jan 07 12:40:46 PM PST 24
Finished Jan 07 12:41:48 PM PST 24
Peak memory 205124 kb
Host smart-dd5481d7-2ba4-4ddf-ba47-643133dead08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709597421 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.2709597421
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.3845673120
Short name T326
Test name
Test status
Simulation time 70660222 ps
CPU time 0.92 seconds
Started Jan 07 12:41:06 PM PST 24
Finished Jan 07 12:42:23 PM PST 24
Peak memory 204764 kb
Host smart-bf41aec8-c6e1-48db-8c60-c3987be2abed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845673120 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.3845673120
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.75668374
Short name T699
Test name
Test status
Simulation time 30654383 ps
CPU time 1.05 seconds
Started Jan 07 12:40:47 PM PST 24
Finished Jan 07 12:41:52 PM PST 24
Peak memory 214600 kb
Host smart-f2e801ba-e4c9-4a14-b041-783daac8596f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75668374 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_dis
able_auto_req_mode.75668374
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.3436893175
Short name T393
Test name
Test status
Simulation time 42416826 ps
CPU time 1.03 seconds
Started Jan 07 12:40:41 PM PST 24
Finished Jan 07 12:41:42 PM PST 24
Peak memory 216880 kb
Host smart-ea80f60a-a105-47e0-830e-97919a213f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436893175 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.3436893175
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.2828498501
Short name T510
Test name
Test status
Simulation time 42354551 ps
CPU time 1.08 seconds
Started Jan 07 12:40:43 PM PST 24
Finished Jan 07 12:41:44 PM PST 24
Peak memory 205432 kb
Host smart-38cad8b9-914c-4bc0-b863-2875b02213e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828498501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.2828498501
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_smoke.526088237
Short name T34
Test name
Test status
Simulation time 11586785 ps
CPU time 0.84 seconds
Started Jan 07 12:40:24 PM PST 24
Finished Jan 07 12:42:13 PM PST 24
Peak memory 204692 kb
Host smart-8e8a922e-6a64-4210-982f-900061f9ae21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526088237 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.526088237
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.2190280986
Short name T378
Test name
Test status
Simulation time 362625150 ps
CPU time 2.34 seconds
Started Jan 07 12:40:48 PM PST 24
Finished Jan 07 12:42:09 PM PST 24
Peak memory 205748 kb
Host smart-b893d138-dfdc-434c-8317-4bba2144b6c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190280986 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2190280986
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.3261614097
Short name T755
Test name
Test status
Simulation time 38587551205 ps
CPU time 906.04 seconds
Started Jan 07 12:40:50 PM PST 24
Finished Jan 07 12:56:59 PM PST 24
Peak memory 214768 kb
Host smart-d3ccf935-cefd-494f-825d-293bfc844af6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261614097 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.3261614097
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.3904939439
Short name T686
Test name
Test status
Simulation time 14439218 ps
CPU time 0.88 seconds
Started Jan 07 12:42:12 PM PST 24
Finished Jan 07 12:43:55 PM PST 24
Peak memory 204836 kb
Host smart-99ef15e8-11f2-49ba-880f-907dfb6a5a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904939439 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.3904939439
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.4168279350
Short name T501
Test name
Test status
Simulation time 59126034 ps
CPU time 0.93 seconds
Started Jan 07 12:42:24 PM PST 24
Finished Jan 07 12:43:52 PM PST 24
Peak memory 205184 kb
Host smart-ca999d0b-d7f7-4b40-a702-5ba69265f7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168279350 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.4168279350
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.1136622604
Short name T249
Test name
Test status
Simulation time 177080436 ps
CPU time 1 seconds
Started Jan 07 12:42:31 PM PST 24
Finished Jan 07 12:43:46 PM PST 24
Peak memory 205424 kb
Host smart-d831c84b-16bd-40da-92f0-d162cbe27fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136622604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.1136622604
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.3385445593
Short name T667
Test name
Test status
Simulation time 36814137 ps
CPU time 0.94 seconds
Started Jan 07 12:42:30 PM PST 24
Finished Jan 07 12:43:45 PM PST 24
Peak memory 205668 kb
Host smart-9dea9a17-008a-47cf-af1f-7bdbbe6a3e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385445593 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.3385445593
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.921918877
Short name T243
Test name
Test status
Simulation time 23484286 ps
CPU time 1.1 seconds
Started Jan 07 12:42:06 PM PST 24
Finished Jan 07 12:43:38 PM PST 24
Peak memory 214136 kb
Host smart-3b439c14-3da1-4078-8429-f3e80385be95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921918877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.921918877
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.339294081
Short name T610
Test name
Test status
Simulation time 16808399 ps
CPU time 0.94 seconds
Started Jan 07 12:42:34 PM PST 24
Finished Jan 07 12:44:08 PM PST 24
Peak memory 205284 kb
Host smart-3cf8ef71-b14c-491b-a36f-64879965b240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339294081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.339294081
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.1391834
Short name T257
Test name
Test status
Simulation time 34082314 ps
CPU time 1.18 seconds
Started Jan 07 12:42:11 PM PST 24
Finished Jan 07 12:43:27 PM PST 24
Peak memory 205524 kb
Host smart-e629ed65-fa5c-4360-9dac-d6558c03f78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.1391834
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.2669046338
Short name T88
Test name
Test status
Simulation time 22999766 ps
CPU time 1 seconds
Started Jan 07 12:42:02 PM PST 24
Finished Jan 07 12:43:19 PM PST 24
Peak memory 205376 kb
Host smart-f9f6572f-36e4-44ce-8d2b-fa80fa9baf73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669046338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.2669046338
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert_test.3300131484
Short name T337
Test name
Test status
Simulation time 13778775 ps
CPU time 0.84 seconds
Started Jan 07 12:41:00 PM PST 24
Finished Jan 07 12:42:42 PM PST 24
Peak memory 204596 kb
Host smart-68b4f621-8e6c-4a32-a189-7d7bdd55ff4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300131484 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.3300131484
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.3178382360
Short name T290
Test name
Test status
Simulation time 12929211 ps
CPU time 0.86 seconds
Started Jan 07 12:40:29 PM PST 24
Finished Jan 07 12:41:31 PM PST 24
Peak memory 214368 kb
Host smart-fcbc962b-eeac-4048-84f8-d76eecc2fc40
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178382360 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.3178382360
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.3586603203
Short name T739
Test name
Test status
Simulation time 66145632 ps
CPU time 0.92 seconds
Started Jan 07 12:40:41 PM PST 24
Finished Jan 07 12:41:55 PM PST 24
Peak memory 214468 kb
Host smart-19b817ff-f6b5-4e7d-8f18-dfa5639b47bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586603203 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.3586603203
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.65635289
Short name T379
Test name
Test status
Simulation time 23639508 ps
CPU time 0.92 seconds
Started Jan 07 12:40:37 PM PST 24
Finished Jan 07 12:41:34 PM PST 24
Peak memory 214372 kb
Host smart-06b5f804-b5cc-4712-8237-e3e40709dbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65635289 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.65635289
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.165047366
Short name T373
Test name
Test status
Simulation time 25604952 ps
CPU time 0.88 seconds
Started Jan 07 12:40:41 PM PST 24
Finished Jan 07 12:41:48 PM PST 24
Peak memory 205032 kb
Host smart-2e9ea662-432b-4b72-ae0b-721f6e6d1cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165047366 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.165047366
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.260320319
Short name T114
Test name
Test status
Simulation time 21879734 ps
CPU time 0.87 seconds
Started Jan 07 12:40:50 PM PST 24
Finished Jan 07 12:41:57 PM PST 24
Peak memory 214512 kb
Host smart-be98067b-632d-4726-be87-8d560cfe7e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260320319 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.260320319
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.2723702170
Short name T427
Test name
Test status
Simulation time 21234543 ps
CPU time 0.84 seconds
Started Jan 07 12:40:38 PM PST 24
Finished Jan 07 12:41:57 PM PST 24
Peak memory 204684 kb
Host smart-daadd601-a1df-4c5f-b325-2ecfdf0d3893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723702170 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.2723702170
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.1885393631
Short name T45
Test name
Test status
Simulation time 733729396 ps
CPU time 2.93 seconds
Started Jan 07 12:40:41 PM PST 24
Finished Jan 07 12:41:57 PM PST 24
Peak memory 205800 kb
Host smart-ae60c00c-6a35-4cde-85eb-43c885c5ff3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885393631 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.1885393631
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.4162169033
Short name T332
Test name
Test status
Simulation time 145796910685 ps
CPU time 977.1 seconds
Started Jan 07 12:40:54 PM PST 24
Finished Jan 07 12:58:11 PM PST 24
Peak memory 217352 kb
Host smart-19faf882-7f8a-41de-9d13-041f20969285
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162169033 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.4162169033
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.4166143120
Short name T245
Test name
Test status
Simulation time 63970797 ps
CPU time 1.13 seconds
Started Jan 07 12:42:16 PM PST 24
Finished Jan 07 12:43:35 PM PST 24
Peak memory 214200 kb
Host smart-bef89381-5ddb-42a8-b72d-788b0e17c10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166143120 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.4166143120
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.3288001633
Short name T420
Test name
Test status
Simulation time 20660800 ps
CPU time 1.1 seconds
Started Jan 07 12:42:33 PM PST 24
Finished Jan 07 12:43:52 PM PST 24
Peak memory 205464 kb
Host smart-a628d631-4914-428a-8c3b-eeda670ef440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288001633 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.3288001633
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.1051933983
Short name T588
Test name
Test status
Simulation time 280525222 ps
CPU time 4.01 seconds
Started Jan 07 12:42:07 PM PST 24
Finished Jan 07 12:43:38 PM PST 24
Peak memory 214080 kb
Host smart-47c8e473-6223-4aba-836b-75d11fc3ddee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051933983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.1051933983
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.2089058631
Short name T366
Test name
Test status
Simulation time 63341539 ps
CPU time 2.57 seconds
Started Jan 07 12:42:08 PM PST 24
Finished Jan 07 12:43:48 PM PST 24
Peak memory 214148 kb
Host smart-49e81c26-7219-43b1-99b0-384a92e1e49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089058631 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.2089058631
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.801398678
Short name T744
Test name
Test status
Simulation time 22967216 ps
CPU time 1.12 seconds
Started Jan 07 12:42:07 PM PST 24
Finished Jan 07 12:43:22 PM PST 24
Peak memory 214132 kb
Host smart-2d57b3cc-06a9-4aa0-af0b-fa92d5c5d1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801398678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.801398678
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.2782096742
Short name T254
Test name
Test status
Simulation time 39426210 ps
CPU time 1.06 seconds
Started Jan 07 12:42:35 PM PST 24
Finished Jan 07 12:43:54 PM PST 24
Peak memory 214032 kb
Host smart-3f37f4bd-6dc1-4143-a714-3ee24cfe009e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782096742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.2782096742
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.864445503
Short name T504
Test name
Test status
Simulation time 52676063 ps
CPU time 1.38 seconds
Started Jan 07 12:42:36 PM PST 24
Finished Jan 07 12:43:57 PM PST 24
Peak memory 214188 kb
Host smart-b0a922f6-25eb-47bb-8b69-2498a98da787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864445503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.864445503
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.628709451
Short name T79
Test name
Test status
Simulation time 58471643 ps
CPU time 1.16 seconds
Started Jan 07 12:42:05 PM PST 24
Finished Jan 07 12:43:34 PM PST 24
Peak memory 214256 kb
Host smart-21c404d9-88db-408a-ae34-5090200d82f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628709451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.628709451
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.1711778382
Short name T13
Test name
Test status
Simulation time 46577814 ps
CPU time 0.95 seconds
Started Jan 07 12:42:35 PM PST 24
Finished Jan 07 12:43:50 PM PST 24
Peak memory 214248 kb
Host smart-14bc8fd2-c95b-4489-913c-38887434c0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711778382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.1711778382
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert_test.3121004052
Short name T651
Test name
Test status
Simulation time 16400992 ps
CPU time 0.89 seconds
Started Jan 07 12:41:05 PM PST 24
Finished Jan 07 12:42:31 PM PST 24
Peak memory 204592 kb
Host smart-d27b3a9f-9dcf-4a8f-be04-ba8ca14c19c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121004052 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.3121004052
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.57088113
Short name T134
Test name
Test status
Simulation time 20062611 ps
CPU time 0.83 seconds
Started Jan 07 12:40:40 PM PST 24
Finished Jan 07 12:41:50 PM PST 24
Peak memory 214320 kb
Host smart-e9067b28-2b77-4df5-aa7f-6eef0d7abb37
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57088113 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.57088113
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.2888131279
Short name T59
Test name
Test status
Simulation time 45820237 ps
CPU time 1.03 seconds
Started Jan 07 12:40:54 PM PST 24
Finished Jan 07 12:42:04 PM PST 24
Peak memory 214532 kb
Host smart-3da0c8f7-bb46-442d-98b8-142c39c511c4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888131279 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.2888131279
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.3853662064
Short name T727
Test name
Test status
Simulation time 25452497 ps
CPU time 0.97 seconds
Started Jan 07 12:40:56 PM PST 24
Finished Jan 07 12:42:40 PM PST 24
Peak memory 221712 kb
Host smart-a26b4346-ad2a-410c-9ffd-bd5c5b3154ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853662064 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.3853662064
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.284772399
Short name T262
Test name
Test status
Simulation time 19651420 ps
CPU time 0.92 seconds
Started Jan 07 12:40:58 PM PST 24
Finished Jan 07 12:42:42 PM PST 24
Peak memory 204976 kb
Host smart-f76f79ce-3dc6-46da-94bc-20ddf84d770b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284772399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.284772399
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.2908666780
Short name T698
Test name
Test status
Simulation time 19510441 ps
CPU time 0.94 seconds
Started Jan 07 12:41:25 PM PST 24
Finished Jan 07 12:42:38 PM PST 24
Peak memory 214556 kb
Host smart-996a3a87-d784-4c40-8318-f2dddc53f660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908666780 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.2908666780
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.133179558
Short name T83
Test name
Test status
Simulation time 13777010 ps
CPU time 0.86 seconds
Started Jan 07 12:40:23 PM PST 24
Finished Jan 07 12:41:27 PM PST 24
Peak memory 205004 kb
Host smart-ce9dda55-e59f-446a-9dc7-f2719d5eba8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133179558 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.133179558
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/270.edn_genbits.2571494572
Short name T296
Test name
Test status
Simulation time 54466354 ps
CPU time 0.86 seconds
Started Jan 07 12:42:04 PM PST 24
Finished Jan 07 12:43:34 PM PST 24
Peak memory 204932 kb
Host smart-d339d65c-e1a1-4011-93f0-3dd603239cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571494572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2571494572
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.1961039376
Short name T538
Test name
Test status
Simulation time 60705432 ps
CPU time 0.95 seconds
Started Jan 07 12:42:15 PM PST 24
Finished Jan 07 12:43:35 PM PST 24
Peak memory 205188 kb
Host smart-6899e5ef-bf76-4afb-8eac-f66410563d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961039376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.1961039376
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.2741990390
Short name T664
Test name
Test status
Simulation time 254312421 ps
CPU time 1.14 seconds
Started Jan 07 12:42:12 PM PST 24
Finished Jan 07 12:43:42 PM PST 24
Peak memory 214164 kb
Host smart-b787340a-150b-403b-a11c-420d8236725c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741990390 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.2741990390
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.162715948
Short name T732
Test name
Test status
Simulation time 15320118 ps
CPU time 1.04 seconds
Started Jan 07 12:43:11 PM PST 24
Finished Jan 07 12:44:20 PM PST 24
Peak memory 205412 kb
Host smart-1a786e71-8e6c-4f61-bf3b-f7752b7a29e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162715948 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.162715948
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.3478488168
Short name T470
Test name
Test status
Simulation time 60884874 ps
CPU time 1.07 seconds
Started Jan 07 12:43:07 PM PST 24
Finished Jan 07 12:44:15 PM PST 24
Peak memory 205604 kb
Host smart-43e017a8-4457-4714-aafa-c1f76629a2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478488168 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.3478488168
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.4168652299
Short name T377
Test name
Test status
Simulation time 62117358 ps
CPU time 0.93 seconds
Started Jan 07 12:42:56 PM PST 24
Finished Jan 07 12:44:28 PM PST 24
Peak memory 204912 kb
Host smart-90b9ee92-9665-4da9-a5b6-89b544a2c347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168652299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.4168652299
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.2995725591
Short name T604
Test name
Test status
Simulation time 34511413 ps
CPU time 1.14 seconds
Started Jan 07 12:43:07 PM PST 24
Finished Jan 07 12:44:13 PM PST 24
Peak memory 214084 kb
Host smart-ed9a72b3-ab29-4849-90ae-3fb621ea815c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995725591 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.2995725591
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.4182980812
Short name T273
Test name
Test status
Simulation time 33520967 ps
CPU time 1.02 seconds
Started Jan 07 12:42:42 PM PST 24
Finished Jan 07 12:43:53 PM PST 24
Peak memory 205516 kb
Host smart-e68663bf-d577-4771-8a0b-773688890b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182980812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.4182980812
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert_test.775615917
Short name T517
Test name
Test status
Simulation time 67605809 ps
CPU time 0.77 seconds
Started Jan 07 12:41:43 PM PST 24
Finished Jan 07 12:43:15 PM PST 24
Peak memory 204448 kb
Host smart-57de2fa0-6c76-48e0-a273-356adf53fa4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775615917 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.775615917
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.3708032272
Short name T515
Test name
Test status
Simulation time 35328102 ps
CPU time 0.99 seconds
Started Jan 07 12:40:57 PM PST 24
Finished Jan 07 12:42:17 PM PST 24
Peak memory 214588 kb
Host smart-b3422393-7c15-4365-a198-ea553e291f16
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708032272 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.3708032272
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.3476597264
Short name T443
Test name
Test status
Simulation time 28868446 ps
CPU time 1.16 seconds
Started Jan 07 12:41:14 PM PST 24
Finished Jan 07 12:43:06 PM PST 24
Peak memory 217004 kb
Host smart-9c0e9f29-7060-488f-b30f-b49dbe806b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476597264 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.3476597264
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.1046109528
Short name T505
Test name
Test status
Simulation time 15314739 ps
CPU time 0.93 seconds
Started Jan 07 12:41:00 PM PST 24
Finished Jan 07 12:42:25 PM PST 24
Peak memory 204996 kb
Host smart-25ebd1b3-f122-4b31-8293-63daeba483fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046109528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.1046109528
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.3709403747
Short name T293
Test name
Test status
Simulation time 36267286 ps
CPU time 0.83 seconds
Started Jan 07 12:41:27 PM PST 24
Finished Jan 07 12:42:58 PM PST 24
Peak memory 214112 kb
Host smart-407e1faa-e7a1-446d-bb25-d1e642b38dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709403747 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.3709403747
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.239455051
Short name T598
Test name
Test status
Simulation time 34947432 ps
CPU time 0.79 seconds
Started Jan 07 12:41:17 PM PST 24
Finished Jan 07 12:42:48 PM PST 24
Peak memory 204584 kb
Host smart-1e0fecc5-de34-4e92-8489-6ce49028a8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239455051 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.239455051
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.381342009
Short name T643
Test name
Test status
Simulation time 273843133 ps
CPU time 2.89 seconds
Started Jan 07 12:40:48 PM PST 24
Finished Jan 07 12:41:53 PM PST 24
Peak memory 205832 kb
Host smart-1ac4c555-2a54-425e-a2a2-2f2809132557
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381342009 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.381342009
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.205944283
Short name T595
Test name
Test status
Simulation time 47575679785 ps
CPU time 1011.22 seconds
Started Jan 07 12:40:54 PM PST 24
Finished Jan 07 12:59:21 PM PST 24
Peak memory 215544 kb
Host smart-bc1e746d-2b47-4e3e-9879-117afda134fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205944283 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.205944283
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.2289089391
Short name T706
Test name
Test status
Simulation time 75101226 ps
CPU time 0.98 seconds
Started Jan 07 12:42:54 PM PST 24
Finished Jan 07 12:44:02 PM PST 24
Peak memory 205488 kb
Host smart-c7550517-e2e6-4869-9c85-aa17c5d8c264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289089391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.2289089391
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.3481575679
Short name T734
Test name
Test status
Simulation time 15013737 ps
CPU time 0.88 seconds
Started Jan 07 12:42:41 PM PST 24
Finished Jan 07 12:44:16 PM PST 24
Peak memory 204896 kb
Host smart-5533af06-a7cd-4ac4-8ae2-13398426641e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481575679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.3481575679
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.729673632
Short name T215
Test name
Test status
Simulation time 22178789 ps
CPU time 0.94 seconds
Started Jan 07 12:43:17 PM PST 24
Finished Jan 07 12:45:03 PM PST 24
Peak memory 205576 kb
Host smart-3cd72d88-fd82-4dfb-92fb-921c00feb6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729673632 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.729673632
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.3513540096
Short name T401
Test name
Test status
Simulation time 15635156 ps
CPU time 0.94 seconds
Started Jan 07 12:43:01 PM PST 24
Finished Jan 07 12:44:22 PM PST 24
Peak memory 205204 kb
Host smart-083bf3e7-e6a7-4514-99f3-3ca043e58d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513540096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.3513540096
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.942112239
Short name T684
Test name
Test status
Simulation time 216014971 ps
CPU time 2.2 seconds
Started Jan 07 12:43:05 PM PST 24
Finished Jan 07 12:44:31 PM PST 24
Peak memory 214072 kb
Host smart-2d34e4eb-8c8c-4a80-bc7d-25913ec615d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942112239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.942112239
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.1576210131
Short name T590
Test name
Test status
Simulation time 28231591 ps
CPU time 0.98 seconds
Started Jan 07 12:43:34 PM PST 24
Finished Jan 07 12:44:34 PM PST 24
Peak memory 214080 kb
Host smart-3993d607-89b7-42d3-879d-13199239f9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576210131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.1576210131
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.1630317624
Short name T354
Test name
Test status
Simulation time 48744008 ps
CPU time 0.82 seconds
Started Jan 07 12:42:56 PM PST 24
Finished Jan 07 12:44:17 PM PST 24
Peak memory 204816 kb
Host smart-8a379b9d-a7dd-4159-a0ea-fa43a282a96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630317624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.1630317624
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.812120087
Short name T381
Test name
Test status
Simulation time 49037701 ps
CPU time 0.92 seconds
Started Jan 07 12:42:53 PM PST 24
Finished Jan 07 12:44:15 PM PST 24
Peak memory 205000 kb
Host smart-d27d5c9f-9f9b-4fa8-9068-248e12d86437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812120087 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.812120087
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.2468290137
Short name T212
Test name
Test status
Simulation time 19272320 ps
CPU time 1.02 seconds
Started Jan 07 12:43:17 PM PST 24
Finished Jan 07 12:44:49 PM PST 24
Peak memory 214288 kb
Host smart-00f984a0-d988-4756-ab3a-daa0c1955ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468290137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.2468290137
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.3173686433
Short name T18
Test name
Test status
Simulation time 22558208 ps
CPU time 0.99 seconds
Started Jan 07 12:41:19 PM PST 24
Finished Jan 07 12:42:55 PM PST 24
Peak memory 205032 kb
Host smart-906f3aec-687c-4419-b31f-37e2e756b8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173686433 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.3173686433
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_err.3834662787
Short name T4
Test name
Test status
Simulation time 220026323 ps
CPU time 0.99 seconds
Started Jan 07 12:41:37 PM PST 24
Finished Jan 07 12:43:16 PM PST 24
Peak memory 214172 kb
Host smart-b6a2501a-c251-4c81-ac6e-3e9dd52ce2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834662787 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.3834662787
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.2559169883
Short name T748
Test name
Test status
Simulation time 120612745 ps
CPU time 1.32 seconds
Started Jan 07 12:40:58 PM PST 24
Finished Jan 07 12:42:18 PM PST 24
Peak memory 214192 kb
Host smart-96cc9699-0a13-423d-8c91-54f7d49b2e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559169883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.2559169883
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.2772154091
Short name T132
Test name
Test status
Simulation time 35710390 ps
CPU time 0.82 seconds
Started Jan 07 12:40:59 PM PST 24
Finished Jan 07 12:42:18 PM PST 24
Peak memory 214316 kb
Host smart-2fc34126-4eaa-4340-b574-2bf5b4420a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772154091 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.2772154091
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.413910918
Short name T652
Test name
Test status
Simulation time 61031307 ps
CPU time 0.86 seconds
Started Jan 07 12:41:40 PM PST 24
Finished Jan 07 12:43:20 PM PST 24
Peak memory 204812 kb
Host smart-b960da0c-4392-4324-b58a-01f27826bedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413910918 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.413910918
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.2122612003
Short name T256
Test name
Test status
Simulation time 2169189176 ps
CPU time 3.8 seconds
Started Jan 07 12:40:57 PM PST 24
Finished Jan 07 12:42:22 PM PST 24
Peak memory 205964 kb
Host smart-102e870a-966a-4eaa-b13b-0333e24a90f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122612003 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.2122612003
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.2722134499
Short name T475
Test name
Test status
Simulation time 81688470746 ps
CPU time 1831.37 seconds
Started Jan 07 12:41:07 PM PST 24
Finished Jan 07 01:13:07 PM PST 24
Peak memory 220080 kb
Host smart-4ceb3b70-86a5-4d69-9788-f7babd1d58ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722134499 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.2722134499
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/291.edn_genbits.4112071477
Short name T358
Test name
Test status
Simulation time 21726233 ps
CPU time 1.06 seconds
Started Jan 07 12:42:29 PM PST 24
Finished Jan 07 12:43:50 PM PST 24
Peak memory 205584 kb
Host smart-7edf58c7-8558-40e1-a3dd-53b0d040bc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112071477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.4112071477
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.3286348949
Short name T454
Test name
Test status
Simulation time 66682970 ps
CPU time 0.97 seconds
Started Jan 07 12:43:00 PM PST 24
Finished Jan 07 12:44:11 PM PST 24
Peak memory 205216 kb
Host smart-38be26df-ae3b-411f-99a6-ecf9c173c288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286348949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.3286348949
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.1625193459
Short name T313
Test name
Test status
Simulation time 22015672 ps
CPU time 0.92 seconds
Started Jan 07 12:43:03 PM PST 24
Finished Jan 07 12:44:20 PM PST 24
Peak memory 205280 kb
Host smart-48a2871b-4291-42c8-bb1a-8c8ab47cfb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625193459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.1625193459
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.1251332591
Short name T292
Test name
Test status
Simulation time 17853519 ps
CPU time 1.05 seconds
Started Jan 07 12:43:01 PM PST 24
Finished Jan 07 12:44:08 PM PST 24
Peak memory 205120 kb
Host smart-374c9772-2a34-4edd-bc5c-31644fbc22d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251332591 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.1251332591
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.3407474677
Short name T469
Test name
Test status
Simulation time 107386262 ps
CPU time 0.99 seconds
Started Jan 07 12:42:36 PM PST 24
Finished Jan 07 12:43:53 PM PST 24
Peak memory 214168 kb
Host smart-5480f05c-337d-4356-9df6-3debb37da3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407474677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.3407474677
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.321481107
Short name T508
Test name
Test status
Simulation time 74130333 ps
CPU time 1.26 seconds
Started Jan 07 12:42:29 PM PST 24
Finished Jan 07 12:44:14 PM PST 24
Peak memory 205620 kb
Host smart-792171a2-35f0-4a63-85d2-9e0ebd1647a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321481107 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.321481107
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.207631245
Short name T206
Test name
Test status
Simulation time 43832411 ps
CPU time 0.86 seconds
Started Jan 07 12:42:26 PM PST 24
Finished Jan 07 12:43:53 PM PST 24
Peak memory 205464 kb
Host smart-c0920d0d-36e6-443f-899b-e5f47f627280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207631245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.207631245
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.1203054897
Short name T230
Test name
Test status
Simulation time 30431288 ps
CPU time 0.88 seconds
Started Jan 07 12:40:31 PM PST 24
Finished Jan 07 12:41:30 PM PST 24
Peak memory 206052 kb
Host smart-61c72e1c-79b4-45ef-8c8f-548cf9119030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203054897 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.1203054897
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.2833946348
Short name T498
Test name
Test status
Simulation time 85857795 ps
CPU time 1.03 seconds
Started Jan 07 12:39:54 PM PST 24
Finished Jan 07 12:41:44 PM PST 24
Peak memory 214628 kb
Host smart-1d562567-f10f-4034-84ae-90f130d454f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833946348 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.2833946348
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.859020311
Short name T367
Test name
Test status
Simulation time 53378766 ps
CPU time 0.94 seconds
Started Jan 07 12:40:03 PM PST 24
Finished Jan 07 12:41:15 PM PST 24
Peak memory 216004 kb
Host smart-4ac85b38-3555-419f-8751-27546aaedc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859020311 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.859020311
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.3778652191
Short name T567
Test name
Test status
Simulation time 17781316 ps
CPU time 0.98 seconds
Started Jan 07 12:40:19 PM PST 24
Finished Jan 07 12:41:36 PM PST 24
Peak memory 204984 kb
Host smart-dec04419-beea-4175-91d4-903b0938fd08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778652191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.3778652191
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_sec_cm.2456429201
Short name T73
Test name
Test status
Simulation time 171185936 ps
CPU time 3.2 seconds
Started Jan 07 12:40:15 PM PST 24
Finished Jan 07 12:41:57 PM PST 24
Peak memory 233244 kb
Host smart-eb91bd9e-9079-4514-b633-644f22c639e8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456429201 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.2456429201
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.3207779906
Short name T710
Test name
Test status
Simulation time 25536811 ps
CPU time 0.87 seconds
Started Jan 07 12:40:38 PM PST 24
Finished Jan 07 12:41:53 PM PST 24
Peak memory 204704 kb
Host smart-c2a038c0-9336-4092-93b2-e97530042baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207779906 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.3207779906
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.3575892088
Short name T315
Test name
Test status
Simulation time 243167690 ps
CPU time 1.76 seconds
Started Jan 07 12:40:26 PM PST 24
Finished Jan 07 12:41:27 PM PST 24
Peak memory 205936 kb
Host smart-a388c5f4-da8a-47fb-b6d1-bdb9937601dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575892088 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.3575892088
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3833258911
Short name T513
Test name
Test status
Simulation time 74266552336 ps
CPU time 1640.12 seconds
Started Jan 07 12:40:19 PM PST 24
Finished Jan 07 01:08:39 PM PST 24
Peak memory 220636 kb
Host smart-08cb6387-9331-459c-8881-f94c330576c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833258911 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3833258911
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.352722850
Short name T606
Test name
Test status
Simulation time 29321026 ps
CPU time 0.87 seconds
Started Jan 07 12:41:35 PM PST 24
Finished Jan 07 12:42:46 PM PST 24
Peak memory 205192 kb
Host smart-ef2717a0-749a-42c9-a2f3-ff7910f7cfc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352722850 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.352722850
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.62206769
Short name T685
Test name
Test status
Simulation time 15601465 ps
CPU time 0.9 seconds
Started Jan 07 12:41:24 PM PST 24
Finished Jan 07 12:42:45 PM PST 24
Peak memory 205136 kb
Host smart-52dd2216-8e63-4647-bd0e-00c7e3556e35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62206769 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.62206769
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.1212352405
Short name T380
Test name
Test status
Simulation time 28148860 ps
CPU time 0.89 seconds
Started Jan 07 12:41:27 PM PST 24
Finished Jan 07 12:43:34 PM PST 24
Peak memory 214624 kb
Host smart-e4fa038b-4b4a-4717-bdca-68c200069944
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212352405 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.1212352405
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.2311794803
Short name T681
Test name
Test status
Simulation time 37535491 ps
CPU time 0.86 seconds
Started Jan 07 12:41:41 PM PST 24
Finished Jan 07 12:43:13 PM PST 24
Peak memory 216020 kb
Host smart-0ec70edf-be75-4ba9-b25b-122ad3d7370d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311794803 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.2311794803
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.1154075636
Short name T239
Test name
Test status
Simulation time 28415888 ps
CPU time 0.93 seconds
Started Jan 07 12:41:38 PM PST 24
Finished Jan 07 12:43:25 PM PST 24
Peak memory 205036 kb
Host smart-4ac83703-0ca9-472d-a583-d2c8a49e160c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154075636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.1154075636
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.407413182
Short name T616
Test name
Test status
Simulation time 22105070 ps
CPU time 0.86 seconds
Started Jan 07 12:41:09 PM PST 24
Finished Jan 07 12:42:36 PM PST 24
Peak memory 214620 kb
Host smart-28143e84-6aad-4c9d-8756-46043899b869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407413182 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.407413182
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.3159519266
Short name T362
Test name
Test status
Simulation time 26309922 ps
CPU time 0.85 seconds
Started Jan 07 12:41:11 PM PST 24
Finished Jan 07 12:42:41 PM PST 24
Peak memory 204708 kb
Host smart-1d437de6-91ae-45a1-97f7-2a0f1dd9610e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159519266 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.3159519266
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.1919493162
Short name T95
Test name
Test status
Simulation time 1122560673 ps
CPU time 2.31 seconds
Started Jan 07 12:41:14 PM PST 24
Finished Jan 07 12:42:48 PM PST 24
Peak memory 205396 kb
Host smart-73366fcd-b130-443f-9f2f-2dd228143819
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919493162 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.1919493162
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.4020440053
Short name T152
Test name
Test status
Simulation time 47452866777 ps
CPU time 723.32 seconds
Started Jan 07 12:40:54 PM PST 24
Finished Jan 07 12:54:03 PM PST 24
Peak memory 215420 kb
Host smart-43fb19b1-1add-4faa-92cf-a514cec3329d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020440053 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.4020440053
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.2398400400
Short name T500
Test name
Test status
Simulation time 36932471 ps
CPU time 0.97 seconds
Started Jan 07 12:41:16 PM PST 24
Finished Jan 07 12:42:31 PM PST 24
Peak memory 205044 kb
Host smart-02e8484f-c7dd-4ba0-90ef-909c78709d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398400400 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.2398400400
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.2588127990
Short name T405
Test name
Test status
Simulation time 19387333 ps
CPU time 0.91 seconds
Started Jan 07 12:41:14 PM PST 24
Finished Jan 07 12:42:49 PM PST 24
Peak memory 204580 kb
Host smart-c2a3162f-5395-46ae-8863-c4a35b23ac99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588127990 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.2588127990
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.2113018407
Short name T74
Test name
Test status
Simulation time 21191400 ps
CPU time 0.87 seconds
Started Jan 07 12:41:00 PM PST 24
Finished Jan 07 12:42:26 PM PST 24
Peak memory 214304 kb
Host smart-1c931ef8-9553-4403-b496-f695c1b49d80
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113018407 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.2113018407
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.2771222305
Short name T546
Test name
Test status
Simulation time 415664800 ps
CPU time 1 seconds
Started Jan 07 12:41:00 PM PST 24
Finished Jan 07 12:42:06 PM PST 24
Peak memory 214556 kb
Host smart-752ea4ad-bde6-4b80-a23c-ac0b9d07598f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771222305 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.2771222305
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.41345700
Short name T717
Test name
Test status
Simulation time 18872249 ps
CPU time 1.04 seconds
Started Jan 07 12:40:32 PM PST 24
Finished Jan 07 12:41:57 PM PST 24
Peak memory 215532 kb
Host smart-c97a9c0c-9840-450f-882e-85816a56d022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41345700 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.41345700
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.3221083558
Short name T753
Test name
Test status
Simulation time 61759175 ps
CPU time 2.35 seconds
Started Jan 07 12:41:03 PM PST 24
Finished Jan 07 12:42:33 PM PST 24
Peak memory 214252 kb
Host smart-1c135ebb-ac31-47f8-a3d6-43097535c677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221083558 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.3221083558
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.420454314
Short name T435
Test name
Test status
Simulation time 100921955 ps
CPU time 0.79 seconds
Started Jan 07 12:41:03 PM PST 24
Finished Jan 07 12:42:09 PM PST 24
Peak memory 214272 kb
Host smart-a42b4ef8-95aa-4811-8fae-18bb6b8a3bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420454314 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.420454314
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.600187329
Short name T596
Test name
Test status
Simulation time 17795797 ps
CPU time 0.83 seconds
Started Jan 07 12:41:31 PM PST 24
Finished Jan 07 12:43:09 PM PST 24
Peak memory 204712 kb
Host smart-45c5a134-2e62-498d-aed0-905227f0e57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600187329 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.600187329
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.2690386319
Short name T336
Test name
Test status
Simulation time 269733887 ps
CPU time 1.59 seconds
Started Jan 07 12:41:19 PM PST 24
Finished Jan 07 12:42:56 PM PST 24
Peak memory 205448 kb
Host smart-bdc50d87-d766-4558-afb3-762aa09bcaab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690386319 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.2690386319
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.1550827620
Short name T502
Test name
Test status
Simulation time 144160493214 ps
CPU time 1610.69 seconds
Started Jan 07 12:41:40 PM PST 24
Finished Jan 07 01:10:14 PM PST 24
Peak memory 219372 kb
Host smart-b837ddc9-814d-45e1-8ef3-3f3a4b8621e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550827620 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.1550827620
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.3274324808
Short name T220
Test name
Test status
Simulation time 34804521 ps
CPU time 0.98 seconds
Started Jan 07 12:40:51 PM PST 24
Finished Jan 07 12:42:07 PM PST 24
Peak memory 205316 kb
Host smart-e3de298c-6eb4-4928-8c98-7540f169958a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274324808 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.3274324808
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.281317761
Short name T649
Test name
Test status
Simulation time 17275523 ps
CPU time 0.91 seconds
Started Jan 07 12:41:15 PM PST 24
Finished Jan 07 12:42:55 PM PST 24
Peak memory 204592 kb
Host smart-dcce3b38-60fe-436c-ac50-77ab59f492c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281317761 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.281317761
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.393675100
Short name T135
Test name
Test status
Simulation time 13404086 ps
CPU time 0.85 seconds
Started Jan 07 12:40:41 PM PST 24
Finished Jan 07 12:41:50 PM PST 24
Peak memory 214392 kb
Host smart-f6c4f0dc-e370-4846-a7f2-c73aa1c17fdb
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393675100 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.393675100
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.1439457173
Short name T303
Test name
Test status
Simulation time 66809402 ps
CPU time 0.99 seconds
Started Jan 07 12:41:05 PM PST 24
Finished Jan 07 12:42:52 PM PST 24
Peak memory 214572 kb
Host smart-faf14269-c064-4051-bc2e-b6763504876c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439457173 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.1439457173
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.904765802
Short name T650
Test name
Test status
Simulation time 28465898 ps
CPU time 0.84 seconds
Started Jan 07 12:41:24 PM PST 24
Finished Jan 07 12:42:36 PM PST 24
Peak memory 215624 kb
Host smart-d1ab1c40-144f-46d2-9b96-114acf9e00d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904765802 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.904765802
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.984353994
Short name T60
Test name
Test status
Simulation time 25449903 ps
CPU time 1.01 seconds
Started Jan 07 12:41:32 PM PST 24
Finished Jan 07 12:43:24 PM PST 24
Peak memory 205384 kb
Host smart-83b65ad5-4f84-4c41-bcf3-c0dcfa70201f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984353994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.984353994
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.2857475104
Short name T113
Test name
Test status
Simulation time 32064045 ps
CPU time 0.83 seconds
Started Jan 07 12:40:46 PM PST 24
Finished Jan 07 12:42:13 PM PST 24
Peak memory 214364 kb
Host smart-29175c93-4286-494c-80b7-d41a35638075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857475104 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.2857475104
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.3101524970
Short name T343
Test name
Test status
Simulation time 31886719 ps
CPU time 0.88 seconds
Started Jan 07 12:41:09 PM PST 24
Finished Jan 07 12:42:17 PM PST 24
Peak memory 204820 kb
Host smart-0e8b058b-fa3f-44bc-b7da-4a660f2303fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101524970 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.3101524970
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.1186634069
Short name T159
Test name
Test status
Simulation time 377598304 ps
CPU time 4.08 seconds
Started Jan 07 12:40:36 PM PST 24
Finished Jan 07 12:42:29 PM PST 24
Peak memory 205948 kb
Host smart-c1d73f02-af53-4507-ae7f-95ae38b18caf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186634069 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.1186634069
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.4080139512
Short name T151
Test name
Test status
Simulation time 103513522008 ps
CPU time 1061.97 seconds
Started Jan 07 12:40:53 PM PST 24
Finished Jan 07 01:00:09 PM PST 24
Peak memory 216760 kb
Host smart-57ecee62-8d63-4fbc-b883-46c05861f69a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080139512 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.4080139512
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.3344957332
Short name T237
Test name
Test status
Simulation time 28218512 ps
CPU time 0.88 seconds
Started Jan 07 12:41:34 PM PST 24
Finished Jan 07 12:43:01 PM PST 24
Peak memory 205096 kb
Host smart-e52e2555-94fe-44bb-b97d-91aa35e4dd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344957332 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.3344957332
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.3445763019
Short name T283
Test name
Test status
Simulation time 17472594 ps
CPU time 0.89 seconds
Started Jan 07 12:40:56 PM PST 24
Finished Jan 07 12:42:16 PM PST 24
Peak memory 204648 kb
Host smart-25c3d97b-6d52-4a96-80be-0b50a813c992
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445763019 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.3445763019
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.1836312251
Short name T605
Test name
Test status
Simulation time 38097174 ps
CPU time 0.86 seconds
Started Jan 07 12:40:53 PM PST 24
Finished Jan 07 12:42:09 PM PST 24
Peak memory 214260 kb
Host smart-137f0e60-33c6-4900-a0fc-b96efd570ee0
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836312251 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.1836312251
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.725754969
Short name T105
Test name
Test status
Simulation time 27080551 ps
CPU time 1.03 seconds
Started Jan 07 12:41:04 PM PST 24
Finished Jan 07 12:42:36 PM PST 24
Peak memory 214444 kb
Host smart-775c23f7-cb8f-43b3-89e6-3d893e96e241
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725754969 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_di
sable_auto_req_mode.725754969
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.1368408698
Short name T493
Test name
Test status
Simulation time 19873026 ps
CPU time 1.11 seconds
Started Jan 07 12:41:01 PM PST 24
Finished Jan 07 12:42:19 PM PST 24
Peak memory 228352 kb
Host smart-da12c537-3807-44d8-b0c2-f9601129dcca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368408698 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.1368408698
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.901573746
Short name T338
Test name
Test status
Simulation time 20997394 ps
CPU time 0.84 seconds
Started Jan 07 12:40:54 PM PST 24
Finished Jan 07 12:42:13 PM PST 24
Peak memory 205048 kb
Host smart-577e5ac4-5f70-4300-abaa-7f0975986f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901573746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.901573746
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.1686322468
Short name T492
Test name
Test status
Simulation time 29387868 ps
CPU time 0.92 seconds
Started Jan 07 12:41:05 PM PST 24
Finished Jan 07 12:42:31 PM PST 24
Peak memory 221768 kb
Host smart-7dbf5a2a-fe69-4711-a43c-c924ceda55b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686322468 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.1686322468
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.3884315538
Short name T638
Test name
Test status
Simulation time 16184701 ps
CPU time 0.86 seconds
Started Jan 07 12:41:38 PM PST 24
Finished Jan 07 12:42:49 PM PST 24
Peak memory 204904 kb
Host smart-f752d110-10a7-41cb-bbe0-61cf920c2035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884315538 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.3884315538
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.3181596254
Short name T361
Test name
Test status
Simulation time 103149607 ps
CPU time 1.42 seconds
Started Jan 07 12:40:59 PM PST 24
Finished Jan 07 12:42:39 PM PST 24
Peak memory 206008 kb
Host smart-d1fffb49-58cc-4886-bac8-1f709a0fa65a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181596254 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3181596254
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.3222238544
Short name T544
Test name
Test status
Simulation time 145803566262 ps
CPU time 1626.83 seconds
Started Jan 07 12:40:58 PM PST 24
Finished Jan 07 01:09:54 PM PST 24
Peak memory 218972 kb
Host smart-b98a9612-f354-48a2-b85e-54eb1090d1c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222238544 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.3222238544
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.1487000911
Short name T223
Test name
Test status
Simulation time 54110592 ps
CPU time 0.89 seconds
Started Jan 07 12:41:10 PM PST 24
Finished Jan 07 12:42:17 PM PST 24
Peak memory 205080 kb
Host smart-9e434754-dae1-457a-a2e7-afb4ec0e9dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487000911 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.1487000911
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.338651496
Short name T319
Test name
Test status
Simulation time 66025465 ps
CPU time 1.02 seconds
Started Jan 07 12:40:54 PM PST 24
Finished Jan 07 12:42:28 PM PST 24
Peak memory 205128 kb
Host smart-0690c84a-3491-4906-812b-137eddec0dac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338651496 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.338651496
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.224909230
Short name T101
Test name
Test status
Simulation time 42029984 ps
CPU time 0.84 seconds
Started Jan 07 12:41:10 PM PST 24
Finished Jan 07 12:42:17 PM PST 24
Peak memory 214340 kb
Host smart-408bc598-ab20-42be-9583-62c14801c756
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224909230 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.224909230
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.586149651
Short name T128
Test name
Test status
Simulation time 21832528 ps
CPU time 0.93 seconds
Started Jan 07 12:41:42 PM PST 24
Finished Jan 07 12:43:02 PM PST 24
Peak memory 214528 kb
Host smart-65c81dcf-fbb5-4599-b7f5-2bb51c78a715
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586149651 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_di
sable_auto_req_mode.586149651
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.2725667039
Short name T68
Test name
Test status
Simulation time 22244130 ps
CPU time 0.94 seconds
Started Jan 07 12:41:37 PM PST 24
Finished Jan 07 12:43:09 PM PST 24
Peak memory 221212 kb
Host smart-0d87c007-6218-4ec1-859b-0d5beb639945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725667039 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.2725667039
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_smoke.2095670645
Short name T345
Test name
Test status
Simulation time 30980235 ps
CPU time 0.78 seconds
Started Jan 07 12:41:03 PM PST 24
Finished Jan 07 12:42:34 PM PST 24
Peak memory 204944 kb
Host smart-f3f9d241-4318-4445-958f-c19ac30e4e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095670645 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.2095670645
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.3780962746
Short name T46
Test name
Test status
Simulation time 97307277 ps
CPU time 2.27 seconds
Started Jan 07 12:41:19 PM PST 24
Finished Jan 07 12:43:25 PM PST 24
Peak memory 205776 kb
Host smart-bc867a81-f3ae-4d83-87b5-818929b5f5dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780962746 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.3780962746
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_alert.2143297217
Short name T569
Test name
Test status
Simulation time 17426980 ps
CPU time 1.1 seconds
Started Jan 07 12:42:03 PM PST 24
Finished Jan 07 12:43:25 PM PST 24
Peak memory 206052 kb
Host smart-fd8914c0-2dbf-4fc6-9768-019558abdeb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143297217 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.2143297217
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.1873716436
Short name T566
Test name
Test status
Simulation time 57174007 ps
CPU time 0.9 seconds
Started Jan 07 12:41:04 PM PST 24
Finished Jan 07 12:42:34 PM PST 24
Peak memory 204728 kb
Host smart-17e74b01-0bfb-4a2f-8c71-d4368478f8ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873716436 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1873716436
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.3938986094
Short name T655
Test name
Test status
Simulation time 31718293 ps
CPU time 0.98 seconds
Started Jan 07 12:41:08 PM PST 24
Finished Jan 07 12:42:26 PM PST 24
Peak memory 214600 kb
Host smart-d571d13a-b1eb-4dba-af69-5d288745e0f0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938986094 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.3938986094
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.1258797580
Short name T533
Test name
Test status
Simulation time 30991152 ps
CPU time 0.93 seconds
Started Jan 07 12:41:02 PM PST 24
Finished Jan 07 12:42:41 PM PST 24
Peak memory 221564 kb
Host smart-9e1f96ef-5637-42c0-a4c0-c889fecdb682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258797580 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.1258797580
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.1734609532
Short name T42
Test name
Test status
Simulation time 17628216 ps
CPU time 0.94 seconds
Started Jan 07 12:40:59 PM PST 24
Finished Jan 07 12:42:03 PM PST 24
Peak memory 204964 kb
Host smart-4533ebaf-5ad2-4546-8df5-eeff6d6b4ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734609532 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.1734609532
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.444610859
Short name T328
Test name
Test status
Simulation time 22283153 ps
CPU time 1.02 seconds
Started Jan 07 12:41:04 PM PST 24
Finished Jan 07 12:42:40 PM PST 24
Peak memory 214396 kb
Host smart-42b3ef00-cf63-4313-9bab-5c0a16795fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444610859 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.444610859
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_stress_all.2104049548
Short name T511
Test name
Test status
Simulation time 173848007 ps
CPU time 3.19 seconds
Started Jan 07 12:41:07 PM PST 24
Finished Jan 07 12:42:38 PM PST 24
Peak memory 205996 kb
Host smart-0afb7a95-7876-4850-9422-dd71c2f87e85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104049548 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.2104049548
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.1171311379
Short name T528
Test name
Test status
Simulation time 48603374599 ps
CPU time 1049.9 seconds
Started Jan 07 12:41:17 PM PST 24
Finished Jan 07 01:00:18 PM PST 24
Peak memory 214716 kb
Host smart-f1fa8115-6fab-4489-a504-0447bf1a1449
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171311379 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.1171311379
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.21163778
Short name T372
Test name
Test status
Simulation time 68134709 ps
CPU time 0.98 seconds
Started Jan 07 12:40:27 PM PST 24
Finished Jan 07 12:41:45 PM PST 24
Peak memory 205320 kb
Host smart-be4c89b1-c59d-46e6-9f81-3db36ac61543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21163778 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.21163778
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.1107583184
Short name T636
Test name
Test status
Simulation time 15371556 ps
CPU time 0.86 seconds
Started Jan 07 12:41:00 PM PST 24
Finished Jan 07 12:42:19 PM PST 24
Peak memory 204528 kb
Host smart-78cb33c5-6e83-4a08-83b9-4cd9ad766d49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107583184 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.1107583184
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.3812466388
Short name T314
Test name
Test status
Simulation time 10537439 ps
CPU time 0.94 seconds
Started Jan 07 12:40:42 PM PST 24
Finished Jan 07 12:41:42 PM PST 24
Peak memory 214332 kb
Host smart-ff3d0a74-db06-4ea5-9ee4-1e7a5c33d061
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812466388 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.3812466388
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.1524500345
Short name T720
Test name
Test status
Simulation time 394984966 ps
CPU time 1.04 seconds
Started Jan 07 12:40:51 PM PST 24
Finished Jan 07 12:41:57 PM PST 24
Peak memory 214496 kb
Host smart-7725d6c7-e365-4aec-9d16-53f7c88396af
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524500345 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.1524500345
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.3343345038
Short name T676
Test name
Test status
Simulation time 39207685 ps
CPU time 1.06 seconds
Started Jan 07 12:41:04 PM PST 24
Finished Jan 07 12:42:40 PM PST 24
Peak memory 216844 kb
Host smart-59a21e3e-debf-4c8b-84cd-000df1dd54cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343345038 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.3343345038
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.2028597563
Short name T663
Test name
Test status
Simulation time 63911375 ps
CPU time 1 seconds
Started Jan 07 12:41:13 PM PST 24
Finished Jan 07 12:42:55 PM PST 24
Peak memory 205356 kb
Host smart-f36a7ab0-4564-4622-bb79-100ce9ddf5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028597563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.2028597563
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.2369940306
Short name T67
Test name
Test status
Simulation time 20117179 ps
CPU time 1.11 seconds
Started Jan 07 12:41:17 PM PST 24
Finished Jan 07 12:42:40 PM PST 24
Peak memory 221692 kb
Host smart-7a60ba42-cfd0-41d1-92d2-d83d5811e663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369940306 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.2369940306
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.2586057776
Short name T531
Test name
Test status
Simulation time 51712414 ps
CPU time 0.87 seconds
Started Jan 07 12:41:17 PM PST 24
Finished Jan 07 12:42:26 PM PST 24
Peak memory 204736 kb
Host smart-2d1a4ad7-970f-4b3d-8607-ff8a8f657422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586057776 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.2586057776
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.426223198
Short name T81
Test name
Test status
Simulation time 1168144540 ps
CPU time 3.2 seconds
Started Jan 07 12:40:58 PM PST 24
Finished Jan 07 12:42:10 PM PST 24
Peak memory 205980 kb
Host smart-041a578e-7d1c-42cd-9bfb-a037a0036974
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426223198 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.426223198
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.2522766287
Short name T321
Test name
Test status
Simulation time 57002235943 ps
CPU time 1281.65 seconds
Started Jan 07 12:41:15 PM PST 24
Finished Jan 07 01:03:44 PM PST 24
Peak memory 215580 kb
Host smart-358993e0-dbfb-4a91-88a6-01dedc9e4593
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522766287 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.2522766287
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.15145475
Short name T232
Test name
Test status
Simulation time 18070597 ps
CPU time 0.97 seconds
Started Jan 07 12:41:34 PM PST 24
Finished Jan 07 12:42:52 PM PST 24
Peak memory 205960 kb
Host smart-c07dcd05-1590-46fc-ba90-eb504d77612c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15145475 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.15145475
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_disable.12591098
Short name T138
Test name
Test status
Simulation time 27250420 ps
CPU time 0.77 seconds
Started Jan 07 12:41:19 PM PST 24
Finished Jan 07 12:43:18 PM PST 24
Peak memory 214296 kb
Host smart-1865d172-25c4-4f76-8328-b82e85a3a4a3
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12591098 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.12591098
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.2728454930
Short name T575
Test name
Test status
Simulation time 52992993 ps
CPU time 1.02 seconds
Started Jan 07 12:41:17 PM PST 24
Finished Jan 07 12:43:14 PM PST 24
Peak memory 214524 kb
Host smart-0372ea8b-b107-40ca-8f5a-7ee6f9219e0e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728454930 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.2728454930
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.159092720
Short name T341
Test name
Test status
Simulation time 26382391 ps
CPU time 0.89 seconds
Started Jan 07 12:41:00 PM PST 24
Finished Jan 07 12:42:25 PM PST 24
Peak memory 215696 kb
Host smart-44e511e6-f2b2-4372-802e-d4068bc9448a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159092720 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.159092720
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.1881210379
Short name T352
Test name
Test status
Simulation time 174292792 ps
CPU time 1.93 seconds
Started Jan 07 12:40:58 PM PST 24
Finished Jan 07 12:42:23 PM PST 24
Peak memory 214268 kb
Host smart-8249f504-6817-4c40-a229-e63e48211cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881210379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1881210379
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.210546727
Short name T754
Test name
Test status
Simulation time 19529802 ps
CPU time 1.05 seconds
Started Jan 07 12:41:13 PM PST 24
Finished Jan 07 12:42:31 PM PST 24
Peak memory 214484 kb
Host smart-7cc4ccb1-3802-4d61-ae03-5ae188dcedae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210546727 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.210546727
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.207763318
Short name T440
Test name
Test status
Simulation time 46166432 ps
CPU time 0.81 seconds
Started Jan 07 12:41:05 PM PST 24
Finished Jan 07 12:42:14 PM PST 24
Peak memory 204928 kb
Host smart-7672322c-8887-49c4-be60-4a7e4748b20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207763318 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.207763318
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.4019382274
Short name T156
Test name
Test status
Simulation time 684695090 ps
CPU time 3.72 seconds
Started Jan 07 12:40:53 PM PST 24
Finished Jan 07 12:42:11 PM PST 24
Peak memory 205844 kb
Host smart-0b290d54-812b-405a-bd52-f6508f5e8974
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019382274 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.4019382274
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.1908602038
Short name T149
Test name
Test status
Simulation time 1204460885483 ps
CPU time 2446.4 seconds
Started Jan 07 12:41:30 PM PST 24
Finished Jan 07 01:23:27 PM PST 24
Peak memory 222216 kb
Host smart-9a694527-f193-4684-a8b2-11221638a6d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908602038 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.1908602038
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert_test.1287192375
Short name T503
Test name
Test status
Simulation time 42144016 ps
CPU time 0.88 seconds
Started Jan 07 12:41:16 PM PST 24
Finished Jan 07 12:42:52 PM PST 24
Peak memory 204568 kb
Host smart-4dd02024-6a1a-4f48-8ccb-5da3c091c640
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287192375 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.1287192375
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.1708654839
Short name T682
Test name
Test status
Simulation time 11602609 ps
CPU time 0.83 seconds
Started Jan 07 12:41:11 PM PST 24
Finished Jan 07 12:42:50 PM PST 24
Peak memory 214448 kb
Host smart-e59db993-b5ce-4fff-b9d7-fc87f0908639
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708654839 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.1708654839
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.3657271665
Short name T390
Test name
Test status
Simulation time 78491672 ps
CPU time 0.97 seconds
Started Jan 07 12:41:43 PM PST 24
Finished Jan 07 12:43:03 PM PST 24
Peak memory 214652 kb
Host smart-5e6f9501-f6d0-4418-9f3d-570f12e24008
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657271665 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.3657271665
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.2186962000
Short name T69
Test name
Test status
Simulation time 42970530 ps
CPU time 0.92 seconds
Started Jan 07 12:41:10 PM PST 24
Finished Jan 07 12:42:17 PM PST 24
Peak memory 221540 kb
Host smart-80ed3354-8fa7-4fa3-a2b9-407dad06f66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186962000 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.2186962000
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.2783935097
Short name T207
Test name
Test status
Simulation time 61538298 ps
CPU time 0.87 seconds
Started Jan 07 12:41:25 PM PST 24
Finished Jan 07 12:42:40 PM PST 24
Peak memory 204868 kb
Host smart-54403d81-0d5f-4a7e-8bab-a8a7a1a01a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783935097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.2783935097
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_smoke.4262687808
Short name T612
Test name
Test status
Simulation time 41439064 ps
CPU time 0.8 seconds
Started Jan 07 12:41:03 PM PST 24
Finished Jan 07 12:42:35 PM PST 24
Peak memory 204788 kb
Host smart-d767d069-9249-405a-8e6f-2e626fbdfd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262687808 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.4262687808
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.2911680071
Short name T425
Test name
Test status
Simulation time 124929862 ps
CPU time 1.13 seconds
Started Jan 07 12:40:57 PM PST 24
Finished Jan 07 12:42:38 PM PST 24
Peak memory 204560 kb
Host smart-4c096748-bdb8-4d0f-a39f-3fb6ef4c7e0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911680071 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.2911680071
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.2017383560
Short name T329
Test name
Test status
Simulation time 58915460047 ps
CPU time 1312.74 seconds
Started Jan 07 12:41:12 PM PST 24
Finished Jan 07 01:04:40 PM PST 24
Peak memory 216232 kb
Host smart-5ea4ad89-e69d-49b4-a5a1-734404bc7138
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017383560 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.2017383560
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.899070324
Short name T19
Test name
Test status
Simulation time 20413587 ps
CPU time 0.91 seconds
Started Jan 07 12:40:58 PM PST 24
Finished Jan 07 12:42:19 PM PST 24
Peak memory 205236 kb
Host smart-0490f00a-11a1-47f4-b3f8-806dd5936219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899070324 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.899070324
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.2093170097
Short name T287
Test name
Test status
Simulation time 18714707 ps
CPU time 0.88 seconds
Started Jan 07 12:41:12 PM PST 24
Finished Jan 07 12:42:44 PM PST 24
Peak memory 205448 kb
Host smart-e773656a-6c8a-4638-9cbd-66128acec7ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093170097 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.2093170097
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.3612870216
Short name T141
Test name
Test status
Simulation time 13510928 ps
CPU time 0.83 seconds
Started Jan 07 12:41:34 PM PST 24
Finished Jan 07 12:42:53 PM PST 24
Peak memory 214504 kb
Host smart-085e11c0-839c-4559-b935-4feb01f915b2
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612870216 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.3612870216
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.1089075063
Short name T683
Test name
Test status
Simulation time 246055133 ps
CPU time 0.9 seconds
Started Jan 07 12:41:00 PM PST 24
Finished Jan 07 12:42:25 PM PST 24
Peak memory 214488 kb
Host smart-1c9ac560-b148-403e-9d42-2be1b5016413
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089075063 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.1089075063
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.4060538633
Short name T388
Test name
Test status
Simulation time 29667942 ps
CPU time 1.15 seconds
Started Jan 07 12:41:08 PM PST 24
Finished Jan 07 12:42:14 PM PST 24
Peak memory 217056 kb
Host smart-5d5996e2-71e1-4ef6-a5a4-c073a70c53e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060538633 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.4060538633
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.2458430989
Short name T97
Test name
Test status
Simulation time 21905975 ps
CPU time 1.07 seconds
Started Jan 07 12:41:14 PM PST 24
Finished Jan 07 12:42:34 PM PST 24
Peak memory 205364 kb
Host smart-dfc73082-fa67-4bbd-8e00-ba5191537155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458430989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.2458430989
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.2141385941
Short name T632
Test name
Test status
Simulation time 27633912 ps
CPU time 0.86 seconds
Started Jan 07 12:41:25 PM PST 24
Finished Jan 07 12:43:02 PM PST 24
Peak memory 214540 kb
Host smart-6dc59653-e84a-47ce-b449-e2bbe0e304c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141385941 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.2141385941
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.969585660
Short name T485
Test name
Test status
Simulation time 14276502 ps
CPU time 0.88 seconds
Started Jan 07 12:41:39 PM PST 24
Finished Jan 07 12:43:20 PM PST 24
Peak memory 204624 kb
Host smart-2cb700e8-fda8-42b4-80e1-736d948b0e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969585660 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.969585660
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.2926727194
Short name T78
Test name
Test status
Simulation time 336558676 ps
CPU time 2.28 seconds
Started Jan 07 12:41:40 PM PST 24
Finished Jan 07 12:43:03 PM PST 24
Peak memory 205792 kb
Host smart-3cc317e7-701c-48dd-8033-b1248dc8c874
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926727194 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.2926727194
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.3422047054
Short name T490
Test name
Test status
Simulation time 126733040383 ps
CPU time 2745.96 seconds
Started Jan 07 12:41:05 PM PST 24
Finished Jan 07 01:27:56 PM PST 24
Peak memory 223692 kb
Host smart-7064140c-c9d2-4fea-87ef-838dec23d2d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422047054 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.3422047054
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.2651977840
Short name T233
Test name
Test status
Simulation time 66770280 ps
CPU time 0.93 seconds
Started Jan 07 12:40:03 PM PST 24
Finished Jan 07 12:41:20 PM PST 24
Peak memory 205272 kb
Host smart-0f06fb86-ba27-4799-9f82-d59956ab4900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651977840 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.2651977840
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.2513335443
Short name T324
Test name
Test status
Simulation time 15025005 ps
CPU time 0.86 seconds
Started Jan 07 12:40:19 PM PST 24
Finished Jan 07 12:41:20 PM PST 24
Peak memory 205164 kb
Host smart-987efc7c-e38b-403e-aea5-44ce4b12afdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513335443 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.2513335443
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.748232034
Short name T497
Test name
Test status
Simulation time 21916723 ps
CPU time 0.82 seconds
Started Jan 07 12:39:58 PM PST 24
Finished Jan 07 12:41:35 PM PST 24
Peak memory 214312 kb
Host smart-ce71b6af-e684-4438-a79c-cfa998699b72
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748232034 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.748232034
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_err.19869153
Short name T37
Test name
Test status
Simulation time 20116183 ps
CPU time 0.88 seconds
Started Jan 07 12:40:20 PM PST 24
Finished Jan 07 12:42:32 PM PST 24
Peak memory 215636 kb
Host smart-f5ed14c6-1a87-40fc-8302-37780b50a125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19869153 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.19869153
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.1432183922
Short name T738
Test name
Test status
Simulation time 32546620 ps
CPU time 1.02 seconds
Started Jan 07 12:40:41 PM PST 24
Finished Jan 07 12:42:07 PM PST 24
Peak memory 205624 kb
Host smart-b4f09187-d1cc-482f-9e98-b3a703c16eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432183922 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1432183922
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_regwen.3038767002
Short name T200
Test name
Test status
Simulation time 32378332 ps
CPU time 0.84 seconds
Started Jan 07 12:39:57 PM PST 24
Finished Jan 07 12:41:22 PM PST 24
Peak memory 204668 kb
Host smart-d69bea3a-4f83-48d3-a8d9-e3206b3c50b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038767002 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.3038767002
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_smoke.2992337515
Short name T495
Test name
Test status
Simulation time 111269269 ps
CPU time 0.82 seconds
Started Jan 07 12:39:48 PM PST 24
Finished Jan 07 12:41:01 PM PST 24
Peak memory 204920 kb
Host smart-41d7cd18-988e-46d5-868e-6f0a3447123c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992337515 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.2992337515
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.788585051
Short name T406
Test name
Test status
Simulation time 354788443 ps
CPU time 1.75 seconds
Started Jan 07 12:40:19 PM PST 24
Finished Jan 07 12:41:20 PM PST 24
Peak memory 205920 kb
Host smart-c0346206-a55d-4470-9429-10b567efcffc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788585051 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.788585051
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.2075369111
Short name T333
Test name
Test status
Simulation time 875635360813 ps
CPU time 1864.06 seconds
Started Jan 07 12:40:08 PM PST 24
Finished Jan 07 01:12:51 PM PST 24
Peak memory 222008 kb
Host smart-64a9f8bf-9b0f-4969-a244-88dfcce79491
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075369111 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.2075369111
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.2033294251
Short name T51
Test name
Test status
Simulation time 35307207 ps
CPU time 0.92 seconds
Started Jan 07 12:41:35 PM PST 24
Finished Jan 07 12:43:14 PM PST 24
Peak memory 205924 kb
Host smart-26b78edc-762e-4544-8d63-64186d39dd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033294251 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.2033294251
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_disable.358748590
Short name T459
Test name
Test status
Simulation time 13343481 ps
CPU time 0.87 seconds
Started Jan 07 12:41:05 PM PST 24
Finished Jan 07 12:42:31 PM PST 24
Peak memory 214628 kb
Host smart-d4f1e40f-ff45-4bae-a088-995169d2d48e
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358748590 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.358748590
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.553908838
Short name T126
Test name
Test status
Simulation time 90662991 ps
CPU time 0.98 seconds
Started Jan 07 12:41:45 PM PST 24
Finished Jan 07 12:43:05 PM PST 24
Peak memory 206312 kb
Host smart-63d8d2b8-6fcb-437c-b335-a6c247f2b342
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553908838 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_di
sable_auto_req_mode.553908838
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_genbits.3980753553
Short name T44
Test name
Test status
Simulation time 194727770 ps
CPU time 2.82 seconds
Started Jan 07 12:41:12 PM PST 24
Finished Jan 07 12:42:42 PM PST 24
Peak memory 214112 kb
Host smart-e5ee05ca-a2f0-44b3-8157-1c0892e2e465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980753553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.3980753553
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.1146501869
Short name T110
Test name
Test status
Simulation time 25864880 ps
CPU time 0.8 seconds
Started Jan 07 12:41:15 PM PST 24
Finished Jan 07 12:42:34 PM PST 24
Peak memory 214292 kb
Host smart-344a8af0-ae17-4b9c-88bc-2022deb96ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146501869 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.1146501869
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.3413580197
Short name T477
Test name
Test status
Simulation time 24327652 ps
CPU time 0.84 seconds
Started Jan 07 12:41:43 PM PST 24
Finished Jan 07 12:42:55 PM PST 24
Peak memory 204824 kb
Host smart-c0321d13-7f49-43a5-ae38-928ed44278f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413580197 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.3413580197
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.1349483178
Short name T700
Test name
Test status
Simulation time 564283365 ps
CPU time 3.98 seconds
Started Jan 07 12:41:12 PM PST 24
Finished Jan 07 12:42:34 PM PST 24
Peak memory 205944 kb
Host smart-fc190f95-410d-4dbe-befa-bfc8d3928e47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349483178 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.1349483178
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.554290047
Short name T626
Test name
Test status
Simulation time 47932572662 ps
CPU time 354.57 seconds
Started Jan 07 12:40:58 PM PST 24
Finished Jan 07 12:48:10 PM PST 24
Peak memory 215204 kb
Host smart-c72abc89-7b81-41f0-8f6d-749b87bf298d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554290047 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.554290047
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.3047762629
Short name T194
Test name
Test status
Simulation time 80491075 ps
CPU time 0.94 seconds
Started Jan 07 12:41:17 PM PST 24
Finished Jan 07 12:43:09 PM PST 24
Peak memory 205204 kb
Host smart-785d1d7b-2c55-4d36-ac09-27fbdc7bb43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047762629 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.3047762629
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.1300440113
Short name T63
Test name
Test status
Simulation time 164978153 ps
CPU time 0.93 seconds
Started Jan 07 12:41:05 PM PST 24
Finished Jan 07 12:42:18 PM PST 24
Peak memory 205192 kb
Host smart-ebaa8858-c335-41e9-a01d-f94cc3d92c08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300440113 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.1300440113
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.596383493
Short name T582
Test name
Test status
Simulation time 42724964 ps
CPU time 0.83 seconds
Started Jan 07 12:41:12 PM PST 24
Finished Jan 07 12:42:59 PM PST 24
Peak memory 214380 kb
Host smart-d9856cf1-6767-460c-a3e0-45da83f81a39
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596383493 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.596383493
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.2619027632
Short name T384
Test name
Test status
Simulation time 51858903 ps
CPU time 0.89 seconds
Started Jan 07 12:41:13 PM PST 24
Finished Jan 07 12:42:44 PM PST 24
Peak memory 214552 kb
Host smart-5e045e9d-852d-464e-8422-f4ae60d348f8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619027632 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.2619027632
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.2149934079
Short name T584
Test name
Test status
Simulation time 35422741 ps
CPU time 1.29 seconds
Started Jan 07 12:41:26 PM PST 24
Finished Jan 07 12:42:47 PM PST 24
Peak memory 214788 kb
Host smart-e85f7a97-f7d4-4b03-9cff-f1c5d8cc9600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149934079 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2149934079
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.972623177
Short name T36
Test name
Test status
Simulation time 19427255 ps
CPU time 0.95 seconds
Started Jan 07 12:41:07 PM PST 24
Finished Jan 07 12:42:36 PM PST 24
Peak memory 205180 kb
Host smart-bd201ac8-3034-46c2-839f-9d6bc4549a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972623177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.972623177
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.4289321611
Short name T371
Test name
Test status
Simulation time 45038498 ps
CPU time 0.91 seconds
Started Jan 07 12:41:17 PM PST 24
Finished Jan 07 12:42:37 PM PST 24
Peak memory 221604 kb
Host smart-ca25e6e8-dc61-4fb7-bc4a-c1b1d6371893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289321611 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.4289321611
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.1005129984
Short name T527
Test name
Test status
Simulation time 52505546 ps
CPU time 0.82 seconds
Started Jan 07 12:41:45 PM PST 24
Finished Jan 07 12:43:02 PM PST 24
Peak memory 204620 kb
Host smart-be5c1184-dd04-467a-bd10-d73b0d2f2c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005129984 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.1005129984
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.4063897511
Short name T491
Test name
Test status
Simulation time 369425417 ps
CPU time 3.58 seconds
Started Jan 07 12:41:10 PM PST 24
Finished Jan 07 12:42:20 PM PST 24
Peak memory 206036 kb
Host smart-e2a018a1-373c-493d-b84a-305e4aa95e09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063897511 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.4063897511
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.191853975
Short name T147
Test name
Test status
Simulation time 41578023960 ps
CPU time 149.83 seconds
Started Jan 07 12:41:11 PM PST 24
Finished Jan 07 12:44:49 PM PST 24
Peak memory 214468 kb
Host smart-217d9551-d488-4f87-91a9-602707ab8c78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191853975 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.191853975
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.3833757471
Short name T197
Test name
Test status
Simulation time 33058443 ps
CPU time 0.9 seconds
Started Jan 07 12:41:20 PM PST 24
Finished Jan 07 12:42:29 PM PST 24
Peak memory 205352 kb
Host smart-157885d1-90b7-4d1c-8ad0-6c500e63ecb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833757471 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.3833757471
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.1057402446
Short name T70
Test name
Test status
Simulation time 18530955 ps
CPU time 0.91 seconds
Started Jan 07 12:40:58 PM PST 24
Finished Jan 07 12:42:11 PM PST 24
Peak memory 204580 kb
Host smart-cbf883fa-4fe6-4049-8c42-169f2e6724ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057402446 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.1057402446
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.702040214
Short name T723
Test name
Test status
Simulation time 68917973 ps
CPU time 0.78 seconds
Started Jan 07 12:41:10 PM PST 24
Finished Jan 07 12:42:16 PM PST 24
Peak memory 214280 kb
Host smart-ed3483e8-e770-46a7-8b0b-076d1fcf6316
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702040214 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.702040214
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.1384665833
Short name T104
Test name
Test status
Simulation time 30321991 ps
CPU time 1.01 seconds
Started Jan 07 12:41:05 PM PST 24
Finished Jan 07 12:42:31 PM PST 24
Peak memory 214476 kb
Host smart-eeaa3e9a-66c0-4d3d-af83-48ac09a80183
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384665833 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.1384665833
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_genbits.3939567464
Short name T730
Test name
Test status
Simulation time 459184958 ps
CPU time 3.49 seconds
Started Jan 07 12:41:01 PM PST 24
Finished Jan 07 12:42:43 PM PST 24
Peak memory 214164 kb
Host smart-544d2b24-3fd5-459b-806d-5a8b3fc24c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939567464 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.3939567464
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.2399333117
Short name T306
Test name
Test status
Simulation time 48519510 ps
CPU time 0.84 seconds
Started Jan 07 12:41:11 PM PST 24
Finished Jan 07 12:42:40 PM PST 24
Peak memory 214356 kb
Host smart-2b7cb46d-c397-442c-b953-b613e71263cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399333117 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.2399333117
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.2878915770
Short name T288
Test name
Test status
Simulation time 16827855 ps
CPU time 0.91 seconds
Started Jan 07 12:41:01 PM PST 24
Finished Jan 07 12:42:26 PM PST 24
Peak memory 204616 kb
Host smart-d57fb842-6095-49ef-bab3-f2773e9594d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878915770 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.2878915770
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.653687343
Short name T119
Test name
Test status
Simulation time 198152802 ps
CPU time 4.24 seconds
Started Jan 07 12:41:05 PM PST 24
Finished Jan 07 12:42:27 PM PST 24
Peak memory 206120 kb
Host smart-4b256e2c-c33e-4511-a674-0bd6a25507b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653687343 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.653687343
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_alert.2966896225
Short name T693
Test name
Test status
Simulation time 21018187 ps
CPU time 0.96 seconds
Started Jan 07 12:41:22 PM PST 24
Finished Jan 07 12:42:42 PM PST 24
Peak memory 205960 kb
Host smart-af7cf3e6-0ce0-4bfd-b562-c121d6d1b71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966896225 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2966896225
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.2512664113
Short name T660
Test name
Test status
Simulation time 169968786 ps
CPU time 0.91 seconds
Started Jan 07 12:41:31 PM PST 24
Finished Jan 07 12:43:23 PM PST 24
Peak memory 205556 kb
Host smart-8cdc89f8-38e6-4111-b067-2de670f3abd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512664113 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.2512664113
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.1957991475
Short name T519
Test name
Test status
Simulation time 16213544 ps
CPU time 0.91 seconds
Started Jan 07 12:41:44 PM PST 24
Finished Jan 07 12:43:13 PM PST 24
Peak memory 214412 kb
Host smart-a95019cd-6e04-43b1-88df-bcf034984929
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957991475 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.1957991475
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.3442330488
Short name T551
Test name
Test status
Simulation time 21814623 ps
CPU time 0.98 seconds
Started Jan 07 12:41:08 PM PST 24
Finished Jan 07 12:42:24 PM PST 24
Peak memory 214504 kb
Host smart-173449d4-99f4-465d-818d-fcc029612f22
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442330488 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.3442330488
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.2677986944
Short name T707
Test name
Test status
Simulation time 115284105 ps
CPU time 1.02 seconds
Started Jan 07 12:41:36 PM PST 24
Finished Jan 07 12:42:52 PM PST 24
Peak memory 215984 kb
Host smart-79909663-f9a2-42de-bd5a-cb013e9ae188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677986944 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.2677986944
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.280704220
Short name T671
Test name
Test status
Simulation time 34171730 ps
CPU time 1.11 seconds
Started Jan 07 12:41:13 PM PST 24
Finished Jan 07 12:42:59 PM PST 24
Peak memory 214152 kb
Host smart-63e675fb-fd9b-4f5b-bdae-b80078e2deca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280704220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.280704220
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_smoke.2553645182
Short name T374
Test name
Test status
Simulation time 19177580 ps
CPU time 0.81 seconds
Started Jan 07 12:41:22 PM PST 24
Finished Jan 07 12:42:53 PM PST 24
Peak memory 204740 kb
Host smart-23df3f10-717b-4844-9c2d-e21a746c3a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553645182 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.2553645182
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.1021906922
Short name T601
Test name
Test status
Simulation time 132870846 ps
CPU time 1.11 seconds
Started Jan 07 12:41:17 PM PST 24
Finished Jan 07 12:43:03 PM PST 24
Peak memory 205140 kb
Host smart-778ac7ce-d207-49f9-b062-0f12cd29f1c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021906922 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1021906922
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.2971923709
Short name T507
Test name
Test status
Simulation time 40855651699 ps
CPU time 904.18 seconds
Started Jan 07 12:41:41 PM PST 24
Finished Jan 07 12:57:56 PM PST 24
Peak memory 214376 kb
Host smart-8368d39f-d14c-4380-9ec1-3c0e0ae1b154
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971923709 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.2971923709
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.1770826905
Short name T38
Test name
Test status
Simulation time 16880018 ps
CPU time 0.92 seconds
Started Jan 07 12:41:07 PM PST 24
Finished Jan 07 12:42:49 PM PST 24
Peak memory 205244 kb
Host smart-d21eaebf-143f-4354-b06a-dc928f716f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770826905 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.1770826905
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_disable.1016630994
Short name T365
Test name
Test status
Simulation time 17451348 ps
CPU time 0.81 seconds
Started Jan 07 12:41:39 PM PST 24
Finished Jan 07 12:43:05 PM PST 24
Peak memory 214352 kb
Host smart-b37ba9f3-1816-4c7d-b934-10dcee8fb965
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016630994 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.1016630994
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.3376034123
Short name T127
Test name
Test status
Simulation time 16388493 ps
CPU time 0.88 seconds
Started Jan 07 12:41:05 PM PST 24
Finished Jan 07 12:42:31 PM PST 24
Peak memory 214568 kb
Host smart-5796af61-97e6-47bd-a707-e2b885ce57c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376034123 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.3376034123
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.4061864887
Short name T666
Test name
Test status
Simulation time 28813511 ps
CPU time 0.8 seconds
Started Jan 07 12:41:38 PM PST 24
Finished Jan 07 12:43:02 PM PST 24
Peak memory 215536 kb
Host smart-f04a5765-a468-4222-a191-5c5418508620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061864887 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.4061864887
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.4112077175
Short name T272
Test name
Test status
Simulation time 19673929 ps
CPU time 0.86 seconds
Started Jan 07 12:41:16 PM PST 24
Finished Jan 07 12:43:00 PM PST 24
Peak memory 204896 kb
Host smart-29d7cff0-23ba-49c5-93b9-1b97a94a3dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112077175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.4112077175
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.3916475622
Short name T111
Test name
Test status
Simulation time 22392241 ps
CPU time 0.89 seconds
Started Jan 07 12:41:09 PM PST 24
Finished Jan 07 12:42:38 PM PST 24
Peak memory 214484 kb
Host smart-77b9214c-5326-4c8a-b985-204673eec3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916475622 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.3916475622
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.2079481230
Short name T600
Test name
Test status
Simulation time 41973145 ps
CPU time 0.86 seconds
Started Jan 07 12:41:14 PM PST 24
Finished Jan 07 12:43:10 PM PST 24
Peak memory 204712 kb
Host smart-19ac1531-e053-4e30-a371-e8915eaefca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079481230 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.2079481230
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.3054697418
Short name T356
Test name
Test status
Simulation time 348120339 ps
CPU time 1.16 seconds
Started Jan 07 12:41:45 PM PST 24
Finished Jan 07 12:43:03 PM PST 24
Peak memory 205524 kb
Host smart-f0d3d8ba-9ccc-4865-865a-2b2b68d572b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054697418 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.3054697418
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_alert_test.2766265915
Short name T743
Test name
Test status
Simulation time 46404973 ps
CPU time 0.96 seconds
Started Jan 07 12:41:15 PM PST 24
Finished Jan 07 12:42:47 PM PST 24
Peak memory 204696 kb
Host smart-e8c7a8ba-92c3-4164-ad52-d6e9ce47f0f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766265915 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.2766265915
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.3318861044
Short name T133
Test name
Test status
Simulation time 19280513 ps
CPU time 0.8 seconds
Started Jan 07 12:41:28 PM PST 24
Finished Jan 07 12:42:50 PM PST 24
Peak memory 214284 kb
Host smart-77acbb26-f8b6-40da-942d-10b2c2466496
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318861044 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3318861044
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.1298470000
Short name T298
Test name
Test status
Simulation time 80631625 ps
CPU time 0.96 seconds
Started Jan 07 12:41:06 PM PST 24
Finished Jan 07 12:42:35 PM PST 24
Peak memory 214484 kb
Host smart-eaf59d99-e17a-40e0-9863-80e8ceedcbcb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298470000 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.1298470000
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.2241592660
Short name T565
Test name
Test status
Simulation time 33189779 ps
CPU time 0.91 seconds
Started Jan 07 12:41:05 PM PST 24
Finished Jan 07 12:42:23 PM PST 24
Peak memory 214876 kb
Host smart-a0c6ddfc-c4aa-4512-beb6-0eb2245aa69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241592660 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.2241592660
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.2637734175
Short name T294
Test name
Test status
Simulation time 14161214 ps
CPU time 0.92 seconds
Started Jan 07 12:41:14 PM PST 24
Finished Jan 07 12:42:40 PM PST 24
Peak memory 205164 kb
Host smart-edc7b6fe-085f-4dac-bbc5-05603a5e391e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637734175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.2637734175
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.529592672
Short name T335
Test name
Test status
Simulation time 19596814 ps
CPU time 0.97 seconds
Started Jan 07 12:41:02 PM PST 24
Finished Jan 07 12:42:29 PM PST 24
Peak memory 214308 kb
Host smart-c4baee57-9b59-4f93-ac9e-3d1f633d94be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529592672 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.529592672
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_stress_all.4112321202
Short name T120
Test name
Test status
Simulation time 905639667 ps
CPU time 3.55 seconds
Started Jan 07 12:41:36 PM PST 24
Finished Jan 07 12:43:15 PM PST 24
Peak memory 205768 kb
Host smart-99ebae33-09a1-4e26-bef8-1d9a0d2f7800
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112321202 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.4112321202
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.1763306998
Short name T471
Test name
Test status
Simulation time 204335424975 ps
CPU time 1251.54 seconds
Started Jan 07 12:41:05 PM PST 24
Finished Jan 07 01:03:46 PM PST 24
Peak memory 218080 kb
Host smart-015c7ba4-4c41-4731-b2ac-b290fd3e071e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763306998 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.1763306998
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.3020673212
Short name T695
Test name
Test status
Simulation time 19220052 ps
CPU time 0.96 seconds
Started Jan 07 12:41:53 PM PST 24
Finished Jan 07 12:43:25 PM PST 24
Peak memory 205932 kb
Host smart-d384be0f-0596-4682-80d3-094012593159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020673212 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.3020673212
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.4207182864
Short name T424
Test name
Test status
Simulation time 14427411 ps
CPU time 0.86 seconds
Started Jan 07 12:41:28 PM PST 24
Finished Jan 07 12:42:46 PM PST 24
Peak memory 205144 kb
Host smart-e0382921-e204-425a-9744-03dde9562247
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207182864 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.4207182864
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.2895731364
Short name T320
Test name
Test status
Simulation time 47698222 ps
CPU time 0.77 seconds
Started Jan 07 12:41:34 PM PST 24
Finished Jan 07 12:43:20 PM PST 24
Peak memory 214456 kb
Host smart-2bd48055-66f5-4656-a831-e4a802833672
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895731364 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.2895731364
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.3054737539
Short name T125
Test name
Test status
Simulation time 69005930 ps
CPU time 0.93 seconds
Started Jan 07 12:41:26 PM PST 24
Finished Jan 07 12:42:48 PM PST 24
Peak memory 214576 kb
Host smart-6b5292d0-30f5-4854-ae0d-0f8575fbb003
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054737539 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.3054737539
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.2159929278
Short name T537
Test name
Test status
Simulation time 35451378 ps
CPU time 0.82 seconds
Started Jan 07 12:42:02 PM PST 24
Finished Jan 07 12:43:32 PM PST 24
Peak memory 214584 kb
Host smart-7f86e915-0fe2-4151-952f-488df9ee34e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159929278 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.2159929278
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.1198389199
Short name T711
Test name
Test status
Simulation time 53940291 ps
CPU time 1.1 seconds
Started Jan 07 12:41:51 PM PST 24
Finished Jan 07 12:43:13 PM PST 24
Peak memory 214100 kb
Host smart-53983e7c-6e35-42bc-8256-53ca71ca8a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198389199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1198389199
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.3977656838
Short name T478
Test name
Test status
Simulation time 21196783 ps
CPU time 1 seconds
Started Jan 07 12:41:45 PM PST 24
Finished Jan 07 12:43:32 PM PST 24
Peak memory 214528 kb
Host smart-899db433-5343-4c73-a527-ef76fe5be628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977656838 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.3977656838
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.854423677
Short name T579
Test name
Test status
Simulation time 38425938 ps
CPU time 0.85 seconds
Started Jan 07 12:41:58 PM PST 24
Finished Jan 07 12:43:19 PM PST 24
Peak memory 204584 kb
Host smart-1728debb-3b43-4067-a675-3fd755a95c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854423677 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.854423677
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.827866357
Short name T368
Test name
Test status
Simulation time 282290154 ps
CPU time 1.93 seconds
Started Jan 07 12:41:10 PM PST 24
Finished Jan 07 12:42:21 PM PST 24
Peak memory 205988 kb
Host smart-ed054f3b-def7-4262-98c7-90ec0115bb8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827866357 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.827866357
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.2340479424
Short name T150
Test name
Test status
Simulation time 113163661125 ps
CPU time 1234.29 seconds
Started Jan 07 12:41:47 PM PST 24
Finished Jan 07 01:03:42 PM PST 24
Peak memory 215872 kb
Host smart-fc2ed14d-b827-43be-a2bb-89d91807c9ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340479424 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.2340479424
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.4144765289
Short name T236
Test name
Test status
Simulation time 58361168 ps
CPU time 0.89 seconds
Started Jan 07 12:41:27 PM PST 24
Finished Jan 07 12:43:11 PM PST 24
Peak memory 205176 kb
Host smart-5b567d5f-ed49-4b09-91af-f60e3c218703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144765289 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.4144765289
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.3554577658
Short name T94
Test name
Test status
Simulation time 21582981 ps
CPU time 0.79 seconds
Started Jan 07 12:42:06 PM PST 24
Finished Jan 07 12:43:24 PM PST 24
Peak memory 204300 kb
Host smart-7a3a8dd7-6e5a-4316-b46e-f454141f99f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554577658 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.3554577658
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.3709956861
Short name T103
Test name
Test status
Simulation time 13753458 ps
CPU time 0.84 seconds
Started Jan 07 12:41:41 PM PST 24
Finished Jan 07 12:43:50 PM PST 24
Peak memory 214352 kb
Host smart-22e31f88-e41e-4199-b0bc-051e26db8eab
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709956861 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.3709956861
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_err.1415760242
Short name T449
Test name
Test status
Simulation time 48183232 ps
CPU time 0.91 seconds
Started Jan 07 12:41:15 PM PST 24
Finished Jan 07 12:42:40 PM PST 24
Peak memory 214652 kb
Host smart-e5ef3b62-f4d9-44ef-b212-104e9285c8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415760242 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.1415760242
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.903150045
Short name T419
Test name
Test status
Simulation time 18148642 ps
CPU time 0.81 seconds
Started Jan 07 12:41:27 PM PST 24
Finished Jan 07 12:42:49 PM PST 24
Peak memory 204852 kb
Host smart-a8e3ff55-f6bc-4c7d-9768-cf48d7529809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903150045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.903150045
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.3612916733
Short name T5
Test name
Test status
Simulation time 34989708 ps
CPU time 0.88 seconds
Started Jan 07 12:41:24 PM PST 24
Finished Jan 07 12:42:49 PM PST 24
Peak memory 221108 kb
Host smart-ae1107c6-b6e1-41c5-bc6e-8bd7f8f124e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612916733 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.3612916733
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.2468830529
Short name T520
Test name
Test status
Simulation time 49860612 ps
CPU time 0.83 seconds
Started Jan 07 12:41:28 PM PST 24
Finished Jan 07 12:42:46 PM PST 24
Peak memory 204644 kb
Host smart-d7770a37-caa1-429e-bba6-faa6000a50dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468830529 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.2468830529
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.3958608646
Short name T369
Test name
Test status
Simulation time 603986355 ps
CPU time 3.51 seconds
Started Jan 07 12:41:30 PM PST 24
Finished Jan 07 12:42:51 PM PST 24
Peak memory 205960 kb
Host smart-2082819b-adfa-479b-93ed-49dec0538cea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958608646 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.3958608646
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.2340517020
Short name T592
Test name
Test status
Simulation time 7964927347 ps
CPU time 176.76 seconds
Started Jan 07 12:41:42 PM PST 24
Finished Jan 07 12:46:10 PM PST 24
Peak memory 214564 kb
Host smart-73223d02-eebf-4ee9-851c-488c7a4f6d28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340517020 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.2340517020
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.3890169377
Short name T50
Test name
Test status
Simulation time 17695965 ps
CPU time 0.97 seconds
Started Jan 07 12:41:09 PM PST 24
Finished Jan 07 12:43:00 PM PST 24
Peak memory 205196 kb
Host smart-e84c3ac6-879b-488c-8a46-00694b9c0433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890169377 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.3890169377
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.1500275468
Short name T464
Test name
Test status
Simulation time 55204139 ps
CPU time 0.91 seconds
Started Jan 07 12:41:26 PM PST 24
Finished Jan 07 12:42:36 PM PST 24
Peak memory 204480 kb
Host smart-d7d07fbb-da06-4149-81ce-d397eb3374e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500275468 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.1500275468
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.3801294137
Short name T139
Test name
Test status
Simulation time 17266518 ps
CPU time 0.85 seconds
Started Jan 07 12:41:43 PM PST 24
Finished Jan 07 12:43:03 PM PST 24
Peak memory 214364 kb
Host smart-69574745-de4a-4c2b-b6c0-fda23b657eae
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801294137 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.3801294137
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.3651710308
Short name T647
Test name
Test status
Simulation time 142490113 ps
CPU time 1.02 seconds
Started Jan 07 12:41:47 PM PST 24
Finished Jan 07 12:43:43 PM PST 24
Peak memory 214496 kb
Host smart-e6a25b9d-5299-4304-86d8-7af9d716cc1c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651710308 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.3651710308
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.3358377336
Short name T482
Test name
Test status
Simulation time 24238198 ps
CPU time 0.99 seconds
Started Jan 07 12:41:14 PM PST 24
Finished Jan 07 12:42:45 PM PST 24
Peak memory 221552 kb
Host smart-d53fdd2c-8897-45c8-84d8-deb9960fc041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358377336 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.3358377336
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.1021881037
Short name T413
Test name
Test status
Simulation time 73913600 ps
CPU time 1.09 seconds
Started Jan 07 12:41:38 PM PST 24
Finished Jan 07 12:43:00 PM PST 24
Peak memory 214160 kb
Host smart-c5ac5aba-bc65-4c8c-803f-3d7e6320b808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021881037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.1021881037
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.2781785557
Short name T86
Test name
Test status
Simulation time 29226256 ps
CPU time 0.82 seconds
Started Jan 07 12:41:39 PM PST 24
Finished Jan 07 12:43:14 PM PST 24
Peak memory 214292 kb
Host smart-63f45749-3dd5-43d0-baa1-220a80360e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781785557 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.2781785557
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.3691373461
Short name T484
Test name
Test status
Simulation time 25686540 ps
CPU time 0.89 seconds
Started Jan 07 12:41:48 PM PST 24
Finished Jan 07 12:43:19 PM PST 24
Peak memory 204580 kb
Host smart-a56c710a-602a-4439-a468-720fda5a13a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691373461 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.3691373461
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.2362132932
Short name T412
Test name
Test status
Simulation time 382815870 ps
CPU time 3.93 seconds
Started Jan 07 12:41:47 PM PST 24
Finished Jan 07 12:43:38 PM PST 24
Peak memory 205980 kb
Host smart-fedc3351-1e2a-4b21-a4f6-b036d3fc5f81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362132932 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.2362132932
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.1898657912
Short name T539
Test name
Test status
Simulation time 1365042394987 ps
CPU time 2536.24 seconds
Started Jan 07 12:41:48 PM PST 24
Finished Jan 07 01:25:46 PM PST 24
Peak memory 221824 kb
Host smart-f6dbf335-4b20-4e34-8f7e-94b943e0a58d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898657912 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.1898657912
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.1411759466
Short name T623
Test name
Test status
Simulation time 18342282 ps
CPU time 0.94 seconds
Started Jan 07 12:41:46 PM PST 24
Finished Jan 07 12:42:58 PM PST 24
Peak memory 205208 kb
Host smart-555f4b48-5444-4a4a-a2cb-487abc6ef641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411759466 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.1411759466
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.1296572555
Short name T597
Test name
Test status
Simulation time 81193541 ps
CPU time 0.94 seconds
Started Jan 07 12:41:47 PM PST 24
Finished Jan 07 12:43:13 PM PST 24
Peak memory 204684 kb
Host smart-f9b9b38e-8509-405b-b50b-e2c365605f6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296572555 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.1296572555
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.528329872
Short name T411
Test name
Test status
Simulation time 68252756 ps
CPU time 0.94 seconds
Started Jan 07 12:41:17 PM PST 24
Finished Jan 07 12:43:00 PM PST 24
Peak memory 214592 kb
Host smart-5e463343-e73c-4011-b994-8e74ab40ff44
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528329872 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_di
sable_auto_req_mode.528329872
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_genbits.2360415348
Short name T670
Test name
Test status
Simulation time 27090705 ps
CPU time 1.07 seconds
Started Jan 07 12:41:48 PM PST 24
Finished Jan 07 12:43:21 PM PST 24
Peak memory 205600 kb
Host smart-12283111-8c94-415e-aac3-a4506642d65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360415348 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.2360415348
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_smoke.1507424542
Short name T433
Test name
Test status
Simulation time 51974293 ps
CPU time 0.85 seconds
Started Jan 07 12:41:39 PM PST 24
Finished Jan 07 12:43:02 PM PST 24
Peak memory 204588 kb
Host smart-fbdf2069-de5d-4a03-a69e-d33d196dd29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507424542 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.1507424542
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_alert.3186279802
Short name T193
Test name
Test status
Simulation time 21921717 ps
CPU time 1 seconds
Started Jan 07 12:40:05 PM PST 24
Finished Jan 07 12:41:33 PM PST 24
Peak memory 205352 kb
Host smart-fa834c17-e077-4f95-b63d-000423478bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186279802 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.3186279802
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.2516712356
Short name T634
Test name
Test status
Simulation time 82131985 ps
CPU time 0.86 seconds
Started Jan 07 12:40:46 PM PST 24
Finished Jan 07 12:41:53 PM PST 24
Peak memory 204528 kb
Host smart-12bd9696-53d5-4570-a52a-cbc2e624de82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516712356 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2516712356
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.1503655674
Short name T56
Test name
Test status
Simulation time 12181374 ps
CPU time 0.85 seconds
Started Jan 07 12:39:44 PM PST 24
Finished Jan 07 12:41:29 PM PST 24
Peak memory 214572 kb
Host smart-936e2c8e-119c-4cff-bebf-f20770735a6b
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503655674 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1503655674
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.4095352106
Short name T633
Test name
Test status
Simulation time 26135061 ps
CPU time 0.94 seconds
Started Jan 07 12:41:10 PM PST 24
Finished Jan 07 12:42:17 PM PST 24
Peak memory 214260 kb
Host smart-0b6a383c-3c57-446e-8a83-8212e0020197
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095352106 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.4095352106
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.2038803711
Short name T494
Test name
Test status
Simulation time 49090233 ps
CPU time 0.95 seconds
Started Jan 07 12:40:12 PM PST 24
Finished Jan 07 12:41:46 PM PST 24
Peak memory 215916 kb
Host smart-649d0d9f-babe-4735-aeeb-840f2688607e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038803711 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.2038803711
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.2115284170
Short name T715
Test name
Test status
Simulation time 175637954 ps
CPU time 0.85 seconds
Started Jan 07 12:39:43 PM PST 24
Finished Jan 07 12:41:18 PM PST 24
Peak memory 205032 kb
Host smart-9b6900ad-edc6-4a16-8f1a-854bd2c8ec7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115284170 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.2115284170
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_smoke.756567377
Short name T530
Test name
Test status
Simulation time 24474302 ps
CPU time 0.86 seconds
Started Jan 07 12:40:16 PM PST 24
Finished Jan 07 12:41:17 PM PST 24
Peak memory 204508 kb
Host smart-a615c7aa-bfbc-4dc5-a030-198980593f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756567377 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.756567377
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.2978891188
Short name T385
Test name
Test status
Simulation time 53553411 ps
CPU time 0.94 seconds
Started Jan 07 12:39:50 PM PST 24
Finished Jan 07 12:41:15 PM PST 24
Peak memory 204716 kb
Host smart-e8aae843-e03d-4323-ad6d-f906b51c8de9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978891188 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.2978891188
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.2824824774
Short name T669
Test name
Test status
Simulation time 8834107586 ps
CPU time 192.73 seconds
Started Jan 07 12:39:45 PM PST 24
Finished Jan 07 12:44:18 PM PST 24
Peak memory 215376 kb
Host smart-876d517d-9ffd-4e65-8a06-206741fb6a2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824824774 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.2824824774
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_genbits.255590957
Short name T268
Test name
Test status
Simulation time 25086330 ps
CPU time 1.12 seconds
Started Jan 07 12:41:16 PM PST 24
Finished Jan 07 12:42:38 PM PST 24
Peak memory 205236 kb
Host smart-07b0c8ae-faed-4c0a-bd5d-edc80d6321c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255590957 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.255590957
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.3028828966
Short name T458
Test name
Test status
Simulation time 21785396 ps
CPU time 0.85 seconds
Started Jan 07 12:41:09 PM PST 24
Finished Jan 07 12:42:17 PM PST 24
Peak memory 215688 kb
Host smart-e1f99b1d-cab8-491f-9b08-fcaf64f67d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028828966 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.3028828966
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.1422369351
Short name T260
Test name
Test status
Simulation time 27816115 ps
CPU time 0.94 seconds
Started Jan 07 12:41:37 PM PST 24
Finished Jan 07 12:43:16 PM PST 24
Peak memory 205328 kb
Host smart-decdbcad-3f42-4836-8a85-0b12006ff690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422369351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.1422369351
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.2308991653
Short name T442
Test name
Test status
Simulation time 18593279 ps
CPU time 1.06 seconds
Started Jan 07 12:41:22 PM PST 24
Finished Jan 07 12:42:56 PM PST 24
Peak memory 221660 kb
Host smart-d9a0e073-f9dd-43bd-922c-63bf66cdd39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308991653 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.2308991653
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.743561808
Short name T247
Test name
Test status
Simulation time 28173253 ps
CPU time 1.01 seconds
Started Jan 07 12:41:45 PM PST 24
Finished Jan 07 12:43:11 PM PST 24
Peak memory 214176 kb
Host smart-0531ead3-4b8f-42a2-a7a3-e6c1f09f85d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743561808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.743561808
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.2654382508
Short name T558
Test name
Test status
Simulation time 24136111 ps
CPU time 1.01 seconds
Started Jan 07 12:41:19 PM PST 24
Finished Jan 07 12:42:46 PM PST 24
Peak memory 228320 kb
Host smart-7746f3c4-03ba-4cb3-9a79-9b85c238c6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654382508 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.2654382508
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/54.edn_err.3994693805
Short name T642
Test name
Test status
Simulation time 29723490 ps
CPU time 1.22 seconds
Started Jan 07 12:41:32 PM PST 24
Finished Jan 07 12:43:19 PM PST 24
Peak memory 214744 kb
Host smart-b6fd35e8-6237-4365-8b62-03dce0b5bf26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994693805 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.3994693805
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/55.edn_err.2063762639
Short name T387
Test name
Test status
Simulation time 24368188 ps
CPU time 1.25 seconds
Started Jan 07 12:41:44 PM PST 24
Finished Jan 07 12:43:10 PM PST 24
Peak memory 228248 kb
Host smart-c9761c9f-1ee1-4f91-8fda-ff85e56317c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063762639 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.2063762639
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.662461649
Short name T451
Test name
Test status
Simulation time 44391863 ps
CPU time 0.86 seconds
Started Jan 07 12:41:56 PM PST 24
Finished Jan 07 12:43:24 PM PST 24
Peak memory 204924 kb
Host smart-83c88178-609b-46b4-88e1-809ef836ac7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662461649 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.662461649
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.80744402
Short name T9
Test name
Test status
Simulation time 76154977 ps
CPU time 0.99 seconds
Started Jan 07 12:41:43 PM PST 24
Finished Jan 07 12:43:14 PM PST 24
Peak memory 214776 kb
Host smart-30851666-a789-44eb-b2b7-a20c8a682975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80744402 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.80744402
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.2451691002
Short name T460
Test name
Test status
Simulation time 31010914 ps
CPU time 1.02 seconds
Started Jan 07 12:41:46 PM PST 24
Finished Jan 07 12:43:08 PM PST 24
Peak memory 205408 kb
Host smart-fb5b1e34-395b-420b-ac24-b4e1b05c5ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451691002 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.2451691002
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_genbits.755975207
Short name T266
Test name
Test status
Simulation time 25422445 ps
CPU time 0.94 seconds
Started Jan 07 12:41:31 PM PST 24
Finished Jan 07 12:42:49 PM PST 24
Peak memory 205252 kb
Host smart-84626905-9a34-42d2-9d7a-05cdfd6a26db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755975207 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.755975207
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.1993950988
Short name T648
Test name
Test status
Simulation time 27988463 ps
CPU time 1.01 seconds
Started Jan 07 12:41:45 PM PST 24
Finished Jan 07 12:43:16 PM PST 24
Peak memory 214608 kb
Host smart-1950a9dd-2023-416f-9218-9cf64c300827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993950988 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.1993950988
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.3911499114
Short name T431
Test name
Test status
Simulation time 67588507 ps
CPU time 0.91 seconds
Started Jan 07 12:41:15 PM PST 24
Finished Jan 07 12:43:06 PM PST 24
Peak memory 205588 kb
Host smart-9fcb7bb3-07ba-4a01-a4f5-0e86110782de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911499114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.3911499114
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.3262756114
Short name T629
Test name
Test status
Simulation time 31649245 ps
CPU time 1.2 seconds
Started Jan 07 12:41:12 PM PST 24
Finished Jan 07 12:42:46 PM PST 24
Peak memory 214788 kb
Host smart-bbff672c-3a9f-49fa-9866-796f4d5fb6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262756114 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.3262756114
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.2054185465
Short name T258
Test name
Test status
Simulation time 204235125 ps
CPU time 2.71 seconds
Started Jan 07 12:41:12 PM PST 24
Finished Jan 07 12:42:41 PM PST 24
Peak memory 214152 kb
Host smart-042d92f0-32b1-495b-9bcc-f7f372526b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054185465 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.2054185465
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.759797446
Short name T235
Test name
Test status
Simulation time 46991156 ps
CPU time 0.93 seconds
Started Jan 07 12:40:11 PM PST 24
Finished Jan 07 12:41:27 PM PST 24
Peak memory 205356 kb
Host smart-10aa6480-914b-4e07-9c54-24e02d1c11be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759797446 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.759797446
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.1844716310
Short name T286
Test name
Test status
Simulation time 21254715 ps
CPU time 0.96 seconds
Started Jan 07 12:40:30 PM PST 24
Finished Jan 07 12:41:38 PM PST 24
Peak memory 205236 kb
Host smart-8012ba0a-f3ae-4620-864c-a3ed9b81aa08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844716310 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.1844716310
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.2068243733
Short name T316
Test name
Test status
Simulation time 56990202 ps
CPU time 0.74 seconds
Started Jan 07 12:39:48 PM PST 24
Finished Jan 07 12:41:05 PM PST 24
Peak memory 214320 kb
Host smart-47bb60c4-a5e1-45d2-93e0-a785a4fdb49d
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068243733 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.2068243733
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.2371627138
Short name T364
Test name
Test status
Simulation time 98511903 ps
CPU time 0.96 seconds
Started Jan 07 12:39:58 PM PST 24
Finished Jan 07 12:41:36 PM PST 24
Peak memory 214676 kb
Host smart-dc396947-7f29-4ca0-b84a-5b05156613f4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371627138 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.2371627138
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.3558104643
Short name T417
Test name
Test status
Simulation time 21462992 ps
CPU time 0.83 seconds
Started Jan 07 12:40:38 PM PST 24
Finished Jan 07 12:42:01 PM PST 24
Peak memory 215664 kb
Host smart-4f622317-5e39-4388-a12c-45e7b73f24b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558104643 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.3558104643
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.1050252430
Short name T14
Test name
Test status
Simulation time 44475815 ps
CPU time 1.19 seconds
Started Jan 07 12:39:50 PM PST 24
Finished Jan 07 12:41:27 PM PST 24
Peak memory 214168 kb
Host smart-5fd2504a-33bf-4052-bc59-c0b034c99292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050252430 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.1050252430
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_regwen.3420643322
Short name T547
Test name
Test status
Simulation time 78380767 ps
CPU time 0.83 seconds
Started Jan 07 12:40:58 PM PST 24
Finished Jan 07 12:42:42 PM PST 24
Peak memory 204596 kb
Host smart-c83b95b9-231e-41b6-82ef-f836a94e3dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420643322 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.3420643322
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_stress_all.3990884358
Short name T344
Test name
Test status
Simulation time 124758053 ps
CPU time 1.14 seconds
Started Jan 07 12:40:41 PM PST 24
Finished Jan 07 12:42:09 PM PST 24
Peak memory 205912 kb
Host smart-72234b4a-8a16-41c2-b951-85842e633b12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990884358 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.3990884358
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.324063739
Short name T543
Test name
Test status
Simulation time 38815997833 ps
CPU time 457.39 seconds
Started Jan 07 12:40:29 PM PST 24
Finished Jan 07 12:49:09 PM PST 24
Peak memory 215376 kb
Host smart-5c775e77-e439-47b5-8f08-30fae2980bb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324063739 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.324063739
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.3938720880
Short name T10
Test name
Test status
Simulation time 26924844 ps
CPU time 1.16 seconds
Started Jan 07 12:41:23 PM PST 24
Finished Jan 07 12:42:54 PM PST 24
Peak memory 214920 kb
Host smart-1a76f123-7ea9-4e71-996c-56cae762a0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938720880 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.3938720880
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.461172044
Short name T514
Test name
Test status
Simulation time 15433269 ps
CPU time 0.93 seconds
Started Jan 07 12:41:17 PM PST 24
Finished Jan 07 12:43:09 PM PST 24
Peak memory 205104 kb
Host smart-8c36c33d-8c8b-4964-ab4d-cbce6c84a2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461172044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.461172044
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_genbits.779098018
Short name T261
Test name
Test status
Simulation time 35214010 ps
CPU time 0.92 seconds
Started Jan 07 12:41:52 PM PST 24
Finished Jan 07 12:43:16 PM PST 24
Peak memory 205056 kb
Host smart-6013e726-bc9c-4b9a-8019-bc5c39cf4cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779098018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.779098018
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.1183368755
Short name T407
Test name
Test status
Simulation time 41806677 ps
CPU time 1.13 seconds
Started Jan 07 12:41:49 PM PST 24
Finished Jan 07 12:43:20 PM PST 24
Peak memory 221772 kb
Host smart-3a4a4be3-0d1f-4190-ba09-fdb6cda52650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183368755 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.1183368755
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.859205688
Short name T577
Test name
Test status
Simulation time 19707921 ps
CPU time 1.1 seconds
Started Jan 07 12:41:29 PM PST 24
Finished Jan 07 12:43:00 PM PST 24
Peak memory 214076 kb
Host smart-5747f64f-6b27-4e4d-9f27-ace6e69f181c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859205688 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.859205688
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_genbits.728482169
Short name T745
Test name
Test status
Simulation time 17034268 ps
CPU time 0.98 seconds
Started Jan 07 12:41:49 PM PST 24
Finished Jan 07 12:43:24 PM PST 24
Peak memory 205448 kb
Host smart-41b77dc5-b5f5-4eb4-9598-37202c7eff40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728482169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.728482169
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.1764691776
Short name T541
Test name
Test status
Simulation time 26621498 ps
CPU time 1.25 seconds
Started Jan 07 12:41:48 PM PST 24
Finished Jan 07 12:43:13 PM PST 24
Peak memory 228408 kb
Host smart-8184ccb1-f4be-4e76-85d9-a25c0c57dc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764691776 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.1764691776
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.4169439844
Short name T439
Test name
Test status
Simulation time 35358889 ps
CPU time 1 seconds
Started Jan 07 12:41:31 PM PST 24
Finished Jan 07 12:43:20 PM PST 24
Peak memory 205464 kb
Host smart-588769d4-edbb-48ee-9d51-ce2db9d4ca3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169439844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.4169439844
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.2751944253
Short name T450
Test name
Test status
Simulation time 24977669 ps
CPU time 0.89 seconds
Started Jan 07 12:41:06 PM PST 24
Finished Jan 07 12:42:21 PM PST 24
Peak memory 215924 kb
Host smart-04abe845-e0eb-4026-bb35-1068d8201af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751944253 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.2751944253
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.739137794
Short name T620
Test name
Test status
Simulation time 36377373 ps
CPU time 0.95 seconds
Started Jan 07 12:41:29 PM PST 24
Finished Jan 07 12:43:31 PM PST 24
Peak memory 205204 kb
Host smart-6e162aa6-30a4-4526-b7cc-4ca6f618dba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739137794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.739137794
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.1174522228
Short name T628
Test name
Test status
Simulation time 55029696 ps
CPU time 0.96 seconds
Started Jan 07 12:41:14 PM PST 24
Finished Jan 07 12:43:06 PM PST 24
Peak memory 214600 kb
Host smart-e2d52a01-6cc2-47cf-b7c9-7e412745fc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174522228 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.1174522228
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.4273527272
Short name T91
Test name
Test status
Simulation time 139622343 ps
CPU time 1.08 seconds
Started Jan 07 12:41:47 PM PST 24
Finished Jan 07 12:43:38 PM PST 24
Peak memory 205768 kb
Host smart-3b4fcf50-adae-4e07-bfa2-c2ba46778bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273527272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.4273527272
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_genbits.3228509848
Short name T376
Test name
Test status
Simulation time 24569523 ps
CPU time 1.03 seconds
Started Jan 07 12:41:17 PM PST 24
Finished Jan 07 12:43:03 PM PST 24
Peak memory 205132 kb
Host smart-9f8f4dab-e731-4892-88d2-3005d6fa0a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228509848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.3228509848
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.1613344813
Short name T370
Test name
Test status
Simulation time 17962418 ps
CPU time 1.07 seconds
Started Jan 07 12:41:44 PM PST 24
Finished Jan 07 12:43:10 PM PST 24
Peak memory 221728 kb
Host smart-049f0829-0a32-4f30-b51d-7fad69420285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613344813 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.1613344813
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.497349836
Short name T455
Test name
Test status
Simulation time 16392443 ps
CPU time 1.01 seconds
Started Jan 07 12:41:11 PM PST 24
Finished Jan 07 12:42:26 PM PST 24
Peak memory 205328 kb
Host smart-f46dff7a-562d-4296-a0a3-b2fda86b236b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497349836 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.497349836
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.1453898031
Short name T725
Test name
Test status
Simulation time 61199763 ps
CPU time 0.91 seconds
Started Jan 07 12:40:25 PM PST 24
Finished Jan 07 12:41:40 PM PST 24
Peak memory 205944 kb
Host smart-44f2fb2a-c0fa-44bf-91d8-800d62e3d3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453898031 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.1453898031
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.3026650066
Short name T729
Test name
Test status
Simulation time 81338996 ps
CPU time 0.76 seconds
Started Jan 07 12:40:42 PM PST 24
Finished Jan 07 12:41:48 PM PST 24
Peak memory 204256 kb
Host smart-a9aa2c4e-ecd9-41da-aa4e-36fb14758b0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026650066 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.3026650066
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.267209756
Short name T301
Test name
Test status
Simulation time 12212832 ps
CPU time 0.85 seconds
Started Jan 07 12:40:36 PM PST 24
Finished Jan 07 12:41:59 PM PST 24
Peak memory 214612 kb
Host smart-57868310-1408-41ca-9608-92b664802431
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267209756 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.267209756
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.1363904650
Short name T713
Test name
Test status
Simulation time 25368624 ps
CPU time 0.98 seconds
Started Jan 07 12:40:36 PM PST 24
Finished Jan 07 12:42:19 PM PST 24
Peak memory 214488 kb
Host smart-aff32b07-95de-48ec-9690-79457ce637b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363904650 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.1363904650
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_genbits.750669162
Short name T447
Test name
Test status
Simulation time 20215039 ps
CPU time 0.92 seconds
Started Jan 07 12:40:35 PM PST 24
Finished Jan 07 12:41:59 PM PST 24
Peak memory 205212 kb
Host smart-a74e9177-e3a2-44d4-95a3-170d3502ea07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750669162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.750669162
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.639507542
Short name T556
Test name
Test status
Simulation time 34506948 ps
CPU time 0.83 seconds
Started Jan 07 12:40:03 PM PST 24
Finished Jan 07 12:41:20 PM PST 24
Peak memory 214168 kb
Host smart-10751384-3ccc-415a-b701-3051309f411c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639507542 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.639507542
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_smoke.1820151760
Short name T452
Test name
Test status
Simulation time 15890317 ps
CPU time 0.89 seconds
Started Jan 07 12:40:31 PM PST 24
Finished Jan 07 12:42:07 PM PST 24
Peak memory 204872 kb
Host smart-7578cf51-0ae6-46c0-8388-03f49dcfc8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820151760 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.1820151760
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.1916635013
Short name T548
Test name
Test status
Simulation time 151301182 ps
CPU time 3.79 seconds
Started Jan 07 12:40:35 PM PST 24
Finished Jan 07 12:41:53 PM PST 24
Peak memory 206052 kb
Host smart-4feeae07-9136-4492-b414-89681577640e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916635013 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.1916635013
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.2137330668
Short name T437
Test name
Test status
Simulation time 95111735809 ps
CPU time 1069.71 seconds
Started Jan 07 12:39:55 PM PST 24
Finished Jan 07 12:58:59 PM PST 24
Peak memory 216988 kb
Host smart-ca604329-9453-4aef-8a33-7822aacee1fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137330668 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.2137330668
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.316964309
Short name T64
Test name
Test status
Simulation time 29970950 ps
CPU time 1.24 seconds
Started Jan 07 12:42:09 PM PST 24
Finished Jan 07 12:44:11 PM PST 24
Peak memory 221816 kb
Host smart-165ea934-4e54-40a0-8397-82fa598bf6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316964309 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.316964309
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.169413150
Short name T312
Test name
Test status
Simulation time 26214986 ps
CPU time 1 seconds
Started Jan 07 12:41:42 PM PST 24
Finished Jan 07 12:43:14 PM PST 24
Peak memory 205548 kb
Host smart-0a4704e0-f202-495f-a5f9-79a361e2c1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169413150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.169413150
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.258995668
Short name T85
Test name
Test status
Simulation time 43294802 ps
CPU time 1.02 seconds
Started Jan 07 12:41:45 PM PST 24
Finished Jan 07 12:43:34 PM PST 24
Peak memory 216896 kb
Host smart-ef83f6da-ad9f-40d2-b4fd-b1b02cadb788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258995668 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.258995668
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.493095131
Short name T603
Test name
Test status
Simulation time 31910864 ps
CPU time 0.95 seconds
Started Jan 07 12:41:47 PM PST 24
Finished Jan 07 12:43:37 PM PST 24
Peak memory 204932 kb
Host smart-3e34d419-835d-4bfd-8055-a9afcc8c3b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493095131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.493095131
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.768536849
Short name T327
Test name
Test status
Simulation time 67778745 ps
CPU time 1.07 seconds
Started Jan 07 12:41:21 PM PST 24
Finished Jan 07 12:42:36 PM PST 24
Peak memory 215080 kb
Host smart-847a0b51-e0ca-463e-8226-4afe226f7b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768536849 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.768536849
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.4249728522
Short name T599
Test name
Test status
Simulation time 34834947 ps
CPU time 0.96 seconds
Started Jan 07 12:41:41 PM PST 24
Finished Jan 07 12:43:21 PM PST 24
Peak memory 205328 kb
Host smart-4308df4c-e983-4bcf-99f4-09c52152d80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249728522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.4249728522
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.654560076
Short name T428
Test name
Test status
Simulation time 32772752 ps
CPU time 0.94 seconds
Started Jan 07 12:41:48 PM PST 24
Finished Jan 07 12:43:02 PM PST 24
Peak memory 214528 kb
Host smart-2ad55740-bcaf-46fa-bfdd-3f63b8d2e151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654560076 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.654560076
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/74.edn_err.145991402
Short name T432
Test name
Test status
Simulation time 72068069 ps
CPU time 0.88 seconds
Started Jan 07 12:41:55 PM PST 24
Finished Jan 07 12:43:11 PM PST 24
Peak memory 214592 kb
Host smart-0cb5c493-133a-414c-a07c-04f2d9d291e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145991402 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.145991402
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.539357726
Short name T621
Test name
Test status
Simulation time 21983335 ps
CPU time 1.02 seconds
Started Jan 07 12:41:46 PM PST 24
Finished Jan 07 12:42:59 PM PST 24
Peak memory 205460 kb
Host smart-e3fd96c1-414b-448f-8aa2-02ad1e1eee09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539357726 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.539357726
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.2838356093
Short name T697
Test name
Test status
Simulation time 22313319 ps
CPU time 1.05 seconds
Started Jan 07 12:41:52 PM PST 24
Finished Jan 07 12:43:30 PM PST 24
Peak memory 228488 kb
Host smart-f5c898e0-f58c-4a90-bf3e-177e0c6d4e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838356093 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.2838356093
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.1855048528
Short name T291
Test name
Test status
Simulation time 65508683 ps
CPU time 2.25 seconds
Started Jan 07 12:41:51 PM PST 24
Finished Jan 07 12:43:24 PM PST 24
Peak memory 214160 kb
Host smart-c99b97af-0a85-4dc9-8ada-46cba8b84f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855048528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.1855048528
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.2056715919
Short name T16
Test name
Test status
Simulation time 24813921 ps
CPU time 1.02 seconds
Started Jan 07 12:41:05 PM PST 24
Finished Jan 07 12:42:24 PM PST 24
Peak memory 221704 kb
Host smart-8bfe9055-f026-45c6-b884-cd2c540dea8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056715919 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.2056715919
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.2741977764
Short name T479
Test name
Test status
Simulation time 21731115 ps
CPU time 0.95 seconds
Started Jan 07 12:41:49 PM PST 24
Finished Jan 07 12:43:38 PM PST 24
Peak memory 205008 kb
Host smart-16ee1a21-cc28-46a9-8ab9-f6a419ca442b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741977764 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.2741977764
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.2767826015
Short name T665
Test name
Test status
Simulation time 32107144 ps
CPU time 1.09 seconds
Started Jan 07 12:41:31 PM PST 24
Finished Jan 07 12:42:46 PM PST 24
Peak memory 221696 kb
Host smart-08786073-7b2f-49d7-98ff-9b83c822b691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767826015 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.2767826015
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.3654863767
Short name T607
Test name
Test status
Simulation time 126270042 ps
CPU time 0.98 seconds
Started Jan 07 12:41:48 PM PST 24
Finished Jan 07 12:43:35 PM PST 24
Peak memory 205456 kb
Host smart-10ced697-cf79-46ae-b371-bc4c9c275be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654863767 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.3654863767
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.3400808623
Short name T618
Test name
Test status
Simulation time 29135226 ps
CPU time 0.88 seconds
Started Jan 07 12:41:46 PM PST 24
Finished Jan 07 12:43:18 PM PST 24
Peak memory 215876 kb
Host smart-b1b73231-20c4-4001-85a7-ba85ffb7e6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400808623 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.3400808623
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/79.edn_err.3882179315
Short name T402
Test name
Test status
Simulation time 60287496 ps
CPU time 0.9 seconds
Started Jan 07 12:41:18 PM PST 24
Finished Jan 07 12:42:30 PM PST 24
Peak memory 214528 kb
Host smart-dc7e7745-5df8-42f0-9828-739d6709826c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882179315 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.3882179315
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.4245714457
Short name T282
Test name
Test status
Simulation time 27480250 ps
CPU time 0.89 seconds
Started Jan 07 12:41:46 PM PST 24
Finished Jan 07 12:43:08 PM PST 24
Peak memory 205248 kb
Host smart-8dce928c-8cce-40c4-bc5c-a66295238a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245714457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.4245714457
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.3607298643
Short name T701
Test name
Test status
Simulation time 55787707 ps
CPU time 0.91 seconds
Started Jan 07 12:40:09 PM PST 24
Finished Jan 07 12:41:40 PM PST 24
Peak memory 205176 kb
Host smart-b0bc8b6c-e0fb-4e71-b0bb-cf066558f426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607298643 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.3607298643
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.3817664583
Short name T583
Test name
Test status
Simulation time 14205693 ps
CPU time 0.83 seconds
Started Jan 07 12:40:12 PM PST 24
Finished Jan 07 12:41:15 PM PST 24
Peak memory 204500 kb
Host smart-6cca794e-e90a-44db-9e82-1a1a23f97507
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817664583 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.3817664583
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.3155733794
Short name T395
Test name
Test status
Simulation time 56881755 ps
CPU time 0.8 seconds
Started Jan 07 12:40:15 PM PST 24
Finished Jan 07 12:41:45 PM PST 24
Peak memory 214376 kb
Host smart-637f38d0-ce9d-4841-8f6d-debf1787c784
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155733794 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.3155733794
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.3371013309
Short name T11
Test name
Test status
Simulation time 249997897 ps
CPU time 1.07 seconds
Started Jan 07 12:39:57 PM PST 24
Finished Jan 07 12:41:34 PM PST 24
Peak memory 214496 kb
Host smart-b80d055f-fb23-4834-b269-bda0b15a7237
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371013309 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.3371013309
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.3504084496
Short name T473
Test name
Test status
Simulation time 18311541 ps
CPU time 0.99 seconds
Started Jan 07 12:40:07 PM PST 24
Finished Jan 07 12:41:23 PM PST 24
Peak memory 215648 kb
Host smart-17da4690-ec43-4804-a331-6bfa32344481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504084496 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3504084496
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.1925211882
Short name T342
Test name
Test status
Simulation time 470491415 ps
CPU time 3.14 seconds
Started Jan 07 12:40:07 PM PST 24
Finished Jan 07 12:41:24 PM PST 24
Peak memory 214116 kb
Host smart-dc07e540-eb1e-4217-aecd-6e8bb22da050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925211882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.1925211882
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.1667809172
Short name T66
Test name
Test status
Simulation time 22425254 ps
CPU time 1.02 seconds
Started Jan 07 12:40:40 PM PST 24
Finished Jan 07 12:41:40 PM PST 24
Peak memory 221804 kb
Host smart-dbc5053e-dd0e-4aa9-b167-fd7f3cfac70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667809172 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.1667809172
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_smoke.1154974712
Short name T609
Test name
Test status
Simulation time 21119054 ps
CPU time 0.8 seconds
Started Jan 07 12:39:54 PM PST 24
Finished Jan 07 12:41:30 PM PST 24
Peak memory 204748 kb
Host smart-7642fbd3-e7c6-4997-9754-209017280ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154974712 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.1154974712
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.191782098
Short name T305
Test name
Test status
Simulation time 35963619 ps
CPU time 1.27 seconds
Started Jan 07 12:40:11 PM PST 24
Finished Jan 07 12:41:38 PM PST 24
Peak memory 205464 kb
Host smart-fef361e2-9465-4f8e-a952-cf96f4891907
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191782098 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.191782098
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.1288658592
Short name T153
Test name
Test status
Simulation time 79505899797 ps
CPU time 826.37 seconds
Started Jan 07 12:40:06 PM PST 24
Finished Jan 07 12:55:12 PM PST 24
Peak memory 221856 kb
Host smart-abc98389-065c-4d4b-a675-740005d0288d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288658592 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.1288658592
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_genbits.742569566
Short name T526
Test name
Test status
Simulation time 196427147 ps
CPU time 2.52 seconds
Started Jan 07 12:41:23 PM PST 24
Finished Jan 07 12:42:55 PM PST 24
Peak memory 214172 kb
Host smart-0ad3a5e0-fb03-465f-bcbf-4a081f6c8455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742569566 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.742569566
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.3745811827
Short name T637
Test name
Test status
Simulation time 25503733 ps
CPU time 1.09 seconds
Started Jan 07 12:41:35 PM PST 24
Finished Jan 07 12:43:14 PM PST 24
Peak memory 214388 kb
Host smart-2cce20e0-2e48-4e00-b40f-5e7052453c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745811827 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.3745811827
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.3217532052
Short name T564
Test name
Test status
Simulation time 17343588 ps
CPU time 0.94 seconds
Started Jan 07 12:41:22 PM PST 24
Finished Jan 07 12:42:53 PM PST 24
Peak memory 205104 kb
Host smart-7b279e0a-47fc-4576-87d2-0ccdbfd7886f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217532052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.3217532052
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.599993544
Short name T593
Test name
Test status
Simulation time 46027755 ps
CPU time 0.93 seconds
Started Jan 07 12:41:51 PM PST 24
Finished Jan 07 12:43:06 PM PST 24
Peak memory 221628 kb
Host smart-f281ffd0-8ef3-40f4-8e43-d1c66bda9f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599993544 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.599993544
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.1954540646
Short name T572
Test name
Test status
Simulation time 68184475 ps
CPU time 0.96 seconds
Started Jan 07 12:41:33 PM PST 24
Finished Jan 07 12:42:56 PM PST 24
Peak memory 205088 kb
Host smart-64810f56-ee62-4efc-9a77-c5859b71047e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954540646 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.1954540646
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.4211123347
Short name T540
Test name
Test status
Simulation time 28882685 ps
CPU time 1.24 seconds
Started Jan 07 12:41:44 PM PST 24
Finished Jan 07 12:43:11 PM PST 24
Peak memory 221772 kb
Host smart-c5d8e356-1442-43f7-a898-f3a91ddd3958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211123347 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.4211123347
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.673814425
Short name T102
Test name
Test status
Simulation time 42690634 ps
CPU time 1.03 seconds
Started Jan 07 12:41:52 PM PST 24
Finished Jan 07 12:43:15 PM PST 24
Peak memory 205232 kb
Host smart-505d41d7-f1b2-4084-a88e-847323f3f554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673814425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.673814425
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.3370109745
Short name T297
Test name
Test status
Simulation time 71211957 ps
CPU time 0.8 seconds
Started Jan 07 12:41:58 PM PST 24
Finished Jan 07 12:43:35 PM PST 24
Peak memory 215700 kb
Host smart-9ac93763-9f89-47a1-8073-65896f114954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370109745 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.3370109745
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.3969767723
Short name T696
Test name
Test status
Simulation time 21951164 ps
CPU time 1.32 seconds
Started Jan 07 12:41:52 PM PST 24
Finished Jan 07 12:43:25 PM PST 24
Peak memory 205328 kb
Host smart-8882a3da-53f3-4753-842c-bd80d298b863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969767723 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.3969767723
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.1011063572
Short name T733
Test name
Test status
Simulation time 24087544 ps
CPU time 1.04 seconds
Started Jan 07 12:41:29 PM PST 24
Finished Jan 07 12:43:24 PM PST 24
Peak memory 221752 kb
Host smart-6fd24cc2-87db-4815-8dc6-e5eb715646ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011063572 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.1011063572
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.2211292185
Short name T107
Test name
Test status
Simulation time 75647437 ps
CPU time 2.7 seconds
Started Jan 07 12:41:51 PM PST 24
Finished Jan 07 12:43:18 PM PST 24
Peak memory 214188 kb
Host smart-951a417c-a416-4f65-9033-fba25b57ba16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211292185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.2211292185
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.1242437152
Short name T386
Test name
Test status
Simulation time 51745501 ps
CPU time 1.1 seconds
Started Jan 07 12:41:53 PM PST 24
Finished Jan 07 12:43:14 PM PST 24
Peak memory 221736 kb
Host smart-2bf860bb-e07e-486b-810d-5ad77b554601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242437152 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.1242437152
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.98451319
Short name T422
Test name
Test status
Simulation time 62909481 ps
CPU time 2.4 seconds
Started Jan 07 12:41:30 PM PST 24
Finished Jan 07 12:42:43 PM PST 24
Peak memory 214172 kb
Host smart-9297e3d5-967d-40bf-9565-f3cb5850a16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98451319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.98451319
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.1242554465
Short name T568
Test name
Test status
Simulation time 32668584 ps
CPU time 1.38 seconds
Started Jan 07 12:42:09 PM PST 24
Finished Jan 07 12:43:37 PM PST 24
Peak memory 227648 kb
Host smart-3b6ac309-6dd2-49fd-a293-255982f9226c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242554465 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.1242554465
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.2973247584
Short name T462
Test name
Test status
Simulation time 15643784 ps
CPU time 1.04 seconds
Started Jan 07 12:41:48 PM PST 24
Finished Jan 07 12:43:32 PM PST 24
Peak memory 205744 kb
Host smart-c3475e4f-c0e8-4cd5-8918-2d95f54e3e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973247584 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.2973247584
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.2126339057
Short name T331
Test name
Test status
Simulation time 23701882 ps
CPU time 0.86 seconds
Started Jan 07 12:42:07 PM PST 24
Finished Jan 07 12:43:21 PM PST 24
Peak memory 215992 kb
Host smart-4a7a28c8-ddba-47a0-b12c-7daf97a02cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126339057 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.2126339057
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.51929516
Short name T445
Test name
Test status
Simulation time 55403470 ps
CPU time 0.88 seconds
Started Jan 07 12:42:15 PM PST 24
Finished Jan 07 12:43:35 PM PST 24
Peak memory 205424 kb
Host smart-767a5fa9-b1a9-46b7-9579-46f85ae6b7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51929516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.51929516
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.3485304879
Short name T330
Test name
Test status
Simulation time 22553783 ps
CPU time 0.96 seconds
Started Jan 07 12:41:18 PM PST 24
Finished Jan 07 12:42:49 PM PST 24
Peak memory 214528 kb
Host smart-58cf2aa1-9e20-4f64-999c-81edb4ec1438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485304879 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.3485304879
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.2059908282
Short name T524
Test name
Test status
Simulation time 29835751 ps
CPU time 1.06 seconds
Started Jan 07 12:41:52 PM PST 24
Finished Jan 07 12:43:19 PM PST 24
Peak memory 205244 kb
Host smart-74f068c2-2e26-4ab4-b0d1-37ccb3a11e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059908282 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.2059908282
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.1987874282
Short name T219
Test name
Test status
Simulation time 22970344 ps
CPU time 0.96 seconds
Started Jan 07 12:40:43 PM PST 24
Finished Jan 07 12:41:50 PM PST 24
Peak memory 205232 kb
Host smart-d86ebcb4-1b14-450b-96b5-5923edef34e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987874282 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.1987874282
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.352537651
Short name T585
Test name
Test status
Simulation time 35332113 ps
CPU time 0.9 seconds
Started Jan 07 12:40:41 PM PST 24
Finished Jan 07 12:41:43 PM PST 24
Peak memory 204572 kb
Host smart-435e3e6e-6d4f-4c02-bbfe-59411cb4b585
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352537651 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.352537651
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.1975347738
Short name T465
Test name
Test status
Simulation time 38417925 ps
CPU time 1.02 seconds
Started Jan 07 12:40:10 PM PST 24
Finished Jan 07 12:41:12 PM PST 24
Peak memory 214484 kb
Host smart-2621c92d-6325-41ba-a161-f3d3f6cf21eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975347738 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.1975347738
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.3720399409
Short name T457
Test name
Test status
Simulation time 33142205 ps
CPU time 0.87 seconds
Started Jan 07 12:40:08 PM PST 24
Finished Jan 07 12:41:36 PM PST 24
Peak memory 214816 kb
Host smart-8e3d25a8-9153-42eb-bcb1-7cb596edb380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720399409 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.3720399409
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_regwen.1557787115
Short name T199
Test name
Test status
Simulation time 13220316 ps
CPU time 0.91 seconds
Started Jan 07 12:40:13 PM PST 24
Finished Jan 07 12:41:18 PM PST 24
Peak memory 204944 kb
Host smart-dc01b493-d909-4f8d-b699-2dd21a864a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557787115 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.1557787115
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.4096859233
Short name T499
Test name
Test status
Simulation time 15099688 ps
CPU time 0.88 seconds
Started Jan 07 12:40:03 PM PST 24
Finished Jan 07 12:41:15 PM PST 24
Peak memory 204760 kb
Host smart-fdafe4b4-c132-4bb6-99a5-368f9dc2873d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096859233 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.4096859233
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.626540127
Short name T736
Test name
Test status
Simulation time 29952351720 ps
CPU time 640.51 seconds
Started Jan 07 12:40:06 PM PST 24
Finished Jan 07 12:52:04 PM PST 24
Peak memory 214500 kb
Host smart-1c3e5606-dd94-459f-a5b9-eb78b58a43d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626540127 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.626540127
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.1968679379
Short name T325
Test name
Test status
Simulation time 26899255 ps
CPU time 0.82 seconds
Started Jan 07 12:41:43 PM PST 24
Finished Jan 07 12:43:17 PM PST 24
Peak memory 215740 kb
Host smart-f5c490cd-a4a3-433c-bf07-239695e9b61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968679379 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.1968679379
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.3132797024
Short name T267
Test name
Test status
Simulation time 15644214 ps
CPU time 1.01 seconds
Started Jan 07 12:42:09 PM PST 24
Finished Jan 07 12:43:49 PM PST 24
Peak memory 205436 kb
Host smart-be354e86-6097-40e9-af14-42faee170cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132797024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3132797024
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.3918242668
Short name T586
Test name
Test status
Simulation time 17881440 ps
CPU time 1.04 seconds
Started Jan 07 12:41:45 PM PST 24
Finished Jan 07 12:43:26 PM PST 24
Peak memory 215760 kb
Host smart-a3763ae5-72ed-4a52-ab37-634449ddc2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918242668 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.3918242668
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.4227290191
Short name T210
Test name
Test status
Simulation time 17125446 ps
CPU time 0.97 seconds
Started Jan 07 12:41:54 PM PST 24
Finished Jan 07 12:43:30 PM PST 24
Peak memory 205596 kb
Host smart-1a31b337-ea17-465d-9409-5677ea5f0f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227290191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.4227290191
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.379612820
Short name T403
Test name
Test status
Simulation time 18911657 ps
CPU time 0.97 seconds
Started Jan 07 12:41:54 PM PST 24
Finished Jan 07 12:43:35 PM PST 24
Peak memory 215740 kb
Host smart-eb50f314-68fd-47bd-bb8c-b00e9e985e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379612820 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.379612820
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.3255549067
Short name T489
Test name
Test status
Simulation time 46994349 ps
CPU time 1.01 seconds
Started Jan 07 12:41:50 PM PST 24
Finished Jan 07 12:43:45 PM PST 24
Peak memory 205136 kb
Host smart-9ff11efb-1e9c-4e6f-b584-348fdce00946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255549067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.3255549067
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.3871803917
Short name T359
Test name
Test status
Simulation time 19271559 ps
CPU time 1 seconds
Started Jan 07 12:42:00 PM PST 24
Finished Jan 07 12:44:03 PM PST 24
Peak memory 215420 kb
Host smart-512c02ff-0dcb-475e-96ea-f07c420ccb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871803917 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.3871803917
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.607280083
Short name T463
Test name
Test status
Simulation time 17282826 ps
CPU time 1.02 seconds
Started Jan 07 12:41:51 PM PST 24
Finished Jan 07 12:43:16 PM PST 24
Peak memory 205524 kb
Host smart-35358908-dc24-4393-818c-f5ea9ed139c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607280083 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.607280083
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.1366877845
Short name T309
Test name
Test status
Simulation time 23060872 ps
CPU time 0.91 seconds
Started Jan 07 12:41:38 PM PST 24
Finished Jan 07 12:43:00 PM PST 24
Peak memory 215596 kb
Host smart-bb4cbad5-e9c3-4b38-8c87-3f9b7b14f5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366877845 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.1366877845
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/95.edn_err.803059683
Short name T142
Test name
Test status
Simulation time 19661933 ps
CPU time 0.97 seconds
Started Jan 07 12:41:32 PM PST 24
Finished Jan 07 12:43:19 PM PST 24
Peak memory 215580 kb
Host smart-524476cb-17e9-4ed9-948b-329a58ff8dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803059683 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.803059683
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.955217483
Short name T217
Test name
Test status
Simulation time 16048814 ps
CPU time 1.02 seconds
Started Jan 07 12:42:04 PM PST 24
Finished Jan 07 12:43:22 PM PST 24
Peak memory 205244 kb
Host smart-696ef59f-ab02-4c1c-a351-af8edb32d6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955217483 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.955217483
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.3323833860
Short name T594
Test name
Test status
Simulation time 30875125 ps
CPU time 1.01 seconds
Started Jan 07 12:41:25 PM PST 24
Finished Jan 07 12:43:18 PM PST 24
Peak memory 214456 kb
Host smart-d44778bc-d0d7-4711-bc8d-7c0edc427d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323833860 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.3323833860
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/97.edn_err.4054632628
Short name T410
Test name
Test status
Simulation time 31077210 ps
CPU time 0.78 seconds
Started Jan 07 12:41:29 PM PST 24
Finished Jan 07 12:43:31 PM PST 24
Peak memory 215692 kb
Host smart-413ea5c1-603a-4ae5-8228-ba6fd8bd7ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054632628 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.4054632628
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.2978227333
Short name T108
Test name
Test status
Simulation time 22751039 ps
CPU time 1.15 seconds
Started Jan 07 12:41:36 PM PST 24
Finished Jan 07 12:43:13 PM PST 24
Peak memory 205364 kb
Host smart-39bc93df-8c7c-41d0-b0cc-f286ca6401a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978227333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.2978227333
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.2106700752
Short name T532
Test name
Test status
Simulation time 42239354 ps
CPU time 0.81 seconds
Started Jan 07 12:41:45 PM PST 24
Finished Jan 07 12:43:05 PM PST 24
Peak memory 214264 kb
Host smart-bb1b6b8d-3a12-411a-8e14-3acc2d62b146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106700752 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.2106700752
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.4153913765
Short name T52
Test name
Test status
Simulation time 68920493 ps
CPU time 1.02 seconds
Started Jan 07 12:41:49 PM PST 24
Finished Jan 07 12:43:19 PM PST 24
Peak memory 205568 kb
Host smart-acf47517-201f-4042-bb7a-97560f0d0b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153913765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.4153913765
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.3631416913
Short name T589
Test name
Test status
Simulation time 20448517 ps
CPU time 1.09 seconds
Started Jan 07 12:41:45 PM PST 24
Finished Jan 07 12:43:15 PM PST 24
Peak memory 221768 kb
Host smart-02233b93-40f2-421f-80fe-8e7ffb4c39f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631416913 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.3631416913
Directory /workspace/99.edn_err/latest
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