Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	2	0	2	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_intr

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

7549

1

T6

15

T40

4

T42

7

all_values[1]

7549

1

T6

15

T40

4

T42

7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7761

1

T6

17

T40

4

T42

9

auto[1]

7337

1

T6

13

T40

4

T42

5

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5877

1

T6

14

T40

3

T42

6

auto[1]

9221

1

T6

16

T40

5

T42

8

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8877

1

T6

18

T40

4

T42

9

auto[1]

6221

1

T6

12

T40

4

T42

5

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	12	0	12	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

1522

1

T6

4

T40

1

T42

5

all_values[0]

auto[0]

auto[0]

auto[1]

745

1

T6

3

T42

1

T199

1

all_values[0]

auto[0]

auto[1]

auto[0]

1477

1

T6

3

T40

2

T199

2

all_values[0]

auto[0]

auto[1]

auto[1]

724

1

T294

1

T295

2

T296

1

all_values[0]

auto[1]

auto[0]

auto[1]

1633

1

T6

4

T40

1

T42

1

all_values[0]

auto[1]

auto[1]

auto[1]

1448

1

T6

1

T41

1

T204

2

all_values[1]

auto[0]

auto[0]

auto[0]

1515

1

T6

2

T42

1

T199

1

all_values[1]

auto[0]

auto[0]

auto[1]

744

1

T6

1

T40

1

T199

1

all_values[1]

auto[0]

auto[1]

auto[0]

1363

1

T6

5

T204

1

T297

1

all_values[1]

auto[0]

auto[1]

auto[1]

787

1

T42

2

T199

2

T41

1

all_values[1]

auto[1]

auto[0]

auto[1]

1602

1

T6

3

T40

1

T42

1

all_values[1]

auto[1]

auto[1]

auto[1]

1538

1

T6

4

T40

2

T42

3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal