Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.04	99.02	92.46	96.79	93.42	98.62	99.77	99.20

Total test records in report: 979

T775	/workspace/coverage/default/7.edn_alert.2472378709	Jan 10 01:19:19 PM PST 24	Jan 10 01:19:24 PM PST 24	42480661 ps
T776	/workspace/coverage/default/8.edn_genbits.2055441841	Jan 10 01:19:23 PM PST 24	Jan 10 01:19:34 PM PST 24	23882581 ps
T150	/workspace/coverage/default/30.edn_err.4031337393	Jan 10 01:19:49 PM PST 24	Jan 10 01:20:04 PM PST 24	49278411 ps
T777	/workspace/coverage/default/5.edn_err.1717268185	Jan 10 01:18:36 PM PST 24	Jan 10 01:18:44 PM PST 24	28526739 ps
T778	/workspace/coverage/default/89.edn_genbits.3893589318	Jan 10 01:21:02 PM PST 24	Jan 10 01:21:06 PM PST 24	98009197 ps
T779	/workspace/coverage/default/276.edn_genbits.3553617484	Jan 10 01:21:46 PM PST 24	Jan 10 01:22:13 PM PST 24	16813262 ps
T780	/workspace/coverage/default/73.edn_genbits.3440927142	Jan 10 01:20:33 PM PST 24	Jan 10 01:20:43 PM PST 24	21187853 ps
T781	/workspace/coverage/default/30.edn_alert.3144359086	Jan 10 01:19:40 PM PST 24	Jan 10 01:19:54 PM PST 24	35885710 ps
T782	/workspace/coverage/default/49.edn_smoke.697930564	Jan 10 01:20:42 PM PST 24	Jan 10 01:20:50 PM PST 24	13504189 ps
T783	/workspace/coverage/default/31.edn_disable.1743142569	Jan 10 01:19:41 PM PST 24	Jan 10 01:19:55 PM PST 24	23389840 ps
T784	/workspace/coverage/default/108.edn_genbits.3272353261	Jan 10 01:20:47 PM PST 24	Jan 10 01:20:53 PM PST 24	20798193 ps
T785	/workspace/coverage/default/214.edn_genbits.4118243632	Jan 10 01:20:56 PM PST 24	Jan 10 01:21:00 PM PST 24	17169570 ps
T786	/workspace/coverage/default/22.edn_disable_auto_req_mode.2451166260	Jan 10 01:19:33 PM PST 24	Jan 10 01:19:50 PM PST 24	41496234 ps
T787	/workspace/coverage/default/94.edn_err.376450596	Jan 10 01:21:35 PM PST 24	Jan 10 01:21:55 PM PST 24	25769427 ps
T788	/workspace/coverage/default/97.edn_err.2479450631	Jan 10 01:20:47 PM PST 24	Jan 10 01:20:53 PM PST 24	49549450 ps
T789	/workspace/coverage/default/70.edn_err.1223463897	Jan 10 01:20:37 PM PST 24	Jan 10 01:20:48 PM PST 24	23311441 ps
T790	/workspace/coverage/default/38.edn_disable.1979467486	Jan 10 01:20:16 PM PST 24	Jan 10 01:20:20 PM PST 24	16772784 ps
T278	/workspace/coverage/default/218.edn_genbits.1024365095	Jan 10 01:20:58 PM PST 24	Jan 10 01:21:03 PM PST 24	56346236 ps
T791	/workspace/coverage/default/99.edn_err.4278293746	Jan 10 01:20:49 PM PST 24	Jan 10 01:20:55 PM PST 24	35334184 ps
T792	/workspace/coverage/default/189.edn_genbits.685954270	Jan 10 01:20:45 PM PST 24	Jan 10 01:20:51 PM PST 24	263289014 ps
T793	/workspace/coverage/default/28.edn_disable.2669953959	Jan 10 01:19:46 PM PST 24	Jan 10 01:20:01 PM PST 24	23151708 ps
T794	/workspace/coverage/default/22.edn_stress_all.110469184	Jan 10 01:19:27 PM PST 24	Jan 10 01:19:42 PM PST 24	32582160 ps
T795	/workspace/coverage/default/35.edn_smoke.3817646319	Jan 10 01:19:49 PM PST 24	Jan 10 01:20:04 PM PST 24	26687712 ps
T314	/workspace/coverage/default/29.edn_alert.3248453262	Jan 10 01:19:34 PM PST 24	Jan 10 01:19:50 PM PST 24	16925741 ps
T128	/workspace/coverage/default/42.edn_disable.1494315035	Jan 10 01:20:17 PM PST 24	Jan 10 01:20:23 PM PST 24	19797247 ps
T796	/workspace/coverage/default/142.edn_genbits.1760047660	Jan 10 01:20:48 PM PST 24	Jan 10 01:20:55 PM PST 24	106521064 ps
T797	/workspace/coverage/default/22.edn_alert_test.3451921413	Jan 10 01:19:37 PM PST 24	Jan 10 01:19:52 PM PST 24	23416300 ps
T798	/workspace/coverage/default/12.edn_alert_test.3018974889	Jan 10 01:19:22 PM PST 24	Jan 10 01:19:32 PM PST 24	67115735 ps
T799	/workspace/coverage/default/199.edn_genbits.2474250139	Jan 10 01:20:40 PM PST 24	Jan 10 01:20:53 PM PST 24	581497810 ps
T800	/workspace/coverage/default/137.edn_genbits.694484921	Jan 10 01:21:07 PM PST 24	Jan 10 01:21:12 PM PST 24	33540560 ps
T801	/workspace/coverage/default/25.edn_stress_all.2035013205	Jan 10 01:19:29 PM PST 24	Jan 10 01:19:46 PM PST 24	60682100 ps
T802	/workspace/coverage/default/24.edn_alert_test.842886734	Jan 10 01:19:29 PM PST 24	Jan 10 01:19:44 PM PST 24	32611169 ps
T803	/workspace/coverage/default/49.edn_disable_auto_req_mode.3909846541	Jan 10 01:20:56 PM PST 24	Jan 10 01:21:00 PM PST 24	98658234 ps
T804	/workspace/coverage/default/180.edn_genbits.632863326	Jan 10 01:21:40 PM PST 24	Jan 10 01:22:00 PM PST 24	56890216 ps
T805	/workspace/coverage/default/15.edn_disable_auto_req_mode.3211636282	Jan 10 01:19:27 PM PST 24	Jan 10 01:19:42 PM PST 24	206765441 ps
T806	/workspace/coverage/default/38.edn_intr.4274333282	Jan 10 01:20:05 PM PST 24	Jan 10 01:20:11 PM PST 24	79844952 ps
T807	/workspace/coverage/default/3.edn_stress_all_with_rand_reset.1407610450	Jan 10 01:18:36 PM PST 24	Jan 10 01:33:51 PM PST 24	86968529677 ps
T808	/workspace/coverage/default/68.edn_err.2680006138	Jan 10 01:20:23 PM PST 24	Jan 10 01:20:34 PM PST 24	69872092 ps
T316	/workspace/coverage/default/0.edn_regwen.3606512635	Jan 10 01:18:24 PM PST 24	Jan 10 01:18:34 PM PST 24	71135329 ps
T809	/workspace/coverage/default/12.edn_disable.2346554343	Jan 10 01:19:18 PM PST 24	Jan 10 01:19:22 PM PST 24	20800692 ps
T810	/workspace/coverage/default/99.edn_genbits.3966158071	Jan 10 01:20:48 PM PST 24	Jan 10 01:20:54 PM PST 24	16111987 ps
T811	/workspace/coverage/default/151.edn_genbits.1423914251	Jan 10 01:20:53 PM PST 24	Jan 10 01:20:59 PM PST 24	26402336 ps
T812	/workspace/coverage/default/15.edn_stress_all_with_rand_reset.3262114048	Jan 10 01:19:26 PM PST 24	Jan 10 01:53:03 PM PST 24	166195156158 ps
T315	/workspace/coverage/default/10.edn_alert.1268552869	Jan 10 01:19:26 PM PST 24	Jan 10 01:19:39 PM PST 24	53062295 ps
T281	/workspace/coverage/default/58.edn_genbits.3810313949	Jan 10 01:20:22 PM PST 24	Jan 10 01:20:33 PM PST 24	20585248 ps
T813	/workspace/coverage/default/191.edn_genbits.76798514	Jan 10 01:20:54 PM PST 24	Jan 10 01:21:00 PM PST 24	22611098 ps
T814	/workspace/coverage/default/25.edn_smoke.4191151128	Jan 10 01:19:38 PM PST 24	Jan 10 01:19:53 PM PST 24	13677630 ps
T815	/workspace/coverage/default/19.edn_stress_all_with_rand_reset.1963604212	Jan 10 01:19:24 PM PST 24	Jan 10 01:29:21 PM PST 24	103902755613 ps
T816	/workspace/coverage/default/9.edn_stress_all.1711969435	Jan 10 01:19:23 PM PST 24	Jan 10 01:19:35 PM PST 24	216150092 ps
T817	/workspace/coverage/default/20.edn_disable.431686702	Jan 10 01:19:27 PM PST 24	Jan 10 01:19:40 PM PST 24	12714230 ps
T818	/workspace/coverage/default/87.edn_err.1914979769	Jan 10 01:20:49 PM PST 24	Jan 10 01:20:55 PM PST 24	28359532 ps
T819	/workspace/coverage/default/3.edn_smoke.3198563894	Jan 10 01:18:41 PM PST 24	Jan 10 01:18:49 PM PST 24	14018253 ps
T820	/workspace/coverage/default/34.edn_smoke.4031085548	Jan 10 01:19:43 PM PST 24	Jan 10 01:19:58 PM PST 24	57849586 ps
T238	/workspace/coverage/default/88.edn_err.1904814583	Jan 10 01:21:03 PM PST 24	Jan 10 01:21:08 PM PST 24	44939057 ps
T821	/workspace/coverage/default/148.edn_genbits.2655345866	Jan 10 01:20:36 PM PST 24	Jan 10 01:20:46 PM PST 24	20015785 ps
T822	/workspace/coverage/default/34.edn_alert_test.1872646899	Jan 10 01:19:54 PM PST 24	Jan 10 01:20:07 PM PST 24	15829694 ps
T823	/workspace/coverage/default/292.edn_genbits.1586361415	Jan 10 01:21:06 PM PST 24	Jan 10 01:21:11 PM PST 24	146078005 ps
T824	/workspace/coverage/default/204.edn_genbits.1399173607	Jan 10 01:20:51 PM PST 24	Jan 10 01:20:57 PM PST 24	15960314 ps
T825	/workspace/coverage/default/206.edn_genbits.2079834013	Jan 10 01:21:03 PM PST 24	Jan 10 01:21:08 PM PST 24	32018097 ps
T826	/workspace/coverage/default/15.edn_err.3578370642	Jan 10 01:19:29 PM PST 24	Jan 10 01:19:45 PM PST 24	33023196 ps
T827	/workspace/coverage/default/65.edn_genbits.523582424	Jan 10 01:20:22 PM PST 24	Jan 10 01:20:32 PM PST 24	25982100 ps
T828	/workspace/coverage/default/284.edn_genbits.3402923652	Jan 10 01:21:46 PM PST 24	Jan 10 01:22:11 PM PST 24	16735394 ps
T829	/workspace/coverage/default/84.edn_genbits.4033870469	Jan 10 01:20:47 PM PST 24	Jan 10 01:20:53 PM PST 24	119990592 ps
T830	/workspace/coverage/default/265.edn_genbits.3799071964	Jan 10 01:21:40 PM PST 24	Jan 10 01:22:01 PM PST 24	21792691 ps
T831	/workspace/coverage/default/140.edn_genbits.1456667250	Jan 10 01:20:29 PM PST 24	Jan 10 01:20:40 PM PST 24	209034277 ps
T832	/workspace/coverage/default/31.edn_genbits.3020408424	Jan 10 01:19:37 PM PST 24	Jan 10 01:19:52 PM PST 24	47398692 ps
T833	/workspace/coverage/default/18.edn_smoke.1355631413	Jan 10 01:19:22 PM PST 24	Jan 10 01:19:30 PM PST 24	172664587 ps
T834	/workspace/coverage/default/17.edn_genbits.1139756652	Jan 10 01:19:10 PM PST 24	Jan 10 01:19:16 PM PST 24	31194315 ps
T835	/workspace/coverage/default/250.edn_genbits.2654163735	Jan 10 01:21:05 PM PST 24	Jan 10 01:21:10 PM PST 24	23155652 ps
T836	/workspace/coverage/default/253.edn_genbits.1398015203	Jan 10 01:21:32 PM PST 24	Jan 10 01:21:52 PM PST 24	20822029 ps
T837	/workspace/coverage/default/6.edn_smoke.345266232	Jan 10 01:18:38 PM PST 24	Jan 10 01:18:46 PM PST 24	83297605 ps
T838	/workspace/coverage/default/18.edn_stress_all_with_rand_reset.977924266	Jan 10 01:19:22 PM PST 24	Jan 10 01:23:49 PM PST 24	45310764584 ps
T839	/workspace/coverage/default/36.edn_genbits.989657622	Jan 10 01:19:40 PM PST 24	Jan 10 01:19:55 PM PST 24	113054741 ps
T840	/workspace/coverage/default/41.edn_disable.3253140563	Jan 10 01:20:07 PM PST 24	Jan 10 01:20:13 PM PST 24	11897019 ps
T841	/workspace/coverage/default/39.edn_disable.2742031569	Jan 10 01:20:15 PM PST 24	Jan 10 01:20:18 PM PST 24	22589120 ps
T842	/workspace/coverage/default/257.edn_genbits.1251734520	Jan 10 01:21:40 PM PST 24	Jan 10 01:22:01 PM PST 24	52693225 ps
T843	/workspace/coverage/default/18.edn_genbits.1292573919	Jan 10 01:19:22 PM PST 24	Jan 10 01:19:30 PM PST 24	18431891 ps
T844	/workspace/coverage/default/93.edn_err.1681198745	Jan 10 01:21:06 PM PST 24	Jan 10 01:21:11 PM PST 24	19314196 ps
T845	/workspace/coverage/default/23.edn_stress_all.3521344684	Jan 10 01:19:27 PM PST 24	Jan 10 01:19:44 PM PST 24	158821797 ps
T846	/workspace/coverage/default/13.edn_stress_all_with_rand_reset.447014122	Jan 10 01:19:23 PM PST 24	Jan 10 01:28:03 PM PST 24	62517184403 ps
T847	/workspace/coverage/default/138.edn_genbits.1123375919	Jan 10 01:20:34 PM PST 24	Jan 10 01:20:44 PM PST 24	67157861 ps
T848	/workspace/coverage/default/37.edn_smoke.3764193953	Jan 10 01:19:43 PM PST 24	Jan 10 01:19:58 PM PST 24	13900878 ps
T849	/workspace/coverage/default/27.edn_genbits.1948625687	Jan 10 01:19:40 PM PST 24	Jan 10 01:19:54 PM PST 24	29702372 ps
T274	/workspace/coverage/default/181.edn_genbits.321665772	Jan 10 01:21:37 PM PST 24	Jan 10 01:21:56 PM PST 24	38576201 ps
T850	/workspace/coverage/default/294.edn_genbits.1091783596	Jan 10 01:21:31 PM PST 24	Jan 10 01:21:50 PM PST 24	19542350 ps
T851	/workspace/coverage/default/121.edn_genbits.624346623	Jan 10 01:20:31 PM PST 24	Jan 10 01:20:41 PM PST 24	96181848 ps
T852	/workspace/coverage/default/10.edn_stress_all.2056287264	Jan 10 01:19:26 PM PST 24	Jan 10 01:19:41 PM PST 24	667764945 ps
T853	/workspace/coverage/default/3.edn_intr.3865191084	Jan 10 01:18:26 PM PST 24	Jan 10 01:18:36 PM PST 24	18979494 ps
T854	/workspace/coverage/default/0.edn_intr.1932069905	Jan 10 01:18:21 PM PST 24	Jan 10 01:18:28 PM PST 24	26004571 ps
T855	/workspace/coverage/default/6.edn_disable_auto_req_mode.984988071	Jan 10 01:19:09 PM PST 24	Jan 10 01:19:13 PM PST 24	22651203 ps
T856	/workspace/coverage/default/10.edn_smoke.1146887052	Jan 10 01:19:26 PM PST 24	Jan 10 01:19:37 PM PST 24	15413986 ps
T857	/workspace/coverage/default/146.edn_genbits.3402735334	Jan 10 01:20:35 PM PST 24	Jan 10 01:20:45 PM PST 24	59439309 ps
T93	/workspace/coverage/default/9.edn_intr.1543242515	Jan 10 01:19:26 PM PST 24	Jan 10 01:19:38 PM PST 24	19787620 ps
T858	/workspace/coverage/default/185.edn_genbits.519394749	Jan 10 01:21:42 PM PST 24	Jan 10 01:22:05 PM PST 24	51589530 ps
T859	/workspace/coverage/default/240.edn_genbits.1399092375	Jan 10 01:20:56 PM PST 24	Jan 10 01:21:01 PM PST 24	17180028 ps
T860	/workspace/coverage/default/39.edn_err.3651596562	Jan 10 01:20:03 PM PST 24	Jan 10 01:20:10 PM PST 24	22818373 ps
T861	/workspace/coverage/default/36.edn_alert_test.2873166644	Jan 10 01:19:43 PM PST 24	Jan 10 01:19:58 PM PST 24	51886768 ps
T326	/workspace/coverage/default/6.edn_regwen.2192043100	Jan 10 01:18:30 PM PST 24	Jan 10 01:18:38 PM PST 24	37924726 ps
T862	/workspace/coverage/default/167.edn_genbits.727293870	Jan 10 01:21:04 PM PST 24	Jan 10 01:21:09 PM PST 24	35073300 ps
T289	/workspace/coverage/default/145.edn_genbits.1502444136	Jan 10 01:20:50 PM PST 24	Jan 10 01:20:56 PM PST 24	45437828 ps
T863	/workspace/coverage/default/37.edn_err.2825856216	Jan 10 01:20:22 PM PST 24	Jan 10 01:20:33 PM PST 24	29079781 ps
T864	/workspace/coverage/default/25.edn_stress_all_with_rand_reset.415326066	Jan 10 01:19:27 PM PST 24	Jan 10 01:28:54 PM PST 24	61824620808 ps
T865	/workspace/coverage/default/298.edn_genbits.3511166394	Jan 10 01:20:56 PM PST 24	Jan 10 01:21:01 PM PST 24	19233614 ps
T866	/workspace/coverage/default/46.edn_disable_auto_req_mode.1061286654	Jan 10 01:20:21 PM PST 24	Jan 10 01:20:30 PM PST 24	30939289 ps
T867	/workspace/coverage/default/223.edn_genbits.2637973937	Jan 10 01:21:05 PM PST 24	Jan 10 01:21:10 PM PST 24	15227250 ps
T868	/workspace/coverage/default/19.edn_alert_test.1221518976	Jan 10 01:19:30 PM PST 24	Jan 10 01:19:46 PM PST 24	16264605 ps
T869	/workspace/coverage/default/133.edn_genbits.3613133305	Jan 10 01:20:34 PM PST 24	Jan 10 01:20:44 PM PST 24	16429406 ps
T870	/workspace/coverage/default/143.edn_genbits.2619319187	Jan 10 01:20:49 PM PST 24	Jan 10 01:20:55 PM PST 24	18076288 ps
T871	/workspace/coverage/default/59.edn_genbits.4135190643	Jan 10 01:20:29 PM PST 24	Jan 10 01:20:38 PM PST 24	45256838 ps
T872	/workspace/coverage/default/26.edn_alert_test.572808206	Jan 10 01:19:39 PM PST 24	Jan 10 01:19:54 PM PST 24	15987256 ps
T873	/workspace/coverage/default/232.edn_genbits.628974520	Jan 10 01:20:56 PM PST 24	Jan 10 01:21:00 PM PST 24	18214544 ps
T874	/workspace/coverage/default/34.edn_disable_auto_req_mode.601856316	Jan 10 01:19:49 PM PST 24	Jan 10 01:20:04 PM PST 24	41234567 ps
T875	/workspace/coverage/default/256.edn_genbits.2533814447	Jan 10 01:21:37 PM PST 24	Jan 10 01:21:56 PM PST 24	52684457 ps
T876	/workspace/coverage/default/39.edn_alert.2611382262	Jan 10 01:20:11 PM PST 24	Jan 10 01:20:14 PM PST 24	87712204 ps
T877	/workspace/coverage/default/25.edn_disable_auto_req_mode.1600522186	Jan 10 01:19:31 PM PST 24	Jan 10 01:19:48 PM PST 24	28998889 ps
T878	/workspace/coverage/default/105.edn_genbits.1398251119	Jan 10 01:20:31 PM PST 24	Jan 10 01:20:42 PM PST 24	145943671 ps
T879	/workspace/coverage/default/11.edn_alert.3906162889	Jan 10 01:19:19 PM PST 24	Jan 10 01:19:24 PM PST 24	149243523 ps
T880	/workspace/coverage/default/19.edn_disable_auto_req_mode.1765697683	Jan 10 01:19:25 PM PST 24	Jan 10 01:19:37 PM PST 24	24535867 ps
T881	/workspace/coverage/default/30.edn_genbits.956550808	Jan 10 01:19:40 PM PST 24	Jan 10 01:19:54 PM PST 24	99434790 ps
T882	/workspace/coverage/default/34.edn_genbits.1181477143	Jan 10 01:19:44 PM PST 24	Jan 10 01:19:59 PM PST 24	13816009 ps
T883	/workspace/coverage/default/6.edn_alert_test.1044546876	Jan 10 01:19:20 PM PST 24	Jan 10 01:19:25 PM PST 24	47773207 ps
T235	/workspace/coverage/default/91.edn_err.4041738388	Jan 10 01:20:54 PM PST 24	Jan 10 01:21:00 PM PST 24	68446525 ps
T884	/workspace/coverage/default/177.edn_genbits.1795980384	Jan 10 01:21:38 PM PST 24	Jan 10 01:21:58 PM PST 24	152031893 ps
T885	/workspace/coverage/default/54.edn_err.1704553641	Jan 10 01:21:28 PM PST 24	Jan 10 01:21:41 PM PST 24	19038242 ps
T886	/workspace/coverage/default/14.edn_err.1883567624	Jan 10 01:19:25 PM PST 24	Jan 10 01:19:37 PM PST 24	24636709 ps
T887	/workspace/coverage/default/17.edn_smoke.621573189	Jan 10 01:19:13 PM PST 24	Jan 10 01:19:18 PM PST 24	35864092 ps
T888	/workspace/coverage/default/44.edn_alert_test.990720064	Jan 10 01:20:20 PM PST 24	Jan 10 01:20:29 PM PST 24	69092768 ps
T889	/workspace/coverage/default/18.edn_disable.3540503649	Jan 10 01:19:23 PM PST 24	Jan 10 01:19:32 PM PST 24	87539320 ps
T890	/workspace/coverage/default/9.edn_alert.1588957255	Jan 10 01:19:26 PM PST 24	Jan 10 01:19:38 PM PST 24	50904284 ps
T891	/workspace/coverage/default/37.edn_alert_test.1841154284	Jan 10 01:20:02 PM PST 24	Jan 10 01:20:10 PM PST 24	55995397 ps
T892	/workspace/coverage/default/19.edn_intr.2392704594	Jan 10 01:19:26 PM PST 24	Jan 10 01:19:39 PM PST 24	19388997 ps
T893	/workspace/coverage/default/23.edn_intr.1761155908	Jan 10 01:19:39 PM PST 24	Jan 10 01:19:54 PM PST 24	41105119 ps
T894	/workspace/coverage/default/17.edn_disable_auto_req_mode.1165283862	Jan 10 01:19:22 PM PST 24	Jan 10 01:19:30 PM PST 24	22171663 ps
T895	/workspace/coverage/default/62.edn_err.3862822586	Jan 10 01:20:28 PM PST 24	Jan 10 01:20:38 PM PST 24	19238571 ps
T896	/workspace/coverage/default/1.edn_alert_test.3271243479	Jan 10 01:18:34 PM PST 24	Jan 10 01:18:42 PM PST 24	21580396 ps
T897	/workspace/coverage/default/45.edn_alert_test.2271074557	Jan 10 01:20:19 PM PST 24	Jan 10 01:20:27 PM PST 24	24202296 ps
T248	/workspace/coverage/default/80.edn_err.3382530085	Jan 10 01:20:20 PM PST 24	Jan 10 01:20:28 PM PST 24	70050493 ps
T898	/workspace/coverage/default/40.edn_disable_auto_req_mode.4160238299	Jan 10 01:20:23 PM PST 24	Jan 10 01:20:34 PM PST 24	37853311 ps
T899	/workspace/coverage/default/2.edn_genbits.3761627057	Jan 10 01:18:43 PM PST 24	Jan 10 01:18:50 PM PST 24	33192071 ps
T900	/workspace/coverage/default/23.edn_genbits.1662714590	Jan 10 01:19:29 PM PST 24	Jan 10 01:19:46 PM PST 24	142270304 ps
T901	/workspace/coverage/default/45.edn_genbits.1856528344	Jan 10 01:20:21 PM PST 24	Jan 10 01:20:30 PM PST 24	32772822 ps
T902	/workspace/coverage/default/45.edn_disable_auto_req_mode.3870199409	Jan 10 01:20:22 PM PST 24	Jan 10 01:20:32 PM PST 24	107067343 ps
T903	/workspace/coverage/default/47.edn_alert.4233521	Jan 10 01:20:17 PM PST 24	Jan 10 01:20:23 PM PST 24	18417541 ps
T904	/workspace/coverage/default/15.edn_genbits.1300276801	Jan 10 01:19:24 PM PST 24	Jan 10 01:19:38 PM PST 24	119638453 ps
T905	/workspace/coverage/default/22.edn_genbits.3412895026	Jan 10 01:19:37 PM PST 24	Jan 10 01:19:54 PM PST 24	61867625 ps
T906	/workspace/coverage/default/40.edn_stress_all.4249234122	Jan 10 01:20:13 PM PST 24	Jan 10 01:20:19 PM PST 24	400855806 ps
T907	/workspace/coverage/default/68.edn_genbits.3004639966	Jan 10 01:20:20 PM PST 24	Jan 10 01:20:28 PM PST 24	49534487 ps
T908	/workspace/coverage/default/7.edn_alert_test.344312470	Jan 10 01:19:20 PM PST 24	Jan 10 01:19:24 PM PST 24	15950717 ps
T909	/workspace/coverage/default/190.edn_genbits.3519151021	Jan 10 01:20:33 PM PST 24	Jan 10 01:20:45 PM PST 24	156810320 ps
T910	/workspace/coverage/default/233.edn_genbits.1192940996	Jan 10 01:21:29 PM PST 24	Jan 10 01:21:44 PM PST 24	66681655 ps
T911	/workspace/coverage/default/44.edn_smoke.274884504	Jan 10 01:20:19 PM PST 24	Jan 10 01:20:28 PM PST 24	59330626 ps
T177	/workspace/coverage/default/2.edn_disable.2578010676	Jan 10 01:18:38 PM PST 24	Jan 10 01:18:47 PM PST 24	14043041 ps
T912	/workspace/coverage/default/15.edn_intr.2264796760	Jan 10 01:19:26 PM PST 24	Jan 10 01:19:38 PM PST 24	52860066 ps
T913	/workspace/coverage/default/45.edn_err.1956234566	Jan 10 01:20:17 PM PST 24	Jan 10 01:20:24 PM PST 24	51451604 ps
T130	/workspace/coverage/default/26.edn_disable.2934213824	Jan 10 01:19:38 PM PST 24	Jan 10 01:19:52 PM PST 24	52409125 ps
T914	/workspace/coverage/default/13.edn_intr.3578626706	Jan 10 01:19:24 PM PST 24	Jan 10 01:19:35 PM PST 24	27192079 ps
T915	/workspace/coverage/default/10.edn_alert_test.2186542688	Jan 10 01:19:27 PM PST 24	Jan 10 01:19:42 PM PST 24	68892557 ps
T916	/workspace/coverage/default/11.edn_stress_all_with_rand_reset.721196661	Jan 10 01:19:09 PM PST 24	Jan 10 01:34:47 PM PST 24	37090093219 ps
T291	/workspace/coverage/default/95.edn_genbits.438649846	Jan 10 01:21:04 PM PST 24	Jan 10 01:21:09 PM PST 24	74965106 ps
T180	/workspace/coverage/default/1.edn_err.3873178358	Jan 10 01:18:28 PM PST 24	Jan 10 01:18:37 PM PST 24	21652190 ps
T917	/workspace/coverage/default/21.edn_alert.3670455306	Jan 10 01:19:10 PM PST 24	Jan 10 01:19:15 PM PST 24	42151792 ps
T239	/workspace/coverage/default/35.edn_disable.1537927506	Jan 10 01:19:52 PM PST 24	Jan 10 01:20:06 PM PST 24	16571589 ps
T918	/workspace/coverage/default/154.edn_genbits.3509551409	Jan 10 01:21:05 PM PST 24	Jan 10 01:21:09 PM PST 24	134652596 ps
T919	/workspace/coverage/default/2.edn_alert.1883283090	Jan 10 01:18:30 PM PST 24	Jan 10 01:18:38 PM PST 24	18351255 ps
T920	/workspace/coverage/default/16.edn_alert_test.3267072482	Jan 10 01:19:08 PM PST 24	Jan 10 01:19:11 PM PST 24	13214684 ps
T122	/workspace/coverage/default/36.edn_disable.2679320949	Jan 10 01:19:48 PM PST 24	Jan 10 01:20:03 PM PST 24	17773332 ps
T921	/workspace/coverage/default/227.edn_genbits.811464993	Jan 10 01:20:59 PM PST 24	Jan 10 01:21:05 PM PST 24	15171884 ps
T271	/workspace/coverage/default/24.edn_genbits.1905795744	Jan 10 01:19:35 PM PST 24	Jan 10 01:19:50 PM PST 24	16559331 ps
T922	/workspace/coverage/default/39.edn_smoke.2351275977	Jan 10 01:20:11 PM PST 24	Jan 10 01:20:15 PM PST 24	13378764 ps
T923	/workspace/coverage/default/36.edn_disable_auto_req_mode.2482547656	Jan 10 01:19:38 PM PST 24	Jan 10 01:19:52 PM PST 24	103952570 ps
T924	/workspace/coverage/default/26.edn_stress_all.4036616757	Jan 10 01:19:28 PM PST 24	Jan 10 01:19:44 PM PST 24	49434296 ps
T925	/workspace/coverage/default/5.edn_intr.4267285846	Jan 10 01:18:43 PM PST 24	Jan 10 01:18:50 PM PST 24	18647758 ps
T926	/workspace/coverage/default/282.edn_genbits.1148872960	Jan 10 01:21:45 PM PST 24	Jan 10 01:22:10 PM PST 24	27279416 ps
T927	/workspace/coverage/default/25.edn_alert_test.3989741922	Jan 10 01:19:37 PM PST 24	Jan 10 01:19:52 PM PST 24	35713402 ps
T928	/workspace/coverage/default/31.edn_err.149065066	Jan 10 01:19:40 PM PST 24	Jan 10 01:19:54 PM PST 24	20679987 ps
T929	/workspace/coverage/default/46.edn_alert.929908484	Jan 10 01:20:22 PM PST 24	Jan 10 01:20:32 PM PST 24	22695308 ps
T930	/workspace/coverage/default/43.edn_genbits.4165457130	Jan 10 01:20:22 PM PST 24	Jan 10 01:20:33 PM PST 24	142908472 ps
T931	/workspace/coverage/default/79.edn_err.2069965989	Jan 10 01:20:21 PM PST 24	Jan 10 01:20:30 PM PST 24	19347642 ps
T932	/workspace/coverage/default/47.edn_stress_all_with_rand_reset.681227589	Jan 10 01:20:22 PM PST 24	Jan 10 01:56:51 PM PST 24	89709434070 ps
T933	/workspace/coverage/default/186.edn_genbits.130283476	Jan 10 01:20:47 PM PST 24	Jan 10 01:20:53 PM PST 24	47722929 ps
T934	/workspace/coverage/default/155.edn_genbits.3594049534	Jan 10 01:21:29 PM PST 24	Jan 10 01:21:45 PM PST 24	17178436 ps
T935	/workspace/coverage/default/28.edn_alert.2934689851	Jan 10 01:19:40 PM PST 24	Jan 10 01:19:54 PM PST 24	71423491 ps
T936	/workspace/coverage/default/4.edn_genbits.2736475402	Jan 10 01:18:37 PM PST 24	Jan 10 01:18:46 PM PST 24	98773184 ps
T937	/workspace/coverage/default/12.edn_genbits.2479122030	Jan 10 01:19:09 PM PST 24	Jan 10 01:19:13 PM PST 24	52710931 ps
T938	/workspace/coverage/default/13.edn_genbits.3532960243	Jan 10 01:19:23 PM PST 24	Jan 10 01:19:34 PM PST 24	46363333 ps
T939	/workspace/coverage/default/47.edn_disable_auto_req_mode.1819169014	Jan 10 01:20:20 PM PST 24	Jan 10 01:20:29 PM PST 24	184597973 ps
T940	/workspace/coverage/default/56.edn_genbits.827615540	Jan 10 01:20:31 PM PST 24	Jan 10 01:20:40 PM PST 24	17196170 ps
T232	/workspace/coverage/default/89.edn_err.3393327883	Jan 10 01:20:56 PM PST 24	Jan 10 01:21:01 PM PST 24	32018271 ps
T941	/workspace/coverage/default/86.edn_genbits.2490961128	Jan 10 01:20:34 PM PST 24	Jan 10 01:20:44 PM PST 24	63711221 ps
T942	/workspace/coverage/default/33.edn_err.1236626165	Jan 10 01:19:42 PM PST 24	Jan 10 01:19:57 PM PST 24	29183209 ps
T943	/workspace/coverage/default/32.edn_alert_test.94177975	Jan 10 01:19:47 PM PST 24	Jan 10 01:20:02 PM PST 24	15278803 ps
T944	/workspace/coverage/default/212.edn_genbits.3669098963	Jan 10 01:20:59 PM PST 24	Jan 10 01:21:05 PM PST 24	51997874 ps
T945	/workspace/coverage/default/1.edn_intr.4213256700	Jan 10 01:18:38 PM PST 24	Jan 10 01:18:45 PM PST 24	30767469 ps
T946	/workspace/coverage/default/208.edn_genbits.3857231924	Jan 10 01:21:32 PM PST 24	Jan 10 01:21:54 PM PST 24	42786131 ps
T947	/workspace/coverage/default/41.edn_genbits.1768678834	Jan 10 01:20:04 PM PST 24	Jan 10 01:20:11 PM PST 24	74911858 ps
T948	/workspace/coverage/default/260.edn_genbits.1748664648	Jan 10 01:21:38 PM PST 24	Jan 10 01:21:58 PM PST 24	47889848 ps
T111	/workspace/coverage/default/13.edn_disable_auto_req_mode.1392726896	Jan 10 01:19:24 PM PST 24	Jan 10 01:19:36 PM PST 24	61909360 ps
T949	/workspace/coverage/default/29.edn_disable.1461053331	Jan 10 01:19:42 PM PST 24	Jan 10 01:19:56 PM PST 24	13271379 ps
T950	/workspace/coverage/default/13.edn_stress_all.3502727615	Jan 10 01:19:21 PM PST 24	Jan 10 01:19:31 PM PST 24	258619706 ps
T951	/workspace/coverage/default/237.edn_genbits.3542086478	Jan 10 01:21:30 PM PST 24	Jan 10 01:21:48 PM PST 24	27355628 ps
T952	/workspace/coverage/default/28.edn_genbits.4091001024	Jan 10 01:19:39 PM PST 24	Jan 10 01:19:54 PM PST 24	17874456 ps
T953	/workspace/coverage/default/36.edn_alert.218394234	Jan 10 01:19:47 PM PST 24	Jan 10 01:20:02 PM PST 24	18491741 ps
T954	/workspace/coverage/default/288.edn_genbits.3580985907	Jan 10 01:21:24 PM PST 24	Jan 10 01:21:30 PM PST 24	56414399 ps
T955	/workspace/coverage/default/81.edn_err.1365476055	Jan 10 01:20:31 PM PST 24	Jan 10 01:20:40 PM PST 24	36033512 ps
T956	/workspace/coverage/default/19.edn_stress_all.648113285	Jan 10 01:19:24 PM PST 24	Jan 10 01:19:36 PM PST 24	37775442 ps
T957	/workspace/coverage/default/4.edn_alert.974887963	Jan 10 01:18:43 PM PST 24	Jan 10 01:18:50 PM PST 24	18822917 ps
T958	/workspace/coverage/default/3.edn_err.3277385088	Jan 10 01:18:32 PM PST 24	Jan 10 01:18:40 PM PST 24	18563417 ps
T959	/workspace/coverage/default/35.edn_genbits.1211420154	Jan 10 01:19:43 PM PST 24	Jan 10 01:19:59 PM PST 24	66375949 ps
T960	/workspace/coverage/default/115.edn_genbits.48946574	Jan 10 01:20:35 PM PST 24	Jan 10 01:20:45 PM PST 24	50696948 ps
T961	/workspace/coverage/default/5.edn_alert.326051718	Jan 10 01:18:37 PM PST 24	Jan 10 01:18:44 PM PST 24	27543928 ps
T59	/workspace/coverage/default/0.edn_sec_cm.1160585603	Jan 10 01:18:25 PM PST 24	Jan 10 01:18:36 PM PST 24	631587435 ps
T962	/workspace/coverage/default/102.edn_genbits.4238303621	Jan 10 01:20:53 PM PST 24	Jan 10 01:20:59 PM PST 24	18535666 ps
T963	/workspace/coverage/default/109.edn_genbits.1145804321	Jan 10 01:20:51 PM PST 24	Jan 10 01:20:57 PM PST 24	52663614 ps
T964	/workspace/coverage/default/14.edn_intr.1249477679	Jan 10 01:19:26 PM PST 24	Jan 10 01:19:38 PM PST 24	25344266 ps
T965	/workspace/coverage/default/38.edn_err.4265836383	Jan 10 01:20:02 PM PST 24	Jan 10 01:20:10 PM PST 24	138072070 ps
T966	/workspace/coverage/default/5.edn_stress_all.4069658178	Jan 10 01:18:38 PM PST 24	Jan 10 01:18:48 PM PST 24	132170229 ps
T967	/workspace/coverage/default/64.edn_genbits.2906815818	Jan 10 01:20:30 PM PST 24	Jan 10 01:20:40 PM PST 24	65049973 ps
T968	/workspace/coverage/default/28.edn_stress_all.1513793289	Jan 10 01:19:29 PM PST 24	Jan 10 01:19:46 PM PST 24	101146102 ps
T969	/workspace/coverage/default/29.edn_genbits.2373991726	Jan 10 01:19:34 PM PST 24	Jan 10 01:19:50 PM PST 24	40309036 ps
T970	/workspace/coverage/default/15.edn_alert.847104668	Jan 10 01:19:30 PM PST 24	Jan 10 01:19:47 PM PST 24	21379458 ps
T971	/workspace/coverage/default/83.edn_err.3328338881	Jan 10 01:20:32 PM PST 24	Jan 10 01:20:41 PM PST 24	30946830 ps
T972	/workspace/coverage/default/18.edn_alert_test.2558863041	Jan 10 01:19:26 PM PST 24	Jan 10 01:19:38 PM PST 24	39013218 ps
T973	/workspace/coverage/default/35.edn_disable_auto_req_mode.1866916413	Jan 10 01:19:46 PM PST 24	Jan 10 01:20:01 PM PST 24	19635055 ps
T974	/workspace/coverage/default/248.edn_genbits.1416226427	Jan 10 01:21:32 PM PST 24	Jan 10 01:21:52 PM PST 24	15995801 ps
T975	/workspace/coverage/default/20.edn_genbits.3605457977	Jan 10 01:19:26 PM PST 24	Jan 10 01:19:38 PM PST 24	40472409 ps
T976	/workspace/coverage/default/44.edn_intr.1059044653	Jan 10 01:20:20 PM PST 24	Jan 10 01:20:28 PM PST 24	22464152 ps
T977	/workspace/coverage/default/32.edn_genbits.3875253662	Jan 10 01:19:40 PM PST 24	Jan 10 01:19:54 PM PST 24	47830042 ps
T978	/workspace/coverage/default/30.edn_stress_all.3023722551	Jan 10 01:19:42 PM PST 24	Jan 10 01:19:59 PM PST 24	430732586 ps
T979	/workspace/coverage/default/7.edn_smoke.1727307001	Jan 10 01:19:10 PM PST 24	Jan 10 01:19:14 PM PST 24	25643188 ps

Test location	/workspace/coverage/default/26.edn_genbits.1312820875
Short name	T1
Test name
Test status
Simulation time	50521032 ps
CPU time	1.26 seconds
Started	Jan 10 01:19:37 PM PST 24
Finished	Jan 10 01:19:52 PM PST 24
Peak memory	214252 kb
Host	smart-bee163cb-8d0a-4118-9e99-862d0a3697d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1312820875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.1312820875
Directory	/workspace/26.edn_genbits/latest

Test location	/workspace/coverage/default/35.edn_stress_all.1427132596
Short name	T6
Test name
Test status
Simulation time	397690732 ps
CPU time	2.8 seconds
Started	Jan 10 01:19:52 PM PST 24
Finished	Jan 10 01:20:08 PM PST 24
Peak memory	205688 kb
Host	smart-e8293d17-352b-4d31-b83d-81a55b228526
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427132596 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.1427132596
Directory	/workspace/35.edn_stress_all/latest

Test location	/workspace/coverage/default/72.edn_genbits.2820486821
Short name	T32
Test name
Test status
Simulation time	38606055 ps
CPU time	1.15 seconds
Started	Jan 10 01:20:31 PM PST 24
Finished	Jan 10 01:20:40 PM PST 24
Peak memory	205892 kb
Host	smart-772efeab-6a5a-422f-a7fc-0c0971cadd5d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2820486821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.2820486821
Directory	/workspace/72.edn_genbits/latest

Test location	/workspace/coverage/default/65.edn_err.2084819259
Short name	T4
Test name
Test status
Simulation time	30875889 ps
CPU time	0.99 seconds
Started	Jan 10 01:20:23 PM PST 24
Finished	Jan 10 01:20:34 PM PST 24
Peak memory	215892 kb
Host	smart-8a7fd364-aafb-41d6-ac6e-d6b582e85f90
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2084819259 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.2084819259
Directory	/workspace/65.edn_err/latest

Test location	/workspace/coverage/default/1.edn_sec_cm.2700867083
Short name	T23
Test name
Test status
Simulation time	267902406 ps
CPU time	4.41 seconds
Started	Jan 10 01:18:33 PM PST 24
Finished	Jan 10 01:18:44 PM PST 24
Peak memory	232028 kb
Host	smart-a72fa94f-bed8-49c1-878d-7c7a7f104e80
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700867083 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.2700867083
Directory	/workspace/1.edn_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/0.edn_tl_errors.3200764147
Short name	T135
Test name
Test status
Simulation time	1486711814 ps
CPU time	3.68 seconds
Started	Jan 10 12:57:51 PM PST 24
Finished	Jan 10 12:59:13 PM PST 24
Peak memory	214312 kb
Host	smart-e53e0da6-1417-43a4-b888-9e229432b5c9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200764147 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3200764147
Directory	/workspace/0.edn_tl_errors/latest

Test location	/workspace/coverage/default/24.edn_disable_auto_req_mode.3592220359
Short name	T77
Test name
Test status
Simulation time	33800495 ps
CPU time	1.05 seconds
Started	Jan 10 01:19:36 PM PST 24
Finished	Jan 10 01:19:51 PM PST 24
Peak memory	214712 kb
Host	smart-dbf649fc-1b3f-4491-821a-aab3bb57ab3b
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592220359 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d isable_auto_req_mode.3592220359
Directory	/workspace/24.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/15.edn_stress_all.1047016510
Short name	T227
Test name
Test status
Simulation time	588731309 ps
CPU time	3.48 seconds
Started	Jan 10 01:19:25 PM PST 24
Finished	Jan 10 01:19:39 PM PST 24
Peak memory	206112 kb
Host	smart-626cda37-2043-4973-9e98-35030131bb0d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047016510 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.1047016510
Directory	/workspace/15.edn_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/15.edn_tl_intg_err.574690057
Short name	T26
Test name
Test status
Simulation time	83103468 ps
CPU time	1.6 seconds
Started	Jan 10 12:58:12 PM PST 24
Finished	Jan 10 12:59:33 PM PST 24
Peak memory	206072 kb
Host	smart-8842f360-0345-44d9-8e47-a738e2a8f1d7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574690057 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.574690057
Directory	/workspace/15.edn_tl_intg_err/latest

Test location	/workspace/coverage/default/17.edn_intr.2295692294
Short name	T36
Test name
Test status
Simulation time	50481034 ps
CPU time	0.85 seconds
Started	Jan 10 01:19:22 PM PST 24
Finished	Jan 10 01:19:30 PM PST 24
Peak memory	214512 kb
Host	smart-4b590b3a-d88c-461f-b7c5-dd3a3168ad93
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2295692294 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.2295692294
Directory	/workspace/17.edn_intr/latest

Test location	/workspace/coverage/default/20.edn_stress_all_with_rand_reset.1966130655
Short name	T80
Test name
Test status
Simulation time	283577126060 ps
CPU time	1666.45 seconds
Started	Jan 10 01:19:26 PM PST 24
Finished	Jan 10 01:47:24 PM PST 24
Peak memory	220888 kb
Host	smart-ee8b20d8-5e78-425f-ae5d-385998f1d41c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966130655 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.1966130655
Directory	/workspace/20.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/71.edn_err.245130521
Short name	T48
Test name
Test status
Simulation time	24001203 ps
CPU time	1.25 seconds
Started	Jan 10 01:20:31 PM PST 24
Finished	Jan 10 01:20:40 PM PST 24
Peak memory	220108 kb
Host	smart-a25cf3c1-7cd6-4105-80a1-2758728adcd7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=245130521 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.245130521
Directory	/workspace/71.edn_err/latest

Test location	/workspace/coverage/default/32.edn_alert.296535424
Short name	T18
Test name
Test status
Simulation time	30905070 ps
CPU time	0.97 seconds
Started	Jan 10 01:19:47 PM PST 24
Finished	Jan 10 01:20:02 PM PST 24
Peak memory	206052 kb
Host	smart-603b3c50-12c2-49a6-b168-cd1cb0db8351
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=296535424 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.296535424
Directory	/workspace/32.edn_alert/latest

Test location	/workspace/coverage/default/32.edn_disable.3411131512
Short name	T50
Test name
Test status
Simulation time	46004350 ps
CPU time	0.78 seconds
Started	Jan 10 01:19:39 PM PST 24
Finished	Jan 10 01:19:53 PM PST 24
Peak memory	214584 kb
Host	smart-c2340a39-96a7-4b2c-886f-7972730d0462
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411131512 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.3411131512
Directory	/workspace/32.edn_disable/latest

Test location	/workspace/coverage/cover_reg_top/1.edn_csr_aliasing.605541591
Short name	T193
Test name
Test status
Simulation time	84989645 ps
CPU time	1.09 seconds
Started	Jan 10 12:59:46 PM PST 24
Finished	Jan 10 01:01:20 PM PST 24
Peak memory	204880 kb
Host	smart-8d311773-ed86-4bfb-8599-1d62660164b7
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605541591 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.605541591
Directory	/workspace/1.edn_csr_aliasing/latest

Test location	/workspace/coverage/default/10.edn_disable.3090780619
Short name	T120
Test name
Test status
Simulation time	11199081 ps
CPU time	0.88 seconds
Started	Jan 10 01:19:26 PM PST 24
Finished	Jan 10 01:19:38 PM PST 24
Peak memory	214488 kb
Host	smart-727b9361-e8f0-4f34-8cf1-006609836443
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090780619 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.3090780619
Directory	/workspace/10.edn_disable/latest

Test location	/workspace/coverage/default/16.edn_intr.4217678326
Short name	T73
Test name
Test status
Simulation time	35818093 ps
CPU time	0.85 seconds
Started	Jan 10 01:19:09 PM PST 24
Finished	Jan 10 01:19:12 PM PST 24
Peak memory	214508 kb
Host	smart-0799b649-4304-41a7-b7ca-044a646c294c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4217678326 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.4217678326
Directory	/workspace/16.edn_intr/latest

Test location	/workspace/coverage/default/1.edn_disable_auto_req_mode.2775541936
Short name	T113
Test name
Test status
Simulation time	337740720 ps
CPU time	1.05 seconds
Started	Jan 10 01:18:38 PM PST 24
Finished	Jan 10 01:18:46 PM PST 24
Peak memory	206532 kb
Host	smart-bd2e9b4f-c7f7-4780-bac9-ac99dc184684
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775541936 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di sable_auto_req_mode.2775541936
Directory	/workspace/1.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/26.edn_disable.2934213824
Short name	T130
Test name
Test status
Simulation time	52409125 ps
CPU time	0.91 seconds
Started	Jan 10 01:19:38 PM PST 24
Finished	Jan 10 01:19:52 PM PST 24
Peak memory	214448 kb
Host	smart-2a31bd15-a8e3-46d5-8a99-290f9e0f3e30
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934213824 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.2934213824
Directory	/workspace/26.edn_disable/latest

Test location	/workspace/coverage/default/0.edn_regwen.3606512635
Short name	T316
Test name
Test status
Simulation time	71135329 ps
CPU time	0.85 seconds
Started	Jan 10 01:18:24 PM PST 24
Finished	Jan 10 01:18:34 PM PST 24
Peak memory	204820 kb
Host	smart-914aff40-7cf4-4f14-9a08-12218f4db2f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3606512635 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.3606512635
Directory	/workspace/0.edn_regwen/latest

Test location	/workspace/coverage/default/29.edn_disable.1461053331
Short name	T949
Test name
Test status
Simulation time	13271379 ps
CPU time	0.86 seconds
Started	Jan 10 01:19:42 PM PST 24
Finished	Jan 10 01:19:56 PM PST 24
Peak memory	214620 kb
Host	smart-2d634218-7f2b-44b2-a42a-18273adfda2d
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461053331 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.1461053331
Directory	/workspace/29.edn_disable/latest

Test location	/workspace/coverage/default/34.edn_disable.3944266185
Short name	T182
Test name
Test status
Simulation time	14000083 ps
CPU time	0.85 seconds
Started	Jan 10 01:19:35 PM PST 24
Finished	Jan 10 01:19:50 PM PST 24
Peak memory	214560 kb
Host	smart-9ec0760e-b895-4a1e-a1a8-9237d4a95f7e
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944266185 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.3944266185
Directory	/workspace/34.edn_disable/latest

Test location	/workspace/coverage/default/16.edn_disable_auto_req_mode.1854981993
Short name	T247
Test name
Test status
Simulation time	25100665 ps
CPU time	1.06 seconds
Started	Jan 10 01:19:18 PM PST 24
Finished	Jan 10 01:19:22 PM PST 24
Peak memory	214608 kb
Host	smart-0c113320-1d0a-4560-9839-7f2d6e93acef
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854981993 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d isable_auto_req_mode.1854981993
Directory	/workspace/16.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/cover_reg_top/14.edn_intr_test.1579510141
Short name	T358
Test name
Test status
Simulation time	14030639 ps
CPU time	0.83 seconds
Started	Jan 10 12:58:07 PM PST 24
Finished	Jan 10 12:59:28 PM PST 24
Peak memory	205928 kb
Host	smart-25eb2cc9-66eb-46ec-85dd-c1f3b475e0a7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579510141 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.1579510141
Directory	/workspace/14.edn_intr_test/latest

Test location	/workspace/coverage/default/6.edn_genbits.171123847
Short name	T265
Test name
Test status
Simulation time	17836376 ps
CPU time	1.03 seconds
Started	Jan 10 01:18:26 PM PST 24
Finished	Jan 10 01:18:35 PM PST 24
Peak memory	205388 kb
Host	smart-d47ebc8f-f5e1-4ee4-95ef-f72588567d79
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=171123847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.171123847
Directory	/workspace/6.edn_genbits/latest

Test location	/workspace/coverage/default/103.edn_genbits.4278454923
Short name	T75
Test name
Test status
Simulation time	23257009 ps
CPU time	1.07 seconds
Started	Jan 10 01:20:52 PM PST 24
Finished	Jan 10 01:20:58 PM PST 24
Peak memory	205412 kb
Host	smart-cbbb4e53-c579-419d-9a8d-57ff00b7b0eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4278454923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.4278454923
Directory	/workspace/103.edn_genbits/latest

Test location	/workspace/coverage/default/263.edn_genbits.870831683
Short name	T301
Test name
Test status
Simulation time	24026212 ps
CPU time	1.26 seconds
Started	Jan 10 01:21:39 PM PST 24
Finished	Jan 10 01:21:58 PM PST 24
Peak memory	214280 kb
Host	smart-64d3a672-775e-4c2d-8f27-c293a205df44
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=870831683 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.870831683
Directory	/workspace/263.edn_genbits/latest

Test location	/workspace/coverage/default/7.edn_genbits.4118854736
Short name	T66
Test name
Test status
Simulation time	29253818 ps
CPU time	1.01 seconds
Started	Jan 10 01:19:10 PM PST 24
Finished	Jan 10 01:19:15 PM PST 24
Peak memory	205732 kb
Host	smart-1fb3a6bb-7d49-422a-8966-0a19cf0b8047
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4118854736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.4118854736
Directory	/workspace/7.edn_genbits/latest

Test location	/workspace/coverage/default/37.edn_disable.4072114606
Short name	T21
Test name
Test status
Simulation time	41877346 ps
CPU time	0.86 seconds
Started	Jan 10 01:20:15 PM PST 24
Finished	Jan 10 01:20:19 PM PST 24
Peak memory	214504 kb
Host	smart-b4c4e4a5-eccf-447d-9a8f-06f4e0c363a7
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072114606 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.4072114606
Directory	/workspace/37.edn_disable/latest

Test location	/workspace/coverage/default/15.edn_intr.2264796760
Short name	T912
Test name
Test status
Simulation time	52860066 ps
CPU time	0.76 seconds
Started	Jan 10 01:19:26 PM PST 24
Finished	Jan 10 01:19:38 PM PST 24
Peak memory	214508 kb
Host	smart-9d630c21-2361-4626-a91f-171de32dd3cd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2264796760 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.2264796760
Directory	/workspace/15.edn_intr/latest

Test location	/workspace/coverage/default/3.edn_sec_cm.2963811711
Short name	T15
Test name
Test status
Simulation time	354180934 ps
CPU time	5.72 seconds
Started	Jan 10 01:18:29 PM PST 24
Finished	Jan 10 01:18:43 PM PST 24
Peak memory	234864 kb
Host	smart-2b963302-56e1-4b58-b189-9df961b942f2
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963811711 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.2963811711
Directory	/workspace/3.edn_sec_cm/latest

Test location	/workspace/coverage/default/38.edn_alert.140690776
Short name	T317
Test name
Test status
Simulation time	176222510 ps
CPU time	0.95 seconds
Started	Jan 10 01:20:02 PM PST 24
Finished	Jan 10 01:20:10 PM PST 24
Peak memory	205296 kb
Host	smart-8fdc5dd2-59eb-4ae4-9e71-4cbaa10f2601
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=140690776 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.140690776
Directory	/workspace/38.edn_alert/latest

Test location	/workspace/coverage/default/0.edn_disable.1308945160
Short name	T170
Test name
Test status
Simulation time	28182222 ps
CPU time	0.78 seconds
Started	Jan 10 01:18:15 PM PST 24
Finished	Jan 10 01:18:23 PM PST 24
Peak memory	214592 kb
Host	smart-4bb2a9c1-5296-4cb3-8392-22fc08ce43f4
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308945160 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.1308945160
Directory	/workspace/0.edn_disable/latest

Test location	/workspace/coverage/default/1.edn_disable.3117944563
Short name	T174
Test name
Test status
Simulation time	38384380 ps
CPU time	0.84 seconds
Started	Jan 10 01:18:38 PM PST 24
Finished	Jan 10 01:18:46 PM PST 24
Peak memory	214396 kb
Host	smart-d5d50dcc-5228-4147-b561-03f1d3db604c
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117944563 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.3117944563
Directory	/workspace/1.edn_disable/latest

Test location	/workspace/coverage/default/12.edn_disable_auto_req_mode.3492134715
Short name	T148
Test name
Test status
Simulation time	22843595 ps
CPU time	0.99 seconds
Started	Jan 10 01:19:22 PM PST 24
Finished	Jan 10 01:19:31 PM PST 24
Peak memory	214628 kb
Host	smart-bb4edafe-feda-43e4-9141-2aaff12402e9
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492134715 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d isable_auto_req_mode.3492134715
Directory	/workspace/12.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/14.edn_disable_auto_req_mode.3188071840
Short name	T711
Test name
Test status
Simulation time	55646274 ps
CPU time	1.07 seconds
Started	Jan 10 01:19:23 PM PST 24
Finished	Jan 10 01:19:33 PM PST 24
Peak memory	214916 kb
Host	smart-1f67a677-73ff-46e2-a3a5-cfdaed03b20a
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188071840 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d isable_auto_req_mode.3188071840
Directory	/workspace/14.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/2.edn_disable_auto_req_mode.913186405
Short name	T142
Test name
Test status
Simulation time	25268603 ps
CPU time	1 seconds
Started	Jan 10 01:18:34 PM PST 24
Finished	Jan 10 01:18:42 PM PST 24
Peak memory	214640 kb
Host	smart-4b4a71cd-125d-4773-a982-fce14d7f33dd
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913186405 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_dis able_auto_req_mode.913186405
Directory	/workspace/2.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/27.edn_disable_auto_req_mode.3618094869
Short name	T680
Test name
Test status
Simulation time	39991588 ps
CPU time	0.93 seconds
Started	Jan 10 01:19:38 PM PST 24
Finished	Jan 10 01:19:53 PM PST 24
Peak memory	214668 kb
Host	smart-29cc4f7b-c4fe-4a4c-b029-9362ba32bfe9
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618094869 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d isable_auto_req_mode.3618094869
Directory	/workspace/27.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/12.edn_stress_all_with_rand_reset.1193472038
Short name	T268
Test name
Test status
Simulation time	133192300639 ps
CPU time	1661.52 seconds
Started	Jan 10 01:19:10 PM PST 24
Finished	Jan 10 01:46:55 PM PST 24
Peak memory	221408 kb
Host	smart-e5b9a18e-06e2-45fd-866c-5ba8d6e4fe08
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193472038 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.1193472038
Directory	/workspace/12.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/12.edn_alert.1459641575
Short name	T253
Test name
Test status
Simulation time	20939404 ps
CPU time	0.97 seconds
Started	Jan 10 01:19:10 PM PST 24
Finished	Jan 10 01:19:15 PM PST 24
Peak memory	205248 kb
Host	smart-38196c04-39b2-4574-b128-5e06fdf38171
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1459641575 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.1459641575
Directory	/workspace/12.edn_alert/latest

Test location	/workspace/coverage/default/26.edn_alert.1728546261
Short name	T753
Test name
Test status
Simulation time	56324751 ps
CPU time	0.87 seconds
Started	Jan 10 01:19:38 PM PST 24
Finished	Jan 10 01:19:52 PM PST 24
Peak memory	205292 kb
Host	smart-67ae36ea-67de-44a0-837b-26cd4098f5a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1728546261 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.1728546261
Directory	/workspace/26.edn_alert/latest

Test location	/workspace/coverage/default/42.edn_genbits.2803513457
Short name	T292
Test name
Test status
Simulation time	82443746 ps
CPU time	1.15 seconds
Started	Jan 10 01:20:13 PM PST 24
Finished	Jan 10 01:20:17 PM PST 24
Peak memory	214268 kb
Host	smart-f0b933de-d32c-47ea-bcf6-a318478821b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2803513457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.2803513457
Directory	/workspace/42.edn_genbits/latest

Test location	/workspace/coverage/default/128.edn_genbits.3171177927
Short name	T277
Test name
Test status
Simulation time	62560673 ps
CPU time	1.17 seconds
Started	Jan 10 01:20:33 PM PST 24
Finished	Jan 10 01:20:44 PM PST 24
Peak memory	214256 kb
Host	smart-df90fba9-6470-45a9-901d-db6180cd6dc1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3171177927 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.3171177927
Directory	/workspace/128.edn_genbits/latest

Test location	/workspace/coverage/default/3.edn_regwen.3924975935
Short name	T69
Test name
Test status
Simulation time	62022486 ps
CPU time	0.88 seconds
Started	Jan 10 01:18:39 PM PST 24
Finished	Jan 10 01:18:47 PM PST 24
Peak memory	205020 kb
Host	smart-8f9c3f76-b97c-4143-a736-41ba67cc3690
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3924975935 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.3924975935
Directory	/workspace/3.edn_regwen/latest

Test location	/workspace/coverage/default/39.edn_genbits.4192246072
Short name	T309
Test name
Test status
Simulation time	27548776 ps
CPU time	0.91 seconds
Started	Jan 10 01:20:13 PM PST 24
Finished	Jan 10 01:20:16 PM PST 24
Peak memory	205168 kb
Host	smart-07b7747e-9c79-4374-906c-fa8ea351b9cd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4192246072 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.4192246072
Directory	/workspace/39.edn_genbits/latest

Test location	/workspace/coverage/default/58.edn_genbits.3810313949
Short name	T281
Test name
Test status
Simulation time	20585248 ps
CPU time	0.94 seconds
Started	Jan 10 01:20:22 PM PST 24
Finished	Jan 10 01:20:33 PM PST 24
Peak memory	205244 kb
Host	smart-52dbb079-5724-49bc-ad15-c3d891dcbda4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3810313949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.3810313949
Directory	/workspace/58.edn_genbits/latest

Test location	/workspace/coverage/default/54.edn_genbits.2109428230
Short name	T11
Test name
Test status
Simulation time	30959095 ps
CPU time	1.17 seconds
Started	Jan 10 01:21:03 PM PST 24
Finished	Jan 10 01:21:08 PM PST 24
Peak memory	214332 kb
Host	smart-28716cb3-11cf-47c2-a0d0-69451d284a8d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2109428230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.2109428230
Directory	/workspace/54.edn_genbits/latest

Test location	/workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2801013271
Short name	T183
Test name
Test status
Simulation time	214923825 ps
CPU time	1.35 seconds
Started	Jan 10 12:58:06 PM PST 24
Finished	Jan 10 12:59:28 PM PST 24
Peak memory	206056 kb
Host	smart-87ac3667-b7b5-4986-aae3-9080336305db
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801013271 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o utstanding.2801013271
Directory	/workspace/11.edn_same_csr_outstanding/latest

Test location	/workspace/coverage/default/168.edn_genbits.3576228187
Short name	T306
Test name
Test status
Simulation time	18512235 ps
CPU time	0.98 seconds
Started	Jan 10 01:21:31 PM PST 24
Finished	Jan 10 01:21:50 PM PST 24
Peak memory	205636 kb
Host	smart-18881242-a3bd-4096-84af-b35cc0ea03f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3576228187 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.3576228187
Directory	/workspace/168.edn_genbits/latest

Test location	/workspace/coverage/default/2.edn_regwen.3462575093
Short name	T308
Test name
Test status
Simulation time	46576434 ps
CPU time	0.81 seconds
Started	Jan 10 01:18:36 PM PST 24
Finished	Jan 10 01:18:44 PM PST 24
Peak memory	204676 kb
Host	smart-55302c97-6f7b-410b-9219-98925c103fa8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3462575093 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.3462575093
Directory	/workspace/2.edn_regwen/latest

Test location	/workspace/coverage/default/24.edn_stress_all_with_rand_reset.906707046
Short name	T537
Test name
Test status
Simulation time	61306392275 ps
CPU time	676.07 seconds
Started	Jan 10 01:19:30 PM PST 24
Finished	Jan 10 01:31:02 PM PST 24
Peak memory	215244 kb
Host	smart-492502df-e463-4fb0-a6a4-55f5e01af97e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906707046 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.906707046
Directory	/workspace/24.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/7.edn_regwen.1708362542
Short name	T256
Test name
Test status
Simulation time	45538566 ps
CPU time	0.78 seconds
Started	Jan 10 01:19:15 PM PST 24
Finished	Jan 10 01:19:18 PM PST 24
Peak memory	205000 kb
Host	smart-4ede0cce-4ebe-44b6-95dd-decc5cb88879
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1708362542 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.1708362542
Directory	/workspace/7.edn_regwen/latest

Test location	/workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.4018061468
Short name	T203
Test name
Test status
Simulation time	72630321 ps
CPU time	1.67 seconds
Started	Jan 10 12:57:59 PM PST 24
Finished	Jan 10 12:59:20 PM PST 24
Peak memory	222552 kb
Host	smart-24ea65f2-5911-4055-a55c-5e2ec0b606fb
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018061468 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.4018061468
Directory	/workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/default/0.edn_alert_test.3875458640
Short name	T78
Test name
Test status
Simulation time	25264485 ps
CPU time	0.95 seconds
Started	Jan 10 01:18:21 PM PST 24
Finished	Jan 10 01:18:29 PM PST 24
Peak memory	205252 kb
Host	smart-39fc437f-c0f0-43d2-87ad-402a0aafe6aa
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875458640 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.3875458640
Directory	/workspace/0.edn_alert_test/latest

Test location	/workspace/coverage/default/12.edn_intr.1814252757
Short name	T765
Test name
Test status
Simulation time	20780407 ps
CPU time	1.16 seconds
Started	Jan 10 01:19:20 PM PST 24
Finished	Jan 10 01:19:24 PM PST 24
Peak memory	225688 kb
Host	smart-3011ca31-4457-484d-a9e0-52ef0ae7f294
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1814252757 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.1814252757
Directory	/workspace/12.edn_intr/latest

Test location	/workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1336752710
Short name	T260
Test name
Test status
Simulation time	275726268 ps
CPU time	2.06 seconds
Started	Jan 10 12:59:45 PM PST 24
Finished	Jan 10 01:01:21 PM PST 24
Peak memory	204428 kb
Host	smart-bebd43b0-40ba-428d-8f5b-0d2282bde399
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336752710 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.1336752710
Directory	/workspace/5.edn_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.edn_intr_test.4002248237
Short name	T366
Test name
Test status
Simulation time	122262814 ps
CPU time	0.74 seconds
Started	Jan 10 12:58:11 PM PST 24
Finished	Jan 10 12:59:34 PM PST 24
Peak memory	205420 kb
Host	smart-84971305-db5d-4d45-8260-23bc043f006e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002248237 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.4002248237
Directory	/workspace/12.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2008528185
Short name	T262
Test name
Test status
Simulation time	84836683 ps
CPU time	2.19 seconds
Started	Jan 10 01:00:43 PM PST 24
Finished	Jan 10 01:01:56 PM PST 24
Peak memory	205604 kb
Host	smart-a2abf538-1a9e-4bd9-8f2d-76c9ecbcbad3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008528185 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.2008528185
Directory	/workspace/18.edn_tl_intg_err/latest

Test location	/workspace/coverage/default/10.edn_genbits.697556066
Short name	T760
Test name
Test status
Simulation time	16456728 ps
CPU time	1.08 seconds
Started	Jan 10 01:19:25 PM PST 24
Finished	Jan 10 01:19:37 PM PST 24
Peak memory	205840 kb
Host	smart-8216cfc5-8c10-4166-83d3-f948ae7a6da2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=697556066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.697556066
Directory	/workspace/10.edn_genbits/latest

Test location	/workspace/coverage/default/100.edn_genbits.2979463569
Short name	T337
Test name
Test status
Simulation time	27121008 ps
CPU time	0.98 seconds
Started	Jan 10 01:20:33 PM PST 24
Finished	Jan 10 01:20:42 PM PST 24
Peak memory	205532 kb
Host	smart-00c9472d-8c9c-432d-b7da-da1bbc743a7f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2979463569 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.2979463569
Directory	/workspace/100.edn_genbits/latest

Test location	/workspace/coverage/default/102.edn_genbits.4238303621
Short name	T962
Test name
Test status
Simulation time	18535666 ps
CPU time	1.02 seconds
Started	Jan 10 01:20:53 PM PST 24
Finished	Jan 10 01:20:59 PM PST 24
Peak memory	214308 kb
Host	smart-ce032572-7181-44da-a9c5-b103e3c0c3b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4238303621 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.4238303621
Directory	/workspace/102.edn_genbits/latest

Test location	/workspace/coverage/default/112.edn_genbits.2114575156
Short name	T340
Test name
Test status
Simulation time	103367230 ps
CPU time	1.02 seconds
Started	Jan 10 01:20:33 PM PST 24
Finished	Jan 10 01:20:43 PM PST 24
Peak memory	205744 kb
Host	smart-058bc1be-596c-4b06-b28a-c7d82df1ef64
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2114575156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.2114575156
Directory	/workspace/112.edn_genbits/latest

Test location	/workspace/coverage/default/12.edn_genbits.2479122030
Short name	T937
Test name
Test status
Simulation time	52710931 ps
CPU time	1.31 seconds
Started	Jan 10 01:19:09 PM PST 24
Finished	Jan 10 01:19:13 PM PST 24
Peak memory	214256 kb
Host	smart-4c728aa6-5221-4bd4-bf2e-851e87dbe3b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2479122030 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.2479122030
Directory	/workspace/12.edn_genbits/latest

Test location	/workspace/coverage/default/129.edn_genbits.4183256767
Short name	T117
Test name
Test status
Simulation time	115884464 ps
CPU time	2.6 seconds
Started	Jan 10 01:20:52 PM PST 24
Finished	Jan 10 01:21:00 PM PST 24
Peak memory	214348 kb
Host	smart-129a1daa-9873-45da-a8e8-43ccf2c78a7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4183256767 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.4183256767
Directory	/workspace/129.edn_genbits/latest

Test location	/workspace/coverage/default/139.edn_genbits.1563275632
Short name	T598
Test name
Test status
Simulation time	18554706 ps
CPU time	0.99 seconds
Started	Jan 10 01:20:50 PM PST 24
Finished	Jan 10 01:20:57 PM PST 24
Peak memory	205356 kb
Host	smart-9e4df01a-6b30-4e02-92a0-a2ddb7d021c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1563275632 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.1563275632
Directory	/workspace/139.edn_genbits/latest

Test location	/workspace/coverage/default/146.edn_genbits.3402735334
Short name	T857
Test name
Test status
Simulation time	59439309 ps
CPU time	1.02 seconds
Started	Jan 10 01:20:35 PM PST 24
Finished	Jan 10 01:20:45 PM PST 24
Peak memory	214316 kb
Host	smart-1cc8695a-d7de-4ca8-b878-7ffaf7372567
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3402735334 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.3402735334
Directory	/workspace/146.edn_genbits/latest

Test location	/workspace/coverage/default/16.edn_err.316333964
Short name	T91
Test name
Test status
Simulation time	53773499 ps
CPU time	1.28 seconds
Started	Jan 10 01:19:24 PM PST 24
Finished	Jan 10 01:19:35 PM PST 24
Peak memory	214948 kb
Host	smart-18210493-bf55-4a5a-8a07-7cc89e73eba3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=316333964 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.316333964
Directory	/workspace/16.edn_err/latest

Test location	/workspace/coverage/default/18.edn_alert.1650262586
Short name	T321
Test name
Test status
Simulation time	205234564 ps
CPU time	0.96 seconds
Started	Jan 10 01:19:22 PM PST 24
Finished	Jan 10 01:19:30 PM PST 24
Peak memory	206160 kb
Host	smart-71824564-6622-4cbe-b157-0d30a36b5fc0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1650262586 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.1650262586
Directory	/workspace/18.edn_alert/latest

Test location	/workspace/coverage/default/215.edn_genbits.3091759592
Short name	T275
Test name
Test status
Simulation time	32909975 ps
CPU time	1.05 seconds
Started	Jan 10 01:21:01 PM PST 24
Finished	Jan 10 01:21:06 PM PST 24
Peak memory	205628 kb
Host	smart-9220756a-1272-4b25-bc64-e8b649b2ff28
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3091759592 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.3091759592
Directory	/workspace/215.edn_genbits/latest

Test location	/workspace/coverage/default/241.edn_genbits.3702099759
Short name	T344
Test name
Test status
Simulation time	15367269 ps
CPU time	0.95 seconds
Started	Jan 10 01:21:04 PM PST 24
Finished	Jan 10 01:21:08 PM PST 24
Peak memory	205156 kb
Host	smart-e6ded913-47f0-453b-a352-c7aa6702b799
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3702099759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.3702099759
Directory	/workspace/241.edn_genbits/latest

Test location	/workspace/coverage/default/95.edn_genbits.438649846
Short name	T291
Test name
Test status
Simulation time	74965106 ps
CPU time	1.07 seconds
Started	Jan 10 01:21:04 PM PST 24
Finished	Jan 10 01:21:09 PM PST 24
Peak memory	205360 kb
Host	smart-3409bf83-bee9-4533-a0f5-5ca7a77cc3de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=438649846 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.438649846
Directory	/workspace/95.edn_genbits/latest

Test location	/workspace/coverage/default/20.edn_intr.1355696734
Short name	T95
Test name
Test status
Simulation time	23753419 ps
CPU time	0.9 seconds
Started	Jan 10 01:19:27 PM PST 24
Finished	Jan 10 01:19:40 PM PST 24
Peak memory	214664 kb
Host	smart-c5e93eb7-8e76-4fd7-872c-a7a74bdd73e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1355696734 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.1355696734
Directory	/workspace/20.edn_intr/latest

Test location	/workspace/coverage/default/10.edn_disable_auto_req_mode.4093760588
Short name	T127
Test name
Test status
Simulation time	48048601 ps
CPU time	0.93 seconds
Started	Jan 10 01:19:25 PM PST 24
Finished	Jan 10 01:19:37 PM PST 24
Peak memory	206528 kb
Host	smart-0a636f63-4a90-4687-8434-cdfe962e1471
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093760588 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d isable_auto_req_mode.4093760588
Directory	/workspace/10.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/12.edn_disable.2346554343
Short name	T809
Test name
Test status
Simulation time	20800692 ps
CPU time	0.84 seconds
Started	Jan 10 01:19:18 PM PST 24
Finished	Jan 10 01:19:22 PM PST 24
Peak memory	214528 kb
Host	smart-9cbb7f01-acf0-44f4-87ca-bea498245b36
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346554343 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.2346554343
Directory	/workspace/12.edn_disable/latest

Test location	/workspace/coverage/default/13.edn_disable_auto_req_mode.1392726896
Short name	T111
Test name
Test status
Simulation time	61909360 ps
CPU time	1.04 seconds
Started	Jan 10 01:19:24 PM PST 24
Finished	Jan 10 01:19:36 PM PST 24
Peak memory	214752 kb
Host	smart-0a78ee28-452e-4d3e-911b-10a550480ab5
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392726896 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d isable_auto_req_mode.1392726896
Directory	/workspace/13.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/17.edn_disable.3539948797
Short name	T82
Test name
Test status
Simulation time	38204769 ps
CPU time	0.81 seconds
Started	Jan 10 01:19:23 PM PST 24
Finished	Jan 10 01:19:32 PM PST 24
Peak memory	214484 kb
Host	smart-cb848560-31f4-47a5-a033-34e93cd402b5
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539948797 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.3539948797
Directory	/workspace/17.edn_disable/latest

Test location	/workspace/coverage/default/22.edn_disable_auto_req_mode.2451166260
Short name	T786
Test name
Test status
Simulation time	41496234 ps
CPU time	1.01 seconds
Started	Jan 10 01:19:33 PM PST 24
Finished	Jan 10 01:19:50 PM PST 24
Peak memory	206444 kb
Host	smart-96b5776e-a037-4feb-bf4b-97747511e7ad
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451166260 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d isable_auto_req_mode.2451166260
Directory	/workspace/22.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1616386571
Short name	T212
Test name
Test status
Simulation time	188764584 ps
CPU time	1.54 seconds
Started	Jan 10 12:57:48 PM PST 24
Finished	Jan 10 12:59:08 PM PST 24
Peak memory	205992 kb
Host	smart-48b72863-67a2-4f8c-9c1e-cb233d85fdc3
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616386571 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.1616386571
Directory	/workspace/0.edn_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1297246364
Short name	T378
Test name
Test status
Simulation time	394753529 ps
CPU time	2.97 seconds
Started	Jan 10 12:57:41 PM PST 24
Finished	Jan 10 12:59:02 PM PST 24
Peak memory	205988 kb
Host	smart-d4e31201-ac42-415e-8816-6e8522424cac
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297246364 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.1297246364
Directory	/workspace/0.edn_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3782038542
Short name	T221
Test name
Test status
Simulation time	87842341 ps
CPU time	0.85 seconds
Started	Jan 10 12:57:56 PM PST 24
Finished	Jan 10 12:59:16 PM PST 24
Peak memory	206012 kb
Host	smart-4079bd7b-47fb-444b-aea6-a2313e8541ec
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782038542 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.3782038542
Directory	/workspace/0.edn_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2051451504
Short name	T401
Test name
Test status
Simulation time	397490347 ps
CPU time	2.06 seconds
Started	Jan 10 12:58:04 PM PST 24
Finished	Jan 10 12:59:26 PM PST 24
Peak memory	214312 kb
Host	smart-1443dbbb-ccd7-4b13-a2f8-a5206171e5f0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051451504 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.2051451504
Directory	/workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.edn_csr_rw.3379514533
Short name	T391
Test name
Test status
Simulation time	18804735 ps
CPU time	0.82 seconds
Started	Jan 10 12:59:46 PM PST 24
Finished	Jan 10 01:01:24 PM PST 24
Peak memory	205452 kb
Host	smart-b9dbf0f3-c6b6-408b-a90c-972d9ca73c42
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379514533 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.3379514533
Directory	/workspace/0.edn_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.edn_intr_test.3885811300
Short name	T384
Test name
Test status
Simulation time	46983752 ps
CPU time	0.79 seconds
Started	Jan 10 12:57:44 PM PST 24
Finished	Jan 10 12:59:04 PM PST 24
Peak memory	205656 kb
Host	smart-f0da4f66-4d30-4335-bbaf-c43e335c2ee2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885811300 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.3885811300
Directory	/workspace/0.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3818336962
Short name	T359
Test name
Test status
Simulation time	149890181 ps
CPU time	1.19 seconds
Started	Jan 10 12:57:45 PM PST 24
Finished	Jan 10 12:59:05 PM PST 24
Peak memory	205872 kb
Host	smart-c7bcc69a-385f-4a0b-a6d7-d5e4c1942830
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818336962 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou tstanding.3818336962
Directory	/workspace/0.edn_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2083964239
Short name	T184
Test name
Test status
Simulation time	78135910 ps
CPU time	2.19 seconds
Started	Jan 10 12:57:47 PM PST 24
Finished	Jan 10 12:59:11 PM PST 24
Peak memory	205996 kb
Host	smart-6e2bd8a8-d33c-4de1-81e7-49c1cfc77b8a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083964239 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.2083964239
Directory	/workspace/0.edn_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3944171437
Short name	T424
Test name
Test status
Simulation time	113955960 ps
CPU time	3.16 seconds
Started	Jan 10 12:57:48 PM PST 24
Finished	Jan 10 12:59:10 PM PST 24
Peak memory	205992 kb
Host	smart-abf824ad-f81e-4cd9-8cd2-26c8441629bb
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944171437 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.3944171437
Directory	/workspace/1.edn_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3584701677
Short name	T364
Test name
Test status
Simulation time	51361168 ps
CPU time	0.87 seconds
Started	Jan 10 12:57:48 PM PST 24
Finished	Jan 10 12:59:07 PM PST 24
Peak memory	205884 kb
Host	smart-3d035737-e7c6-4913-9d6d-b3606220a1cd
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584701677 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.3584701677
Directory	/workspace/1.edn_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3950681984
Short name	T202
Test name
Test status
Simulation time	57221210 ps
CPU time	1.31 seconds
Started	Jan 10 01:00:02 PM PST 24
Finished	Jan 10 01:01:31 PM PST 24
Peak memory	213844 kb
Host	smart-c9aed85f-3cbf-4aec-9dcd-9270a981fc49
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950681984 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.3950681984
Directory	/workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.edn_csr_rw.3571114912
Short name	T216
Test name
Test status
Simulation time	13433262 ps
CPU time	0.89 seconds
Started	Jan 10 12:57:45 PM PST 24
Finished	Jan 10 12:59:04 PM PST 24
Peak memory	205992 kb
Host	smart-bfdd3b58-40b7-46c2-a517-1d13c3d649b9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571114912 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.3571114912
Directory	/workspace/1.edn_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.edn_intr_test.3480349804
Short name	T400
Test name
Test status
Simulation time	22335157 ps
CPU time	0.81 seconds
Started	Jan 10 12:57:47 PM PST 24
Finished	Jan 10 12:59:10 PM PST 24
Peak memory	205944 kb
Host	smart-ff539c7f-cdd9-49f3-9c6c-81f294cc2b12
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480349804 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3480349804
Directory	/workspace/1.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1970600262
Short name	T195
Test name
Test status
Simulation time	27432750 ps
CPU time	1.09 seconds
Started	Jan 10 12:57:51 PM PST 24
Finished	Jan 10 12:59:11 PM PST 24
Peak memory	205884 kb
Host	smart-7ef96ef6-0c78-4c7e-b171-4ba1c0d47ab6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970600262 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou tstanding.1970600262
Directory	/workspace/1.edn_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.edn_tl_errors.3730702235
Short name	T188
Test name
Test status
Simulation time	83320474 ps
CPU time	2.62 seconds
Started	Jan 10 12:57:46 PM PST 24
Finished	Jan 10 12:59:07 PM PST 24
Peak memory	214288 kb
Host	smart-d589d9c4-38ff-4e26-ad42-f5eb732f3bb2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730702235 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.3730702235
Directory	/workspace/1.edn_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.edn_tl_intg_err.342480707
Short name	T187
Test name
Test status
Simulation time	47610157 ps
CPU time	1.56 seconds
Started	Jan 10 12:57:46 PM PST 24
Finished	Jan 10 12:59:06 PM PST 24
Peak memory	205972 kb
Host	smart-41977898-b570-4edd-ae34-89d3d8bc74f3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342480707 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.342480707
Directory	/workspace/1.edn_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1566436839
Short name	T430
Test name
Test status
Simulation time	31377325 ps
CPU time	1.16 seconds
Started	Jan 10 12:58:02 PM PST 24
Finished	Jan 10 12:59:23 PM PST 24
Peak memory	214324 kb
Host	smart-9a2f6b48-50b5-4f9c-afaf-db60b4076751
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566436839 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.1566436839
Directory	/workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.edn_csr_rw.1204524254
Short name	T415
Test name
Test status
Simulation time	24320283 ps
CPU time	0.8 seconds
Started	Jan 10 01:00:21 PM PST 24
Finished	Jan 10 01:01:50 PM PST 24
Peak memory	205412 kb
Host	smart-59516d9a-aece-42c9-a5f8-7c37d82d78fd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204524254 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.1204524254
Directory	/workspace/10.edn_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.edn_intr_test.445460495
Short name	T389
Test name
Test status
Simulation time	38458379 ps
CPU time	0.82 seconds
Started	Jan 10 12:58:03 PM PST 24
Finished	Jan 10 12:59:24 PM PST 24
Peak memory	206000 kb
Host	smart-1b00c371-2889-45f9-bb4a-1304bb6544be
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445460495 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.445460495
Directory	/workspace/10.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1940739320
Short name	T190
Test name
Test status
Simulation time	63132353 ps
CPU time	0.99 seconds
Started	Jan 10 12:58:01 PM PST 24
Finished	Jan 10 12:59:22 PM PST 24
Peak memory	206076 kb
Host	smart-65b89901-0a84-4015-a20a-92592ab9e686
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940739320 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o utstanding.1940739320
Directory	/workspace/10.edn_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.edn_tl_errors.3499644325
Short name	T388
Test name
Test status
Simulation time	280848022 ps
CPU time	2.57 seconds
Started	Jan 10 12:58:07 PM PST 24
Finished	Jan 10 12:59:30 PM PST 24
Peak memory	214344 kb
Host	smart-28f88021-d5e7-4264-bd09-6d13b89448b1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499644325 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.3499644325
Directory	/workspace/10.edn_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3311690142
Short name	T409
Test name
Test status
Simulation time	87661423 ps
CPU time	2.37 seconds
Started	Jan 10 12:58:01 PM PST 24
Finished	Jan 10 12:59:24 PM PST 24
Peak memory	206012 kb
Host	smart-ba965cf1-1bd5-46c4-a88c-88da2075cfc6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311690142 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.3311690142
Directory	/workspace/10.edn_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.594685420
Short name	T197
Test name
Test status
Simulation time	53811906 ps
CPU time	1.26 seconds
Started	Jan 10 12:58:06 PM PST 24
Finished	Jan 10 12:59:28 PM PST 24
Peak memory	214120 kb
Host	smart-58942829-f792-4b43-bcf6-80cb20105f2d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594685420 -assert nopostproc +UVM_TESTNAME= edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.594685420
Directory	/workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.edn_csr_rw.1131637558
Short name	T210
Test name
Test status
Simulation time	22897551 ps
CPU time	0.84 seconds
Started	Jan 10 12:58:06 PM PST 24
Finished	Jan 10 12:59:27 PM PST 24
Peak memory	206008 kb
Host	smart-fd441192-f950-4290-b01c-63e04c44ca72
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131637558 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.1131637558
Directory	/workspace/11.edn_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.edn_intr_test.1753715639
Short name	T355
Test name
Test status
Simulation time	12719694 ps
CPU time	0.85 seconds
Started	Jan 10 12:58:01 PM PST 24
Finished	Jan 10 12:59:22 PM PST 24
Peak memory	205952 kb
Host	smart-b07f6b87-2f2e-496a-a618-5d55b24b1aee
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753715639 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.1753715639
Directory	/workspace/11.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.edn_tl_errors.2978847719
Short name	T426
Test name
Test status
Simulation time	100223265 ps
CPU time	2.32 seconds
Started	Jan 10 12:58:10 PM PST 24
Finished	Jan 10 12:59:32 PM PST 24
Peak memory	214260 kb
Host	smart-68da4185-f3e9-412a-8165-337a31c2695b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978847719 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.2978847719
Directory	/workspace/11.edn_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2600239198
Short name	T258
Test name
Test status
Simulation time	127445520 ps
CPU time	2.77 seconds
Started	Jan 10 12:58:04 PM PST 24
Finished	Jan 10 12:59:28 PM PST 24
Peak memory	205900 kb
Host	smart-9177a35f-13ac-448f-a670-4878a3bec2df
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600239198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.2600239198
Directory	/workspace/11.edn_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3231309042
Short name	T405
Test name
Test status
Simulation time	50700610 ps
CPU time	1.23 seconds
Started	Jan 10 12:58:08 PM PST 24
Finished	Jan 10 12:59:29 PM PST 24
Peak memory	214260 kb
Host	smart-c4082855-af8d-473c-9126-99ebe5f94b80
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231309042 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.3231309042
Directory	/workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.edn_csr_rw.3083739919
Short name	T214
Test name
Test status
Simulation time	12120929 ps
CPU time	0.83 seconds
Started	Jan 10 12:58:15 PM PST 24
Finished	Jan 10 12:59:37 PM PST 24
Peak memory	205892 kb
Host	smart-3a079e7f-ed87-4658-a188-127098c56ffe
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083739919 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.3083739919
Directory	/workspace/12.edn_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1446841443
Short name	T395
Test name
Test status
Simulation time	21192297 ps
CPU time	0.95 seconds
Started	Jan 10 12:58:05 PM PST 24
Finished	Jan 10 12:59:26 PM PST 24
Peak memory	206032 kb
Host	smart-cf7cc41c-79bb-40d4-a83a-6e55e8273a51
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446841443 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o utstanding.1446841443
Directory	/workspace/12.edn_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.edn_tl_errors.2663328697
Short name	T436
Test name
Test status
Simulation time	441283981 ps
CPU time	2.69 seconds
Started	Jan 10 12:58:07 PM PST 24
Finished	Jan 10 12:59:30 PM PST 24
Peak memory	214324 kb
Host	smart-b84c5a40-d341-4264-96b9-f6ce7c3a5ec0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663328697 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.2663328697
Directory	/workspace/12.edn_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2674439366
Short name	T373
Test name
Test status
Simulation time	110877432 ps
CPU time	2.39 seconds
Started	Jan 10 12:58:08 PM PST 24
Finished	Jan 10 12:59:31 PM PST 24
Peak memory	206084 kb
Host	smart-b0711029-6170-4ade-b5aa-2f8887b4974f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674439366 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.2674439366
Directory	/workspace/12.edn_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.4204306628
Short name	T200
Test name
Test status
Simulation time	27820517 ps
CPU time	1.27 seconds
Started	Jan 10 12:58:05 PM PST 24
Finished	Jan 10 12:59:27 PM PST 24
Peak memory	214336 kb
Host	smart-d0b51ae9-3268-437b-b5da-4af9a9050d6d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204306628 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.4204306628
Directory	/workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.edn_csr_rw.1098770273
Short name	T218
Test name
Test status
Simulation time	20110528 ps
CPU time	0.87 seconds
Started	Jan 10 12:58:09 PM PST 24
Finished	Jan 10 12:59:30 PM PST 24
Peak memory	205896 kb
Host	smart-a50fb6db-7a90-46b8-b367-e8e4820a65bc
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098770273 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.1098770273
Directory	/workspace/13.edn_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.edn_intr_test.923704737
Short name	T446
Test name
Test status
Simulation time	27723685 ps
CPU time	0.85 seconds
Started	Jan 10 12:58:07 PM PST 24
Finished	Jan 10 12:59:28 PM PST 24
Peak memory	205900 kb
Host	smart-9ea3cd91-1711-4e8a-84ed-b111e082590e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923704737 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.923704737
Directory	/workspace/13.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.864732497
Short name	T225
Test name
Test status
Simulation time	119437861 ps
CPU time	0.92 seconds
Started	Jan 10 12:58:13 PM PST 24
Finished	Jan 10 12:59:33 PM PST 24
Peak memory	205884 kb
Host	smart-1ed5d865-6d2c-405c-a32c-f9dab35261e3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864732497 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_ou tstanding.864732497
Directory	/workspace/13.edn_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.edn_tl_errors.1599621860
Short name	T257
Test name
Test status
Simulation time	74935200 ps
CPU time	1.44 seconds
Started	Jan 10 12:58:14 PM PST 24
Finished	Jan 10 12:59:34 PM PST 24
Peak memory	214144 kb
Host	smart-5233df77-4ab4-4338-ba7d-18d20a52f5f5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599621860 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.1599621860
Directory	/workspace/13.edn_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2859730155
Short name	T397
Test name
Test status
Simulation time	85946287 ps
CPU time	2.37 seconds
Started	Jan 10 12:58:08 PM PST 24
Finished	Jan 10 12:59:31 PM PST 24
Peak memory	205992 kb
Host	smart-caca8cd7-dbb6-4bda-b108-7d7b254f6df0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859730155 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.2859730155
Directory	/workspace/13.edn_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1888339378
Short name	T392
Test name
Test status
Simulation time	22740449 ps
CPU time	1.42 seconds
Started	Jan 10 12:58:11 PM PST 24
Finished	Jan 10 12:59:32 PM PST 24
Peak memory	214336 kb
Host	smart-fab2ce07-c444-4318-880d-3810e8477820
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888339378 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.1888339378
Directory	/workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.edn_csr_rw.2930068794
Short name	T215
Test name
Test status
Simulation time	20403309 ps
CPU time	0.81 seconds
Started	Jan 10 12:58:13 PM PST 24
Finished	Jan 10 12:59:32 PM PST 24
Peak memory	205760 kb
Host	smart-4408a4e8-1ce9-4eda-b4ee-4446c211abcf
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930068794 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.2930068794
Directory	/workspace/14.edn_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.880726329
Short name	T356
Test name
Test status
Simulation time	22477532 ps
CPU time	1.13 seconds
Started	Jan 10 12:58:08 PM PST 24
Finished	Jan 10 12:59:29 PM PST 24
Peak memory	205992 kb
Host	smart-e8f40a54-50b7-4e38-b63d-d3efe4865ca5
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880726329 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_ou tstanding.880726329
Directory	/workspace/14.edn_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.edn_tl_errors.1206388876
Short name	T416
Test name
Test status
Simulation time	59493515 ps
CPU time	2.42 seconds
Started	Jan 10 12:58:08 PM PST 24
Finished	Jan 10 12:59:31 PM PST 24
Peak memory	214284 kb
Host	smart-77bf3968-5de8-481d-9e14-b2d195b6f7da
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206388876 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.1206388876
Directory	/workspace/14.edn_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.edn_tl_intg_err.402162635
Short name	T27
Test name
Test status
Simulation time	127679631 ps
CPU time	1.47 seconds
Started	Jan 10 12:58:11 PM PST 24
Finished	Jan 10 12:59:35 PM PST 24
Peak memory	205604 kb
Host	smart-e9c7c1c4-7999-443b-8b7b-0313fab47904
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402162635 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.402162635
Directory	/workspace/14.edn_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.3845699911
Short name	T434
Test name
Test status
Simulation time	41126259 ps
CPU time	0.9 seconds
Started	Jan 10 12:58:08 PM PST 24
Finished	Jan 10 12:59:29 PM PST 24
Peak memory	205984 kb
Host	smart-d74e0976-9d6a-4545-ad10-c585aadc7947
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845699911 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.3845699911
Directory	/workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.edn_csr_rw.2390858361
Short name	T220
Test name
Test status
Simulation time	20216901 ps
CPU time	0.82 seconds
Started	Jan 10 12:58:47 PM PST 24
Finished	Jan 10 01:00:12 PM PST 24
Peak memory	206016 kb
Host	smart-99b6f3a6-1463-45be-adf9-9ddfecc8b6cb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390858361 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.2390858361
Directory	/workspace/15.edn_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.edn_intr_test.3636093965
Short name	T371
Test name
Test status
Simulation time	12297543 ps
CPU time	0.78 seconds
Started	Jan 10 12:58:09 PM PST 24
Finished	Jan 10 12:59:29 PM PST 24
Peak memory	205676 kb
Host	smart-00cf4b42-80b0-4385-9202-29cdee95c012
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636093965 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3636093965
Directory	/workspace/15.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3188896352
Short name	T411
Test name
Test status
Simulation time	255050114 ps
CPU time	1.2 seconds
Started	Jan 10 01:00:21 PM PST 24
Finished	Jan 10 01:01:50 PM PST 24
Peak memory	205624 kb
Host	smart-c6abb5b5-cbfd-43f6-9e50-b5e029fe0cbe
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188896352 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o utstanding.3188896352
Directory	/workspace/15.edn_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.edn_tl_errors.3662346196
Short name	T259
Test name
Test status
Simulation time	293631059 ps
CPU time	2.63 seconds
Started	Jan 10 12:58:06 PM PST 24
Finished	Jan 10 12:59:28 PM PST 24
Peak memory	214188 kb
Host	smart-6b3c30ff-37ea-4a30-8043-5b156cde7222
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662346196 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.3662346196
Directory	/workspace/15.edn_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3326324427
Short name	T421
Test name
Test status
Simulation time	101257460 ps
CPU time	1.15 seconds
Started	Jan 10 12:58:14 PM PST 24
Finished	Jan 10 12:59:34 PM PST 24
Peak memory	214208 kb
Host	smart-ef6c88a7-538a-4c82-b1bc-4c95f262abdb
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326324427 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.3326324427
Directory	/workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.edn_csr_rw.1688465135
Short name	T114
Test name
Test status
Simulation time	25348274 ps
CPU time	0.82 seconds
Started	Jan 10 01:00:19 PM PST 24
Finished	Jan 10 01:02:00 PM PST 24
Peak memory	205600 kb
Host	smart-ce1d941e-dc20-49f4-a773-4009c2a08681
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688465135 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1688465135
Directory	/workspace/16.edn_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.edn_intr_test.1890546578
Short name	T437
Test name
Test status
Simulation time	11627311 ps
CPU time	0.8 seconds
Started	Jan 10 12:58:12 PM PST 24
Finished	Jan 10 12:59:33 PM PST 24
Peak memory	205896 kb
Host	smart-9cc7c2b2-b095-4f54-b47f-5fcf0a84a748
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890546578 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.1890546578
Directory	/workspace/16.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1537545536
Short name	T442
Test name
Test status
Simulation time	27764227 ps
CPU time	1.21 seconds
Started	Jan 10 12:58:05 PM PST 24
Finished	Jan 10 12:59:27 PM PST 24
Peak memory	206008 kb
Host	smart-8c4969f3-a46f-42e0-8338-bc7fed7eddc9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537545536 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o utstanding.1537545536
Directory	/workspace/16.edn_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.edn_tl_errors.2011792600
Short name	T386
Test name
Test status
Simulation time	86858043 ps
CPU time	2.78 seconds
Started	Jan 10 12:58:10 PM PST 24
Finished	Jan 10 12:59:33 PM PST 24
Peak memory	214184 kb
Host	smart-d3f88d58-5792-49b1-a4f0-3460677b1859
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011792600 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.2011792600
Directory	/workspace/16.edn_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1150766260
Short name	T444
Test name
Test status
Simulation time	157000846 ps
CPU time	1.61 seconds
Started	Jan 10 12:58:11 PM PST 24
Finished	Jan 10 12:59:32 PM PST 24
Peak memory	206052 kb
Host	smart-8587834a-d7d8-4c1d-9453-08e0a87018e7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150766260 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.1150766260
Directory	/workspace/16.edn_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1728364183
Short name	T425
Test name
Test status
Simulation time	33973893 ps
CPU time	1.4 seconds
Started	Jan 10 12:58:10 PM PST 24
Finished	Jan 10 12:59:31 PM PST 24
Peak memory	214216 kb
Host	smart-cc193d88-7dc6-4ead-bb4b-d9c0d2f49e5f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728364183 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.1728364183
Directory	/workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.edn_csr_rw.971874986
Short name	T428
Test name
Test status
Simulation time	28853372 ps
CPU time	0.86 seconds
Started	Jan 10 12:58:10 PM PST 24
Finished	Jan 10 12:59:31 PM PST 24
Peak memory	205852 kb
Host	smart-04fca577-1454-473d-ab4e-acd8207661dc
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971874986 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.971874986
Directory	/workspace/17.edn_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.edn_intr_test.466386347
Short name	T383
Test name
Test status
Simulation time	24038856 ps
CPU time	0.83 seconds
Started	Jan 10 12:58:08 PM PST 24
Finished	Jan 10 12:59:30 PM PST 24
Peak memory	205872 kb
Host	smart-988c2510-c141-4563-825f-b9a5ad57b60a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466386347 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.466386347
Directory	/workspace/17.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1140411952
Short name	T449
Test name
Test status
Simulation time	40616907 ps
CPU time	1.1 seconds
Started	Jan 10 12:58:07 PM PST 24
Finished	Jan 10 12:59:28 PM PST 24
Peak memory	205900 kb
Host	smart-5bcfebb1-9446-4e5e-a3d9-21830e1efec7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140411952 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o utstanding.1140411952
Directory	/workspace/17.edn_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.edn_tl_errors.2835094464
Short name	T390
Test name
Test status
Simulation time	365579450 ps
CPU time	3.17 seconds
Started	Jan 10 12:58:10 PM PST 24
Finished	Jan 10 12:59:33 PM PST 24
Peak memory	214268 kb
Host	smart-602d1aef-a1a0-4f55-a1fc-a4b42423a359
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835094464 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.2835094464
Directory	/workspace/17.edn_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2670862559
Short name	T402
Test name
Test status
Simulation time	76111758 ps
CPU time	1.97 seconds
Started	Jan 10 12:58:37 PM PST 24
Finished	Jan 10 12:59:59 PM PST 24
Peak memory	206032 kb
Host	smart-953db398-b2e4-4147-b9ff-72bd4ff92eba
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670862559 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.2670862559
Directory	/workspace/17.edn_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.565724072
Short name	T423
Test name
Test status
Simulation time	22681817 ps
CPU time	1.54 seconds
Started	Jan 10 12:58:06 PM PST 24
Finished	Jan 10 12:59:28 PM PST 24
Peak memory	214276 kb
Host	smart-26169858-758c-4065-843f-f9f59b998d4d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565724072 -assert nopostproc +UVM_TESTNAME= edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.565724072
Directory	/workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.edn_csr_rw.1624212688
Short name	T217
Test name
Test status
Simulation time	28160381 ps
CPU time	0.88 seconds
Started	Jan 10 01:00:19 PM PST 24
Finished	Jan 10 01:02:10 PM PST 24
Peak memory	205604 kb
Host	smart-98560434-dbac-4f5d-946f-29985a17605a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624212688 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1624212688
Directory	/workspace/18.edn_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.edn_intr_test.2151264073
Short name	T404
Test name
Test status
Simulation time	42988499 ps
CPU time	0.89 seconds
Started	Jan 10 01:00:21 PM PST 24
Finished	Jan 10 01:01:57 PM PST 24
Peak memory	205452 kb
Host	smart-a816565e-92d3-4fe4-8d3a-202a19d03f1e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151264073 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2151264073
Directory	/workspace/18.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2410665937
Short name	T407
Test name
Test status
Simulation time	30523726 ps
CPU time	1.31 seconds
Started	Jan 10 12:58:17 PM PST 24
Finished	Jan 10 12:59:37 PM PST 24
Peak memory	206020 kb
Host	smart-7c401ad6-96a5-41d3-98b4-c6d60e2644d6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410665937 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o utstanding.2410665937
Directory	/workspace/18.edn_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.edn_tl_errors.551086196
Short name	T418
Test name
Test status
Simulation time	88730797 ps
CPU time	2.81 seconds
Started	Jan 10 12:58:09 PM PST 24
Finished	Jan 10 12:59:32 PM PST 24
Peak memory	214268 kb
Host	smart-9cf9bc35-1e6f-407d-9f5b-d0457e583298
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551086196 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.551086196
Directory	/workspace/18.edn_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.4044312086
Short name	T427
Test name
Test status
Simulation time	121061831 ps
CPU time	1.41 seconds
Started	Jan 10 12:58:29 PM PST 24
Finished	Jan 10 12:59:51 PM PST 24
Peak memory	214352 kb
Host	smart-7524bdea-9224-44a7-9731-705b8c95d9fd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044312086 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.4044312086
Directory	/workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.edn_csr_rw.3322421754
Short name	T223
Test name
Test status
Simulation time	40453821 ps
CPU time	0.9 seconds
Started	Jan 10 12:58:25 PM PST 24
Finished	Jan 10 12:59:46 PM PST 24
Peak memory	206068 kb
Host	smart-c7aa5833-c60c-4eec-8fe5-27fcdb6327fa
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322421754 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.3322421754
Directory	/workspace/19.edn_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.edn_intr_test.577073957
Short name	T352
Test name
Test status
Simulation time	13694652 ps
CPU time	0.83 seconds
Started	Jan 10 01:00:19 PM PST 24
Finished	Jan 10 01:02:06 PM PST 24
Peak memory	205596 kb
Host	smart-b7c99fde-cc91-4264-a8d0-4bf842567d97
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577073957 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.577073957
Directory	/workspace/19.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.4111581841
Short name	T408
Test name
Test status
Simulation time	73554381 ps
CPU time	1.03 seconds
Started	Jan 10 12:58:25 PM PST 24
Finished	Jan 10 12:59:46 PM PST 24
Peak memory	206060 kb
Host	smart-40004903-eb45-428a-ac39-ab7550f3b92e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111581841 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o utstanding.4111581841
Directory	/workspace/19.edn_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.edn_tl_errors.1737525475
Short name	T370
Test name
Test status
Simulation time	155593994 ps
CPU time	2.68 seconds
Started	Jan 10 01:00:21 PM PST 24
Finished	Jan 10 01:01:59 PM PST 24
Peak memory	213892 kb
Host	smart-6ede7c7b-132a-4b4d-9b9c-cbf902507206
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737525475 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1737525475
Directory	/workspace/19.edn_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.edn_tl_intg_err.168737007
Short name	T206
Test name
Test status
Simulation time	151412832 ps
CPU time	1.49 seconds
Started	Jan 10 01:00:21 PM PST 24
Finished	Jan 10 01:01:57 PM PST 24
Peak memory	205412 kb
Host	smart-56a6c225-459f-493c-9981-7df80eed6868
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168737007 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.168737007
Directory	/workspace/19.edn_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3705011845
Short name	T222
Test name
Test status
Simulation time	175537532 ps
CPU time	1.25 seconds
Started	Jan 10 12:57:52 PM PST 24
Finished	Jan 10 12:59:11 PM PST 24
Peak memory	205996 kb
Host	smart-b03bbfa7-3993-4419-82e4-eadb6f45da5c
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705011845 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.3705011845
Directory	/workspace/2.edn_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3013951467
Short name	T219
Test name
Test status
Simulation time	260801555 ps
CPU time	3.19 seconds
Started	Jan 10 12:57:55 PM PST 24
Finished	Jan 10 12:59:18 PM PST 24
Peak memory	205884 kb
Host	smart-531b0127-c244-4e82-b50c-6aab359055eb
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013951467 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.3013951467
Directory	/workspace/2.edn_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.4101969470
Short name	T201
Test name
Test status
Simulation time	54035150 ps
CPU time	0.89 seconds
Started	Jan 10 12:57:55 PM PST 24
Finished	Jan 10 12:59:15 PM PST 24
Peak memory	205964 kb
Host	smart-f3b9b9ed-4450-4a98-8b01-c83395e4d210
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101969470 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.4101969470
Directory	/workspace/2.edn_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.83035229
Short name	T403
Test name
Test status
Simulation time	297802589 ps
CPU time	1.22 seconds
Started	Jan 10 12:57:52 PM PST 24
Finished	Jan 10 12:59:12 PM PST 24
Peak memory	214224 kb
Host	smart-59b57af4-f9d5-4bec-9099-b07ad89cf8eb
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83035229 -assert nopostproc +UVM_TESTNAME=e dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.83035229
Directory	/workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.edn_csr_rw.1508904149
Short name	T420
Test name
Test status
Simulation time	22403363 ps
CPU time	0.81 seconds
Started	Jan 10 12:57:51 PM PST 24
Finished	Jan 10 12:59:10 PM PST 24
Peak memory	205888 kb
Host	smart-5c2aa67f-ebc0-43e7-a918-560c9dd5f82f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508904149 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.1508904149
Directory	/workspace/2.edn_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.edn_intr_test.3141346458
Short name	T360
Test name
Test status
Simulation time	44265786 ps
CPU time	0.82 seconds
Started	Jan 10 12:57:57 PM PST 24
Finished	Jan 10 12:59:17 PM PST 24
Peak memory	205980 kb
Host	smart-46af14a2-f52a-4b33-8ad9-77fe02963c9b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141346458 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.3141346458
Directory	/workspace/2.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.904958566
Short name	T224
Test name
Test status
Simulation time	97040754 ps
CPU time	1.25 seconds
Started	Jan 10 12:57:57 PM PST 24
Finished	Jan 10 12:59:18 PM PST 24
Peak memory	206032 kb
Host	smart-ffa0d341-d814-4b69-be81-abee527ee605
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904958566 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_out standing.904958566
Directory	/workspace/2.edn_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.edn_tl_errors.3162943169
Short name	T387
Test name
Test status
Simulation time	99075917 ps
CPU time	3.77 seconds
Started	Jan 10 12:57:53 PM PST 24
Finished	Jan 10 12:59:15 PM PST 24
Peak memory	214248 kb
Host	smart-01220899-95fc-4116-ba57-c71e2c632b8a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162943169 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.3162943169
Directory	/workspace/2.edn_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1624461153
Short name	T186
Test name
Test status
Simulation time	72415953 ps
CPU time	1.38 seconds
Started	Jan 10 12:57:55 PM PST 24
Finished	Jan 10 12:59:15 PM PST 24
Peak memory	206024 kb
Host	smart-debd999f-ab83-4ea9-95b9-46df6babc677
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624461153 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.1624461153
Directory	/workspace/2.edn_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.edn_intr_test.2582872792
Short name	T382
Test name
Test status
Simulation time	22952471 ps
CPU time	0.82 seconds
Started	Jan 10 12:58:25 PM PST 24
Finished	Jan 10 12:59:46 PM PST 24
Peak memory	206016 kb
Host	smart-759f4f00-8215-481b-aad0-2ea95c94cc21
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582872792 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.2582872792
Directory	/workspace/20.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.edn_intr_test.399444785
Short name	T42
Test name
Test status
Simulation time	38209399 ps
CPU time	0.78 seconds
Started	Jan 10 12:58:29 PM PST 24
Finished	Jan 10 12:59:50 PM PST 24
Peak memory	205928 kb
Host	smart-2bd5abbc-50cd-434b-9347-fa2ddde26a87
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399444785 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.399444785
Directory	/workspace/21.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.edn_intr_test.2099489661
Short name	T204
Test name
Test status
Simulation time	31245991 ps
CPU time	0.89 seconds
Started	Jan 10 12:58:23 PM PST 24
Finished	Jan 10 12:59:43 PM PST 24
Peak memory	205920 kb
Host	smart-e8221ffd-8eca-44c6-afe7-87c6ea499a96
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099489661 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.2099489661
Directory	/workspace/22.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.edn_intr_test.2895162880
Short name	T354
Test name
Test status
Simulation time	46784779 ps
CPU time	0.82 seconds
Started	Jan 10 12:58:27 PM PST 24
Finished	Jan 10 12:59:48 PM PST 24
Peak memory	205944 kb
Host	smart-db3c81ff-6721-4d84-905b-50a6fd875cd5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895162880 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.2895162880
Directory	/workspace/23.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.edn_intr_test.852925627
Short name	T432
Test name
Test status
Simulation time	26518098 ps
CPU time	0.83 seconds
Started	Jan 10 12:58:19 PM PST 24
Finished	Jan 10 12:59:38 PM PST 24
Peak memory	205904 kb
Host	smart-932203ee-be3a-4871-981d-c5787cb44d92
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852925627 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.852925627
Directory	/workspace/24.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.edn_intr_test.3284288307
Short name	T199
Test name
Test status
Simulation time	13646386 ps
CPU time	0.85 seconds
Started	Jan 10 12:58:22 PM PST 24
Finished	Jan 10 12:59:42 PM PST 24
Peak memory	205924 kb
Host	smart-5754a0fe-3ab6-4f2e-bb74-f671a82499f3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284288307 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3284288307
Directory	/workspace/25.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.edn_intr_test.3147340557
Short name	T294
Test name
Test status
Simulation time	22276364 ps
CPU time	0.83 seconds
Started	Jan 10 12:58:21 PM PST 24
Finished	Jan 10 12:59:41 PM PST 24
Peak memory	205976 kb
Host	smart-1e038135-1ecb-4f61-ba25-e625c9965a28
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147340557 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.3147340557
Directory	/workspace/26.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.edn_intr_test.3296544605
Short name	T368
Test name
Test status
Simulation time	18077534 ps
CPU time	0.88 seconds
Started	Jan 10 12:58:23 PM PST 24
Finished	Jan 10 12:59:43 PM PST 24
Peak memory	206008 kb
Host	smart-6a34f8d2-a0ed-4663-a458-b75f453f2ac2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296544605 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3296544605
Directory	/workspace/27.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.edn_intr_test.3638473936
Short name	T435
Test name
Test status
Simulation time	12399941 ps
CPU time	0.8 seconds
Started	Jan 10 12:58:25 PM PST 24
Finished	Jan 10 12:59:46 PM PST 24
Peak memory	205988 kb
Host	smart-18337056-71d5-4f1f-a3f5-c8b24c341203
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638473936 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.3638473936
Directory	/workspace/28.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.edn_intr_test.2011773982
Short name	T357
Test name
Test status
Simulation time	75207239 ps
CPU time	0.86 seconds
Started	Jan 10 12:58:24 PM PST 24
Finished	Jan 10 12:59:44 PM PST 24
Peak memory	205848 kb
Host	smart-6b8374d4-b75b-4106-9fb6-237b1e43eb33
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011773982 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.2011773982
Directory	/workspace/29.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.edn_csr_aliasing.770048283
Short name	T441
Test name
Test status
Simulation time	46591799 ps
CPU time	0.93 seconds
Started	Jan 10 12:57:58 PM PST 24
Finished	Jan 10 12:59:18 PM PST 24
Peak memory	206044 kb
Host	smart-6ec6ac69-ba97-4e81-a5fc-934e0fed6ce5
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770048283 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.770048283
Directory	/workspace/3.edn_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3139260663
Short name	T443
Test name
Test status
Simulation time	269086176 ps
CPU time	2.05 seconds
Started	Jan 10 12:57:55 PM PST 24
Finished	Jan 10 12:59:17 PM PST 24
Peak memory	206016 kb
Host	smart-6f946c2a-5a4f-43dd-9f48-f62f0737b5b0
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139260663 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.3139260663
Directory	/workspace/3.edn_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.1812814436
Short name	T213
Test name
Test status
Simulation time	21499877 ps
CPU time	0.82 seconds
Started	Jan 10 12:57:57 PM PST 24
Finished	Jan 10 12:59:17 PM PST 24
Peak memory	205884 kb
Host	smart-b3b979ca-8210-4563-8f3b-fd52c5410d45
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812814436 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.1812814436
Directory	/workspace/3.edn_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.217093787
Short name	T429
Test name
Test status
Simulation time	29234247 ps
CPU time	1.34 seconds
Started	Jan 10 12:57:57 PM PST 24
Finished	Jan 10 12:59:18 PM PST 24
Peak memory	214452 kb
Host	smart-cf25cb6b-8e3e-4cc5-a3f9-db75cd9a3356
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217093787 -assert nopostproc +UVM_TESTNAME= edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.217093787
Directory	/workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.edn_csr_rw.3049931672
Short name	T191
Test name
Test status
Simulation time	38543307 ps
CPU time	0.81 seconds
Started	Jan 10 12:57:56 PM PST 24
Finished	Jan 10 12:59:16 PM PST 24
Peak memory	205680 kb
Host	smart-9763387c-4412-4889-bf74-5369af6a9671
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049931672 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.3049931672
Directory	/workspace/3.edn_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.edn_intr_test.3901551991
Short name	T353
Test name
Test status
Simulation time	25626202 ps
CPU time	0.78 seconds
Started	Jan 10 12:59:46 PM PST 24
Finished	Jan 10 01:01:27 PM PST 24
Peak memory	205572 kb
Host	smart-760787e6-1bca-4f6f-b338-3709c803a7cf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901551991 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.3901551991
Directory	/workspace/3.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1714287246
Short name	T372
Test name
Test status
Simulation time	19104786 ps
CPU time	1.23 seconds
Started	Jan 10 12:57:57 PM PST 24
Finished	Jan 10 12:59:18 PM PST 24
Peak memory	206068 kb
Host	smart-dfeab87c-3fb3-44e3-bc35-2b9fddc74db9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714287246 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou tstanding.1714287246
Directory	/workspace/3.edn_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.edn_tl_errors.2731269497
Short name	T134
Test name
Test status
Simulation time	203985408 ps
CPU time	2.04 seconds
Started	Jan 10 12:58:00 PM PST 24
Finished	Jan 10 12:59:22 PM PST 24
Peak memory	214340 kb
Host	smart-aefd105e-f6b4-4d7b-b8bd-7d36ee25f669
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731269497 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.2731269497
Directory	/workspace/3.edn_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.edn_tl_intg_err.865268471
Short name	T385
Test name
Test status
Simulation time	1197495494 ps
CPU time	2.62 seconds
Started	Jan 10 12:57:55 PM PST 24
Finished	Jan 10 12:59:17 PM PST 24
Peak memory	206072 kb
Host	smart-3ee25004-7b6e-4039-afbc-3ef32e6cc385
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865268471 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.865268471
Directory	/workspace/3.edn_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.edn_intr_test.2550684741
Short name	T440
Test name
Test status
Simulation time	160462265 ps
CPU time	0.79 seconds
Started	Jan 10 12:58:20 PM PST 24
Finished	Jan 10 12:59:40 PM PST 24
Peak memory	205816 kb
Host	smart-2a7d2f94-85d6-44e3-b762-f0e61b6a8f84
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550684741 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2550684741
Directory	/workspace/30.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.edn_intr_test.2808293731
Short name	T297
Test name
Test status
Simulation time	30692551 ps
CPU time	0.77 seconds
Started	Jan 10 12:58:19 PM PST 24
Finished	Jan 10 12:59:39 PM PST 24
Peak memory	205728 kb
Host	smart-78e12c05-c4c7-4e69-9a7a-39df1fdb0caf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808293731 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.2808293731
Directory	/workspace/31.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.edn_intr_test.184694585
Short name	T362
Test name
Test status
Simulation time	12966113 ps
CPU time	0.85 seconds
Started	Jan 10 12:58:21 PM PST 24
Finished	Jan 10 12:59:41 PM PST 24
Peak memory	205944 kb
Host	smart-70488e17-3c37-4e2c-a709-5bd573cdaba1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184694585 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.184694585
Directory	/workspace/32.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.edn_intr_test.2654907517
Short name	T399
Test name
Test status
Simulation time	18783260 ps
CPU time	0.78 seconds
Started	Jan 10 12:58:23 PM PST 24
Finished	Jan 10 12:59:43 PM PST 24
Peak memory	206020 kb
Host	smart-5f245302-f91d-4f12-98ca-9c3591ca4090
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654907517 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.2654907517
Directory	/workspace/33.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.edn_intr_test.1816792778
Short name	T41
Test name
Test status
Simulation time	55598358 ps
CPU time	0.77 seconds
Started	Jan 10 12:58:17 PM PST 24
Finished	Jan 10 12:59:37 PM PST 24
Peak memory	205676 kb
Host	smart-132bb034-c9e7-4d02-9278-3dca6c294297
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816792778 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.1816792778
Directory	/workspace/34.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.edn_intr_test.2429869288
Short name	T296
Test name
Test status
Simulation time	48667187 ps
CPU time	0.86 seconds
Started	Jan 10 12:58:25 PM PST 24
Finished	Jan 10 12:59:46 PM PST 24
Peak memory	205988 kb
Host	smart-4ef6b3c1-bda3-40da-ac2f-cb03d29ae90d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429869288 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.2429869288
Directory	/workspace/35.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.edn_intr_test.4081935064
Short name	T414
Test name
Test status
Simulation time	21854737 ps
CPU time	0.81 seconds
Started	Jan 10 12:58:22 PM PST 24
Finished	Jan 10 12:59:42 PM PST 24
Peak memory	205984 kb
Host	smart-d731e353-fe4b-4882-914b-c29e031bc3d0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081935064 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.4081935064
Directory	/workspace/36.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.edn_intr_test.1640829784
Short name	T367
Test name
Test status
Simulation time	22355014 ps
CPU time	0.79 seconds
Started	Jan 10 12:58:20 PM PST 24
Finished	Jan 10 12:59:40 PM PST 24
Peak memory	205880 kb
Host	smart-1c28d50a-cfa6-4777-8084-9d9ca4c3746f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640829784 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.1640829784
Directory	/workspace/37.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.edn_intr_test.3202963018
Short name	T189
Test name
Test status
Simulation time	42287914 ps
CPU time	0.8 seconds
Started	Jan 10 12:58:27 PM PST 24
Finished	Jan 10 12:59:48 PM PST 24
Peak memory	205944 kb
Host	smart-b7d7ad25-57a2-4919-800f-5bf73ff0dd48
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202963018 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.3202963018
Directory	/workspace/38.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.edn_intr_test.3259154283
Short name	T380
Test name
Test status
Simulation time	51329715 ps
CPU time	0.76 seconds
Started	Jan 10 12:58:24 PM PST 24
Finished	Jan 10 12:59:44 PM PST 24
Peak memory	205812 kb
Host	smart-44e3a140-3ca8-46fb-9e2a-8543631d47a6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259154283 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3259154283
Directory	/workspace/39.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.edn_csr_aliasing.1170520104
Short name	T211
Test name
Test status
Simulation time	229886204 ps
CPU time	1.21 seconds
Started	Jan 10 12:57:59 PM PST 24
Finished	Jan 10 12:59:19 PM PST 24
Peak memory	206052 kb
Host	smart-d52c1cf7-2a5b-4836-924b-861a287b9929
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170520104 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.1170520104
Directory	/workspace/4.edn_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3822452713
Short name	T351
Test name
Test status
Simulation time	1701212737 ps
CPU time	4.98 seconds
Started	Jan 10 12:57:50 PM PST 24
Finished	Jan 10 12:59:13 PM PST 24
Peak memory	205980 kb
Host	smart-82988a28-f0e7-470a-849b-efe36c71db18
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822452713 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.3822452713
Directory	/workspace/4.edn_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3047475151
Short name	T379
Test name
Test status
Simulation time	98236652 ps
CPU time	0.92 seconds
Started	Jan 10 12:59:45 PM PST 24
Finished	Jan 10 01:01:20 PM PST 24
Peak memory	204344 kb
Host	smart-f9d3dfdf-fa5a-4438-943f-b8c7a5a1a7d4
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047475151 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3047475151
Directory	/workspace/4.edn_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2428437486
Short name	T28
Test name
Test status
Simulation time	27914775 ps
CPU time	1.26 seconds
Started	Jan 10 12:57:52 PM PST 24
Finished	Jan 10 12:59:11 PM PST 24
Peak memory	214240 kb
Host	smart-be3718a1-29f6-4907-840d-208081263623
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428437486 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.2428437486
Directory	/workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.edn_csr_rw.2677324017
Short name	T431
Test name
Test status
Simulation time	48415185 ps
CPU time	0.88 seconds
Started	Jan 10 12:57:51 PM PST 24
Finished	Jan 10 12:59:11 PM PST 24
Peak memory	205920 kb
Host	smart-e2474968-cc62-4d39-ae6f-defd4f7fdf66
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677324017 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2677324017
Directory	/workspace/4.edn_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.edn_intr_test.4097839891
Short name	T419
Test name
Test status
Simulation time	31764279 ps
CPU time	0.77 seconds
Started	Jan 10 12:57:59 PM PST 24
Finished	Jan 10 12:59:20 PM PST 24
Peak memory	205812 kb
Host	smart-0ac33c6e-9f7b-4b70-bad9-4f48c3209197
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097839891 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.4097839891
Directory	/workspace/4.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2708646340
Short name	T445
Test name
Test status
Simulation time	27358483 ps
CPU time	1.08 seconds
Started	Jan 10 12:57:54 PM PST 24
Finished	Jan 10 12:59:15 PM PST 24
Peak memory	206056 kb
Host	smart-1810297f-69a6-4ad2-9f92-c8d068f98513
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708646340 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou tstanding.2708646340
Directory	/workspace/4.edn_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.edn_tl_errors.3958236588
Short name	T422
Test name
Test status
Simulation time	94907118 ps
CPU time	3.21 seconds
Started	Jan 10 12:57:54 PM PST 24
Finished	Jan 10 12:59:17 PM PST 24
Peak memory	214288 kb
Host	smart-ae8b93de-bc87-41e1-ad14-84f3a8484d27
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958236588 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.3958236588
Directory	/workspace/4.edn_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.edn_tl_intg_err.661870355
Short name	T406
Test name
Test status
Simulation time	364820904 ps
CPU time	2.36 seconds
Started	Jan 10 12:57:51 PM PST 24
Finished	Jan 10 12:59:12 PM PST 24
Peak memory	206012 kb
Host	smart-1bdd0f55-7f4f-4486-b058-78fba5fc20d5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661870355 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.661870355
Directory	/workspace/4.edn_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.edn_intr_test.2313518519
Short name	T438
Test name
Test status
Simulation time	17263558 ps
CPU time	0.81 seconds
Started	Jan 10 12:58:32 PM PST 24
Finished	Jan 10 12:59:53 PM PST 24
Peak memory	205956 kb
Host	smart-7f7762fd-4c1e-4031-98ae-b716df60b2a5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313518519 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.2313518519
Directory	/workspace/40.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.edn_intr_test.633830476
Short name	T192
Test name
Test status
Simulation time	24200685 ps
CPU time	0.83 seconds
Started	Jan 10 12:58:25 PM PST 24
Finished	Jan 10 12:59:45 PM PST 24
Peak memory	205864 kb
Host	smart-ddaed358-0a31-4b7b-a38a-5372ea9ed37f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633830476 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.633830476
Directory	/workspace/41.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.edn_intr_test.3633377484
Short name	T376
Test name
Test status
Simulation time	28012818 ps
CPU time	0.73 seconds
Started	Jan 10 12:58:28 PM PST 24
Finished	Jan 10 12:59:49 PM PST 24
Peak memory	205820 kb
Host	smart-4d7f81d5-f57c-4a57-96ce-31cfd19efcc0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633377484 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.3633377484
Directory	/workspace/42.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.edn_intr_test.3567393579
Short name	T394
Test name
Test status
Simulation time	21378440 ps
CPU time	0.83 seconds
Started	Jan 10 12:58:28 PM PST 24
Finished	Jan 10 12:59:49 PM PST 24
Peak memory	205956 kb
Host	smart-f6ae9cc5-ff2e-44bb-a7af-97ea2fdadfd8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567393579 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.3567393579
Directory	/workspace/43.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.edn_intr_test.1492478797
Short name	T381
Test name
Test status
Simulation time	30618930 ps
CPU time	0.77 seconds
Started	Jan 10 12:58:32 PM PST 24
Finished	Jan 10 12:59:53 PM PST 24
Peak memory	205772 kb
Host	smart-607e48ff-d07e-41af-93d0-9b9aa9e16c61
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492478797 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.1492478797
Directory	/workspace/44.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.edn_intr_test.2172776860
Short name	T413
Test name
Test status
Simulation time	58303151 ps
CPU time	0.75 seconds
Started	Jan 10 12:58:28 PM PST 24
Finished	Jan 10 12:59:49 PM PST 24
Peak memory	205752 kb
Host	smart-d9c994e8-50fc-4511-9d03-44c8d263610e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172776860 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.2172776860
Directory	/workspace/45.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.edn_intr_test.721519340
Short name	T295
Test name
Test status
Simulation time	16259447 ps
CPU time	0.9 seconds
Started	Jan 10 12:59:05 PM PST 24
Finished	Jan 10 01:00:43 PM PST 24
Peak memory	206020 kb
Host	smart-39cf883f-16cb-42e0-b3b8-74207a044203
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721519340 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.721519340
Directory	/workspace/46.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.edn_intr_test.1118833271
Short name	T363
Test name
Test status
Simulation time	13621567 ps
CPU time	0.9 seconds
Started	Jan 10 12:58:28 PM PST 24
Finished	Jan 10 12:59:49 PM PST 24
Peak memory	205948 kb
Host	smart-1a23d68d-162c-4c91-ba4f-886b18a2dbfd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118833271 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.1118833271
Directory	/workspace/47.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.edn_intr_test.3850763513
Short name	T361
Test name
Test status
Simulation time	18410742 ps
CPU time	0.8 seconds
Started	Jan 10 12:58:33 PM PST 24
Finished	Jan 10 12:59:54 PM PST 24
Peak memory	206000 kb
Host	smart-701f3528-afde-4023-b658-45c06bce5835
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850763513 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.3850763513
Directory	/workspace/48.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.edn_intr_test.2166743109
Short name	T398
Test name
Test status
Simulation time	14051515 ps
CPU time	0.88 seconds
Started	Jan 10 12:58:31 PM PST 24
Finished	Jan 10 12:59:52 PM PST 24
Peak memory	205992 kb
Host	smart-0c408798-5aa2-433c-bcff-ce33aec6af39
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166743109 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.2166743109
Directory	/workspace/49.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2741798075
Short name	T410
Test name
Test status
Simulation time	29765098 ps
CPU time	1.18 seconds
Started	Jan 10 12:58:02 PM PST 24
Finished	Jan 10 12:59:24 PM PST 24
Peak memory	214192 kb
Host	smart-ed0e820f-a735-4f57-a208-51fa63a80725
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741798075 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.2741798075
Directory	/workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.edn_csr_rw.1928113420
Short name	T198
Test name
Test status
Simulation time	16658766 ps
CPU time	0.94 seconds
Started	Jan 10 12:58:10 PM PST 24
Finished	Jan 10 12:59:31 PM PST 24
Peak memory	205996 kb
Host	smart-ec73fc89-6580-4bae-a721-2610336c7e16
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928113420 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.1928113420
Directory	/workspace/5.edn_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.edn_intr_test.1157580639
Short name	T417
Test name
Test status
Simulation time	21786521 ps
CPU time	0.8 seconds
Started	Jan 10 12:57:54 PM PST 24
Finished	Jan 10 12:59:13 PM PST 24
Peak memory	206008 kb
Host	smart-8ae8635e-e16a-45fe-8b7b-be5db13d2bd2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157580639 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.1157580639
Directory	/workspace/5.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3496699896
Short name	T205
Test name
Test status
Simulation time	108766108 ps
CPU time	1.26 seconds
Started	Jan 10 12:58:02 PM PST 24
Finished	Jan 10 12:59:23 PM PST 24
Peak memory	205984 kb
Host	smart-0ab433e7-bad2-4cb3-95d3-801236655607
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496699896 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou tstanding.3496699896
Directory	/workspace/5.edn_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.edn_tl_errors.664775224
Short name	T369
Test name
Test status
Simulation time	124852440 ps
CPU time	2.45 seconds
Started	Jan 10 12:57:52 PM PST 24
Finished	Jan 10 12:59:13 PM PST 24
Peak memory	214184 kb
Host	smart-1fdaece7-3680-4eaa-b82d-333232b83406
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664775224 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.664775224
Directory	/workspace/5.edn_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.edn_csr_rw.1335212742
Short name	T207
Test name
Test status
Simulation time	21695670 ps
CPU time	0.87 seconds
Started	Jan 10 12:58:09 PM PST 24
Finished	Jan 10 12:59:30 PM PST 24
Peak memory	205820 kb
Host	smart-b256d869-2f87-4526-8b95-0c1fd85728b9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335212742 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.1335212742
Directory	/workspace/6.edn_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.edn_intr_test.1797526951
Short name	T365
Test name
Test status
Simulation time	23674574 ps
CPU time	0.82 seconds
Started	Jan 10 12:58:07 PM PST 24
Finished	Jan 10 12:59:28 PM PST 24
Peak memory	205948 kb
Host	smart-885cbe1a-f54a-4c3b-add1-33009ca11ed3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797526951 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.1797526951
Directory	/workspace/6.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.4072186969
Short name	T196
Test name
Test status
Simulation time	36413646 ps
CPU time	1.37 seconds
Started	Jan 10 12:58:11 PM PST 24
Finished	Jan 10 12:59:32 PM PST 24
Peak memory	206080 kb
Host	smart-3e5fd078-b71c-4586-9152-c26b6b8fcaeb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072186969 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou tstanding.4072186969
Directory	/workspace/6.edn_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.edn_tl_errors.2351914421
Short name	T393
Test name
Test status
Simulation time	37858473 ps
CPU time	2.63 seconds
Started	Jan 10 12:58:08 PM PST 24
Finished	Jan 10 12:59:31 PM PST 24
Peak memory	214240 kb
Host	smart-a2313b04-f23f-4e01-ba48-2af3a10ab26e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351914421 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.2351914421
Directory	/workspace/6.edn_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.edn_tl_intg_err.118057990
Short name	T263
Test name
Test status
Simulation time	156944383 ps
CPU time	2.25 seconds
Started	Jan 10 12:58:26 PM PST 24
Finished	Jan 10 12:59:48 PM PST 24
Peak memory	205904 kb
Host	smart-92985cbb-1442-4756-8050-c4fa8f7c1f22
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118057990 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.118057990
Directory	/workspace/6.edn_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1467960993
Short name	T433
Test name
Test status
Simulation time	50861146 ps
CPU time	1.37 seconds
Started	Jan 10 12:58:02 PM PST 24
Finished	Jan 10 12:59:23 PM PST 24
Peak memory	214236 kb
Host	smart-edacc401-5f8b-435b-80a8-74c4b7fdc7ce
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467960993 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.1467960993
Directory	/workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.edn_csr_rw.3548700557
Short name	T447
Test name
Test status
Simulation time	137881218 ps
CPU time	0.9 seconds
Started	Jan 10 12:58:05 PM PST 24
Finished	Jan 10 12:59:28 PM PST 24
Peak memory	205712 kb
Host	smart-f47b6ea1-b29d-4bb2-8f2a-c39325d62a06
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548700557 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.3548700557
Directory	/workspace/7.edn_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.edn_intr_test.980891205
Short name	T439
Test name
Test status
Simulation time	73015871 ps
CPU time	0.86 seconds
Started	Jan 10 12:58:02 PM PST 24
Finished	Jan 10 12:59:23 PM PST 24
Peak memory	205988 kb
Host	smart-4c482f1e-2d76-4ade-9228-8180713565da
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980891205 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.980891205
Directory	/workspace/7.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3385676338
Short name	T115
Test name
Test status
Simulation time	16303132 ps
CPU time	1.05 seconds
Started	Jan 10 12:58:10 PM PST 24
Finished	Jan 10 12:59:31 PM PST 24
Peak memory	205956 kb
Host	smart-5e763640-ab00-4b9b-a2a5-74fc61ee2895
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385676338 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou tstanding.3385676338
Directory	/workspace/7.edn_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.edn_tl_errors.2613533742
Short name	T375
Test name
Test status
Simulation time	110352349 ps
CPU time	3.85 seconds
Started	Jan 10 12:58:07 PM PST 24
Finished	Jan 10 12:59:31 PM PST 24
Peak memory	214180 kb
Host	smart-2dc1ba73-9e8c-4436-bda1-a07a71564bef
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613533742 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2613533742
Directory	/workspace/7.edn_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.edn_tl_intg_err.13456041
Short name	T412
Test name
Test status
Simulation time	147347309 ps
CPU time	2.37 seconds
Started	Jan 10 12:58:06 PM PST 24
Finished	Jan 10 12:59:29 PM PST 24
Peak memory	206008 kb
Host	smart-7d391a6d-669c-41d8-b966-6dde881ddc0f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13456041 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.13456041
Directory	/workspace/7.edn_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1412507153
Short name	T350
Test name
Test status
Simulation time	415986953 ps
CPU time	1.34 seconds
Started	Jan 10 12:58:05 PM PST 24
Finished	Jan 10 12:59:28 PM PST 24
Peak memory	214224 kb
Host	smart-1f23b02f-41d6-4c59-9245-3e3d8ecc7411
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412507153 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.1412507153
Directory	/workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.edn_csr_rw.3280552162
Short name	T209
Test name
Test status
Simulation time	25686178 ps
CPU time	0.88 seconds
Started	Jan 10 12:58:06 PM PST 24
Finished	Jan 10 12:59:28 PM PST 24
Peak memory	205904 kb
Host	smart-9f973716-09f3-4078-adbd-73ab24d55de6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280552162 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.3280552162
Directory	/workspace/8.edn_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.edn_intr_test.770562556
Short name	T374
Test name
Test status
Simulation time	22534985 ps
CPU time	0.79 seconds
Started	Jan 10 12:58:00 PM PST 24
Finished	Jan 10 12:59:21 PM PST 24
Peak memory	205900 kb
Host	smart-55153862-59b6-438f-b72d-26f4d4b95a3b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770562556 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.770562556
Directory	/workspace/8.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2912515123
Short name	T194
Test name
Test status
Simulation time	118234327 ps
CPU time	1.36 seconds
Started	Jan 10 12:58:03 PM PST 24
Finished	Jan 10 12:59:25 PM PST 24
Peak memory	206016 kb
Host	smart-419db6e6-26e6-4a35-a0ea-21d3bdc9303f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912515123 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou tstanding.2912515123
Directory	/workspace/8.edn_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.edn_tl_errors.1794165737
Short name	T185
Test name
Test status
Simulation time	196497356 ps
CPU time	3.1 seconds
Started	Jan 10 12:58:08 PM PST 24
Finished	Jan 10 12:59:31 PM PST 24
Peak memory	214264 kb
Host	smart-52b2e212-eb9f-45c3-90e5-467b32eef799
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794165737 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.1794165737
Directory	/workspace/8.edn_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.edn_tl_intg_err.4212088531
Short name	T377
Test name
Test status
Simulation time	190090495 ps
CPU time	1.56 seconds
Started	Jan 10 12:58:01 PM PST 24
Finished	Jan 10 12:59:22 PM PST 24
Peak memory	205940 kb
Host	smart-61c2f03b-646f-4ece-9cf0-fa27ca3ebf80
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212088531 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.4212088531
Directory	/workspace/8.edn_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1121339120
Short name	T349
Test name
Test status
Simulation time	24471299 ps
CPU time	0.89 seconds
Started	Jan 10 12:58:05 PM PST 24
Finished	Jan 10 12:59:26 PM PST 24
Peak memory	205992 kb
Host	smart-d22224e6-6485-4119-9d1a-bb9b9c00142b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121339120 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.1121339120
Directory	/workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.edn_csr_rw.3505818356
Short name	T208
Test name
Test status
Simulation time	14249727 ps
CPU time	0.92 seconds
Started	Jan 10 12:58:09 PM PST 24
Finished	Jan 10 12:59:30 PM PST 24
Peak memory	205968 kb
Host	smart-132346cb-c54c-4d67-9f5f-c97bcaf753a2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505818356 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3505818356
Directory	/workspace/9.edn_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.edn_intr_test.1859646581
Short name	T40
Test name
Test status
Simulation time	102133048 ps
CPU time	0.8 seconds
Started	Jan 10 12:58:09 PM PST 24
Finished	Jan 10 12:59:30 PM PST 24
Peak memory	205816 kb
Host	smart-7cf44934-1535-4f9c-8c04-a614924237ba
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859646581 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.1859646581
Directory	/workspace/9.edn_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2545976346
Short name	T448
Test name
Test status
Simulation time	150099431 ps
CPU time	1 seconds
Started	Jan 10 12:58:06 PM PST 24
Finished	Jan 10 12:59:27 PM PST 24
Peak memory	205988 kb
Host	smart-a12e6c6a-cff1-4071-8124-b677b473e5e9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545976346 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou tstanding.2545976346
Directory	/workspace/9.edn_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.edn_tl_errors.1213317818
Short name	T396
Test name
Test status
Simulation time	660696609 ps
CPU time	2.43 seconds
Started	Jan 10 12:59:59 PM PST 24
Finished	Jan 10 01:01:34 PM PST 24
Peak memory	213348 kb
Host	smart-17e4a62a-cdcc-43a0-bc36-43c47fd12222
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213317818 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.1213317818
Directory	/workspace/9.edn_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2231441992
Short name	T261
Test name
Test status
Simulation time	263981162 ps
CPU time	2.03 seconds
Started	Jan 10 12:58:06 PM PST 24
Finished	Jan 10 12:59:28 PM PST 24
Peak memory	206020 kb
Host	smart-ae5ea15e-b982-4d57-b28a-316b6db8a94a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231441992 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.2231441992
Directory	/workspace/9.edn_tl_intg_err/latest

Test location	/workspace/coverage/default/0.edn_alert.3711622883
Short name	T328
Test name
Test status
Simulation time	28006453 ps
CPU time	0.97 seconds
Started	Jan 10 01:18:15 PM PST 24
Finished	Jan 10 01:18:23 PM PST 24
Peak memory	205360 kb
Host	smart-683e3f78-700c-482b-9f0c-706f2a592f30
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3711622883 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.3711622883
Directory	/workspace/0.edn_alert/latest

Test location	/workspace/coverage/default/0.edn_disable_auto_req_mode.837909586
Short name	T229
Test name
Test status
Simulation time	23024029 ps
CPU time	0.96 seconds
Started	Jan 10 01:18:21 PM PST 24
Finished	Jan 10 01:18:29 PM PST 24
Peak memory	214556 kb
Host	smart-e2556551-ba96-464b-8c63-ad13472db041
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837909586 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_dis able_auto_req_mode.837909586
Directory	/workspace/0.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/0.edn_err.416996314
Short name	T453
Test name
Test status
Simulation time	38526312 ps
CPU time	1.09 seconds
Started	Jan 10 01:18:23 PM PST 24
Finished	Jan 10 01:18:32 PM PST 24
Peak memory	215116 kb
Host	smart-4682eef9-34f7-49b2-b32b-6d5a84276fdc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=416996314 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.416996314
Directory	/workspace/0.edn_err/latest

Test location	/workspace/coverage/default/0.edn_genbits.616786407
Short name	T761
Test name
Test status
Simulation time	15483665 ps
CPU time	0.98 seconds
Started	Jan 10 01:18:20 PM PST 24
Finished	Jan 10 01:18:27 PM PST 24
Peak memory	205612 kb
Host	smart-1f541ccd-3369-4cb4-96ba-1a40c1241197
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=616786407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.616786407
Directory	/workspace/0.edn_genbits/latest

Test location	/workspace/coverage/default/0.edn_intr.1932069905
Short name	T854
Test name
Test status
Simulation time	26004571 ps
CPU time	0.88 seconds
Started	Jan 10 01:18:21 PM PST 24
Finished	Jan 10 01:18:28 PM PST 24
Peak memory	214472 kb
Host	smart-52883749-b7f0-4077-a7b7-cacbe98f1893
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1932069905 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.1932069905
Directory	/workspace/0.edn_intr/latest

Test location	/workspace/coverage/default/0.edn_sec_cm.1160585603
Short name	T59
Test name
Test status
Simulation time	631587435 ps
CPU time	2.87 seconds
Started	Jan 10 01:18:25 PM PST 24
Finished	Jan 10 01:18:36 PM PST 24
Peak memory	232020 kb
Host	smart-00e9cfc5-65ba-4747-94b0-b050b78ab08d
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160585603 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.1160585603
Directory	/workspace/0.edn_sec_cm/latest

Test location	/workspace/coverage/default/0.edn_smoke.1924231273
Short name	T490
Test name
Test status
Simulation time	14989627 ps
CPU time	0.97 seconds
Started	Jan 10 01:18:21 PM PST 24
Finished	Jan 10 01:18:28 PM PST 24
Peak memory	204832 kb
Host	smart-b75a90df-fd76-4b1f-925a-199e35861674
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1924231273 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.1924231273
Directory	/workspace/0.edn_smoke/latest

Test location	/workspace/coverage/default/0.edn_stress_all.2963280224
Short name	T691
Test name
Test status
Simulation time	144821041 ps
CPU time	1.89 seconds
Started	Jan 10 01:18:25 PM PST 24
Finished	Jan 10 01:18:36 PM PST 24
Peak memory	205512 kb
Host	smart-0827df38-f773-4cd4-a46d-04f1a3ddd2db
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963280224 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.2963280224
Directory	/workspace/0.edn_stress_all/latest

Test location	/workspace/coverage/default/0.edn_stress_all_with_rand_reset.3171455227
Short name	T746
Test name
Test status
Simulation time	886986643347 ps
CPU time	2328.27 seconds
Started	Jan 10 01:18:23 PM PST 24
Finished	Jan 10 01:57:20 PM PST 24
Peak memory	232240 kb
Host	smart-13f6287c-9cf2-4016-8512-f1dd1e015e3a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171455227 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.3171455227
Directory	/workspace/0.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.edn_alert.986851715
Short name	T252
Test name
Test status
Simulation time	27855961 ps
CPU time	0.89 seconds
Started	Jan 10 01:18:34 PM PST 24
Finished	Jan 10 01:18:43 PM PST 24
Peak memory	205468 kb
Host	smart-9f5ab551-9674-4e9f-8700-0c65d6c651ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=986851715 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.986851715
Directory	/workspace/1.edn_alert/latest

Test location	/workspace/coverage/default/1.edn_alert_test.3271243479
Short name	T896
Test name
Test status
Simulation time	21580396 ps
CPU time	0.93 seconds
Started	Jan 10 01:18:34 PM PST 24
Finished	Jan 10 01:18:42 PM PST 24
Peak memory	205320 kb
Host	smart-f9dcfd2b-88b3-44d9-803b-e81d2efce6f7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271243479 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.3271243479
Directory	/workspace/1.edn_alert_test/latest

Test location	/workspace/coverage/default/1.edn_err.3873178358
Short name	T180
Test name
Test status
Simulation time	21652190 ps
CPU time	1.03 seconds
Started	Jan 10 01:18:28 PM PST 24
Finished	Jan 10 01:18:37 PM PST 24
Peak memory	221808 kb
Host	smart-955feba8-39b0-4d1f-b3b5-953b55bd09e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3873178358 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.3873178358
Directory	/workspace/1.edn_err/latest

Test location	/workspace/coverage/default/1.edn_genbits.2487925696
Short name	T585
Test name
Test status
Simulation time	66236826 ps
CPU time	1.13 seconds
Started	Jan 10 01:18:33 PM PST 24
Finished	Jan 10 01:18:41 PM PST 24
Peak memory	205604 kb
Host	smart-b85e6551-946c-47d9-a980-93a9a2b86fde
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2487925696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2487925696
Directory	/workspace/1.edn_genbits/latest

Test location	/workspace/coverage/default/1.edn_intr.4213256700
Short name	T945
Test name
Test status
Simulation time	30767469 ps
CPU time	0.84 seconds
Started	Jan 10 01:18:38 PM PST 24
Finished	Jan 10 01:18:45 PM PST 24
Peak memory	214368 kb
Host	smart-e386c211-4a24-4008-9e2c-a3175dcef11f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4213256700 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.4213256700
Directory	/workspace/1.edn_intr/latest

Test location	/workspace/coverage/default/1.edn_regwen.1552196418
Short name	T329
Test name
Test status
Simulation time	44589290 ps
CPU time	0.81 seconds
Started	Jan 10 01:18:25 PM PST 24
Finished	Jan 10 01:18:35 PM PST 24
Peak memory	205076 kb
Host	smart-1655b6f2-ab65-4d6f-a52c-48cc278599ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1552196418 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.1552196418
Directory	/workspace/1.edn_regwen/latest

Test location	/workspace/coverage/default/1.edn_smoke.3168629456
Short name	T641
Test name
Test status
Simulation time	69723633 ps
CPU time	0.84 seconds
Started	Jan 10 01:18:21 PM PST 24
Finished	Jan 10 01:18:28 PM PST 24
Peak memory	205016 kb
Host	smart-359fca4c-6cac-43e1-88a5-c0f691835ebe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3168629456 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.3168629456
Directory	/workspace/1.edn_smoke/latest

Test location	/workspace/coverage/default/1.edn_stress_all.612568892
Short name	T580
Test name
Test status
Simulation time	216353555 ps
CPU time	3.79 seconds
Started	Jan 10 01:18:39 PM PST 24
Finished	Jan 10 01:18:51 PM PST 24
Peak memory	205984 kb
Host	smart-f7ab97ae-74e1-4da3-b166-439321f74942
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612568892 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.612568892
Directory	/workspace/1.edn_stress_all/latest

Test location	/workspace/coverage/default/1.edn_stress_all_with_rand_reset.3189242792
Short name	T267
Test name
Test status
Simulation time	885142839986 ps
CPU time	2438.39 seconds
Started	Jan 10 01:18:32 PM PST 24
Finished	Jan 10 01:59:18 PM PST 24
Peak memory	225648 kb
Host	smart-94221c79-3694-4458-ba4b-0acd5cba029c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189242792 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.3189242792
Directory	/workspace/1.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/10.edn_alert.1268552869
Short name	T315
Test name
Test status
Simulation time	53062295 ps
CPU time	0.87 seconds
Started	Jan 10 01:19:26 PM PST 24
Finished	Jan 10 01:19:39 PM PST 24
Peak memory	205952 kb
Host	smart-d766838d-3019-4c56-b352-4bb336dd591a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1268552869 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.1268552869
Directory	/workspace/10.edn_alert/latest

Test location	/workspace/coverage/default/10.edn_alert_test.2186542688
Short name	T915
Test name
Test status
Simulation time	68892557 ps
CPU time	0.93 seconds
Started	Jan 10 01:19:27 PM PST 24
Finished	Jan 10 01:19:42 PM PST 24
Peak memory	205236 kb
Host	smart-37e16bf3-250e-4a8c-a7d6-7a28a56987c5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186542688 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2186542688
Directory	/workspace/10.edn_alert_test/latest

Test location	/workspace/coverage/default/10.edn_err.1590981618
Short name	T570
Test name
Test status
Simulation time	18901672 ps
CPU time	1.35 seconds
Started	Jan 10 01:19:26 PM PST 24
Finished	Jan 10 01:19:39 PM PST 24
Peak memory	222024 kb
Host	smart-39fc0875-c655-4093-899c-67d588180b58
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1590981618 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.1590981618
Directory	/workspace/10.edn_err/latest

Test location	/workspace/coverage/default/10.edn_intr.3582780338
Short name	T773
Test name
Test status
Simulation time	19067521 ps
CPU time	1.11 seconds
Started	Jan 10 01:19:25 PM PST 24
Finished	Jan 10 01:19:37 PM PST 24
Peak memory	221872 kb
Host	smart-467126fd-03ee-4285-af31-664affb793c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3582780338 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.3582780338
Directory	/workspace/10.edn_intr/latest

Test location	/workspace/coverage/default/10.edn_smoke.1146887052
Short name	T856
Test name
Test status
Simulation time	15413986 ps
CPU time	0.88 seconds
Started	Jan 10 01:19:26 PM PST 24
Finished	Jan 10 01:19:37 PM PST 24
Peak memory	204864 kb
Host	smart-46c2d9dc-7d05-4e5d-8820-65808b82cc09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1146887052 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1146887052
Directory	/workspace/10.edn_smoke/latest

Test location	/workspace/coverage/default/10.edn_stress_all.2056287264
Short name	T852
Test name
Test status
Simulation time	667764945 ps
CPU time	3.63 seconds
Started	Jan 10 01:19:26 PM PST 24
Finished	Jan 10 01:19:41 PM PST 24
Peak memory	214304 kb
Host	smart-5acb5653-4332-4878-8489-6f9ae7a43a6b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056287264 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.2056287264
Directory	/workspace/10.edn_stress_all/latest

Test location	/workspace/coverage/default/10.edn_stress_all_with_rand_reset.2024427329
Short name	T587
Test name
Test status
Simulation time	10516368738 ps
CPU time	255.71 seconds
Started	Jan 10 01:19:10 PM PST 24
Finished	Jan 10 01:23:30 PM PST 24
Peak memory	215296 kb
Host	smart-06e47c52-6822-492f-a659-663b88f6dae0
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024427329 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.2024427329
Directory	/workspace/10.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/101.edn_genbits.3692698567
Short name	T643
Test name
Test status
Simulation time	77147223 ps
CPU time	1.13 seconds
Started	Jan 10 01:20:48 PM PST 24
Finished	Jan 10 01:20:55 PM PST 24
Peak memory	214404 kb
Host	smart-956ee781-aa14-4ee2-bedf-f62e6612d14b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3692698567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.3692698567
Directory	/workspace/101.edn_genbits/latest

Test location	/workspace/coverage/default/104.edn_genbits.3495001804
Short name	T530
Test name
Test status
Simulation time	34565800 ps
CPU time	0.96 seconds
Started	Jan 10 01:20:31 PM PST 24
Finished	Jan 10 01:20:40 PM PST 24
Peak memory	205568 kb
Host	smart-e6a5e2fc-e8e1-4f45-887c-2bc6aa119e83
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3495001804 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.3495001804
Directory	/workspace/104.edn_genbits/latest

Test location	/workspace/coverage/default/105.edn_genbits.1398251119
Short name	T878
Test name
Test status
Simulation time	145943671 ps
CPU time	2.56 seconds
Started	Jan 10 01:20:31 PM PST 24
Finished	Jan 10 01:20:42 PM PST 24
Peak memory	214340 kb
Host	smart-8a7119ec-32f1-4596-bf42-4e597964ca09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1398251119 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.1398251119
Directory	/workspace/105.edn_genbits/latest

Test location	/workspace/coverage/default/106.edn_genbits.2978231283
Short name	T558
Test name
Test status
Simulation time	36288865 ps
CPU time	1.04 seconds
Started	Jan 10 01:20:31 PM PST 24
Finished	Jan 10 01:20:41 PM PST 24
Peak memory	214288 kb
Host	smart-90e301df-b016-4a06-b07a-23ce973f86d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2978231283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.2978231283
Directory	/workspace/106.edn_genbits/latest

Test location	/workspace/coverage/default/107.edn_genbits.3092062463
Short name	T636
Test name
Test status
Simulation time	28052827 ps
CPU time	1.33 seconds
Started	Jan 10 01:20:29 PM PST 24
Finished	Jan 10 01:20:38 PM PST 24
Peak memory	214284 kb
Host	smart-8ae98d0d-ebdf-479c-9371-807acfd29d2b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3092062463 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.3092062463
Directory	/workspace/107.edn_genbits/latest

Test location	/workspace/coverage/default/108.edn_genbits.3272353261
Short name	T784
Test name
Test status
Simulation time	20798193 ps
CPU time	0.94 seconds
Started	Jan 10 01:20:47 PM PST 24
Finished	Jan 10 01:20:53 PM PST 24
Peak memory	205520 kb
Host	smart-9f4920b9-5977-4e11-a438-17e97aafa17e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3272353261 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.3272353261
Directory	/workspace/108.edn_genbits/latest

Test location	/workspace/coverage/default/109.edn_genbits.1145804321
Short name	T963
Test name
Test status
Simulation time	52663614 ps
CPU time	1.01 seconds
Started	Jan 10 01:20:51 PM PST 24
Finished	Jan 10 01:20:57 PM PST 24
Peak memory	214252 kb
Host	smart-5ba08cd3-d016-417d-b88d-ecf9834a3e79
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1145804321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.1145804321
Directory	/workspace/109.edn_genbits/latest

Test location	/workspace/coverage/default/11.edn_alert.3906162889
Short name	T879
Test name
Test status
Simulation time	149243523 ps
CPU time	0.9 seconds
Started	Jan 10 01:19:19 PM PST 24
Finished	Jan 10 01:19:24 PM PST 24
Peak memory	205224 kb
Host	smart-5afeae31-cc92-43a2-86dc-feedf83861b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3906162889 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.3906162889
Directory	/workspace/11.edn_alert/latest

Test location	/workspace/coverage/default/11.edn_alert_test.2422043895
Short name	T474
Test name
Test status
Simulation time	95570395 ps
CPU time	0.83 seconds
Started	Jan 10 01:19:20 PM PST 24
Finished	Jan 10 01:19:25 PM PST 24
Peak memory	205256 kb
Host	smart-58e0f40d-bf47-4a3a-8bff-fafc1a15145b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422043895 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.2422043895
Directory	/workspace/11.edn_alert_test/latest

Test location	/workspace/coverage/default/11.edn_disable.2286419498
Short name	T175
Test name
Test status
Simulation time	24267907 ps
CPU time	0.82 seconds
Started	Jan 10 01:19:08 PM PST 24
Finished	Jan 10 01:19:11 PM PST 24
Peak memory	214304 kb
Host	smart-edc23253-8f1d-41ee-a3c7-9d1ba62ee369
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286419498 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.2286419498
Directory	/workspace/11.edn_disable/latest

Test location	/workspace/coverage/default/11.edn_disable_auto_req_mode.1824764840
Short name	T599
Test name
Test status
Simulation time	79048023 ps
CPU time	1.08 seconds
Started	Jan 10 01:19:09 PM PST 24
Finished	Jan 10 01:19:14 PM PST 24
Peak memory	214676 kb
Host	smart-27149eeb-5ccc-4096-b227-bab58d149f96
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824764840 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d isable_auto_req_mode.1824764840
Directory	/workspace/11.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/11.edn_err.1434361169
Short name	T160
Test name
Test status
Simulation time	38467558 ps
CPU time	0.96 seconds
Started	Jan 10 01:19:27 PM PST 24
Finished	Jan 10 01:19:42 PM PST 24
Peak memory	221732 kb
Host	smart-1a56a62d-95d1-4755-9825-bd300e20c40b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1434361169 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.1434361169
Directory	/workspace/11.edn_err/latest

Test location	/workspace/coverage/default/11.edn_genbits.1256239715
Short name	T29
Test name
Test status
Simulation time	16738391 ps
CPU time	1.06 seconds
Started	Jan 10 01:19:19 PM PST 24
Finished	Jan 10 01:19:23 PM PST 24
Peak memory	205276 kb
Host	smart-5fd2bbf5-e4c7-4f81-975c-9bd565aece3c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1256239715 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1256239715
Directory	/workspace/11.edn_genbits/latest

Test location	/workspace/coverage/default/11.edn_intr.540697656
Short name	T99
Test name
Test status
Simulation time	62772425 ps
CPU time	0.77 seconds
Started	Jan 10 01:19:14 PM PST 24
Finished	Jan 10 01:19:18 PM PST 24
Peak memory	214488 kb
Host	smart-94b42536-f29b-42dc-a8b9-25cf386d58ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=540697656 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.540697656
Directory	/workspace/11.edn_intr/latest

Test location	/workspace/coverage/default/11.edn_smoke.113340014
Short name	T62
Test name
Test status
Simulation time	47868181 ps
CPU time	0.84 seconds
Started	Jan 10 01:19:29 PM PST 24
Finished	Jan 10 01:19:45 PM PST 24
Peak memory	204928 kb
Host	smart-23a04b46-080d-4393-9132-b5ceeb03ce9b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=113340014 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.113340014
Directory	/workspace/11.edn_smoke/latest

Test location	/workspace/coverage/default/11.edn_stress_all.3517396803
Short name	T464
Test name
Test status
Simulation time	354926619 ps
CPU time	2.36 seconds
Started	Jan 10 01:19:10 PM PST 24
Finished	Jan 10 01:19:16 PM PST 24
Peak memory	206120 kb
Host	smart-aed12ec2-e8d4-4345-b872-44f97de43d92
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517396803 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.3517396803
Directory	/workspace/11.edn_stress_all/latest

Test location	/workspace/coverage/default/11.edn_stress_all_with_rand_reset.721196661
Short name	T916
Test name
Test status
Simulation time	37090093219 ps
CPU time	936.57 seconds
Started	Jan 10 01:19:09 PM PST 24
Finished	Jan 10 01:34:47 PM PST 24
Peak memory	215472 kb
Host	smart-628f34d6-5e20-41cd-b75c-b1bde1bc0fcc
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721196661 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.721196661
Directory	/workspace/11.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/110.edn_genbits.2003695732
Short name	T86
Test name
Test status
Simulation time	18098748 ps
CPU time	0.98 seconds
Started	Jan 10 01:20:33 PM PST 24
Finished	Jan 10 01:20:42 PM PST 24
Peak memory	205156 kb
Host	smart-060d87be-97b0-46bd-bb72-eacd29039a12
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2003695732 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2003695732
Directory	/workspace/110.edn_genbits/latest

Test location	/workspace/coverage/default/111.edn_genbits.286983776
Short name	T303
Test name
Test status
Simulation time	27298261 ps
CPU time	0.96 seconds
Started	Jan 10 01:20:48 PM PST 24
Finished	Jan 10 01:20:54 PM PST 24
Peak memory	205244 kb
Host	smart-df90c6c1-f634-4c0d-9434-497d45450aa2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=286983776 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.286983776
Directory	/workspace/111.edn_genbits/latest

Test location	/workspace/coverage/default/113.edn_genbits.4237251449
Short name	T721
Test name
Test status
Simulation time	29098714 ps
CPU time	0.88 seconds
Started	Jan 10 01:20:28 PM PST 24
Finished	Jan 10 01:20:38 PM PST 24
Peak memory	205264 kb
Host	smart-6d8d5f5a-fc42-45a5-a029-1f3180476e41
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4237251449 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.4237251449
Directory	/workspace/113.edn_genbits/latest

Test location	/workspace/coverage/default/114.edn_genbits.1290961610
Short name	T697
Test name
Test status
Simulation time	135107615 ps
CPU time	3.04 seconds
Started	Jan 10 01:20:48 PM PST 24
Finished	Jan 10 01:20:57 PM PST 24
Peak memory	214292 kb
Host	smart-3c5963d8-301f-4df2-9a44-34fa5842f600
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1290961610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.1290961610
Directory	/workspace/114.edn_genbits/latest

Test location	/workspace/coverage/default/115.edn_genbits.48946574
Short name	T960
Test name
Test status
Simulation time	50696948 ps
CPU time	1.15 seconds
Started	Jan 10 01:20:35 PM PST 24
Finished	Jan 10 01:20:45 PM PST 24
Peak memory	205628 kb
Host	smart-c25df964-1d3c-43f8-8151-9db3f04fd2d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=48946574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.48946574
Directory	/workspace/115.edn_genbits/latest

Test location	/workspace/coverage/default/116.edn_genbits.2157233834
Short name	T772
Test name
Test status
Simulation time	18439626 ps
CPU time	1.01 seconds
Started	Jan 10 01:20:31 PM PST 24
Finished	Jan 10 01:20:40 PM PST 24
Peak memory	205332 kb
Host	smart-9f86acf5-73eb-4aaf-9470-c64b3297ceb9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2157233834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.2157233834
Directory	/workspace/116.edn_genbits/latest

Test location	/workspace/coverage/default/117.edn_genbits.111574069
Short name	T725
Test name
Test status
Simulation time	26427418 ps
CPU time	1.15 seconds
Started	Jan 10 01:20:29 PM PST 24
Finished	Jan 10 01:20:38 PM PST 24
Peak memory	205668 kb
Host	smart-12bbd063-a368-44c7-89a2-7ecf4f10650e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=111574069 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.111574069
Directory	/workspace/117.edn_genbits/latest

Test location	/workspace/coverage/default/118.edn_genbits.2725037811
Short name	T508
Test name
Test status
Simulation time	17239283 ps
CPU time	0.99 seconds
Started	Jan 10 01:20:32 PM PST 24
Finished	Jan 10 01:20:41 PM PST 24
Peak memory	205468 kb
Host	smart-6b77b3b6-0c68-4bf5-952d-155ac281950e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2725037811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.2725037811
Directory	/workspace/118.edn_genbits/latest

Test location	/workspace/coverage/default/119.edn_genbits.3852355224
Short name	T672
Test name
Test status
Simulation time	54011550 ps
CPU time	0.86 seconds
Started	Jan 10 01:20:33 PM PST 24
Finished	Jan 10 01:20:42 PM PST 24
Peak memory	205168 kb
Host	smart-521fb6e3-9628-42bb-9782-129714765508
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3852355224 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3852355224
Directory	/workspace/119.edn_genbits/latest

Test location	/workspace/coverage/default/12.edn_alert_test.3018974889
Short name	T798
Test name
Test status
Simulation time	67115735 ps
CPU time	0.87 seconds
Started	Jan 10 01:19:22 PM PST 24
Finished	Jan 10 01:19:32 PM PST 24
Peak memory	204744 kb
Host	smart-0abbfe2a-4966-4de7-8acc-068df45f9990
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018974889 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.3018974889
Directory	/workspace/12.edn_alert_test/latest

Test location	/workspace/coverage/default/12.edn_err.3105987116
Short name	T647
Test name
Test status
Simulation time	76705217 ps
CPU time	1.08 seconds
Started	Jan 10 01:19:19 PM PST 24
Finished	Jan 10 01:19:23 PM PST 24
Peak memory	221724 kb
Host	smart-d11789aa-85eb-4ef9-9a65-0cdc17e36e88
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3105987116 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.3105987116
Directory	/workspace/12.edn_err/latest

Test location	/workspace/coverage/default/12.edn_smoke.508933229
Short name	T646
Test name
Test status
Simulation time	23044838 ps
CPU time	0.76 seconds
Started	Jan 10 01:19:14 PM PST 24
Finished	Jan 10 01:19:18 PM PST 24
Peak memory	204496 kb
Host	smart-a1537688-e9de-4c00-985c-01057e6d1105
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=508933229 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.508933229
Directory	/workspace/12.edn_smoke/latest

Test location	/workspace/coverage/default/12.edn_stress_all.2539165230
Short name	T473
Test name
Test status
Simulation time	155004330 ps
CPU time	3.21 seconds
Started	Jan 10 01:19:10 PM PST 24
Finished	Jan 10 01:19:18 PM PST 24
Peak memory	206136 kb
Host	smart-d9bee521-93d6-40fa-9e4e-6cc4c32cee5b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539165230 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.2539165230
Directory	/workspace/12.edn_stress_all/latest

Test location	/workspace/coverage/default/120.edn_genbits.4194668712
Short name	T528
Test name
Test status
Simulation time	23587326 ps
CPU time	0.92 seconds
Started	Jan 10 01:20:50 PM PST 24
Finished	Jan 10 01:20:57 PM PST 24
Peak memory	205320 kb
Host	smart-ae7eae28-6dad-46c7-8784-8546661b9d34
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4194668712 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.4194668712
Directory	/workspace/120.edn_genbits/latest

Test location	/workspace/coverage/default/121.edn_genbits.624346623
Short name	T851
Test name
Test status
Simulation time	96181848 ps
CPU time	2.5 seconds
Started	Jan 10 01:20:31 PM PST 24
Finished	Jan 10 01:20:41 PM PST 24
Peak memory	214368 kb
Host	smart-2be66e25-8c04-4e9a-83ca-a23ef33f94ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=624346623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.624346623
Directory	/workspace/121.edn_genbits/latest

Test location	/workspace/coverage/default/122.edn_genbits.584655067
Short name	T669
Test name
Test status
Simulation time	21135233 ps
CPU time	1.06 seconds
Started	Jan 10 01:20:49 PM PST 24
Finished	Jan 10 01:20:56 PM PST 24
Peak memory	205688 kb
Host	smart-0dc455df-87ee-4006-9a00-533ddf84daa7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=584655067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.584655067
Directory	/workspace/122.edn_genbits/latest

Test location	/workspace/coverage/default/123.edn_genbits.1723848743
Short name	T486
Test name
Test status
Simulation time	16606916 ps
CPU time	1.06 seconds
Started	Jan 10 01:20:49 PM PST 24
Finished	Jan 10 01:20:55 PM PST 24
Peak memory	205292 kb
Host	smart-279b5e20-1735-44ba-bfd4-8412df572e67
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1723848743 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.1723848743
Directory	/workspace/123.edn_genbits/latest

Test location	/workspace/coverage/default/124.edn_genbits.2032683105
Short name	T341
Test name
Test status
Simulation time	71713257 ps
CPU time	1.19 seconds
Started	Jan 10 01:20:30 PM PST 24
Finished	Jan 10 01:20:39 PM PST 24
Peak memory	205532 kb
Host	smart-726d4dc4-8c81-49ed-8b94-312e9a91f1d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2032683105 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.2032683105
Directory	/workspace/124.edn_genbits/latest

Test location	/workspace/coverage/default/125.edn_genbits.2841978572
Short name	T559
Test name
Test status
Simulation time	18216808 ps
CPU time	0.99 seconds
Started	Jan 10 01:20:33 PM PST 24
Finished	Jan 10 01:20:43 PM PST 24
Peak memory	205332 kb
Host	smart-33383550-0321-4406-bff8-c5a57846572b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2841978572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.2841978572
Directory	/workspace/125.edn_genbits/latest

Test location	/workspace/coverage/default/126.edn_genbits.1871178882
Short name	T701
Test name
Test status
Simulation time	22739179 ps
CPU time	0.93 seconds
Started	Jan 10 01:20:35 PM PST 24
Finished	Jan 10 01:20:45 PM PST 24
Peak memory	205172 kb
Host	smart-6110ba99-53bc-41c4-8dbf-d75a236a0cca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1871178882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.1871178882
Directory	/workspace/126.edn_genbits/latest

Test location	/workspace/coverage/default/127.edn_genbits.457186026
Short name	T737
Test name
Test status
Simulation time	21464762 ps
CPU time	1.07 seconds
Started	Jan 10 01:20:31 PM PST 24
Finished	Jan 10 01:20:40 PM PST 24
Peak memory	205688 kb
Host	smart-46ea1989-ef32-4952-98a2-cd2c1bc3821e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=457186026 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.457186026
Directory	/workspace/127.edn_genbits/latest

Test location	/workspace/coverage/default/13.edn_alert.3410600139
Short name	T325
Test name
Test status
Simulation time	53186153 ps
CPU time	0.93 seconds
Started	Jan 10 01:19:20 PM PST 24
Finished	Jan 10 01:19:25 PM PST 24
Peak memory	205372 kb
Host	smart-c0da7d7b-11c2-42d5-bfca-5ae6d24d132a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3410600139 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.3410600139
Directory	/workspace/13.edn_alert/latest

Test location	/workspace/coverage/default/13.edn_alert_test.828566561
Short name	T500
Test name
Test status
Simulation time	35414624 ps
CPU time	0.81 seconds
Started	Jan 10 01:19:23 PM PST 24
Finished	Jan 10 01:19:33 PM PST 24
Peak memory	204472 kb
Host	smart-256d90f9-14f1-4cbb-8ff6-28fd5aebbfc0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828566561 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.828566561
Directory	/workspace/13.edn_alert_test/latest

Test location	/workspace/coverage/default/13.edn_disable.3245546013
Short name	T169
Test name
Test status
Simulation time	10445674 ps
CPU time	0.82 seconds
Started	Jan 10 01:19:22 PM PST 24
Finished	Jan 10 01:19:30 PM PST 24
Peak memory	214352 kb
Host	smart-e858f326-1199-42d9-82c3-7924b2d9cfe9
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245546013 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.3245546013
Directory	/workspace/13.edn_disable/latest

Test location	/workspace/coverage/default/13.edn_err.1126096178
Short name	T143
Test name
Test status
Simulation time	24511494 ps
CPU time	1.11 seconds
Started	Jan 10 01:19:21 PM PST 24
Finished	Jan 10 01:19:27 PM PST 24
Peak memory	214852 kb
Host	smart-026ead44-c639-4b10-923a-38e1a217f228
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1126096178 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.1126096178
Directory	/workspace/13.edn_err/latest

Test location	/workspace/coverage/default/13.edn_genbits.3532960243
Short name	T938
Test name
Test status
Simulation time	46363333 ps
CPU time	0.88 seconds
Started	Jan 10 01:19:23 PM PST 24
Finished	Jan 10 01:19:34 PM PST 24
Peak memory	205052 kb
Host	smart-b2d50c06-afc2-44bf-8831-2459a126f67c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3532960243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.3532960243
Directory	/workspace/13.edn_genbits/latest

Test location	/workspace/coverage/default/13.edn_intr.3578626706
Short name	T914
Test name
Test status
Simulation time	27192079 ps
CPU time	1.01 seconds
Started	Jan 10 01:19:24 PM PST 24
Finished	Jan 10 01:19:35 PM PST 24
Peak memory	221428 kb
Host	smart-b598403d-8381-4f04-8017-c15dce82731b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3578626706 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.3578626706
Directory	/workspace/13.edn_intr/latest

Test location	/workspace/coverage/default/13.edn_smoke.2756099203
Short name	T757
Test name
Test status
Simulation time	43435446 ps
CPU time	0.85 seconds
Started	Jan 10 01:19:19 PM PST 24
Finished	Jan 10 01:19:23 PM PST 24
Peak memory	205080 kb
Host	smart-b18e4313-96e0-470e-bec4-136de0623dc5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2756099203 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.2756099203
Directory	/workspace/13.edn_smoke/latest

Test location	/workspace/coverage/default/13.edn_stress_all.3502727615
Short name	T950
Test name
Test status
Simulation time	258619706 ps
CPU time	3.32 seconds
Started	Jan 10 01:19:21 PM PST 24
Finished	Jan 10 01:19:31 PM PST 24
Peak memory	206076 kb
Host	smart-4d87d371-43dc-4fae-9b6c-662da816d170
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502727615 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.3502727615
Directory	/workspace/13.edn_stress_all/latest

Test location	/workspace/coverage/default/13.edn_stress_all_with_rand_reset.447014122
Short name	T846
Test name
Test status
Simulation time	62517184403 ps
CPU time	510.8 seconds
Started	Jan 10 01:19:23 PM PST 24
Finished	Jan 10 01:28:03 PM PST 24
Peak memory	215364 kb
Host	smart-2c257090-4e5d-4653-b06d-ca28a3fb1d60
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447014122 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.447014122
Directory	/workspace/13.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/130.edn_genbits.1423439994
Short name	T269
Test name
Test status
Simulation time	17078422 ps
CPU time	1.1 seconds
Started	Jan 10 01:21:12 PM PST 24
Finished	Jan 10 01:21:16 PM PST 24
Peak memory	205392 kb
Host	smart-e7508995-f22a-4d5b-970b-5e10acdd61c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1423439994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1423439994
Directory	/workspace/130.edn_genbits/latest

Test location	/workspace/coverage/default/131.edn_genbits.364827245
Short name	T731
Test name
Test status
Simulation time	77391328 ps
CPU time	1.1 seconds
Started	Jan 10 01:20:46 PM PST 24
Finished	Jan 10 01:20:53 PM PST 24
Peak memory	214280 kb
Host	smart-7896f029-804c-4f1b-b050-eebced24943a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=364827245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.364827245
Directory	/workspace/131.edn_genbits/latest

Test location	/workspace/coverage/default/132.edn_genbits.1905905086
Short name	T578
Test name
Test status
Simulation time	25918909 ps
CPU time	0.97 seconds
Started	Jan 10 01:20:47 PM PST 24
Finished	Jan 10 01:20:53 PM PST 24
Peak memory	205348 kb
Host	smart-0a0670bf-6f7f-4aaa-ad22-1c812cedda39
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1905905086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.1905905086
Directory	/workspace/132.edn_genbits/latest

Test location	/workspace/coverage/default/133.edn_genbits.3613133305
Short name	T869
Test name
Test status
Simulation time	16429406 ps
CPU time	0.96 seconds
Started	Jan 10 01:20:34 PM PST 24
Finished	Jan 10 01:20:44 PM PST 24
Peak memory	205100 kb
Host	smart-b87d59e2-fae0-4a99-a21c-3c4a593c9966
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3613133305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.3613133305
Directory	/workspace/133.edn_genbits/latest

Test location	/workspace/coverage/default/134.edn_genbits.418894177
Short name	T339
Test name
Test status
Simulation time	95365822 ps
CPU time	0.99 seconds
Started	Jan 10 01:20:31 PM PST 24
Finished	Jan 10 01:20:40 PM PST 24
Peak memory	205756 kb
Host	smart-6ae6b096-dc07-4483-97f5-a765ffaf2492
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=418894177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.418894177
Directory	/workspace/134.edn_genbits/latest

Test location	/workspace/coverage/default/135.edn_genbits.3531576717
Short name	T342
Test name
Test status
Simulation time	21104920 ps
CPU time	1.02 seconds
Started	Jan 10 01:20:29 PM PST 24
Finished	Jan 10 01:20:38 PM PST 24
Peak memory	205368 kb
Host	smart-88ab34c8-a42e-49e9-b464-87a71a9d282d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3531576717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.3531576717
Directory	/workspace/135.edn_genbits/latest

Test location	/workspace/coverage/default/136.edn_genbits.4170292632
Short name	T763
Test name
Test status
Simulation time	19161826 ps
CPU time	1 seconds
Started	Jan 10 01:20:46 PM PST 24
Finished	Jan 10 01:20:52 PM PST 24
Peak memory	205784 kb
Host	smart-37dc5aac-95c8-49ce-ae05-6eac819b4241
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4170292632 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.4170292632
Directory	/workspace/136.edn_genbits/latest

Test location	/workspace/coverage/default/137.edn_genbits.694484921
Short name	T800
Test name
Test status
Simulation time	33540560 ps
CPU time	0.96 seconds
Started	Jan 10 01:21:07 PM PST 24
Finished	Jan 10 01:21:12 PM PST 24
Peak memory	205268 kb
Host	smart-bbf14400-cbb6-4c60-ad5b-317e75394697
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=694484921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.694484921
Directory	/workspace/137.edn_genbits/latest

Test location	/workspace/coverage/default/138.edn_genbits.1123375919
Short name	T847
Test name
Test status
Simulation time	67157861 ps
CPU time	1.03 seconds
Started	Jan 10 01:20:34 PM PST 24
Finished	Jan 10 01:20:44 PM PST 24
Peak memory	214388 kb
Host	smart-f8057017-2bd8-4e83-9c13-9ffe21eb9d2e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1123375919 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.1123375919
Directory	/workspace/138.edn_genbits/latest

Test location	/workspace/coverage/default/14.edn_alert.472660549
Short name	T249
Test name
Test status
Simulation time	17870857 ps
CPU time	0.95 seconds
Started	Jan 10 01:19:23 PM PST 24
Finished	Jan 10 01:19:34 PM PST 24
Peak memory	205288 kb
Host	smart-8510a67b-efc6-4cfa-837a-43f3698e5f61
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=472660549 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.472660549
Directory	/workspace/14.edn_alert/latest

Test location	/workspace/coverage/default/14.edn_alert_test.1315569777
Short name	T626
Test name
Test status
Simulation time	22741599 ps
CPU time	0.8 seconds
Started	Jan 10 01:19:24 PM PST 24
Finished	Jan 10 01:19:36 PM PST 24
Peak memory	204376 kb
Host	smart-9b8b4e37-12ad-40d9-bdc9-ef952f136f78
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315569777 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.1315569777
Directory	/workspace/14.edn_alert_test/latest

Test location	/workspace/coverage/default/14.edn_disable.2703191710
Short name	T132
Test name
Test status
Simulation time	14542628 ps
CPU time	0.88 seconds
Started	Jan 10 01:19:26 PM PST 24
Finished	Jan 10 01:19:38 PM PST 24
Peak memory	214652 kb
Host	smart-6337d220-ebf3-4f30-a35a-947eeba6f678
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703191710 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.2703191710
Directory	/workspace/14.edn_disable/latest

Test location	/workspace/coverage/default/14.edn_err.1883567624
Short name	T886
Test name
Test status
Simulation time	24636709 ps
CPU time	0.96 seconds
Started	Jan 10 01:19:25 PM PST 24
Finished	Jan 10 01:19:37 PM PST 24
Peak memory	215900 kb
Host	smart-2686ef09-3151-4368-9da9-ad045b814576
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1883567624 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.1883567624
Directory	/workspace/14.edn_err/latest

Test location	/workspace/coverage/default/14.edn_genbits.3797739988
Short name	T624
Test name
Test status
Simulation time	79342348 ps
CPU time	0.84 seconds
Started	Jan 10 01:19:24 PM PST 24
Finished	Jan 10 01:19:34 PM PST 24
Peak memory	204988 kb
Host	smart-fd4d34d2-0c25-43eb-ad7b-0896fcaf7719
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3797739988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.3797739988
Directory	/workspace/14.edn_genbits/latest

Test location	/workspace/coverage/default/14.edn_intr.1249477679
Short name	T964
Test name
Test status
Simulation time	25344266 ps
CPU time	0.93 seconds
Started	Jan 10 01:19:26 PM PST 24
Finished	Jan 10 01:19:38 PM PST 24
Peak memory	214400 kb
Host	smart-347a23e7-6b88-4df8-9088-95f1ce051403
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1249477679 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.1249477679
Directory	/workspace/14.edn_intr/latest

Test location	/workspace/coverage/default/14.edn_smoke.1452169173
Short name	T674
Test name
Test status
Simulation time	15061484 ps
CPU time	0.88 seconds
Started	Jan 10 01:19:26 PM PST 24
Finished	Jan 10 01:19:39 PM PST 24
Peak memory	204636 kb
Host	smart-b2c3c457-d3eb-49cc-b662-1efb6da3d582
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1452169173 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.1452169173
Directory	/workspace/14.edn_smoke/latest

Test location	/workspace/coverage/default/14.edn_stress_all.1594820824
Short name	T103
Test name
Test status
Simulation time	348091950 ps
CPU time	2.95 seconds
Started	Jan 10 01:19:23 PM PST 24
Finished	Jan 10 01:19:36 PM PST 24
Peak memory	205964 kb
Host	smart-f7be8921-c236-4778-a3b6-1cd7c7230824
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594820824 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.1594820824
Directory	/workspace/14.edn_stress_all/latest

Test location	/workspace/coverage/default/14.edn_stress_all_with_rand_reset.901116577
Short name	T547
Test name
Test status
Simulation time	94721077859 ps
CPU time	566.12 seconds
Started	Jan 10 01:19:25 PM PST 24
Finished	Jan 10 01:29:02 PM PST 24
Peak memory	216184 kb
Host	smart-2c0d2467-752a-4628-80d8-83ccdcf0f9f6
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901116577 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.901116577
Directory	/workspace/14.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/140.edn_genbits.1456667250
Short name	T831
Test name
Test status
Simulation time	209034277 ps
CPU time	2.54 seconds
Started	Jan 10 01:20:29 PM PST 24
Finished	Jan 10 01:20:40 PM PST 24
Peak memory	214332 kb
Host	smart-cf940ebf-e3eb-49e1-a06b-012a45c53023
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1456667250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.1456667250
Directory	/workspace/140.edn_genbits/latest

Test location	/workspace/coverage/default/141.edn_genbits.2431888743
Short name	T694
Test name
Test status
Simulation time	30707894 ps
CPU time	1.07 seconds
Started	Jan 10 01:21:32 PM PST 24
Finished	Jan 10 01:21:52 PM PST 24
Peak memory	214364 kb
Host	smart-3181e617-9304-4893-bd91-142c587a9b3f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2431888743 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.2431888743
Directory	/workspace/141.edn_genbits/latest

Test location	/workspace/coverage/default/142.edn_genbits.1760047660
Short name	T796
Test name
Test status
Simulation time	106521064 ps
CPU time	0.9 seconds
Started	Jan 10 01:20:48 PM PST 24
Finished	Jan 10 01:20:55 PM PST 24
Peak memory	205284 kb
Host	smart-f1143e7b-bf9c-4649-819c-2a8dbe07df3a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1760047660 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.1760047660
Directory	/workspace/142.edn_genbits/latest

Test location	/workspace/coverage/default/143.edn_genbits.2619319187
Short name	T870
Test name
Test status
Simulation time	18076288 ps
CPU time	0.94 seconds
Started	Jan 10 01:20:49 PM PST 24
Finished	Jan 10 01:20:55 PM PST 24
Peak memory	205176 kb
Host	smart-219b37a7-7760-4052-8a10-365c52905c8b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2619319187 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.2619319187
Directory	/workspace/143.edn_genbits/latest

Test location	/workspace/coverage/default/144.edn_genbits.4134757418
Short name	T37
Test name
Test status
Simulation time	81677099 ps
CPU time	2.12 seconds
Started	Jan 10 01:20:33 PM PST 24
Finished	Jan 10 01:20:44 PM PST 24
Peak memory	214180 kb
Host	smart-514c09bf-1a31-4d6f-81c5-0ebc1e678ffa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4134757418 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.4134757418
Directory	/workspace/144.edn_genbits/latest

Test location	/workspace/coverage/default/145.edn_genbits.1502444136
Short name	T289
Test name
Test status
Simulation time	45437828 ps
CPU time	1.15 seconds
Started	Jan 10 01:20:50 PM PST 24
Finished	Jan 10 01:20:56 PM PST 24
Peak memory	214384 kb
Host	smart-1ef9ed43-7fba-423b-99af-10d5710b8bd4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1502444136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.1502444136
Directory	/workspace/145.edn_genbits/latest

Test location	/workspace/coverage/default/147.edn_genbits.1685594836
Short name	T346
Test name
Test status
Simulation time	97432774 ps
CPU time	2.39 seconds
Started	Jan 10 01:20:33 PM PST 24
Finished	Jan 10 01:20:44 PM PST 24
Peak memory	214388 kb
Host	smart-587ffb06-1cd8-416f-953a-7ab4f086549e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1685594836 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.1685594836
Directory	/workspace/147.edn_genbits/latest

Test location	/workspace/coverage/default/148.edn_genbits.2655345866
Short name	T821
Test name
Test status
Simulation time	20015785 ps
CPU time	0.98 seconds
Started	Jan 10 01:20:36 PM PST 24
Finished	Jan 10 01:20:46 PM PST 24
Peak memory	205684 kb
Host	smart-d5ae6846-0751-4be9-af62-a784069a8274
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2655345866 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.2655345866
Directory	/workspace/148.edn_genbits/latest

Test location	/workspace/coverage/default/149.edn_genbits.1582616149
Short name	T764
Test name
Test status
Simulation time	14025170 ps
CPU time	0.95 seconds
Started	Jan 10 01:20:49 PM PST 24
Finished	Jan 10 01:20:56 PM PST 24
Peak memory	205464 kb
Host	smart-29b33b7d-5517-4c97-9a53-e70bfc53f9bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1582616149 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.1582616149
Directory	/workspace/149.edn_genbits/latest

Test location	/workspace/coverage/default/15.edn_alert.847104668
Short name	T970
Test name
Test status
Simulation time	21379458 ps
CPU time	1.03 seconds
Started	Jan 10 01:19:30 PM PST 24
Finished	Jan 10 01:19:47 PM PST 24
Peak memory	205284 kb
Host	smart-7b71e88d-5839-4299-9f89-e10c14318110
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=847104668 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.847104668
Directory	/workspace/15.edn_alert/latest

Test location	/workspace/coverage/default/15.edn_alert_test.1837552420
Short name	T665
Test name
Test status
Simulation time	48152315 ps
CPU time	0.89 seconds
Started	Jan 10 01:19:27 PM PST 24
Finished	Jan 10 01:19:42 PM PST 24
Peak memory	204824 kb
Host	smart-b1adedb2-e664-40dd-948a-1c677d64b962
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837552420 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.1837552420
Directory	/workspace/15.edn_alert_test/latest

Test location	/workspace/coverage/default/15.edn_disable.635543460
Short name	T131
Test name
Test status
Simulation time	20206866 ps
CPU time	0.8 seconds
Started	Jan 10 01:19:26 PM PST 24
Finished	Jan 10 01:19:39 PM PST 24
Peak memory	214340 kb
Host	smart-08609f2b-1221-4d5f-82e0-b6c005b7d722
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635543460 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.635543460
Directory	/workspace/15.edn_disable/latest

Test location	/workspace/coverage/default/15.edn_disable_auto_req_mode.3211636282
Short name	T805
Test name
Test status
Simulation time	206765441 ps
CPU time	1.04 seconds
Started	Jan 10 01:19:27 PM PST 24
Finished	Jan 10 01:19:42 PM PST 24
Peak memory	206500 kb
Host	smart-c0b9d804-0468-4578-8035-e20578735fcd
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211636282 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d isable_auto_req_mode.3211636282
Directory	/workspace/15.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/15.edn_err.3578370642
Short name	T826
Test name
Test status
Simulation time	33023196 ps
CPU time	0.8 seconds
Started	Jan 10 01:19:29 PM PST 24
Finished	Jan 10 01:19:45 PM PST 24
Peak memory	215696 kb
Host	smart-6fe5ecab-3546-47d3-a582-feb08bdefdad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3578370642 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.3578370642
Directory	/workspace/15.edn_err/latest

Test location	/workspace/coverage/default/15.edn_genbits.1300276801
Short name	T904
Test name
Test status
Simulation time	119638453 ps
CPU time	2.41 seconds
Started	Jan 10 01:19:24 PM PST 24
Finished	Jan 10 01:19:38 PM PST 24
Peak memory	214244 kb
Host	smart-619de536-f0f1-4c3e-a660-d00ea218b9a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1300276801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.1300276801
Directory	/workspace/15.edn_genbits/latest

Test location	/workspace/coverage/default/15.edn_smoke.2575742842
Short name	T481
Test name
Test status
Simulation time	31092933 ps
CPU time	0.85 seconds
Started	Jan 10 01:19:26 PM PST 24
Finished	Jan 10 01:19:39 PM PST 24
Peak memory	205012 kb
Host	smart-c8d02bf6-17d0-42bf-8a3b-b98aec9e1be7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2575742842 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2575742842
Directory	/workspace/15.edn_smoke/latest

Test location	/workspace/coverage/default/15.edn_stress_all_with_rand_reset.3262114048
Short name	T812
Test name
Test status
Simulation time	166195156158 ps
CPU time	2005.29 seconds
Started	Jan 10 01:19:26 PM PST 24
Finished	Jan 10 01:53:03 PM PST 24
Peak memory	224048 kb
Host	smart-308710f4-a524-4c77-9b33-8ea28b55be21
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262114048 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.3262114048
Directory	/workspace/15.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/150.edn_genbits.1044365268
Short name	T564
Test name
Test status
Simulation time	42163019 ps
CPU time	1.12 seconds
Started	Jan 10 01:20:48 PM PST 24
Finished	Jan 10 01:20:54 PM PST 24
Peak memory	214272 kb
Host	smart-b1714481-c8fb-45fd-85b7-f9e1ca3de13e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1044365268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.1044365268
Directory	/workspace/150.edn_genbits/latest

Test location	/workspace/coverage/default/151.edn_genbits.1423914251
Short name	T811
Test name
Test status
Simulation time	26402336 ps
CPU time	1.01 seconds
Started	Jan 10 01:20:53 PM PST 24
Finished	Jan 10 01:20:59 PM PST 24
Peak memory	205376 kb
Host	smart-8fc8f86e-ab2c-4905-9aad-0a6f39774164
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1423914251 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.1423914251
Directory	/workspace/151.edn_genbits/latest

Test location	/workspace/coverage/default/152.edn_genbits.2095401277
Short name	T507
Test name
Test status
Simulation time	82654577 ps
CPU time	1.18 seconds
Started	Jan 10 01:20:36 PM PST 24
Finished	Jan 10 01:20:46 PM PST 24
Peak memory	214280 kb
Host	smart-1f8d4a66-f44e-431c-ad11-0b7bbb1baa95
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2095401277 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.2095401277
Directory	/workspace/152.edn_genbits/latest

Test location	/workspace/coverage/default/153.edn_genbits.2712668916
Short name	T338
Test name
Test status
Simulation time	24488068 ps
CPU time	1.29 seconds
Started	Jan 10 01:20:50 PM PST 24
Finished	Jan 10 01:20:57 PM PST 24
Peak memory	205764 kb
Host	smart-8b1c66bc-38ad-4287-94c7-ef6f3769f9cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2712668916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.2712668916
Directory	/workspace/153.edn_genbits/latest

Test location	/workspace/coverage/default/154.edn_genbits.3509551409
Short name	T918
Test name
Test status
Simulation time	134652596 ps
CPU time	0.99 seconds
Started	Jan 10 01:21:05 PM PST 24
Finished	Jan 10 01:21:09 PM PST 24
Peak memory	205672 kb
Host	smart-be319ecf-85bf-43ad-9f96-2c2c692e60f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3509551409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.3509551409
Directory	/workspace/154.edn_genbits/latest

Test location	/workspace/coverage/default/155.edn_genbits.3594049534
Short name	T934
Test name
Test status
Simulation time	17178436 ps
CPU time	1.01 seconds
Started	Jan 10 01:21:29 PM PST 24
Finished	Jan 10 01:21:45 PM PST 24
Peak memory	205608 kb
Host	smart-db90b651-fc79-4385-8224-228595c6463a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3594049534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.3594049534
Directory	/workspace/155.edn_genbits/latest

Test location	/workspace/coverage/default/156.edn_genbits.2706687263
Short name	T579
Test name
Test status
Simulation time	32066982 ps
CPU time	1.17 seconds
Started	Jan 10 01:21:01 PM PST 24
Finished	Jan 10 01:21:06 PM PST 24
Peak memory	214272 kb
Host	smart-1a95ad72-f15c-482a-8e86-8f9802eeae24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2706687263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.2706687263
Directory	/workspace/156.edn_genbits/latest

Test location	/workspace/coverage/default/157.edn_genbits.1416292080
Short name	T465
Test name
Test status
Simulation time	50865662 ps
CPU time	0.92 seconds
Started	Jan 10 01:21:10 PM PST 24
Finished	Jan 10 01:21:15 PM PST 24
Peak memory	205172 kb
Host	smart-72662cc6-b040-4517-b41c-58f39133e4c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1416292080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.1416292080
Directory	/workspace/157.edn_genbits/latest

Test location	/workspace/coverage/default/158.edn_genbits.3357343698
Short name	T650
Test name
Test status
Simulation time	34609507 ps
CPU time	1.53 seconds
Started	Jan 10 01:21:08 PM PST 24
Finished	Jan 10 01:21:14 PM PST 24
Peak memory	214436 kb
Host	smart-42fb404f-dfb0-4809-bae7-8d63633d170f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3357343698 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.3357343698
Directory	/workspace/158.edn_genbits/latest

Test location	/workspace/coverage/default/159.edn_genbits.1571226464
Short name	T639
Test name
Test status
Simulation time	66643510 ps
CPU time	1.15 seconds
Started	Jan 10 01:21:06 PM PST 24
Finished	Jan 10 01:21:12 PM PST 24
Peak memory	205596 kb
Host	smart-1790c2b3-b7aa-41d3-876d-fd910994fa7b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1571226464 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.1571226464
Directory	/workspace/159.edn_genbits/latest

Test location	/workspace/coverage/default/16.edn_alert.2891766677
Short name	T504
Test name
Test status
Simulation time	17065526 ps
CPU time	0.94 seconds
Started	Jan 10 01:19:18 PM PST 24
Finished	Jan 10 01:19:22 PM PST 24
Peak memory	205488 kb
Host	smart-64dc85d9-c47e-4f6d-85a7-a2f8639b8c84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2891766677 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.2891766677
Directory	/workspace/16.edn_alert/latest

Test location	/workspace/coverage/default/16.edn_alert_test.3267072482
Short name	T920
Test name
Test status
Simulation time	13214684 ps
CPU time	0.86 seconds
Started	Jan 10 01:19:08 PM PST 24
Finished	Jan 10 01:19:11 PM PST 24
Peak memory	204780 kb
Host	smart-12126ec4-d081-4b9b-9331-48e6ea9b4648
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267072482 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.3267072482
Directory	/workspace/16.edn_alert_test/latest

Test location	/workspace/coverage/default/16.edn_disable.2440907149
Short name	T168
Test name
Test status
Simulation time	37098914 ps
CPU time	0.85 seconds
Started	Jan 10 01:19:18 PM PST 24
Finished	Jan 10 01:19:22 PM PST 24
Peak memory	214480 kb
Host	smart-90b68db7-f411-4e29-afd5-5aed922a62c6
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440907149 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2440907149
Directory	/workspace/16.edn_disable/latest

Test location	/workspace/coverage/default/16.edn_genbits.41648461
Short name	T64
Test name
Test status
Simulation time	42645774 ps
CPU time	0.92 seconds
Started	Jan 10 01:19:28 PM PST 24
Finished	Jan 10 01:19:43 PM PST 24
Peak memory	205684 kb
Host	smart-b251dc33-990a-414b-9492-414770eea5ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=41648461 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.41648461
Directory	/workspace/16.edn_genbits/latest

Test location	/workspace/coverage/default/16.edn_smoke.1546394360
Short name	T625
Test name
Test status
Simulation time	14685713 ps
CPU time	0.89 seconds
Started	Jan 10 01:19:27 PM PST 24
Finished	Jan 10 01:19:43 PM PST 24
Peak memory	204768 kb
Host	smart-67c46e96-fa07-4bf0-afae-0318fc14d677
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1546394360 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.1546394360
Directory	/workspace/16.edn_smoke/latest

Test location	/workspace/coverage/default/16.edn_stress_all.4287730789
Short name	T457
Test name
Test status
Simulation time	246974374 ps
CPU time	1.27 seconds
Started	Jan 10 01:19:19 PM PST 24
Finished	Jan 10 01:19:24 PM PST 24
Peak memory	205384 kb
Host	smart-5f787956-c08a-456f-8d90-8b5ff96a1e3e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287730789 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.4287730789
Directory	/workspace/16.edn_stress_all/latest

Test location	/workspace/coverage/default/16.edn_stress_all_with_rand_reset.4279251063
Short name	T509
Test name
Test status
Simulation time	64714359474 ps
CPU time	1315.56 seconds
Started	Jan 10 01:19:17 PM PST 24
Finished	Jan 10 01:41:15 PM PST 24
Peak memory	216544 kb
Host	smart-1c8524f2-cd32-4ed1-a030-4ac7a6c0cb5f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279251063 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.4279251063
Directory	/workspace/16.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/160.edn_genbits.2078220923
Short name	T348
Test name
Test status
Simulation time	19679132 ps
CPU time	1.17 seconds
Started	Jan 10 01:20:51 PM PST 24
Finished	Jan 10 01:20:58 PM PST 24
Peak memory	214292 kb
Host	smart-891b1327-ccf9-44cc-b2a8-33fd3452d330
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2078220923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.2078220923
Directory	/workspace/160.edn_genbits/latest

Test location	/workspace/coverage/default/161.edn_genbits.2658895772
Short name	T485
Test name
Test status
Simulation time	166523547 ps
CPU time	1.07 seconds
Started	Jan 10 01:21:34 PM PST 24
Finished	Jan 10 01:21:55 PM PST 24
Peak memory	214336 kb
Host	smart-4535d4f2-31b2-4256-a872-7d3beacb658a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2658895772 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.2658895772
Directory	/workspace/161.edn_genbits/latest

Test location	/workspace/coverage/default/162.edn_genbits.3131813377
Short name	T483
Test name
Test status
Simulation time	17161592 ps
CPU time	1.15 seconds
Started	Jan 10 01:20:52 PM PST 24
Finished	Jan 10 01:20:58 PM PST 24
Peak memory	205896 kb
Host	smart-ae8d0174-3b39-480f-b149-9302ba6ad949
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3131813377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.3131813377
Directory	/workspace/162.edn_genbits/latest

Test location	/workspace/coverage/default/163.edn_genbits.357106859
Short name	T460
Test name
Test status
Simulation time	72339786 ps
CPU time	0.98 seconds
Started	Jan 10 01:20:56 PM PST 24
Finished	Jan 10 01:21:01 PM PST 24
Peak memory	205612 kb
Host	smart-629fe7d5-958f-4f38-a1a3-160d8dbc142c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=357106859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.357106859
Directory	/workspace/163.edn_genbits/latest

Test location	/workspace/coverage/default/164.edn_genbits.1202950992
Short name	T54
Test name
Test status
Simulation time	30391868 ps
CPU time	1.16 seconds
Started	Jan 10 01:21:31 PM PST 24
Finished	Jan 10 01:21:51 PM PST 24
Peak memory	205708 kb
Host	smart-4ed2d1a4-afb8-44ea-bcc3-e5f6967e6985
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1202950992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.1202950992
Directory	/workspace/164.edn_genbits/latest

Test location	/workspace/coverage/default/165.edn_genbits.3322020343
Short name	T330
Test name
Test status
Simulation time	14432473 ps
CPU time	0.98 seconds
Started	Jan 10 01:21:33 PM PST 24
Finished	Jan 10 01:21:54 PM PST 24
Peak memory	205584 kb
Host	smart-1963a95a-5990-458c-a377-15c3f1ac19a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3322020343 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3322020343
Directory	/workspace/165.edn_genbits/latest

Test location	/workspace/coverage/default/166.edn_genbits.4098785890
Short name	T282
Test name
Test status
Simulation time	23180423 ps
CPU time	1.08 seconds
Started	Jan 10 01:21:31 PM PST 24
Finished	Jan 10 01:21:50 PM PST 24
Peak memory	214420 kb
Host	smart-f3a104f8-fd73-4ea2-93bf-3f37c4082752
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4098785890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.4098785890
Directory	/workspace/166.edn_genbits/latest

Test location	/workspace/coverage/default/167.edn_genbits.727293870
Short name	T862
Test name
Test status
Simulation time	35073300 ps
CPU time	0.98 seconds
Started	Jan 10 01:21:04 PM PST 24
Finished	Jan 10 01:21:09 PM PST 24
Peak memory	205568 kb
Host	smart-3982cb4f-fab1-4377-b05e-3fcb11a56a00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=727293870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.727293870
Directory	/workspace/167.edn_genbits/latest

Test location	/workspace/coverage/default/169.edn_genbits.2256619290
Short name	T517
Test name
Test status
Simulation time	18924997 ps
CPU time	1.13 seconds
Started	Jan 10 01:21:31 PM PST 24
Finished	Jan 10 01:21:50 PM PST 24
Peak memory	205304 kb
Host	smart-43a9c9f7-486e-4dc2-a338-a228b9aff74d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2256619290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.2256619290
Directory	/workspace/169.edn_genbits/latest

Test location	/workspace/coverage/default/17.edn_alert.2690520836
Short name	T320
Test name
Test status
Simulation time	33597513 ps
CPU time	0.95 seconds
Started	Jan 10 01:19:22 PM PST 24
Finished	Jan 10 01:19:29 PM PST 24
Peak memory	205568 kb
Host	smart-ebe811fb-d150-4476-84d7-5f91284bce66
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2690520836 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.2690520836
Directory	/workspace/17.edn_alert/latest

Test location	/workspace/coverage/default/17.edn_alert_test.2874687074
Short name	T541
Test name
Test status
Simulation time	22878338 ps
CPU time	0.96 seconds
Started	Jan 10 01:19:24 PM PST 24
Finished	Jan 10 01:19:36 PM PST 24
Peak memory	205336 kb
Host	smart-7c7ed23a-fac2-4410-b7f1-6eedad1c16d1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874687074 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.2874687074
Directory	/workspace/17.edn_alert_test/latest

Test location	/workspace/coverage/default/17.edn_disable_auto_req_mode.1165283862
Short name	T894
Test name
Test status
Simulation time	22171663 ps
CPU time	0.9 seconds
Started	Jan 10 01:19:22 PM PST 24
Finished	Jan 10 01:19:30 PM PST 24
Peak memory	214588 kb
Host	smart-1ae052a8-a148-49e8-8df8-af67e32eeeb4
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165283862 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d isable_auto_req_mode.1165283862
Directory	/workspace/17.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/17.edn_err.200530475
Short name	T740
Test name
Test status
Simulation time	237079392 ps
CPU time	1.05 seconds
Started	Jan 10 01:19:23 PM PST 24
Finished	Jan 10 01:19:32 PM PST 24
Peak memory	217196 kb
Host	smart-5c3b147e-c5c4-48bd-89ea-850b54bca692
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=200530475 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.200530475
Directory	/workspace/17.edn_err/latest

Test location	/workspace/coverage/default/17.edn_genbits.1139756652
Short name	T834
Test name
Test status
Simulation time	31194315 ps
CPU time	1 seconds
Started	Jan 10 01:19:10 PM PST 24
Finished	Jan 10 01:19:16 PM PST 24
Peak memory	205772 kb
Host	smart-786e2320-f4a2-4b8b-a6d1-1eefa81fe6fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1139756652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.1139756652
Directory	/workspace/17.edn_genbits/latest

Test location	/workspace/coverage/default/17.edn_smoke.621573189
Short name	T887
Test name
Test status
Simulation time	35864092 ps
CPU time	0.81 seconds
Started	Jan 10 01:19:13 PM PST 24
Finished	Jan 10 01:19:18 PM PST 24
Peak memory	204900 kb
Host	smart-1d9829d2-dad3-4d98-8a44-64181ed03375
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=621573189 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.621573189
Directory	/workspace/17.edn_smoke/latest

Test location	/workspace/coverage/default/17.edn_stress_all.61217215
Short name	T594
Test name
Test status
Simulation time	299632989 ps
CPU time	3.27 seconds
Started	Jan 10 01:19:18 PM PST 24
Finished	Jan 10 01:19:24 PM PST 24
Peak memory	206164 kb
Host	smart-09d4b278-007d-49d2-8923-6ff5709b6540
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61217215 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.61217215
Directory	/workspace/17.edn_stress_all/latest

Test location	/workspace/coverage/default/17.edn_stress_all_with_rand_reset.447728102
Short name	T522
Test name
Test status
Simulation time	88188738766 ps
CPU time	1000.77 seconds
Started	Jan 10 01:19:21 PM PST 24
Finished	Jan 10 01:36:08 PM PST 24
Peak memory	216332 kb
Host	smart-80deccb7-23e4-4a92-9b06-c00533859042
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447728102 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.447728102
Directory	/workspace/17.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/170.edn_genbits.1206524131
Short name	T307
Test name
Test status
Simulation time	29201209 ps
CPU time	1.03 seconds
Started	Jan 10 01:21:11 PM PST 24
Finished	Jan 10 01:21:15 PM PST 24
Peak memory	205576 kb
Host	smart-7aa54630-3584-4dfc-88f5-2d8d0c573388
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1206524131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.1206524131
Directory	/workspace/170.edn_genbits/latest

Test location	/workspace/coverage/default/171.edn_genbits.1493420749
Short name	T333
Test name
Test status
Simulation time	61239824 ps
CPU time	2.26 seconds
Started	Jan 10 01:21:11 PM PST 24
Finished	Jan 10 01:21:16 PM PST 24
Peak memory	214396 kb
Host	smart-c4882fd5-0a12-4d6f-a124-785f5864808e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1493420749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.1493420749
Directory	/workspace/171.edn_genbits/latest

Test location	/workspace/coverage/default/172.edn_genbits.1709809965
Short name	T707
Test name
Test status
Simulation time	35909365 ps
CPU time	1.5 seconds
Started	Jan 10 01:21:31 PM PST 24
Finished	Jan 10 01:21:51 PM PST 24
Peak memory	214108 kb
Host	smart-2fc2a92d-da6f-4940-ac6c-21a4bf912037
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1709809965 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.1709809965
Directory	/workspace/172.edn_genbits/latest

Test location	/workspace/coverage/default/173.edn_genbits.2920079300
Short name	T287
Test name
Test status
Simulation time	55779775 ps
CPU time	1.35 seconds
Started	Jan 10 01:21:37 PM PST 24
Finished	Jan 10 01:21:56 PM PST 24
Peak memory	214268 kb
Host	smart-e775a1d1-6f59-4266-8829-f91e94c669f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2920079300 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.2920079300
Directory	/workspace/173.edn_genbits/latest

Test location	/workspace/coverage/default/174.edn_genbits.682340801
Short name	T649
Test name
Test status
Simulation time	72625638 ps
CPU time	1.01 seconds
Started	Jan 10 01:21:42 PM PST 24
Finished	Jan 10 01:22:05 PM PST 24
Peak memory	205652 kb
Host	smart-3a40b0c3-d4e7-421d-9a32-56e9f02a9abf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=682340801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.682340801
Directory	/workspace/174.edn_genbits/latest

Test location	/workspace/coverage/default/175.edn_genbits.2274058996
Short name	T38
Test name
Test status
Simulation time	36915456 ps
CPU time	1.05 seconds
Started	Jan 10 01:21:36 PM PST 24
Finished	Jan 10 01:21:56 PM PST 24
Peak memory	205488 kb
Host	smart-005029b5-0675-40e4-bd93-4199a5538402
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2274058996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.2274058996
Directory	/workspace/175.edn_genbits/latest

Test location	/workspace/coverage/default/176.edn_genbits.3349820550
Short name	T13
Test name
Test status
Simulation time	178839738 ps
CPU time	1.13 seconds
Started	Jan 10 01:21:40 PM PST 24
Finished	Jan 10 01:22:00 PM PST 24
Peak memory	214300 kb
Host	smart-743af4c6-9449-4226-af23-42913e170865
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3349820550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.3349820550
Directory	/workspace/176.edn_genbits/latest

Test location	/workspace/coverage/default/177.edn_genbits.1795980384
Short name	T884
Test name
Test status
Simulation time	152031893 ps
CPU time	0.87 seconds
Started	Jan 10 01:21:38 PM PST 24
Finished	Jan 10 01:21:58 PM PST 24
Peak memory	205252 kb
Host	smart-a068c7f9-8952-4f38-9af4-0d971ea3cbb4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1795980384 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.1795980384
Directory	/workspace/177.edn_genbits/latest

Test location	/workspace/coverage/default/178.edn_genbits.2007310665
Short name	T545
Test name
Test status
Simulation time	18298659 ps
CPU time	1.03 seconds
Started	Jan 10 01:21:41 PM PST 24
Finished	Jan 10 01:22:04 PM PST 24
Peak memory	205600 kb
Host	smart-600a4054-ef17-4de7-a3c7-1f92de6714ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2007310665 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.2007310665
Directory	/workspace/178.edn_genbits/latest

Test location	/workspace/coverage/default/179.edn_genbits.747177883
Short name	T112
Test name
Test status
Simulation time	277019821 ps
CPU time	3.57 seconds
Started	Jan 10 01:21:36 PM PST 24
Finished	Jan 10 01:21:58 PM PST 24
Peak memory	214228 kb
Host	smart-f332dc2b-78bc-42fc-ae08-0db806332665
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=747177883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.747177883
Directory	/workspace/179.edn_genbits/latest

Test location	/workspace/coverage/default/18.edn_alert_test.2558863041
Short name	T972
Test name
Test status
Simulation time	39013218 ps
CPU time	0.85 seconds
Started	Jan 10 01:19:26 PM PST 24
Finished	Jan 10 01:19:38 PM PST 24
Peak memory	204548 kb
Host	smart-f2c72cdf-538e-4708-a544-a0e6e3cb0e88
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558863041 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2558863041
Directory	/workspace/18.edn_alert_test/latest

Test location	/workspace/coverage/default/18.edn_disable.3540503649
Short name	T889
Test name
Test status
Simulation time	87539320 ps
CPU time	0.92 seconds
Started	Jan 10 01:19:23 PM PST 24
Finished	Jan 10 01:19:32 PM PST 24
Peak memory	214512 kb
Host	smart-c9bda873-b94b-4d7b-b2e9-0fb14b9f90ff
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540503649 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.3540503649
Directory	/workspace/18.edn_disable/latest

Test location	/workspace/coverage/default/18.edn_disable_auto_req_mode.4151591928
Short name	T151
Test name
Test status
Simulation time	156791087 ps
CPU time	1.07 seconds
Started	Jan 10 01:19:23 PM PST 24
Finished	Jan 10 01:19:33 PM PST 24
Peak memory	214692 kb
Host	smart-637fe90c-9648-4ed4-81aa-30c9816353d9
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151591928 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d isable_auto_req_mode.4151591928
Directory	/workspace/18.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/18.edn_err.1413724614
Short name	T5
Test name
Test status
Simulation time	19267813 ps
CPU time	1.05 seconds
Started	Jan 10 01:19:23 PM PST 24
Finished	Jan 10 01:19:32 PM PST 24
Peak memory	214976 kb
Host	smart-f6fc3ff1-d464-40be-859b-6ddbe183a005
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1413724614 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.1413724614
Directory	/workspace/18.edn_err/latest

Test location	/workspace/coverage/default/18.edn_genbits.1292573919
Short name	T843
Test name
Test status
Simulation time	18431891 ps
CPU time	1 seconds
Started	Jan 10 01:19:22 PM PST 24
Finished	Jan 10 01:19:30 PM PST 24
Peak memory	205136 kb
Host	smart-6e05bbdb-0dcc-4427-a623-c0300796d50f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1292573919 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.1292573919
Directory	/workspace/18.edn_genbits/latest

Test location	/workspace/coverage/default/18.edn_intr.2637644714
Short name	T39
Test name
Test status
Simulation time	27126111 ps
CPU time	0.91 seconds
Started	Jan 10 01:19:23 PM PST 24
Finished	Jan 10 01:19:34 PM PST 24
Peak memory	225616 kb
Host	smart-b4726003-0754-4985-8916-a842ca804218
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2637644714 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.2637644714
Directory	/workspace/18.edn_intr/latest

Test location	/workspace/coverage/default/18.edn_smoke.1355631413
Short name	T833
Test name
Test status
Simulation time	172664587 ps
CPU time	0.91 seconds
Started	Jan 10 01:19:22 PM PST 24
Finished	Jan 10 01:19:30 PM PST 24
Peak memory	204980 kb
Host	smart-0d0f5cc6-be09-4c54-91ab-9fcb67ec5e0b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1355631413 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.1355631413
Directory	/workspace/18.edn_smoke/latest

Test location	/workspace/coverage/default/18.edn_stress_all.2343260278
Short name	T532
Test name
Test status
Simulation time	66728277 ps
CPU time	1.31 seconds
Started	Jan 10 01:19:24 PM PST 24
Finished	Jan 10 01:19:36 PM PST 24
Peak memory	205892 kb
Host	smart-a0974e9d-10fa-483c-97ec-49dc280e7605
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343260278 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.2343260278
Directory	/workspace/18.edn_stress_all/latest

Test location	/workspace/coverage/default/18.edn_stress_all_with_rand_reset.977924266
Short name	T838
Test name
Test status
Simulation time	45310764584 ps
CPU time	259.52 seconds
Started	Jan 10 01:19:22 PM PST 24
Finished	Jan 10 01:23:49 PM PST 24
Peak memory	218604 kb
Host	smart-f6362e1c-6f15-4cb9-9414-0a719c8874fb
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977924266 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.977924266
Directory	/workspace/18.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/180.edn_genbits.632863326
Short name	T804
Test name
Test status
Simulation time	56890216 ps
CPU time	0.9 seconds
Started	Jan 10 01:21:40 PM PST 24
Finished	Jan 10 01:22:00 PM PST 24
Peak memory	205244 kb
Host	smart-2d33ddf3-6ecb-4e2c-a15c-ee36dc55e3c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=632863326 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.632863326
Directory	/workspace/180.edn_genbits/latest

Test location	/workspace/coverage/default/181.edn_genbits.321665772
Short name	T274
Test name
Test status
Simulation time	38576201 ps
CPU time	1.04 seconds
Started	Jan 10 01:21:37 PM PST 24
Finished	Jan 10 01:21:56 PM PST 24
Peak memory	214184 kb
Host	smart-dc07cc4e-22fd-400f-85e4-83c5155f77a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=321665772 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.321665772
Directory	/workspace/181.edn_genbits/latest

Test location	/workspace/coverage/default/182.edn_genbits.684428205
Short name	T656
Test name
Test status
Simulation time	256007047 ps
CPU time	1.33 seconds
Started	Jan 10 01:21:37 PM PST 24
Finished	Jan 10 01:21:56 PM PST 24
Peak memory	214364 kb
Host	smart-374d4111-b67c-4708-90f6-4fc3088ae2a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=684428205 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.684428205
Directory	/workspace/182.edn_genbits/latest

Test location	/workspace/coverage/default/183.edn_genbits.2959123519
Short name	T584
Test name
Test status
Simulation time	22534594 ps
CPU time	1.13 seconds
Started	Jan 10 01:21:42 PM PST 24
Finished	Jan 10 01:22:06 PM PST 24
Peak memory	205744 kb
Host	smart-6255a917-6d5f-40e0-8046-14da7c87a452
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2959123519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.2959123519
Directory	/workspace/183.edn_genbits/latest

Test location	/workspace/coverage/default/184.edn_genbits.3289839722
Short name	T491
Test name
Test status
Simulation time	20792159 ps
CPU time	1.03 seconds
Started	Jan 10 01:21:03 PM PST 24
Finished	Jan 10 01:21:07 PM PST 24
Peak memory	205652 kb
Host	smart-56d1622b-c7e2-4028-a108-5ff409a3ca84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3289839722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.3289839722
Directory	/workspace/184.edn_genbits/latest

Test location	/workspace/coverage/default/185.edn_genbits.519394749
Short name	T858
Test name
Test status
Simulation time	51589530 ps
CPU time	0.94 seconds
Started	Jan 10 01:21:42 PM PST 24
Finished	Jan 10 01:22:05 PM PST 24
Peak memory	205300 kb
Host	smart-c977190b-b594-47f6-b80f-17d8cf7f0092
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=519394749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.519394749
Directory	/workspace/185.edn_genbits/latest

Test location	/workspace/coverage/default/186.edn_genbits.130283476
Short name	T933
Test name
Test status
Simulation time	47722929 ps
CPU time	0.95 seconds
Started	Jan 10 01:20:47 PM PST 24
Finished	Jan 10 01:20:53 PM PST 24
Peak memory	205508 kb
Host	smart-4f1135f0-4dd7-4e5e-a273-2482a859f956
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=130283476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.130283476
Directory	/workspace/186.edn_genbits/latest

Test location	/workspace/coverage/default/187.edn_genbits.2799985568
Short name	T302
Test name
Test status
Simulation time	54925221 ps
CPU time	0.94 seconds
Started	Jan 10 01:20:34 PM PST 24
Finished	Jan 10 01:20:44 PM PST 24
Peak memory	205476 kb
Host	smart-5f5e76f1-39a4-4b96-b8b8-66fb45e8ba67
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2799985568 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.2799985568
Directory	/workspace/187.edn_genbits/latest

Test location	/workspace/coverage/default/188.edn_genbits.3845354116
Short name	T470
Test name
Test status
Simulation time	55096039 ps
CPU time	0.95 seconds
Started	Jan 10 01:20:53 PM PST 24
Finished	Jan 10 01:20:59 PM PST 24
Peak memory	205176 kb
Host	smart-1f718ece-5b4d-4234-b3e0-95180561a9f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3845354116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.3845354116
Directory	/workspace/188.edn_genbits/latest

Test location	/workspace/coverage/default/189.edn_genbits.685954270
Short name	T792
Test name
Test status
Simulation time	263289014 ps
CPU time	0.99 seconds
Started	Jan 10 01:20:45 PM PST 24
Finished	Jan 10 01:20:51 PM PST 24
Peak memory	205212 kb
Host	smart-bb268771-ad29-4b70-85cf-54b027bf74fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=685954270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.685954270
Directory	/workspace/189.edn_genbits/latest

Test location	/workspace/coverage/default/19.edn_alert.854505402
Short name	T722
Test name
Test status
Simulation time	18865297 ps
CPU time	0.99 seconds
Started	Jan 10 01:19:25 PM PST 24
Finished	Jan 10 01:19:37 PM PST 24
Peak memory	206068 kb
Host	smart-5cfac915-7dd6-441a-a738-36b7696c063d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=854505402 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.854505402
Directory	/workspace/19.edn_alert/latest

Test location	/workspace/coverage/default/19.edn_alert_test.1221518976
Short name	T868
Test name
Test status
Simulation time	16264605 ps
CPU time	0.95 seconds
Started	Jan 10 01:19:30 PM PST 24
Finished	Jan 10 01:19:46 PM PST 24
Peak memory	204724 kb
Host	smart-bdb35f8a-bbfd-4df7-9842-3f92501818f6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221518976 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.1221518976
Directory	/workspace/19.edn_alert_test/latest

Test location	/workspace/coverage/default/19.edn_disable.3231837969
Short name	T242
Test name
Test status
Simulation time	31589817 ps
CPU time	0.8 seconds
Started	Jan 10 01:19:25 PM PST 24
Finished	Jan 10 01:19:37 PM PST 24
Peak memory	214528 kb
Host	smart-4821c090-fd2e-415f-a44a-45e1797492b3
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231837969 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.3231837969
Directory	/workspace/19.edn_disable/latest

Test location	/workspace/coverage/default/19.edn_disable_auto_req_mode.1765697683
Short name	T880
Test name
Test status
Simulation time	24535867 ps
CPU time	1.05 seconds
Started	Jan 10 01:19:25 PM PST 24
Finished	Jan 10 01:19:37 PM PST 24
Peak memory	206412 kb
Host	smart-508fad72-1547-4212-9fbb-fa82ea33dfaa
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765697683 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d isable_auto_req_mode.1765697683
Directory	/workspace/19.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/19.edn_err.1669190691
Short name	T159
Test name
Test status
Simulation time	29523444 ps
CPU time	1.3 seconds
Started	Jan 10 01:19:26 PM PST 24
Finished	Jan 10 01:19:39 PM PST 24
Peak memory	221864 kb
Host	smart-c2c655c5-d1e9-4917-802c-7ccefefffd12
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1669190691 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.1669190691
Directory	/workspace/19.edn_err/latest

Test location	/workspace/coverage/default/19.edn_genbits.2363230947
Short name	T642
Test name
Test status
Simulation time	51735166 ps
CPU time	1.01 seconds
Started	Jan 10 01:19:23 PM PST 24
Finished	Jan 10 01:19:34 PM PST 24
Peak memory	214332 kb
Host	smart-f1302f53-b120-491c-b5d1-125494a94ddf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2363230947 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.2363230947
Directory	/workspace/19.edn_genbits/latest

Test location	/workspace/coverage/default/19.edn_intr.2392704594
Short name	T892
Test name
Test status
Simulation time	19388997 ps
CPU time	1.1 seconds
Started	Jan 10 01:19:26 PM PST 24
Finished	Jan 10 01:19:39 PM PST 24
Peak memory	221952 kb
Host	smart-234a9b43-c6b3-486e-9232-6f5b31aac3cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2392704594 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.2392704594
Directory	/workspace/19.edn_intr/latest

Test location	/workspace/coverage/default/19.edn_smoke.4203219443
Short name	T552
Test name
Test status
Simulation time	12976241 ps
CPU time	0.94 seconds
Started	Jan 10 01:19:22 PM PST 24
Finished	Jan 10 01:19:31 PM PST 24
Peak memory	205176 kb
Host	smart-f38baea7-9cae-4050-96a7-97525cccba7d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4203219443 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.4203219443
Directory	/workspace/19.edn_smoke/latest

Test location	/workspace/coverage/default/19.edn_stress_all.648113285
Short name	T956
Test name
Test status
Simulation time	37775442 ps
CPU time	0.99 seconds
Started	Jan 10 01:19:24 PM PST 24
Finished	Jan 10 01:19:36 PM PST 24
Peak memory	205380 kb
Host	smart-8b4dd01b-bed6-4893-8d2d-8b309c357af9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648113285 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.648113285
Directory	/workspace/19.edn_stress_all/latest

Test location	/workspace/coverage/default/19.edn_stress_all_with_rand_reset.1963604212
Short name	T815
Test name
Test status
Simulation time	103902755613 ps
CPU time	585.53 seconds
Started	Jan 10 01:19:24 PM PST 24
Finished	Jan 10 01:29:21 PM PST 24
Peak memory	214696 kb
Host	smart-17262b1d-9ee5-444d-997f-98f4eb746dd1
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963604212 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.1963604212
Directory	/workspace/19.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/190.edn_genbits.3519151021
Short name	T909
Test name
Test status
Simulation time	156810320 ps
CPU time	2.57 seconds
Started	Jan 10 01:20:33 PM PST 24
Finished	Jan 10 01:20:45 PM PST 24
Peak memory	214316 kb
Host	smart-13e5b01e-ee52-4318-aa88-bec3d5f77c2c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3519151021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.3519151021
Directory	/workspace/190.edn_genbits/latest

Test location	/workspace/coverage/default/191.edn_genbits.76798514
Short name	T813
Test name
Test status
Simulation time	22611098 ps
CPU time	1.36 seconds
Started	Jan 10 01:20:54 PM PST 24
Finished	Jan 10 01:21:00 PM PST 24
Peak memory	205656 kb
Host	smart-3edfe902-a7e4-45a8-8484-55691aaeb875
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=76798514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.76798514
Directory	/workspace/191.edn_genbits/latest

Test location	/workspace/coverage/default/192.edn_genbits.2956875106
Short name	T573
Test name
Test status
Simulation time	26264133 ps
CPU time	0.99 seconds
Started	Jan 10 01:20:34 PM PST 24
Finished	Jan 10 01:20:44 PM PST 24
Peak memory	205232 kb
Host	smart-ed44109d-71d2-4df2-9a72-57b053f611bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2956875106 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.2956875106
Directory	/workspace/192.edn_genbits/latest

Test location	/workspace/coverage/default/193.edn_genbits.3242157054
Short name	T65
Test name
Test status
Simulation time	53163166 ps
CPU time	0.95 seconds
Started	Jan 10 01:20:43 PM PST 24
Finished	Jan 10 01:20:50 PM PST 24
Peak memory	205292 kb
Host	smart-dab0020d-852d-47ab-913e-8c3ecb4684ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3242157054 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.3242157054
Directory	/workspace/193.edn_genbits/latest

Test location	/workspace/coverage/default/194.edn_genbits.2319043469
Short name	T553
Test name
Test status
Simulation time	21441306 ps
CPU time	1.1 seconds
Started	Jan 10 01:20:35 PM PST 24
Finished	Jan 10 01:20:45 PM PST 24
Peak memory	205520 kb
Host	smart-1ba60648-4d9c-4569-af49-3b103bb02237
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2319043469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2319043469
Directory	/workspace/194.edn_genbits/latest

Test location	/workspace/coverage/default/195.edn_genbits.3216585371
Short name	T461
Test name
Test status
Simulation time	17267774 ps
CPU time	1.06 seconds
Started	Jan 10 01:20:34 PM PST 24
Finished	Jan 10 01:20:44 PM PST 24
Peak memory	205224 kb
Host	smart-ab13371d-4099-4301-ae77-b1330958ac6a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3216585371 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.3216585371
Directory	/workspace/195.edn_genbits/latest

Test location	/workspace/coverage/default/196.edn_genbits.2620288994
Short name	T455
Test name
Test status
Simulation time	28286141 ps
CPU time	0.92 seconds
Started	Jan 10 01:20:35 PM PST 24
Finished	Jan 10 01:20:45 PM PST 24
Peak memory	205268 kb
Host	smart-5f623756-df1e-4439-9eb6-2d54e3a31d23
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2620288994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.2620288994
Directory	/workspace/196.edn_genbits/latest

Test location	/workspace/coverage/default/197.edn_genbits.4031564090
Short name	T704
Test name
Test status
Simulation time	13961545 ps
CPU time	0.95 seconds
Started	Jan 10 01:20:35 PM PST 24
Finished	Jan 10 01:20:45 PM PST 24
Peak memory	205816 kb
Host	smart-a6460166-59da-4b83-9c40-847bef45bdbc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4031564090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.4031564090
Directory	/workspace/197.edn_genbits/latest

Test location	/workspace/coverage/default/198.edn_genbits.1137444910
Short name	T513
Test name
Test status
Simulation time	16122946 ps
CPU time	0.91 seconds
Started	Jan 10 01:20:40 PM PST 24
Finished	Jan 10 01:20:49 PM PST 24
Peak memory	205236 kb
Host	smart-81efee1e-3f50-43bd-b403-d02519f7c6c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1137444910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.1137444910
Directory	/workspace/198.edn_genbits/latest

Test location	/workspace/coverage/default/199.edn_genbits.2474250139
Short name	T799
Test name
Test status
Simulation time	581497810 ps
CPU time	4.96 seconds
Started	Jan 10 01:20:40 PM PST 24
Finished	Jan 10 01:20:53 PM PST 24
Peak memory	214308 kb
Host	smart-6ee5c4cc-49ad-40f0-afca-e3ab0aea8a5e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2474250139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.2474250139
Directory	/workspace/199.edn_genbits/latest

Test location	/workspace/coverage/default/2.edn_alert.1883283090
Short name	T919
Test name
Test status
Simulation time	18351255 ps
CPU time	0.99 seconds
Started	Jan 10 01:18:30 PM PST 24
Finished	Jan 10 01:18:38 PM PST 24
Peak memory	206204 kb
Host	smart-89b87997-3e7c-419a-b097-a9d75d224cb6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1883283090 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.1883283090
Directory	/workspace/2.edn_alert/latest

Test location	/workspace/coverage/default/2.edn_alert_test.1385476498
Short name	T679
Test name
Test status
Simulation time	38096359 ps
CPU time	0.81 seconds
Started	Jan 10 01:18:38 PM PST 24
Finished	Jan 10 01:18:46 PM PST 24
Peak memory	205112 kb
Host	smart-64e1cbbc-ecd2-435c-9989-37f17dc33603
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385476498 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.1385476498
Directory	/workspace/2.edn_alert_test/latest

Test location	/workspace/coverage/default/2.edn_disable.2578010676
Short name	T177
Test name
Test status
Simulation time	14043041 ps
CPU time	0.96 seconds
Started	Jan 10 01:18:38 PM PST 24
Finished	Jan 10 01:18:47 PM PST 24
Peak memory	214600 kb
Host	smart-b87356ec-7fb4-49e8-baa7-de6b0f3b6798
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578010676 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2578010676
Directory	/workspace/2.edn_disable/latest

Test location	/workspace/coverage/default/2.edn_err.4255114026
Short name	T652
Test name
Test status
Simulation time	18891470 ps
CPU time	1.03 seconds
Started	Jan 10 01:18:33 PM PST 24
Finished	Jan 10 01:18:41 PM PST 24
Peak memory	214956 kb
Host	smart-cd7c3070-451f-4600-949d-73891d9365e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4255114026 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.4255114026
Directory	/workspace/2.edn_err/latest

Test location	/workspace/coverage/default/2.edn_genbits.3761627057
Short name	T899
Test name
Test status
Simulation time	33192071 ps
CPU time	1.03 seconds
Started	Jan 10 01:18:43 PM PST 24
Finished	Jan 10 01:18:50 PM PST 24
Peak memory	205188 kb
Host	smart-d7daa432-bf2a-4a59-afa7-edad9708a514
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3761627057 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.3761627057
Directory	/workspace/2.edn_genbits/latest

Test location	/workspace/coverage/default/2.edn_intr.2046700898
Short name	T47
Test name
Test status
Simulation time	24745908 ps
CPU time	1.01 seconds
Started	Jan 10 01:18:39 PM PST 24
Finished	Jan 10 01:18:48 PM PST 24
Peak memory	221932 kb
Host	smart-0a9beabb-d34e-4a92-8020-35241ecce5c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2046700898 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.2046700898
Directory	/workspace/2.edn_intr/latest

Test location	/workspace/coverage/default/2.edn_sec_cm.1331612050
Short name	T24
Test name
Test status
Simulation time	177204959 ps
CPU time	3.26 seconds
Started	Jan 10 01:18:36 PM PST 24
Finished	Jan 10 01:18:47 PM PST 24
Peak memory	231832 kb
Host	smart-69453477-3b1d-4563-8716-fef65b4def9d
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331612050 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.1331612050
Directory	/workspace/2.edn_sec_cm/latest

Test location	/workspace/coverage/default/2.edn_smoke.1566826926
Short name	T458
Test name
Test status
Simulation time	21718670 ps
CPU time	0.85 seconds
Started	Jan 10 01:18:38 PM PST 24
Finished	Jan 10 01:18:46 PM PST 24
Peak memory	204812 kb
Host	smart-d9a61a7c-3493-4ee1-83e7-6e40f31848cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1566826926 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.1566826926
Directory	/workspace/2.edn_smoke/latest

Test location	/workspace/coverage/default/2.edn_stress_all.1599377490
Short name	T562
Test name
Test status
Simulation time	432112826 ps
CPU time	2.62 seconds
Started	Jan 10 01:18:36 PM PST 24
Finished	Jan 10 01:18:46 PM PST 24
Peak memory	205976 kb
Host	smart-be616194-9e29-4b60-9f71-7808971d08ed
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599377490 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.1599377490
Directory	/workspace/2.edn_stress_all/latest

Test location	/workspace/coverage/default/2.edn_stress_all_with_rand_reset.216117659
Short name	T535
Test name
Test status
Simulation time	31807304131 ps
CPU time	357.48 seconds
Started	Jan 10 01:18:33 PM PST 24
Finished	Jan 10 01:24:37 PM PST 24
Peak memory	215420 kb
Host	smart-bd59f38e-a2dd-4bbd-95b2-31d57cfff0ed
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216117659 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.216117659
Directory	/workspace/2.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/20.edn_alert.945995347
Short name	T658
Test name
Test status
Simulation time	66088960 ps
CPU time	0.94 seconds
Started	Jan 10 01:19:27 PM PST 24
Finished	Jan 10 01:19:41 PM PST 24
Peak memory	205512 kb
Host	smart-a979b4f3-f803-47b7-b830-cb28ced45324
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=945995347 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.945995347
Directory	/workspace/20.edn_alert/latest

Test location	/workspace/coverage/default/20.edn_alert_test.3005816800
Short name	T662
Test name
Test status
Simulation time	47484520 ps
CPU time	0.85 seconds
Started	Jan 10 01:19:26 PM PST 24
Finished	Jan 10 01:19:38 PM PST 24
Peak memory	204728 kb
Host	smart-c48d737e-98ca-4470-85c3-db86b3d98564
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005816800 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.3005816800
Directory	/workspace/20.edn_alert_test/latest

Test location	/workspace/coverage/default/20.edn_disable.431686702
Short name	T817
Test name
Test status
Simulation time	12714230 ps
CPU time	0.84 seconds
Started	Jan 10 01:19:27 PM PST 24
Finished	Jan 10 01:19:40 PM PST 24
Peak memory	214624 kb
Host	smart-5645bd57-2fd9-46c9-890a-839b4bee45ad
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431686702 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.431686702
Directory	/workspace/20.edn_disable/latest

Test location	/workspace/coverage/default/20.edn_disable_auto_req_mode.2539746051
Short name	T619
Test name
Test status
Simulation time	16728925 ps
CPU time	0.91 seconds
Started	Jan 10 01:19:27 PM PST 24
Finished	Jan 10 01:19:42 PM PST 24
Peak memory	214672 kb
Host	smart-4458961f-373a-474b-85b3-ea001c603c39
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539746051 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d isable_auto_req_mode.2539746051
Directory	/workspace/20.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/20.edn_err.3713437885
Short name	T137
Test name
Test status
Simulation time	33765224 ps
CPU time	0.88 seconds
Started	Jan 10 01:19:28 PM PST 24
Finished	Jan 10 01:19:44 PM PST 24
Peak memory	214568 kb
Host	smart-6115d66e-a109-4663-b2ed-bdf38dd79769
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3713437885 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.3713437885
Directory	/workspace/20.edn_err/latest

Test location	/workspace/coverage/default/20.edn_genbits.3605457977
Short name	T975
Test name
Test status
Simulation time	40472409 ps
CPU time	0.97 seconds
Started	Jan 10 01:19:26 PM PST 24
Finished	Jan 10 01:19:38 PM PST 24
Peak memory	205464 kb
Host	smart-ee44c23a-58db-43fd-9003-ee2a9a2e951e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3605457977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.3605457977
Directory	/workspace/20.edn_genbits/latest

Test location	/workspace/coverage/default/20.edn_smoke.130282037
Short name	T61
Test name
Test status
Simulation time	49148146 ps
CPU time	0.86 seconds
Started	Jan 10 01:19:26 PM PST 24
Finished	Jan 10 01:19:39 PM PST 24
Peak memory	205028 kb
Host	smart-5052194b-647b-405e-8c2a-6947189c9b23
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=130282037 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.130282037
Directory	/workspace/20.edn_smoke/latest

Test location	/workspace/coverage/default/20.edn_stress_all.808754094
Short name	T478
Test name
Test status
Simulation time	170505094 ps
CPU time	3.81 seconds
Started	Jan 10 01:19:27 PM PST 24
Finished	Jan 10 01:19:44 PM PST 24
Peak memory	214316 kb
Host	smart-6a8324ea-aeaf-425f-afee-51d8f7d6dada
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808754094 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.808754094
Directory	/workspace/20.edn_stress_all/latest

Test location	/workspace/coverage/default/200.edn_genbits.2614083798
Short name	T3
Test name
Test status
Simulation time	27954003 ps
CPU time	0.92 seconds
Started	Jan 10 01:20:51 PM PST 24
Finished	Jan 10 01:20:57 PM PST 24
Peak memory	205216 kb
Host	smart-73f0cb3a-f566-413f-bf85-e80de850fae3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2614083798 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.2614083798
Directory	/workspace/200.edn_genbits/latest

Test location	/workspace/coverage/default/201.edn_genbits.2118710713
Short name	T644
Test name
Test status
Simulation time	39568031 ps
CPU time	1.42 seconds
Started	Jan 10 01:20:32 PM PST 24
Finished	Jan 10 01:20:42 PM PST 24
Peak memory	205608 kb
Host	smart-2b7b0b07-22e5-4a42-a01e-0378b6d5c194
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2118710713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.2118710713
Directory	/workspace/201.edn_genbits/latest

Test location	/workspace/coverage/default/202.edn_genbits.1067418255
Short name	T285
Test name
Test status
Simulation time	12706019 ps
CPU time	0.86 seconds
Started	Jan 10 01:20:49 PM PST 24
Finished	Jan 10 01:20:56 PM PST 24
Peak memory	205404 kb
Host	smart-5d131e2d-d90c-4bbf-a868-02b8ecde3d39
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1067418255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.1067418255
Directory	/workspace/202.edn_genbits/latest

Test location	/workspace/coverage/default/203.edn_genbits.2326192987
Short name	T583
Test name
Test status
Simulation time	60118959 ps
CPU time	0.87 seconds
Started	Jan 10 01:20:40 PM PST 24
Finished	Jan 10 01:20:49 PM PST 24
Peak memory	205212 kb
Host	smart-42f3891e-86cf-4f3d-ba0e-6daeb6a55d9c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2326192987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2326192987
Directory	/workspace/203.edn_genbits/latest

Test location	/workspace/coverage/default/204.edn_genbits.1399173607
Short name	T824
Test name
Test status
Simulation time	15960314 ps
CPU time	0.95 seconds
Started	Jan 10 01:20:51 PM PST 24
Finished	Jan 10 01:20:57 PM PST 24
Peak memory	205148 kb
Host	smart-768a4caf-397b-40ba-bbcf-7858f3d2bb9e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1399173607 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.1399173607
Directory	/workspace/204.edn_genbits/latest

Test location	/workspace/coverage/default/205.edn_genbits.2346458566
Short name	T712
Test name
Test status
Simulation time	51406046 ps
CPU time	1.34 seconds
Started	Jan 10 01:21:00 PM PST 24
Finished	Jan 10 01:21:05 PM PST 24
Peak memory	214356 kb
Host	smart-78c14fd9-7640-42c6-b542-460dd9ad89b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2346458566 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.2346458566
Directory	/workspace/205.edn_genbits/latest

Test location	/workspace/coverage/default/206.edn_genbits.2079834013
Short name	T825
Test name
Test status
Simulation time	32018097 ps
CPU time	1.17 seconds
Started	Jan 10 01:21:03 PM PST 24
Finished	Jan 10 01:21:08 PM PST 24
Peak memory	214244 kb
Host	smart-b44f02d4-652e-4d46-abc8-054e385c0166
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2079834013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.2079834013
Directory	/workspace/206.edn_genbits/latest

Test location	/workspace/coverage/default/207.edn_genbits.2677923726
Short name	T33
Test name
Test status
Simulation time	28029708 ps
CPU time	1.09 seconds
Started	Jan 10 01:21:07 PM PST 24
Finished	Jan 10 01:21:12 PM PST 24
Peak memory	205600 kb
Host	smart-ce94cc80-e228-4f0c-87b8-23adc2bdb944
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2677923726 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.2677923726
Directory	/workspace/207.edn_genbits/latest

Test location	/workspace/coverage/default/208.edn_genbits.3857231924
Short name	T946
Test name
Test status
Simulation time	42786131 ps
CPU time	1.05 seconds
Started	Jan 10 01:21:32 PM PST 24
Finished	Jan 10 01:21:54 PM PST 24
Peak memory	214336 kb
Host	smart-2b32e6de-cbcd-4cba-ab4d-a60721168b9a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3857231924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.3857231924
Directory	/workspace/208.edn_genbits/latest

Test location	/workspace/coverage/default/209.edn_genbits.687352231
Short name	T488
Test name
Test status
Simulation time	16533797 ps
CPU time	1.02 seconds
Started	Jan 10 01:21:31 PM PST 24
Finished	Jan 10 01:21:50 PM PST 24
Peak memory	205748 kb
Host	smart-3b28dc1a-d7f0-430d-9534-266c7eb3b869
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=687352231 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.687352231
Directory	/workspace/209.edn_genbits/latest

Test location	/workspace/coverage/default/21.edn_alert.3670455306
Short name	T917
Test name
Test status
Simulation time	42151792 ps
CPU time	0.89 seconds
Started	Jan 10 01:19:10 PM PST 24
Finished	Jan 10 01:19:15 PM PST 24
Peak memory	205896 kb
Host	smart-ea3f0f52-e2c6-48a2-b2fc-5c7b13861c84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3670455306 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3670455306
Directory	/workspace/21.edn_alert/latest

Test location	/workspace/coverage/default/21.edn_alert_test.2938554864
Short name	T734
Test name
Test status
Simulation time	22055669 ps
CPU time	0.97 seconds
Started	Jan 10 01:19:22 PM PST 24
Finished	Jan 10 01:19:31 PM PST 24
Peak memory	204784 kb
Host	smart-0461ea06-fe18-4062-a934-0299a7e06390
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938554864 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.2938554864
Directory	/workspace/21.edn_alert_test/latest

Test location	/workspace/coverage/default/21.edn_disable.731842744
Short name	T157
Test name
Test status
Simulation time	45932210 ps
CPU time	0.86 seconds
Started	Jan 10 01:19:09 PM PST 24
Finished	Jan 10 01:19:13 PM PST 24
Peak memory	214568 kb
Host	smart-1319ad72-4f2d-4410-9597-449d7b722fb2
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731842744 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.731842744
Directory	/workspace/21.edn_disable/latest

Test location	/workspace/coverage/default/21.edn_disable_auto_req_mode.461787018
Short name	T152
Test name
Test status
Simulation time	21293272 ps
CPU time	0.97 seconds
Started	Jan 10 01:19:20 PM PST 24
Finished	Jan 10 01:19:26 PM PST 24
Peak memory	214652 kb
Host	smart-a69158d8-61b9-44f6-b7c0-531bdcfc4ad0
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461787018 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_di sable_auto_req_mode.461787018
Directory	/workspace/21.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/21.edn_err.1806036868
Short name	T575
Test name
Test status
Simulation time	49464434 ps
CPU time	1.34 seconds
Started	Jan 10 01:19:21 PM PST 24
Finished	Jan 10 01:19:28 PM PST 24
Peak memory	227720 kb
Host	smart-2a394560-e5f4-41fc-8e00-b334f9935ff7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1806036868 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.1806036868
Directory	/workspace/21.edn_err/latest

Test location	/workspace/coverage/default/21.edn_genbits.307214283
Short name	T685
Test name
Test status
Simulation time	15528978 ps
CPU time	1.03 seconds
Started	Jan 10 01:19:27 PM PST 24
Finished	Jan 10 01:19:41 PM PST 24
Peak memory	205312 kb
Host	smart-dec37b4a-0816-4511-be4e-15cf5229619e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=307214283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.307214283
Directory	/workspace/21.edn_genbits/latest

Test location	/workspace/coverage/default/21.edn_intr.2678000798
Short name	T72
Test name
Test status
Simulation time	23526963 ps
CPU time	0.93 seconds
Started	Jan 10 01:19:08 PM PST 24
Finished	Jan 10 01:19:11 PM PST 24
Peak memory	214456 kb
Host	smart-38add967-dda7-414f-852e-e1d2ba1dc313
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2678000798 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.2678000798
Directory	/workspace/21.edn_intr/latest

Test location	/workspace/coverage/default/21.edn_smoke.374854196
Short name	T487
Test name
Test status
Simulation time	20503191 ps
CPU time	0.84 seconds
Started	Jan 10 01:19:27 PM PST 24
Finished	Jan 10 01:19:41 PM PST 24
Peak memory	205072 kb
Host	smart-94d28992-5406-44dd-9672-102304c6cf66
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=374854196 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.374854196
Directory	/workspace/21.edn_smoke/latest

Test location	/workspace/coverage/default/21.edn_stress_all.2291141071
Short name	T588
Test name
Test status
Simulation time	254001820 ps
CPU time	2.96 seconds
Started	Jan 10 01:19:28 PM PST 24
Finished	Jan 10 01:19:47 PM PST 24
Peak memory	206224 kb
Host	smart-5b981335-e57f-4b74-9841-52f2e8eded5d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291141071 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.2291141071
Directory	/workspace/21.edn_stress_all/latest

Test location	/workspace/coverage/default/21.edn_stress_all_with_rand_reset.1463839088
Short name	T496
Test name
Test status
Simulation time	75374766386 ps
CPU time	411.94 seconds
Started	Jan 10 01:19:10 PM PST 24
Finished	Jan 10 01:26:06 PM PST 24
Peak memory	216088 kb
Host	smart-18a94788-bd75-4f29-8238-7335b6daddfc
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463839088 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.1463839088
Directory	/workspace/21.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/210.edn_genbits.3924171955
Short name	T563
Test name
Test status
Simulation time	46713723 ps
CPU time	1.19 seconds
Started	Jan 10 01:21:10 PM PST 24
Finished	Jan 10 01:21:15 PM PST 24
Peak memory	214296 kb
Host	smart-c912516f-e36f-4641-9f2a-f02c4cc73187
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3924171955 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.3924171955
Directory	/workspace/210.edn_genbits/latest

Test location	/workspace/coverage/default/211.edn_genbits.3803788136
Short name	T343
Test name
Test status
Simulation time	54362744 ps
CPU time	0.9 seconds
Started	Jan 10 01:21:34 PM PST 24
Finished	Jan 10 01:21:54 PM PST 24
Peak memory	205024 kb
Host	smart-5c6daf13-278b-4b66-be26-9fe5ef90970e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3803788136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.3803788136
Directory	/workspace/211.edn_genbits/latest

Test location	/workspace/coverage/default/212.edn_genbits.3669098963
Short name	T944
Test name
Test status
Simulation time	51997874 ps
CPU time	1.31 seconds
Started	Jan 10 01:20:59 PM PST 24
Finished	Jan 10 01:21:05 PM PST 24
Peak memory	214312 kb
Host	smart-12427385-10a1-47bc-82eb-56e9dc280fe7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3669098963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.3669098963
Directory	/workspace/212.edn_genbits/latest

Test location	/workspace/coverage/default/213.edn_genbits.1931151075
Short name	T640
Test name
Test status
Simulation time	19080574 ps
CPU time	1.13 seconds
Started	Jan 10 01:21:26 PM PST 24
Finished	Jan 10 01:21:32 PM PST 24
Peak memory	214316 kb
Host	smart-ff79d982-8c1f-45cb-83e3-f8ee68237fdd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1931151075 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.1931151075
Directory	/workspace/213.edn_genbits/latest

Test location	/workspace/coverage/default/214.edn_genbits.4118243632
Short name	T785
Test name
Test status
Simulation time	17169570 ps
CPU time	0.99 seconds
Started	Jan 10 01:20:56 PM PST 24
Finished	Jan 10 01:21:00 PM PST 24
Peak memory	205348 kb
Host	smart-bed4e0a3-2b45-488c-baec-7ab24f11db01
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4118243632 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.4118243632
Directory	/workspace/214.edn_genbits/latest

Test location	/workspace/coverage/default/216.edn_genbits.4182869457
Short name	T511
Test name
Test status
Simulation time	121936853 ps
CPU time	1.22 seconds
Started	Jan 10 01:21:02 PM PST 24
Finished	Jan 10 01:21:06 PM PST 24
Peak memory	214308 kb
Host	smart-daa52a65-8c9d-4fdc-b718-0bbb1d07dd69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4182869457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.4182869457
Directory	/workspace/216.edn_genbits/latest

Test location	/workspace/coverage/default/217.edn_genbits.2041176307
Short name	T266
Test name
Test status
Simulation time	50533517 ps
CPU time	0.94 seconds
Started	Jan 10 01:20:55 PM PST 24
Finished	Jan 10 01:21:00 PM PST 24
Peak memory	205380 kb
Host	smart-0c26993c-e878-4160-8212-246a8e93cd73
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2041176307 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.2041176307
Directory	/workspace/217.edn_genbits/latest

Test location	/workspace/coverage/default/218.edn_genbits.1024365095
Short name	T278
Test name
Test status
Simulation time	56346236 ps
CPU time	1.03 seconds
Started	Jan 10 01:20:58 PM PST 24
Finished	Jan 10 01:21:03 PM PST 24
Peak memory	214364 kb
Host	smart-1e15053e-901f-4b9c-9daf-6a4bd02f816b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1024365095 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.1024365095
Directory	/workspace/218.edn_genbits/latest

Test location	/workspace/coverage/default/219.edn_genbits.2187648591
Short name	T276
Test name
Test status
Simulation time	62435200 ps
CPU time	2.33 seconds
Started	Jan 10 01:21:09 PM PST 24
Finished	Jan 10 01:21:15 PM PST 24
Peak memory	214364 kb
Host	smart-a6ab8be5-dfa6-4c77-af4c-6eaac78f0e0b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2187648591 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.2187648591
Directory	/workspace/219.edn_genbits/latest

Test location	/workspace/coverage/default/22.edn_alert.3582084917
Short name	T85
Test name
Test status
Simulation time	31808364 ps
CPU time	0.91 seconds
Started	Jan 10 01:19:27 PM PST 24
Finished	Jan 10 01:19:43 PM PST 24
Peak memory	205408 kb
Host	smart-8917539e-836a-475b-8f2d-3607129fab51
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3582084917 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.3582084917
Directory	/workspace/22.edn_alert/latest

Test location	/workspace/coverage/default/22.edn_alert_test.3451921413
Short name	T797
Test name
Test status
Simulation time	23416300 ps
CPU time	0.81 seconds
Started	Jan 10 01:19:37 PM PST 24
Finished	Jan 10 01:19:52 PM PST 24
Peak memory	204544 kb
Host	smart-c02a4a5f-b008-4ebb-b685-cf370ab4f823
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451921413 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.3451921413
Directory	/workspace/22.edn_alert_test/latest

Test location	/workspace/coverage/default/22.edn_disable.4139668590
Short name	T543
Test name
Test status
Simulation time	11709059 ps
CPU time	0.78 seconds
Started	Jan 10 01:19:32 PM PST 24
Finished	Jan 10 01:19:48 PM PST 24
Peak memory	214416 kb
Host	smart-91f07057-cf41-4d0f-bcb9-6f12dcd3b714
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139668590 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.4139668590
Directory	/workspace/22.edn_disable/latest

Test location	/workspace/coverage/default/22.edn_err.1205381969
Short name	T244
Test name
Test status
Simulation time	83547257 ps
CPU time	1.16 seconds
Started	Jan 10 01:19:35 PM PST 24
Finished	Jan 10 01:19:51 PM PST 24
Peak memory	221908 kb
Host	smart-9274182d-6ce8-4b6c-b81b-48fda3369af6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1205381969 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.1205381969
Directory	/workspace/22.edn_err/latest

Test location	/workspace/coverage/default/22.edn_genbits.3412895026
Short name	T905
Test name
Test status
Simulation time	61867625 ps
CPU time	2.43 seconds
Started	Jan 10 01:19:37 PM PST 24
Finished	Jan 10 01:19:54 PM PST 24
Peak memory	214316 kb
Host	smart-a34d2ec6-a217-41e4-be1a-73ff647be52a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3412895026 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.3412895026
Directory	/workspace/22.edn_genbits/latest

Test location	/workspace/coverage/default/22.edn_intr.2890286047
Short name	T89
Test name
Test status
Simulation time	47266746 ps
CPU time	0.78 seconds
Started	Jan 10 01:19:29 PM PST 24
Finished	Jan 10 01:19:45 PM PST 24
Peak memory	214588 kb
Host	smart-f87148df-030c-4950-a459-759b782f19f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2890286047 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.2890286047
Directory	/workspace/22.edn_intr/latest

Test location	/workspace/coverage/default/22.edn_smoke.2839305511
Short name	T749
Test name
Test status
Simulation time	26844982 ps
CPU time	0.92 seconds
Started	Jan 10 01:19:29 PM PST 24
Finished	Jan 10 01:19:45 PM PST 24
Peak memory	204808 kb
Host	smart-3c88d811-0b60-4ea8-8adf-4cb645172b5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2839305511 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.2839305511
Directory	/workspace/22.edn_smoke/latest

Test location	/workspace/coverage/default/22.edn_stress_all.110469184
Short name	T794
Test name
Test status
Simulation time	32582160 ps
CPU time	1.02 seconds
Started	Jan 10 01:19:27 PM PST 24
Finished	Jan 10 01:19:42 PM PST 24
Peak memory	205168 kb
Host	smart-e7c97901-3ec3-4878-87bd-471eb42af784
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110469184 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.110469184
Directory	/workspace/22.edn_stress_all/latest

Test location	/workspace/coverage/default/22.edn_stress_all_with_rand_reset.2739334890
Short name	T608
Test name
Test status
Simulation time	105007115273 ps
CPU time	650.15 seconds
Started	Jan 10 01:19:30 PM PST 24
Finished	Jan 10 01:30:36 PM PST 24
Peak memory	215960 kb
Host	smart-85712c74-a465-417a-bcf2-3442ca28946f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739334890 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.2739334890
Directory	/workspace/22.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/220.edn_genbits.1896286748
Short name	T332
Test name
Test status
Simulation time	18183507 ps
CPU time	0.99 seconds
Started	Jan 10 01:21:06 PM PST 24
Finished	Jan 10 01:21:11 PM PST 24
Peak memory	205276 kb
Host	smart-7272f7cd-ff54-40bc-afd1-5b7fb7d56537
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1896286748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.1896286748
Directory	/workspace/220.edn_genbits/latest

Test location	/workspace/coverage/default/221.edn_genbits.2905926897
Short name	T529
Test name
Test status
Simulation time	31955178 ps
CPU time	1.16 seconds
Started	Jan 10 01:21:03 PM PST 24
Finished	Jan 10 01:21:08 PM PST 24
Peak memory	205884 kb
Host	smart-8c091584-627d-41eb-924d-7a330792f790
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2905926897 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.2905926897
Directory	/workspace/221.edn_genbits/latest

Test location	/workspace/coverage/default/222.edn_genbits.3652225253
Short name	T548
Test name
Test status
Simulation time	23680923 ps
CPU time	1.19 seconds
Started	Jan 10 01:21:00 PM PST 24
Finished	Jan 10 01:21:05 PM PST 24
Peak memory	205412 kb
Host	smart-49644a19-34f5-4197-ae53-d6bc7f55b7de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3652225253 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.3652225253
Directory	/workspace/222.edn_genbits/latest

Test location	/workspace/coverage/default/223.edn_genbits.2637973937
Short name	T867
Test name
Test status
Simulation time	15227250 ps
CPU time	0.96 seconds
Started	Jan 10 01:21:05 PM PST 24
Finished	Jan 10 01:21:10 PM PST 24
Peak memory	204996 kb
Host	smart-911ca435-79c0-42a5-b8c3-8eb367491a0c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2637973937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.2637973937
Directory	/workspace/223.edn_genbits/latest

Test location	/workspace/coverage/default/224.edn_genbits.1387086824
Short name	T35
Test name
Test status
Simulation time	256344395 ps
CPU time	1 seconds
Started	Jan 10 01:21:03 PM PST 24
Finished	Jan 10 01:21:07 PM PST 24
Peak memory	205664 kb
Host	smart-bb84f81a-4eca-4aad-be88-6a6f578be2e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1387086824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.1387086824
Directory	/workspace/224.edn_genbits/latest

Test location	/workspace/coverage/default/225.edn_genbits.1274577478
Short name	T687
Test name
Test status
Simulation time	18141663 ps
CPU time	1.11 seconds
Started	Jan 10 01:21:04 PM PST 24
Finished	Jan 10 01:21:09 PM PST 24
Peak memory	205760 kb
Host	smart-e18647ad-2aad-4da2-8906-75a3e514581c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1274577478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.1274577478
Directory	/workspace/225.edn_genbits/latest

Test location	/workspace/coverage/default/226.edn_genbits.1882137525
Short name	T2
Test name
Test status
Simulation time	18823114 ps
CPU time	1.01 seconds
Started	Jan 10 01:20:59 PM PST 24
Finished	Jan 10 01:21:05 PM PST 24
Peak memory	205284 kb
Host	smart-e3453fbf-35da-40bf-a96c-bd80d722c4a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1882137525 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.1882137525
Directory	/workspace/226.edn_genbits/latest

Test location	/workspace/coverage/default/227.edn_genbits.811464993
Short name	T921
Test name
Test status
Simulation time	15171884 ps
CPU time	1.04 seconds
Started	Jan 10 01:20:59 PM PST 24
Finished	Jan 10 01:21:05 PM PST 24
Peak memory	214320 kb
Host	smart-05ef0ef0-9890-4994-a763-48a4731ace61
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=811464993 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.811464993
Directory	/workspace/227.edn_genbits/latest

Test location	/workspace/coverage/default/228.edn_genbits.1767307869
Short name	T305
Test name
Test status
Simulation time	17899789 ps
CPU time	1 seconds
Started	Jan 10 01:21:07 PM PST 24
Finished	Jan 10 01:21:12 PM PST 24
Peak memory	206016 kb
Host	smart-7b26e2ea-e179-4260-bb55-5088a0e17201
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1767307869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.1767307869
Directory	/workspace/228.edn_genbits/latest

Test location	/workspace/coverage/default/229.edn_genbits.166869641
Short name	T518
Test name
Test status
Simulation time	87999893 ps
CPU time	1.3 seconds
Started	Jan 10 01:21:16 PM PST 24
Finished	Jan 10 01:21:19 PM PST 24
Peak memory	205756 kb
Host	smart-f79534e1-47fe-4abd-947c-2b34801017a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=166869641 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.166869641
Directory	/workspace/229.edn_genbits/latest

Test location	/workspace/coverage/default/23.edn_alert.1252713809
Short name	T313
Test name
Test status
Simulation time	16542939 ps
CPU time	0.91 seconds
Started	Jan 10 01:19:30 PM PST 24
Finished	Jan 10 01:19:47 PM PST 24
Peak memory	206116 kb
Host	smart-8a589198-a87f-4ccc-ae48-97d4a25484d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1252713809 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.1252713809
Directory	/workspace/23.edn_alert/latest

Test location	/workspace/coverage/default/23.edn_alert_test.228129279
Short name	T717
Test name
Test status
Simulation time	15132878 ps
CPU time	0.93 seconds
Started	Jan 10 01:19:38 PM PST 24
Finished	Jan 10 01:19:53 PM PST 24
Peak memory	204672 kb
Host	smart-4f2bfaf0-de62-46f9-945e-6be8a37ed0e6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228129279 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.228129279
Directory	/workspace/23.edn_alert_test/latest

Test location	/workspace/coverage/default/23.edn_disable.3569973910
Short name	T542
Test name
Test status
Simulation time	13376359 ps
CPU time	0.88 seconds
Started	Jan 10 01:19:28 PM PST 24
Finished	Jan 10 01:19:43 PM PST 24
Peak memory	214588 kb
Host	smart-e976229b-b34c-4549-9f67-c761755929c6
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569973910 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3569973910
Directory	/workspace/23.edn_disable/latest

Test location	/workspace/coverage/default/23.edn_disable_auto_req_mode.3077755873
Short name	T119
Test name
Test status
Simulation time	32434586 ps
CPU time	0.94 seconds
Started	Jan 10 01:19:37 PM PST 24
Finished	Jan 10 01:19:52 PM PST 24
Peak memory	206456 kb
Host	smart-9b9b46fb-972e-4287-82cc-732d16120bdb
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077755873 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d isable_auto_req_mode.3077755873
Directory	/workspace/23.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/23.edn_err.3220772246
Short name	T163
Test name
Test status
Simulation time	22071339 ps
CPU time	0.96 seconds
Started	Jan 10 01:19:29 PM PST 24
Finished	Jan 10 01:19:45 PM PST 24
Peak memory	221860 kb
Host	smart-a01d6485-4fc3-42cd-8251-14677d27ef8d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3220772246 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.3220772246
Directory	/workspace/23.edn_err/latest

Test location	/workspace/coverage/default/23.edn_genbits.1662714590
Short name	T900
Test name
Test status
Simulation time	142270304 ps
CPU time	2.02 seconds
Started	Jan 10 01:19:29 PM PST 24
Finished	Jan 10 01:19:46 PM PST 24
Peak memory	214124 kb
Host	smart-00b4a13a-25ff-4ace-9156-fc659d1fe3a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1662714590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.1662714590
Directory	/workspace/23.edn_genbits/latest

Test location	/workspace/coverage/default/23.edn_intr.1761155908
Short name	T893
Test name
Test status
Simulation time	41105119 ps
CPU time	0.88 seconds
Started	Jan 10 01:19:39 PM PST 24
Finished	Jan 10 01:19:54 PM PST 24
Peak memory	214560 kb
Host	smart-1f10e340-ec13-403c-b8df-db36fae4d69d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1761155908 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.1761155908
Directory	/workspace/23.edn_intr/latest

Test location	/workspace/coverage/default/23.edn_smoke.2128136734
Short name	T568
Test name
Test status
Simulation time	22349894 ps
CPU time	0.84 seconds
Started	Jan 10 01:19:30 PM PST 24
Finished	Jan 10 01:19:46 PM PST 24
Peak memory	205052 kb
Host	smart-59215b23-5d91-422c-ad85-443270b21875
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2128136734 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.2128136734
Directory	/workspace/23.edn_smoke/latest

Test location	/workspace/coverage/default/23.edn_stress_all.3521344684
Short name	T845
Test name
Test status
Simulation time	158821797 ps
CPU time	3.56 seconds
Started	Jan 10 01:19:27 PM PST 24
Finished	Jan 10 01:19:44 PM PST 24
Peak memory	206128 kb
Host	smart-32156158-bb71-437c-88c4-9f38a274d3f2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521344684 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.3521344684
Directory	/workspace/23.edn_stress_all/latest

Test location	/workspace/coverage/default/23.edn_stress_all_with_rand_reset.4136588710
Short name	T631
Test name
Test status
Simulation time	145532126925 ps
CPU time	485.72 seconds
Started	Jan 10 01:19:38 PM PST 24
Finished	Jan 10 01:27:57 PM PST 24
Peak memory	214780 kb
Host	smart-3487f119-e944-4c8c-a43b-e3a14187a543
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136588710 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.4136588710
Directory	/workspace/23.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/230.edn_genbits.7185250
Short name	T336
Test name
Test status
Simulation time	49179890 ps
CPU time	1.58 seconds
Started	Jan 10 01:21:03 PM PST 24
Finished	Jan 10 01:21:08 PM PST 24
Peak memory	205468 kb
Host	smart-730a77fd-9fb8-4596-ac9a-feef1d49a621
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=7185250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.7185250
Directory	/workspace/230.edn_genbits/latest

Test location	/workspace/coverage/default/231.edn_genbits.4269701676
Short name	T10
Test name
Test status
Simulation time	22585243 ps
CPU time	1.11 seconds
Started	Jan 10 01:20:54 PM PST 24
Finished	Jan 10 01:21:00 PM PST 24
Peak memory	214288 kb
Host	smart-5b65144e-5e0b-4508-992e-eb896fff9aac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4269701676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.4269701676
Directory	/workspace/231.edn_genbits/latest

Test location	/workspace/coverage/default/232.edn_genbits.628974520
Short name	T873
Test name
Test status
Simulation time	18214544 ps
CPU time	1.08 seconds
Started	Jan 10 01:20:56 PM PST 24
Finished	Jan 10 01:21:00 PM PST 24
Peak memory	205348 kb
Host	smart-73e572c5-6b22-4277-9c9a-e5360a1fe48a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=628974520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.628974520
Directory	/workspace/232.edn_genbits/latest

Test location	/workspace/coverage/default/233.edn_genbits.1192940996
Short name	T910
Test name
Test status
Simulation time	66681655 ps
CPU time	1.31 seconds
Started	Jan 10 01:21:29 PM PST 24
Finished	Jan 10 01:21:44 PM PST 24
Peak memory	214252 kb
Host	smart-209d5639-a6b4-4c98-9f4c-991bfe28bd01
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1192940996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.1192940996
Directory	/workspace/233.edn_genbits/latest

Test location	/workspace/coverage/default/234.edn_genbits.924806045
Short name	T479
Test name
Test status
Simulation time	40666604 ps
CPU time	1.05 seconds
Started	Jan 10 01:20:49 PM PST 24
Finished	Jan 10 01:20:56 PM PST 24
Peak memory	205676 kb
Host	smart-ef450555-c50f-4736-a470-aa5679388363
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=924806045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.924806045
Directory	/workspace/234.edn_genbits/latest

Test location	/workspace/coverage/default/235.edn_genbits.445668863
Short name	T668
Test name
Test status
Simulation time	73683075 ps
CPU time	0.96 seconds
Started	Jan 10 01:20:58 PM PST 24
Finished	Jan 10 01:21:03 PM PST 24
Peak memory	205544 kb
Host	smart-272776cf-46a3-478b-83da-021f9069c3da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=445668863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.445668863
Directory	/workspace/235.edn_genbits/latest

Test location	/workspace/coverage/default/236.edn_genbits.2640716921
Short name	T480
Test name
Test status
Simulation time	84317566 ps
CPU time	0.88 seconds
Started	Jan 10 01:21:02 PM PST 24
Finished	Jan 10 01:21:06 PM PST 24
Peak memory	205164 kb
Host	smart-f96583e8-4c6b-409f-96f4-a7e8b2c905d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2640716921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.2640716921
Directory	/workspace/236.edn_genbits/latest

Test location	/workspace/coverage/default/237.edn_genbits.3542086478
Short name	T951
Test name
Test status
Simulation time	27355628 ps
CPU time	0.86 seconds
Started	Jan 10 01:21:30 PM PST 24
Finished	Jan 10 01:21:48 PM PST 24
Peak memory	205040 kb
Host	smart-769cc92c-7157-45e9-ace5-f8a2cbcc7853
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3542086478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.3542086478
Directory	/workspace/237.edn_genbits/latest

Test location	/workspace/coverage/default/238.edn_genbits.1829025097
Short name	T505
Test name
Test status
Simulation time	97089644 ps
CPU time	1.55 seconds
Started	Jan 10 01:21:24 PM PST 24
Finished	Jan 10 01:21:31 PM PST 24
Peak memory	214344 kb
Host	smart-3724536e-0fe1-40a0-8b14-774fb4062684
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1829025097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.1829025097
Directory	/workspace/238.edn_genbits/latest

Test location	/workspace/coverage/default/239.edn_genbits.1141537957
Short name	T300
Test name
Test status
Simulation time	96583149 ps
CPU time	0.9 seconds
Started	Jan 10 01:20:56 PM PST 24
Finished	Jan 10 01:21:01 PM PST 24
Peak memory	205024 kb
Host	smart-1f05f2bc-c304-48ba-b58e-b696598e8cbd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1141537957 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.1141537957
Directory	/workspace/239.edn_genbits/latest

Test location	/workspace/coverage/default/24.edn_alert.2520445402
Short name	T19
Test name
Test status
Simulation time	65487549 ps
CPU time	0.92 seconds
Started	Jan 10 01:19:35 PM PST 24
Finished	Jan 10 01:19:51 PM PST 24
Peak memory	205360 kb
Host	smart-d1cf2567-1ceb-422a-86e4-c7e8618df819
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2520445402 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.2520445402
Directory	/workspace/24.edn_alert/latest

Test location	/workspace/coverage/default/24.edn_alert_test.842886734
Short name	T802
Test name
Test status
Simulation time	32611169 ps
CPU time	0.73 seconds
Started	Jan 10 01:19:29 PM PST 24
Finished	Jan 10 01:19:44 PM PST 24
Peak memory	204428 kb
Host	smart-10f58955-f62b-4220-936d-46febd6d2d2f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842886734 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.842886734
Directory	/workspace/24.edn_alert_test/latest

Test location	/workspace/coverage/default/24.edn_disable.3844344290
Short name	T727
Test name
Test status
Simulation time	12144245 ps
CPU time	0.89 seconds
Started	Jan 10 01:19:38 PM PST 24
Finished	Jan 10 01:19:52 PM PST 24
Peak memory	214620 kb
Host	smart-a6083327-00fb-42e6-8e51-7d12e518e7b6
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844344290 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.3844344290
Directory	/workspace/24.edn_disable/latest

Test location	/workspace/coverage/default/24.edn_err.4266813712
Short name	T719
Test name
Test status
Simulation time	28899115 ps
CPU time	0.84 seconds
Started	Jan 10 01:19:39 PM PST 24
Finished	Jan 10 01:19:54 PM PST 24
Peak memory	215744 kb
Host	smart-1f867896-9f06-4594-8f03-44e1974d2b36
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4266813712 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.4266813712
Directory	/workspace/24.edn_err/latest

Test location	/workspace/coverage/default/24.edn_genbits.1905795744
Short name	T271
Test name
Test status
Simulation time	16559331 ps
CPU time	0.94 seconds
Started	Jan 10 01:19:35 PM PST 24
Finished	Jan 10 01:19:50 PM PST 24
Peak memory	205172 kb
Host	smart-3ca0af10-536c-42d3-b622-fb8a5c61edaa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1905795744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1905795744
Directory	/workspace/24.edn_genbits/latest

Test location	/workspace/coverage/default/24.edn_intr.1045266719
Short name	T97
Test name
Test status
Simulation time	19931567 ps
CPU time	1.02 seconds
Started	Jan 10 01:19:39 PM PST 24
Finished	Jan 10 01:19:54 PM PST 24
Peak memory	225684 kb
Host	smart-31d4bd1d-55ba-4419-af28-a8781b453a14
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1045266719 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.1045266719
Directory	/workspace/24.edn_intr/latest

Test location	/workspace/coverage/default/24.edn_smoke.1050503338
Short name	T450
Test name
Test status
Simulation time	74711779 ps
CPU time	0.94 seconds
Started	Jan 10 01:19:38 PM PST 24
Finished	Jan 10 01:19:53 PM PST 24
Peak memory	204704 kb
Host	smart-66f2fb51-1750-4fc1-b538-72de1494fff1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1050503338 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.1050503338
Directory	/workspace/24.edn_smoke/latest

Test location	/workspace/coverage/default/24.edn_stress_all.531145741
Short name	T539
Test name
Test status
Simulation time	94307776 ps
CPU time	1.45 seconds
Started	Jan 10 01:19:27 PM PST 24
Finished	Jan 10 01:19:43 PM PST 24
Peak memory	206056 kb
Host	smart-07904d34-e021-43fc-9253-c6b900646f2b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531145741 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.531145741
Directory	/workspace/24.edn_stress_all/latest

Test location	/workspace/coverage/default/240.edn_genbits.1399092375
Short name	T859
Test name
Test status
Simulation time	17180028 ps
CPU time	0.93 seconds
Started	Jan 10 01:20:56 PM PST 24
Finished	Jan 10 01:21:01 PM PST 24
Peak memory	205248 kb
Host	smart-a1bb035f-c5b4-49d9-bb70-d4390ec027f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1399092375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.1399092375
Directory	/workspace/240.edn_genbits/latest

Test location	/workspace/coverage/default/242.edn_genbits.265258379
Short name	T769
Test name
Test status
Simulation time	19646129 ps
CPU time	1.11 seconds
Started	Jan 10 01:21:02 PM PST 24
Finished	Jan 10 01:21:07 PM PST 24
Peak memory	205820 kb
Host	smart-6093b113-5659-44ce-8586-02133d4c32fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=265258379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.265258379
Directory	/workspace/242.edn_genbits/latest

Test location	/workspace/coverage/default/243.edn_genbits.3638358766
Short name	T304
Test name
Test status
Simulation time	14536963 ps
CPU time	0.95 seconds
Started	Jan 10 01:21:31 PM PST 24
Finished	Jan 10 01:21:49 PM PST 24
Peak memory	205508 kb
Host	smart-38d953f4-b5d1-4249-a56b-a771743962f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3638358766 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.3638358766
Directory	/workspace/243.edn_genbits/latest

Test location	/workspace/coverage/default/244.edn_genbits.1676565082
Short name	T9
Test name
Test status
Simulation time	65176709 ps
CPU time	1.03 seconds
Started	Jan 10 01:21:01 PM PST 24
Finished	Jan 10 01:21:05 PM PST 24
Peak memory	214356 kb
Host	smart-e8002031-a156-43f0-8334-50814500f2d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1676565082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.1676565082
Directory	/workspace/244.edn_genbits/latest

Test location	/workspace/coverage/default/245.edn_genbits.3870344509
Short name	T554
Test name
Test status
Simulation time	14356487 ps
CPU time	0.89 seconds
Started	Jan 10 01:21:06 PM PST 24
Finished	Jan 10 01:21:11 PM PST 24
Peak memory	205404 kb
Host	smart-09cd683c-9af8-48bc-99ea-1a0457e8ec55
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3870344509 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.3870344509
Directory	/workspace/245.edn_genbits/latest

Test location	/workspace/coverage/default/246.edn_genbits.1909215993
Short name	T710
Test name
Test status
Simulation time	70613011 ps
CPU time	1.09 seconds
Started	Jan 10 01:20:58 PM PST 24
Finished	Jan 10 01:21:03 PM PST 24
Peak memory	205612 kb
Host	smart-7478e6dc-c612-44fb-8e41-349c42c3baac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1909215993 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.1909215993
Directory	/workspace/246.edn_genbits/latest

Test location	/workspace/coverage/default/247.edn_genbits.796495918
Short name	T560
Test name
Test status
Simulation time	18652033 ps
CPU time	1 seconds
Started	Jan 10 01:21:27 PM PST 24
Finished	Jan 10 01:21:38 PM PST 24
Peak memory	205216 kb
Host	smart-d3626582-bd8f-44ee-9669-9617c11cc2da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=796495918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.796495918
Directory	/workspace/247.edn_genbits/latest

Test location	/workspace/coverage/default/248.edn_genbits.1416226427
Short name	T974
Test name
Test status
Simulation time	15995801 ps
CPU time	0.94 seconds
Started	Jan 10 01:21:32 PM PST 24
Finished	Jan 10 01:21:52 PM PST 24
Peak memory	205568 kb
Host	smart-0c4f9f86-653a-444a-8b9a-bf854c76a456
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1416226427 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.1416226427
Directory	/workspace/248.edn_genbits/latest

Test location	/workspace/coverage/default/249.edn_genbits.589367096
Short name	T489
Test name
Test status
Simulation time	65944046 ps
CPU time	1.01 seconds
Started	Jan 10 01:21:30 PM PST 24
Finished	Jan 10 01:21:47 PM PST 24
Peak memory	205728 kb
Host	smart-9aee64ea-22a3-4ff7-8d41-ff1f7370d2e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=589367096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.589367096
Directory	/workspace/249.edn_genbits/latest

Test location	/workspace/coverage/default/25.edn_alert.1715258784
Short name	T254
Test name
Test status
Simulation time	16805699 ps
CPU time	0.95 seconds
Started	Jan 10 01:19:29 PM PST 24
Finished	Jan 10 01:19:45 PM PST 24
Peak memory	205864 kb
Host	smart-9020863e-7ca2-468b-a5b6-edd93298e759
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1715258784 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.1715258784
Directory	/workspace/25.edn_alert/latest

Test location	/workspace/coverage/default/25.edn_alert_test.3989741922
Short name	T927
Test name
Test status
Simulation time	35713402 ps
CPU time	0.92 seconds
Started	Jan 10 01:19:37 PM PST 24
Finished	Jan 10 01:19:52 PM PST 24
Peak memory	204828 kb
Host	smart-3890103f-b04e-4983-97bd-d3a52811660e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989741922 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.3989741922
Directory	/workspace/25.edn_alert_test/latest

Test location	/workspace/coverage/default/25.edn_disable.3973948015
Short name	T165
Test name
Test status
Simulation time	21524127 ps
CPU time	0.87 seconds
Started	Jan 10 01:19:35 PM PST 24
Finished	Jan 10 01:19:51 PM PST 24
Peak memory	214532 kb
Host	smart-18e5528d-9985-427f-ad92-8d6684a2f213
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973948015 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.3973948015
Directory	/workspace/25.edn_disable/latest

Test location	/workspace/coverage/default/25.edn_disable_auto_req_mode.1600522186
Short name	T877
Test name
Test status
Simulation time	28998889 ps
CPU time	0.94 seconds
Started	Jan 10 01:19:31 PM PST 24
Finished	Jan 10 01:19:48 PM PST 24
Peak memory	214556 kb
Host	smart-bc383f2b-ede5-476f-83e8-1a1d9a8a3581
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600522186 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d isable_auto_req_mode.1600522186
Directory	/workspace/25.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/25.edn_err.1020981074
Short name	T230
Test name
Test status
Simulation time	29993443 ps
CPU time	1.07 seconds
Started	Jan 10 01:19:30 PM PST 24
Finished	Jan 10 01:19:47 PM PST 24
Peak memory	230104 kb
Host	smart-080c59ad-e6ba-4d33-bb58-140eaa13a5ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1020981074 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.1020981074
Directory	/workspace/25.edn_err/latest

Test location	/workspace/coverage/default/25.edn_genbits.4035310428
Short name	T283
Test name
Test status
Simulation time	46452656 ps
CPU time	1.17 seconds
Started	Jan 10 01:19:27 PM PST 24
Finished	Jan 10 01:19:43 PM PST 24
Peak memory	214280 kb
Host	smart-72c33eaa-9966-4354-93da-22d4b7b3df69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4035310428 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.4035310428
Directory	/workspace/25.edn_genbits/latest

Test location	/workspace/coverage/default/25.edn_intr.1464084604
Short name	T630
Test name
Test status
Simulation time	70247047 ps
CPU time	0.8 seconds
Started	Jan 10 01:19:31 PM PST 24
Finished	Jan 10 01:19:47 PM PST 24
Peak memory	214288 kb
Host	smart-e2ff5148-8ef4-4acb-9759-2425be56a499
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1464084604 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.1464084604
Directory	/workspace/25.edn_intr/latest

Test location	/workspace/coverage/default/25.edn_smoke.4191151128
Short name	T814
Test name
Test status
Simulation time	13677630 ps
CPU time	0.87 seconds
Started	Jan 10 01:19:38 PM PST 24
Finished	Jan 10 01:19:53 PM PST 24
Peak memory	204804 kb
Host	smart-c74cfab6-720c-4a6a-81fd-a01e494cf11b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4191151128 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.4191151128
Directory	/workspace/25.edn_smoke/latest

Test location	/workspace/coverage/default/25.edn_stress_all.2035013205
Short name	T801
Test name
Test status
Simulation time	60682100 ps
CPU time	1.71 seconds
Started	Jan 10 01:19:29 PM PST 24
Finished	Jan 10 01:19:46 PM PST 24
Peak memory	205656 kb
Host	smart-2c44524c-2034-467f-a9e9-039ff895490a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035013205 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2035013205
Directory	/workspace/25.edn_stress_all/latest

Test location	/workspace/coverage/default/25.edn_stress_all_with_rand_reset.415326066
Short name	T864
Test name
Test status
Simulation time	61824620808 ps
CPU time	552.39 seconds
Started	Jan 10 01:19:27 PM PST 24
Finished	Jan 10 01:28:54 PM PST 24
Peak memory	214492 kb
Host	smart-580ab407-f912-44a9-85c5-f22b754c0390
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415326066 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.415326066
Directory	/workspace/25.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/250.edn_genbits.2654163735
Short name	T835
Test name
Test status
Simulation time	23155652 ps
CPU time	0.91 seconds
Started	Jan 10 01:21:05 PM PST 24
Finished	Jan 10 01:21:10 PM PST 24
Peak memory	205228 kb
Host	smart-dd9c7202-60ff-4394-89c4-611336e842a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2654163735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.2654163735
Directory	/workspace/250.edn_genbits/latest

Test location	/workspace/coverage/default/251.edn_genbits.1405638691
Short name	T607
Test name
Test status
Simulation time	24801441 ps
CPU time	1.21 seconds
Started	Jan 10 01:21:32 PM PST 24
Finished	Jan 10 01:21:54 PM PST 24
Peak memory	214360 kb
Host	smart-0d385ce5-2720-4946-b98f-9eb2228991b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1405638691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.1405638691
Directory	/workspace/251.edn_genbits/latest

Test location	/workspace/coverage/default/252.edn_genbits.4205685637
Short name	T748
Test name
Test status
Simulation time	21745632 ps
CPU time	1.16 seconds
Started	Jan 10 01:21:30 PM PST 24
Finished	Jan 10 01:21:48 PM PST 24
Peak memory	205288 kb
Host	smart-d1292012-8e0a-4c07-8354-e4d04bb1ac1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4205685637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.4205685637
Directory	/workspace/252.edn_genbits/latest

Test location	/workspace/coverage/default/253.edn_genbits.1398015203
Short name	T836
Test name
Test status
Simulation time	20822029 ps
CPU time	0.9 seconds
Started	Jan 10 01:21:32 PM PST 24
Finished	Jan 10 01:21:52 PM PST 24
Peak memory	205432 kb
Host	smart-909c4147-41e8-46ec-8fc2-d76367894715
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1398015203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.1398015203
Directory	/workspace/253.edn_genbits/latest

Test location	/workspace/coverage/default/254.edn_genbits.3591062845
Short name	T762
Test name
Test status
Simulation time	470220179 ps
CPU time	4.53 seconds
Started	Jan 10 01:21:38 PM PST 24
Finished	Jan 10 01:22:00 PM PST 24
Peak memory	214336 kb
Host	smart-01d361aa-e755-4039-8c76-ac4641bf9aa8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3591062845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.3591062845
Directory	/workspace/254.edn_genbits/latest

Test location	/workspace/coverage/default/255.edn_genbits.1397525393
Short name	T705
Test name
Test status
Simulation time	43646260 ps
CPU time	1.05 seconds
Started	Jan 10 01:21:40 PM PST 24
Finished	Jan 10 01:22:02 PM PST 24
Peak memory	205472 kb
Host	smart-efae744f-0580-408c-8178-e5a29fb12126
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1397525393 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.1397525393
Directory	/workspace/255.edn_genbits/latest

Test location	/workspace/coverage/default/256.edn_genbits.2533814447
Short name	T875
Test name
Test status
Simulation time	52684457 ps
CPU time	1.55 seconds
Started	Jan 10 01:21:37 PM PST 24
Finished	Jan 10 01:21:56 PM PST 24
Peak memory	214324 kb
Host	smart-7f69bd86-4c10-46b3-bf84-0796e1e01d51
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2533814447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.2533814447
Directory	/workspace/256.edn_genbits/latest

Test location	/workspace/coverage/default/257.edn_genbits.1251734520
Short name	T842
Test name
Test status
Simulation time	52693225 ps
CPU time	1.06 seconds
Started	Jan 10 01:21:40 PM PST 24
Finished	Jan 10 01:22:01 PM PST 24
Peak memory	205940 kb
Host	smart-6a6a627c-cc99-41de-b6f4-f53f4fa5b3dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1251734520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.1251734520
Directory	/workspace/257.edn_genbits/latest

Test location	/workspace/coverage/default/258.edn_genbits.1649874523
Short name	T68
Test name
Test status
Simulation time	13144487 ps
CPU time	0.92 seconds
Started	Jan 10 01:21:38 PM PST 24
Finished	Jan 10 01:21:58 PM PST 24
Peak memory	205304 kb
Host	smart-27ce7151-1960-4412-acbe-379af5adac92
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1649874523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.1649874523
Directory	/workspace/258.edn_genbits/latest

Test location	/workspace/coverage/default/259.edn_genbits.3136037516
Short name	T497
Test name
Test status
Simulation time	132786792 ps
CPU time	2.88 seconds
Started	Jan 10 01:21:34 PM PST 24
Finished	Jan 10 01:21:56 PM PST 24
Peak memory	214308 kb
Host	smart-e1116f5a-e905-41e1-954a-6433885a36c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3136037516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.3136037516
Directory	/workspace/259.edn_genbits/latest

Test location	/workspace/coverage/default/26.edn_alert_test.572808206
Short name	T872
Test name
Test status
Simulation time	15987256 ps
CPU time	0.89 seconds
Started	Jan 10 01:19:39 PM PST 24
Finished	Jan 10 01:19:54 PM PST 24
Peak memory	204676 kb
Host	smart-6bf12ba5-eb3e-4ca7-9dfa-f5830e9670bd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572808206 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.572808206
Directory	/workspace/26.edn_alert_test/latest

Test location	/workspace/coverage/default/26.edn_disable_auto_req_mode.4019179707
Short name	T514
Test name
Test status
Simulation time	55179595 ps
CPU time	0.95 seconds
Started	Jan 10 01:19:27 PM PST 24
Finished	Jan 10 01:19:43 PM PST 24
Peak memory	214596 kb
Host	smart-6892a734-5ac9-49dc-8497-d8ef54194143
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019179707 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d isable_auto_req_mode.4019179707
Directory	/workspace/26.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/26.edn_err.3997772883
Short name	T611
Test name
Test status
Simulation time	23884540 ps
CPU time	1.11 seconds
Started	Jan 10 01:19:39 PM PST 24
Finished	Jan 10 01:19:54 PM PST 24
Peak memory	215936 kb
Host	smart-b8614adc-640a-4ed5-be26-24cc6a5ac576
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3997772883 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.3997772883
Directory	/workspace/26.edn_err/latest

Test location	/workspace/coverage/default/26.edn_intr.1002921797
Short name	T88
Test name
Test status
Simulation time	22579411 ps
CPU time	0.94 seconds
Started	Jan 10 01:19:31 PM PST 24
Finished	Jan 10 01:19:47 PM PST 24
Peak memory	225508 kb
Host	smart-4ccad99c-506f-4679-92e2-74435ed300bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1002921797 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.1002921797
Directory	/workspace/26.edn_intr/latest

Test location	/workspace/coverage/default/26.edn_smoke.4254031908
Short name	T686
Test name
Test status
Simulation time	12386198 ps
CPU time	0.87 seconds
Started	Jan 10 01:19:35 PM PST 24
Finished	Jan 10 01:19:50 PM PST 24
Peak memory	205140 kb
Host	smart-01e35002-7ee7-47cc-bb1a-fa91c943bac2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4254031908 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.4254031908
Directory	/workspace/26.edn_smoke/latest

Test location	/workspace/coverage/default/26.edn_stress_all.4036616757
Short name	T924
Test name
Test status
Simulation time	49434296 ps
CPU time	1.01 seconds
Started	Jan 10 01:19:28 PM PST 24
Finished	Jan 10 01:19:44 PM PST 24
Peak memory	204648 kb
Host	smart-482a6434-be53-4be6-bfc9-7dbddb93dfbc
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036616757 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.4036616757
Directory	/workspace/26.edn_stress_all/latest

Test location	/workspace/coverage/default/26.edn_stress_all_with_rand_reset.1458608679
Short name	T102
Test name
Test status
Simulation time	90264891084 ps
CPU time	1870.38 seconds
Started	Jan 10 01:19:38 PM PST 24
Finished	Jan 10 01:51:02 PM PST 24
Peak memory	221240 kb
Host	smart-5b2b33d8-a11a-4d5e-b124-3335a252ef01
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458608679 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.1458608679
Directory	/workspace/26.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/260.edn_genbits.1748664648
Short name	T948
Test name
Test status
Simulation time	47889848 ps
CPU time	0.88 seconds
Started	Jan 10 01:21:38 PM PST 24
Finished	Jan 10 01:21:58 PM PST 24
Peak memory	205260 kb
Host	smart-253d5f93-8592-4d4f-8223-2ba201764852
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1748664648 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.1748664648
Directory	/workspace/260.edn_genbits/latest

Test location	/workspace/coverage/default/261.edn_genbits.2720691018
Short name	T463
Test name
Test status
Simulation time	44076812 ps
CPU time	0.89 seconds
Started	Jan 10 01:21:38 PM PST 24
Finished	Jan 10 01:21:58 PM PST 24
Peak memory	205108 kb
Host	smart-d6605c36-a249-4b6f-af08-483560f617ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2720691018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.2720691018
Directory	/workspace/261.edn_genbits/latest

Test location	/workspace/coverage/default/262.edn_genbits.1947728454
Short name	T577
Test name
Test status
Simulation time	41100506 ps
CPU time	0.97 seconds
Started	Jan 10 01:21:38 PM PST 24
Finished	Jan 10 01:21:56 PM PST 24
Peak memory	205460 kb
Host	smart-93cc30fd-cb30-4a6a-9459-60fdbdbe8d9b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1947728454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.1947728454
Directory	/workspace/262.edn_genbits/latest

Test location	/workspace/coverage/default/264.edn_genbits.3457726332
Short name	T503
Test name
Test status
Simulation time	23360366 ps
CPU time	1.27 seconds
Started	Jan 10 01:21:02 PM PST 24
Finished	Jan 10 01:21:07 PM PST 24
Peak memory	214264 kb
Host	smart-2ffe8473-73c2-4c7c-9160-55e25ce8459c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3457726332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.3457726332
Directory	/workspace/264.edn_genbits/latest

Test location	/workspace/coverage/default/265.edn_genbits.3799071964
Short name	T830
Test name
Test status
Simulation time	21792691 ps
CPU time	1.05 seconds
Started	Jan 10 01:21:40 PM PST 24
Finished	Jan 10 01:22:01 PM PST 24
Peak memory	205396 kb
Host	smart-69451f31-7776-43b7-a14a-af547f263525
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3799071964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.3799071964
Directory	/workspace/265.edn_genbits/latest

Test location	/workspace/coverage/default/266.edn_genbits.140769293
Short name	T703
Test name
Test status
Simulation time	32853450 ps
CPU time	1.08 seconds
Started	Jan 10 01:21:40 PM PST 24
Finished	Jan 10 01:22:02 PM PST 24
Peak memory	205732 kb
Host	smart-1a1d75d7-b61e-4d82-bbd1-bbf40f503225
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=140769293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.140769293
Directory	/workspace/266.edn_genbits/latest

Test location	/workspace/coverage/default/267.edn_genbits.40216617
Short name	T739
Test name
Test status
Simulation time	61977344 ps
CPU time	1.19 seconds
Started	Jan 10 01:21:37 PM PST 24
Finished	Jan 10 01:21:56 PM PST 24
Peak memory	214252 kb
Host	smart-94674d7c-79d5-4895-a8a3-35e0ac51ba1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=40216617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.40216617
Directory	/workspace/267.edn_genbits/latest

Test location	/workspace/coverage/default/268.edn_genbits.1497389624
Short name	T755
Test name
Test status
Simulation time	36182353 ps
CPU time	1.6 seconds
Started	Jan 10 01:21:40 PM PST 24
Finished	Jan 10 01:22:01 PM PST 24
Peak memory	214344 kb
Host	smart-6a9df698-18e5-4d12-9b49-c6be853a6ab9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1497389624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1497389624
Directory	/workspace/268.edn_genbits/latest

Test location	/workspace/coverage/default/269.edn_genbits.307502039
Short name	T676
Test name
Test status
Simulation time	135329748 ps
CPU time	1.08 seconds
Started	Jan 10 01:21:40 PM PST 24
Finished	Jan 10 01:22:01 PM PST 24
Peak memory	205368 kb
Host	smart-9d797e5f-98cb-4d2a-8594-5529cb13fdbc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=307502039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.307502039
Directory	/workspace/269.edn_genbits/latest

Test location	/workspace/coverage/default/27.edn_alert.1195232552
Short name	T17
Test name
Test status
Simulation time	60902817 ps
CPU time	0.91 seconds
Started	Jan 10 01:19:39 PM PST 24
Finished	Jan 10 01:19:54 PM PST 24
Peak memory	206092 kb
Host	smart-c4f529b1-182a-47eb-b903-ee18d1464d33
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1195232552 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.1195232552
Directory	/workspace/27.edn_alert/latest

Test location	/workspace/coverage/default/27.edn_alert_test.2120473938
Short name	T57
Test name
Test status
Simulation time	26634086 ps
CPU time	0.89 seconds
Started	Jan 10 01:19:33 PM PST 24
Finished	Jan 10 01:19:50 PM PST 24
Peak memory	204764 kb
Host	smart-6d06c8ae-a0ff-4cc6-86c4-0c1846aaf552
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120473938 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.2120473938
Directory	/workspace/27.edn_alert_test/latest

Test location	/workspace/coverage/default/27.edn_disable.1331432830
Short name	T614
Test name
Test status
Simulation time	14179082 ps
CPU time	0.81 seconds
Started	Jan 10 01:19:38 PM PST 24
Finished	Jan 10 01:19:53 PM PST 24
Peak memory	214516 kb
Host	smart-c0a22778-0383-450d-9e28-3a3da00d47e1
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331432830 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.1331432830
Directory	/workspace/27.edn_disable/latest

Test location	/workspace/coverage/default/27.edn_err.2157126646
Short name	T245
Test name
Test status
Simulation time	18806725 ps
CPU time	0.94 seconds
Started	Jan 10 01:19:39 PM PST 24
Finished	Jan 10 01:19:54 PM PST 24
Peak memory	215860 kb
Host	smart-bdbd9450-ba14-4a9e-9946-a0b80015f5bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2157126646 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.2157126646
Directory	/workspace/27.edn_err/latest

Test location	/workspace/coverage/default/27.edn_genbits.1948625687
Short name	T849
Test name
Test status
Simulation time	29702372 ps
CPU time	0.9 seconds
Started	Jan 10 01:19:40 PM PST 24
Finished	Jan 10 01:19:54 PM PST 24
Peak memory	205304 kb
Host	smart-3fae386d-4bb0-4c98-80aa-061ba2508930
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1948625687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.1948625687
Directory	/workspace/27.edn_genbits/latest

Test location	/workspace/coverage/default/27.edn_intr.3950833707
Short name	T648
Test name
Test status
Simulation time	20202726 ps
CPU time	0.98 seconds
Started	Jan 10 01:19:28 PM PST 24
Finished	Jan 10 01:19:44 PM PST 24
Peak memory	214444 kb
Host	smart-a8a39217-ed9e-4f5c-bd2b-7740dc1d3cd3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3950833707 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.3950833707
Directory	/workspace/27.edn_intr/latest

Test location	/workspace/coverage/default/27.edn_smoke.2822873540
Short name	T729
Test name
Test status
Simulation time	38827713 ps
CPU time	0.88 seconds
Started	Jan 10 01:19:33 PM PST 24
Finished	Jan 10 01:19:49 PM PST 24
Peak memory	204960 kb
Host	smart-fc266439-06f8-41b6-b979-c9b302efeb3c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2822873540 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.2822873540
Directory	/workspace/27.edn_smoke/latest

Test location	/workspace/coverage/default/27.edn_stress_all.1232305669
Short name	T751
Test name
Test status
Simulation time	277860086 ps
CPU time	3.05 seconds
Started	Jan 10 01:19:33 PM PST 24
Finished	Jan 10 01:19:52 PM PST 24
Peak memory	206140 kb
Host	smart-4306334c-ad47-47df-a558-b91c93ea33bd
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232305669 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.1232305669
Directory	/workspace/27.edn_stress_all/latest

Test location	/workspace/coverage/default/27.edn_stress_all_with_rand_reset.2705783711
Short name	T492
Test name
Test status
Simulation time	126438884084 ps
CPU time	1329.16 seconds
Started	Jan 10 01:19:38 PM PST 24
Finished	Jan 10 01:42:02 PM PST 24
Peak memory	219844 kb
Host	smart-e1dd9575-abbc-436c-878e-e7d8812e4950
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705783711 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.2705783711
Directory	/workspace/27.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/270.edn_genbits.2166673112
Short name	T613
Test name
Test status
Simulation time	18270508 ps
CPU time	0.98 seconds
Started	Jan 10 01:21:41 PM PST 24
Finished	Jan 10 01:22:02 PM PST 24
Peak memory	205608 kb
Host	smart-6e144a99-7836-4dc2-be1a-dc39889da8d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2166673112 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2166673112
Directory	/workspace/270.edn_genbits/latest

Test location	/workspace/coverage/default/271.edn_genbits.4236375908
Short name	T331
Test name
Test status
Simulation time	23323544 ps
CPU time	0.9 seconds
Started	Jan 10 01:21:39 PM PST 24
Finished	Jan 10 01:21:59 PM PST 24
Peak memory	205208 kb
Host	smart-606f9695-dd20-402c-9dc4-7ee1ca3dfa7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4236375908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.4236375908
Directory	/workspace/271.edn_genbits/latest

Test location	/workspace/coverage/default/272.edn_genbits.3382725931
Short name	T334
Test name
Test status
Simulation time	14682113 ps
CPU time	0.94 seconds
Started	Jan 10 01:21:43 PM PST 24
Finished	Jan 10 01:22:06 PM PST 24
Peak memory	205208 kb
Host	smart-aff5fc72-4c9e-4e72-ae2a-e6d3e7c49f94
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3382725931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.3382725931
Directory	/workspace/272.edn_genbits/latest

Test location	/workspace/coverage/default/273.edn_genbits.463057546
Short name	T546
Test name
Test status
Simulation time	256599496 ps
CPU time	3.27 seconds
Started	Jan 10 01:21:42 PM PST 24
Finished	Jan 10 01:22:07 PM PST 24
Peak memory	214428 kb
Host	smart-3b8b2e3e-dde2-4301-a03f-b14589a45285
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=463057546 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.463057546
Directory	/workspace/273.edn_genbits/latest

Test location	/workspace/coverage/default/274.edn_genbits.1942916051
Short name	T56
Test name
Test status
Simulation time	97605851 ps
CPU time	0.96 seconds
Started	Jan 10 01:21:48 PM PST 24
Finished	Jan 10 01:22:14 PM PST 24
Peak memory	205260 kb
Host	smart-8face810-1ecf-4d4b-95f1-840d9d5758ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1942916051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.1942916051
Directory	/workspace/274.edn_genbits/latest

Test location	/workspace/coverage/default/275.edn_genbits.2400318939
Short name	T744
Test name
Test status
Simulation time	77681772 ps
CPU time	0.98 seconds
Started	Jan 10 01:21:40 PM PST 24
Finished	Jan 10 01:22:00 PM PST 24
Peak memory	205680 kb
Host	smart-6ebd1726-2690-469a-83f6-925fbdb826ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2400318939 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2400318939
Directory	/workspace/275.edn_genbits/latest

Test location	/workspace/coverage/default/276.edn_genbits.3553617484
Short name	T779
Test name
Test status
Simulation time	16813262 ps
CPU time	0.93 seconds
Started	Jan 10 01:21:46 PM PST 24
Finished	Jan 10 01:22:13 PM PST 24
Peak memory	205268 kb
Host	smart-c7ef68b8-d030-47db-b2b9-1b7121813c87
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3553617484 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3553617484
Directory	/workspace/276.edn_genbits/latest

Test location	/workspace/coverage/default/277.edn_genbits.402269853
Short name	T526
Test name
Test status
Simulation time	119065098 ps
CPU time	0.95 seconds
Started	Jan 10 01:21:41 PM PST 24
Finished	Jan 10 01:22:04 PM PST 24
Peak memory	205272 kb
Host	smart-e4238e44-305d-4890-a8d7-8d3d8133b9ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=402269853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.402269853
Directory	/workspace/277.edn_genbits/latest

Test location	/workspace/coverage/default/278.edn_genbits.1888562512
Short name	T620
Test name
Test status
Simulation time	177969540 ps
CPU time	0.91 seconds
Started	Jan 10 01:21:42 PM PST 24
Finished	Jan 10 01:22:04 PM PST 24
Peak memory	205132 kb
Host	smart-6b35feb1-0344-4a4e-ae4b-8b054e554c7e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1888562512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.1888562512
Directory	/workspace/278.edn_genbits/latest

Test location	/workspace/coverage/default/279.edn_genbits.3871738386
Short name	T743
Test name
Test status
Simulation time	22767247 ps
CPU time	0.9 seconds
Started	Jan 10 01:21:45 PM PST 24
Finished	Jan 10 01:22:09 PM PST 24
Peak memory	205244 kb
Host	smart-238bd42c-3e17-4cb8-bc82-d84b4253376e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3871738386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.3871738386
Directory	/workspace/279.edn_genbits/latest

Test location	/workspace/coverage/default/28.edn_alert.2934689851
Short name	T935
Test name
Test status
Simulation time	71423491 ps
CPU time	0.92 seconds
Started	Jan 10 01:19:40 PM PST 24
Finished	Jan 10 01:19:54 PM PST 24
Peak memory	206052 kb
Host	smart-a69956bd-dde1-45c3-872f-4e0f55d1446f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2934689851 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.2934689851
Directory	/workspace/28.edn_alert/latest

Test location	/workspace/coverage/default/28.edn_alert_test.2031549323
Short name	T742
Test name
Test status
Simulation time	31758946 ps
CPU time	0.92 seconds
Started	Jan 10 01:19:29 PM PST 24
Finished	Jan 10 01:19:45 PM PST 24
Peak memory	205308 kb
Host	smart-af1fb2ae-7b28-4cec-8a3a-b2b331a19e1e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031549323 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.2031549323
Directory	/workspace/28.edn_alert_test/latest

Test location	/workspace/coverage/default/28.edn_disable.2669953959
Short name	T793
Test name
Test status
Simulation time	23151708 ps
CPU time	0.9 seconds
Started	Jan 10 01:19:46 PM PST 24
Finished	Jan 10 01:20:01 PM PST 24
Peak memory	214464 kb
Host	smart-9939d0b9-a10d-467a-bc4b-8fb43156a5b1
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669953959 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.2669953959
Directory	/workspace/28.edn_disable/latest

Test location	/workspace/coverage/default/28.edn_disable_auto_req_mode.1444907035
Short name	T506
Test name
Test status
Simulation time	77288473 ps
CPU time	0.97 seconds
Started	Jan 10 01:19:33 PM PST 24
Finished	Jan 10 01:19:50 PM PST 24
Peak memory	214684 kb
Host	smart-731fe619-588f-4e65-a103-5023ecf5afba
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444907035 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d isable_auto_req_mode.1444907035
Directory	/workspace/28.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/28.edn_err.4121629866
Short name	T171
Test name
Test status
Simulation time	19345762 ps
CPU time	0.97 seconds
Started	Jan 10 01:19:34 PM PST 24
Finished	Jan 10 01:19:50 PM PST 24
Peak memory	215564 kb
Host	smart-5167189b-3cb4-4cab-b82d-081127915e18
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4121629866 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.4121629866
Directory	/workspace/28.edn_err/latest

Test location	/workspace/coverage/default/28.edn_genbits.4091001024
Short name	T952
Test name
Test status
Simulation time	17874456 ps
CPU time	1.06 seconds
Started	Jan 10 01:19:39 PM PST 24
Finished	Jan 10 01:19:54 PM PST 24
Peak memory	205280 kb
Host	smart-2fec78bb-2e55-4b2b-aa7e-41f9d4f3ef06
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4091001024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.4091001024
Directory	/workspace/28.edn_genbits/latest

Test location	/workspace/coverage/default/28.edn_intr.342412399
Short name	T634
Test name
Test status
Simulation time	18048181 ps
CPU time	1.07 seconds
Started	Jan 10 01:19:39 PM PST 24
Finished	Jan 10 01:19:54 PM PST 24
Peak memory	225620 kb
Host	smart-68e79377-92e8-45b9-bbfe-4a6511a59c1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=342412399 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.342412399
Directory	/workspace/28.edn_intr/latest

Test location	/workspace/coverage/default/28.edn_smoke.3777028896
Short name	T20
Test name
Test status
Simulation time	24853598 ps
CPU time	0.88 seconds
Started	Jan 10 01:19:28 PM PST 24
Finished	Jan 10 01:19:44 PM PST 24
Peak memory	205044 kb
Host	smart-b1ceed6d-5827-4174-b169-6c635c8711bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3777028896 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.3777028896
Directory	/workspace/28.edn_smoke/latest

Test location	/workspace/coverage/default/28.edn_stress_all.1513793289
Short name	T968
Test name
Test status
Simulation time	101146102 ps
CPU time	1.55 seconds
Started	Jan 10 01:19:29 PM PST 24
Finished	Jan 10 01:19:46 PM PST 24
Peak memory	205864 kb
Host	smart-bf08a8e6-6cac-4f87-afb9-200ae795cf24
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513793289 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.1513793289
Directory	/workspace/28.edn_stress_all/latest

Test location	/workspace/coverage/default/28.edn_stress_all_with_rand_reset.46622318
Short name	T462
Test name
Test status
Simulation time	28592396822 ps
CPU time	317.92 seconds
Started	Jan 10 01:19:34 PM PST 24
Finished	Jan 10 01:25:07 PM PST 24
Peak memory	215636 kb
Host	smart-4f956b8f-3aa5-4f20-b06d-1cf4704d080f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46622318 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.46622318
Directory	/workspace/28.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/280.edn_genbits.3714137626
Short name	T550
Test name
Test status
Simulation time	390547527 ps
CPU time	1.12 seconds
Started	Jan 10 01:21:49 PM PST 24
Finished	Jan 10 01:22:15 PM PST 24
Peak memory	205280 kb
Host	smart-f535a127-c20c-4a1a-afc3-0047ef4c1f44
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3714137626 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.3714137626
Directory	/workspace/280.edn_genbits/latest

Test location	/workspace/coverage/default/281.edn_genbits.1613876918
Short name	T596
Test name
Test status
Simulation time	58953223 ps
CPU time	0.94 seconds
Started	Jan 10 01:21:45 PM PST 24
Finished	Jan 10 01:22:10 PM PST 24
Peak memory	205460 kb
Host	smart-bdda4939-944d-4df7-aad0-8d1bfac70d4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1613876918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.1613876918
Directory	/workspace/281.edn_genbits/latest

Test location	/workspace/coverage/default/282.edn_genbits.1148872960
Short name	T926
Test name
Test status
Simulation time	27279416 ps
CPU time	0.93 seconds
Started	Jan 10 01:21:45 PM PST 24
Finished	Jan 10 01:22:10 PM PST 24
Peak memory	205252 kb
Host	smart-4d911aff-de2f-4bbd-a79c-a4fc09d320eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1148872960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.1148872960
Directory	/workspace/282.edn_genbits/latest

Test location	/workspace/coverage/default/283.edn_genbits.1654900559
Short name	T293
Test name
Test status
Simulation time	91480408 ps
CPU time	1.11 seconds
Started	Jan 10 01:21:46 PM PST 24
Finished	Jan 10 01:22:12 PM PST 24
Peak memory	214408 kb
Host	smart-465285a1-c385-4d51-b5e5-f9e9007350d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1654900559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.1654900559
Directory	/workspace/283.edn_genbits/latest

Test location	/workspace/coverage/default/284.edn_genbits.3402923652
Short name	T828
Test name
Test status
Simulation time	16735394 ps
CPU time	0.96 seconds
Started	Jan 10 01:21:46 PM PST 24
Finished	Jan 10 01:22:11 PM PST 24
Peak memory	205080 kb
Host	smart-9a35378a-2a20-4b64-8583-2f74432cbc7b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3402923652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.3402923652
Directory	/workspace/284.edn_genbits/latest

Test location	/workspace/coverage/default/285.edn_genbits.2902318775
Short name	T592
Test name
Test status
Simulation time	461800529 ps
CPU time	1.57 seconds
Started	Jan 10 01:21:49 PM PST 24
Finished	Jan 10 01:22:16 PM PST 24
Peak memory	214352 kb
Host	smart-de5474f1-0155-40c3-9d5c-3fba51106ac2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2902318775 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.2902318775
Directory	/workspace/285.edn_genbits/latest

Test location	/workspace/coverage/default/286.edn_genbits.153889878
Short name	T738
Test name
Test status
Simulation time	148399028 ps
CPU time	1.01 seconds
Started	Jan 10 01:21:46 PM PST 24
Finished	Jan 10 01:22:12 PM PST 24
Peak memory	205608 kb
Host	smart-b9d4ddd2-47eb-4543-864c-4ce4af3e789d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=153889878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.153889878
Directory	/workspace/286.edn_genbits/latest

Test location	/workspace/coverage/default/287.edn_genbits.934810665
Short name	T732
Test name
Test status
Simulation time	24770638 ps
CPU time	0.98 seconds
Started	Jan 10 01:21:03 PM PST 24
Finished	Jan 10 01:21:08 PM PST 24
Peak memory	214204 kb
Host	smart-284c6490-088e-4f7b-8330-ad987dbdc689
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=934810665 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.934810665
Directory	/workspace/287.edn_genbits/latest

Test location	/workspace/coverage/default/288.edn_genbits.3580985907
Short name	T954
Test name
Test status
Simulation time	56414399 ps
CPU time	0.94 seconds
Started	Jan 10 01:21:24 PM PST 24
Finished	Jan 10 01:21:30 PM PST 24
Peak memory	205040 kb
Host	smart-67f6534b-271f-4dd2-ba55-56b49c610de6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3580985907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3580985907
Directory	/workspace/288.edn_genbits/latest

Test location	/workspace/coverage/default/289.edn_genbits.2119143161
Short name	T273
Test name
Test status
Simulation time	19190353 ps
CPU time	1.07 seconds
Started	Jan 10 01:21:03 PM PST 24
Finished	Jan 10 01:21:08 PM PST 24
Peak memory	214252 kb
Host	smart-9e8f9168-3feb-411c-9cf9-46b1952786ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2119143161 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.2119143161
Directory	/workspace/289.edn_genbits/latest

Test location	/workspace/coverage/default/29.edn_alert.3248453262
Short name	T314
Test name
Test status
Simulation time	16925741 ps
CPU time	0.98 seconds
Started	Jan 10 01:19:34 PM PST 24
Finished	Jan 10 01:19:50 PM PST 24
Peak memory	206156 kb
Host	smart-44ce1d79-3f83-4dc3-8008-280edfc69db0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3248453262 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.3248453262
Directory	/workspace/29.edn_alert/latest

Test location	/workspace/coverage/default/29.edn_alert_test.78943375
Short name	T653
Test name
Test status
Simulation time	17004101 ps
CPU time	0.97 seconds
Started	Jan 10 01:19:38 PM PST 24
Finished	Jan 10 01:19:53 PM PST 24
Peak memory	204748 kb
Host	smart-b88fdc95-2078-48a2-872c-9f6f60dfcb0b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78943375 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.78943375
Directory	/workspace/29.edn_alert_test/latest

Test location	/workspace/coverage/default/29.edn_disable_auto_req_mode.996497792
Short name	T144
Test name
Test status
Simulation time	95465227 ps
CPU time	0.94 seconds
Started	Jan 10 01:19:38 PM PST 24
Finished	Jan 10 01:19:53 PM PST 24
Peak memory	214724 kb
Host	smart-f2d31213-5555-4e64-8443-467787a8fbba
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996497792 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_di sable_auto_req_mode.996497792
Directory	/workspace/29.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/29.edn_err.3763929453
Short name	T45
Test name
Test status
Simulation time	19937259 ps
CPU time	1.25 seconds
Started	Jan 10 01:19:33 PM PST 24
Finished	Jan 10 01:19:50 PM PST 24
Peak memory	221988 kb
Host	smart-2cd7a5af-d88f-4666-ba64-2e63130a6b4c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3763929453 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.3763929453
Directory	/workspace/29.edn_err/latest

Test location	/workspace/coverage/default/29.edn_genbits.2373991726
Short name	T969
Test name
Test status
Simulation time	40309036 ps
CPU time	1.26 seconds
Started	Jan 10 01:19:34 PM PST 24
Finished	Jan 10 01:19:50 PM PST 24
Peak memory	214180 kb
Host	smart-41366e11-b3ab-4f1b-9ff0-78d51e51d18a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2373991726 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.2373991726
Directory	/workspace/29.edn_genbits/latest

Test location	/workspace/coverage/default/29.edn_intr.110049954
Short name	T96
Test name
Test status
Simulation time	23210061 ps
CPU time	0.86 seconds
Started	Jan 10 01:19:35 PM PST 24
Finished	Jan 10 01:19:50 PM PST 24
Peak memory	214656 kb
Host	smart-39051771-2d23-4dbe-ae58-0328fbe36254
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=110049954 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.110049954
Directory	/workspace/29.edn_intr/latest

Test location	/workspace/coverage/default/29.edn_smoke.2450057929
Short name	T536
Test name
Test status
Simulation time	16506639 ps
CPU time	0.91 seconds
Started	Jan 10 01:19:31 PM PST 24
Finished	Jan 10 01:19:47 PM PST 24
Peak memory	204984 kb
Host	smart-e0ddfb18-e437-460f-b0e6-18b14a5f2c1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2450057929 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.2450057929
Directory	/workspace/29.edn_smoke/latest

Test location	/workspace/coverage/default/29.edn_stress_all.748592314
Short name	T290
Test name
Test status
Simulation time	208800240 ps
CPU time	2.43 seconds
Started	Jan 10 01:19:34 PM PST 24
Finished	Jan 10 01:19:51 PM PST 24
Peak memory	205980 kb
Host	smart-5dbfc6f1-5818-498d-bae9-d9bb0cd5e924
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748592314 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.748592314
Directory	/workspace/29.edn_stress_all/latest

Test location	/workspace/coverage/default/290.edn_genbits.1452267376
Short name	T31
Test name
Test status
Simulation time	22002106 ps
CPU time	0.93 seconds
Started	Jan 10 01:20:57 PM PST 24
Finished	Jan 10 01:21:02 PM PST 24
Peak memory	205644 kb
Host	smart-1c2afd0a-fd59-4e7d-90eb-7590a4736894
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1452267376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.1452267376
Directory	/workspace/290.edn_genbits/latest

Test location	/workspace/coverage/default/291.edn_genbits.1930050591
Short name	T728
Test name
Test status
Simulation time	23254628 ps
CPU time	1.28 seconds
Started	Jan 10 01:20:59 PM PST 24
Finished	Jan 10 01:21:04 PM PST 24
Peak memory	214372 kb
Host	smart-125a7496-2365-4180-945d-ddebbc854274
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1930050591 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.1930050591
Directory	/workspace/291.edn_genbits/latest

Test location	/workspace/coverage/default/292.edn_genbits.1586361415
Short name	T823
Test name
Test status
Simulation time	146078005 ps
CPU time	1 seconds
Started	Jan 10 01:21:06 PM PST 24
Finished	Jan 10 01:21:11 PM PST 24
Peak memory	205864 kb
Host	smart-ff210c74-f68d-4c55-97fa-64ebe3e3386c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1586361415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.1586361415
Directory	/workspace/292.edn_genbits/latest

Test location	/workspace/coverage/default/293.edn_genbits.936377994
Short name	T723
Test name
Test status
Simulation time	13266937 ps
CPU time	0.95 seconds
Started	Jan 10 01:20:57 PM PST 24
Finished	Jan 10 01:21:02 PM PST 24
Peak memory	205072 kb
Host	smart-3450f137-3ab0-4c77-9567-260748e23f84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=936377994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.936377994
Directory	/workspace/293.edn_genbits/latest

Test location	/workspace/coverage/default/294.edn_genbits.1091783596
Short name	T850
Test name
Test status
Simulation time	19542350 ps
CPU time	0.98 seconds
Started	Jan 10 01:21:31 PM PST 24
Finished	Jan 10 01:21:50 PM PST 24
Peak memory	205576 kb
Host	smart-bfe3f762-7322-4f7c-93d0-8ea609a3b5d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1091783596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.1091783596
Directory	/workspace/294.edn_genbits/latest

Test location	/workspace/coverage/default/295.edn_genbits.576550242
Short name	T635
Test name
Test status
Simulation time	31175345 ps
CPU time	1.02 seconds
Started	Jan 10 01:21:25 PM PST 24
Finished	Jan 10 01:21:30 PM PST 24
Peak memory	205536 kb
Host	smart-5357a773-e0b0-46a2-b41f-5b2cd16ad686
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=576550242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.576550242
Directory	/workspace/295.edn_genbits/latest

Test location	/workspace/coverage/default/296.edn_genbits.774312345
Short name	T714
Test name
Test status
Simulation time	19821463 ps
CPU time	1.09 seconds
Started	Jan 10 01:21:08 PM PST 24
Finished	Jan 10 01:21:13 PM PST 24
Peak memory	205704 kb
Host	smart-ebee5bb3-62dd-49bd-80ce-e86ffc069679
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=774312345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.774312345
Directory	/workspace/296.edn_genbits/latest

Test location	/workspace/coverage/default/297.edn_genbits.1002968599
Short name	T709
Test name
Test status
Simulation time	27122874 ps
CPU time	1.02 seconds
Started	Jan 10 01:21:04 PM PST 24
Finished	Jan 10 01:21:09 PM PST 24
Peak memory	214360 kb
Host	smart-cb7c4fc5-d893-4554-82c7-9ba1f26b8199
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1002968599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.1002968599
Directory	/workspace/297.edn_genbits/latest

Test location	/workspace/coverage/default/298.edn_genbits.3511166394
Short name	T865
Test name
Test status
Simulation time	19233614 ps
CPU time	1.04 seconds
Started	Jan 10 01:20:56 PM PST 24
Finished	Jan 10 01:21:01 PM PST 24
Peak memory	214276 kb
Host	smart-e7a916a8-b8bd-4c81-8564-a05ac652ed11
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3511166394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.3511166394
Directory	/workspace/298.edn_genbits/latest

Test location	/workspace/coverage/default/299.edn_genbits.1535455725
Short name	T299
Test name
Test status
Simulation time	15272625 ps
CPU time	0.94 seconds
Started	Jan 10 01:21:39 PM PST 24
Finished	Jan 10 01:21:59 PM PST 24
Peak memory	205356 kb
Host	smart-f5d14834-dd55-4dee-9814-987a8cf25eee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1535455725 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.1535455725
Directory	/workspace/299.edn_genbits/latest

Test location	/workspace/coverage/default/3.edn_alert.26348110
Short name	T327
Test name
Test status
Simulation time	16845084 ps
CPU time	0.95 seconds
Started	Jan 10 01:18:36 PM PST 24
Finished	Jan 10 01:18:44 PM PST 24
Peak memory	206096 kb
Host	smart-55a788df-e42e-49de-93dc-b48e2b0f0319
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=26348110 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.26348110
Directory	/workspace/3.edn_alert/latest

Test location	/workspace/coverage/default/3.edn_alert_test.4293220068
Short name	T484
Test name
Test status
Simulation time	35837012 ps
CPU time	0.77 seconds
Started	Jan 10 01:18:38 PM PST 24
Finished	Jan 10 01:18:46 PM PST 24
Peak memory	204348 kb
Host	smart-e78e4ab6-c5a5-469f-903c-07d9bb7e6d11
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293220068 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.4293220068
Directory	/workspace/3.edn_alert_test/latest

Test location	/workspace/coverage/default/3.edn_disable.80685725
Short name	T181
Test name
Test status
Simulation time	63933104 ps
CPU time	0.79 seconds
Started	Jan 10 01:18:37 PM PST 24
Finished	Jan 10 01:18:45 PM PST 24
Peak memory	214464 kb
Host	smart-5c74a592-2d3f-42e7-b8ab-04b3cae63491
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80685725 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.80685725
Directory	/workspace/3.edn_disable/latest

Test location	/workspace/coverage/default/3.edn_disable_auto_req_mode.591563624
Short name	T149
Test name
Test status
Simulation time	30580588 ps
CPU time	0.95 seconds
Started	Jan 10 01:18:39 PM PST 24
Finished	Jan 10 01:18:47 PM PST 24
Peak memory	214584 kb
Host	smart-405ce0b1-d7b5-4379-85dc-2739d1049315
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591563624 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_dis able_auto_req_mode.591563624
Directory	/workspace/3.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/3.edn_err.3277385088
Short name	T958
Test name
Test status
Simulation time	18563417 ps
CPU time	0.98 seconds
Started	Jan 10 01:18:32 PM PST 24
Finished	Jan 10 01:18:40 PM PST 24
Peak memory	215824 kb
Host	smart-b7da25cc-b9b4-450c-b7b7-7e4cf9ba7d46
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3277385088 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.3277385088
Directory	/workspace/3.edn_err/latest

Test location	/workspace/coverage/default/3.edn_genbits.2818363569
Short name	T475
Test name
Test status
Simulation time	19906311 ps
CPU time	1.16 seconds
Started	Jan 10 01:18:39 PM PST 24
Finished	Jan 10 01:18:47 PM PST 24
Peak memory	205612 kb
Host	smart-864fe5bf-f459-4041-93c0-b82d3d5056ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2818363569 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.2818363569
Directory	/workspace/3.edn_genbits/latest

Test location	/workspace/coverage/default/3.edn_intr.3865191084
Short name	T853
Test name
Test status
Simulation time	18979494 ps
CPU time	1.11 seconds
Started	Jan 10 01:18:26 PM PST 24
Finished	Jan 10 01:18:36 PM PST 24
Peak memory	221896 kb
Host	smart-5b54c3b7-eb17-44e9-9862-d19491c961a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3865191084 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.3865191084
Directory	/workspace/3.edn_intr/latest

Test location	/workspace/coverage/default/3.edn_smoke.3198563894
Short name	T819
Test name
Test status
Simulation time	14018253 ps
CPU time	0.88 seconds
Started	Jan 10 01:18:41 PM PST 24
Finished	Jan 10 01:18:49 PM PST 24
Peak memory	204896 kb
Host	smart-ccf8943e-361b-4eee-bef3-0e9a80178bbe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3198563894 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.3198563894
Directory	/workspace/3.edn_smoke/latest

Test location	/workspace/coverage/default/3.edn_stress_all.3762758720
Short name	T692
Test name
Test status
Simulation time	1372052062 ps
CPU time	3 seconds
Started	Jan 10 01:18:36 PM PST 24
Finished	Jan 10 01:18:46 PM PST 24
Peak memory	206080 kb
Host	smart-8bf31e71-b41b-4d3e-bb2a-132c5c840c1e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762758720 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.3762758720
Directory	/workspace/3.edn_stress_all/latest

Test location	/workspace/coverage/default/3.edn_stress_all_with_rand_reset.1407610450
Short name	T807
Test name
Test status
Simulation time	86968529677 ps
CPU time	907.98 seconds
Started	Jan 10 01:18:36 PM PST 24
Finished	Jan 10 01:33:51 PM PST 24
Peak memory	217320 kb
Host	smart-064a128c-bfc2-4a04-8d8b-b61538252368
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407610450 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.1407610450
Directory	/workspace/3.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/30.edn_alert.3144359086
Short name	T781
Test name
Test status
Simulation time	35885710 ps
CPU time	0.95 seconds
Started	Jan 10 01:19:40 PM PST 24
Finished	Jan 10 01:19:54 PM PST 24
Peak memory	206028 kb
Host	smart-60523072-2ba7-4715-b84a-c1113696919d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3144359086 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.3144359086
Directory	/workspace/30.edn_alert/latest

Test location	/workspace/coverage/default/30.edn_alert_test.4203870922
Short name	T716
Test name
Test status
Simulation time	107066538 ps
CPU time	0.89 seconds
Started	Jan 10 01:19:49 PM PST 24
Finished	Jan 10 01:20:03 PM PST 24
Peak memory	204824 kb
Host	smart-2c652b63-d71f-40b1-b4b9-b6d7b7de03dd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203870922 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.4203870922
Directory	/workspace/30.edn_alert_test/latest

Test location	/workspace/coverage/default/30.edn_disable.2081902272
Short name	T108
Test name
Test status
Simulation time	17275703 ps
CPU time	0.88 seconds
Started	Jan 10 01:19:47 PM PST 24
Finished	Jan 10 01:20:02 PM PST 24
Peak memory	214596 kb
Host	smart-8ae2a83f-399e-4ebd-ae48-186a4059b6f0
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081902272 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.2081902272
Directory	/workspace/30.edn_disable/latest

Test location	/workspace/coverage/default/30.edn_disable_auto_req_mode.2896581526
Short name	T140
Test name
Test status
Simulation time	31493750 ps
CPU time	1.1 seconds
Started	Jan 10 01:19:30 PM PST 24
Finished	Jan 10 01:19:47 PM PST 24
Peak memory	214724 kb
Host	smart-959fe6e3-8d95-47e3-8294-748439271087
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896581526 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d isable_auto_req_mode.2896581526
Directory	/workspace/30.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/30.edn_err.4031337393
Short name	T150
Test name
Test status
Simulation time	49278411 ps
CPU time	1.07 seconds
Started	Jan 10 01:19:49 PM PST 24
Finished	Jan 10 01:20:04 PM PST 24
Peak memory	228564 kb
Host	smart-f354f893-8d71-4baf-9d9e-053a890db8c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4031337393 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.4031337393
Directory	/workspace/30.edn_err/latest

Test location	/workspace/coverage/default/30.edn_genbits.956550808
Short name	T881
Test name
Test status
Simulation time	99434790 ps
CPU time	1.05 seconds
Started	Jan 10 01:19:40 PM PST 24
Finished	Jan 10 01:19:54 PM PST 24
Peak memory	205588 kb
Host	smart-895fa85b-3591-4a08-bf57-fa2dfd6beb52
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=956550808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.956550808
Directory	/workspace/30.edn_genbits/latest

Test location	/workspace/coverage/default/30.edn_intr.2593498410
Short name	T612
Test name
Test status
Simulation time	29615421 ps
CPU time	0.81 seconds
Started	Jan 10 01:19:39 PM PST 24
Finished	Jan 10 01:19:54 PM PST 24
Peak memory	214484 kb
Host	smart-96af53a6-93aa-4de1-a53b-949a3fcd4fbc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2593498410 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.2593498410
Directory	/workspace/30.edn_intr/latest

Test location	/workspace/coverage/default/30.edn_smoke.798207939
Short name	T606
Test name
Test status
Simulation time	19699166 ps
CPU time	0.83 seconds
Started	Jan 10 01:19:33 PM PST 24
Finished	Jan 10 01:19:50 PM PST 24
Peak memory	205248 kb
Host	smart-7956a10a-f01b-44f4-9132-3bd165fb8226
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=798207939 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.798207939
Directory	/workspace/30.edn_smoke/latest

Test location	/workspace/coverage/default/30.edn_stress_all.3023722551
Short name	T978
Test name
Test status
Simulation time	430732586 ps
CPU time	3.14 seconds
Started	Jan 10 01:19:42 PM PST 24
Finished	Jan 10 01:19:59 PM PST 24
Peak memory	206040 kb
Host	smart-331dc84b-5ac6-4aaf-a3d1-917ca6d708d5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023722551 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.3023722551
Directory	/workspace/30.edn_stress_all/latest

Test location	/workspace/coverage/default/30.edn_stress_all_with_rand_reset.2051064549
Short name	T637
Test name
Test status
Simulation time	557629159366 ps
CPU time	769.39 seconds
Started	Jan 10 01:19:40 PM PST 24
Finished	Jan 10 01:32:43 PM PST 24
Peak memory	216388 kb
Host	smart-ed14b672-8e43-491a-a49d-3f4439cfb4ce
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051064549 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.2051064549
Directory	/workspace/30.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/31.edn_alert.3085681089
Short name	T735
Test name
Test status
Simulation time	34409934 ps
CPU time	0.98 seconds
Started	Jan 10 01:19:39 PM PST 24
Finished	Jan 10 01:19:54 PM PST 24
Peak memory	205436 kb
Host	smart-33143c4d-e088-41c6-9871-73d40e809da2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3085681089 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.3085681089
Directory	/workspace/31.edn_alert/latest

Test location	/workspace/coverage/default/31.edn_alert_test.907238287
Short name	T556
Test name
Test status
Simulation time	42023030 ps
CPU time	0.83 seconds
Started	Jan 10 01:19:52 PM PST 24
Finished	Jan 10 01:20:06 PM PST 24
Peak memory	204328 kb
Host	smart-73e3ad3b-6603-4f78-84d8-4e8c72773250
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907238287 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.907238287
Directory	/workspace/31.edn_alert_test/latest

Test location	/workspace/coverage/default/31.edn_disable.1743142569
Short name	T783
Test name
Test status
Simulation time	23389840 ps
CPU time	0.83 seconds
Started	Jan 10 01:19:41 PM PST 24
Finished	Jan 10 01:19:55 PM PST 24
Peak memory	214476 kb
Host	smart-e0864b95-2890-4d36-9d3f-69692f390894
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743142569 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.1743142569
Directory	/workspace/31.edn_disable/latest

Test location	/workspace/coverage/default/31.edn_disable_auto_req_mode.3247275577
Short name	T67
Test name
Test status
Simulation time	22569112 ps
CPU time	1 seconds
Started	Jan 10 01:19:40 PM PST 24
Finished	Jan 10 01:19:55 PM PST 24
Peak memory	214640 kb
Host	smart-1ccc97ba-03bd-467e-af66-9fda6517a96e
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247275577 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d isable_auto_req_mode.3247275577
Directory	/workspace/31.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/31.edn_err.149065066
Short name	T928
Test name
Test status
Simulation time	20679987 ps
CPU time	0.97 seconds
Started	Jan 10 01:19:40 PM PST 24
Finished	Jan 10 01:19:54 PM PST 24
Peak memory	216000 kb
Host	smart-3e693673-16fb-4398-89f8-e29511240318
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=149065066 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.149065066
Directory	/workspace/31.edn_err/latest

Test location	/workspace/coverage/default/31.edn_genbits.3020408424
Short name	T832
Test name
Test status
Simulation time	47398692 ps
CPU time	1.2 seconds
Started	Jan 10 01:19:37 PM PST 24
Finished	Jan 10 01:19:52 PM PST 24
Peak memory	214300 kb
Host	smart-53bbe414-7d1a-49eb-88d7-67a56b347307
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3020408424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.3020408424
Directory	/workspace/31.edn_genbits/latest

Test location	/workspace/coverage/default/31.edn_intr.3092221201
Short name	T512
Test name
Test status
Simulation time	36875543 ps
CPU time	0.82 seconds
Started	Jan 10 01:19:39 PM PST 24
Finished	Jan 10 01:19:54 PM PST 24
Peak memory	214268 kb
Host	smart-e2b88f3a-23f1-4fc7-8ab4-ba66696fdffd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3092221201 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.3092221201
Directory	/workspace/31.edn_intr/latest

Test location	/workspace/coverage/default/31.edn_smoke.1081931499
Short name	T733
Test name
Test status
Simulation time	19917460 ps
CPU time	0.88 seconds
Started	Jan 10 01:19:38 PM PST 24
Finished	Jan 10 01:19:52 PM PST 24
Peak memory	204816 kb
Host	smart-be54e947-bfb7-4b57-b732-aac17b9b57c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1081931499 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.1081931499
Directory	/workspace/31.edn_smoke/latest

Test location	/workspace/coverage/default/31.edn_stress_all.2285816736
Short name	T671
Test name
Test status
Simulation time	722128632 ps
CPU time	4.19 seconds
Started	Jan 10 01:19:50 PM PST 24
Finished	Jan 10 01:20:09 PM PST 24
Peak memory	206072 kb
Host	smart-5dcfb8ae-61c0-458b-8445-ae791e3740b0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285816736 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.2285816736
Directory	/workspace/31.edn_stress_all/latest

Test location	/workspace/coverage/default/31.edn_stress_all_with_rand_reset.2442954645
Short name	T544
Test name
Test status
Simulation time	286517639982 ps
CPU time	1935.85 seconds
Started	Jan 10 01:19:38 PM PST 24
Finished	Jan 10 01:52:09 PM PST 24
Peak memory	222268 kb
Host	smart-392851e0-1062-4e8c-8ece-788bd8ea4c16
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442954645 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.2442954645
Directory	/workspace/31.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/32.edn_alert_test.94177975
Short name	T943
Test name
Test status
Simulation time	15278803 ps
CPU time	0.87 seconds
Started	Jan 10 01:19:47 PM PST 24
Finished	Jan 10 01:20:02 PM PST 24
Peak memory	204668 kb
Host	smart-5297f9a4-ef9c-49ea-9d6f-bf84e47b9f73
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94177975 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.94177975
Directory	/workspace/32.edn_alert_test/latest

Test location	/workspace/coverage/default/32.edn_disable_auto_req_mode.3401802074
Short name	T153
Test name
Test status
Simulation time	143888175 ps
CPU time	1.04 seconds
Started	Jan 10 01:19:38 PM PST 24
Finished	Jan 10 01:19:52 PM PST 24
Peak memory	214656 kb
Host	smart-d4f5b7e1-f634-4654-af3a-9dd73f525446
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401802074 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d isable_auto_req_mode.3401802074
Directory	/workspace/32.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/32.edn_err.1797529336
Short name	T246
Test name
Test status
Simulation time	24591364 ps
CPU time	0.96 seconds
Started	Jan 10 01:19:36 PM PST 24
Finished	Jan 10 01:19:51 PM PST 24
Peak memory	215028 kb
Host	smart-5da4d6a8-e9a3-493d-a885-6d642b88f339
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1797529336 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.1797529336
Directory	/workspace/32.edn_err/latest

Test location	/workspace/coverage/default/32.edn_genbits.3875253662
Short name	T977
Test name
Test status
Simulation time	47830042 ps
CPU time	0.84 seconds
Started	Jan 10 01:19:40 PM PST 24
Finished	Jan 10 01:19:54 PM PST 24
Peak memory	205100 kb
Host	smart-f60ca841-bed3-44a0-a478-9fbe54c0a051
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3875253662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.3875253662
Directory	/workspace/32.edn_genbits/latest

Test location	/workspace/coverage/default/32.edn_intr.1412623304
Short name	T670
Test name
Test status
Simulation time	35241488 ps
CPU time	0.84 seconds
Started	Jan 10 01:19:41 PM PST 24
Finished	Jan 10 01:19:55 PM PST 24
Peak memory	214276 kb
Host	smart-3bfeb568-7262-4a30-a1b3-0e6889b63930
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1412623304 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.1412623304
Directory	/workspace/32.edn_intr/latest

Test location	/workspace/coverage/default/32.edn_smoke.3955480883
Short name	T696
Test name
Test status
Simulation time	24542183 ps
CPU time	0.87 seconds
Started	Jan 10 01:19:52 PM PST 24
Finished	Jan 10 01:20:06 PM PST 24
Peak memory	205144 kb
Host	smart-4fffc734-0c8d-4efb-acda-a2ac1132d650
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3955480883 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.3955480883
Directory	/workspace/32.edn_smoke/latest

Test location	/workspace/coverage/default/32.edn_stress_all.1222860890
Short name	T104
Test name
Test status
Simulation time	228987991 ps
CPU time	2.49 seconds
Started	Jan 10 01:19:38 PM PST 24
Finished	Jan 10 01:19:55 PM PST 24
Peak memory	206032 kb
Host	smart-b3732c0c-dd0a-49c9-af47-a1ad03cd7ba3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222860890 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.1222860890
Directory	/workspace/32.edn_stress_all/latest

Test location	/workspace/coverage/default/32.edn_stress_all_with_rand_reset.3437182474
Short name	T284
Test name
Test status
Simulation time	102645820817 ps
CPU time	1126.36 seconds
Started	Jan 10 01:19:38 PM PST 24
Finished	Jan 10 01:38:38 PM PST 24
Peak memory	215668 kb
Host	smart-f6c700d1-6c6f-4e77-bc59-0450e90baeb4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437182474 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.3437182474
Directory	/workspace/32.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/33.edn_alert.2213518339
Short name	T318
Test name
Test status
Simulation time	16929008 ps
CPU time	0.98 seconds
Started	Jan 10 01:19:52 PM PST 24
Finished	Jan 10 01:20:06 PM PST 24
Peak memory	206092 kb
Host	smart-4aa15585-d4cb-4366-be26-fcd23dc96f46
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2213518339 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.2213518339
Directory	/workspace/33.edn_alert/latest

Test location	/workspace/coverage/default/33.edn_alert_test.2226516676
Short name	T713
Test name
Test status
Simulation time	11603425 ps
CPU time	0.92 seconds
Started	Jan 10 01:19:44 PM PST 24
Finished	Jan 10 01:19:59 PM PST 24
Peak memory	204640 kb
Host	smart-62bd141c-e753-495d-8d57-9e53c888988c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226516676 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.2226516676
Directory	/workspace/33.edn_alert_test/latest

Test location	/workspace/coverage/default/33.edn_disable.3064639411
Short name	T173
Test name
Test status
Simulation time	12308388 ps
CPU time	0.87 seconds
Started	Jan 10 01:19:41 PM PST 24
Finished	Jan 10 01:19:55 PM PST 24
Peak memory	214544 kb
Host	smart-2da587f5-6411-465e-aa63-bcd8d5b6e126
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064639411 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.3064639411
Directory	/workspace/33.edn_disable/latest

Test location	/workspace/coverage/default/33.edn_disable_auto_req_mode.443233030
Short name	T138
Test name
Test status
Simulation time	94236727 ps
CPU time	1.06 seconds
Started	Jan 10 01:19:46 PM PST 24
Finished	Jan 10 01:20:02 PM PST 24
Peak memory	214632 kb
Host	smart-3e7a9531-3c17-4c62-9150-89e5d4eaeaaf
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443233030 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_di sable_auto_req_mode.443233030
Directory	/workspace/33.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/33.edn_err.1236626165
Short name	T942
Test name
Test status
Simulation time	29183209 ps
CPU time	1.02 seconds
Started	Jan 10 01:19:42 PM PST 24
Finished	Jan 10 01:19:57 PM PST 24
Peak memory	216060 kb
Host	smart-60667588-f133-4c82-b99c-5e28f1fa1827
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1236626165 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.1236626165
Directory	/workspace/33.edn_err/latest

Test location	/workspace/coverage/default/33.edn_genbits.3268221992
Short name	T591
Test name
Test status
Simulation time	45541029 ps
CPU time	1.2 seconds
Started	Jan 10 01:19:49 PM PST 24
Finished	Jan 10 01:20:04 PM PST 24
Peak memory	205940 kb
Host	smart-d5478718-72b2-4fc7-82d8-728021b074a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3268221992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.3268221992
Directory	/workspace/33.edn_genbits/latest

Test location	/workspace/coverage/default/33.edn_intr.3928032506
Short name	T586
Test name
Test status
Simulation time	76325139 ps
CPU time	0.77 seconds
Started	Jan 10 01:19:51 PM PST 24
Finished	Jan 10 01:20:06 PM PST 24
Peak memory	214600 kb
Host	smart-03c2b688-ebfc-42fb-9085-1b47c63e87d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3928032506 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.3928032506
Directory	/workspace/33.edn_intr/latest

Test location	/workspace/coverage/default/33.edn_smoke.2387198610
Short name	T623
Test name
Test status
Simulation time	76883762 ps
CPU time	0.86 seconds
Started	Jan 10 01:19:52 PM PST 24
Finished	Jan 10 01:20:06 PM PST 24
Peak memory	204916 kb
Host	smart-b3dcc973-a308-40b7-9c9b-8e3e3f852cb2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2387198610 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.2387198610
Directory	/workspace/33.edn_smoke/latest

Test location	/workspace/coverage/default/33.edn_stress_all.3352332646
Short name	T699
Test name
Test status
Simulation time	221025087 ps
CPU time	1.51 seconds
Started	Jan 10 01:19:46 PM PST 24
Finished	Jan 10 01:20:01 PM PST 24
Peak memory	205960 kb
Host	smart-3f376770-89df-42f4-b0e7-340dfd78f758
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352332646 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3352332646
Directory	/workspace/33.edn_stress_all/latest

Test location	/workspace/coverage/default/33.edn_stress_all_with_rand_reset.1134004581
Short name	T590
Test name
Test status
Simulation time	4615738452 ps
CPU time	51.95 seconds
Started	Jan 10 01:19:40 PM PST 24
Finished	Jan 10 01:20:45 PM PST 24
Peak memory	214616 kb
Host	smart-d26f94e7-cb99-47c9-941b-93dd2f5e8970
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134004581 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.1134004581
Directory	/workspace/33.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/34.edn_alert.3404597586
Short name	T323
Test name
Test status
Simulation time	105803950 ps
CPU time	0.89 seconds
Started	Jan 10 01:19:39 PM PST 24
Finished	Jan 10 01:19:54 PM PST 24
Peak memory	205344 kb
Host	smart-8a834c90-ccc6-497f-9a9a-fe3199feee63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3404597586 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.3404597586
Directory	/workspace/34.edn_alert/latest

Test location	/workspace/coverage/default/34.edn_alert_test.1872646899
Short name	T822
Test name
Test status
Simulation time	15829694 ps
CPU time	0.95 seconds
Started	Jan 10 01:19:54 PM PST 24
Finished	Jan 10 01:20:07 PM PST 24
Peak memory	205620 kb
Host	smart-cb350e88-9b2c-434c-84cc-ddf2ec3e430b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872646899 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1872646899
Directory	/workspace/34.edn_alert_test/latest

Test location	/workspace/coverage/default/34.edn_disable_auto_req_mode.601856316
Short name	T874
Test name
Test status
Simulation time	41234567 ps
CPU time	0.99 seconds
Started	Jan 10 01:19:49 PM PST 24
Finished	Jan 10 01:20:04 PM PST 24
Peak memory	214644 kb
Host	smart-dcd7bfe3-7bd0-4490-85a8-d118fdf39b98
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601856316 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_di sable_auto_req_mode.601856316
Directory	/workspace/34.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/34.edn_err.61920561
Short name	T241
Test name
Test status
Simulation time	32465496 ps
CPU time	0.94 seconds
Started	Jan 10 01:19:52 PM PST 24
Finished	Jan 10 01:20:06 PM PST 24
Peak memory	214984 kb
Host	smart-ff3ad0fd-727a-420f-8534-cd50e1eaaa4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=61920561 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.61920561
Directory	/workspace/34.edn_err/latest

Test location	/workspace/coverage/default/34.edn_genbits.1181477143
Short name	T882
Test name
Test status
Simulation time	13816009 ps
CPU time	0.94 seconds
Started	Jan 10 01:19:44 PM PST 24
Finished	Jan 10 01:19:59 PM PST 24
Peak memory	205228 kb
Host	smart-dc1f987f-a380-4974-aa9c-8c4ac0bb38a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1181477143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.1181477143
Directory	/workspace/34.edn_genbits/latest

Test location	/workspace/coverage/default/34.edn_intr.3354453231
Short name	T628
Test name
Test status
Simulation time	26802090 ps
CPU time	0.85 seconds
Started	Jan 10 01:19:52 PM PST 24
Finished	Jan 10 01:20:06 PM PST 24
Peak memory	214584 kb
Host	smart-6e65bad4-fc12-46ba-83b1-e6e422a506cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3354453231 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.3354453231
Directory	/workspace/34.edn_intr/latest

Test location	/workspace/coverage/default/34.edn_smoke.4031085548
Short name	T820
Test name
Test status
Simulation time	57849586 ps
CPU time	0.8 seconds
Started	Jan 10 01:19:43 PM PST 24
Finished	Jan 10 01:19:58 PM PST 24
Peak memory	204808 kb
Host	smart-f6499a91-1a25-4564-b503-4c908ca0b76e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4031085548 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.4031085548
Directory	/workspace/34.edn_smoke/latest

Test location	/workspace/coverage/default/34.edn_stress_all.3471063557
Short name	T632
Test name
Test status
Simulation time	65143350 ps
CPU time	0.9 seconds
Started	Jan 10 01:19:46 PM PST 24
Finished	Jan 10 01:20:01 PM PST 24
Peak memory	204548 kb
Host	smart-7b663b27-92aa-44d5-bc25-8757a6404457
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471063557 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.3471063557
Directory	/workspace/34.edn_stress_all/latest

Test location	/workspace/coverage/default/34.edn_stress_all_with_rand_reset.3954385987
Short name	T298
Test name
Test status
Simulation time	278864017479 ps
CPU time	424.66 seconds
Started	Jan 10 01:19:43 PM PST 24
Finished	Jan 10 01:27:02 PM PST 24
Peak memory	215628 kb
Host	smart-06fbc967-57f7-48fc-92f0-95438ec3f9dc
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954385987 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.3954385987
Directory	/workspace/34.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/35.edn_alert.371693984
Short name	T251
Test name
Test status
Simulation time	38881702 ps
CPU time	0.99 seconds
Started	Jan 10 01:19:39 PM PST 24
Finished	Jan 10 01:19:54 PM PST 24
Peak memory	205152 kb
Host	smart-cd9c0018-ef74-47ce-aeb3-5703091bb828
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=371693984 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.371693984
Directory	/workspace/35.edn_alert/latest

Test location	/workspace/coverage/default/35.edn_alert_test.1937724726
Short name	T655
Test name
Test status
Simulation time	33389727 ps
CPU time	0.99 seconds
Started	Jan 10 01:19:44 PM PST 24
Finished	Jan 10 01:19:59 PM PST 24
Peak memory	204708 kb
Host	smart-3c0ed6a4-344d-4281-b546-45ca2bad7412
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937724726 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1937724726
Directory	/workspace/35.edn_alert_test/latest

Test location	/workspace/coverage/default/35.edn_disable.1537927506
Short name	T239
Test name
Test status
Simulation time	16571589 ps
CPU time	0.91 seconds
Started	Jan 10 01:19:52 PM PST 24
Finished	Jan 10 01:20:06 PM PST 24
Peak memory	214472 kb
Host	smart-10b7a070-8f71-4094-9971-d8341a5c7908
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537927506 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.1537927506
Directory	/workspace/35.edn_disable/latest

Test location	/workspace/coverage/default/35.edn_disable_auto_req_mode.1866916413
Short name	T973
Test name
Test status
Simulation time	19635055 ps
CPU time	1.01 seconds
Started	Jan 10 01:19:46 PM PST 24
Finished	Jan 10 01:20:01 PM PST 24
Peak memory	214676 kb
Host	smart-77d65e7a-646d-4f31-855c-31db9f4108b3
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866916413 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d isable_auto_req_mode.1866916413
Directory	/workspace/35.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/35.edn_err.2517990349
Short name	T145
Test name
Test status
Simulation time	30898057 ps
CPU time	1.05 seconds
Started	Jan 10 01:19:40 PM PST 24
Finished	Jan 10 01:19:55 PM PST 24
Peak memory	215880 kb
Host	smart-c0c3f275-ea8b-47c2-8b23-679ea97d3179
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2517990349 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.2517990349
Directory	/workspace/35.edn_err/latest

Test location	/workspace/coverage/default/35.edn_genbits.1211420154
Short name	T959
Test name
Test status
Simulation time	66375949 ps
CPU time	1.29 seconds
Started	Jan 10 01:19:43 PM PST 24
Finished	Jan 10 01:19:59 PM PST 24
Peak memory	214352 kb
Host	smart-32c44f0a-23c8-4d34-af6a-618aa0de966a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1211420154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.1211420154
Directory	/workspace/35.edn_genbits/latest

Test location	/workspace/coverage/default/35.edn_intr.2293604406
Short name	T675
Test name
Test status
Simulation time	18679467 ps
CPU time	0.98 seconds
Started	Jan 10 01:19:52 PM PST 24
Finished	Jan 10 01:20:06 PM PST 24
Peak memory	214732 kb
Host	smart-5ab25583-6ea2-46e4-b8c0-e1012735a61b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2293604406 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.2293604406
Directory	/workspace/35.edn_intr/latest

Test location	/workspace/coverage/default/35.edn_smoke.3817646319
Short name	T795
Test name
Test status
Simulation time	26687712 ps
CPU time	0.89 seconds
Started	Jan 10 01:19:49 PM PST 24
Finished	Jan 10 01:20:04 PM PST 24
Peak memory	204980 kb
Host	smart-4f54e5d7-1cc2-4b04-9b01-5e7bebeae532
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3817646319 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.3817646319
Directory	/workspace/35.edn_smoke/latest

Test location	/workspace/coverage/default/35.edn_stress_all_with_rand_reset.2133433500
Short name	T471
Test name
Test status
Simulation time	15750716029 ps
CPU time	332.52 seconds
Started	Jan 10 01:19:38 PM PST 24
Finished	Jan 10 01:25:24 PM PST 24
Peak memory	214440 kb
Host	smart-0887a4e1-814d-4956-b25b-22085f82241a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133433500 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.2133433500
Directory	/workspace/35.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/36.edn_alert.218394234
Short name	T953
Test name
Test status
Simulation time	18491741 ps
CPU time	1.05 seconds
Started	Jan 10 01:19:47 PM PST 24
Finished	Jan 10 01:20:02 PM PST 24
Peak memory	206076 kb
Host	smart-3e791352-5ab6-43af-86c8-b87f728e58a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=218394234 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.218394234
Directory	/workspace/36.edn_alert/latest

Test location	/workspace/coverage/default/36.edn_alert_test.2873166644
Short name	T861
Test name
Test status
Simulation time	51886768 ps
CPU time	0.8 seconds
Started	Jan 10 01:19:43 PM PST 24
Finished	Jan 10 01:19:58 PM PST 24
Peak memory	205052 kb
Host	smart-4d5c46b9-ae45-4126-8b99-f239a44806fc
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873166644 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.2873166644
Directory	/workspace/36.edn_alert_test/latest

Test location	/workspace/coverage/default/36.edn_disable.2679320949
Short name	T122
Test name
Test status
Simulation time	17773332 ps
CPU time	0.81 seconds
Started	Jan 10 01:19:48 PM PST 24
Finished	Jan 10 01:20:03 PM PST 24
Peak memory	214520 kb
Host	smart-cfec9890-0e87-4c4a-8c65-bd56316b97c5
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679320949 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.2679320949
Directory	/workspace/36.edn_disable/latest

Test location	/workspace/coverage/default/36.edn_disable_auto_req_mode.2482547656
Short name	T923
Test name
Test status
Simulation time	103952570 ps
CPU time	0.95 seconds
Started	Jan 10 01:19:38 PM PST 24
Finished	Jan 10 01:19:52 PM PST 24
Peak memory	214644 kb
Host	smart-cce6e559-dd98-4a65-9657-b24d1975cad1
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482547656 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d isable_auto_req_mode.2482547656
Directory	/workspace/36.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/36.edn_err.1755031277
Short name	T234
Test name
Test status
Simulation time	29148159 ps
CPU time	0.8 seconds
Started	Jan 10 01:19:46 PM PST 24
Finished	Jan 10 01:20:01 PM PST 24
Peak memory	215696 kb
Host	smart-9f770b66-06f5-4c24-9a33-50362e444b53
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1755031277 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1755031277
Directory	/workspace/36.edn_err/latest

Test location	/workspace/coverage/default/36.edn_genbits.989657622
Short name	T839
Test name
Test status
Simulation time	113054741 ps
CPU time	1.04 seconds
Started	Jan 10 01:19:40 PM PST 24
Finished	Jan 10 01:19:55 PM PST 24
Peak memory	206136 kb
Host	smart-2d7277c4-ff00-4ec9-89af-2a50f414e18b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=989657622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.989657622
Directory	/workspace/36.edn_genbits/latest

Test location	/workspace/coverage/default/36.edn_intr.390840762
Short name	T100
Test name
Test status
Simulation time	23361230 ps
CPU time	0.89 seconds
Started	Jan 10 01:19:42 PM PST 24
Finished	Jan 10 01:19:56 PM PST 24
Peak memory	214612 kb
Host	smart-f04572ab-63fb-43ff-8c4d-b1d3bfa880c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=390840762 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.390840762
Directory	/workspace/36.edn_intr/latest

Test location	/workspace/coverage/default/36.edn_smoke.1109141924
Short name	T750
Test name
Test status
Simulation time	27047447 ps
CPU time	0.87 seconds
Started	Jan 10 01:19:47 PM PST 24
Finished	Jan 10 01:20:02 PM PST 24
Peak memory	204964 kb
Host	smart-9d3456eb-e56c-4ecc-b862-5897bb9d1af3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1109141924 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.1109141924
Directory	/workspace/36.edn_smoke/latest

Test location	/workspace/coverage/default/36.edn_stress_all.921862950
Short name	T745
Test name
Test status
Simulation time	134807826 ps
CPU time	1.24 seconds
Started	Jan 10 01:19:38 PM PST 24
Finished	Jan 10 01:19:53 PM PST 24
Peak memory	205668 kb
Host	smart-46a30422-6209-45fe-909a-7d7ce6350b0e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921862950 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.921862950
Directory	/workspace/36.edn_stress_all/latest

Test location	/workspace/coverage/default/36.edn_stress_all_with_rand_reset.3125614726
Short name	T595
Test name
Test status
Simulation time	26078809517 ps
CPU time	554.45 seconds
Started	Jan 10 01:19:52 PM PST 24
Finished	Jan 10 01:29:20 PM PST 24
Peak memory	215840 kb
Host	smart-d448e014-caeb-4e6d-b49e-7311c72befef
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125614726 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.3125614726
Directory	/workspace/36.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/37.edn_alert.2232111180
Short name	T688
Test name
Test status
Simulation time	20764920 ps
CPU time	1 seconds
Started	Jan 10 01:19:42 PM PST 24
Finished	Jan 10 01:19:57 PM PST 24
Peak memory	205268 kb
Host	smart-381745a0-9b9a-4783-bb75-a0921ce71422
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2232111180 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.2232111180
Directory	/workspace/37.edn_alert/latest

Test location	/workspace/coverage/default/37.edn_alert_test.1841154284
Short name	T891
Test name
Test status
Simulation time	55995397 ps
CPU time	0.8 seconds
Started	Jan 10 01:20:02 PM PST 24
Finished	Jan 10 01:20:10 PM PST 24
Peak memory	204640 kb
Host	smart-0e392a15-2f3d-4362-afea-655aff786465
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841154284 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.1841154284
Directory	/workspace/37.edn_alert_test/latest

Test location	/workspace/coverage/default/37.edn_disable_auto_req_mode.2582553694
Short name	T589
Test name
Test status
Simulation time	47150617 ps
CPU time	1.02 seconds
Started	Jan 10 01:20:03 PM PST 24
Finished	Jan 10 01:20:11 PM PST 24
Peak memory	214716 kb
Host	smart-9469a4cf-d4a0-4052-aa21-ef36d7a195a5
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582553694 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d isable_auto_req_mode.2582553694
Directory	/workspace/37.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/37.edn_err.2825856216
Short name	T863
Test name
Test status
Simulation time	29079781 ps
CPU time	1.21 seconds
Started	Jan 10 01:20:22 PM PST 24
Finished	Jan 10 01:20:33 PM PST 24
Peak memory	217224 kb
Host	smart-1b2a8aca-7d01-4c63-97d7-82328d118708
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2825856216 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.2825856216
Directory	/workspace/37.edn_err/latest

Test location	/workspace/coverage/default/37.edn_genbits.3900408748
Short name	T345
Test name
Test status
Simulation time	15552338 ps
CPU time	1.02 seconds
Started	Jan 10 01:19:52 PM PST 24
Finished	Jan 10 01:20:06 PM PST 24
Peak memory	205680 kb
Host	smart-9b313015-cce0-4ded-bacf-9f134508933b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3900408748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.3900408748
Directory	/workspace/37.edn_genbits/latest

Test location	/workspace/coverage/default/37.edn_intr.1649954611
Short name	T667
Test name
Test status
Simulation time	40419706 ps
CPU time	0.9 seconds
Started	Jan 10 01:19:35 PM PST 24
Finished	Jan 10 01:19:51 PM PST 24
Peak memory	214496 kb
Host	smart-0d022c23-e5a2-4d8c-8281-1c57574e7ee0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1649954611 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.1649954611
Directory	/workspace/37.edn_intr/latest

Test location	/workspace/coverage/default/37.edn_smoke.3764193953
Short name	T848
Test name
Test status
Simulation time	13900878 ps
CPU time	0.87 seconds
Started	Jan 10 01:19:43 PM PST 24
Finished	Jan 10 01:19:58 PM PST 24
Peak memory	204700 kb
Host	smart-061df39b-681b-465d-a9ad-c662aa53d53d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3764193953 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.3764193953
Directory	/workspace/37.edn_smoke/latest

Test location	/workspace/coverage/default/37.edn_stress_all.447466855
Short name	T531
Test name
Test status
Simulation time	259120266 ps
CPU time	3.34 seconds
Started	Jan 10 01:19:52 PM PST 24
Finished	Jan 10 01:20:09 PM PST 24
Peak memory	205724 kb
Host	smart-753071eb-9e00-4c5f-a057-51b5028ea879
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447466855 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.447466855
Directory	/workspace/37.edn_stress_all/latest

Test location	/workspace/coverage/default/37.edn_stress_all_with_rand_reset.1217029942
Short name	T565
Test name
Test status
Simulation time	16470093754 ps
CPU time	206.11 seconds
Started	Jan 10 01:19:43 PM PST 24
Finished	Jan 10 01:23:23 PM PST 24
Peak memory	215280 kb
Host	smart-50ad24a1-7f40-4547-8424-ed7d85ef78b3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217029942 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.1217029942
Directory	/workspace/37.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/38.edn_alert_test.3023544542
Short name	T698
Test name
Test status
Simulation time	13592197 ps
CPU time	0.83 seconds
Started	Jan 10 01:20:12 PM PST 24
Finished	Jan 10 01:20:15 PM PST 24
Peak memory	204568 kb
Host	smart-5b7d2271-b726-4f58-a5ac-51f74dcb393f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023544542 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.3023544542
Directory	/workspace/38.edn_alert_test/latest

Test location	/workspace/coverage/default/38.edn_disable.1979467486
Short name	T790
Test name
Test status
Simulation time	16772784 ps
CPU time	0.86 seconds
Started	Jan 10 01:20:16 PM PST 24
Finished	Jan 10 01:20:20 PM PST 24
Peak memory	214648 kb
Host	smart-e39e4db0-5be0-4daf-9038-b55134e15924
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979467486 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.1979467486
Directory	/workspace/38.edn_disable/latest

Test location	/workspace/coverage/default/38.edn_disable_auto_req_mode.1864274856
Short name	T695
Test name
Test status
Simulation time	17155183 ps
CPU time	0.97 seconds
Started	Jan 10 01:20:24 PM PST 24
Finished	Jan 10 01:20:35 PM PST 24
Peak memory	215648 kb
Host	smart-4ba8c7c6-5510-4a9b-8f2a-14824f52c285
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864274856 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d isable_auto_req_mode.1864274856
Directory	/workspace/38.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/38.edn_err.4265836383
Short name	T965
Test name
Test status
Simulation time	138072070 ps
CPU time	1 seconds
Started	Jan 10 01:20:02 PM PST 24
Finished	Jan 10 01:20:10 PM PST 24
Peak memory	217216 kb
Host	smart-4d91408b-1ad4-420c-bd0b-def0195c22d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4265836383 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.4265836383
Directory	/workspace/38.edn_err/latest

Test location	/workspace/coverage/default/38.edn_genbits.3731672959
Short name	T451
Test name
Test status
Simulation time	29862073 ps
CPU time	0.91 seconds
Started	Jan 10 01:20:13 PM PST 24
Finished	Jan 10 01:20:17 PM PST 24
Peak memory	205072 kb
Host	smart-78925c2f-2909-4004-bc0a-bcf23812c317
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3731672959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.3731672959
Directory	/workspace/38.edn_genbits/latest

Test location	/workspace/coverage/default/38.edn_intr.4274333282
Short name	T806
Test name
Test status
Simulation time	79844952 ps
CPU time	0.83 seconds
Started	Jan 10 01:20:05 PM PST 24
Finished	Jan 10 01:20:11 PM PST 24
Peak memory	214524 kb
Host	smart-2801cf6d-c2c5-4d83-b326-f0b3c9004ee4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4274333282 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.4274333282
Directory	/workspace/38.edn_intr/latest

Test location	/workspace/coverage/default/38.edn_smoke.1369308256
Short name	T516
Test name
Test status
Simulation time	51794116 ps
CPU time	0.88 seconds
Started	Jan 10 01:20:13 PM PST 24
Finished	Jan 10 01:20:17 PM PST 24
Peak memory	204972 kb
Host	smart-8f8d03ef-2d5b-4219-8859-a054644d0049
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1369308256 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.1369308256
Directory	/workspace/38.edn_smoke/latest

Test location	/workspace/coverage/default/38.edn_stress_all.4279870858
Short name	T754
Test name
Test status
Simulation time	20242934 ps
CPU time	0.97 seconds
Started	Jan 10 01:20:10 PM PST 24
Finished	Jan 10 01:20:15 PM PST 24
Peak memory	204668 kb
Host	smart-21f97d61-180d-4f6e-be3b-2ddffa267625
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279870858 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.4279870858
Directory	/workspace/38.edn_stress_all/latest

Test location	/workspace/coverage/default/38.edn_stress_all_with_rand_reset.363290418
Short name	T657
Test name
Test status
Simulation time	43886966841 ps
CPU time	237.5 seconds
Started	Jan 10 01:20:30 PM PST 24
Finished	Jan 10 01:24:36 PM PST 24
Peak memory	215364 kb
Host	smart-ff08e134-6dec-42ef-83e9-cac2adae45e6
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363290418 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.363290418
Directory	/workspace/38.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/39.edn_alert.2611382262
Short name	T876
Test name
Test status
Simulation time	87712204 ps
CPU time	0.9 seconds
Started	Jan 10 01:20:11 PM PST 24
Finished	Jan 10 01:20:14 PM PST 24
Peak memory	205320 kb
Host	smart-f352fe2f-1b70-4227-b5bf-7ebbb06b1e5e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2611382262 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2611382262
Directory	/workspace/39.edn_alert/latest

Test location	/workspace/coverage/default/39.edn_alert_test.3881978117
Short name	T689
Test name
Test status
Simulation time	97325630 ps
CPU time	0.85 seconds
Started	Jan 10 01:20:05 PM PST 24
Finished	Jan 10 01:20:12 PM PST 24
Peak memory	204572 kb
Host	smart-9db71dfa-736a-4750-b6c7-5a00b80452b3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881978117 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.3881978117
Directory	/workspace/39.edn_alert_test/latest

Test location	/workspace/coverage/default/39.edn_disable.2742031569
Short name	T841
Test name
Test status
Simulation time	22589120 ps
CPU time	0.83 seconds
Started	Jan 10 01:20:15 PM PST 24
Finished	Jan 10 01:20:18 PM PST 24
Peak memory	214540 kb
Host	smart-bf3aef09-9683-4168-bc6d-abcc4e41afaa
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742031569 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2742031569
Directory	/workspace/39.edn_disable/latest

Test location	/workspace/coverage/default/39.edn_disable_auto_req_mode.2088443152
Short name	T154
Test name
Test status
Simulation time	45293131 ps
CPU time	1.03 seconds
Started	Jan 10 01:20:17 PM PST 24
Finished	Jan 10 01:20:23 PM PST 24
Peak memory	214632 kb
Host	smart-67c8793b-8cbd-4146-9a72-e31d3d00c8cb
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088443152 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d isable_auto_req_mode.2088443152
Directory	/workspace/39.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/39.edn_err.3651596562
Short name	T860
Test name
Test status
Simulation time	22818373 ps
CPU time	0.94 seconds
Started	Jan 10 01:20:03 PM PST 24
Finished	Jan 10 01:20:10 PM PST 24
Peak memory	216020 kb
Host	smart-b1ae58e6-1f8f-4f5d-8e7c-274f266ee69f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3651596562 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.3651596562
Directory	/workspace/39.edn_err/latest

Test location	/workspace/coverage/default/39.edn_intr.3539316675
Short name	T90
Test name
Test status
Simulation time	24200096 ps
CPU time	0.88 seconds
Started	Jan 10 01:20:01 PM PST 24
Finished	Jan 10 01:20:09 PM PST 24
Peak memory	214528 kb
Host	smart-94676475-b907-4fe0-8b42-459df1fca7a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3539316675 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.3539316675
Directory	/workspace/39.edn_intr/latest

Test location	/workspace/coverage/default/39.edn_smoke.2351275977
Short name	T922
Test name
Test status
Simulation time	13378764 ps
CPU time	0.89 seconds
Started	Jan 10 01:20:11 PM PST 24
Finished	Jan 10 01:20:15 PM PST 24
Peak memory	205100 kb
Host	smart-186baf9e-e0ee-4568-9bb1-4ff112741f57
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2351275977 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.2351275977
Directory	/workspace/39.edn_smoke/latest

Test location	/workspace/coverage/default/39.edn_stress_all.3100309407
Short name	T494
Test name
Test status
Simulation time	685522699 ps
CPU time	3.77 seconds
Started	Jan 10 01:20:09 PM PST 24
Finished	Jan 10 01:20:17 PM PST 24
Peak memory	206120 kb
Host	smart-12cc88c8-94a5-4ff1-9a35-05d55f10e0d2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100309407 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.3100309407
Directory	/workspace/39.edn_stress_all/latest

Test location	/workspace/coverage/default/39.edn_stress_all_with_rand_reset.3560740719
Short name	T527
Test name
Test status
Simulation time	696515845403 ps
CPU time	1796.72 seconds
Started	Jan 10 01:20:15 PM PST 24
Finished	Jan 10 01:50:14 PM PST 24
Peak memory	218292 kb
Host	smart-26cd123d-6dd4-4050-8bf1-5ef17e8b8349
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560740719 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.3560740719
Directory	/workspace/39.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/4.edn_alert.974887963
Short name	T957
Test name
Test status
Simulation time	18822917 ps
CPU time	1.01 seconds
Started	Jan 10 01:18:43 PM PST 24
Finished	Jan 10 01:18:50 PM PST 24
Peak memory	206108 kb
Host	smart-38130611-f0aa-43fc-9906-f3b8c33902e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=974887963 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.974887963
Directory	/workspace/4.edn_alert/latest

Test location	/workspace/coverage/default/4.edn_alert_test.3782706525
Short name	T538
Test name
Test status
Simulation time	24416217 ps
CPU time	0.84 seconds
Started	Jan 10 01:18:33 PM PST 24
Finished	Jan 10 01:18:41 PM PST 24
Peak memory	205488 kb
Host	smart-f20e5eb1-5956-4ddd-b678-1916e79e4432
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782706525 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.3782706525
Directory	/workspace/4.edn_alert_test/latest

Test location	/workspace/coverage/default/4.edn_disable.451490157
Short name	T236
Test name
Test status
Simulation time	28988364 ps
CPU time	0.88 seconds
Started	Jan 10 01:18:35 PM PST 24
Finished	Jan 10 01:18:43 PM PST 24
Peak memory	214560 kb
Host	smart-fd7582f2-42cd-4163-93f5-a5572c69dbf2
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451490157 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.451490157
Directory	/workspace/4.edn_disable/latest

Test location	/workspace/coverage/default/4.edn_disable_auto_req_mode.3576870173
Short name	T84
Test name
Test status
Simulation time	30576623 ps
CPU time	1.01 seconds
Started	Jan 10 01:18:37 PM PST 24
Finished	Jan 10 01:18:45 PM PST 24
Peak memory	214756 kb
Host	smart-3cf48bd4-044b-4f8f-91cb-2cac082662b1
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576870173 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di sable_auto_req_mode.3576870173
Directory	/workspace/4.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/4.edn_err.490586457
Short name	T176
Test name
Test status
Simulation time	20235321 ps
CPU time	1.18 seconds
Started	Jan 10 01:18:31 PM PST 24
Finished	Jan 10 01:18:39 PM PST 24
Peak memory	221868 kb
Host	smart-66fe5f24-0ab2-4ba4-9c1d-ca9072f4627f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=490586457 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.490586457
Directory	/workspace/4.edn_err/latest

Test location	/workspace/coverage/default/4.edn_genbits.2736475402
Short name	T936
Test name
Test status
Simulation time	98773184 ps
CPU time	2.8 seconds
Started	Jan 10 01:18:37 PM PST 24
Finished	Jan 10 01:18:46 PM PST 24
Peak memory	214180 kb
Host	smart-50cfdbfd-1151-4ef8-b875-0b3cff3c322b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2736475402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.2736475402
Directory	/workspace/4.edn_genbits/latest

Test location	/workspace/coverage/default/4.edn_intr.548484447
Short name	T94
Test name
Test status
Simulation time	21203287 ps
CPU time	0.91 seconds
Started	Jan 10 01:18:34 PM PST 24
Finished	Jan 10 01:18:42 PM PST 24
Peak memory	214764 kb
Host	smart-f9f1db8b-1903-4d93-b8a2-12180d8d7473
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=548484447 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.548484447
Directory	/workspace/4.edn_intr/latest

Test location	/workspace/coverage/default/4.edn_regwen.3433602543
Short name	T311
Test name
Test status
Simulation time	72630456 ps
CPU time	0.9 seconds
Started	Jan 10 01:18:43 PM PST 24
Finished	Jan 10 01:18:50 PM PST 24
Peak memory	204796 kb
Host	smart-41f6a963-21af-4f1b-8d25-b481f1d6d2b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3433602543 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.3433602543
Directory	/workspace/4.edn_regwen/latest

Test location	/workspace/coverage/default/4.edn_sec_cm.1464719448
Short name	T58
Test name
Test status
Simulation time	620369576 ps
CPU time	3.75 seconds
Started	Jan 10 01:18:35 PM PST 24
Finished	Jan 10 01:18:46 PM PST 24
Peak memory	232004 kb
Host	smart-c0ac54e1-1d5b-48d9-a76d-38f9f4092ed9
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464719448 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.1464719448
Directory	/workspace/4.edn_sec_cm/latest

Test location	/workspace/coverage/default/4.edn_smoke.3370387243
Short name	T533
Test name
Test status
Simulation time	45540293 ps
CPU time	0.85 seconds
Started	Jan 10 01:18:37 PM PST 24
Finished	Jan 10 01:18:45 PM PST 24
Peak memory	204840 kb
Host	smart-ac61bbe9-d969-4ed5-baf6-d9497ef78efe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3370387243 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3370387243
Directory	/workspace/4.edn_smoke/latest

Test location	/workspace/coverage/default/4.edn_stress_all.1246432326
Short name	T52
Test name
Test status
Simulation time	1206851477 ps
CPU time	1.82 seconds
Started	Jan 10 01:18:43 PM PST 24
Finished	Jan 10 01:18:51 PM PST 24
Peak memory	205804 kb
Host	smart-1c808c13-e68e-4e52-bc53-e9f57960ec3f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246432326 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1246432326
Directory	/workspace/4.edn_stress_all/latest

Test location	/workspace/coverage/default/4.edn_stress_all_with_rand_reset.1798874145
Short name	T79
Test name
Test status
Simulation time	117277528742 ps
CPU time	703.61 seconds
Started	Jan 10 01:18:37 PM PST 24
Finished	Jan 10 01:30:27 PM PST 24
Peak memory	216752 kb
Host	smart-f9e88463-0d4a-4562-85b7-8668a7642ac2
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798874145 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.1798874145
Directory	/workspace/4.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/40.edn_alert.1782863200
Short name	T322
Test name
Test status
Simulation time	69100808 ps
CPU time	0.96 seconds
Started	Jan 10 01:20:23 PM PST 24
Finished	Jan 10 01:20:34 PM PST 24
Peak memory	205488 kb
Host	smart-d6535a4a-c13a-4d16-b60e-bb4d7c01e775
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1782863200 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.1782863200
Directory	/workspace/40.edn_alert/latest

Test location	/workspace/coverage/default/40.edn_alert_test.142931408
Short name	T597
Test name
Test status
Simulation time	26417364 ps
CPU time	0.98 seconds
Started	Jan 10 01:20:20 PM PST 24
Finished	Jan 10 01:20:29 PM PST 24
Peak memory	205584 kb
Host	smart-ede28bdb-cfdb-41c3-a2bc-616edc9e9ae8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142931408 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.142931408
Directory	/workspace/40.edn_alert_test/latest

Test location	/workspace/coverage/default/40.edn_disable.2898280915
Short name	T702
Test name
Test status
Simulation time	27690263 ps
CPU time	0.79 seconds
Started	Jan 10 01:20:14 PM PST 24
Finished	Jan 10 01:20:18 PM PST 24
Peak memory	214644 kb
Host	smart-9bd80c4e-4bbf-4b8b-8e30-624798e6247a
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898280915 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.2898280915
Directory	/workspace/40.edn_disable/latest

Test location	/workspace/coverage/default/40.edn_disable_auto_req_mode.4160238299
Short name	T898
Test name
Test status
Simulation time	37853311 ps
CPU time	1 seconds
Started	Jan 10 01:20:23 PM PST 24
Finished	Jan 10 01:20:34 PM PST 24
Peak memory	214592 kb
Host	smart-d0d2c644-d630-4549-8977-1e632fdc72d0
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160238299 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d isable_auto_req_mode.4160238299
Directory	/workspace/40.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/40.edn_err.3787244013
Short name	T172
Test name
Test status
Simulation time	20915714 ps
CPU time	0.86 seconds
Started	Jan 10 01:20:12 PM PST 24
Finished	Jan 10 01:20:15 PM PST 24
Peak memory	215500 kb
Host	smart-6a8239f3-ff90-4597-9582-1378516b998c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3787244013 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.3787244013
Directory	/workspace/40.edn_err/latest

Test location	/workspace/coverage/default/40.edn_genbits.2799974085
Short name	T593
Test name
Test status
Simulation time	11994710 ps
CPU time	0.91 seconds
Started	Jan 10 01:20:30 PM PST 24
Finished	Jan 10 01:20:39 PM PST 24
Peak memory	205244 kb
Host	smart-3ab214bf-1fc7-4ea1-bf51-fbd6a6991a36
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2799974085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.2799974085
Directory	/workspace/40.edn_genbits/latest

Test location	/workspace/coverage/default/40.edn_intr.1439366416
Short name	T521
Test name
Test status
Simulation time	23199859 ps
CPU time	1.04 seconds
Started	Jan 10 01:20:15 PM PST 24
Finished	Jan 10 01:20:19 PM PST 24
Peak memory	221948 kb
Host	smart-f22d066e-8b0f-440f-b18b-643f1129647f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1439366416 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.1439366416
Directory	/workspace/40.edn_intr/latest

Test location	/workspace/coverage/default/40.edn_smoke.785707810
Short name	T720
Test name
Test status
Simulation time	15435794 ps
CPU time	0.9 seconds
Started	Jan 10 01:20:12 PM PST 24
Finished	Jan 10 01:20:15 PM PST 24
Peak memory	204820 kb
Host	smart-8f7f2a02-f62f-420d-a661-e23486a9052e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=785707810 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.785707810
Directory	/workspace/40.edn_smoke/latest

Test location	/workspace/coverage/default/40.edn_stress_all.4249234122
Short name	T906
Test name
Test status
Simulation time	400855806 ps
CPU time	2.67 seconds
Started	Jan 10 01:20:13 PM PST 24
Finished	Jan 10 01:20:19 PM PST 24
Peak memory	205972 kb
Host	smart-86b76af6-4848-40f3-8865-e2f182d4fc4a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249234122 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.4249234122
Directory	/workspace/40.edn_stress_all/latest

Test location	/workspace/coverage/default/40.edn_stress_all_with_rand_reset.4053371871
Short name	T101
Test name
Test status
Simulation time	118562070536 ps
CPU time	2012.79 seconds
Started	Jan 10 01:20:16 PM PST 24
Finished	Jan 10 01:53:54 PM PST 24
Peak memory	223140 kb
Host	smart-645b81dc-3b65-4b2e-b937-174def6bc411
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053371871 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.4053371871
Directory	/workspace/40.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/41.edn_alert.2061917611
Short name	T87
Test name
Test status
Simulation time	58913516 ps
CPU time	0.96 seconds
Started	Jan 10 01:20:04 PM PST 24
Finished	Jan 10 01:20:11 PM PST 24
Peak memory	205940 kb
Host	smart-3ae67cea-1b5c-4ecb-94ca-0b3981f8233a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2061917611 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.2061917611
Directory	/workspace/41.edn_alert/latest

Test location	/workspace/coverage/default/41.edn_alert_test.3370729670
Short name	T106
Test name
Test status
Simulation time	42720225 ps
CPU time	0.84 seconds
Started	Jan 10 01:20:13 PM PST 24
Finished	Jan 10 01:20:17 PM PST 24
Peak memory	205136 kb
Host	smart-df85629c-c8f6-42eb-8c0a-b59aacd283f0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370729670 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.3370729670
Directory	/workspace/41.edn_alert_test/latest

Test location	/workspace/coverage/default/41.edn_disable.3253140563
Short name	T840
Test name
Test status
Simulation time	11897019 ps
CPU time	0.87 seconds
Started	Jan 10 01:20:07 PM PST 24
Finished	Jan 10 01:20:13 PM PST 24
Peak memory	214540 kb
Host	smart-d5817cb8-5e2b-40d7-b5fd-15a5c5783ab7
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253140563 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.3253140563
Directory	/workspace/41.edn_disable/latest

Test location	/workspace/coverage/default/41.edn_disable_auto_req_mode.1556190024
Short name	T81
Test name
Test status
Simulation time	29599728 ps
CPU time	0.98 seconds
Started	Jan 10 01:20:10 PM PST 24
Finished	Jan 10 01:20:15 PM PST 24
Peak memory	214516 kb
Host	smart-848f836a-7a48-48ff-a06e-b1b110868d16
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556190024 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d isable_auto_req_mode.1556190024
Directory	/workspace/41.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/41.edn_err.2670562974
Short name	T92
Test name
Test status
Simulation time	34039510 ps
CPU time	0.99 seconds
Started	Jan 10 01:20:15 PM PST 24
Finished	Jan 10 01:20:18 PM PST 24
Peak memory	228516 kb
Host	smart-3dcb0656-0f13-4955-b648-84f93afb7cac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2670562974 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2670562974
Directory	/workspace/41.edn_err/latest

Test location	/workspace/coverage/default/41.edn_genbits.1768678834
Short name	T947
Test name
Test status
Simulation time	74911858 ps
CPU time	0.87 seconds
Started	Jan 10 01:20:04 PM PST 24
Finished	Jan 10 01:20:11 PM PST 24
Peak memory	205200 kb
Host	smart-616f77b8-ae67-4e17-9996-fe15aed961bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1768678834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.1768678834
Directory	/workspace/41.edn_genbits/latest

Test location	/workspace/coverage/default/41.edn_intr.3607600312
Short name	T663
Test name
Test status
Simulation time	94176038 ps
CPU time	0.76 seconds
Started	Jan 10 01:20:04 PM PST 24
Finished	Jan 10 01:20:11 PM PST 24
Peak memory	214536 kb
Host	smart-bbac88ea-fa38-499e-9873-c1fbff9eef00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3607600312 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.3607600312
Directory	/workspace/41.edn_intr/latest

Test location	/workspace/coverage/default/41.edn_smoke.2078467098
Short name	T622
Test name
Test status
Simulation time	40766552 ps
CPU time	0.9 seconds
Started	Jan 10 01:20:10 PM PST 24
Finished	Jan 10 01:20:14 PM PST 24
Peak memory	204972 kb
Host	smart-42c9f12e-10d0-48e3-a19b-97eafaa84942
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2078467098 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.2078467098
Directory	/workspace/41.edn_smoke/latest

Test location	/workspace/coverage/default/41.edn_stress_all.3420314999
Short name	T472
Test name
Test status
Simulation time	473005306 ps
CPU time	2.34 seconds
Started	Jan 10 01:20:04 PM PST 24
Finished	Jan 10 01:20:13 PM PST 24
Peak memory	205868 kb
Host	smart-21ccf910-4692-4ca4-a822-615d062a5675
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420314999 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.3420314999
Directory	/workspace/41.edn_stress_all/latest

Test location	/workspace/coverage/default/41.edn_stress_all_with_rand_reset.3887470117
Short name	T105
Test name
Test status
Simulation time	415847337072 ps
CPU time	2557.37 seconds
Started	Jan 10 01:20:05 PM PST 24
Finished	Jan 10 02:02:48 PM PST 24
Peak memory	224556 kb
Host	smart-dfbaf140-8c11-44e0-8619-80ee9bbedb71
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887470117 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.3887470117
Directory	/workspace/41.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/42.edn_alert.3029914384
Short name	T310
Test name
Test status
Simulation time	20023409 ps
CPU time	0.96 seconds
Started	Jan 10 01:20:17 PM PST 24
Finished	Jan 10 01:20:22 PM PST 24
Peak memory	206132 kb
Host	smart-dfc27be6-38ea-448e-beb1-5500826b4733
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3029914384 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.3029914384
Directory	/workspace/42.edn_alert/latest

Test location	/workspace/coverage/default/42.edn_alert_test.4121371158
Short name	T107
Test name
Test status
Simulation time	26935668 ps
CPU time	0.84 seconds
Started	Jan 10 01:20:33 PM PST 24
Finished	Jan 10 01:20:42 PM PST 24
Peak memory	204700 kb
Host	smart-0e45600c-63ac-4172-9fed-cbcaa415fc9a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121371158 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.4121371158
Directory	/workspace/42.edn_alert_test/latest

Test location	/workspace/coverage/default/42.edn_disable.1494315035
Short name	T128
Test name
Test status
Simulation time	19797247 ps
CPU time	0.81 seconds
Started	Jan 10 01:20:17 PM PST 24
Finished	Jan 10 01:20:23 PM PST 24
Peak memory	214484 kb
Host	smart-0b3f940b-e2bb-46d5-9b36-ae40b7f749e6
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494315035 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.1494315035
Directory	/workspace/42.edn_disable/latest

Test location	/workspace/coverage/default/42.edn_disable_auto_req_mode.1591372291
Short name	T141
Test name
Test status
Simulation time	28179772 ps
CPU time	1.02 seconds
Started	Jan 10 01:20:16 PM PST 24
Finished	Jan 10 01:20:20 PM PST 24
Peak memory	214684 kb
Host	smart-9b59aeee-21b4-47cd-8fe5-3ffcded97c30
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591372291 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d isable_auto_req_mode.1591372291
Directory	/workspace/42.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/42.edn_err.780401126
Short name	T161
Test name
Test status
Simulation time	67975210 ps
CPU time	0.91 seconds
Started	Jan 10 01:20:15 PM PST 24
Finished	Jan 10 01:20:19 PM PST 24
Peak memory	221176 kb
Host	smart-9d59496d-51a1-486f-a867-a0b2faeb70cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=780401126 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.780401126
Directory	/workspace/42.edn_err/latest

Test location	/workspace/coverage/default/42.edn_intr.2716206245
Short name	T16
Test name
Test status
Simulation time	26150670 ps
CPU time	1.01 seconds
Started	Jan 10 01:20:17 PM PST 24
Finished	Jan 10 01:20:23 PM PST 24
Peak memory	221936 kb
Host	smart-a594dacf-bff0-46ba-b545-528827ec7710
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2716206245 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.2716206245
Directory	/workspace/42.edn_intr/latest

Test location	/workspace/coverage/default/42.edn_smoke.3492083423
Short name	T456
Test name
Test status
Simulation time	14942880 ps
CPU time	0.93 seconds
Started	Jan 10 01:20:23 PM PST 24
Finished	Jan 10 01:20:34 PM PST 24
Peak memory	204752 kb
Host	smart-cffd5ec6-cacf-4acb-abfc-25e76c1e2100
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3492083423 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.3492083423
Directory	/workspace/42.edn_smoke/latest

Test location	/workspace/coverage/default/42.edn_stress_all.1722247791
Short name	T609
Test name
Test status
Simulation time	411559598 ps
CPU time	4.02 seconds
Started	Jan 10 01:20:20 PM PST 24
Finished	Jan 10 01:20:31 PM PST 24
Peak memory	206136 kb
Host	smart-a94c3e41-153f-48bb-ae68-a1035456e574
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722247791 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.1722247791
Directory	/workspace/42.edn_stress_all/latest

Test location	/workspace/coverage/default/42.edn_stress_all_with_rand_reset.959662584
Short name	T519
Test name
Test status
Simulation time	150234718500 ps
CPU time	486.34 seconds
Started	Jan 10 01:20:32 PM PST 24
Finished	Jan 10 01:28:46 PM PST 24
Peak memory	215148 kb
Host	smart-f7ca4ec8-81aa-411b-895d-61605d388bb3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959662584 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.959662584
Directory	/workspace/42.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/43.edn_alert.1232337365
Short name	T756
Test name
Test status
Simulation time	66816445 ps
CPU time	0.97 seconds
Started	Jan 10 01:20:16 PM PST 24
Finished	Jan 10 01:20:22 PM PST 24
Peak memory	205224 kb
Host	smart-43a38314-7965-419d-868b-e31abba8e031
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1232337365 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.1232337365
Directory	/workspace/43.edn_alert/latest

Test location	/workspace/coverage/default/43.edn_alert_test.174081931
Short name	T493
Test name
Test status
Simulation time	35531130 ps
CPU time	0.98 seconds
Started	Jan 10 01:20:20 PM PST 24
Finished	Jan 10 01:20:29 PM PST 24
Peak memory	204764 kb
Host	smart-8dafef84-9fc3-48f2-9f97-de137b777179
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174081931 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.174081931
Directory	/workspace/43.edn_alert_test/latest

Test location	/workspace/coverage/default/43.edn_disable.2012961604
Short name	T123
Test name
Test status
Simulation time	46261530 ps
CPU time	0.86 seconds
Started	Jan 10 01:20:18 PM PST 24
Finished	Jan 10 01:20:26 PM PST 24
Peak memory	214552 kb
Host	smart-1aeef9a6-2196-4a55-a4d6-efe1e2afd725
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012961604 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2012961604
Directory	/workspace/43.edn_disable/latest

Test location	/workspace/coverage/default/43.edn_disable_auto_req_mode.2679847078
Short name	T133
Test name
Test status
Simulation time	60271074 ps
CPU time	1.07 seconds
Started	Jan 10 01:20:15 PM PST 24
Finished	Jan 10 01:20:19 PM PST 24
Peak memory	206428 kb
Host	smart-be416f15-5dcd-44e7-866b-571c6344e3fa
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679847078 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d isable_auto_req_mode.2679847078
Directory	/workspace/43.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/43.edn_err.1922551142
Short name	T525
Test name
Test status
Simulation time	23043959 ps
CPU time	0.98 seconds
Started	Jan 10 01:20:17 PM PST 24
Finished	Jan 10 01:20:23 PM PST 24
Peak memory	215916 kb
Host	smart-0eb3e8f4-4a9c-4ef4-b4f8-640d3889fab2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1922551142 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.1922551142
Directory	/workspace/43.edn_err/latest

Test location	/workspace/coverage/default/43.edn_genbits.4165457130
Short name	T930
Test name
Test status
Simulation time	142908472 ps
CPU time	1.03 seconds
Started	Jan 10 01:20:22 PM PST 24
Finished	Jan 10 01:20:33 PM PST 24
Peak memory	203956 kb
Host	smart-49faad63-e0f6-4674-a582-2242c86d13c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4165457130 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.4165457130
Directory	/workspace/43.edn_genbits/latest

Test location	/workspace/coverage/default/43.edn_intr.3135008980
Short name	T566
Test name
Test status
Simulation time	20741642 ps
CPU time	1.02 seconds
Started	Jan 10 01:20:17 PM PST 24
Finished	Jan 10 01:20:24 PM PST 24
Peak memory	214424 kb
Host	smart-ea63b595-2769-46ea-86b6-67eeefe207f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3135008980 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.3135008980
Directory	/workspace/43.edn_intr/latest

Test location	/workspace/coverage/default/43.edn_smoke.2553085867
Short name	T602
Test name
Test status
Simulation time	24278207 ps
CPU time	0.86 seconds
Started	Jan 10 01:20:28 PM PST 24
Finished	Jan 10 01:20:37 PM PST 24
Peak memory	204828 kb
Host	smart-ca795b67-59df-4346-a850-d41812e14a87
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2553085867 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.2553085867
Directory	/workspace/43.edn_smoke/latest

Test location	/workspace/coverage/default/43.edn_stress_all.2727693819
Short name	T498
Test name
Test status
Simulation time	216253087 ps
CPU time	4.51 seconds
Started	Jan 10 01:20:20 PM PST 24
Finished	Jan 10 01:20:32 PM PST 24
Peak memory	206072 kb
Host	smart-4aaacce6-b25d-461e-841c-006c928bdb37
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727693819 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.2727693819
Directory	/workspace/43.edn_stress_all/latest

Test location	/workspace/coverage/default/43.edn_stress_all_with_rand_reset.940708339
Short name	T576
Test name
Test status
Simulation time	136998159051 ps
CPU time	1506.01 seconds
Started	Jan 10 01:20:19 PM PST 24
Finished	Jan 10 01:45:33 PM PST 24
Peak memory	218544 kb
Host	smart-a42c1467-d246-4856-bb73-bc3b3d397b82
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940708339 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.940708339
Directory	/workspace/43.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/44.edn_alert.2061228140
Short name	T83
Test name
Test status
Simulation time	237156437 ps
CPU time	0.93 seconds
Started	Jan 10 01:20:21 PM PST 24
Finished	Jan 10 01:20:30 PM PST 24
Peak memory	206080 kb
Host	smart-afc67c5a-05b2-40c4-b0fa-589884adcac9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2061228140 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.2061228140
Directory	/workspace/44.edn_alert/latest

Test location	/workspace/coverage/default/44.edn_alert_test.990720064
Short name	T888
Test name
Test status
Simulation time	69092768 ps
CPU time	0.91 seconds
Started	Jan 10 01:20:20 PM PST 24
Finished	Jan 10 01:20:29 PM PST 24
Peak memory	204740 kb
Host	smart-2b7b384c-bf96-40a5-9a98-f829d98f8384
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990720064 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.990720064
Directory	/workspace/44.edn_alert_test/latest

Test location	/workspace/coverage/default/44.edn_disable.1400561765
Short name	T124
Test name
Test status
Simulation time	11297119 ps
CPU time	0.83 seconds
Started	Jan 10 01:20:19 PM PST 24
Finished	Jan 10 01:20:27 PM PST 24
Peak memory	214504 kb
Host	smart-d7cf6af8-4403-4893-bee6-485529d6cac9
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400561765 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.1400561765
Directory	/workspace/44.edn_disable/latest

Test location	/workspace/coverage/default/44.edn_disable_auto_req_mode.2148022367
Short name	T469
Test name
Test status
Simulation time	153627421 ps
CPU time	1.02 seconds
Started	Jan 10 01:20:20 PM PST 24
Finished	Jan 10 01:20:28 PM PST 24
Peak memory	214748 kb
Host	smart-6e736632-e951-4f6b-aee5-a957b374e849
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148022367 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d isable_auto_req_mode.2148022367
Directory	/workspace/44.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/44.edn_err.1609048477
Short name	T651
Test name
Test status
Simulation time	35387225 ps
CPU time	0.87 seconds
Started	Jan 10 01:20:28 PM PST 24
Finished	Jan 10 01:20:37 PM PST 24
Peak memory	214572 kb
Host	smart-6536acc0-b3da-4219-9256-965140ace2eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1609048477 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.1609048477
Directory	/workspace/44.edn_err/latest

Test location	/workspace/coverage/default/44.edn_genbits.1553050283
Short name	T654
Test name
Test status
Simulation time	25514892 ps
CPU time	1.09 seconds
Started	Jan 10 01:20:21 PM PST 24
Finished	Jan 10 01:20:30 PM PST 24
Peak memory	205512 kb
Host	smart-73505ba3-7eec-44af-8b29-b9c0e5923fac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1553050283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.1553050283
Directory	/workspace/44.edn_genbits/latest

Test location	/workspace/coverage/default/44.edn_intr.1059044653
Short name	T976
Test name
Test status
Simulation time	22464152 ps
CPU time	0.89 seconds
Started	Jan 10 01:20:20 PM PST 24
Finished	Jan 10 01:20:28 PM PST 24
Peak memory	214716 kb
Host	smart-26ad6120-2890-4942-8205-705891fc0e9a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1059044653 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.1059044653
Directory	/workspace/44.edn_intr/latest

Test location	/workspace/coverage/default/44.edn_smoke.274884504
Short name	T911
Test name
Test status
Simulation time	59330626 ps
CPU time	0.8 seconds
Started	Jan 10 01:20:19 PM PST 24
Finished	Jan 10 01:20:28 PM PST 24
Peak memory	204764 kb
Host	smart-cd480ec3-044b-4837-88a0-653c9899bd7b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=274884504 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.274884504
Directory	/workspace/44.edn_smoke/latest

Test location	/workspace/coverage/default/44.edn_stress_all.2115742449
Short name	T523
Test name
Test status
Simulation time	284282302 ps
CPU time	2.98 seconds
Started	Jan 10 01:20:18 PM PST 24
Finished	Jan 10 01:20:27 PM PST 24
Peak memory	205896 kb
Host	smart-d7e45657-a0e3-4478-bbbe-85dd3debf903
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115742449 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.2115742449
Directory	/workspace/44.edn_stress_all/latest

Test location	/workspace/coverage/default/44.edn_stress_all_with_rand_reset.4156681853
Short name	T618
Test name
Test status
Simulation time	140025869987 ps
CPU time	1355.53 seconds
Started	Jan 10 01:20:32 PM PST 24
Finished	Jan 10 01:43:15 PM PST 24
Peak memory	220100 kb
Host	smart-b5430339-e08c-47a4-a828-11d544d45932
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156681853 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.4156681853
Directory	/workspace/44.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/45.edn_alert.575410442
Short name	T250
Test name
Test status
Simulation time	30885499 ps
CPU time	0.94 seconds
Started	Jan 10 01:20:20 PM PST 24
Finished	Jan 10 01:20:28 PM PST 24
Peak memory	206124 kb
Host	smart-022eb358-6a6b-4c8a-beb7-b95b18ac77d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=575410442 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.575410442
Directory	/workspace/45.edn_alert/latest

Test location	/workspace/coverage/default/45.edn_alert_test.2271074557
Short name	T897
Test name
Test status
Simulation time	24202296 ps
CPU time	0.82 seconds
Started	Jan 10 01:20:19 PM PST 24
Finished	Jan 10 01:20:27 PM PST 24
Peak memory	205276 kb
Host	smart-d65f9536-1abc-4999-90e2-a25b4f727569
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271074557 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.2271074557
Directory	/workspace/45.edn_alert_test/latest

Test location	/workspace/coverage/default/45.edn_disable.2381945385
Short name	T167
Test name
Test status
Simulation time	11017205 ps
CPU time	0.83 seconds
Started	Jan 10 01:20:17 PM PST 24
Finished	Jan 10 01:20:23 PM PST 24
Peak memory	214488 kb
Host	smart-08b87f29-7fee-4210-b2f2-96506a4fc42b
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381945385 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.2381945385
Directory	/workspace/45.edn_disable/latest

Test location	/workspace/coverage/default/45.edn_disable_auto_req_mode.3870199409
Short name	T902
Test name
Test status
Simulation time	107067343 ps
CPU time	1.15 seconds
Started	Jan 10 01:20:22 PM PST 24
Finished	Jan 10 01:20:32 PM PST 24
Peak memory	214628 kb
Host	smart-570240ed-3546-4a0a-a791-5a823254eccf
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870199409 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d isable_auto_req_mode.3870199409
Directory	/workspace/45.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/45.edn_err.1956234566
Short name	T913
Test name
Test status
Simulation time	51451604 ps
CPU time	1.32 seconds
Started	Jan 10 01:20:17 PM PST 24
Finished	Jan 10 01:20:24 PM PST 24
Peak memory	227732 kb
Host	smart-31925641-4b44-4509-97c5-c7ba37d847d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1956234566 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.1956234566
Directory	/workspace/45.edn_err/latest

Test location	/workspace/coverage/default/45.edn_genbits.1856528344
Short name	T901
Test name
Test status
Simulation time	32772822 ps
CPU time	1.03 seconds
Started	Jan 10 01:20:21 PM PST 24
Finished	Jan 10 01:20:30 PM PST 24
Peak memory	205804 kb
Host	smart-3679dc2b-1537-4e41-8de9-78add4d8c4a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1856528344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.1856528344
Directory	/workspace/45.edn_genbits/latest

Test location	/workspace/coverage/default/45.edn_intr.3248518101
Short name	T693
Test name
Test status
Simulation time	20829691 ps
CPU time	1.09 seconds
Started	Jan 10 01:20:25 PM PST 24
Finished	Jan 10 01:20:36 PM PST 24
Peak memory	221492 kb
Host	smart-b4d093c9-b695-42cd-b3fa-b8800b0264b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3248518101 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.3248518101
Directory	/workspace/45.edn_intr/latest

Test location	/workspace/coverage/default/45.edn_smoke.1688312827
Short name	T700
Test name
Test status
Simulation time	37723725 ps
CPU time	0.87 seconds
Started	Jan 10 01:20:31 PM PST 24
Finished	Jan 10 01:20:40 PM PST 24
Peak memory	205028 kb
Host	smart-5a763b7f-94fe-45d9-b89f-a5b178d39c43
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1688312827 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.1688312827
Directory	/workspace/45.edn_smoke/latest

Test location	/workspace/coverage/default/45.edn_stress_all.1051733994
Short name	T768
Test name
Test status
Simulation time	82409105 ps
CPU time	2.08 seconds
Started	Jan 10 01:20:21 PM PST 24
Finished	Jan 10 01:20:31 PM PST 24
Peak memory	206128 kb
Host	smart-72c7519a-708d-4164-b718-9f0a8d44a0fa
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051733994 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1051733994
Directory	/workspace/45.edn_stress_all/latest

Test location	/workspace/coverage/default/45.edn_stress_all_with_rand_reset.32856011
Short name	T638
Test name
Test status
Simulation time	97054957155 ps
CPU time	613.35 seconds
Started	Jan 10 01:20:20 PM PST 24
Finished	Jan 10 01:30:41 PM PST 24
Peak memory	215512 kb
Host	smart-25f5635b-24c7-4f4c-9039-b6e97db2c81c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32856011 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.32856011
Directory	/workspace/45.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/46.edn_alert.929908484
Short name	T929
Test name
Test status
Simulation time	22695308 ps
CPU time	1 seconds
Started	Jan 10 01:20:22 PM PST 24
Finished	Jan 10 01:20:32 PM PST 24
Peak memory	205924 kb
Host	smart-14691df9-2219-4df3-91f8-d970d47bf9ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=929908484 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.929908484
Directory	/workspace/46.edn_alert/latest

Test location	/workspace/coverage/default/46.edn_alert_test.3766110005
Short name	T603
Test name
Test status
Simulation time	78914237 ps
CPU time	0.86 seconds
Started	Jan 10 01:20:21 PM PST 24
Finished	Jan 10 01:20:31 PM PST 24
Peak memory	204572 kb
Host	smart-234ed554-cd77-4985-866c-cf39cf4ab308
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766110005 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.3766110005
Directory	/workspace/46.edn_alert_test/latest

Test location	/workspace/coverage/default/46.edn_disable.555748291
Short name	T76
Test name
Test status
Simulation time	13692154 ps
CPU time	0.9 seconds
Started	Jan 10 01:20:19 PM PST 24
Finished	Jan 10 01:20:27 PM PST 24
Peak memory	214592 kb
Host	smart-00c4b63b-7ea3-4ea9-9f8d-12c463159b80
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555748291 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.555748291
Directory	/workspace/46.edn_disable/latest

Test location	/workspace/coverage/default/46.edn_disable_auto_req_mode.1061286654
Short name	T866
Test name
Test status
Simulation time	30939289 ps
CPU time	1.07 seconds
Started	Jan 10 01:20:21 PM PST 24
Finished	Jan 10 01:20:30 PM PST 24
Peak memory	214720 kb
Host	smart-921d8792-1068-494f-8295-a9d9aa0e43d3
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061286654 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d isable_auto_req_mode.1061286654
Directory	/workspace/46.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/46.edn_err.3508319550
Short name	T7
Test name
Test status
Simulation time	37873480 ps
CPU time	1.33 seconds
Started	Jan 10 01:20:20 PM PST 24
Finished	Jan 10 01:20:28 PM PST 24
Peak memory	214728 kb
Host	smart-d131751d-16af-4ea2-977e-69ca5e1c52a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3508319550 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.3508319550
Directory	/workspace/46.edn_err/latest

Test location	/workspace/coverage/default/46.edn_genbits.3866274228
Short name	T627
Test name
Test status
Simulation time	16095151 ps
CPU time	1.05 seconds
Started	Jan 10 01:20:28 PM PST 24
Finished	Jan 10 01:20:38 PM PST 24
Peak memory	205252 kb
Host	smart-69861ec8-af1f-40cd-a7b4-8cde07e66d5e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3866274228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.3866274228
Directory	/workspace/46.edn_genbits/latest

Test location	/workspace/coverage/default/46.edn_intr.1950301924
Short name	T683
Test name
Test status
Simulation time	24426578 ps
CPU time	0.84 seconds
Started	Jan 10 01:20:20 PM PST 24
Finished	Jan 10 01:20:28 PM PST 24
Peak memory	214504 kb
Host	smart-a00f4ebb-5eef-47ec-8e7f-3fa7dc77a71a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1950301924 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.1950301924
Directory	/workspace/46.edn_intr/latest

Test location	/workspace/coverage/default/46.edn_smoke.1574083010
Short name	T63
Test name
Test status
Simulation time	12765854 ps
CPU time	0.83 seconds
Started	Jan 10 01:20:17 PM PST 24
Finished	Jan 10 01:20:23 PM PST 24
Peak memory	204724 kb
Host	smart-05c10730-12fc-4458-ac17-9f5d8d125f50
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1574083010 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.1574083010
Directory	/workspace/46.edn_smoke/latest

Test location	/workspace/coverage/default/46.edn_stress_all.3128989315
Short name	T228
Test name
Test status
Simulation time	607627125 ps
CPU time	3.25 seconds
Started	Jan 10 01:20:21 PM PST 24
Finished	Jan 10 01:20:32 PM PST 24
Peak memory	206180 kb
Host	smart-0ad8858b-ad44-4c03-8c77-8a8480e3d7d2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128989315 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.3128989315
Directory	/workspace/46.edn_stress_all/latest

Test location	/workspace/coverage/default/46.edn_stress_all_with_rand_reset.413052498
Short name	T724
Test name
Test status
Simulation time	259175269315 ps
CPU time	1891.52 seconds
Started	Jan 10 01:20:18 PM PST 24
Finished	Jan 10 01:51:55 PM PST 24
Peak memory	219640 kb
Host	smart-f99e88ae-c0e5-4b0d-bf48-aafe21759da7
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413052498 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.413052498
Directory	/workspace/46.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/47.edn_alert.4233521
Short name	T903
Test name
Test status
Simulation time	18417541 ps
CPU time	1.01 seconds
Started	Jan 10 01:20:17 PM PST 24
Finished	Jan 10 01:20:23 PM PST 24
Peak memory	206112 kb
Host	smart-f8af9b22-27ff-4c2f-bf96-6ba9d11b4c16
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4233521 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.4233521
Directory	/workspace/47.edn_alert/latest

Test location	/workspace/coverage/default/47.edn_alert_test.3943617917
Short name	T501
Test name
Test status
Simulation time	59855031 ps
CPU time	0.93 seconds
Started	Jan 10 01:20:21 PM PST 24
Finished	Jan 10 01:20:31 PM PST 24
Peak memory	205156 kb
Host	smart-3ecc3605-997b-48c5-8406-8ea55671ea10
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943617917 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.3943617917
Directory	/workspace/47.edn_alert_test/latest

Test location	/workspace/coverage/default/47.edn_disable.3625888006
Short name	T126
Test name
Test status
Simulation time	24215756 ps
CPU time	0.87 seconds
Started	Jan 10 01:20:21 PM PST 24
Finished	Jan 10 01:20:31 PM PST 24
Peak memory	214564 kb
Host	smart-e7292360-80a7-4c26-8aff-94e3118960b7
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625888006 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.3625888006
Directory	/workspace/47.edn_disable/latest

Test location	/workspace/coverage/default/47.edn_disable_auto_req_mode.1819169014
Short name	T939
Test name
Test status
Simulation time	184597973 ps
CPU time	1.01 seconds
Started	Jan 10 01:20:20 PM PST 24
Finished	Jan 10 01:20:29 PM PST 24
Peak memory	214680 kb
Host	smart-53c192ba-1ee9-4ee3-81e8-964dcab42f2e
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819169014 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d isable_auto_req_mode.1819169014
Directory	/workspace/47.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/47.edn_err.788227124
Short name	T673
Test name
Test status
Simulation time	20870544 ps
CPU time	0.99 seconds
Started	Jan 10 01:20:20 PM PST 24
Finished	Jan 10 01:20:28 PM PST 24
Peak memory	214464 kb
Host	smart-4b14d3ed-1da8-40f7-9b0f-8423265c0242
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=788227124 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.788227124
Directory	/workspace/47.edn_err/latest

Test location	/workspace/coverage/default/47.edn_genbits.3087574973
Short name	T22
Test name
Test status
Simulation time	22271304 ps
CPU time	1.13 seconds
Started	Jan 10 01:20:18 PM PST 24
Finished	Jan 10 01:20:26 PM PST 24
Peak memory	205476 kb
Host	smart-343dd489-e9d6-4a8c-8dfe-7171b8b04535
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3087574973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3087574973
Directory	/workspace/47.edn_genbits/latest

Test location	/workspace/coverage/default/47.edn_intr.3740045533
Short name	T555
Test name
Test status
Simulation time	18805409 ps
CPU time	1.07 seconds
Started	Jan 10 01:20:21 PM PST 24
Finished	Jan 10 01:20:31 PM PST 24
Peak memory	214484 kb
Host	smart-eddbc42d-0394-4392-a4e5-fc318a88e45d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3740045533 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.3740045533
Directory	/workspace/47.edn_intr/latest

Test location	/workspace/coverage/default/47.edn_smoke.2359214644
Short name	T476
Test name
Test status
Simulation time	19188175 ps
CPU time	0.84 seconds
Started	Jan 10 01:20:18 PM PST 24
Finished	Jan 10 01:20:24 PM PST 24
Peak memory	204972 kb
Host	smart-e7d923b9-6528-4113-98c6-739c6ead8feb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2359214644 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.2359214644
Directory	/workspace/47.edn_smoke/latest

Test location	/workspace/coverage/default/47.edn_stress_all.1465214616
Short name	T264
Test name
Test status
Simulation time	202145338 ps
CPU time	3.04 seconds
Started	Jan 10 01:20:14 PM PST 24
Finished	Jan 10 01:20:20 PM PST 24
Peak memory	205856 kb
Host	smart-02e45b53-dd2f-4676-8546-dbb12efdc01c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465214616 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.1465214616
Directory	/workspace/47.edn_stress_all/latest

Test location	/workspace/coverage/default/47.edn_stress_all_with_rand_reset.681227589
Short name	T932
Test name
Test status
Simulation time	89709434070 ps
CPU time	2178.42 seconds
Started	Jan 10 01:20:22 PM PST 24
Finished	Jan 10 01:56:51 PM PST 24
Peak memory	224804 kb
Host	smart-82225aa9-50f4-4405-8dbf-6846a5a0787b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681227589 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.681227589
Directory	/workspace/47.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/48.edn_alert.4237011167
Short name	T766
Test name
Test status
Simulation time	53660468 ps
CPU time	1.01 seconds
Started	Jan 10 01:20:45 PM PST 24
Finished	Jan 10 01:20:51 PM PST 24
Peak memory	205428 kb
Host	smart-6d150074-2087-40cc-bf08-345018105748
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4237011167 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.4237011167
Directory	/workspace/48.edn_alert/latest

Test location	/workspace/coverage/default/48.edn_alert_test.1477177134
Short name	T633
Test name
Test status
Simulation time	30625850 ps
CPU time	0.89 seconds
Started	Jan 10 01:20:42 PM PST 24
Finished	Jan 10 01:20:50 PM PST 24
Peak memory	205304 kb
Host	smart-63a72c5c-667f-4e94-92e7-16357189b74c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477177134 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.1477177134
Directory	/workspace/48.edn_alert_test/latest

Test location	/workspace/coverage/default/48.edn_disable.3135105000
Short name	T121
Test name
Test status
Simulation time	40277963 ps
CPU time	0.84 seconds
Started	Jan 10 01:20:23 PM PST 24
Finished	Jan 10 01:20:34 PM PST 24
Peak memory	214616 kb
Host	smart-dfd30a69-2c0c-43a0-a2c7-e6ac3b671618
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135105000 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.3135105000
Directory	/workspace/48.edn_disable/latest

Test location	/workspace/coverage/default/48.edn_disable_auto_req_mode.570283432
Short name	T147
Test name
Test status
Simulation time	245239432 ps
CPU time	1.04 seconds
Started	Jan 10 01:20:47 PM PST 24
Finished	Jan 10 01:20:53 PM PST 24
Peak memory	214548 kb
Host	smart-c96cf7dc-1165-4398-a16a-9faec9ec57cd
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570283432 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_di sable_auto_req_mode.570283432
Directory	/workspace/48.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/48.edn_err.2739949091
Short name	T178
Test name
Test status
Simulation time	18871707 ps
CPU time	1.09 seconds
Started	Jan 10 01:20:29 PM PST 24
Finished	Jan 10 01:20:38 PM PST 24
Peak memory	221828 kb
Host	smart-c1330c08-39de-443e-8576-ddc21143ac94
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2739949091 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.2739949091
Directory	/workspace/48.edn_err/latest

Test location	/workspace/coverage/default/48.edn_genbits.1650660832
Short name	T347
Test name
Test status
Simulation time	56089962 ps
CPU time	2.17 seconds
Started	Jan 10 01:20:21 PM PST 24
Finished	Jan 10 01:20:30 PM PST 24
Peak memory	214376 kb
Host	smart-a3d19038-a00b-4bf7-b4e6-be8a9656d1c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1650660832 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.1650660832
Directory	/workspace/48.edn_genbits/latest

Test location	/workspace/coverage/default/48.edn_intr.692001395
Short name	T129
Test name
Test status
Simulation time	34397963 ps
CPU time	0.88 seconds
Started	Jan 10 01:20:34 PM PST 24
Finished	Jan 10 01:20:44 PM PST 24
Peak memory	214332 kb
Host	smart-ea87dddb-0c2f-459a-8426-f9b6c9efcf48
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=692001395 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.692001395
Directory	/workspace/48.edn_intr/latest

Test location	/workspace/coverage/default/48.edn_smoke.663382321
Short name	T747
Test name
Test status
Simulation time	14626504 ps
CPU time	0.88 seconds
Started	Jan 10 01:20:22 PM PST 24
Finished	Jan 10 01:20:32 PM PST 24
Peak memory	205128 kb
Host	smart-ff98272a-af21-4a80-a7dd-ef558735fb3d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=663382321 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.663382321
Directory	/workspace/48.edn_smoke/latest

Test location	/workspace/coverage/default/48.edn_stress_all.3703131393
Short name	T520
Test name
Test status
Simulation time	36657801 ps
CPU time	0.98 seconds
Started	Jan 10 01:20:29 PM PST 24
Finished	Jan 10 01:20:38 PM PST 24
Peak memory	205108 kb
Host	smart-e3b2815a-0683-4e34-b013-293a7be67712
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703131393 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.3703131393
Directory	/workspace/48.edn_stress_all/latest

Test location	/workspace/coverage/default/48.edn_stress_all_with_rand_reset.684323023
Short name	T466
Test name
Test status
Simulation time	9226715934 ps
CPU time	231.06 seconds
Started	Jan 10 01:20:43 PM PST 24
Finished	Jan 10 01:24:40 PM PST 24
Peak memory	214516 kb
Host	smart-96bc2e9b-143b-4777-95ba-41ee13b0e981
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684323023 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.684323023
Directory	/workspace/48.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/49.edn_alert.3861900431
Short name	T678
Test name
Test status
Simulation time	63276965 ps
CPU time	0.92 seconds
Started	Jan 10 01:20:55 PM PST 24
Finished	Jan 10 01:21:00 PM PST 24
Peak memory	205968 kb
Host	smart-c095a86f-0063-4837-a535-12502bc92fb9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3861900431 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.3861900431
Directory	/workspace/49.edn_alert/latest

Test location	/workspace/coverage/default/49.edn_alert_test.2630296743
Short name	T452
Test name
Test status
Simulation time	104923800 ps
CPU time	0.79 seconds
Started	Jan 10 01:21:22 PM PST 24
Finished	Jan 10 01:21:25 PM PST 24
Peak memory	204552 kb
Host	smart-92f556ae-35e2-433e-a28b-c7c05add0b68
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630296743 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.2630296743
Directory	/workspace/49.edn_alert_test/latest

Test location	/workspace/coverage/default/49.edn_disable.2813650334
Short name	T118
Test name
Test status
Simulation time	18902889 ps
CPU time	0.89 seconds
Started	Jan 10 01:21:04 PM PST 24
Finished	Jan 10 01:21:08 PM PST 24
Peak memory	214580 kb
Host	smart-c0355b8d-6592-47b7-b45d-749c53853611
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813650334 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2813650334
Directory	/workspace/49.edn_disable/latest

Test location	/workspace/coverage/default/49.edn_disable_auto_req_mode.3909846541
Short name	T803
Test name
Test status
Simulation time	98658234 ps
CPU time	0.89 seconds
Started	Jan 10 01:20:56 PM PST 24
Finished	Jan 10 01:21:00 PM PST 24
Peak memory	214740 kb
Host	smart-16dc4b53-616f-4198-a077-e6afb164549a
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909846541 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d isable_auto_req_mode.3909846541
Directory	/workspace/49.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/49.edn_err.3256164078
Short name	T14
Test name
Test status
Simulation time	22319665 ps
CPU time	1.04 seconds
Started	Jan 10 01:20:48 PM PST 24
Finished	Jan 10 01:20:55 PM PST 24
Peak memory	221900 kb
Host	smart-05cf129a-d585-4442-a86c-55c5869a3b54
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3256164078 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.3256164078
Directory	/workspace/49.edn_err/latest

Test location	/workspace/coverage/default/49.edn_genbits.3420922879
Short name	T758
Test name
Test status
Simulation time	19010445 ps
CPU time	1 seconds
Started	Jan 10 01:20:41 PM PST 24
Finished	Jan 10 01:20:49 PM PST 24
Peak memory	205208 kb
Host	smart-98d71d49-14d7-4b80-a424-babc969c010e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3420922879 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3420922879
Directory	/workspace/49.edn_genbits/latest

Test location	/workspace/coverage/default/49.edn_intr.4234477319
Short name	T759
Test name
Test status
Simulation time	18249007 ps
CPU time	0.95 seconds
Started	Jan 10 01:21:01 PM PST 24
Finished	Jan 10 01:21:05 PM PST 24
Peak memory	214532 kb
Host	smart-86bd28ed-0237-425f-bb30-035283b63466
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4234477319 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.4234477319
Directory	/workspace/49.edn_intr/latest

Test location	/workspace/coverage/default/49.edn_smoke.697930564
Short name	T782
Test name
Test status
Simulation time	13504189 ps
CPU time	0.89 seconds
Started	Jan 10 01:20:42 PM PST 24
Finished	Jan 10 01:20:50 PM PST 24
Peak memory	204956 kb
Host	smart-27a9455a-093b-4a04-9cbe-27c004b22e3a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=697930564 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.697930564
Directory	/workspace/49.edn_smoke/latest

Test location	/workspace/coverage/default/49.edn_stress_all.1931613844
Short name	T549
Test name
Test status
Simulation time	80783956 ps
CPU time	2.25 seconds
Started	Jan 10 01:20:49 PM PST 24
Finished	Jan 10 01:20:57 PM PST 24
Peak memory	206044 kb
Host	smart-e63a93a5-b1da-413b-9ba7-2648bb45ec4b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931613844 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.1931613844
Directory	/workspace/49.edn_stress_all/latest

Test location	/workspace/coverage/default/49.edn_stress_all_with_rand_reset.1264630777
Short name	T610
Test name
Test status
Simulation time	64676920639 ps
CPU time	1416.01 seconds
Started	Jan 10 01:20:49 PM PST 24
Finished	Jan 10 01:44:31 PM PST 24
Peak memory	217052 kb
Host	smart-07eb9504-7d1b-45d5-ab6e-1d1e9ff7c388
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264630777 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1264630777
Directory	/workspace/49.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/5.edn_alert.326051718
Short name	T961
Test name
Test status
Simulation time	27543928 ps
CPU time	0.93 seconds
Started	Jan 10 01:18:37 PM PST 24
Finished	Jan 10 01:18:44 PM PST 24
Peak memory	205960 kb
Host	smart-4bf9dd43-94c4-49d7-8c20-1b4629845dcd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=326051718 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.326051718
Directory	/workspace/5.edn_alert/latest

Test location	/workspace/coverage/default/5.edn_alert_test.4251787063
Short name	T467
Test name
Test status
Simulation time	118853935 ps
CPU time	0.86 seconds
Started	Jan 10 01:18:33 PM PST 24
Finished	Jan 10 01:18:41 PM PST 24
Peak memory	204740 kb
Host	smart-e39e5191-3fa2-408f-ad6b-0c05332abcb8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251787063 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.4251787063
Directory	/workspace/5.edn_alert_test/latest

Test location	/workspace/coverage/default/5.edn_disable.1367762533
Short name	T617
Test name
Test status
Simulation time	50849992 ps
CPU time	0.8 seconds
Started	Jan 10 01:18:38 PM PST 24
Finished	Jan 10 01:18:45 PM PST 24
Peak memory	214424 kb
Host	smart-23845374-95b5-4df4-8f60-0698897045e0
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367762533 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1367762533
Directory	/workspace/5.edn_disable/latest

Test location	/workspace/coverage/default/5.edn_disable_auto_req_mode.867703951
Short name	T110
Test name
Test status
Simulation time	87242561 ps
CPU time	0.96 seconds
Started	Jan 10 01:18:36 PM PST 24
Finished	Jan 10 01:18:44 PM PST 24
Peak memory	214728 kb
Host	smart-12954f13-e7d1-4271-bf09-32236a850ba7
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867703951 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_dis able_auto_req_mode.867703951
Directory	/workspace/5.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/5.edn_err.1717268185
Short name	T777
Test name
Test status
Simulation time	28526739 ps
CPU time	1.23 seconds
Started	Jan 10 01:18:36 PM PST 24
Finished	Jan 10 01:18:44 PM PST 24
Peak memory	221940 kb
Host	smart-41079a23-604b-450b-b7c3-a0c1ef7de9af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1717268185 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.1717268185
Directory	/workspace/5.edn_err/latest

Test location	/workspace/coverage/default/5.edn_genbits.1397792613
Short name	T601
Test name
Test status
Simulation time	60078117 ps
CPU time	2.29 seconds
Started	Jan 10 01:18:36 PM PST 24
Finished	Jan 10 01:18:45 PM PST 24
Peak memory	214296 kb
Host	smart-2b3257d8-fa94-4afa-84c7-c6d3435c7baf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1397792613 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1397792613
Directory	/workspace/5.edn_genbits/latest

Test location	/workspace/coverage/default/5.edn_intr.4267285846
Short name	T925
Test name
Test status
Simulation time	18647758 ps
CPU time	1.09 seconds
Started	Jan 10 01:18:43 PM PST 24
Finished	Jan 10 01:18:50 PM PST 24
Peak memory	214440 kb
Host	smart-3b1e8332-850e-4099-b6a2-89abfc9d89fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4267285846 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.4267285846
Directory	/workspace/5.edn_intr/latest

Test location	/workspace/coverage/default/5.edn_regwen.251451109
Short name	T770
Test name
Test status
Simulation time	52658635 ps
CPU time	0.9 seconds
Started	Jan 10 01:18:43 PM PST 24
Finished	Jan 10 01:18:50 PM PST 24
Peak memory	204836 kb
Host	smart-ce8639b1-efec-42ea-bcb4-1972533cf276
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=251451109 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.251451109
Directory	/workspace/5.edn_regwen/latest

Test location	/workspace/coverage/default/5.edn_smoke.156228031
Short name	T51
Test name
Test status
Simulation time	13413053 ps
CPU time	0.84 seconds
Started	Jan 10 01:18:38 PM PST 24
Finished	Jan 10 01:18:47 PM PST 24
Peak memory	204884 kb
Host	smart-58e2f056-99a9-45b1-82be-9ae845ff7c44
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=156228031 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.156228031
Directory	/workspace/5.edn_smoke/latest

Test location	/workspace/coverage/default/5.edn_stress_all.4069658178
Short name	T966
Test name
Test status
Simulation time	132170229 ps
CPU time	3.08 seconds
Started	Jan 10 01:18:38 PM PST 24
Finished	Jan 10 01:18:48 PM PST 24
Peak memory	206024 kb
Host	smart-3d6b273a-5923-4197-93bf-9aacb19d90aa
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069658178 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.4069658178
Directory	/workspace/5.edn_stress_all/latest

Test location	/workspace/coverage/default/5.edn_stress_all_with_rand_reset.2913357210
Short name	T660
Test name
Test status
Simulation time	72672097100 ps
CPU time	1589.53 seconds
Started	Jan 10 01:18:30 PM PST 24
Finished	Jan 10 01:45:07 PM PST 24
Peak memory	217640 kb
Host	smart-77629473-5c1f-4dc6-9abd-afc9a651fcda
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913357210 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.2913357210
Directory	/workspace/5.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/50.edn_err.3414928348
Short name	T567
Test name
Test status
Simulation time	19324616 ps
CPU time	1.45 seconds
Started	Jan 10 01:20:53 PM PST 24
Finished	Jan 10 01:21:00 PM PST 24
Peak memory	221844 kb
Host	smart-3c4a65bf-9ef0-4a7b-bf5f-544e3b9b7f5a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3414928348 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.3414928348
Directory	/workspace/50.edn_err/latest

Test location	/workspace/coverage/default/50.edn_genbits.926966751
Short name	T335
Test name
Test status
Simulation time	15292600 ps
CPU time	1 seconds
Started	Jan 10 01:21:15 PM PST 24
Finished	Jan 10 01:21:18 PM PST 24
Peak memory	205592 kb
Host	smart-9d4705ae-cd43-4b26-9a44-0cae01a7d3ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=926966751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.926966751
Directory	/workspace/50.edn_genbits/latest

Test location	/workspace/coverage/default/51.edn_err.3032607401
Short name	T708
Test name
Test status
Simulation time	21912292 ps
CPU time	1.2 seconds
Started	Jan 10 01:20:58 PM PST 24
Finished	Jan 10 01:21:04 PM PST 24
Peak memory	216296 kb
Host	smart-c1bb896d-6c8b-4a6e-9a29-13300a6375b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3032607401 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.3032607401
Directory	/workspace/51.edn_err/latest

Test location	/workspace/coverage/default/51.edn_genbits.1410262356
Short name	T286
Test name
Test status
Simulation time	46949672 ps
CPU time	0.98 seconds
Started	Jan 10 01:20:57 PM PST 24
Finished	Jan 10 01:21:02 PM PST 24
Peak memory	205744 kb
Host	smart-1c41a1da-4550-441b-aded-7c32ad31182c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1410262356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.1410262356
Directory	/workspace/51.edn_genbits/latest

Test location	/workspace/coverage/default/52.edn_err.2617924613
Short name	T240
Test name
Test status
Simulation time	30241912 ps
CPU time	0.92 seconds
Started	Jan 10 01:21:26 PM PST 24
Finished	Jan 10 01:21:31 PM PST 24
Peak memory	221320 kb
Host	smart-0335cf1b-e254-45f2-bb69-1890cab7555c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2617924613 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.2617924613
Directory	/workspace/52.edn_err/latest

Test location	/workspace/coverage/default/52.edn_genbits.3683246518
Short name	T726
Test name
Test status
Simulation time	44376801 ps
CPU time	1.02 seconds
Started	Jan 10 01:21:03 PM PST 24
Finished	Jan 10 01:21:08 PM PST 24
Peak memory	205212 kb
Host	smart-119d535d-9774-46bb-9af6-6fd80c6a1b95
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3683246518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3683246518
Directory	/workspace/52.edn_genbits/latest

Test location	/workspace/coverage/default/53.edn_err.2292218963
Short name	T645
Test name
Test status
Simulation time	42636932 ps
CPU time	1.1 seconds
Started	Jan 10 01:21:32 PM PST 24
Finished	Jan 10 01:21:51 PM PST 24
Peak memory	217076 kb
Host	smart-086ac885-e7bf-4c80-ba82-a685c815d280
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2292218963 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.2292218963
Directory	/workspace/53.edn_err/latest

Test location	/workspace/coverage/default/53.edn_genbits.2280974486
Short name	T690
Test name
Test status
Simulation time	22323053 ps
CPU time	1.1 seconds
Started	Jan 10 01:20:53 PM PST 24
Finished	Jan 10 01:20:59 PM PST 24
Peak memory	205544 kb
Host	smart-7c0aa688-0335-44cb-b335-ac78033215b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2280974486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.2280974486
Directory	/workspace/53.edn_genbits/latest

Test location	/workspace/coverage/default/54.edn_err.1704553641
Short name	T885
Test name
Test status
Simulation time	19038242 ps
CPU time	1.02 seconds
Started	Jan 10 01:21:28 PM PST 24
Finished	Jan 10 01:21:41 PM PST 24
Peak memory	215112 kb
Host	smart-ed839652-7cfa-41fd-900b-e1ff30b1d065
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1704553641 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.1704553641
Directory	/workspace/54.edn_err/latest

Test location	/workspace/coverage/default/55.edn_err.1798889959
Short name	T49
Test name
Test status
Simulation time	30089665 ps
CPU time	1.13 seconds
Started	Jan 10 01:20:32 PM PST 24
Finished	Jan 10 01:20:42 PM PST 24
Peak memory	230216 kb
Host	smart-ee94255f-648c-4487-bb08-6e5c49a1e0da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1798889959 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.1798889959
Directory	/workspace/55.edn_err/latest

Test location	/workspace/coverage/default/55.edn_genbits.1837351563
Short name	T581
Test name
Test status
Simulation time	18842879 ps
CPU time	0.96 seconds
Started	Jan 10 01:20:18 PM PST 24
Finished	Jan 10 01:20:26 PM PST 24
Peak memory	205504 kb
Host	smart-533a94f9-1980-460c-9b64-18f7d4978f0a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1837351563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.1837351563
Directory	/workspace/55.edn_genbits/latest

Test location	/workspace/coverage/default/56.edn_err.3544890347
Short name	T621
Test name
Test status
Simulation time	18182450 ps
CPU time	1.46 seconds
Started	Jan 10 01:20:21 PM PST 24
Finished	Jan 10 01:20:30 PM PST 24
Peak memory	222024 kb
Host	smart-26e35884-b2f2-4da3-a2bb-ff2e1e20faa9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3544890347 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.3544890347
Directory	/workspace/56.edn_err/latest

Test location	/workspace/coverage/default/56.edn_genbits.827615540
Short name	T940
Test name
Test status
Simulation time	17196170 ps
CPU time	1 seconds
Started	Jan 10 01:20:31 PM PST 24
Finished	Jan 10 01:20:40 PM PST 24
Peak memory	205232 kb
Host	smart-a1d2d0e3-bc78-4050-9650-15a3d61a77ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=827615540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.827615540
Directory	/workspace/56.edn_genbits/latest

Test location	/workspace/coverage/default/57.edn_err.56873840
Short name	T771
Test name
Test status
Simulation time	20100982 ps
CPU time	1.2 seconds
Started	Jan 10 01:20:37 PM PST 24
Finished	Jan 10 01:20:48 PM PST 24
Peak memory	228464 kb
Host	smart-96d1d86f-b27e-4d3d-a0ad-20791beaf710
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=56873840 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.56873840
Directory	/workspace/57.edn_err/latest

Test location	/workspace/coverage/default/57.edn_genbits.3494258007
Short name	T524
Test name
Test status
Simulation time	42722432 ps
CPU time	0.86 seconds
Started	Jan 10 01:20:21 PM PST 24
Finished	Jan 10 01:20:31 PM PST 24
Peak memory	205216 kb
Host	smart-344c4cf9-37ee-4ef5-884c-c16221d785ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3494258007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.3494258007
Directory	/workspace/57.edn_genbits/latest

Test location	/workspace/coverage/default/58.edn_err.3673469370
Short name	T681
Test name
Test status
Simulation time	73126770 ps
CPU time	1.18 seconds
Started	Jan 10 01:20:18 PM PST 24
Finished	Jan 10 01:20:24 PM PST 24
Peak memory	227600 kb
Host	smart-e45816cc-38f8-4cab-b3a0-f53eb6c15d03
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3673469370 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.3673469370
Directory	/workspace/58.edn_err/latest

Test location	/workspace/coverage/default/59.edn_err.4132868098
Short name	T459
Test name
Test status
Simulation time	19341726 ps
CPU time	1.09 seconds
Started	Jan 10 01:20:22 PM PST 24
Finished	Jan 10 01:20:34 PM PST 24
Peak memory	215908 kb
Host	smart-d67b744a-ba34-4c33-ade4-3c9c1f5c38ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4132868098 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.4132868098
Directory	/workspace/59.edn_err/latest

Test location	/workspace/coverage/default/59.edn_genbits.4135190643
Short name	T871
Test name
Test status
Simulation time	45256838 ps
CPU time	1.1 seconds
Started	Jan 10 01:20:29 PM PST 24
Finished	Jan 10 01:20:38 PM PST 24
Peak memory	214288 kb
Host	smart-8c82da7a-4c88-4df1-b617-3e54a22b9f5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4135190643 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.4135190643
Directory	/workspace/59.edn_genbits/latest

Test location	/workspace/coverage/default/6.edn_alert.77370381
Short name	T319
Test name
Test status
Simulation time	58899685 ps
CPU time	0.92 seconds
Started	Jan 10 01:19:09 PM PST 24
Finished	Jan 10 01:19:12 PM PST 24
Peak memory	206168 kb
Host	smart-c0b97980-6348-4afb-8d34-483b7293362f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=77370381 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.77370381
Directory	/workspace/6.edn_alert/latest

Test location	/workspace/coverage/default/6.edn_alert_test.1044546876
Short name	T883
Test name
Test status
Simulation time	47773207 ps
CPU time	0.83 seconds
Started	Jan 10 01:19:20 PM PST 24
Finished	Jan 10 01:19:25 PM PST 24
Peak memory	205272 kb
Host	smart-68dc0675-9e3f-4ee8-8765-a33b3a6695d8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044546876 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.1044546876
Directory	/workspace/6.edn_alert_test/latest

Test location	/workspace/coverage/default/6.edn_disable.3965110196
Short name	T109
Test name
Test status
Simulation time	13010557 ps
CPU time	0.86 seconds
Started	Jan 10 01:19:19 PM PST 24
Finished	Jan 10 01:19:24 PM PST 24
Peak memory	214612 kb
Host	smart-b12e22f7-69e1-41c7-a9a8-2c9e20bf3477
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965110196 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.3965110196
Directory	/workspace/6.edn_disable/latest

Test location	/workspace/coverage/default/6.edn_disable_auto_req_mode.984988071
Short name	T855
Test name
Test status
Simulation time	22651203 ps
CPU time	0.96 seconds
Started	Jan 10 01:19:09 PM PST 24
Finished	Jan 10 01:19:13 PM PST 24
Peak memory	214732 kb
Host	smart-13a2983e-49b4-445e-8979-ffcaacdf916f
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984988071 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_dis able_auto_req_mode.984988071
Directory	/workspace/6.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/6.edn_err.3231457732
Short name	T616
Test name
Test status
Simulation time	18546285 ps
CPU time	0.99 seconds
Started	Jan 10 01:19:23 PM PST 24
Finished	Jan 10 01:19:34 PM PST 24
Peak memory	216000 kb
Host	smart-77dcdd35-a6e0-428f-8065-03d6fc48ea37
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3231457732 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.3231457732
Directory	/workspace/6.edn_err/latest

Test location	/workspace/coverage/default/6.edn_intr.1145373155
Short name	T98
Test name
Test status
Simulation time	33807613 ps
CPU time	0.82 seconds
Started	Jan 10 01:18:35 PM PST 24
Finished	Jan 10 01:18:43 PM PST 24
Peak memory	214568 kb
Host	smart-bfff3164-2143-406a-ae64-cec9062796a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1145373155 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.1145373155
Directory	/workspace/6.edn_intr/latest

Test location	/workspace/coverage/default/6.edn_regwen.2192043100
Short name	T326
Test name
Test status
Simulation time	37924726 ps
CPU time	0.83 seconds
Started	Jan 10 01:18:30 PM PST 24
Finished	Jan 10 01:18:38 PM PST 24
Peak memory	204844 kb
Host	smart-7d2bcae9-85e3-43ca-b630-8d312525a59c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2192043100 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.2192043100
Directory	/workspace/6.edn_regwen/latest

Test location	/workspace/coverage/default/6.edn_smoke.345266232
Short name	T837
Test name
Test status
Simulation time	83297605 ps
CPU time	0.81 seconds
Started	Jan 10 01:18:38 PM PST 24
Finished	Jan 10 01:18:46 PM PST 24
Peak memory	204904 kb
Host	smart-19ddb781-4511-48e3-9390-2e8c1b4e12db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=345266232 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.345266232
Directory	/workspace/6.edn_smoke/latest

Test location	/workspace/coverage/default/6.edn_stress_all.1374158287
Short name	T468
Test name
Test status
Simulation time	265090586 ps
CPU time	1.84 seconds
Started	Jan 10 01:18:30 PM PST 24
Finished	Jan 10 01:18:39 PM PST 24
Peak memory	205848 kb
Host	smart-76a2f30b-ca95-4ab0-914a-621968605652
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374158287 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.1374158287
Directory	/workspace/6.edn_stress_all/latest

Test location	/workspace/coverage/default/6.edn_stress_all_with_rand_reset.1051523457
Short name	T715
Test name
Test status
Simulation time	209327371531 ps
CPU time	2383.05 seconds
Started	Jan 10 01:18:38 PM PST 24
Finished	Jan 10 01:58:28 PM PST 24
Peak memory	220984 kb
Host	smart-66b3cb88-6968-4c39-a29a-17c83d583b23
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051523457 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.1051523457
Directory	/workspace/6.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/60.edn_err.2610013550
Short name	T237
Test name
Test status
Simulation time	28581554 ps
CPU time	1.19 seconds
Started	Jan 10 01:20:30 PM PST 24
Finished	Jan 10 01:20:39 PM PST 24
Peak memory	217124 kb
Host	smart-1c7372ab-3ef8-4589-bb87-b3459cbbe1cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2610013550 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.2610013550
Directory	/workspace/60.edn_err/latest

Test location	/workspace/coverage/default/60.edn_genbits.3659750653
Short name	T12
Test name
Test status
Simulation time	38468005 ps
CPU time	1.15 seconds
Started	Jan 10 01:20:22 PM PST 24
Finished	Jan 10 01:20:34 PM PST 24
Peak memory	214316 kb
Host	smart-a7bf23ec-e0b7-466b-98f5-9e8aa3608424
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3659750653 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3659750653
Directory	/workspace/60.edn_genbits/latest

Test location	/workspace/coverage/default/61.edn_err.3582842843
Short name	T71
Test name
Test status
Simulation time	43863336 ps
CPU time	1.05 seconds
Started	Jan 10 01:20:32 PM PST 24
Finished	Jan 10 01:20:41 PM PST 24
Peak memory	217308 kb
Host	smart-705ff9ed-4c09-4911-8ff8-97ae1136bfb6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3582842843 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.3582842843
Directory	/workspace/61.edn_err/latest

Test location	/workspace/coverage/default/61.edn_genbits.1230484143
Short name	T495
Test name
Test status
Simulation time	80159966 ps
CPU time	1.08 seconds
Started	Jan 10 01:20:23 PM PST 24
Finished	Jan 10 01:20:34 PM PST 24
Peak memory	214316 kb
Host	smart-8f585961-e0c0-4eab-bfa1-fea8bc524055
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1230484143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.1230484143
Directory	/workspace/61.edn_genbits/latest

Test location	/workspace/coverage/default/62.edn_err.3862822586
Short name	T895
Test name
Test status
Simulation time	19238571 ps
CPU time	1.06 seconds
Started	Jan 10 01:20:28 PM PST 24
Finished	Jan 10 01:20:38 PM PST 24
Peak memory	215636 kb
Host	smart-aaba1f80-609f-45dd-8e04-dd62d66a58c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3862822586 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.3862822586
Directory	/workspace/62.edn_err/latest

Test location	/workspace/coverage/default/62.edn_genbits.2196283313
Short name	T569
Test name
Test status
Simulation time	48654842 ps
CPU time	0.94 seconds
Started	Jan 10 01:20:21 PM PST 24
Finished	Jan 10 01:20:29 PM PST 24
Peak memory	205680 kb
Host	smart-b8b90a2f-a337-443c-8dd1-fb484b457f63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2196283313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.2196283313
Directory	/workspace/62.edn_genbits/latest

Test location	/workspace/coverage/default/63.edn_err.3549416847
Short name	T677
Test name
Test status
Simulation time	23663865 ps
CPU time	0.94 seconds
Started	Jan 10 01:20:29 PM PST 24
Finished	Jan 10 01:20:38 PM PST 24
Peak memory	216064 kb
Host	smart-eed80aa4-5810-4937-b34a-168aadc1c1b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3549416847 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.3549416847
Directory	/workspace/63.edn_err/latest

Test location	/workspace/coverage/default/63.edn_genbits.1994625955
Short name	T280
Test name
Test status
Simulation time	45340895 ps
CPU time	0.95 seconds
Started	Jan 10 01:20:19 PM PST 24
Finished	Jan 10 01:20:27 PM PST 24
Peak memory	205772 kb
Host	smart-97d9f6ec-2ceb-463c-b4c3-9ff2829e3822
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1994625955 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.1994625955
Directory	/workspace/63.edn_genbits/latest

Test location	/workspace/coverage/default/64.edn_err.3489335969
Short name	T43
Test name
Test status
Simulation time	45671159 ps
CPU time	1.03 seconds
Started	Jan 10 01:20:31 PM PST 24
Finished	Jan 10 01:20:40 PM PST 24
Peak memory	228272 kb
Host	smart-a18bf4ad-46e9-406c-af7c-0562a8cda0df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3489335969 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.3489335969
Directory	/workspace/64.edn_err/latest

Test location	/workspace/coverage/default/64.edn_genbits.2906815818
Short name	T967
Test name
Test status
Simulation time	65049973 ps
CPU time	2.08 seconds
Started	Jan 10 01:20:30 PM PST 24
Finished	Jan 10 01:20:40 PM PST 24
Peak memory	214364 kb
Host	smart-a2100f1a-69f8-4c4a-9f23-dc3780db5f9a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2906815818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2906815818
Directory	/workspace/64.edn_genbits/latest

Test location	/workspace/coverage/default/65.edn_genbits.523582424
Short name	T827
Test name
Test status
Simulation time	25982100 ps
CPU time	0.96 seconds
Started	Jan 10 01:20:22 PM PST 24
Finished	Jan 10 01:20:32 PM PST 24
Peak memory	205424 kb
Host	smart-4df84e39-e58e-4a4a-a496-3052242e0cc0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=523582424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.523582424
Directory	/workspace/65.edn_genbits/latest

Test location	/workspace/coverage/default/66.edn_err.2274141891
Short name	T226
Test name
Test status
Simulation time	19839069 ps
CPU time	1.02 seconds
Started	Jan 10 01:20:18 PM PST 24
Finished	Jan 10 01:20:25 PM PST 24
Peak memory	214936 kb
Host	smart-f99bc565-2cba-4747-9b8a-4c581993e4c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2274141891 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.2274141891
Directory	/workspace/66.edn_err/latest

Test location	/workspace/coverage/default/66.edn_genbits.1967121378
Short name	T736
Test name
Test status
Simulation time	203854497 ps
CPU time	2.56 seconds
Started	Jan 10 01:20:21 PM PST 24
Finished	Jan 10 01:20:31 PM PST 24
Peak memory	214384 kb
Host	smart-bf871f3f-f4c4-47e8-8072-6e022e12abd7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1967121378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.1967121378
Directory	/workspace/66.edn_genbits/latest

Test location	/workspace/coverage/default/67.edn_err.2103898916
Short name	T155
Test name
Test status
Simulation time	21611714 ps
CPU time	0.88 seconds
Started	Jan 10 01:20:20 PM PST 24
Finished	Jan 10 01:20:28 PM PST 24
Peak memory	215760 kb
Host	smart-ec09f9a6-9c05-4223-af08-216502e083b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2103898916 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.2103898916
Directory	/workspace/67.edn_err/latest

Test location	/workspace/coverage/default/67.edn_genbits.3056602889
Short name	T30
Test name
Test status
Simulation time	92633355 ps
CPU time	1 seconds
Started	Jan 10 01:20:20 PM PST 24
Finished	Jan 10 01:20:28 PM PST 24
Peak memory	205612 kb
Host	smart-493ab5b0-9922-4b34-929f-59a258a432da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3056602889 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3056602889
Directory	/workspace/67.edn_genbits/latest

Test location	/workspace/coverage/default/68.edn_err.2680006138
Short name	T808
Test name
Test status
Simulation time	69872092 ps
CPU time	1.01 seconds
Started	Jan 10 01:20:23 PM PST 24
Finished	Jan 10 01:20:34 PM PST 24
Peak memory	217064 kb
Host	smart-cffa76f2-1c9b-4267-960f-a72ff4252be3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2680006138 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.2680006138
Directory	/workspace/68.edn_err/latest

Test location	/workspace/coverage/default/68.edn_genbits.3004639966
Short name	T907
Test name
Test status
Simulation time	49534487 ps
CPU time	0.95 seconds
Started	Jan 10 01:20:20 PM PST 24
Finished	Jan 10 01:20:28 PM PST 24
Peak memory	205332 kb
Host	smart-1a1ee6aa-83df-4c36-929e-e82151f41015
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3004639966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.3004639966
Directory	/workspace/68.edn_genbits/latest

Test location	/workspace/coverage/default/69.edn_err.2162024227
Short name	T70
Test name
Test status
Simulation time	18616745 ps
CPU time	1.14 seconds
Started	Jan 10 01:20:19 PM PST 24
Finished	Jan 10 01:20:27 PM PST 24
Peak memory	216044 kb
Host	smart-0569b40e-9b2b-457f-bcf3-c6f4f686670c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2162024227 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.2162024227
Directory	/workspace/69.edn_err/latest

Test location	/workspace/coverage/default/69.edn_genbits.2275938240
Short name	T730
Test name
Test status
Simulation time	68001775 ps
CPU time	1.13 seconds
Started	Jan 10 01:20:18 PM PST 24
Finished	Jan 10 01:20:24 PM PST 24
Peak memory	214168 kb
Host	smart-534301bd-94e1-4301-91e4-b882936e584f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2275938240 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.2275938240
Directory	/workspace/69.edn_genbits/latest

Test location	/workspace/coverage/default/7.edn_alert.2472378709
Short name	T775
Test name
Test status
Simulation time	42480661 ps
CPU time	1.01 seconds
Started	Jan 10 01:19:19 PM PST 24
Finished	Jan 10 01:19:24 PM PST 24
Peak memory	206092 kb
Host	smart-691442f0-b7a9-4ba9-8d44-0f1c7bf08c6e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2472378709 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.2472378709
Directory	/workspace/7.edn_alert/latest

Test location	/workspace/coverage/default/7.edn_alert_test.344312470
Short name	T908
Test name
Test status
Simulation time	15950717 ps
CPU time	0.74 seconds
Started	Jan 10 01:19:20 PM PST 24
Finished	Jan 10 01:19:24 PM PST 24
Peak memory	204180 kb
Host	smart-76c94098-d876-4e5d-a71d-5b53f3415115
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344312470 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.344312470
Directory	/workspace/7.edn_alert_test/latest

Test location	/workspace/coverage/default/7.edn_disable.2170066879
Short name	T231
Test name
Test status
Simulation time	14409642 ps
CPU time	0.91 seconds
Started	Jan 10 01:19:20 PM PST 24
Finished	Jan 10 01:19:25 PM PST 24
Peak memory	214700 kb
Host	smart-9b86d560-156d-4abe-bdd7-b4359894a624
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170066879 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.2170066879
Directory	/workspace/7.edn_disable/latest

Test location	/workspace/coverage/default/7.edn_disable_auto_req_mode.1470909629
Short name	T661
Test name
Test status
Simulation time	28186467 ps
CPU time	0.98 seconds
Started	Jan 10 01:19:23 PM PST 24
Finished	Jan 10 01:19:32 PM PST 24
Peak memory	214688 kb
Host	smart-15054bbc-4c7e-4780-861a-62da7d8ee2d3
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470909629 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di sable_auto_req_mode.1470909629
Directory	/workspace/7.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/7.edn_err.4277526796
Short name	T46
Test name
Test status
Simulation time	23538518 ps
CPU time	1.06 seconds
Started	Jan 10 01:19:21 PM PST 24
Finished	Jan 10 01:19:28 PM PST 24
Peak memory	228548 kb
Host	smart-931abbd4-7af2-4d88-a666-75db135fe9be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4277526796 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.4277526796
Directory	/workspace/7.edn_err/latest

Test location	/workspace/coverage/default/7.edn_intr.586552027
Short name	T582
Test name
Test status
Simulation time	30537746 ps
CPU time	1 seconds
Started	Jan 10 01:19:08 PM PST 24
Finished	Jan 10 01:19:11 PM PST 24
Peak memory	221220 kb
Host	smart-c424d6ee-4595-4ade-9d2c-042ca8f55550
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=586552027 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.586552027
Directory	/workspace/7.edn_intr/latest

Test location	/workspace/coverage/default/7.edn_smoke.1727307001
Short name	T979
Test name
Test status
Simulation time	25643188 ps
CPU time	0.83 seconds
Started	Jan 10 01:19:10 PM PST 24
Finished	Jan 10 01:19:14 PM PST 24
Peak memory	204744 kb
Host	smart-c7e35dee-2812-4b1a-af6d-52e051f83743
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1727307001 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.1727307001
Directory	/workspace/7.edn_smoke/latest

Test location	/workspace/coverage/default/7.edn_stress_all.3888733919
Short name	T482
Test name
Test status
Simulation time	687162865 ps
CPU time	3.8 seconds
Started	Jan 10 01:19:08 PM PST 24
Finished	Jan 10 01:19:14 PM PST 24
Peak memory	206056 kb
Host	smart-6c76a2ba-8d9e-47e1-b2f5-1d4ac532c9a0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888733919 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.3888733919
Directory	/workspace/7.edn_stress_all/latest

Test location	/workspace/coverage/default/7.edn_stress_all_with_rand_reset.3595029435
Short name	T767
Test name
Test status
Simulation time	135599045370 ps
CPU time	801.74 seconds
Started	Jan 10 01:19:08 PM PST 24
Finished	Jan 10 01:32:31 PM PST 24
Peak memory	214532 kb
Host	smart-dfeb4ee7-586c-494e-814e-5f02c18948ae
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595029435 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.3595029435
Directory	/workspace/7.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/70.edn_err.1223463897
Short name	T789
Test name
Test status
Simulation time	23311441 ps
CPU time	1.15 seconds
Started	Jan 10 01:20:37 PM PST 24
Finished	Jan 10 01:20:48 PM PST 24
Peak memory	214680 kb
Host	smart-6fef1d33-badd-4bef-9a87-e60d91300958
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1223463897 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.1223463897
Directory	/workspace/70.edn_err/latest

Test location	/workspace/coverage/default/70.edn_genbits.2855534658
Short name	T534
Test name
Test status
Simulation time	55798110 ps
CPU time	1.06 seconds
Started	Jan 10 01:20:19 PM PST 24
Finished	Jan 10 01:20:27 PM PST 24
Peak memory	205400 kb
Host	smart-ba368265-e2b4-45a4-a4a4-4368b7f60eef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2855534658 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.2855534658
Directory	/workspace/70.edn_genbits/latest

Test location	/workspace/coverage/default/71.edn_genbits.2107139654
Short name	T706
Test name
Test status
Simulation time	18121127 ps
CPU time	0.95 seconds
Started	Jan 10 01:20:21 PM PST 24
Finished	Jan 10 01:20:29 PM PST 24
Peak memory	205084 kb
Host	smart-d7fd3bf7-e7fc-4348-8fec-d223b994415c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2107139654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.2107139654
Directory	/workspace/71.edn_genbits/latest

Test location	/workspace/coverage/default/72.edn_err.4119589955
Short name	T139
Test name
Test status
Simulation time	26131317 ps
CPU time	0.99 seconds
Started	Jan 10 01:20:29 PM PST 24
Finished	Jan 10 01:20:38 PM PST 24
Peak memory	214756 kb
Host	smart-85a4b0c1-2f6b-4fe7-8bcf-84f34ff74df3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4119589955 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.4119589955
Directory	/workspace/72.edn_err/latest

Test location	/workspace/coverage/default/73.edn_err.2181297733
Short name	T179
Test name
Test status
Simulation time	51774201 ps
CPU time	0.89 seconds
Started	Jan 10 01:20:30 PM PST 24
Finished	Jan 10 01:20:39 PM PST 24
Peak memory	221076 kb
Host	smart-bf68b5c7-bd79-4e08-b09f-49368156df17
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2181297733 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.2181297733
Directory	/workspace/73.edn_err/latest

Test location	/workspace/coverage/default/73.edn_genbits.3440927142
Short name	T780
Test name
Test status
Simulation time	21187853 ps
CPU time	1.35 seconds
Started	Jan 10 01:20:33 PM PST 24
Finished	Jan 10 01:20:43 PM PST 24
Peak memory	205940 kb
Host	smart-be8f8792-20c2-4f52-a618-3de583f0db2a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3440927142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.3440927142
Directory	/workspace/73.edn_genbits/latest

Test location	/workspace/coverage/default/74.edn_err.325822278
Short name	T561
Test name
Test status
Simulation time	143372805 ps
CPU time	1.08 seconds
Started	Jan 10 01:20:32 PM PST 24
Finished	Jan 10 01:20:41 PM PST 24
Peak memory	221836 kb
Host	smart-0b1e63ba-f4cb-4d50-9952-bd2b4ba684ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=325822278 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.325822278
Directory	/workspace/74.edn_err/latest

Test location	/workspace/coverage/default/74.edn_genbits.96227523
Short name	T502
Test name
Test status
Simulation time	22260110 ps
CPU time	0.96 seconds
Started	Jan 10 01:20:33 PM PST 24
Finished	Jan 10 01:20:43 PM PST 24
Peak memory	205412 kb
Host	smart-2447111e-de2e-4b6a-88d0-abd2117aa54c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=96227523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.96227523
Directory	/workspace/74.edn_genbits/latest

Test location	/workspace/coverage/default/75.edn_err.3413890954
Short name	T162
Test name
Test status
Simulation time	31794457 ps
CPU time	0.8 seconds
Started	Jan 10 01:20:31 PM PST 24
Finished	Jan 10 01:20:40 PM PST 24
Peak memory	215664 kb
Host	smart-a4664d59-a521-484b-854f-f49ca7566d1b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3413890954 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.3413890954
Directory	/workspace/75.edn_err/latest

Test location	/workspace/coverage/default/75.edn_genbits.3370459761
Short name	T615
Test name
Test status
Simulation time	31585859 ps
CPU time	1.38 seconds
Started	Jan 10 01:20:21 PM PST 24
Finished	Jan 10 01:20:31 PM PST 24
Peak memory	214424 kb
Host	smart-332d74c4-307a-4da5-9abf-26b0ad296d67
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3370459761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.3370459761
Directory	/workspace/75.edn_genbits/latest

Test location	/workspace/coverage/default/76.edn_err.2582322494
Short name	T8
Test name
Test status
Simulation time	42361297 ps
CPU time	1.09 seconds
Started	Jan 10 01:20:20 PM PST 24
Finished	Jan 10 01:20:29 PM PST 24
Peak memory	216164 kb
Host	smart-a96dc435-cb0f-44b5-9c9f-15d6778a11e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2582322494 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.2582322494
Directory	/workspace/76.edn_err/latest

Test location	/workspace/coverage/default/76.edn_genbits.1019437300
Short name	T499
Test name
Test status
Simulation time	107403153 ps
CPU time	2.25 seconds
Started	Jan 10 01:20:22 PM PST 24
Finished	Jan 10 01:20:35 PM PST 24
Peak memory	214336 kb
Host	smart-df5a9576-9c2e-425d-b575-679578f7117e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1019437300 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.1019437300
Directory	/workspace/76.edn_genbits/latest

Test location	/workspace/coverage/default/77.edn_err.1359768977
Short name	T44
Test name
Test status
Simulation time	25433632 ps
CPU time	1.05 seconds
Started	Jan 10 01:20:22 PM PST 24
Finished	Jan 10 01:20:33 PM PST 24
Peak memory	220400 kb
Host	smart-2a738716-6703-4e82-9799-d982d181f001
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1359768977 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.1359768977
Directory	/workspace/77.edn_err/latest

Test location	/workspace/coverage/default/77.edn_genbits.2726300674
Short name	T34
Test name
Test status
Simulation time	17772086 ps
CPU time	1.09 seconds
Started	Jan 10 01:20:22 PM PST 24
Finished	Jan 10 01:20:33 PM PST 24
Peak memory	205712 kb
Host	smart-8ad2c5ec-5bcf-4eb2-bf1d-39fb47b9422e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2726300674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.2726300674
Directory	/workspace/77.edn_genbits/latest

Test location	/workspace/coverage/default/78.edn_err.4161338325
Short name	T158
Test name
Test status
Simulation time	62123066 ps
CPU time	1.06 seconds
Started	Jan 10 01:20:32 PM PST 24
Finished	Jan 10 01:20:41 PM PST 24
Peak memory	217076 kb
Host	smart-286cb119-5fa8-4d27-9771-9bfed42c95a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4161338325 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.4161338325
Directory	/workspace/78.edn_err/latest

Test location	/workspace/coverage/default/78.edn_genbits.3098383708
Short name	T604
Test name
Test status
Simulation time	16554830 ps
CPU time	0.92 seconds
Started	Jan 10 01:20:30 PM PST 24
Finished	Jan 10 01:20:39 PM PST 24
Peak memory	204844 kb
Host	smart-98698445-771c-4160-8b5e-72b13b349945
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3098383708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.3098383708
Directory	/workspace/78.edn_genbits/latest

Test location	/workspace/coverage/default/79.edn_err.2069965989
Short name	T931
Test name
Test status
Simulation time	19347642 ps
CPU time	1.15 seconds
Started	Jan 10 01:20:21 PM PST 24
Finished	Jan 10 01:20:30 PM PST 24
Peak memory	221796 kb
Host	smart-aba2ff21-9a4f-40e6-af6e-b93771355f94
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2069965989 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.2069965989
Directory	/workspace/79.edn_err/latest

Test location	/workspace/coverage/default/79.edn_genbits.3757672887
Short name	T774
Test name
Test status
Simulation time	68365625 ps
CPU time	0.89 seconds
Started	Jan 10 01:20:45 PM PST 24
Finished	Jan 10 01:20:51 PM PST 24
Peak memory	204920 kb
Host	smart-040bf152-3d27-41ba-8312-a5725e142c30
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3757672887 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.3757672887
Directory	/workspace/79.edn_genbits/latest

Test location	/workspace/coverage/default/8.edn_alert.311325547
Short name	T312
Test name
Test status
Simulation time	19599380 ps
CPU time	1.01 seconds
Started	Jan 10 01:19:24 PM PST 24
Finished	Jan 10 01:19:35 PM PST 24
Peak memory	205444 kb
Host	smart-8cfdb92d-b4bf-4b22-a5a7-46ba88304692
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=311325547 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.311325547
Directory	/workspace/8.edn_alert/latest

Test location	/workspace/coverage/default/8.edn_alert_test.2428905433
Short name	T571
Test name
Test status
Simulation time	26181389 ps
CPU time	1.05 seconds
Started	Jan 10 01:19:23 PM PST 24
Finished	Jan 10 01:19:34 PM PST 24
Peak memory	205168 kb
Host	smart-82604d1c-1afd-4035-bf72-fad209e01574
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428905433 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.2428905433
Directory	/workspace/8.edn_alert_test/latest

Test location	/workspace/coverage/default/8.edn_disable.1430956964
Short name	T166
Test name
Test status
Simulation time	35881723 ps
CPU time	0.81 seconds
Started	Jan 10 01:19:23 PM PST 24
Finished	Jan 10 01:19:34 PM PST 24
Peak memory	214512 kb
Host	smart-9b2298e8-9b2c-417d-9f7b-493be29ec2dc
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430956964 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.1430956964
Directory	/workspace/8.edn_disable/latest

Test location	/workspace/coverage/default/8.edn_disable_auto_req_mode.3965558728
Short name	T55
Test name
Test status
Simulation time	97819319 ps
CPU time	0.95 seconds
Started	Jan 10 01:19:23 PM PST 24
Finished	Jan 10 01:19:33 PM PST 24
Peak memory	214736 kb
Host	smart-18768192-295b-4b6d-835f-e8d26fbf3b90
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965558728 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di sable_auto_req_mode.3965558728
Directory	/workspace/8.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/8.edn_err.3560942794
Short name	T136
Test name
Test status
Simulation time	29589927 ps
CPU time	0.95 seconds
Started	Jan 10 01:19:24 PM PST 24
Finished	Jan 10 01:19:36 PM PST 24
Peak memory	214620 kb
Host	smart-c20c7e38-0e41-48a8-bb5f-07ab77fe051f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3560942794 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3560942794
Directory	/workspace/8.edn_err/latest

Test location	/workspace/coverage/default/8.edn_genbits.2055441841
Short name	T776
Test name
Test status
Simulation time	23882581 ps
CPU time	0.98 seconds
Started	Jan 10 01:19:23 PM PST 24
Finished	Jan 10 01:19:34 PM PST 24
Peak memory	205552 kb
Host	smart-c8ca91fa-4141-4e03-958b-62b52b03a6a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2055441841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.2055441841
Directory	/workspace/8.edn_genbits/latest

Test location	/workspace/coverage/default/8.edn_intr.2542397972
Short name	T574
Test name
Test status
Simulation time	37269793 ps
CPU time	0.85 seconds
Started	Jan 10 01:19:21 PM PST 24
Finished	Jan 10 01:19:27 PM PST 24
Peak memory	214444 kb
Host	smart-87a86cf4-b61c-4806-bbf4-901fcf3e7b2b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2542397972 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.2542397972
Directory	/workspace/8.edn_intr/latest

Test location	/workspace/coverage/default/8.edn_regwen.3195056201
Short name	T255
Test name
Test status
Simulation time	19012402 ps
CPU time	0.82 seconds
Started	Jan 10 01:19:26 PM PST 24
Finished	Jan 10 01:19:37 PM PST 24
Peak memory	204816 kb
Host	smart-b9555106-75eb-40cd-89ef-f42504e84dfa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3195056201 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.3195056201
Directory	/workspace/8.edn_regwen/latest

Test location	/workspace/coverage/default/8.edn_smoke.3936451520
Short name	T600
Test name
Test status
Simulation time	75840065 ps
CPU time	0.92 seconds
Started	Jan 10 01:19:20 PM PST 24
Finished	Jan 10 01:19:25 PM PST 24
Peak memory	204708 kb
Host	smart-70958608-abb5-427b-9751-bb4db2c1f5fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3936451520 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.3936451520
Directory	/workspace/8.edn_smoke/latest

Test location	/workspace/coverage/default/8.edn_stress_all.1478085424
Short name	T741
Test name
Test status
Simulation time	47535130 ps
CPU time	1.22 seconds
Started	Jan 10 01:19:22 PM PST 24
Finished	Jan 10 01:19:30 PM PST 24
Peak memory	206024 kb
Host	smart-ba44b7ef-95cb-49aa-8082-3b07feb9aed0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478085424 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.1478085424
Directory	/workspace/8.edn_stress_all/latest

Test location	/workspace/coverage/default/8.edn_stress_all_with_rand_reset.1500779400
Short name	T659
Test name
Test status
Simulation time	159274395187 ps
CPU time	795.61 seconds
Started	Jan 10 01:19:22 PM PST 24
Finished	Jan 10 01:32:46 PM PST 24
Peak memory	215404 kb
Host	smart-a0933f3a-78e2-4447-8d8a-f56ffc18f5f8
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500779400 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.1500779400
Directory	/workspace/8.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/80.edn_err.3382530085
Short name	T248
Test name
Test status
Simulation time	70050493 ps
CPU time	1.04 seconds
Started	Jan 10 01:20:20 PM PST 24
Finished	Jan 10 01:20:28 PM PST 24
Peak memory	217268 kb
Host	smart-2f69ece4-d3ad-4048-a65a-e8a76d9c1a7f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3382530085 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.3382530085
Directory	/workspace/80.edn_err/latest

Test location	/workspace/coverage/default/80.edn_genbits.2997865295
Short name	T510
Test name
Test status
Simulation time	53988771 ps
CPU time	0.98 seconds
Started	Jan 10 01:20:50 PM PST 24
Finished	Jan 10 01:20:57 PM PST 24
Peak memory	205320 kb
Host	smart-6da4a299-a82f-4327-9ad3-0bdf69237440
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2997865295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.2997865295
Directory	/workspace/80.edn_genbits/latest

Test location	/workspace/coverage/default/81.edn_err.1365476055
Short name	T955
Test name
Test status
Simulation time	36033512 ps
CPU time	0.85 seconds
Started	Jan 10 01:20:31 PM PST 24
Finished	Jan 10 01:20:40 PM PST 24
Peak memory	215728 kb
Host	smart-9d1d35ed-505b-42db-82ba-208e25876687
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1365476055 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.1365476055
Directory	/workspace/81.edn_err/latest

Test location	/workspace/coverage/default/81.edn_genbits.689626705
Short name	T477
Test name
Test status
Simulation time	91438881 ps
CPU time	1.38 seconds
Started	Jan 10 01:20:28 PM PST 24
Finished	Jan 10 01:20:38 PM PST 24
Peak memory	214284 kb
Host	smart-1459aa8b-53dd-4e45-9c2f-74a274dcd23b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=689626705 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.689626705
Directory	/workspace/81.edn_genbits/latest

Test location	/workspace/coverage/default/82.edn_err.623459085
Short name	T25
Test name
Test status
Simulation time	19356063 ps
CPU time	1.02 seconds
Started	Jan 10 01:20:21 PM PST 24
Finished	Jan 10 01:20:30 PM PST 24
Peak memory	215616 kb
Host	smart-30520d62-efd9-41a0-a139-2111c981e50e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=623459085 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.623459085
Directory	/workspace/82.edn_err/latest

Test location	/workspace/coverage/default/82.edn_genbits.2960659716
Short name	T682
Test name
Test status
Simulation time	28737608 ps
CPU time	0.99 seconds
Started	Jan 10 01:20:47 PM PST 24
Finished	Jan 10 01:20:53 PM PST 24
Peak memory	206132 kb
Host	smart-d5cc36af-3c12-40c5-8d82-19d6c2a6d938
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2960659716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.2960659716
Directory	/workspace/82.edn_genbits/latest

Test location	/workspace/coverage/default/83.edn_err.3328338881
Short name	T971
Test name
Test status
Simulation time	30946830 ps
CPU time	0.99 seconds
Started	Jan 10 01:20:32 PM PST 24
Finished	Jan 10 01:20:41 PM PST 24
Peak memory	221612 kb
Host	smart-3a1ef003-738f-46b8-b5c6-160a74f496ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3328338881 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.3328338881
Directory	/workspace/83.edn_err/latest

Test location	/workspace/coverage/default/83.edn_genbits.3526282353
Short name	T572
Test name
Test status
Simulation time	16796197 ps
CPU time	1.17 seconds
Started	Jan 10 01:20:23 PM PST 24
Finished	Jan 10 01:20:34 PM PST 24
Peak memory	205876 kb
Host	smart-7819087d-bcf4-4863-b8d8-f4b9bcb0ae78
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3526282353 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.3526282353
Directory	/workspace/83.edn_genbits/latest

Test location	/workspace/coverage/default/84.edn_err.2919629924
Short name	T684
Test name
Test status
Simulation time	26643038 ps
CPU time	0.95 seconds
Started	Jan 10 01:20:48 PM PST 24
Finished	Jan 10 01:20:54 PM PST 24
Peak memory	216040 kb
Host	smart-7ac82c15-8ddb-4a4c-a429-4402777490de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2919629924 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.2919629924
Directory	/workspace/84.edn_err/latest

Test location	/workspace/coverage/default/84.edn_genbits.4033870469
Short name	T829
Test name
Test status
Simulation time	119990592 ps
CPU time	0.89 seconds
Started	Jan 10 01:20:47 PM PST 24
Finished	Jan 10 01:20:53 PM PST 24
Peak memory	205532 kb
Host	smart-fea57f54-91c6-4bcf-b8e3-d7b9c16f1223
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4033870469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.4033870469
Directory	/workspace/84.edn_genbits/latest

Test location	/workspace/coverage/default/85.edn_err.983560640
Short name	T146
Test name
Test status
Simulation time	34739133 ps
CPU time	1.07 seconds
Started	Jan 10 01:20:53 PM PST 24
Finished	Jan 10 01:20:59 PM PST 24
Peak memory	215864 kb
Host	smart-08d1806c-9371-4735-b07f-e1392470b279
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=983560640 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.983560640
Directory	/workspace/85.edn_err/latest

Test location	/workspace/coverage/default/85.edn_genbits.2794197373
Short name	T272
Test name
Test status
Simulation time	125201231 ps
CPU time	1.88 seconds
Started	Jan 10 01:20:34 PM PST 24
Finished	Jan 10 01:20:45 PM PST 24
Peak memory	214332 kb
Host	smart-a127650b-8f36-422d-96da-981fd158b77a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2794197373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.2794197373
Directory	/workspace/85.edn_genbits/latest

Test location	/workspace/coverage/default/86.edn_err.913544483
Short name	T156
Test name
Test status
Simulation time	24783551 ps
CPU time	0.92 seconds
Started	Jan 10 01:20:37 PM PST 24
Finished	Jan 10 01:20:48 PM PST 24
Peak memory	216140 kb
Host	smart-7ae2deda-b691-4b9a-b53d-aa6b38adb1d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=913544483 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.913544483
Directory	/workspace/86.edn_err/latest

Test location	/workspace/coverage/default/86.edn_genbits.2490961128
Short name	T941
Test name
Test status
Simulation time	63711221 ps
CPU time	1 seconds
Started	Jan 10 01:20:34 PM PST 24
Finished	Jan 10 01:20:44 PM PST 24
Peak memory	205804 kb
Host	smart-bd69b6e7-134d-4dca-b618-b21cc08658f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2490961128 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.2490961128
Directory	/workspace/86.edn_genbits/latest

Test location	/workspace/coverage/default/87.edn_err.1914979769
Short name	T818
Test name
Test status
Simulation time	28359532 ps
CPU time	0.94 seconds
Started	Jan 10 01:20:49 PM PST 24
Finished	Jan 10 01:20:55 PM PST 24
Peak memory	215908 kb
Host	smart-2f1e7950-b556-49c9-be37-2ffecce8d409
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1914979769 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.1914979769
Directory	/workspace/87.edn_err/latest

Test location	/workspace/coverage/default/87.edn_genbits.2349608315
Short name	T270
Test name
Test status
Simulation time	18663544 ps
CPU time	0.96 seconds
Started	Jan 10 01:20:51 PM PST 24
Finished	Jan 10 01:20:58 PM PST 24
Peak memory	205312 kb
Host	smart-7798b2aa-5ebf-43c8-a98c-12db9633f084
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2349608315 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.2349608315
Directory	/workspace/87.edn_genbits/latest

Test location	/workspace/coverage/default/88.edn_err.1904814583
Short name	T238
Test name
Test status
Simulation time	44939057 ps
CPU time	1.08 seconds
Started	Jan 10 01:21:03 PM PST 24
Finished	Jan 10 01:21:08 PM PST 24
Peak memory	217352 kb
Host	smart-84710140-2998-46b0-83b1-10e0cdc0863c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1904814583 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.1904814583
Directory	/workspace/88.edn_err/latest

Test location	/workspace/coverage/default/88.edn_genbits.4058849857
Short name	T551
Test name
Test status
Simulation time	24835253 ps
CPU time	0.97 seconds
Started	Jan 10 01:20:52 PM PST 24
Finished	Jan 10 01:20:58 PM PST 24
Peak memory	205572 kb
Host	smart-68af01e2-d429-4083-b634-ddc8c9dcda10
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4058849857 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.4058849857
Directory	/workspace/88.edn_genbits/latest

Test location	/workspace/coverage/default/89.edn_err.3393327883
Short name	T232
Test name
Test status
Simulation time	32018271 ps
CPU time	1.07 seconds
Started	Jan 10 01:20:56 PM PST 24
Finished	Jan 10 01:21:01 PM PST 24
Peak memory	216156 kb
Host	smart-b3e56424-881d-4849-b4aa-15fa0ab1fab4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3393327883 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.3393327883
Directory	/workspace/89.edn_err/latest

Test location	/workspace/coverage/default/89.edn_genbits.3893589318
Short name	T778
Test name
Test status
Simulation time	98009197 ps
CPU time	1.1 seconds
Started	Jan 10 01:21:02 PM PST 24
Finished	Jan 10 01:21:06 PM PST 24
Peak memory	205396 kb
Host	smart-87e0b3ba-9ea8-4510-b0a1-14da88615a24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3893589318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.3893589318
Directory	/workspace/89.edn_genbits/latest

Test location	/workspace/coverage/default/9.edn_alert.1588957255
Short name	T890
Test name
Test status
Simulation time	50904284 ps
CPU time	0.9 seconds
Started	Jan 10 01:19:26 PM PST 24
Finished	Jan 10 01:19:38 PM PST 24
Peak memory	206152 kb
Host	smart-5be8eb8e-d0cb-4ad1-acd9-dfb1dbbdfbb0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1588957255 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.1588957255
Directory	/workspace/9.edn_alert/latest

Test location	/workspace/coverage/default/9.edn_alert_test.1834875200
Short name	T752
Test name
Test status
Simulation time	49606175 ps
CPU time	0.86 seconds
Started	Jan 10 01:19:26 PM PST 24
Finished	Jan 10 01:19:39 PM PST 24
Peak memory	204620 kb
Host	smart-be89402a-04f3-4add-af4f-12af937ed4ec
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834875200 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.1834875200
Directory	/workspace/9.edn_alert_test/latest

Test location	/workspace/coverage/default/9.edn_disable.304900133
Short name	T125
Test name
Test status
Simulation time	21674673 ps
CPU time	0.83 seconds
Started	Jan 10 01:19:24 PM PST 24
Finished	Jan 10 01:19:34 PM PST 24
Peak memory	214512 kb
Host	smart-19b2fd65-56dc-4fe4-9107-da5b8d26cf16
User	root
Command	/workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304900133 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.304900133
Directory	/workspace/9.edn_disable/latest

Test location	/workspace/coverage/default/9.edn_disable_auto_req_mode.2665564451
Short name	T243
Test name
Test status
Simulation time	28904610 ps
CPU time	1.05 seconds
Started	Jan 10 01:19:27 PM PST 24
Finished	Jan 10 01:19:41 PM PST 24
Peak memory	214536 kb
Host	smart-f51589cd-1242-4061-b99b-0b3f5f4d5728
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665564451 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di sable_auto_req_mode.2665564451
Directory	/workspace/9.edn_disable_auto_req_mode/latest

Test location	/workspace/coverage/default/9.edn_err.1214771964
Short name	T233
Test name
Test status
Simulation time	51331783 ps
CPU time	0.82 seconds
Started	Jan 10 01:19:24 PM PST 24
Finished	Jan 10 01:19:35 PM PST 24
Peak memory	214928 kb
Host	smart-1a5bf377-8486-4087-84d0-a68abd4cfdf1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1214771964 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.1214771964
Directory	/workspace/9.edn_err/latest

Test location	/workspace/coverage/default/9.edn_genbits.2908433491
Short name	T288
Test name
Test status
Simulation time	25448718 ps
CPU time	1.05 seconds
Started	Jan 10 01:19:23 PM PST 24
Finished	Jan 10 01:19:32 PM PST 24
Peak memory	214276 kb
Host	smart-33e58990-1890-4ff2-9e67-bc6c1f3d3bc9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2908433491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.2908433491
Directory	/workspace/9.edn_genbits/latest

Test location	/workspace/coverage/default/9.edn_intr.1543242515
Short name	T93
Test name
Test status
Simulation time	19787620 ps
CPU time	1.02 seconds
Started	Jan 10 01:19:26 PM PST 24
Finished	Jan 10 01:19:38 PM PST 24
Peak memory	214636 kb
Host	smart-ac3f217e-9668-4ddd-86b6-bcfca2d1c990
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1543242515 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.1543242515
Directory	/workspace/9.edn_intr/latest

Test location	/workspace/coverage/default/9.edn_regwen.3102206499
Short name	T324
Test name
Test status
Simulation time	13275488 ps
CPU time	0.89 seconds
Started	Jan 10 01:19:24 PM PST 24
Finished	Jan 10 01:19:35 PM PST 24
Peak memory	204916 kb
Host	smart-48a7cb05-04f6-4c9c-82da-fa3a3a270b41
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3102206499 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.3102206499
Directory	/workspace/9.edn_regwen/latest

Test location	/workspace/coverage/default/9.edn_smoke.3394992868
Short name	T515
Test name
Test status
Simulation time	55635723 ps
CPU time	0.87 seconds
Started	Jan 10 01:19:25 PM PST 24
Finished	Jan 10 01:19:36 PM PST 24
Peak memory	204792 kb
Host	smart-ecb4ef7a-1d77-4317-a13a-54da66803c22
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3394992868 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.3394992868
Directory	/workspace/9.edn_smoke/latest

Test location	/workspace/coverage/default/9.edn_stress_all.1711969435
Short name	T816
Test name
Test status
Simulation time	216150092 ps
CPU time	3.24 seconds
Started	Jan 10 01:19:23 PM PST 24
Finished	Jan 10 01:19:35 PM PST 24
Peak memory	205992 kb
Host	smart-45339338-f481-4928-a6e0-8c6119d87aae
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711969435 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1711969435
Directory	/workspace/9.edn_stress_all/latest

Test location	/workspace/coverage/default/9.edn_stress_all_with_rand_reset.3007392941
Short name	T664
Test name
Test status
Simulation time	21426621091 ps
CPU time	466.44 seconds
Started	Jan 10 01:19:22 PM PST 24
Finished	Jan 10 01:27:17 PM PST 24
Peak memory	215336 kb
Host	smart-240e3c28-51a7-4ef6-9b43-cc22b837a51d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007392941 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.3007392941
Directory	/workspace/9.edn_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/90.edn_err.3313170124
Short name	T605
Test name
Test status
Simulation time	40723784 ps
CPU time	1.14 seconds
Started	Jan 10 01:21:08 PM PST 24
Finished	Jan 10 01:21:13 PM PST 24
Peak memory	216260 kb
Host	smart-a47fc2e7-5b9e-4547-b285-6c63217f4953
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3313170124 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.3313170124
Directory	/workspace/90.edn_err/latest

Test location	/workspace/coverage/default/90.edn_genbits.1865790723
Short name	T279
Test name
Test status
Simulation time	64365587 ps
CPU time	0.94 seconds
Started	Jan 10 01:21:03 PM PST 24
Finished	Jan 10 01:21:07 PM PST 24
Peak memory	205232 kb
Host	smart-cd960e68-32b1-4820-a2a0-b81315283f55
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1865790723 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.1865790723
Directory	/workspace/90.edn_genbits/latest

Test location	/workspace/coverage/default/91.edn_err.4041738388
Short name	T235
Test name
Test status
Simulation time	68446525 ps
CPU time	0.99 seconds
Started	Jan 10 01:20:54 PM PST 24
Finished	Jan 10 01:21:00 PM PST 24
Peak memory	215024 kb
Host	smart-a2d4a079-1abd-4082-9916-6a808ad4e537
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4041738388 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.4041738388
Directory	/workspace/91.edn_err/latest

Test location	/workspace/coverage/default/91.edn_genbits.175171853
Short name	T557
Test name
Test status
Simulation time	35801814 ps
CPU time	1 seconds
Started	Jan 10 01:21:28 PM PST 24
Finished	Jan 10 01:21:41 PM PST 24
Peak memory	205624 kb
Host	smart-50465ec0-0e34-4ae5-b137-2dbd8ea51d4c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=175171853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.175171853
Directory	/workspace/91.edn_genbits/latest

Test location	/workspace/coverage/default/92.edn_err.3190048612
Short name	T60
Test name
Test status
Simulation time	28526014 ps
CPU time	1.26 seconds
Started	Jan 10 01:21:30 PM PST 24
Finished	Jan 10 01:21:47 PM PST 24
Peak memory	214664 kb
Host	smart-d015bcdc-559b-48a2-a2f8-7d0da22e5c83
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3190048612 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.3190048612
Directory	/workspace/92.edn_err/latest

Test location	/workspace/coverage/default/92.edn_genbits.1835033754
Short name	T540
Test name
Test status
Simulation time	75816052 ps
CPU time	1.07 seconds
Started	Jan 10 01:21:05 PM PST 24
Finished	Jan 10 01:21:10 PM PST 24
Peak memory	205596 kb
Host	smart-bf0b41d8-28bb-4406-b9cc-961833da4215
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1835033754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.1835033754
Directory	/workspace/92.edn_genbits/latest

Test location	/workspace/coverage/default/93.edn_err.1681198745
Short name	T844
Test name
Test status
Simulation time	19314196 ps
CPU time	1.09 seconds
Started	Jan 10 01:21:06 PM PST 24
Finished	Jan 10 01:21:11 PM PST 24
Peak memory	215764 kb
Host	smart-f952c4a1-b17c-434a-9a43-ce8ac2ab45d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1681198745 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.1681198745
Directory	/workspace/93.edn_err/latest

Test location	/workspace/coverage/default/93.edn_genbits.276768616
Short name	T74
Test name
Test status
Simulation time	32078499 ps
CPU time	1.14 seconds
Started	Jan 10 01:21:07 PM PST 24
Finished	Jan 10 01:21:13 PM PST 24
Peak memory	205544 kb
Host	smart-e4d4d9ed-99d1-469f-8cdc-a7b81546b35f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=276768616 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.276768616
Directory	/workspace/93.edn_genbits/latest

Test location	/workspace/coverage/default/94.edn_err.376450596
Short name	T787
Test name
Test status
Simulation time	25769427 ps
CPU time	1.15 seconds
Started	Jan 10 01:21:35 PM PST 24
Finished	Jan 10 01:21:55 PM PST 24
Peak memory	214884 kb
Host	smart-530861d6-f296-462b-9919-8d31d290970a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=376450596 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.376450596
Directory	/workspace/94.edn_err/latest

Test location	/workspace/coverage/default/94.edn_genbits.2342084016
Short name	T454
Test name
Test status
Simulation time	24462388 ps
CPU time	0.91 seconds
Started	Jan 10 01:21:29 PM PST 24
Finished	Jan 10 01:21:43 PM PST 24
Peak memory	204996 kb
Host	smart-4cb2d801-d945-4b0b-877d-71e3d41fcd11
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2342084016 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.2342084016
Directory	/workspace/94.edn_genbits/latest

Test location	/workspace/coverage/default/95.edn_err.789465470
Short name	T116
Test name
Test status
Simulation time	21451832 ps
CPU time	1.4 seconds
Started	Jan 10 01:21:31 PM PST 24
Finished	Jan 10 01:21:49 PM PST 24
Peak memory	214880 kb
Host	smart-f929bd81-bfef-41e4-999d-f02340e6af12
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=789465470 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.789465470
Directory	/workspace/95.edn_err/latest

Test location	/workspace/coverage/default/96.edn_err.1065937928
Short name	T629
Test name
Test status
Simulation time	100457445 ps
CPU time	0.94 seconds
Started	Jan 10 01:20:34 PM PST 24
Finished	Jan 10 01:20:44 PM PST 24
Peak memory	214916 kb
Host	smart-bd147ad6-b9d4-4a17-8dee-fcbf034b7574
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1065937928 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.1065937928
Directory	/workspace/96.edn_err/latest

Test location	/workspace/coverage/default/96.edn_genbits.3200378527
Short name	T718
Test name
Test status
Simulation time	47927645 ps
CPU time	0.96 seconds
Started	Jan 10 01:20:49 PM PST 24
Finished	Jan 10 01:20:55 PM PST 24
Peak memory	205396 kb
Host	smart-0876111f-55e6-454c-b34b-f9ffc1d0abd7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3200378527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.3200378527
Directory	/workspace/96.edn_genbits/latest

Test location	/workspace/coverage/default/97.edn_err.2479450631
Short name	T788
Test name
Test status
Simulation time	49549450 ps
CPU time	1.03 seconds
Started	Jan 10 01:20:47 PM PST 24
Finished	Jan 10 01:20:53 PM PST 24
Peak memory	217208 kb
Host	smart-9a940d45-0671-4e34-b778-ae39a1a0be76
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2479450631 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.2479450631
Directory	/workspace/97.edn_err/latest

Test location	/workspace/coverage/default/97.edn_genbits.530334116
Short name	T53
Test name
Test status
Simulation time	19717903 ps
CPU time	0.87 seconds
Started	Jan 10 01:20:53 PM PST 24
Finished	Jan 10 01:20:59 PM PST 24
Peak memory	205272 kb
Host	smart-2fe10785-20e2-42e1-8825-6392dca54951
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=530334116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.530334116
Directory	/workspace/97.edn_genbits/latest

Test location	/workspace/coverage/default/98.edn_err.1298091082
Short name	T164
Test name
Test status
Simulation time	27959608 ps
CPU time	0.9 seconds
Started	Jan 10 01:20:52 PM PST 24
Finished	Jan 10 01:20:58 PM PST 24
Peak memory	221468 kb
Host	smart-d3c35bb3-7ca6-45c7-abcc-6d39c9a2067c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1298091082 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.1298091082
Directory	/workspace/98.edn_err/latest

Test location	/workspace/coverage/default/98.edn_genbits.555877304
Short name	T666
Test name
Test status
Simulation time	20074661 ps
CPU time	1 seconds
Started	Jan 10 01:20:34 PM PST 24
Finished	Jan 10 01:20:44 PM PST 24
Peak memory	205532 kb
Host	smart-aff37027-66a0-479d-a6f0-7ec8861b51e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=555877304 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.555877304
Directory	/workspace/98.edn_genbits/latest

Test location	/workspace/coverage/default/99.edn_err.4278293746
Short name	T791
Test name
Test status
Simulation time	35334184 ps
CPU time	0.89 seconds
Started	Jan 10 01:20:49 PM PST 24
Finished	Jan 10 01:20:55 PM PST 24
Peak memory	214780 kb
Host	smart-a0e6171e-8eac-41c9-bd82-f60f0e18f099
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4278293746 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.4278293746
Directory	/workspace/99.edn_err/latest

Test location	/workspace/coverage/default/99.edn_genbits.3966158071
Short name	T810
Test name
Test status
Simulation time	16111987 ps
CPU time	0.94 seconds
Started	Jan 10 01:20:48 PM PST 24
Finished	Jan 10 01:20:54 PM PST 24
Peak memory	205492 kb
Host	smart-54f37e64-0d37-40c1-83f8-69ce409ea0f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3966158071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.3966158071
Directory	/workspace/99.edn_genbits/latest